1 #ifndef __BNX2X_INIT_VALUES_H__
2 #define __BNX2X_INIT_VALUES_H__
4 /* This array contains the list of operations needed to initialize the chip.
6 * For each block in the chip there are three init stages:
7 * common - HW used by both ports,
8 * port1 and port2 - initialization for a specific Ethernet port.
9 * When a port is opened or closed, the management CPU tells the driver
10 * whether to init/disable common HW in addition to the port HW.
11 * This way the first port going up will first initializes the common HW,
12 * and the last port going down also resets the common HW
14 * For each init stage/block there is a list of actions needed in a format:
15 * {operation, register, data}
17 * OP_WR - write a value to the chip.
18 * OP_RD - read a register (usually a clear on read register).
19 * OP_SW - string write, write a section of consecutive addresses to the chip.
20 * OP_SI - copy a string using indirect writes.
21 * OP_ZR - clear a range of memory.
22 * OP_ZP - unzip and copy using DMAE.
23 * OP_WB - string copy using DMAE.
25 * The #defines mark the stages.
29 static const struct raw_op init_ops[] = {
30 #define PRS_COMMON_START 0
31 {OP_WR, PRS_REG_INC_VALUE, 0xf},
32 {OP_WR, PRS_REG_EVENT_ID_1, 0x45},
33 {OP_WR, PRS_REG_EVENT_ID_2, 0x84},
34 {OP_WR, PRS_REG_EVENT_ID_3, 0x6},
35 {OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
36 {OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
37 {OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
38 {OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
39 {OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
40 {OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
41 {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
42 {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
43 {OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
44 {OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
45 {OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
46 {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
47 {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
48 {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
49 {OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
50 {OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x4},
51 {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
52 {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
53 {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
54 {OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
55 {OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x4},
56 {OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
57 {OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
58 {OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
59 {OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
60 {OP_WR_E1H, PRS_REG_FCOE_TYPE, 0x8906},
61 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
62 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
63 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
64 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
65 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
66 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
67 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
68 {OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
69 {OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
70 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
71 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
72 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
73 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
74 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x0},
75 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
76 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
77 {OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
78 #define PRS_COMMON_END 47
79 #define SRCH_COMMON_START 47
80 {OP_WR_E1H, SRC_REG_E1HMF_ENABLE, 0x1},
81 #define SRCH_COMMON_END 48
82 #define TSDM_COMMON_START 48
83 {OP_WR_E1, TSDM_REG_CFC_RSP_START_ADDR, 0x411},
84 {OP_WR_E1H, TSDM_REG_CFC_RSP_START_ADDR, 0x211},
85 {OP_WR_E1, TSDM_REG_CMP_COUNTER_START_ADDR, 0x400},
86 {OP_WR_E1H, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
87 {OP_WR_E1, TSDM_REG_Q_COUNTER_START_ADDR, 0x404},
88 {OP_WR_E1H, TSDM_REG_Q_COUNTER_START_ADDR, 0x204},
89 {OP_WR_E1, TSDM_REG_PCK_END_MSG_START_ADDR, 0x419},
90 {OP_WR_E1H, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219},
91 {OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
92 {OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
93 {OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
94 {OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
95 {OP_ZR, TSDM_REG_AGG_INT_EVENT_0, 0x2},
96 {OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
97 {OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
98 {OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x7c},
99 {OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
100 {OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
101 {OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
102 {OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
103 {OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
104 {OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
105 {OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
106 {OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
107 {OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
108 {OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
109 {OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
110 {OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
111 {OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
112 {OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
113 {OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
114 {OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
115 {OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
116 {OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
117 {OP_WR_E1, TSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
118 {OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
119 {OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
120 {OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
121 #define TSDM_COMMON_END 86
122 #define TCM_COMMON_START 86
123 {OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
124 {OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
125 {OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
126 {OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
127 {OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
128 {OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
129 {OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
130 {OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
131 {OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
132 {OP_WR, TCM_REG_PRS_WEIGHT, 0x4},
133 {OP_WR, TCM_REG_PBF_WEIGHT, 0x5},
134 {OP_WR, TCM_REG_CP_WEIGHT, 0x0},
135 {OP_WR, TCM_REG_TSDM_WEIGHT, 0x4},
136 {OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
137 {OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
138 {OP_WR, TCM_REG_GR_LD0_PR, 0x1},
139 {OP_WR, TCM_REG_GR_LD1_PR, 0x2},
140 {OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
141 {OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
142 {OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
143 {OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
144 {OP_WR, TCM_REG_XX_INIT_CRD, 0x13},
145 {OP_WR, TCM_REG_XX_MSG_NUM, 0x20},
146 {OP_ZR, TCM_REG_XX_TABLE, 0xa},
147 {OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000},
148 {OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7},
149 {OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7},
150 {OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8},
151 {OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
152 {OP_ZR, TCM_REG_N_SM_CTX_LD_4, 0x4},
153 {OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
154 {OP_WR_E1, TCM_REG_PHYS_QNUM0_0, 0xd},
155 {OP_WR_E1, TCM_REG_PHYS_QNUM0_1, 0x2d},
156 {OP_WR_E1, TCM_REG_PHYS_QNUM1_0, 0x7},
157 {OP_WR_E1, TCM_REG_PHYS_QNUM1_1, 0x27},
158 {OP_WR_E1, TCM_REG_PHYS_QNUM2_0, 0x7},
159 {OP_WR_E1, TCM_REG_PHYS_QNUM2_1, 0x27},
160 {OP_WR_E1, TCM_REG_PHYS_QNUM3_0, 0x7},
161 {OP_WR_E1, TCM_REG_PHYS_QNUM3_1, 0x27},
162 {OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
163 {OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
164 {OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
165 {OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1},
166 {OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1},
167 {OP_WR, TCM_REG_TSDM_IFEN, 0x1},
168 {OP_WR, TCM_REG_TM_TCM_IFEN, 0x1},
169 {OP_WR, TCM_REG_PRS_IFEN, 0x1},
170 {OP_WR, TCM_REG_PBF_IFEN, 0x1},
171 {OP_WR, TCM_REG_USEM_IFEN, 0x1},
172 {OP_WR, TCM_REG_CSEM_IFEN, 0x1},
173 {OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1},
174 {OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1},
175 {OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
176 {OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
177 {OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
178 #define TCM_COMMON_END 141
179 #define TCM_FUNC0_START 141
180 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0xd},
181 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x7},
182 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x7},
183 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x7},
184 #define TCM_FUNC0_END 145
185 #define TCM_FUNC1_START 145
186 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x2d},
187 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x27},
188 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x27},
189 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x27},
190 #define TCM_FUNC1_END 149
191 #define TCM_FUNC2_START 149
192 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x1d},
193 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x17},
194 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x17},
195 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x17},
196 #define TCM_FUNC2_END 153
197 #define TCM_FUNC3_START 153
198 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x3d},
199 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x37},
200 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x37},
201 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x37},
202 #define TCM_FUNC3_END 157
203 #define TCM_FUNC4_START 157
204 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x4d},
205 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x47},
206 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x47},
207 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x47},
208 #define TCM_FUNC4_END 161
209 #define TCM_FUNC5_START 161
210 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x6d},
211 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x67},
212 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x67},
213 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x67},
214 #define TCM_FUNC5_END 165
215 #define TCM_FUNC6_START 165
216 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_0, 0x5d},
217 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_0, 0x57},
218 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_0, 0x57},
219 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_0, 0x57},
220 #define TCM_FUNC6_END 169
221 #define TCM_FUNC7_START 169
222 {OP_WR_E1H, TCM_REG_PHYS_QNUM0_1, 0x7d},
223 {OP_WR_E1H, TCM_REG_PHYS_QNUM1_1, 0x77},
224 {OP_WR_E1H, TCM_REG_PHYS_QNUM2_1, 0x77},
225 {OP_WR_E1H, TCM_REG_PHYS_QNUM3_1, 0x77},
226 #define TCM_FUNC7_END 173
227 #define BRB1_COMMON_START 173
228 {OP_SW, BRB1_REG_LL_RAM, 0x2000020},
229 {OP_WR, BRB1_REG_SOFT_RESET, 0x1},
230 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
231 {OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
232 {OP_WR, BRB1_REG_SOFT_RESET, 0x0},
233 #define BRB1_COMMON_END 178
234 #define BRB1_PORT0_START 178
235 {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_0, 0xb8},
236 {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_0, 0x114},
237 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
238 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
239 #define BRB1_PORT0_END 182
240 #define BRB1_PORT1_START 182
241 {OP_WR_E1, BRB1_REG_PAUSE_LOW_THRESHOLD_1, 0xb8},
242 {OP_WR_E1, BRB1_REG_PAUSE_HIGH_THRESHOLD_1, 0x114},
243 {OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
244 {OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
245 #define BRB1_PORT1_END 186
246 #define TSEM_COMMON_START 186
247 {OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
248 {OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
249 {OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
250 {OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0},
251 {OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0},
252 {OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0},
253 {OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1},
254 {OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2},
255 {OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3},
256 {OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0},
257 {OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4},
258 {OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1},
259 {OP_WR, TSEM_REG_TS_0_AS, 0x0},
260 {OP_WR, TSEM_REG_TS_1_AS, 0x1},
261 {OP_WR, TSEM_REG_TS_2_AS, 0x4},
262 {OP_WR, TSEM_REG_TS_3_AS, 0x0},
263 {OP_WR, TSEM_REG_TS_4_AS, 0x1},
264 {OP_WR, TSEM_REG_TS_5_AS, 0x3},
265 {OP_WR, TSEM_REG_TS_6_AS, 0x0},
266 {OP_WR, TSEM_REG_TS_7_AS, 0x1},
267 {OP_WR, TSEM_REG_TS_8_AS, 0x4},
268 {OP_WR, TSEM_REG_TS_9_AS, 0x0},
269 {OP_WR, TSEM_REG_TS_10_AS, 0x1},
270 {OP_WR, TSEM_REG_TS_11_AS, 0x3},
271 {OP_WR, TSEM_REG_TS_12_AS, 0x0},
272 {OP_WR, TSEM_REG_TS_13_AS, 0x1},
273 {OP_WR, TSEM_REG_TS_14_AS, 0x4},
274 {OP_WR, TSEM_REG_TS_15_AS, 0x0},
275 {OP_WR, TSEM_REG_TS_16_AS, 0x4},
276 {OP_WR, TSEM_REG_TS_17_AS, 0x3},
277 {OP_ZR, TSEM_REG_TS_18_AS, 0x2},
278 {OP_WR, TSEM_REG_ENABLE_IN, 0x3fff},
279 {OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff},
280 {OP_WR, TSEM_REG_FIC0_DISABLE, 0x0},
281 {OP_WR, TSEM_REG_FIC1_DISABLE, 0x0},
282 {OP_WR, TSEM_REG_PAS_DISABLE, 0x0},
283 {OP_WR, TSEM_REG_THREADS_LIST, 0xff},
284 {OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400},
285 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
286 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34},
287 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
288 {OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
289 {OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
290 {OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
291 {OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
292 {OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
293 {OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
294 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2000, 0xb2},
295 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x1},
296 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x23c8, 0xc1},
297 {OP_WR_EMUL_E1H, TSEM_REG_FAST_MEMORY + 0x11480, 0x0},
298 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x23c8 + 0x304, 0x10223},
299 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x1000, 0x2b3},
300 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
301 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x1000 + 0xacc, 0x10223},
302 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1000, 0x2},
303 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8},
304 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1c18, 0x4},
305 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xa000, 0x2},
306 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
307 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x1ad0, 0x0},
308 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
309 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3b28, 0x6},
310 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x810, 0x4},
311 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
312 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x40224},
313 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5008, 0x4},
314 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x4cb0, 0x80228},
315 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5018, 0x4},
316 {OP_ZP_E1, TSEM_REG_INT_TABLE, 0x940000},
317 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5028, 0x4},
318 {OP_WR_64_E1, TSEM_REG_INT_TABLE + 0x360, 0x140230},
319 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5038, 0x4},
320 {OP_ZP_E1, TSEM_REG_PRAM, 0x6ab70000},
321 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5048, 0x4},
322 {OP_WR_64_E1, TSEM_REG_PRAM + 0x117f0, 0x5d020232},
323 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5058, 0x4},
324 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5068, 0x4},
325 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5078, 0x2},
326 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
327 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
328 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x6140, 0x200224},
329 {OP_ZP_E1H, TSEM_REG_INT_TABLE, 0x960000},
330 {OP_WR_64_E1H, TSEM_REG_INT_TABLE + 0x360, 0x140244},
331 {OP_ZP_E1H, TSEM_REG_PRAM, 0x6d080000},
332 {OP_WR_64_E1H, TSEM_REG_PRAM + 0x11c70, 0x5c720246},
333 #define TSEM_COMMON_END 272
334 #define TSEM_PORT0_START 272
335 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x22c8, 0x20},
336 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x2000, 0x16c},
337 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x4000, 0xfc},
338 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb000, 0x28},
339 {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b60, 0x0},
340 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb140, 0xc},
341 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1400, 0xa},
342 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32c0, 0x12},
343 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1450, 0x6},
344 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3350, 0xfa},
345 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1500, 0xe},
346 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8108, 0x2},
347 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1570, 0x12},
348 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x9c0, 0xbe},
349 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x800, 0x2},
350 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x820, 0xe},
351 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb0, 0x20234},
352 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2908, 0x2},
353 #define TSEM_PORT0_END 290
354 #define TSEM_PORT1_START 290
355 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2348, 0x20},
356 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x25b0, 0x16c},
357 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x43f0, 0xfc},
358 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28},
359 {OP_WR_E1, TSEM_REG_FAST_MEMORY + 0x4b64, 0x0},
360 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0xb170, 0xc},
361 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1428, 0xa},
362 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3308, 0x12},
363 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1468, 0x6},
364 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3738, 0xfa},
365 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x1538, 0xe},
366 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x8110, 0x2},
367 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x15b8, 0x12},
368 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0xcb8, 0xbe},
369 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x808, 0x2},
370 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x858, 0xe},
371 {OP_SW_E1, TSEM_REG_FAST_MEMORY + 0x1fb8, 0x20236},
372 {OP_ZR_E1, TSEM_REG_FAST_MEMORY + 0x2910, 0x2},
373 #define TSEM_PORT1_END 308
374 #define TSEM_FUNC0_START 308
375 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b60, 0x0},
376 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3000, 0xe},
377 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31c0, 0x8},
378 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
379 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5080, 0x12},
380 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
381 #define TSEM_FUNC0_END 314
382 #define TSEM_FUNC1_START 314
383 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b64, 0x0},
384 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3038, 0xe},
385 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x31e0, 0x8},
386 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5010, 0x2},
387 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12},
388 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
389 #define TSEM_FUNC1_END 320
390 #define TSEM_FUNC2_START 320
391 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b68, 0x0},
392 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3070, 0xe},
393 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3200, 0x8},
394 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5020, 0x2},
395 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5110, 0x12},
396 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4010, 0x20248},
397 #define TSEM_FUNC2_END 326
398 #define TSEM_FUNC3_START 326
399 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b6c, 0x0},
400 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30a8, 0xe},
401 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3220, 0x8},
402 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5030, 0x2},
403 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5158, 0x12},
404 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4018, 0x2024a},
405 #define TSEM_FUNC3_END 332
406 #define TSEM_FUNC4_START 332
407 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b70, 0x0},
408 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x30e0, 0xe},
409 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3240, 0x8},
410 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5040, 0x2},
411 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12},
412 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4020, 0x2024c},
413 #define TSEM_FUNC4_END 338
414 #define TSEM_FUNC5_START 338
415 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b74, 0x0},
416 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3118, 0xe},
417 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3260, 0x8},
418 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5050, 0x2},
419 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12},
420 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4028, 0x2024e},
421 #define TSEM_FUNC5_END 344
422 #define TSEM_FUNC6_START 344
423 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b78, 0x0},
424 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3150, 0xe},
425 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3280, 0x8},
426 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5060, 0x2},
427 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5230, 0x12},
428 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4030, 0x20250},
429 #define TSEM_FUNC6_END 350
430 #define TSEM_FUNC7_START 350
431 {OP_WR_E1H, TSEM_REG_FAST_MEMORY + 0x2b7c, 0x0},
432 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x3188, 0xe},
433 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8},
434 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5070, 0x2},
435 {OP_ZR_E1H, TSEM_REG_FAST_MEMORY + 0x5278, 0x12},
436 {OP_SW_E1H, TSEM_REG_FAST_MEMORY + 0x4038, 0x20252},
437 #define TSEM_FUNC7_END 356
438 #define MISC_COMMON_START 356
439 {OP_WR_E1, MISC_REG_GRC_TIMEOUT_EN, 0x1},
440 {OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
441 {OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
442 {OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
443 {OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
444 {OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
445 {OP_WR_E1, MISC_REG_SPIO, 0xff000000},
446 #define MISC_COMMON_END 363
447 #define MISC_FUNC0_START 363
448 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
449 #define MISC_FUNC0_END 364
450 #define MISC_FUNC1_START 364
451 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
452 #define MISC_FUNC1_END 365
453 #define MISC_FUNC2_START 365
454 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
455 #define MISC_FUNC2_END 366
456 #define MISC_FUNC3_START 366
457 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
458 #define MISC_FUNC3_END 367
459 #define MISC_FUNC4_START 367
460 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
461 #define MISC_FUNC4_END 368
462 #define MISC_FUNC5_START 368
463 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
464 #define MISC_FUNC5_END 369
465 #define MISC_FUNC6_START 369
466 {OP_WR_E1H, MISC_REG_NIG_WOL_P0, 0x0},
467 #define MISC_FUNC6_END 370
468 #define MISC_FUNC7_START 370
469 {OP_WR_E1H, MISC_REG_NIG_WOL_P1, 0x0},
470 #define MISC_FUNC7_END 371
471 #define NIG_COMMON_START 371
472 {OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
473 {OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
474 {OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
475 {OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
476 {OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
477 #define NIG_COMMON_END 376
478 #define NIG_PORT0_START 376
479 {OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
480 {OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
481 {OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
482 {OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
483 {OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
484 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
485 {OP_WR_E1H, NIG_REG_LLH0_CLS_TYPE, 0x1},
486 {OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
487 {OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
488 {OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
489 {OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
490 {OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
491 #define NIG_PORT0_END 388
492 #define NIG_PORT1_START 388
493 {OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
494 {OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
495 {OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
496 {OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
497 {OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
498 {OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
499 {OP_WR_E1H, NIG_REG_LLH1_CLS_TYPE, 0x1},
500 {OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
501 {OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
502 {OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
503 {OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
504 {OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
505 #define NIG_PORT1_END 400
506 #define UPB_COMMON_START 400
507 {OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
508 #define UPB_COMMON_END 401
509 #define CSDM_COMMON_START 401
510 {OP_WR_E1, CSDM_REG_CFC_RSP_START_ADDR, 0xa11},
511 {OP_WR_E1H, CSDM_REG_CFC_RSP_START_ADDR, 0x211},
512 {OP_WR_E1, CSDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
513 {OP_WR_E1H, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
514 {OP_WR_E1, CSDM_REG_Q_COUNTER_START_ADDR, 0xa04},
515 {OP_WR_E1H, CSDM_REG_Q_COUNTER_START_ADDR, 0x204},
516 {OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
517 {OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
518 {OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
519 {OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
520 {OP_WR, CSDM_REG_AGG_INT_EVENT_0, 0xc6},
521 {OP_WR, CSDM_REG_AGG_INT_EVENT_1, 0x0},
522 {OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
523 {OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
524 {OP_ZR, CSDM_REG_AGG_INT_EVENT_4, 0x1c},
525 {OP_WR, CSDM_REG_AGG_INT_T_0, 0x1},
526 {OP_ZR, CSDM_REG_AGG_INT_T_1, 0x5f},
527 {OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
528 {OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
529 {OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
530 {OP_WR, CSDM_REG_ENABLE_OUT2, 0xf},
531 {OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0},
532 {OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0},
533 {OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0},
534 {OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0},
535 {OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0},
536 {OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0},
537 {OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0},
538 {OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0},
539 {OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0},
540 {OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0},
541 {OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0},
542 {OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
543 {OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
544 {OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
545 {OP_WR_E1, CSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
546 {OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
547 {OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
548 {OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
549 #define CSDM_COMMON_END 440
550 #define USDM_COMMON_START 440
551 {OP_WR_E1, USDM_REG_CFC_RSP_START_ADDR, 0xa11},
552 {OP_WR_E1H, USDM_REG_CFC_RSP_START_ADDR, 0x411},
553 {OP_WR_E1, USDM_REG_CMP_COUNTER_START_ADDR, 0xa00},
554 {OP_WR_E1H, USDM_REG_CMP_COUNTER_START_ADDR, 0x400},
555 {OP_WR_E1, USDM_REG_Q_COUNTER_START_ADDR, 0xa04},
556 {OP_WR_E1H, USDM_REG_Q_COUNTER_START_ADDR, 0x404},
557 {OP_WR_E1, USDM_REG_PCK_END_MSG_START_ADDR, 0xa21},
558 {OP_WR_E1H, USDM_REG_PCK_END_MSG_START_ADDR, 0x421},
559 {OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
560 {OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
561 {OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
562 {OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
563 {OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
564 {OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
565 {OP_WR, USDM_REG_AGG_INT_EVENT_2, 0x34},
566 {OP_WR, USDM_REG_AGG_INT_EVENT_3, 0x35},
567 {OP_ZR, USDM_REG_AGG_INT_EVENT_4, 0x5c},
568 {OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
569 {OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x1f},
570 {OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
571 {OP_WR, USDM_REG_ENABLE_IN2, 0x3f},
572 {OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff},
573 {OP_WR, USDM_REG_ENABLE_OUT2, 0xf},
574 {OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0},
575 {OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0},
576 {OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0},
577 {OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0},
578 {OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0},
579 {OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0},
580 {OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0},
581 {OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0},
582 {OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0},
583 {OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0},
584 {OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0},
585 {OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0},
586 {OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
587 {OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
588 {OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
589 {OP_WR_E1, USDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
590 {OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
591 {OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
592 {OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
593 #define USDM_COMMON_END 482
594 #define CCM_COMMON_START 482
595 {OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
596 {OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
597 {OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
598 {OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000},
599 {OP_WR, CCM_REG_ERR_EVNT_ID, 0x33},
600 {OP_WR, CCM_REG_TSEM_WEIGHT, 0x0},
601 {OP_WR, CCM_REG_XSEM_WEIGHT, 0x4},
602 {OP_WR, CCM_REG_USEM_WEIGHT, 0x4},
603 {OP_ZR, CCM_REG_PBF_WEIGHT, 0x2},
604 {OP_WR, CCM_REG_CQM_P_WEIGHT, 0x2},
605 {OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1},
606 {OP_WR, CCM_REG_CNT_AUX1_Q, 0x2},
607 {OP_WR, CCM_REG_CNT_AUX2_Q, 0x2},
608 {OP_WR, CCM_REG_INV_DONE_Q, 0x1},
609 {OP_WR, CCM_REG_GR_ARB_TYPE, 0x1},
610 {OP_WR, CCM_REG_GR_LD0_PR, 0x1},
611 {OP_WR, CCM_REG_GR_LD1_PR, 0x2},
612 {OP_WR, CCM_REG_CFC_INIT_CRD, 0x1},
613 {OP_WR, CCM_REG_CQM_INIT_CRD, 0x20},
614 {OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40},
615 {OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40},
616 {OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
617 {OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
618 {OP_ZR, CCM_REG_XX_TABLE, 0x12},
619 {OP_SW_E1, CCM_REG_XX_DESCR_TABLE, 0x240238},
620 {OP_SW_E1H, CCM_REG_XX_DESCR_TABLE, 0x240254},
621 {OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
622 {OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
623 {OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
624 {OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
625 {OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
626 {OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
627 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
628 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
629 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
630 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
631 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
632 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
633 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
634 {OP_WR_E1, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
635 {OP_WR_E1, CCM_REG_PHYS_QNUM1_0, 0xc},
636 {OP_WR_E1, CCM_REG_PHYS_QNUM1_1, 0x2c},
637 {OP_WR_E1, CCM_REG_PHYS_QNUM2_0, 0xc},
638 {OP_WR_E1, CCM_REG_PHYS_QNUM2_1, 0x2c},
639 {OP_WR_E1, CCM_REG_PHYS_QNUM3_0, 0xc},
640 {OP_WR_E1, CCM_REG_PHYS_QNUM3_1, 0x2c},
641 {OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
642 {OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
643 {OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
644 {OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1},
645 {OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1},
646 {OP_WR, CCM_REG_CSDM_IFEN, 0x1},
647 {OP_WR, CCM_REG_TSEM_IFEN, 0x1},
648 {OP_WR, CCM_REG_XSEM_IFEN, 0x1},
649 {OP_WR, CCM_REG_USEM_IFEN, 0x1},
650 {OP_WR, CCM_REG_PBF_IFEN, 0x1},
651 {OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1},
652 {OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1},
653 {OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
654 {OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
655 {OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
656 #define CCM_COMMON_END 543
657 #define CCM_FUNC0_START 543
658 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
659 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
660 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
661 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
662 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0xc},
663 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0xb},
664 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x7},
665 #define CCM_FUNC0_END 550
666 #define CCM_FUNC1_START 550
667 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
668 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
669 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
670 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
671 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x2c},
672 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x2b},
673 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x27},
674 #define CCM_FUNC1_END 557
675 #define CCM_FUNC2_START 557
676 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x19},
677 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a},
678 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x17},
679 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x17},
680 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x1c},
681 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x1b},
682 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x17},
683 #define CCM_FUNC2_END 564
684 #define CCM_FUNC3_START 564
685 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x39},
686 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a},
687 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x37},
688 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x37},
689 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x3c},
690 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x3b},
691 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x37},
692 #define CCM_FUNC3_END 571
693 #define CCM_FUNC4_START 571
694 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x49},
695 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a},
696 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x47},
697 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x47},
698 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x4c},
699 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x4b},
700 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x47},
701 #define CCM_FUNC4_END 578
702 #define CCM_FUNC5_START 578
703 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x69},
704 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a},
705 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x67},
706 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x67},
707 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x6c},
708 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x6b},
709 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x67},
710 #define CCM_FUNC5_END 585
711 #define CCM_FUNC6_START 585
712 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_0, 0x59},
713 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a},
714 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_0, 0x57},
715 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_0, 0x57},
716 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_0, 0x5c},
717 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_0, 0x5b},
718 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_0, 0x57},
719 #define CCM_FUNC6_END 592
720 #define CCM_FUNC7_START 592
721 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM0_1, 0x79},
722 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a},
723 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM2_1, 0x77},
724 {OP_WR_E1H, CCM_REG_QOS_PHYS_QNUM3_1, 0x77},
725 {OP_WR_E1H, CCM_REG_PHYS_QNUM1_1, 0x7c},
726 {OP_WR_E1H, CCM_REG_PHYS_QNUM2_1, 0x7b},
727 {OP_WR_E1H, CCM_REG_PHYS_QNUM3_1, 0x77},
728 #define CCM_FUNC7_END 599
729 #define UCM_COMMON_START 599
730 {OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
731 {OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
732 {OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
733 {OP_WR, UCM_REG_TM_UCM_HDR, 0x30},
734 {OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000},
735 {OP_WR, UCM_REG_ERR_EVNT_ID, 0x33},
736 {OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30},
737 {OP_WR, UCM_REG_STOP_EVNT_ID, 0x31},
738 {OP_WR, UCM_REG_TSEM_WEIGHT, 0x3},
739 {OP_WR, UCM_REG_CSEM_WEIGHT, 0x0},
740 {OP_WR, UCM_REG_CP_WEIGHT, 0x0},
741 {OP_WR, UCM_REG_UQM_P_WEIGHT, 0x6},
742 {OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1},
743 {OP_WR, UCM_REG_INV_CFLG_Q, 0x1},
744 {OP_WR, UCM_REG_GR_ARB_TYPE, 0x1},
745 {OP_WR, UCM_REG_GR_LD0_PR, 0x1},
746 {OP_WR, UCM_REG_GR_LD1_PR, 0x2},
747 {OP_WR, UCM_REG_CFC_INIT_CRD, 0x1},
748 {OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40},
749 {OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
750 {OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
751 {OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
752 {OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
753 {OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
754 {OP_ZR, UCM_REG_XX_TABLE, 0x12},
755 {OP_SW_E1, UCM_REG_XX_DESCR_TABLE, 0x1b025c},
756 {OP_SW_E1H, UCM_REG_XX_DESCR_TABLE, 0x1b0278},
757 {OP_WR, UCM_REG_N_SM_CTX_LD_0, 0x10},
758 {OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x7},
759 {OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
760 {OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
761 {OP_ZR_E1, UCM_REG_N_SM_CTX_LD_4, 0x4},
762 {OP_WR_E1H, UCM_REG_N_SM_CTX_LD_4, 0xd},
763 {OP_ZR_E1H, UCM_REG_N_SM_CTX_LD_5, 0x3},
764 {OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
765 {OP_WR_E1, UCM_REG_PHYS_QNUM0_0, 0xf},
766 {OP_WR_E1, UCM_REG_PHYS_QNUM0_1, 0x2f},
767 {OP_WR_E1, UCM_REG_PHYS_QNUM1_0, 0xe},
768 {OP_WR_E1, UCM_REG_PHYS_QNUM1_1, 0x2e},
769 {OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
770 {OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
771 {OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
772 {OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1},
773 {OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1},
774 {OP_WR, UCM_REG_USDM_IFEN, 0x1},
775 {OP_WR, UCM_REG_TM_UCM_IFEN, 0x1},
776 {OP_WR, UCM_REG_UCM_TM_IFEN, 0x1},
777 {OP_WR, UCM_REG_TSEM_IFEN, 0x1},
778 {OP_WR, UCM_REG_CSEM_IFEN, 0x1},
779 {OP_WR, UCM_REG_XSEM_IFEN, 0x1},
780 {OP_WR, UCM_REG_DORQ_IFEN, 0x1},
781 {OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1},
782 {OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1},
783 {OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
784 {OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
785 {OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
786 #define UCM_COMMON_END 655
787 #define UCM_FUNC0_START 655
788 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0xf},
789 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0xe},
790 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
791 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
792 #define UCM_FUNC0_END 659
793 #define UCM_FUNC1_START 659
794 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x2f},
795 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x2e},
796 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
797 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
798 #define UCM_FUNC1_END 663
799 #define UCM_FUNC2_START 663
800 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x1f},
801 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x1e},
802 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
803 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
804 #define UCM_FUNC2_END 667
805 #define UCM_FUNC3_START 667
806 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x3f},
807 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x3e},
808 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
809 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
810 #define UCM_FUNC3_END 671
811 #define UCM_FUNC4_START 671
812 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x4f},
813 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x4e},
814 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
815 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
816 #define UCM_FUNC4_END 675
817 #define UCM_FUNC5_START 675
818 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x6f},
819 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x6e},
820 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
821 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
822 #define UCM_FUNC5_END 679
823 #define UCM_FUNC6_START 679
824 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_0, 0x5f},
825 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_0, 0x5e},
826 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_0, 0x0},
827 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_0, 0x0},
828 #define UCM_FUNC6_END 683
829 #define UCM_FUNC7_START 683
830 {OP_WR_E1H, UCM_REG_PHYS_QNUM0_1, 0x7f},
831 {OP_WR_E1H, UCM_REG_PHYS_QNUM1_1, 0x7e},
832 {OP_WR_E1H, UCM_REG_PHYS_QNUM2_1, 0x0},
833 {OP_WR_E1H, UCM_REG_PHYS_QNUM3_1, 0x0},
834 #define UCM_FUNC7_END 687
835 #define USEM_COMMON_START 687
836 {OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
837 {OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
838 {OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
839 {OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0},
840 {OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0},
841 {OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0},
842 {OP_WR, USEM_REG_ARB_ELEMENT0, 0x1},
843 {OP_WR, USEM_REG_ARB_ELEMENT1, 0x2},
844 {OP_WR, USEM_REG_ARB_ELEMENT2, 0x3},
845 {OP_WR, USEM_REG_ARB_ELEMENT3, 0x0},
846 {OP_WR, USEM_REG_ARB_ELEMENT4, 0x4},
847 {OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1},
848 {OP_WR, USEM_REG_TS_0_AS, 0x0},
849 {OP_WR, USEM_REG_TS_1_AS, 0x1},
850 {OP_WR, USEM_REG_TS_2_AS, 0x4},
851 {OP_WR, USEM_REG_TS_3_AS, 0x0},
852 {OP_WR, USEM_REG_TS_4_AS, 0x1},
853 {OP_WR, USEM_REG_TS_5_AS, 0x3},
854 {OP_WR, USEM_REG_TS_6_AS, 0x0},
855 {OP_WR, USEM_REG_TS_7_AS, 0x1},
856 {OP_WR, USEM_REG_TS_8_AS, 0x4},
857 {OP_WR, USEM_REG_TS_9_AS, 0x0},
858 {OP_WR, USEM_REG_TS_10_AS, 0x1},
859 {OP_WR, USEM_REG_TS_11_AS, 0x3},
860 {OP_WR, USEM_REG_TS_12_AS, 0x0},
861 {OP_WR, USEM_REG_TS_13_AS, 0x1},
862 {OP_WR, USEM_REG_TS_14_AS, 0x4},
863 {OP_WR, USEM_REG_TS_15_AS, 0x0},
864 {OP_WR, USEM_REG_TS_16_AS, 0x4},
865 {OP_WR, USEM_REG_TS_17_AS, 0x3},
866 {OP_ZR, USEM_REG_TS_18_AS, 0x2},
867 {OP_WR, USEM_REG_ENABLE_IN, 0x3fff},
868 {OP_WR, USEM_REG_ENABLE_OUT, 0x3ff},
869 {OP_WR, USEM_REG_FIC0_DISABLE, 0x0},
870 {OP_WR, USEM_REG_FIC1_DISABLE, 0x0},
871 {OP_WR, USEM_REG_PAS_DISABLE, 0x0},
872 {OP_WR, USEM_REG_THREADS_LIST, 0xffff},
873 {OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800},
874 {OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
875 {OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a},
876 {OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
877 {OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
878 {OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
879 {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
880 {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138},
881 {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388},
882 {OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
883 {OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
884 {OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
885 {OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
886 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5000, 0x102},
887 {OP_WR_EMUL_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x0},
888 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1020, 0xc8},
889 {OP_WR_E1H, USEM_REG_FAST_MEMORY + 0x11480, 0x1},
890 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1000, 0x2},
891 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x2000, 0x102},
892 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57e8, 0x4},
893 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8020, 0xc8},
894 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x57d0, 0x5},
895 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x8000, 0x2},
896 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x57d0 + 0x14, 0x10277},
897 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3760, 0x4},
898 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1e20, 0x42},
899 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3738, 0x9},
900 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x400},
901 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x3738 + 0x24, 0x10293},
902 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c00, 0x2},
903 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3180, 0x42},
904 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2c00 + 0x8, 0x20278},
905 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
906 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b68, 0x2},
907 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4000, 0x2},
908 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x4b68 + 0x8, 0x2027a},
909 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x4000 + 0x8, 0x20294},
910 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b10, 0x2},
911 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
912 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x2830, 0x2027c},
913 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x20296},
914 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
915 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x74c0, 0x20298},
916 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
917 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c00, 0x10027e},
918 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c00, 0x10029a},
919 {OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
920 {OP_SW_E1, USEM_REG_FAST_MEMORY + 0x10c40, 0x10028e},
921 {OP_SW_E1H, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002aa},
922 {OP_ZP_E1, USEM_REG_INT_TABLE, 0xc20000},
923 {OP_ZP_E1H, USEM_REG_INT_TABLE, 0xc40000},
924 {OP_WR_64_E1, USEM_REG_INT_TABLE + 0x368, 0x13029e},
925 {OP_WR_64_E1H, USEM_REG_INT_TABLE + 0x368, 0x1302ba},
926 {OP_ZP_E1, USEM_REG_PRAM, 0x975a0000},
927 {OP_ZP_E1H, USEM_REG_PRAM, 0x985c0000},
928 {OP_WR_64_E1, USEM_REG_PRAM + 0x17f90, 0x500e02a0},
929 {OP_WR_64_E1H, USEM_REG_PRAM + 0x18200, 0x4fc002bc},
930 #define USEM_COMMON_END 781
931 #define USEM_PORT0_START 781
932 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1400, 0xa0},
933 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9000, 0xa0},
934 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1900, 0xa},
935 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9500, 0x28},
936 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1950, 0x2e},
937 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9640, 0x34},
938 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d00, 0x4},
939 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3080, 0x20},
940 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d20, 0x20},
941 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3288, 0x96},
942 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5440, 0x72},
943 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
944 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3000, 0x20},
945 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
946 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3100, 0x20},
947 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
948 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3200, 0x20},
949 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
950 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3300, 0x20},
951 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
952 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3400, 0x20},
953 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
954 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3500, 0x20},
955 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
956 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3600, 0x20},
957 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
958 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3700, 0x20},
959 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
960 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3800, 0x20},
961 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
962 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3900, 0x20},
963 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
964 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a00, 0x20},
965 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
966 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b00, 0x20},
967 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
968 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c00, 0x20},
969 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
970 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
971 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
972 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e00, 0x20},
973 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
974 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f00, 0x20},
975 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
976 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c10, 0x2},
977 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
978 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4b78, 0x52},
979 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e08, 0xc},
980 #define USEM_PORT0_END 829
981 #define USEM_PORT1_START 829
982 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1680, 0xa0},
983 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9280, 0xa0},
984 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1928, 0xa},
985 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x95a0, 0x28},
986 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1a08, 0x2e},
987 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x9710, 0x34},
988 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1d10, 0x4},
989 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3100, 0x20},
990 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x1da0, 0x20},
991 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x34e0, 0x96},
992 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x5608, 0x72},
993 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
994 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3080, 0x20},
995 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
996 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3180, 0x20},
997 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
998 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3280, 0x20},
999 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
1000 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3380, 0x20},
1001 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
1002 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3480, 0x20},
1003 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
1004 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3580, 0x20},
1005 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
1006 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3680, 0x20},
1007 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
1008 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3780, 0x20},
1009 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
1010 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3880, 0x20},
1011 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
1012 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3980, 0x20},
1013 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
1014 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3a80, 0x20},
1015 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
1016 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3b80, 0x20},
1017 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
1018 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3c80, 0x20},
1019 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
1020 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3d80, 0x20},
1021 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
1022 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3e80, 0x20},
1023 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
1024 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x3f80, 0x20},
1025 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
1026 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x2c20, 0x2},
1027 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
1028 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4cc0, 0x52},
1029 {OP_ZR_E1, USEM_REG_FAST_MEMORY + 0x4e38, 0xc},
1030 #define USEM_PORT1_END 877
1031 #define USEM_FUNC0_START 877
1032 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3000, 0x4},
1033 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4010, 0x2},
1034 #define USEM_FUNC0_END 879
1035 #define USEM_FUNC1_START 879
1036 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3010, 0x4},
1037 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4020, 0x2},
1038 #define USEM_FUNC1_END 881
1039 #define USEM_FUNC2_START 881
1040 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3020, 0x4},
1041 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4030, 0x2},
1042 #define USEM_FUNC2_END 883
1043 #define USEM_FUNC3_START 883
1044 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3030, 0x4},
1045 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4040, 0x2},
1046 #define USEM_FUNC3_END 885
1047 #define USEM_FUNC4_START 885
1048 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3040, 0x4},
1049 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4050, 0x2},
1050 #define USEM_FUNC4_END 887
1051 #define USEM_FUNC5_START 887
1052 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3050, 0x4},
1053 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4060, 0x2},
1054 #define USEM_FUNC5_END 889
1055 #define USEM_FUNC6_START 889
1056 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3060, 0x4},
1057 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4070, 0x2},
1058 #define USEM_FUNC6_END 891
1059 #define USEM_FUNC7_START 891
1060 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x3070, 0x4},
1061 {OP_ZR_E1H, USEM_REG_FAST_MEMORY + 0x4080, 0x2},
1062 #define USEM_FUNC7_END 893
1063 #define CSEM_COMMON_START 893
1064 {OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
1065 {OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
1066 {OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
1067 {OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0},
1068 {OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0},
1069 {OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0},
1070 {OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1},
1071 {OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2},
1072 {OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3},
1073 {OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0},
1074 {OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4},
1075 {OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1},
1076 {OP_WR, CSEM_REG_TS_0_AS, 0x0},
1077 {OP_WR, CSEM_REG_TS_1_AS, 0x1},
1078 {OP_WR, CSEM_REG_TS_2_AS, 0x4},
1079 {OP_WR, CSEM_REG_TS_3_AS, 0x0},
1080 {OP_WR, CSEM_REG_TS_4_AS, 0x1},
1081 {OP_WR, CSEM_REG_TS_5_AS, 0x3},
1082 {OP_WR, CSEM_REG_TS_6_AS, 0x0},
1083 {OP_WR, CSEM_REG_TS_7_AS, 0x1},
1084 {OP_WR, CSEM_REG_TS_8_AS, 0x4},
1085 {OP_WR, CSEM_REG_TS_9_AS, 0x0},
1086 {OP_WR, CSEM_REG_TS_10_AS, 0x1},
1087 {OP_WR, CSEM_REG_TS_11_AS, 0x3},
1088 {OP_WR, CSEM_REG_TS_12_AS, 0x0},
1089 {OP_WR, CSEM_REG_TS_13_AS, 0x1},
1090 {OP_WR, CSEM_REG_TS_14_AS, 0x4},
1091 {OP_WR, CSEM_REG_TS_15_AS, 0x0},
1092 {OP_WR, CSEM_REG_TS_16_AS, 0x4},
1093 {OP_WR, CSEM_REG_TS_17_AS, 0x3},
1094 {OP_ZR, CSEM_REG_TS_18_AS, 0x2},
1095 {OP_WR, CSEM_REG_ENABLE_IN, 0x3fff},
1096 {OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff},
1097 {OP_WR, CSEM_REG_FIC0_DISABLE, 0x0},
1098 {OP_WR, CSEM_REG_FIC1_DISABLE, 0x0},
1099 {OP_WR, CSEM_REG_PAS_DISABLE, 0x0},
1100 {OP_WR, CSEM_REG_THREADS_LIST, 0xffff},
1101 {OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800},
1102 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
1103 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10},
1104 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12},
1105 {OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
1106 {OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
1107 {OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
1108 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x5000, 0x42},
1109 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11480, 0x1},
1110 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
1111 {OP_WR_EMUL_E1H, CSEM_REG_FAST_MEMORY + 0x11480, 0x0},
1112 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1000, 0x2},
1113 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x1000, 0x42},
1114 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2000, 0xc0},
1115 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x7020, 0xc8},
1116 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3070, 0x80},
1117 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x7000, 0x2},
1118 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x4280, 0x4},
1119 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
1120 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x25c0, 0x240},
1121 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
1122 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x2ec8, 0x802a2},
1123 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
1124 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
1125 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6280, 0x240},
1126 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x6b88, 0x2002be},
1127 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
1128 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002aa},
1129 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c00, 0x1002de},
1130 {OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
1131 {OP_SW_E1, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ba},
1132 {OP_SW_E1H, CSEM_REG_FAST_MEMORY + 0x10c40, 0x1002ee},
1133 {OP_ZP_E1, CSEM_REG_INT_TABLE, 0x6e0000},
1134 {OP_ZP_E1H, CSEM_REG_INT_TABLE, 0x6f0000},
1135 {OP_WR_64_E1, CSEM_REG_INT_TABLE + 0x380, 0x1002ca},
1136 {OP_WR_64_E1H, CSEM_REG_INT_TABLE + 0x380, 0x1002fe},
1137 {OP_ZP_E1, CSEM_REG_PRAM, 0x48bc0000},
1138 {OP_ZP_E1H, CSEM_REG_PRAM, 0x493d0000},
1139 {OP_WR_64_E1, CSEM_REG_PRAM + 0xb210, 0x682402cc},
1140 {OP_WR_64_E1H, CSEM_REG_PRAM + 0xb430, 0x67e00300},
1141 #define CSEM_COMMON_END 970
1142 #define CSEM_PORT0_START 970
1143 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1400, 0xa0},
1144 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8000, 0xa0},
1145 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1900, 0x10},
1146 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8500, 0x40},
1147 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1980, 0x30},
1148 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8700, 0x3c},
1149 {OP_WR_E1, CSEM_REG_FAST_MEMORY + 0x5118, 0x0},
1150 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4040, 0x6},
1151 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2300, 0xe},
1152 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
1153 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3040, 0x6},
1154 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2410, 0x30},
1155 #define CSEM_PORT0_END 982
1156 #define CSEM_PORT1_START 982
1157 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1680, 0xa0},
1158 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8280, 0xa0},
1159 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1940, 0x10},
1160 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x8600, 0x40},
1161 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x1a40, 0x30},
1162 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x87f0, 0x3c},
1163 {OP_WR_E1, CSEM_REG_FAST_MEMORY + 0x511c, 0x0},
1164 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x4058, 0x6},
1165 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x2338, 0xe},
1166 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
1167 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x3058, 0x6},
1168 {OP_ZR_E1, CSEM_REG_FAST_MEMORY + 0x24d0, 0x30},
1169 #define CSEM_PORT1_END 994
1170 #define CSEM_FUNC0_START 994
1171 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
1172 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
1173 #define CSEM_FUNC0_END 996
1174 #define CSEM_FUNC1_START 996
1175 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
1176 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
1177 #define CSEM_FUNC1_END 998
1178 #define CSEM_FUNC2_START 998
1179 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
1180 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
1181 #define CSEM_FUNC2_END 1000
1182 #define CSEM_FUNC3_START 1000
1183 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
1184 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
1185 #define CSEM_FUNC3_END 1002
1186 #define CSEM_FUNC4_START 1002
1187 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
1188 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
1189 #define CSEM_FUNC4_END 1004
1190 #define CSEM_FUNC5_START 1004
1191 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
1192 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
1193 #define CSEM_FUNC5_END 1006
1194 #define CSEM_FUNC6_START 1006
1195 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
1196 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
1197 #define CSEM_FUNC6_END 1008
1198 #define CSEM_FUNC7_START 1008
1199 {OP_WR_E1H, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
1200 {OP_ZR_E1H, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
1201 #define CSEM_FUNC7_END 1010
1202 #define XPB_COMMON_START 1010
1203 {OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x20},
1204 #define XPB_COMMON_END 1011
1205 #define DQ_COMMON_START 1011
1206 {OP_WR, DORQ_REG_MODE_ACT, 0x2},
1207 {OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
1208 {OP_WR, DORQ_REG_OUTST_REQ, 0x4},
1209 {OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8},
1210 {OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2},
1211 {OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90},
1212 {OP_WR, DORQ_REG_CMHEAD_RX, 0x90},
1213 {OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090},
1214 {OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000},
1215 {OP_WR, DORQ_REG_AGG_CMD0, 0x8a},
1216 {OP_WR, DORQ_REG_AGG_CMD1, 0x80},
1217 {OP_WR, DORQ_REG_AGG_CMD2, 0x90},
1218 {OP_WR, DORQ_REG_AGG_CMD3, 0x80},
1219 {OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6},
1220 {OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0},
1221 {OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
1222 {OP_WR, DORQ_REG_REGN, 0x7c1004},
1223 {OP_WR, DORQ_REG_IF_EN, 0xf},
1224 #define DQ_COMMON_END 1029
1225 #define TIMERS_COMMON_START 1029
1226 {OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
1227 {OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
1228 {OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
1229 {OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1},
1230 {OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1},
1231 {OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
1232 {OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
1233 {OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
1234 {OP_WR_E1, TM_REG_PCIARB_CRDCNT_VAL, 0x1},
1235 {OP_WR_E1H, TM_REG_PCIARB_CRDCNT_VAL, 0x2},
1236 {OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090},
1237 {OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c},
1238 {OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4},
1239 {OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
1240 {OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
1241 {OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
1242 {OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20},
1243 {OP_WR, TM_REG_EN_TIMERS, 0x1},
1244 {OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1},
1245 {OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
1246 {OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
1247 {OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
1248 #define TIMERS_COMMON_END 1051
1249 #define TIMERS_PORT0_START 1051
1250 {OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
1251 #define TIMERS_PORT0_END 1052
1252 #define TIMERS_PORT1_START 1052
1253 {OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
1254 #define TIMERS_PORT1_END 1053
1255 #define XSDM_COMMON_START 1053
1256 {OP_WR_E1, XSDM_REG_CFC_RSP_START_ADDR, 0x614},
1257 {OP_WR_E1H, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
1258 {OP_WR_E1, XSDM_REG_CMP_COUNTER_START_ADDR, 0x600},
1259 {OP_WR_E1H, XSDM_REG_CMP_COUNTER_START_ADDR, 0x410},
1260 {OP_WR_E1, XSDM_REG_Q_COUNTER_START_ADDR, 0x604},
1261 {OP_WR_E1H, XSDM_REG_Q_COUNTER_START_ADDR, 0x414},
1262 {OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
1263 {OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
1264 {OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
1265 {OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
1266 {OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
1267 {OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
1268 {OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34},
1269 {OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35},
1270 {OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23},
1271 {OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24},
1272 {OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25},
1273 {OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26},
1274 {OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27},
1275 {OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29},
1276 {OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a},
1277 {OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b},
1278 {OP_ZR, XSDM_REG_AGG_INT_EVENT_12, 0x54},
1279 {OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
1280 {OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
1281 {OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
1282 {OP_WR, XSDM_REG_ENABLE_IN2, 0x3f},
1283 {OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff},
1284 {OP_WR, XSDM_REG_ENABLE_OUT2, 0xf},
1285 {OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0},
1286 {OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0},
1287 {OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0},
1288 {OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0},
1289 {OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0},
1290 {OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0},
1291 {OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0},
1292 {OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0},
1293 {OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0},
1294 {OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0},
1295 {OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0},
1296 {OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
1297 {OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
1298 {OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
1299 {OP_WR_E1, XSDM_REG_INIT_CREDIT_PXP_CTRL, 0x1},
1300 {OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
1301 {OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
1302 {OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
1303 #define XSDM_COMMON_END 1100
1304 #define QM_COMMON_START 1100
1305 {OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
1306 {OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
1307 {OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
1308 {OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5},
1309 {OP_WR, QM_REG_PCIREQAT, 0x2},
1310 {OP_WR, QM_REG_CMINITCRD_0, 0x4},
1311 {OP_WR, QM_REG_CMINITCRD_1, 0x4},
1312 {OP_WR, QM_REG_CMINITCRD_2, 0x4},
1313 {OP_WR, QM_REG_CMINITCRD_3, 0x4},
1314 {OP_WR, QM_REG_CMINITCRD_4, 0x4},
1315 {OP_WR, QM_REG_CMINITCRD_5, 0x4},
1316 {OP_WR, QM_REG_CMINITCRD_6, 0x4},
1317 {OP_WR, QM_REG_CMINITCRD_7, 0x4},
1318 {OP_WR, QM_REG_OUTLDREQ, 0x4},
1319 {OP_WR, QM_REG_CTXREG_0, 0x7c},
1320 {OP_WR, QM_REG_CTXREG_1, 0x3d},
1321 {OP_WR, QM_REG_CTXREG_2, 0x3f},
1322 {OP_WR, QM_REG_CTXREG_3, 0x9c},
1323 {OP_WR, QM_REG_ENSEC, 0x7},
1324 {OP_ZR, QM_REG_QVOQIDX_0, 0x5},
1325 {OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101},
1326 {OP_WR, QM_REG_QVOQIDX_5, 0x0},
1327 {OP_WR, QM_REG_QVOQIDX_6, 0x4},
1328 {OP_WR, QM_REG_QVOQIDX_7, 0x4},
1329 {OP_WR, QM_REG_QVOQIDX_8, 0x2},
1330 {OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004},
1331 {OP_WR, QM_REG_QVOQIDX_9, 0x5},
1332 {OP_WR, QM_REG_QVOQIDX_10, 0x5},
1333 {OP_WR, QM_REG_QVOQIDX_11, 0x5},
1334 {OP_WR, QM_REG_QVOQIDX_12, 0x5},
1335 {OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001},
1336 {OP_WR, QM_REG_QVOQIDX_13, 0x8},
1337 {OP_WR, QM_REG_QVOQIDX_14, 0x6},
1338 {OP_WR, QM_REG_QVOQIDX_15, 0x7},
1339 {OP_WR, QM_REG_QVOQIDX_16, 0x0},
1340 {OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
1341 {OP_ZR, QM_REG_QVOQIDX_17, 0x4},
1342 {OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
1343 {OP_ZR_E1, QM_REG_QVOQIDX_21, 0x4},
1344 {OP_WR_E1H, QM_REG_QVOQIDX_21, 0x0},
1345 {OP_WR_E1, QM_REG_WRRWEIGHTS_5, 0x1010101},
1346 {OP_WR_E1H, QM_REG_QVOQIDX_22, 0x4},
1347 {OP_ZR_E1, QM_REG_QVOQIDX_25, 0x4},
1348 {OP_WR_E1H, QM_REG_QVOQIDX_23, 0x4},
1349 {OP_WR_E1, QM_REG_WRRWEIGHTS_6, 0x1010101},
1350 {OP_WR_E1H, QM_REG_QVOQIDX_24, 0x2},
1351 {OP_ZR_E1, QM_REG_QVOQIDX_29, 0x3},
1352 {OP_WR_E1H, QM_REG_WRRWEIGHTS_5, 0x8012004},
1353 {OP_WR_E1H, QM_REG_QVOQIDX_25, 0x5},
1354 {OP_WR_E1H, QM_REG_QVOQIDX_26, 0x5},
1355 {OP_WR_E1H, QM_REG_QVOQIDX_27, 0x5},
1356 {OP_WR_E1H, QM_REG_QVOQIDX_28, 0x5},
1357 {OP_WR_E1H, QM_REG_WRRWEIGHTS_6, 0x20081001},
1358 {OP_WR_E1H, QM_REG_QVOQIDX_29, 0x8},
1359 {OP_WR_E1H, QM_REG_QVOQIDX_30, 0x6},
1360 {OP_WR_E1H, QM_REG_QVOQIDX_31, 0x7},
1361 {OP_WR, QM_REG_QVOQIDX_32, 0x1},
1362 {OP_WR_E1, QM_REG_WRRWEIGHTS_7, 0x1010101},
1363 {OP_WR_E1H, QM_REG_WRRWEIGHTS_7, 0x1010120},
1364 {OP_WR, QM_REG_QVOQIDX_33, 0x1},
1365 {OP_WR, QM_REG_QVOQIDX_34, 0x1},
1366 {OP_WR, QM_REG_QVOQIDX_35, 0x1},
1367 {OP_WR, QM_REG_QVOQIDX_36, 0x1},
1368 {OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101},
1369 {OP_WR, QM_REG_QVOQIDX_37, 0x1},
1370 {OP_WR, QM_REG_QVOQIDX_38, 0x4},
1371 {OP_WR, QM_REG_QVOQIDX_39, 0x4},
1372 {OP_WR, QM_REG_QVOQIDX_40, 0x2},
1373 {OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004},
1374 {OP_WR, QM_REG_QVOQIDX_41, 0x5},
1375 {OP_WR, QM_REG_QVOQIDX_42, 0x5},
1376 {OP_WR, QM_REG_QVOQIDX_43, 0x5},
1377 {OP_WR, QM_REG_QVOQIDX_44, 0x5},
1378 {OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001},
1379 {OP_WR, QM_REG_QVOQIDX_45, 0x8},
1380 {OP_WR, QM_REG_QVOQIDX_46, 0x6},
1381 {OP_WR, QM_REG_QVOQIDX_47, 0x7},
1382 {OP_WR, QM_REG_QVOQIDX_48, 0x1},
1383 {OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120},
1384 {OP_WR, QM_REG_QVOQIDX_49, 0x1},
1385 {OP_WR, QM_REG_QVOQIDX_50, 0x1},
1386 {OP_WR, QM_REG_QVOQIDX_51, 0x1},
1387 {OP_WR, QM_REG_QVOQIDX_52, 0x1},
1388 {OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
1389 {OP_WR, QM_REG_QVOQIDX_53, 0x1},
1390 {OP_WR_E1, QM_REG_QVOQIDX_54, 0x1},
1391 {OP_WR_E1H, QM_REG_QVOQIDX_54, 0x4},
1392 {OP_WR_E1, QM_REG_QVOQIDX_55, 0x1},
1393 {OP_WR_E1H, QM_REG_QVOQIDX_55, 0x4},
1394 {OP_WR_E1, QM_REG_QVOQIDX_56, 0x1},
1395 {OP_WR_E1H, QM_REG_QVOQIDX_56, 0x2},
1396 {OP_WR_E1, QM_REG_WRRWEIGHTS_13, 0x1010101},
1397 {OP_WR_E1H, QM_REG_WRRWEIGHTS_13, 0x8012004},
1398 {OP_WR_E1, QM_REG_QVOQIDX_57, 0x1},
1399 {OP_WR_E1H, QM_REG_QVOQIDX_57, 0x5},
1400 {OP_WR_E1, QM_REG_QVOQIDX_58, 0x1},
1401 {OP_WR_E1H, QM_REG_QVOQIDX_58, 0x5},
1402 {OP_WR_E1, QM_REG_QVOQIDX_59, 0x1},
1403 {OP_WR_E1H, QM_REG_QVOQIDX_59, 0x5},
1404 {OP_WR_E1, QM_REG_QVOQIDX_60, 0x1},
1405 {OP_WR_E1H, QM_REG_QVOQIDX_60, 0x5},
1406 {OP_WR_E1, QM_REG_WRRWEIGHTS_14, 0x1010101},
1407 {OP_WR_E1H, QM_REG_WRRWEIGHTS_14, 0x20081001},
1408 {OP_WR_E1, QM_REG_QVOQIDX_61, 0x1},
1409 {OP_WR_E1H, QM_REG_QVOQIDX_61, 0x8},
1410 {OP_WR_E1, QM_REG_QVOQIDX_62, 0x1},
1411 {OP_WR_E1H, QM_REG_QVOQIDX_62, 0x6},
1412 {OP_WR_E1, QM_REG_QVOQIDX_63, 0x1},
1413 {OP_WR_E1H, QM_REG_QVOQIDX_63, 0x7},
1414 {OP_WR_E1, QM_REG_WRRWEIGHTS_15, 0x1010101},
1415 {OP_WR_E1H, QM_REG_QVOQIDX_64, 0x0},
1416 {OP_WR_E1, QM_REG_VOQQMASK_0_LSB, 0xffff003f},
1417 {OP_WR_E1H, QM_REG_WRRWEIGHTS_15, 0x1010120},
1418 {OP_ZR_E1, QM_REG_VOQQMASK_0_MSB, 0x2},
1419 {OP_ZR_E1H, QM_REG_QVOQIDX_65, 0x4},
1420 {OP_WR_E1, QM_REG_VOQQMASK_1_MSB, 0xffff003f},
1421 {OP_WR_E1H, QM_REG_WRRWEIGHTS_16, 0x1010101},
1422 {OP_WR_E1, QM_REG_VOQQMASK_2_LSB, 0x100},
1423 {OP_WR_E1H, QM_REG_QVOQIDX_69, 0x0},
1424 {OP_WR_E1, QM_REG_VOQQMASK_2_MSB, 0x100},
1425 {OP_WR_E1H, QM_REG_QVOQIDX_70, 0x4},
1426 {OP_WR_E1H, QM_REG_QVOQIDX_71, 0x4},
1427 {OP_WR_E1H, QM_REG_QVOQIDX_72, 0x2},
1428 {OP_WR_E1H, QM_REG_WRRWEIGHTS_17, 0x8012004},
1429 {OP_WR_E1H, QM_REG_QVOQIDX_73, 0x5},
1430 {OP_WR_E1H, QM_REG_QVOQIDX_74, 0x5},
1431 {OP_WR_E1H, QM_REG_QVOQIDX_75, 0x5},
1432 {OP_WR_E1H, QM_REG_QVOQIDX_76, 0x5},
1433 {OP_WR_E1H, QM_REG_WRRWEIGHTS_18, 0x20081001},
1434 {OP_WR_E1H, QM_REG_QVOQIDX_77, 0x8},
1435 {OP_WR_E1H, QM_REG_QVOQIDX_78, 0x6},
1436 {OP_WR_E1H, QM_REG_QVOQIDX_79, 0x7},
1437 {OP_WR_E1H, QM_REG_QVOQIDX_80, 0x0},
1438 {OP_WR_E1H, QM_REG_WRRWEIGHTS_19, 0x1010120},
1439 {OP_ZR_E1H, QM_REG_QVOQIDX_81, 0x4},
1440 {OP_WR_E1H, QM_REG_WRRWEIGHTS_20, 0x1010101},
1441 {OP_WR_E1H, QM_REG_QVOQIDX_85, 0x0},
1442 {OP_WR_E1H, QM_REG_QVOQIDX_86, 0x4},
1443 {OP_WR_E1H, QM_REG_QVOQIDX_87, 0x4},
1444 {OP_WR_E1H, QM_REG_QVOQIDX_88, 0x2},
1445 {OP_WR_E1H, QM_REG_WRRWEIGHTS_21, 0x8012004},
1446 {OP_WR_E1H, QM_REG_QVOQIDX_89, 0x5},
1447 {OP_WR_E1H, QM_REG_QVOQIDX_90, 0x5},
1448 {OP_WR_E1H, QM_REG_QVOQIDX_91, 0x5},
1449 {OP_WR_E1H, QM_REG_QVOQIDX_92, 0x5},
1450 {OP_WR_E1H, QM_REG_WRRWEIGHTS_22, 0x20081001},
1451 {OP_WR_E1H, QM_REG_QVOQIDX_93, 0x8},
1452 {OP_WR_E1H, QM_REG_QVOQIDX_94, 0x6},
1453 {OP_WR_E1H, QM_REG_QVOQIDX_95, 0x7},
1454 {OP_WR_E1H, QM_REG_QVOQIDX_96, 0x1},
1455 {OP_WR_E1H, QM_REG_WRRWEIGHTS_23, 0x1010120},
1456 {OP_WR_E1H, QM_REG_QVOQIDX_97, 0x1},
1457 {OP_WR_E1H, QM_REG_QVOQIDX_98, 0x1},
1458 {OP_WR_E1H, QM_REG_QVOQIDX_99, 0x1},
1459 {OP_WR_E1H, QM_REG_QVOQIDX_100, 0x1},
1460 {OP_WR_E1H, QM_REG_WRRWEIGHTS_24, 0x1010101},
1461 {OP_WR_E1H, QM_REG_QVOQIDX_101, 0x1},
1462 {OP_WR_E1H, QM_REG_QVOQIDX_102, 0x4},
1463 {OP_WR_E1H, QM_REG_QVOQIDX_103, 0x4},
1464 {OP_WR_E1H, QM_REG_QVOQIDX_104, 0x2},
1465 {OP_WR_E1H, QM_REG_WRRWEIGHTS_25, 0x8012004},
1466 {OP_WR_E1H, QM_REG_QVOQIDX_105, 0x5},
1467 {OP_WR_E1H, QM_REG_QVOQIDX_106, 0x5},
1468 {OP_WR_E1H, QM_REG_QVOQIDX_107, 0x5},
1469 {OP_WR_E1H, QM_REG_QVOQIDX_108, 0x5},
1470 {OP_WR_E1H, QM_REG_WRRWEIGHTS_26, 0x20081001},
1471 {OP_WR_E1H, QM_REG_QVOQIDX_109, 0x8},
1472 {OP_WR_E1H, QM_REG_QVOQIDX_110, 0x6},
1473 {OP_WR_E1H, QM_REG_QVOQIDX_111, 0x7},
1474 {OP_WR_E1H, QM_REG_QVOQIDX_112, 0x1},
1475 {OP_WR_E1H, QM_REG_WRRWEIGHTS_27, 0x1010120},
1476 {OP_WR_E1H, QM_REG_QVOQIDX_113, 0x1},
1477 {OP_WR_E1H, QM_REG_QVOQIDX_114, 0x1},
1478 {OP_WR_E1H, QM_REG_QVOQIDX_115, 0x1},
1479 {OP_WR_E1H, QM_REG_QVOQIDX_116, 0x1},
1480 {OP_WR_E1H, QM_REG_WRRWEIGHTS_28, 0x1010101},
1481 {OP_WR_E1H, QM_REG_QVOQIDX_117, 0x1},
1482 {OP_WR_E1H, QM_REG_QVOQIDX_118, 0x4},
1483 {OP_WR_E1H, QM_REG_QVOQIDX_119, 0x4},
1484 {OP_WR_E1H, QM_REG_QVOQIDX_120, 0x2},
1485 {OP_WR_E1H, QM_REG_WRRWEIGHTS_29, 0x8012004},
1486 {OP_WR_E1H, QM_REG_QVOQIDX_121, 0x5},
1487 {OP_WR_E1H, QM_REG_QVOQIDX_122, 0x5},
1488 {OP_WR_E1H, QM_REG_QVOQIDX_123, 0x5},
1489 {OP_WR_E1H, QM_REG_QVOQIDX_124, 0x5},
1490 {OP_WR_E1H, QM_REG_WRRWEIGHTS_30, 0x20081001},
1491 {OP_WR_E1H, QM_REG_QVOQIDX_125, 0x8},
1492 {OP_WR_E1H, QM_REG_QVOQIDX_126, 0x6},
1493 {OP_WR_E1H, QM_REG_QVOQIDX_127, 0x7},
1494 {OP_WR_E1H, QM_REG_WRRWEIGHTS_31, 0x1010120},
1495 {OP_WR_E1H, QM_REG_VOQQMASK_0_LSB, 0x3f003f},
1496 {OP_WR_E1H, QM_REG_VOQQMASK_0_MSB, 0x0},
1497 {OP_WR_E1H, QM_REG_VOQQMASK_0_LSB_EXT_A, 0x3f003f},
1498 {OP_WR_E1H, QM_REG_VOQQMASK_0_MSB_EXT_A, 0x0},
1499 {OP_WR_E1H, QM_REG_VOQQMASK_1_LSB, 0x0},
1500 {OP_WR_E1H, QM_REG_VOQQMASK_1_MSB, 0x3f003f},
1501 {OP_WR_E1H, QM_REG_VOQQMASK_1_LSB_EXT_A, 0x0},
1502 {OP_WR_E1H, QM_REG_VOQQMASK_1_MSB_EXT_A, 0x3f003f},
1503 {OP_WR_E1H, QM_REG_VOQQMASK_2_LSB, 0x1000100},
1504 {OP_WR_E1H, QM_REG_VOQQMASK_2_MSB, 0x1000100},
1505 {OP_WR_E1H, QM_REG_VOQQMASK_2_LSB_EXT_A, 0x1000100},
1506 {OP_WR_E1H, QM_REG_VOQQMASK_2_MSB_EXT_A, 0x1000100},
1507 {OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
1508 {OP_WR_E1, QM_REG_VOQQMASK_4_LSB, 0xc0},
1509 {OP_WR_E1H, QM_REG_VOQQMASK_3_LSB_EXT_A, 0x0},
1510 {OP_WR_E1, QM_REG_VOQQMASK_4_MSB, 0xc0},
1511 {OP_WR_E1H, QM_REG_VOQQMASK_3_MSB_EXT_A, 0x0},
1512 {OP_WR_E1, QM_REG_VOQQMASK_5_LSB, 0x1e00},
1513 {OP_WR_E1H, QM_REG_VOQQMASK_4_LSB, 0xc000c0},
1514 {OP_WR_E1, QM_REG_VOQQMASK_5_MSB, 0x1e00},
1515 {OP_WR_E1H, QM_REG_VOQQMASK_4_MSB, 0xc000c0},
1516 {OP_WR_E1, QM_REG_VOQQMASK_6_LSB, 0x4000},
1517 {OP_WR_E1H, QM_REG_VOQQMASK_4_LSB_EXT_A, 0xc000c0},
1518 {OP_WR_E1, QM_REG_VOQQMASK_6_MSB, 0x4000},
1519 {OP_WR_E1H, QM_REG_VOQQMASK_4_MSB_EXT_A, 0xc000c0},
1520 {OP_WR_E1, QM_REG_VOQQMASK_7_LSB, 0x8000},
1521 {OP_WR_E1H, QM_REG_VOQQMASK_5_LSB, 0x1e001e00},
1522 {OP_WR_E1, QM_REG_VOQQMASK_7_MSB, 0x8000},
1523 {OP_WR_E1H, QM_REG_VOQQMASK_5_MSB, 0x1e001e00},
1524 {OP_WR_E1, QM_REG_VOQQMASK_8_LSB, 0x2000},
1525 {OP_WR_E1H, QM_REG_VOQQMASK_5_LSB_EXT_A, 0x1e001e00},
1526 {OP_WR_E1, QM_REG_VOQQMASK_8_MSB, 0x2000},
1527 {OP_WR_E1H, QM_REG_VOQQMASK_5_MSB_EXT_A, 0x1e001e00},
1528 {OP_ZR_E1, QM_REG_VOQQMASK_9_LSB, 0x7},
1529 {OP_WR_E1H, QM_REG_VOQQMASK_6_LSB, 0x40004000},
1530 {OP_WR_E1H, QM_REG_VOQQMASK_6_MSB, 0x40004000},
1531 {OP_WR_E1H, QM_REG_VOQQMASK_6_LSB_EXT_A, 0x40004000},
1532 {OP_WR_E1H, QM_REG_VOQQMASK_6_MSB_EXT_A, 0x40004000},
1533 {OP_WR_E1H, QM_REG_VOQQMASK_7_LSB, 0x80008000},
1534 {OP_WR_E1H, QM_REG_VOQQMASK_7_MSB, 0x80008000},
1535 {OP_WR_E1H, QM_REG_VOQQMASK_7_LSB_EXT_A, 0x80008000},
1536 {OP_WR_E1H, QM_REG_VOQQMASK_7_MSB_EXT_A, 0x80008000},
1537 {OP_WR_E1H, QM_REG_VOQQMASK_8_LSB, 0x20002000},
1538 {OP_WR_E1H, QM_REG_VOQQMASK_8_MSB, 0x20002000},
1539 {OP_WR_E1H, QM_REG_VOQQMASK_8_LSB_EXT_A, 0x20002000},
1540 {OP_WR_E1H, QM_REG_VOQQMASK_8_MSB_EXT_A, 0x20002000},
1541 {OP_ZR_E1H, QM_REG_VOQQMASK_9_LSB, 0x2},
1542 {OP_WR_E1H, QM_REG_VOQQMASK_9_LSB_EXT_A, 0x0},
1543 {OP_WR_E1H, QM_REG_VOQQMASK_9_MSB_EXT_A, 0x0},
1544 {OP_WR_E1H, QM_REG_VOQQMASK_10_LSB, 0x0},
1545 {OP_WR_E1H, QM_REG_VOQQMASK_10_MSB, 0x0},
1546 {OP_WR_E1H, QM_REG_VOQQMASK_10_LSB_EXT_A, 0x0},
1547 {OP_WR_E1H, QM_REG_VOQQMASK_10_MSB_EXT_A, 0x0},
1548 {OP_WR_E1H, QM_REG_VOQQMASK_11_LSB, 0x0},
1549 {OP_WR_E1H, QM_REG_VOQQMASK_11_MSB, 0x0},
1550 {OP_WR_E1H, QM_REG_VOQQMASK_11_LSB_EXT_A, 0x0},
1551 {OP_WR_E1H, QM_REG_VOQQMASK_11_MSB_EXT_A, 0x0},
1552 {OP_WR_E1H, QM_REG_VOQPORT_0, 0x0},
1553 {OP_WR, QM_REG_VOQPORT_1, 0x1},
1554 {OP_ZR, QM_REG_VOQPORT_2, 0xa},
1555 {OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
1556 {OP_WR, QM_REG_CMINTVOQMASK_1, 0x40},
1557 {OP_WR, QM_REG_CMINTVOQMASK_2, 0x100},
1558 {OP_WR, QM_REG_CMINTVOQMASK_3, 0x20},
1559 {OP_WR, QM_REG_CMINTVOQMASK_4, 0x17},
1560 {OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
1561 {OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
1562 {OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
1563 {OP_WR_E1, QM_REG_HWAEMPTYMASK_LSB, 0xffff01ff},
1564 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_LSB, 0x1ff01ff},
1565 {OP_WR_E1, QM_REG_HWAEMPTYMASK_MSB, 0xffff01ff},
1566 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_MSB, 0x1ff01ff},
1567 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_LSB_EXT_A, 0x1ff01ff},
1568 {OP_WR_E1H, QM_REG_HWAEMPTYMASK_MSB_EXT_A, 0x1ff01ff},
1569 {OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
1570 {OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
1571 {OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
1572 {OP_WR, QM_REG_VOQINITCREDIT_1, 0x140},
1573 {OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2},
1574 {OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0},
1575 {OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7},
1576 {OP_WR, QM_REG_TASKCRDCOST_0, 0x48},
1577 {OP_WR, QM_REG_TASKCRDCOST_1, 0x48},
1578 {OP_ZR, QM_REG_TASKCRDCOST_2, 0x2},
1579 {OP_WR, QM_REG_TASKCRDCOST_4, 0x48},
1580 {OP_ZR, QM_REG_TASKCRDCOST_5, 0x7},
1581 {OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
1582 {OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
1583 {OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
1584 {OP_WR_E1, QM_REG_ENBYTECRD_LSB, 0x7},
1585 {OP_WR_E1H, QM_REG_ENBYTECRD_LSB, 0x70007},
1586 {OP_WR_E1, QM_REG_ENBYTECRD_MSB, 0x7},
1587 {OP_WR_E1H, QM_REG_ENBYTECRD_MSB, 0x70007},
1588 {OP_WR_E1H, QM_REG_ENBYTECRD_LSB_EXT_A, 0x70007},
1589 {OP_WR_E1H, QM_REG_ENBYTECRD_MSB_EXT_A, 0x70007},
1590 {OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
1591 {OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
1592 {OP_WR_E1, QM_REG_FUNCNUMSEL_LSB, 0x0},
1593 {OP_WR_E1H, QM_REG_BYTECRDPORT_LSB_EXT_A, 0x0},
1594 {OP_WR_E1, QM_REG_FUNCNUMSEL_MSB, 0xffffffff},
1595 {OP_WR_E1H, QM_REG_BYTECRDPORT_MSB_EXT_A, 0xffffffff},
1596 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_0, 0x0},
1597 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_1, 0x2},
1598 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_2, 0x1},
1599 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_3, 0x3},
1600 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_4, 0x4},
1601 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_5, 0x6},
1602 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_6, 0x5},
1603 {OP_WR_E1H, QM_REG_PQ2PCIFUNC_7, 0x7},
1604 {OP_WR, QM_REG_CMINTEN, 0xff},
1605 #define QM_COMMON_END 1400
1606 #define PBF_COMMON_START 1400
1607 {OP_WR, PBF_REG_INIT, 0x1},
1608 {OP_WR, PBF_REG_INIT_P4, 0x1},
1609 {OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
1610 {OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff},
1611 {OP_WR, PBF_REG_INIT_P4, 0x0},
1612 {OP_WR, PBF_REG_INIT, 0x0},
1613 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
1614 #define PBF_COMMON_END 1407
1615 #define PBF_PORT0_START 1407
1616 {OP_WR, PBF_REG_INIT_P0, 0x1},
1617 {OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
1618 {OP_WR, PBF_REG_INIT_P0, 0x0},
1619 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
1620 #define PBF_PORT0_END 1411
1621 #define PBF_PORT1_START 1411
1622 {OP_WR, PBF_REG_INIT_P1, 0x1},
1623 {OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
1624 {OP_WR, PBF_REG_INIT_P1, 0x0},
1625 {OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
1626 #define PBF_PORT1_END 1415
1627 #define XCM_COMMON_START 1415
1628 {OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
1629 {OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
1630 {OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
1631 {OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030},
1632 {OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000},
1633 {OP_WR, XCM_REG_ERR_EVNT_ID, 0x33},
1634 {OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30},
1635 {OP_WR, XCM_REG_STOP_EVNT_ID, 0x31},
1636 {OP_WR, XCM_REG_STORM_WEIGHT, 0x2},
1637 {OP_WR, XCM_REG_TSEM_WEIGHT, 0x5},
1638 {OP_WR, XCM_REG_CSEM_WEIGHT, 0x2},
1639 {OP_WR, XCM_REG_USEM_WEIGHT, 0x2},
1640 {OP_WR, XCM_REG_PBF_WEIGHT, 0x7},
1641 {OP_WR, XCM_REG_NIG1_WEIGHT, 0x1},
1642 {OP_WR, XCM_REG_CP_WEIGHT, 0x0},
1643 {OP_WR, XCM_REG_XSDM_WEIGHT, 0x5},
1644 {OP_WR, XCM_REG_XQM_P_WEIGHT, 0x3},
1645 {OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1},
1646 {OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6},
1647 {OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0},
1648 {OP_WR, XCM_REG_AUX1_Q, 0x2},
1649 {OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1},
1650 {OP_WR, XCM_REG_GR_ARB_TYPE, 0x1},
1651 {OP_WR, XCM_REG_GR_LD0_PR, 0x1},
1652 {OP_WR, XCM_REG_GR_LD1_PR, 0x2},
1653 {OP_WR, XCM_REG_CFC_INIT_CRD, 0x1},
1654 {OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40},
1655 {OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40},
1656 {OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
1657 {OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
1658 {OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
1659 {OP_WR_E1, XCM_REG_XX_MSG_NUM, 0x1f},
1660 {OP_WR_E1H, XCM_REG_XX_MSG_NUM, 0x20},
1661 {OP_ZR, XCM_REG_XX_TABLE, 0x12},
1662 {OP_SW_E1, XCM_REG_XX_DESCR_TABLE, 0x1f02ce},
1663 {OP_SW_E1H, XCM_REG_XX_DESCR_TABLE, 0x1f0302},
1664 {OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
1665 {OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
1666 {OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
1667 {OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
1668 {OP_ZR_E1, XCM_REG_N_SM_CTX_LD_4, 0x4},
1669 {OP_WR_E1H, XCM_REG_N_SM_CTX_LD_4, 0xc},
1670 {OP_ZR_E1H, XCM_REG_N_SM_CTX_LD_5, 0x3},
1671 {OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
1672 {OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
1673 {OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
1674 {OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1},
1675 {OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1},
1676 {OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1},
1677 {OP_WR, XCM_REG_XSDM_IFEN, 0x1},
1678 {OP_WR, XCM_REG_TM_XCM_IFEN, 0x1},
1679 {OP_WR, XCM_REG_XCM_TM_IFEN, 0x1},
1680 {OP_WR, XCM_REG_TSEM_IFEN, 0x1},
1681 {OP_WR, XCM_REG_CSEM_IFEN, 0x1},
1682 {OP_WR, XCM_REG_USEM_IFEN, 0x1},
1683 {OP_WR, XCM_REG_DORQ_IFEN, 0x1},
1684 {OP_WR, XCM_REG_PBF_IFEN, 0x1},
1685 {OP_WR, XCM_REG_NIG0_IFEN, 0x1},
1686 {OP_WR, XCM_REG_NIG1_IFEN, 0x1},
1687 {OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1},
1688 {OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1},
1689 {OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
1690 {OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
1691 {OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
1692 #define XCM_COMMON_END 1479
1693 #define XCM_PORT0_START 1479
1694 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1695 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1696 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1697 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1698 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1699 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1700 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1701 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1702 #define XCM_PORT0_END 1487
1703 #define XCM_PORT1_START 1487
1704 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1705 {OP_WR_E1, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1706 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1707 {OP_WR_E1, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1708 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1709 {OP_WR_E1, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1710 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1711 {OP_WR_E1, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1712 #define XCM_PORT1_END 1495
1713 #define XCM_FUNC0_START 1495
1714 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1715 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1716 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1717 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1718 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1719 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1720 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1721 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1722 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1723 #define XCM_FUNC0_END 1504
1724 #define XCM_FUNC1_START 1504
1725 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1726 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1727 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1728 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1729 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1730 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1731 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1732 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1733 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1734 #define XCM_FUNC1_END 1513
1735 #define XCM_FUNC2_START 1513
1736 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1737 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1738 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1739 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1740 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1741 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1742 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1743 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1744 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1745 #define XCM_FUNC2_END 1522
1746 #define XCM_FUNC3_START 1522
1747 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1748 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1749 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1750 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1751 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1752 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1753 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1754 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1755 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1756 #define XCM_FUNC3_END 1531
1757 #define XCM_FUNC4_START 1531
1758 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1759 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1760 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1761 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1762 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1763 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1764 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1765 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1766 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1767 #define XCM_FUNC4_END 1540
1768 #define XCM_FUNC5_START 1540
1769 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1770 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1771 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1772 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1773 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1774 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1775 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1776 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1777 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1778 #define XCM_FUNC5_END 1549
1779 #define XCM_FUNC6_START 1549
1780 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
1781 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
1782 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
1783 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
1784 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD00, 0x2},
1785 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD10, 0x2},
1786 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
1787 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
1788 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_0, 0x0},
1789 #define XCM_FUNC6_END 1558
1790 #define XCM_FUNC7_START 1558
1791 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
1792 {OP_WR_E1H, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
1793 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
1794 {OP_WR_E1H, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
1795 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD01, 0x2},
1796 {OP_WR_E1H, XCM_REG_WU_DA_CNT_CMD11, 0x2},
1797 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
1798 {OP_WR_E1H, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
1799 {OP_WR_E1H, XCM_REG_PHYS_QNUM3_1, 0x0},
1800 #define XCM_FUNC7_END 1567
1801 #define XSEM_COMMON_START 1567
1802 {OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
1803 {OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
1804 {OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
1805 {OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0},
1806 {OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0},
1807 {OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0},
1808 {OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1},
1809 {OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2},
1810 {OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3},
1811 {OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0},
1812 {OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4},
1813 {OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1},
1814 {OP_WR, XSEM_REG_TS_0_AS, 0x0},
1815 {OP_WR, XSEM_REG_TS_1_AS, 0x1},
1816 {OP_WR, XSEM_REG_TS_2_AS, 0x4},
1817 {OP_WR, XSEM_REG_TS_3_AS, 0x0},
1818 {OP_WR, XSEM_REG_TS_4_AS, 0x1},
1819 {OP_WR, XSEM_REG_TS_5_AS, 0x3},
1820 {OP_WR, XSEM_REG_TS_6_AS, 0x0},
1821 {OP_WR, XSEM_REG_TS_7_AS, 0x1},
1822 {OP_WR, XSEM_REG_TS_8_AS, 0x4},
1823 {OP_WR, XSEM_REG_TS_9_AS, 0x0},
1824 {OP_WR, XSEM_REG_TS_10_AS, 0x1},
1825 {OP_WR, XSEM_REG_TS_11_AS, 0x3},
1826 {OP_WR, XSEM_REG_TS_12_AS, 0x0},
1827 {OP_WR, XSEM_REG_TS_13_AS, 0x1},
1828 {OP_WR, XSEM_REG_TS_14_AS, 0x4},
1829 {OP_WR, XSEM_REG_TS_15_AS, 0x0},
1830 {OP_WR, XSEM_REG_TS_16_AS, 0x4},
1831 {OP_WR, XSEM_REG_TS_17_AS, 0x3},
1832 {OP_ZR, XSEM_REG_TS_18_AS, 0x2},
1833 {OP_WR, XSEM_REG_ENABLE_IN, 0x3fff},
1834 {OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff},
1835 {OP_WR, XSEM_REG_FIC0_DISABLE, 0x0},
1836 {OP_WR, XSEM_REG_FIC1_DISABLE, 0x0},
1837 {OP_WR, XSEM_REG_PAS_DISABLE, 0x0},
1838 {OP_WR, XSEM_REG_THREADS_LIST, 0xffff},
1839 {OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800},
1840 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
1841 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0},
1842 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
1843 {OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
1844 {OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
1845 {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
1846 {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138},
1847 {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
1848 {OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
1849 {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
1850 {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0},
1851 {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5},
1852 {OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
1853 {OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
1854 {OP_WR_EMUL_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x0},
1855 {OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
1856 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3d00, 0x4},
1857 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x11480, 0x1},
1858 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3000, 0x48},
1859 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x28a8, 0x4},
1860 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1020, 0xc8},
1861 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2080, 0x48},
1862 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1000, 0x2},
1863 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9020, 0xc8},
1864 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3128, 0x8e},
1865 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
1866 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3368, 0x0},
1867 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
1868 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3370, 0x202ed},
1869 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
1870 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3b90, 0x402ef},
1871 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
1872 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1518, 0x1},
1873 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x23d0, 0x20321},
1874 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1830, 0x0},
1875 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2498, 0x40323},
1876 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1838, 0x0},
1877 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ac8, 0x0},
1878 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1820, 0x202f3},
1879 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x2ab8, 0x0},
1880 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4ac0, 0x2},
1881 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3010, 0x1},
1882 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b00, 0x4},
1883 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
1884 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x1f50, 0x202f5},
1885 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x4000, 0x100327},
1886 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
1887 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
1888 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x83b0, 0x20337},
1889 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
1890 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c00, 0x1002f7},
1891 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c00, 0x100339},
1892 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
1893 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80307},
1894 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c40, 0x80349},
1895 {OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
1896 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x10c60, 0x8030f},
1897 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80351},
1898 {OP_ZP_E1, XSEM_REG_INT_TABLE, 0xab0000},
1899 {OP_ZP_E1H, XSEM_REG_INT_TABLE, 0xac0000},
1900 {OP_WR_64_E1, XSEM_REG_INT_TABLE + 0x368, 0x130317},
1901 {OP_WR_64_E1H, XSEM_REG_INT_TABLE + 0x368, 0x130359},
1902 {OP_ZP_E1, XSEM_REG_PRAM, 0xc09e0000},
1903 {OP_ZP_E1H, XSEM_REG_PRAM, 0xc3b20000},
1904 {OP_WR_64_E1, XSEM_REG_PRAM + 0x1c0c0, 0x47e80319},
1905 {OP_WR_64_E1H, XSEM_REG_PRAM + 0x1c8c0, 0x46e8035b},
1906 #define XSEM_COMMON_END 1671
1907 #define XSEM_PORT0_START 1671
1908 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3ba0, 0x10},
1909 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc000, 0xfc},
1910 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c20, 0x1c},
1911 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24a8, 0x10},
1912 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1400, 0xa},
1913 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2528, 0x1c},
1914 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1450, 0x6},
1915 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2608, 0x1c},
1916 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3378, 0xfc},
1917 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x26e8, 0x1c},
1918 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b58, 0x0},
1919 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x27c8, 0x1c},
1920 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d10, 0x10031b},
1921 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
1922 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1500, 0x0},
1923 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
1924 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1508, 0x1},
1925 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3000, 0x1},
1926 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2},
1927 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2},
1928 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2},
1929 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2},
1930 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5040, 0x0},
1931 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x5208, 0x1},
1932 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
1933 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x2035d},
1934 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50b8, 0x1},
1935 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
1936 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ac8, 0x2032b},
1937 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
1938 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4b10, 0x42},
1939 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d20, 0x4},
1940 #define XSEM_PORT0_END 1703
1941 #define XSEM_PORT1_START 1703
1942 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3be0, 0x10},
1943 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xc3f0, 0xfc},
1944 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3c90, 0x1c},
1945 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x24e8, 0x10},
1946 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1428, 0xa},
1947 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2598, 0x1c},
1948 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x1468, 0x6},
1949 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2678, 0x1c},
1950 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x3768, 0xfc},
1951 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2758, 0x1c},
1952 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x3b5c, 0x0},
1953 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x2838, 0x1c},
1954 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x3d50, 0x10032d},
1955 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
1956 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x1504, 0x0},
1957 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
1958 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x150c, 0x1},
1959 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x3004, 0x1},
1960 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2},
1961 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2},
1962 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2},
1963 {OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2},
1964 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x5044, 0x0},
1965 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0x520c, 0x1},
1966 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
1967 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x2035f},
1968 {OP_WR_E1, XSEM_REG_FAST_MEMORY + 0x50bc, 0x1},
1969 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
1970 {OP_SW_E1, XSEM_REG_FAST_MEMORY + 0x4ad0, 0x2033d},
1971 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
1972 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4c18, 0x42},
1973 {OP_ZR_E1, XSEM_REG_FAST_MEMORY + 0x4d30, 0x4},
1974 #define XSEM_PORT1_END 1735
1975 #define XSEM_FUNC0_START 1735
1976 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e0, 0x0},
1977 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28b8, 0x100361},
1978 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
1979 #define XSEM_FUNC0_END 1738
1980 #define XSEM_FUNC1_START 1738
1981 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e4, 0x0},
1982 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x28f8, 0x100371},
1983 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
1984 #define XSEM_FUNC1_END 1741
1985 #define XSEM_FUNC2_START 1741
1986 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7e8, 0x0},
1987 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2938, 0x100381},
1988 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
1989 #define XSEM_FUNC2_END 1744
1990 #define XSEM_FUNC3_START 1744
1991 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7ec, 0x0},
1992 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2978, 0x100391},
1993 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
1994 #define XSEM_FUNC3_END 1747
1995 #define XSEM_FUNC4_START 1747
1996 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f0, 0x0},
1997 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29b8, 0x1003a1},
1998 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
1999 #define XSEM_FUNC4_END 1750
2000 #define XSEM_FUNC5_START 1750
2001 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f4, 0x0},
2002 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x29f8, 0x1003b1},
2003 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
2004 #define XSEM_FUNC5_END 1753
2005 #define XSEM_FUNC6_START 1753
2006 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7f8, 0x0},
2007 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a38, 0x1003c1},
2008 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
2009 #define XSEM_FUNC6_END 1756
2010 #define XSEM_FUNC7_START 1756
2011 {OP_WR_E1H, XSEM_REG_FAST_MEMORY + 0xc7fc, 0x0},
2012 {OP_SW_E1H, XSEM_REG_FAST_MEMORY + 0x2a78, 0x1003d1},
2013 {OP_ZR_E1H, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
2014 #define XSEM_FUNC7_END 1759
2015 #define CDU_COMMON_START 1759
2016 {OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
2017 {OP_WR_E1H, CDU_REG_MF_MODE, 0x1},
2018 {OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
2019 {OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
2020 {OP_WB_E1, CDU_REG_L1TT, 0x200033f},
2021 {OP_WB_E1H, CDU_REG_L1TT, 0x20003e1},
2022 {OP_WB_E1, CDU_REG_MATT, 0x20053f},
2023 {OP_WB_E1H, CDU_REG_MATT, 0x2805e1},
2024 {OP_ZR_E1, CDU_REG_MATT + 0x80, 0x2},
2025 {OP_WB_E1, CDU_REG_MATT + 0x88, 0x6055f},
2026 {OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
2027 #define CDU_COMMON_END 1770
2028 #define DMAE_COMMON_START 1770
2029 {OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
2030 {OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
2031 {OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
2032 {OP_WR_E1, DMAE_REG_PXP_REQ_INIT_CRD, 0x1},
2033 {OP_WR_E1H, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
2034 {OP_WR, DMAE_REG_PCI_IFEN, 0x1},
2035 {OP_WR, DMAE_REG_GRC_IFEN, 0x1},
2036 #define DMAE_COMMON_END 1777
2037 #define PXP_COMMON_START 1777
2038 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x400, 0x50565},
2039 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT + 0x400, 0x50609},
2040 {OP_WB_E1, PXP_REG_HST_INBOUND_INT + 0x420, 0x5056a},
2041 {OP_WB_E1H, PXP_REG_HST_INBOUND_INT, 0x5060e},
2042 {OP_WB_E1, PXP_REG_HST_INBOUND_INT, 0x5056f},
2043 #define PXP_COMMON_END 1782
2044 #define CFC_COMMON_START 1782
2045 {OP_ZR_E1H, CFC_REG_LINK_LIST, 0x100},
2046 {OP_WR, CFC_REG_CONTROL0, 0x10},
2047 {OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
2048 {OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
2049 #define CFC_COMMON_END 1786
2050 #define HC_COMMON_START 1786
2051 {OP_ZR_E1, HC_REG_USTORM_ADDR_FOR_COALESCE, 0x4},
2052 #define HC_COMMON_END 1787
2053 #define HC_PORT0_START 1787
2054 {OP_WR_E1, HC_REG_CONFIG_0, 0x1080},
2055 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_0, 0x2},
2056 {OP_WR_E1, HC_REG_ATTN_NUM_P0, 0x10},
2057 {OP_WR_E1, HC_REG_LEADING_EDGE_0, 0xffff},
2058 {OP_WR_E1, HC_REG_TRAILING_EDGE_0, 0xffff},
2059 {OP_WR_E1, HC_REG_AGG_INT_0, 0x0},
2060 {OP_WR_E1, HC_REG_ATTN_IDX, 0x0},
2061 {OP_ZR_E1, HC_REG_ATTN_BIT, 0x2},
2062 {OP_WR_E1, HC_REG_VQID_0, 0x2b5},
2063 {OP_WR_E1, HC_REG_PCI_CONFIG_0, 0x0},
2064 {OP_ZR_E1, HC_REG_P0_PROD_CONS, 0x4a},
2065 {OP_WR_E1, HC_REG_INT_MASK, 0x1ffff},
2066 {OP_ZR_E1, HC_REG_PBA_COMMAND, 0x2},
2067 {OP_WR_E1, HC_REG_CONFIG_0, 0x1a80},
2068 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS, 0x24},
2069 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2070 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2071 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2072 {OP_ZR_E1, HC_REG_PBA_COMMAND, 0x2},
2073 #define HC_PORT0_END 1806
2074 #define HC_PORT1_START 1806
2075 {OP_WR_E1, HC_REG_CONFIG_1, 0x1080},
2076 {OP_ZR_E1, HC_REG_UC_RAM_ADDR_1, 0x2},
2077 {OP_WR_E1, HC_REG_ATTN_NUM_P1, 0x10},
2078 {OP_WR_E1, HC_REG_LEADING_EDGE_1, 0xffff},
2079 {OP_WR_E1, HC_REG_TRAILING_EDGE_1, 0xffff},
2080 {OP_WR_E1, HC_REG_AGG_INT_1, 0x0},
2081 {OP_WR_E1, HC_REG_ATTN_IDX + 0x4, 0x0},
2082 {OP_ZR_E1, HC_REG_ATTN_BIT + 0x8, 0x2},
2083 {OP_WR_E1, HC_REG_VQID_1, 0x2b5},
2084 {OP_WR_E1, HC_REG_PCI_CONFIG_1, 0x0},
2085 {OP_ZR_E1, HC_REG_P1_PROD_CONS, 0x4a},
2086 {OP_WR_E1, HC_REG_INT_MASK + 0x4, 0x1ffff},
2087 {OP_ZR_E1, HC_REG_PBA_COMMAND + 0x8, 0x2},
2088 {OP_WR_E1, HC_REG_CONFIG_1, 0x1a80},
2089 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2090 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2091 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2092 {OP_ZR_E1, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2093 {OP_ZR_E1, HC_REG_PBA_COMMAND + 0x8, 0x2},
2094 #define HC_PORT1_END 1825
2095 #define HC_FUNC0_START 1825
2096 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2097 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x0},
2098 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2099 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2100 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2101 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2102 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2103 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2104 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2105 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2106 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2107 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2108 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2109 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2110 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2111 #define HC_FUNC0_END 1840
2112 #define HC_FUNC1_START 1840
2113 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2114 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x1},
2115 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2116 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2117 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2118 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2119 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2120 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2121 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2122 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2123 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2124 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2125 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2126 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2127 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2128 #define HC_FUNC1_END 1855
2129 #define HC_FUNC2_START 1855
2130 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2131 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x2},
2132 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2133 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2134 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2135 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2136 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2137 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2138 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2139 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2140 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2141 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2142 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2143 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2144 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2145 #define HC_FUNC2_END 1870
2146 #define HC_FUNC3_START 1870
2147 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2148 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x3},
2149 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2150 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2151 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2152 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2153 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2154 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2155 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2156 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2157 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2158 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2159 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2160 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2161 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2162 #define HC_FUNC3_END 1885
2163 #define HC_FUNC4_START 1885
2164 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2165 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x4},
2166 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2167 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2168 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2169 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2170 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2171 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2172 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2173 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2174 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2175 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2176 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2177 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2178 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2179 #define HC_FUNC4_END 1900
2180 #define HC_FUNC5_START 1900
2181 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2182 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x5},
2183 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2184 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2185 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2186 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2187 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2188 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2189 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2190 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2191 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2192 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2193 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2194 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2195 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2196 #define HC_FUNC5_END 1915
2197 #define HC_FUNC6_START 1915
2198 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1080},
2199 {OP_WR_E1H, HC_REG_FUNC_NUM_P0, 0x6},
2200 {OP_WR_E1H, HC_REG_ATTN_NUM_P0, 0x10},
2201 {OP_WR_E1H, HC_REG_ATTN_IDX, 0x0},
2202 {OP_ZR_E1H, HC_REG_ATTN_BIT, 0x2},
2203 {OP_WR_E1H, HC_REG_VQID_0, 0x2b5},
2204 {OP_WR_E1H, HC_REG_PCI_CONFIG_0, 0x0},
2205 {OP_ZR_E1H, HC_REG_P0_PROD_CONS, 0x4a},
2206 {OP_WR_E1H, HC_REG_INT_MASK, 0x1ffff},
2207 {OP_ZR_E1H, HC_REG_PBA_COMMAND, 0x2},
2208 {OP_WR_E1H, HC_REG_CONFIG_0, 0x1a80},
2209 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS, 0x24},
2210 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
2211 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
2212 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
2213 #define HC_FUNC6_END 1930
2214 #define HC_FUNC7_START 1930
2215 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1080},
2216 {OP_WR_E1H, HC_REG_FUNC_NUM_P1, 0x7},
2217 {OP_WR_E1H, HC_REG_ATTN_NUM_P1, 0x10},
2218 {OP_WR_E1H, HC_REG_ATTN_IDX + 0x4, 0x0},
2219 {OP_ZR_E1H, HC_REG_ATTN_BIT + 0x8, 0x2},
2220 {OP_WR_E1H, HC_REG_VQID_1, 0x2b5},
2221 {OP_WR_E1H, HC_REG_PCI_CONFIG_1, 0x0},
2222 {OP_ZR_E1H, HC_REG_P1_PROD_CONS, 0x4a},
2223 {OP_WR_E1H, HC_REG_INT_MASK + 0x4, 0x1ffff},
2224 {OP_ZR_E1H, HC_REG_PBA_COMMAND + 0x8, 0x2},
2225 {OP_WR_E1H, HC_REG_CONFIG_1, 0x1a80},
2226 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
2227 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
2228 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
2229 {OP_ZR_E1H, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
2230 #define HC_FUNC7_END 1945
2231 #define PXP2_COMMON_START 1945
2232 {OP_WR_E1, PXP2_REG_PGL_CONTROL0, 0xe38340},
2233 {OP_WR_E1H, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
2234 {OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
2235 {OP_WR_E1H, PXP2_REG_RQ_ELT_DISABLE, 0x1},
2236 {OP_WR_E1H, PXP2_REG_WR_REV_MODE, 0x0},
2237 {OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
2238 {OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
2239 {OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
2240 {OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff},
2241 {OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff},
2242 {OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff},
2243 {OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff},
2244 {OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff},
2245 {OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xffffffff},
2246 {OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff},
2247 {OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff},
2248 {OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff},
2249 {OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
2250 {OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
2251 {OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
2252 {OP_WR_E1H, PXP2_REG_PGL_INT_XSDM_1, 0xffffffff},
2253 {OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
2254 {OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
2255 {OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
2256 {OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff},
2257 {OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff},
2258 {OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff},
2259 {OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff},
2260 {OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff},
2261 {OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff},
2262 {OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff},
2263 {OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff},
2264 {OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
2265 {OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
2266 {OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
2267 {OP_WR_E1, PXP2_REG_PGL_INT_XSDM_0, 0xffff3330},
2268 {OP_WR_E1H, PXP2_REG_PGL_INT_XSDM_0, 0xff802000},
2269 {OP_WR_E1, PXP2_REG_PGL_INT_XSDM_1, 0xffff3340},
2270 {OP_WR_E1H, PXP2_REG_PGL_INT_USDM_0, 0xf0005000},
2271 {OP_WR_E1, PXP2_REG_PGL_INT_USDM_0, 0xf0003000},
2272 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
2273 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
2274 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8},
2275 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ11, 0x2},
2276 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4},
2277 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ18, 0x5},
2278 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
2279 {OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
2280 {OP_WR, PXP2_REG_RD_START_INIT, 0x1},
2281 {OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f},
2282 {OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
2283 {OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
2284 {OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
2285 {OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803},
2286 {OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40},
2287 {OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3},
2288 {OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803},
2289 {OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803},
2290 {OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803},
2291 {OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003},
2292 {OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803},
2293 {OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803},
2294 {OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3},
2295 {OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3},
2296 {OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3},
2297 {OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3},
2298 {OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3},
2299 {OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3},
2300 {OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3},
2301 {OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3},
2302 {OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3},
2303 {OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3},
2304 {OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3},
2305 {OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3},
2306 {OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3},
2307 {OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3},
2308 {OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3},
2309 {OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403},
2310 {OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f},
2311 {OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9},
2312 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19},
2313 {OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184},
2314 {OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183},
2315 {OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306},
2316 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19},
2317 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6},
2318 {OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306},
2319 {OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306},
2320 {OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306},
2321 {OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86},
2322 {OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306},
2323 {OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306},
2324 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6},
2325 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6},
2326 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6},
2327 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6},
2328 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6},
2329 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6},
2330 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6},
2331 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6},
2332 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6},
2333 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6},
2334 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6},
2335 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6},
2336 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6},
2337 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6},
2338 {OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6},
2339 {OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306},
2340 {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13},
2341 {OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6},
2342 {OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004},
2343 {OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
2344 {OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
2345 {OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
2346 {OP_WR_E1H, PXP2_REG_RQ_ILT_MODE, 0x1},
2347 {OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
2348 #define PXP2_COMMON_END 2061
2349 #define MISC_AEU_COMMON_START 2061
2350 {OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
2351 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
2352 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
2353 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
2354 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_NIG_0, 0xf0000000},
2355 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
2356 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
2357 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
2358 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_0, 0xf0000000},
2359 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
2360 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
2361 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
2362 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_NIG_1, 0xf0000000},
2363 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_PXP_1, 0x0},
2364 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_PXP_1, 0x10000},
2365 {OP_WR_E1H, MISC_REG_AEU_ENABLE3_PXP_1, 0x5014},
2366 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
2367 {OP_WR_E1H, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
2368 {OP_WR_E1H, MISC_REG_AEU_GENERAL_MASK, 0x3},
2369 #define MISC_AEU_COMMON_END 2080
2370 #define MISC_AEU_PORT0_START 2080
2371 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xbf5c0000},
2372 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
2373 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff51fef},
2374 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff55fff},
2375 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
2376 {OP_WR_E1, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0x500003e0},
2377 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0xf00003e0},
2378 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
2379 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
2380 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
2381 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
2382 {OP_ZR_E1, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x14},
2383 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x7},
2384 {OP_WR_E1, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
2385 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4, 0x400},
2386 {OP_WR_E1, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
2387 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5, 0x3},
2388 {OP_WR_E1, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
2389 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5, 0x1000},
2390 {OP_WR_E1, MISC_REG_AEU_ENABLE4_NIG_0, 0x0},
2391 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6, 0x3},
2392 {OP_WR_E1, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
2393 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6, 0x4000},
2394 {OP_WR_E1, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
2395 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7, 0x3},
2396 {OP_WR_E1, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
2397 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7, 0x10000},
2398 {OP_WR_E1, MISC_REG_AEU_ENABLE4_PXP_0, 0x0},
2399 {OP_ZR_E1H, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x4},
2400 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x0},
2401 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_0, 0x3},
2402 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_0, 0x7},
2403 #define MISC_AEU_PORT0_END 2112
2404 #define MISC_AEU_PORT1_START 2112
2405 {OP_WR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xbf5c0000},
2406 {OP_WR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
2407 {OP_WR_E1, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff51fef},
2408 {OP_WR_E1H, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff55fff},
2409 {OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
2410 {OP_WR_E1, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0x500003e0},
2411 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0xf00003e0},
2412 {OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
2413 {OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
2414 {OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
2415 {OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
2416 {OP_ZR_E1, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x14},
2417 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x7},
2418 {OP_WR_E1, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
2419 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4, 0x800},
2420 {OP_WR_E1, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
2421 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5, 0x3},
2422 {OP_WR_E1, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
2423 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5, 0x2000},
2424 {OP_WR_E1, MISC_REG_AEU_ENABLE4_NIG_1, 0x0},
2425 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6, 0x3},
2426 {OP_WR_E1, MISC_REG_AEU_ENABLE1_PXP_1, 0x55540000},
2427 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6, 0x8000},
2428 {OP_WR_E1, MISC_REG_AEU_ENABLE2_PXP_1, 0x55555555},
2429 {OP_ZR_E1H, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7, 0x3},
2430 {OP_WR_E1, MISC_REG_AEU_ENABLE3_PXP_1, 0x5555},
2431 {OP_WR_E1H, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7, 0x20000},
2432 {OP_WR_E1, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
2433 {OP_ZR_E1H, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x4},
2434 {OP_WR_E1, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x0},
2435 {OP_ZR_E1, MISC_REG_AEU_INVERTER_2_FUNC_1, 0x3},
2436 {OP_WR_E1, MISC_REG_AEU_MASK_ATTN_FUNC_1, 0x7},
2437 #define MISC_AEU_PORT1_END 2144
2441 static const u32 init_data_e1[] = {
2442 0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
2443 0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
2444 0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
2445 0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
2446 0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
2447 0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
2448 0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
2449 0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
2450 0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
2451 0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
2452 0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
2453 0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
2454 0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
2455 0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
2456 0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
2457 0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
2458 0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
2459 0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
2460 0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
2461 0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
2462 0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
2463 0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
2464 0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
2465 0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
2466 0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
2467 0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
2468 0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
2469 0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
2470 0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
2471 0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
2472 0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
2473 0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
2474 0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
2475 0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
2476 0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
2477 0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
2478 0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
2479 0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
2480 0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
2481 0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
2482 0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
2483 0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
2484 0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
2485 0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
2486 0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
2487 0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
2488 0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
2489 0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
2490 0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
2491 0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
2492 0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
2493 0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
2494 0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
2495 0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
2496 0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
2497 0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
2498 0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
2499 0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
2500 0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
2501 0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
2502 0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
2503 0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
2504 0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
2505 0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
2506 0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
2507 0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
2508 0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
2509 0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
2510 0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
2511 0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
2512 0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
2513 0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
2514 0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
2515 0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
2516 0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
2517 0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
2518 0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
2519 0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
2520 0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
2521 0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
2522 0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
2523 0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
2524 0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
2525 0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
2526 0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
2527 0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
2528 0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
2529 0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
2530 0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
2531 0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
2532 0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff
2535 static const u32 init_data_e1h[] = {
2538 static const u32 tsem_int_table_data_e1[] = {
2541 static const u32 tsem_pram_data_e1[] = {
2544 static const u32 usem_int_table_data_e1[] = {
2547 static const u32 usem_pram_data_e1[] = {
2550 static const u32 csem_int_table_data_e1[] = {
2553 static const u32 csem_pram_data_e1[] = {
2556 static const u32 xsem_int_table_data_e1[] = {
2559 static const u32 xsem_pram_data_e1[] = {
2562 static const u32 tsem_int_table_data_e1h[] = {
2565 static const u32 tsem_pram_data_e1h[] = {
2568 static const u32 usem_int_table_data_e1h[] = {
2571 static const u32 usem_pram_data_e1h[] = {
2574 static const u32 csem_int_table_data_e1h[] = {
2577 static const u32 csem_pram_data_e1h[] = {
2580 static const u32 xsem_int_table_data_e1h[] = {
2583 static const u32 xsem_pram_data_e1h[] = {
2586 #endif /*__BNX2X_INIT_VALUES_H__*/
git.openpandora.org / pandora-kernel.git / blob