1 /* bnx2x_reg.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * The registers description starts with the register Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
14 * ST - Statistics register (clear on read)
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
24 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
25 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
26 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
27 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
28 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
29 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
30 /* [RW 1] Initiate the ATC array - reset all the valid bits */
31 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
32 /* [R 1] ATC initalization done */
33 #define ATC_REG_ATC_INIT_DONE 0x1100bc
34 /* [RC 6] Interrupt register #0 read clear */
35 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
36 /* [RW 19] Interrupt mask register #0 read/write */
37 #define BRB1_REG_BRB1_INT_MASK 0x60128
38 /* [R 19] Interrupt register #0 read */
39 #define BRB1_REG_BRB1_INT_STS 0x6011c
40 /* [RW 4] Parity mask register #0 read/write */
41 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
42 /* [R 4] Parity register #0 read */
43 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
44 /* [RC 4] Parity register #0 read clear */
45 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
46 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
47 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
48 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
49 * following reset the first rbc access to this reg must be write; there can
50 * be no more rbc writes after the first one; there can be any number of rbc
51 * read following the first write; rbc access not following these rules will
52 * result in hang condition. */
53 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
54 /* [RW 10] The number of free blocks below which the full signal to class 0
56 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
57 /* [RW 10] The number of free blocks above which the full signal to class 0
59 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
60 /* [RW 10] The number of free blocks below which the full signal to class 1
62 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
63 /* [RW 10] The number of free blocks above which the full signal to class 1
65 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
66 /* [RW 10] The number of free blocks below which the full signal to the LB
68 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
69 /* [RW 10] The number of free blocks above which the full signal to the LB
70 * port is de-asserted */
71 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
72 /* [RW 10] The number of free blocks above which the High_llfc signal to
73 interface #n is de-asserted. */
74 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
75 /* [RW 10] The number of free blocks below which the High_llfc signal to
76 interface #n is asserted. */
77 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
78 /* [RW 23] LL RAM data. */
79 #define BRB1_REG_LL_RAM 0x61000
80 /* [RW 10] The number of free blocks above which the Low_llfc signal to
81 interface #n is de-asserted. */
82 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
83 /* [RW 10] The number of free blocks below which the Low_llfc signal to
84 interface #n is asserted. */
85 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
86 /* [RW 10] The number of blocks guarantied for the MAC port */
87 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8
88 #define BRB1_REG_MAC_GUARANTIED_1 0x60240
89 /* [R 24] The number of full blocks. */
90 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
91 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
93 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
94 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
95 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
96 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
98 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
99 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
100 /* [RW 10] The number of free blocks below which the pause signal to class 0
102 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
103 /* [RW 10] The number of free blocks above which the pause signal to class 0
105 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
106 /* [RW 10] The number of free blocks below which the pause signal to class 1
108 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
109 /* [RW 10] The number of free blocks above which the pause signal to class 1
111 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
112 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
113 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
114 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
115 /* [RW 10] Write client 0: Assert pause threshold. */
116 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
117 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
118 /* [R 24] The number of full blocks occupied by port. */
119 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
120 /* [RW 1] Reset the design by software. */
121 #define BRB1_REG_SOFT_RESET 0x600dc
122 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
123 #define CCM_REG_CAM_OCCUP 0xd0188
124 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
125 acknowledge output is deasserted; all other signals are treated as usual;
126 if 1 - normal activity. */
127 #define CCM_REG_CCM_CFC_IFEN 0xd003c
128 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
129 disregarded; valid is deasserted; all other signals are treated as usual;
130 if 1 - normal activity. */
131 #define CCM_REG_CCM_CQM_IFEN 0xd000c
132 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
133 Otherwise 0 is inserted. */
134 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
135 /* [RW 11] Interrupt mask register #0 read/write */
136 #define CCM_REG_CCM_INT_MASK 0xd01e4
137 /* [R 11] Interrupt register #0 read */
138 #define CCM_REG_CCM_INT_STS 0xd01d8
139 /* [RW 27] Parity mask register #0 read/write */
140 #define CCM_REG_CCM_PRTY_MASK 0xd01f4
141 /* [R 27] Parity register #0 read */
142 #define CCM_REG_CCM_PRTY_STS 0xd01e8
143 /* [RC 27] Parity register #0 read clear */
144 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
145 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
146 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
147 Is used to determine the number of the AG context REG-pairs written back;
148 when the input message Reg1WbFlg isn't set. */
149 #define CCM_REG_CCM_REG0_SZ 0xd00c4
150 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
151 disregarded; valid is deasserted; all other signals are treated as usual;
152 if 1 - normal activity. */
153 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
154 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
155 disregarded; valid is deasserted; all other signals are treated as usual;
156 if 1 - normal activity. */
157 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
158 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
159 disregarded; valid output is deasserted; all other signals are treated as
160 usual; if 1 - normal activity. */
161 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
162 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
163 are disregarded; all other signals are treated as usual; if 1 - normal
165 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
166 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
167 disregarded; valid output is deasserted; all other signals are treated as
168 usual; if 1 - normal activity. */
169 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
170 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
171 input is disregarded; all other signals are treated as usual; if 1 -
173 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
174 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
175 the initial credit value; read returns the current value of the credit
176 counter. Must be initialized to 1 at start-up. */
177 #define CCM_REG_CFC_INIT_CRD 0xd0204
178 /* [RW 2] Auxiliary counter flag Q number 1. */
179 #define CCM_REG_CNT_AUX1_Q 0xd00c8
180 /* [RW 2] Auxiliary counter flag Q number 2. */
181 #define CCM_REG_CNT_AUX2_Q 0xd00cc
182 /* [RW 28] The CM header value for QM request (primary). */
183 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
184 /* [RW 28] The CM header value for QM request (secondary). */
185 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
186 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
187 acknowledge output is deasserted; all other signals are treated as usual;
188 if 1 - normal activity. */
189 #define CCM_REG_CQM_CCM_IFEN 0xd0014
190 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
191 the initial credit value; read returns the current value of the credit
192 counter. Must be initialized to 32 at start-up. */
193 #define CCM_REG_CQM_INIT_CRD 0xd020c
194 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
195 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
196 prioritised); 2 stands for weight 2; tc. */
197 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
198 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
199 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
200 prioritised); 2 stands for weight 2; tc. */
201 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
202 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
203 acknowledge output is deasserted; all other signals are treated as usual;
204 if 1 - normal activity. */
205 #define CCM_REG_CSDM_IFEN 0xd0018
206 /* [RC 1] Set when the message length mismatch (relative to last indication)
207 at the SDM interface is detected. */
208 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
209 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
210 weight 8 (the most prioritised); 1 stands for weight 1(least
211 prioritised); 2 stands for weight 2; tc. */
212 #define CCM_REG_CSDM_WEIGHT 0xd00b4
213 /* [RW 28] The CM header for QM formatting in case of an error in the QM
215 #define CCM_REG_ERR_CCM_HDR 0xd0094
216 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
217 #define CCM_REG_ERR_EVNT_ID 0xd0098
218 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
219 writes the initial credit value; read returns the current value of the
220 credit counter. Must be initialized to 64 at start-up. */
221 #define CCM_REG_FIC0_INIT_CRD 0xd0210
222 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
223 writes the initial credit value; read returns the current value of the
224 credit counter. Must be initialized to 64 at start-up. */
225 #define CCM_REG_FIC1_INIT_CRD 0xd0214
226 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
227 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
228 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
229 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
230 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
231 #define CCM_REG_GR_ARB_TYPE 0xd015c
232 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
233 highest priority is 3. It is supposed; that the Store channel priority is
234 the compliment to 4 of the rest priorities - Aggregation channel; Load
235 (FIC0) channel and Load (FIC1). */
236 #define CCM_REG_GR_LD0_PR 0xd0164
237 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
238 highest priority is 3. It is supposed; that the Store channel priority is
239 the compliment to 4 of the rest priorities - Aggregation channel; Load
240 (FIC0) channel and Load (FIC1). */
241 #define CCM_REG_GR_LD1_PR 0xd0168
242 /* [RW 2] General flags index. */
243 #define CCM_REG_INV_DONE_Q 0xd0108
244 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
245 context and sent to STORM; for a specific connection type. The double
246 REG-pairs are used in order to align to STORM context row size of 128
247 bits. The offset of these data in the STORM context is always 0. Index
248 _(0..15) stands for the connection type (one of 16). */
249 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
250 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
251 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
252 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
253 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
254 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
255 acknowledge output is deasserted; all other signals are treated as usual;
256 if 1 - normal activity. */
257 #define CCM_REG_PBF_IFEN 0xd0028
258 /* [RC 1] Set when the message length mismatch (relative to last indication)
259 at the pbf interface is detected. */
260 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
261 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
262 weight 8 (the most prioritised); 1 stands for weight 1(least
263 prioritised); 2 stands for weight 2; tc. */
264 #define CCM_REG_PBF_WEIGHT 0xd00ac
265 #define CCM_REG_PHYS_QNUM1_0 0xd0134
266 #define CCM_REG_PHYS_QNUM1_1 0xd0138
267 #define CCM_REG_PHYS_QNUM2_0 0xd013c
268 #define CCM_REG_PHYS_QNUM2_1 0xd0140
269 #define CCM_REG_PHYS_QNUM3_0 0xd0144
270 #define CCM_REG_PHYS_QNUM3_1 0xd0148
271 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
272 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
273 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
274 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
275 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
276 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
277 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
278 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
279 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
280 disregarded; acknowledge output is deasserted; all other signals are
281 treated as usual; if 1 - normal activity. */
282 #define CCM_REG_STORM_CCM_IFEN 0xd0010
283 /* [RC 1] Set when the message length mismatch (relative to last indication)
284 at the STORM interface is detected. */
285 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
286 /* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
287 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
288 weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
290 #define CCM_REG_STORM_WEIGHT 0xd009c
291 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
292 disregarded; acknowledge output is deasserted; all other signals are
293 treated as usual; if 1 - normal activity. */
294 #define CCM_REG_TSEM_IFEN 0xd001c
295 /* [RC 1] Set when the message length mismatch (relative to last indication)
296 at the tsem interface is detected. */
297 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
298 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
299 weight 8 (the most prioritised); 1 stands for weight 1(least
300 prioritised); 2 stands for weight 2; tc. */
301 #define CCM_REG_TSEM_WEIGHT 0xd00a0
302 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
303 disregarded; acknowledge output is deasserted; all other signals are
304 treated as usual; if 1 - normal activity. */
305 #define CCM_REG_USEM_IFEN 0xd0024
306 /* [RC 1] Set when message length mismatch (relative to last indication) at
307 the usem interface is detected. */
308 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
309 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
310 weight 8 (the most prioritised); 1 stands for weight 1(least
311 prioritised); 2 stands for weight 2; tc. */
312 #define CCM_REG_USEM_WEIGHT 0xd00a8
313 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
314 disregarded; acknowledge output is deasserted; all other signals are
315 treated as usual; if 1 - normal activity. */
316 #define CCM_REG_XSEM_IFEN 0xd0020
317 /* [RC 1] Set when the message length mismatch (relative to last indication)
318 at the xsem interface is detected. */
319 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
320 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
321 weight 8 (the most prioritised); 1 stands for weight 1(least
322 prioritised); 2 stands for weight 2; tc. */
323 #define CCM_REG_XSEM_WEIGHT 0xd00a4
324 /* [RW 19] Indirect access to the descriptor table of the XX protection
325 mechanism. The fields are: [5:0] - message length; [12:6] - message
326 pointer; 18:13] - next pointer. */
327 #define CCM_REG_XX_DESCR_TABLE 0xd0300
328 #define CCM_REG_XX_DESCR_TABLE_SIZE 36
329 /* [R 7] Used to read the value of XX protection Free counter. */
330 #define CCM_REG_XX_FREE 0xd0184
331 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
332 of the Input Stage XX protection buffer by the XX protection pending
333 messages. Max credit available - 127. Write writes the initial credit
334 value; read returns the current value of the credit counter. Must be
335 initialized to maximum XX protected message size - 2 at start-up. */
336 #define CCM_REG_XX_INIT_CRD 0xd0220
337 /* [RW 7] The maximum number of pending messages; which may be stored in XX
338 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
339 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
341 #define CCM_REG_XX_MSG_NUM 0xd0224
342 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
343 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
344 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
345 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
347 #define CCM_REG_XX_TABLE 0xd0280
348 #define CDU_REG_CDU_CHK_MASK0 0x101000
349 #define CDU_REG_CDU_CHK_MASK1 0x101004
350 #define CDU_REG_CDU_CONTROL0 0x101008
351 #define CDU_REG_CDU_DEBUG 0x101010
352 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
353 /* [RW 7] Interrupt mask register #0 read/write */
354 #define CDU_REG_CDU_INT_MASK 0x10103c
355 /* [R 7] Interrupt register #0 read */
356 #define CDU_REG_CDU_INT_STS 0x101030
357 /* [RW 5] Parity mask register #0 read/write */
358 #define CDU_REG_CDU_PRTY_MASK 0x10104c
359 /* [R 5] Parity register #0 read */
360 #define CDU_REG_CDU_PRTY_STS 0x101040
361 /* [RC 5] Parity register #0 read clear */
362 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044
363 /* [RC 32] logging of error data in case of a CDU load error:
364 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
365 ype_error; ctual_active; ctual_compressed_context}; */
366 #define CDU_REG_ERROR_DATA 0x101014
367 /* [WB 216] L1TT ram access. each entry has the following format :
368 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
369 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
370 #define CDU_REG_L1TT 0x101800
371 /* [WB 24] MATT ram access. each entry has the following
372 format:{RegionLength[11:0]; egionOffset[11:0]} */
373 #define CDU_REG_MATT 0x101100
374 /* [RW 1] when this bit is set the CDU operates in e1hmf mode */
375 #define CDU_REG_MF_MODE 0x101050
376 /* [R 1] indication the initializing the activity counter by the hardware
378 #define CFC_REG_AC_INIT_DONE 0x104078
379 /* [RW 13] activity counter ram access */
380 #define CFC_REG_ACTIVITY_COUNTER 0x104400
381 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
382 /* [R 1] indication the initializing the cams by the hardware was done. */
383 #define CFC_REG_CAM_INIT_DONE 0x10407c
384 /* [RW 2] Interrupt mask register #0 read/write */
385 #define CFC_REG_CFC_INT_MASK 0x104108
386 /* [R 2] Interrupt register #0 read */
387 #define CFC_REG_CFC_INT_STS 0x1040fc
388 /* [RC 2] Interrupt register #0 read clear */
389 #define CFC_REG_CFC_INT_STS_CLR 0x104100
390 /* [RW 4] Parity mask register #0 read/write */
391 #define CFC_REG_CFC_PRTY_MASK 0x104118
392 /* [R 4] Parity register #0 read */
393 #define CFC_REG_CFC_PRTY_STS 0x10410c
394 /* [RC 4] Parity register #0 read clear */
395 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110
396 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
397 #define CFC_REG_CID_CAM 0x104800
398 #define CFC_REG_CONTROL0 0x104028
399 #define CFC_REG_DEBUG0 0x104050
400 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
401 vector) whether the cfc should be disabled upon it */
402 #define CFC_REG_DISABLE_ON_ERROR 0x104044
403 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
404 set one of these bits. the bit description can be found in CFC
406 #define CFC_REG_ERROR_VECTOR 0x10403c
407 /* [WB 93] LCID info ram access */
408 #define CFC_REG_INFO_RAM 0x105000
409 #define CFC_REG_INFO_RAM_SIZE 1024
410 #define CFC_REG_INIT_REG 0x10404c
411 #define CFC_REG_INTERFACES 0x104058
412 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
413 field allows changing the priorities of the weighted-round-robin arbiter
414 which selects which CFC load client should be served next */
415 #define CFC_REG_LCREQ_WEIGHTS 0x104084
416 /* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
417 #define CFC_REG_LINK_LIST 0x104c00
418 #define CFC_REG_LINK_LIST_SIZE 256
419 /* [R 1] indication the initializing the link list by the hardware was done. */
420 #define CFC_REG_LL_INIT_DONE 0x104074
421 /* [R 9] Number of allocated LCIDs which are at empty state */
422 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
423 /* [R 9] Number of Arriving LCIDs in Link List Block */
424 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
425 #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
426 /* [R 9] Number of Leaving LCIDs in Link List Block */
427 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
428 #define CFC_REG_WEAK_ENABLE_PF 0x104124
429 /* [RW 8] The event id for aggregated interrupt 0 */
430 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
431 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
432 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
433 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
434 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
435 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
436 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
437 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
438 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
439 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
440 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
441 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
442 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
443 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
444 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
445 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
446 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
447 or auto-mask-mode (1) */
448 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
449 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
450 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
451 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
452 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
453 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
454 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
455 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
456 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
457 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
458 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
459 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
460 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
461 /* [RW 16] The maximum value of the completion counter #0 */
462 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
463 /* [RW 16] The maximum value of the completion counter #1 */
464 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
465 /* [RW 16] The maximum value of the completion counter #2 */
466 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
467 /* [RW 16] The maximum value of the completion counter #3 */
468 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
469 /* [RW 13] The start address in the internal RAM for the completion
471 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
472 /* [RW 32] Interrupt mask register #0 read/write */
473 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
474 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
475 /* [R 32] Interrupt register #0 read */
476 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
477 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
478 /* [RW 11] Parity mask register #0 read/write */
479 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
480 /* [R 11] Parity register #0 read */
481 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
482 /* [RC 11] Parity register #0 read clear */
483 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
484 #define CSDM_REG_ENABLE_IN1 0xc2238
485 #define CSDM_REG_ENABLE_IN2 0xc223c
486 #define CSDM_REG_ENABLE_OUT1 0xc2240
487 #define CSDM_REG_ENABLE_OUT2 0xc2244
488 /* [RW 4] The initial number of messages that can be sent to the pxp control
489 interface without receiving any ACK. */
490 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
491 /* [ST 32] The number of ACK after placement messages received */
492 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
493 /* [ST 32] The number of packet end messages received from the parser */
494 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
495 /* [ST 32] The number of requests received from the pxp async if */
496 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
497 /* [ST 32] The number of commands received in queue 0 */
498 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
499 /* [ST 32] The number of commands received in queue 10 */
500 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
501 /* [ST 32] The number of commands received in queue 11 */
502 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
503 /* [ST 32] The number of commands received in queue 1 */
504 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
505 /* [ST 32] The number of commands received in queue 3 */
506 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
507 /* [ST 32] The number of commands received in queue 4 */
508 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
509 /* [ST 32] The number of commands received in queue 5 */
510 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
511 /* [ST 32] The number of commands received in queue 6 */
512 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
513 /* [ST 32] The number of commands received in queue 7 */
514 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
515 /* [ST 32] The number of commands received in queue 8 */
516 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
517 /* [ST 32] The number of commands received in queue 9 */
518 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
519 /* [RW 13] The start address in the internal RAM for queue counters */
520 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
521 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
522 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
523 /* [R 1] parser fifo empty in sdm_sync block */
524 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
525 /* [R 1] parser serial fifo empty in sdm_sync block */
526 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
527 /* [RW 32] Tick for timer counter. Applicable only when
528 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
529 #define CSDM_REG_TIMER_TICK 0xc2000
530 /* [RW 5] The number of time_slots in the arbitration cycle */
531 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
532 /* [RW 3] The source that is associated with arbitration element 0. Source
533 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
534 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
535 #define CSEM_REG_ARB_ELEMENT0 0x200020
536 /* [RW 3] The source that is associated with arbitration element 1. Source
537 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
538 sleeping thread with priority 1; 4- sleeping thread with priority 2.
539 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
540 #define CSEM_REG_ARB_ELEMENT1 0x200024
541 /* [RW 3] The source that is associated with arbitration element 2. Source
542 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
543 sleeping thread with priority 1; 4- sleeping thread with priority 2.
544 Could not be equal to register ~csem_registers_arb_element0.arb_element0
545 and ~csem_registers_arb_element1.arb_element1 */
546 #define CSEM_REG_ARB_ELEMENT2 0x200028
547 /* [RW 3] The source that is associated with arbitration element 3. Source
548 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
549 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
550 not be equal to register ~csem_registers_arb_element0.arb_element0 and
551 ~csem_registers_arb_element1.arb_element1 and
552 ~csem_registers_arb_element2.arb_element2 */
553 #define CSEM_REG_ARB_ELEMENT3 0x20002c
554 /* [RW 3] The source that is associated with arbitration element 4. Source
555 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
556 sleeping thread with priority 1; 4- sleeping thread with priority 2.
557 Could not be equal to register ~csem_registers_arb_element0.arb_element0
558 and ~csem_registers_arb_element1.arb_element1 and
559 ~csem_registers_arb_element2.arb_element2 and
560 ~csem_registers_arb_element3.arb_element3 */
561 #define CSEM_REG_ARB_ELEMENT4 0x200030
562 /* [RW 32] Interrupt mask register #0 read/write */
563 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
564 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
565 /* [R 32] Interrupt register #0 read */
566 #define CSEM_REG_CSEM_INT_STS_0 0x200104
567 #define CSEM_REG_CSEM_INT_STS_1 0x200114
568 /* [RW 32] Parity mask register #0 read/write */
569 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
570 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
571 /* [R 32] Parity register #0 read */
572 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
573 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
574 /* [RC 32] Parity register #0 read clear */
575 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
576 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
577 #define CSEM_REG_ENABLE_IN 0x2000a4
578 #define CSEM_REG_ENABLE_OUT 0x2000a8
579 /* [RW 32] This address space contains all registers and memories that are
580 placed in SEM_FAST block. The SEM_FAST registers are described in
581 appendix B. In order to access the sem_fast registers the base address
582 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
583 #define CSEM_REG_FAST_MEMORY 0x220000
584 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
586 #define CSEM_REG_FIC0_DISABLE 0x200224
587 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
589 #define CSEM_REG_FIC1_DISABLE 0x200234
590 /* [RW 15] Interrupt table Read and write access to it is not possible in
591 the middle of the work */
592 #define CSEM_REG_INT_TABLE 0x200400
593 /* [ST 24] Statistics register. The number of messages that entered through
595 #define CSEM_REG_MSG_NUM_FIC0 0x200000
596 /* [ST 24] Statistics register. The number of messages that entered through
598 #define CSEM_REG_MSG_NUM_FIC1 0x200004
599 /* [ST 24] Statistics register. The number of messages that were sent to
601 #define CSEM_REG_MSG_NUM_FOC0 0x200008
602 /* [ST 24] Statistics register. The number of messages that were sent to
604 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
605 /* [ST 24] Statistics register. The number of messages that were sent to
607 #define CSEM_REG_MSG_NUM_FOC2 0x200010
608 /* [ST 24] Statistics register. The number of messages that were sent to
610 #define CSEM_REG_MSG_NUM_FOC3 0x200014
611 /* [RW 1] Disables input messages from the passive buffer May be updated
612 during run_time by the microcode */
613 #define CSEM_REG_PAS_DISABLE 0x20024c
614 /* [WB 128] Debug only. Passive buffer memory */
615 #define CSEM_REG_PASSIVE_BUFFER 0x202000
616 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
617 #define CSEM_REG_PRAM 0x240000
618 /* [R 16] Valid sleeping threads indication have bit per thread */
619 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
620 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
621 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
622 /* [RW 16] List of free threads . There is a bit per thread. */
623 #define CSEM_REG_THREADS_LIST 0x2002e4
624 /* [RW 3] The arbitration scheme of time_slot 0 */
625 #define CSEM_REG_TS_0_AS 0x200038
626 /* [RW 3] The arbitration scheme of time_slot 10 */
627 #define CSEM_REG_TS_10_AS 0x200060
628 /* [RW 3] The arbitration scheme of time_slot 11 */
629 #define CSEM_REG_TS_11_AS 0x200064
630 /* [RW 3] The arbitration scheme of time_slot 12 */
631 #define CSEM_REG_TS_12_AS 0x200068
632 /* [RW 3] The arbitration scheme of time_slot 13 */
633 #define CSEM_REG_TS_13_AS 0x20006c
634 /* [RW 3] The arbitration scheme of time_slot 14 */
635 #define CSEM_REG_TS_14_AS 0x200070
636 /* [RW 3] The arbitration scheme of time_slot 15 */
637 #define CSEM_REG_TS_15_AS 0x200074
638 /* [RW 3] The arbitration scheme of time_slot 16 */
639 #define CSEM_REG_TS_16_AS 0x200078
640 /* [RW 3] The arbitration scheme of time_slot 17 */
641 #define CSEM_REG_TS_17_AS 0x20007c
642 /* [RW 3] The arbitration scheme of time_slot 18 */
643 #define CSEM_REG_TS_18_AS 0x200080
644 /* [RW 3] The arbitration scheme of time_slot 1 */
645 #define CSEM_REG_TS_1_AS 0x20003c
646 /* [RW 3] The arbitration scheme of time_slot 2 */
647 #define CSEM_REG_TS_2_AS 0x200040
648 /* [RW 3] The arbitration scheme of time_slot 3 */
649 #define CSEM_REG_TS_3_AS 0x200044
650 /* [RW 3] The arbitration scheme of time_slot 4 */
651 #define CSEM_REG_TS_4_AS 0x200048
652 /* [RW 3] The arbitration scheme of time_slot 5 */
653 #define CSEM_REG_TS_5_AS 0x20004c
654 /* [RW 3] The arbitration scheme of time_slot 6 */
655 #define CSEM_REG_TS_6_AS 0x200050
656 /* [RW 3] The arbitration scheme of time_slot 7 */
657 #define CSEM_REG_TS_7_AS 0x200054
658 /* [RW 3] The arbitration scheme of time_slot 8 */
659 #define CSEM_REG_TS_8_AS 0x200058
660 /* [RW 3] The arbitration scheme of time_slot 9 */
661 #define CSEM_REG_TS_9_AS 0x20005c
662 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
663 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
664 #define CSEM_REG_VFPF_ERR_NUM 0x200380
665 /* [RW 1] Parity mask register #0 read/write */
666 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
667 /* [R 1] Parity register #0 read */
668 #define DBG_REG_DBG_PRTY_STS 0xc09c
669 /* [RC 1] Parity register #0 read clear */
670 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
671 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
672 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
673 * 4.Completion function=0; 5.Error handling=0 */
674 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c
675 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
677 #define DMAE_REG_CMD_MEM 0x102400
678 #define DMAE_REG_CMD_MEM_SIZE 224
679 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
680 initial value is all ones. */
681 #define DMAE_REG_CRC16C_INIT 0x10201c
682 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
683 CRC-16 T10 initial value is all ones. */
684 #define DMAE_REG_CRC16T10_INIT 0x102020
685 /* [RW 2] Interrupt mask register #0 read/write */
686 #define DMAE_REG_DMAE_INT_MASK 0x102054
687 /* [RW 4] Parity mask register #0 read/write */
688 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
689 /* [R 4] Parity register #0 read */
690 #define DMAE_REG_DMAE_PRTY_STS 0x102058
691 /* [RC 4] Parity register #0 read clear */
692 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
693 /* [RW 1] Command 0 go. */
694 #define DMAE_REG_GO_C0 0x102080
695 /* [RW 1] Command 1 go. */
696 #define DMAE_REG_GO_C1 0x102084
697 /* [RW 1] Command 10 go. */
698 #define DMAE_REG_GO_C10 0x102088
699 /* [RW 1] Command 11 go. */
700 #define DMAE_REG_GO_C11 0x10208c
701 /* [RW 1] Command 12 go. */
702 #define DMAE_REG_GO_C12 0x102090
703 /* [RW 1] Command 13 go. */
704 #define DMAE_REG_GO_C13 0x102094
705 /* [RW 1] Command 14 go. */
706 #define DMAE_REG_GO_C14 0x102098
707 /* [RW 1] Command 15 go. */
708 #define DMAE_REG_GO_C15 0x10209c
709 /* [RW 1] Command 2 go. */
710 #define DMAE_REG_GO_C2 0x1020a0
711 /* [RW 1] Command 3 go. */
712 #define DMAE_REG_GO_C3 0x1020a4
713 /* [RW 1] Command 4 go. */
714 #define DMAE_REG_GO_C4 0x1020a8
715 /* [RW 1] Command 5 go. */
716 #define DMAE_REG_GO_C5 0x1020ac
717 /* [RW 1] Command 6 go. */
718 #define DMAE_REG_GO_C6 0x1020b0
719 /* [RW 1] Command 7 go. */
720 #define DMAE_REG_GO_C7 0x1020b4
721 /* [RW 1] Command 8 go. */
722 #define DMAE_REG_GO_C8 0x1020b8
723 /* [RW 1] Command 9 go. */
724 #define DMAE_REG_GO_C9 0x1020bc
725 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
726 input is disregarded; valid is deasserted; all other signals are treated
727 as usual; if 1 - normal activity. */
728 #define DMAE_REG_GRC_IFEN 0x102008
729 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
730 acknowledge input is disregarded; valid is deasserted; full is asserted;
731 all other signals are treated as usual; if 1 - normal activity. */
732 #define DMAE_REG_PCI_IFEN 0x102004
733 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
734 initial value to the credit counter; related to the address. Read returns
735 the current value of the counter. */
736 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
737 /* [RW 8] Aggregation command. */
738 #define DORQ_REG_AGG_CMD0 0x170060
739 /* [RW 8] Aggregation command. */
740 #define DORQ_REG_AGG_CMD1 0x170064
741 /* [RW 8] Aggregation command. */
742 #define DORQ_REG_AGG_CMD2 0x170068
743 /* [RW 8] Aggregation command. */
744 #define DORQ_REG_AGG_CMD3 0x17006c
745 /* [RW 28] UCM Header. */
746 #define DORQ_REG_CMHEAD_RX 0x170050
747 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
748 #define DORQ_REG_DB_ADDR0 0x17008c
749 /* [RW 5] Interrupt mask register #0 read/write */
750 #define DORQ_REG_DORQ_INT_MASK 0x170180
751 /* [R 5] Interrupt register #0 read */
752 #define DORQ_REG_DORQ_INT_STS 0x170174
753 /* [RC 5] Interrupt register #0 read clear */
754 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
755 /* [RW 2] Parity mask register #0 read/write */
756 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
757 /* [R 2] Parity register #0 read */
758 #define DORQ_REG_DORQ_PRTY_STS 0x170184
759 /* [RC 2] Parity register #0 read clear */
760 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
761 /* [RW 8] The address to write the DPM CID to STORM. */
762 #define DORQ_REG_DPM_CID_ADDR 0x170044
763 /* [RW 5] The DPM mode CID extraction offset. */
764 #define DORQ_REG_DPM_CID_OFST 0x170030
765 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
766 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
767 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
768 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
769 /* [R 13] Current value of the DQ FIFO fill level according to following
770 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
772 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
773 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
774 equal to full threshold; reset on full clear. */
775 #define DORQ_REG_DQ_FULL_ST 0x1700c0
776 /* [RW 28] The value sent to CM header in the case of CFC load error. */
777 #define DORQ_REG_ERR_CMHEAD 0x170058
778 #define DORQ_REG_IF_EN 0x170004
779 #define DORQ_REG_MODE_ACT 0x170008
780 /* [RW 5] The normal mode CID extraction offset. */
781 #define DORQ_REG_NORM_CID_OFST 0x17002c
782 /* [RW 28] TCM Header when only TCP context is loaded. */
783 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
784 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
786 #define DORQ_REG_OUTST_REQ 0x17003c
787 #define DORQ_REG_PF_USAGE_CNT 0x1701d0
788 #define DORQ_REG_REGN 0x170038
789 /* [R 4] Current value of response A counter credit. Initial credit is
790 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
792 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
793 /* [R 4] Current value of response B counter credit. Initial credit is
794 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
796 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
797 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
798 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
799 read reads this written value. */
800 #define DORQ_REG_RSP_INIT_CRD 0x170048
801 /* [RW 4] Initial activity counter value on the load request; when the
803 #define DORQ_REG_SHRT_ACT_CNT 0x170070
804 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
805 #define DORQ_REG_SHRT_CMHEAD 0x170054
806 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
807 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
808 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
809 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
810 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
811 #define HC_REG_AGG_INT_0 0x108050
812 #define HC_REG_AGG_INT_1 0x108054
813 #define HC_REG_ATTN_BIT 0x108120
814 #define HC_REG_ATTN_IDX 0x108100
815 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
816 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
817 #define HC_REG_ATTN_NUM_P0 0x108038
818 #define HC_REG_ATTN_NUM_P1 0x10803c
819 #define HC_REG_COMMAND_REG 0x108180
820 #define HC_REG_CONFIG_0 0x108000
821 #define HC_REG_CONFIG_1 0x108004
822 #define HC_REG_FUNC_NUM_P0 0x1080ac
823 #define HC_REG_FUNC_NUM_P1 0x1080b0
824 /* [RW 3] Parity mask register #0 read/write */
825 #define HC_REG_HC_PRTY_MASK 0x1080a0
826 /* [R 3] Parity register #0 read */
827 #define HC_REG_HC_PRTY_STS 0x108094
828 /* [RC 3] Parity register #0 read clear */
829 #define HC_REG_HC_PRTY_STS_CLR 0x108098
830 #define HC_REG_INT_MASK 0x108108
831 #define HC_REG_LEADING_EDGE_0 0x108040
832 #define HC_REG_LEADING_EDGE_1 0x108048
833 #define HC_REG_MAIN_MEMORY 0x108800
834 #define HC_REG_MAIN_MEMORY_SIZE 152
835 #define HC_REG_P0_PROD_CONS 0x108200
836 #define HC_REG_P1_PROD_CONS 0x108400
837 #define HC_REG_PBA_COMMAND 0x108140
838 #define HC_REG_PCI_CONFIG_0 0x108010
839 #define HC_REG_PCI_CONFIG_1 0x108014
840 #define HC_REG_STATISTIC_COUNTERS 0x109000
841 #define HC_REG_TRAILING_EDGE_0 0x108044
842 #define HC_REG_TRAILING_EDGE_1 0x10804c
843 #define HC_REG_UC_RAM_ADDR_0 0x108028
844 #define HC_REG_UC_RAM_ADDR_1 0x108030
845 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
846 #define HC_REG_VQID_0 0x108008
847 #define HC_REG_VQID_1 0x10800c
848 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
849 #define IGU_REG_ATTENTION_ACK_BITS 0x130108
850 /* [R 4] Debug: attn_fsm */
851 #define IGU_REG_ATTN_FSM 0x130054
852 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
853 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120
854 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
855 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
856 * write done didn't receive. */
857 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
858 #define IGU_REG_BLOCK_CONFIGURATION 0x130000
859 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
860 #define IGU_REG_COMMAND_REG_CTRL 0x13012c
861 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
862 * is clear. The bits in this registers are set and clear via the producer
863 * command. Data valid only in addresses 0-4. all the rest are zero. */
864 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
865 /* [R 5] Debug: ctrl_fsm */
866 #define IGU_REG_CTRL_FSM 0x130064
867 /* [R 1] data available for error memory. If this bit is clear do not red
868 * from error_handling_memory. */
869 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
870 /* [RW 11] Parity mask register #0 read/write */
871 #define IGU_REG_IGU_PRTY_MASK 0x1300a8
872 /* [R 11] Parity register #0 read */
873 #define IGU_REG_IGU_PRTY_STS 0x13009c
874 /* [RC 11] Parity register #0 read clear */
875 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
876 /* [R 4] Debug: int_handle_fsm */
877 #define IGU_REG_INT_HANDLE_FSM 0x130050
878 #define IGU_REG_LEADING_EDGE_LATCH 0x130134
879 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
880 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
881 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
882 #define IGU_REG_MAPPING_MEMORY 0x131000
883 #define IGU_REG_MAPPING_MEMORY_SIZE 136
884 #define IGU_REG_PBA_STATUS_LSB 0x130138
885 #define IGU_REG_PBA_STATUS_MSB 0x13013c
886 #define IGU_REG_PCI_PF_MSI_EN 0x130140
887 #define IGU_REG_PCI_PF_MSIX_EN 0x130144
888 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
889 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
890 * pending; 1 = pending. Pendings means interrupt was asserted; and write
891 * done was not received. Data valid only in addresses 0-4. all the rest are
893 #define IGU_REG_PENDING_BITS_STATUS 0x130300
894 #define IGU_REG_PF_CONFIGURATION 0x130154
895 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
896 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
897 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
898 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
899 * - In backward compatible mode; for non default SB; each even line in the
900 * memory holds the U producer and each odd line hold the C producer. The
901 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
902 * last 20 producers are for the DSB for each PF. each PF has five segments
903 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
904 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
905 #define IGU_REG_PROD_CONS_MEMORY 0x132000
906 /* [R 3] Debug: pxp_arb_fsm */
907 #define IGU_REG_PXP_ARB_FSM 0x130068
908 /* [RW 6] Write one for each bit will reset the appropriate memory. When the
909 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
910 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
911 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
912 #define IGU_REG_RESET_MEMORIES 0x130158
913 /* [R 4] Debug: sb_ctrl_fsm */
914 #define IGU_REG_SB_CTRL_FSM 0x13004c
915 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
916 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
917 #define IGU_REG_SB_MASK_LSB 0x130164
918 #define IGU_REG_SB_MASK_MSB 0x130168
919 /* [RW 16] Number of command that were dropped without causing an interrupt
920 * due to: read access for WO BAR address; or write access for RO BAR
921 * address or any access for reserved address or PCI function error is set
922 * and address is not MSIX; PBA or cleanup */
923 #define IGU_REG_SILENT_DROP 0x13016c
924 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
925 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
926 * PF; 68-71 number of ATTN messages per PF */
927 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
928 /* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
929 * timer mask command arrives. Value must be bigger than 100. */
930 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c
931 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104
932 #define IGU_REG_VF_CONFIGURATION 0x130170
933 /* [WB_R 32] Each bit represent write done pending bits status for that SB
934 * (MSI/MSIX message was sent and write done was not received yet). 0 =
935 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
936 #define IGU_REG_WRITE_DONE_PENDING 0x130480
937 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000
938 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
939 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
940 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
941 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
942 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
943 #define MCP_REG_MCPR_NVM_READ 0x86410
944 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
945 #define MCP_REG_MCPR_NVM_WRITE 0x86408
946 #define MCP_REG_MCPR_SCRATCH 0xa0000
947 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
948 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
949 /* [R 32] read first 32 bit after inversion of function 0. mapped as
950 follows: [0] NIG attention for function0; [1] NIG attention for
951 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
952 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
953 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
954 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
955 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
956 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
957 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
958 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
959 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
960 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
961 Parity error; [31] PBF Hw interrupt; */
962 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
963 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
964 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
965 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
966 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
967 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
968 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
969 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
970 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
971 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
972 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
973 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
974 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
975 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
977 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
978 /* [R 32] read second 32 bit after inversion of function 0. mapped as
979 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
980 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
981 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
982 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
983 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
984 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
985 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
986 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
987 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
988 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
989 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
991 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
992 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
993 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
994 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
995 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
996 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
997 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
998 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
999 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1000 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1001 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1002 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1003 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1004 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1005 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1006 /* [R 32] read third 32 bit after inversion of function 0. mapped as
1007 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1008 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
1009 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1010 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1011 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1012 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1013 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1014 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1015 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1016 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1017 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1019 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1020 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1021 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1022 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
1023 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
1024 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
1025 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
1026 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
1027 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
1028 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
1029 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
1030 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
1031 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
1032 timers attn_4 func1; [30] General attn0; [31] General attn1; */
1033 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1034 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1035 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1036 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1037 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1038 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1039 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1040 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1041 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1042 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1043 Latched timeout attention; [27] GRC Latched reserved access attention;
1044 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1045 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1046 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1047 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1048 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1049 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
1050 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
1051 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
1052 General attn13; [12] General attn14; [13] General attn15; [14] General
1053 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
1054 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
1055 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
1056 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
1057 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
1058 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
1059 ump_tx_parity; [31] MCP Latched scpad_parity; */
1060 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
1061 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1062 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1063 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
1064 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1065 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
1066 /* [W 14] write to this register results with the clear of the latched
1067 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
1068 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
1069 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
1070 GRC Latched reserved access attention; one in d7 clears Latched
1071 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
1072 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
1073 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
1074 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
1075 from this register return zero */
1076 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1077 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1078 as follows: [0] NIG attention for function0; [1] NIG attention for
1079 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1080 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1081 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1082 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1083 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1084 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1085 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1086 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1087 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1088 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1089 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1090 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1091 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
1092 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
1093 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
1094 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1095 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1096 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
1097 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
1098 as follows: [0] NIG attention for function0; [1] NIG attention for
1099 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1100 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1101 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1102 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1103 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1104 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
1105 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1106 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1107 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1108 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1109 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1110 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1111 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
1112 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
1113 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
1114 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1115 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1116 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1117 /* [RW 32] first 32b for enabling the output for close the gate nig. mapped
1118 as follows: [0] NIG attention for function0; [1] NIG attention for
1119 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1120 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1121 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1122 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1123 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1124 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1125 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1126 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1127 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1128 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1129 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1130 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1131 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
1132 /* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
1133 as follows: [0] NIG attention for function0; [1] NIG attention for
1134 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1135 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1136 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1137 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1138 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1139 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1140 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
1141 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
1142 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
1143 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
1144 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1145 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1146 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1147 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1148 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1149 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1150 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1151 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1152 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1153 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1154 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1155 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1156 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1157 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1158 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1160 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1161 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1162 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
1163 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1164 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1165 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1166 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1167 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1168 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1169 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1170 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1171 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1172 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1173 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1175 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1176 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1177 /* [RW 32] second 32b for enabling the output for close the gate nig. mapped
1178 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1179 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1180 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1181 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1182 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1183 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1184 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1185 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1186 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1187 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1188 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1190 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1191 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1192 /* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
1193 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1194 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
1195 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
1196 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
1197 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
1198 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
1199 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
1200 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
1201 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
1202 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
1203 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
1205 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1206 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1207 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1208 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1209 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1210 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1211 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1212 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1213 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1214 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1215 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1216 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1217 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1218 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1220 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1221 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1222 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1223 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1224 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1225 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1226 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1227 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1228 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1229 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1230 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1231 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1232 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1233 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1235 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1236 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1237 /* [RW 32] third 32b for enabling the output for close the gate nig. mapped
1238 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1239 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1240 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1241 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1242 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1243 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1244 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1245 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1246 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1247 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1248 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1250 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1251 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1252 /* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
1253 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1254 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1255 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1256 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1257 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1258 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1259 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1260 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1261 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1262 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1263 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1265 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1266 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1267 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1268 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1269 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1270 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1271 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1272 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1273 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1274 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1275 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1276 Latched timeout attention; [27] GRC Latched reserved access attention;
1277 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1278 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1279 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1280 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1281 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1282 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1283 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1284 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1285 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1286 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1287 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1288 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1289 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1290 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1291 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1292 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1293 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1294 Latched timeout attention; [27] GRC Latched reserved access attention;
1295 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1296 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1297 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1298 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1299 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1300 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1301 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1302 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1303 /* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
1304 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1305 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1306 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1307 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1308 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1309 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1310 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1311 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1312 Latched timeout attention; [27] GRC Latched reserved access attention;
1313 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1314 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1315 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1316 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1317 /* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
1318 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1319 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1320 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1321 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1322 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1323 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1324 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1325 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1326 Latched timeout attention; [27] GRC Latched reserved access attention;
1327 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1328 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1329 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1330 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1331 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1333 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1334 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1335 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1336 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1337 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1338 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1339 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1340 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1341 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1342 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1343 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1344 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1345 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1346 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1347 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1348 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1349 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1350 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1351 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1352 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1353 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1354 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1355 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1356 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1357 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1358 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1359 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1360 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1361 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1362 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1363 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1364 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1365 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1366 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1367 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1368 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1369 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1370 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1371 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1372 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1373 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1374 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1375 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1376 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1377 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1378 [9:8] = raserved. Zero = mask; one = unmask */
1379 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1380 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1381 /* [RW 1] If set a system kill occurred */
1382 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1383 /* [RW 32] Represent the status of the input vector to the AEU when a system
1384 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1385 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
1386 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
1387 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
1388 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
1389 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
1390 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
1391 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
1392 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
1393 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
1394 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
1395 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
1397 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1398 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1399 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1400 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1401 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1403 #define MISC_REG_BOND_ID 0xa400
1404 /* [R 8] These bits indicate the metal revision of the chip. This value
1405 starts at 0x00 for each all-layer tape-out and increments by one for each
1407 #define MISC_REG_CHIP_METAL 0xa404
1408 /* [R 16] These bits indicate the part number for the chip. */
1409 #define MISC_REG_CHIP_NUM 0xa408
1410 /* [R 4] These bits indicate the base revision of the chip. This value
1411 starts at 0x0 for the A0 tape-out and increments by one for each
1412 all-layer tape-out. */
1413 #define MISC_REG_CHIP_REV 0xa40c
1414 /* [RW 32] The following driver registers(1...16) represent 16 drivers and
1415 32 clients. Each client can be controlled by one driver only. One in each
1416 bit represent that this driver control the appropriate client (Ex: bit 5
1417 is set means this driver control client number 5). addr1 = set; addr0 =
1418 clear; read from both addresses will give the same result = status. write
1419 to address 1 will set a request to control all the clients that their
1420 appropriate bit (in the write command) is set. if the client is free (the
1421 appropriate bit in all the other drivers is clear) one will be written to
1422 that driver register; if the client isn't free the bit will remain zero.
1423 if the appropriate bit is set (the driver request to gain control on a
1424 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1425 interrupt will be asserted). write to address 0 will set a request to
1426 free all the clients that their appropriate bit (in the write command) is
1427 set. if the appropriate bit is clear (the driver request to free a client
1428 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1430 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1431 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1432 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1434 #define MISC_REG_E1HMF_MODE 0xa5f8
1435 /* [RW 32] Debug only: spare RW register reset by core reset */
1436 #define MISC_REG_GENERIC_CR_0 0xa460
1437 #define MISC_REG_GENERIC_CR_1 0xa464
1438 /* [RW 32] Debug only: spare RW register reset by por reset */
1439 #define MISC_REG_GENERIC_POR_1 0xa474
1440 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1441 these bits is written as a '1'; the corresponding SPIO bit will turn off
1442 it's drivers and become an input. This is the reset state of all GPIO
1443 pins. The read value of these bits will be a '1' if that last command
1444 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1445 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1446 as a '1'; the corresponding GPIO bit will drive low. The read value of
1447 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1448 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1449 SET When any of these bits is written as a '1'; the corresponding GPIO
1450 bit will drive high (if it has that capability). The read value of these
1451 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1452 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1453 RO; These bits indicate the read value of each of the eight GPIO pins.
1454 This is the result value of the pin; not the drive value. Writing these
1455 bits will have not effect. */
1456 #define MISC_REG_GPIO 0xa490
1457 /* [RW 8] These bits enable the GPIO_INTs to signals event to the
1458 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1459 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
1461 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1462 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1463 '1' to these bit clears the corresponding bit in the #OLD_VALUE register.
1464 This will acknowledge an interrupt on the falling edge of corresponding
1465 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1466 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
1467 register. This will acknowledge an interrupt on the rising edge of
1468 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1469 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
1470 value. When the ~INT_STATE bit is set; this bit indicates the OLD value
1471 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1472 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
1473 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1474 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1475 current GPIO interrupt state for each GPIO pin. This bit is cleared when
1476 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
1477 set when the GPIO input does not match the current value in #OLD_VALUE
1479 #define MISC_REG_GPIO_INT 0xa494
1480 /* [R 28] this field hold the last information that caused reserved
1481 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1482 [27:24] the master that caused the attention - according to the following
1483 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1485 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1486 /* [R 28] this field hold the last information that caused timeout
1487 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1488 [27:24] the master that caused the attention - according to the following
1489 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
1491 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1492 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1493 access that does not finish within
1494 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1495 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1496 assert it attention output. */
1497 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1498 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1499 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1500 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1501 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1502 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1503 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1504 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1505 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1506 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1507 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1508 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1509 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1510 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1511 connected to RESET input directly. [15] capRetry_en (reset value 0)
1512 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1513 value 0) bit to continuously monitor vco freq (inverted). [17]
1514 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1515 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1516 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1517 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1518 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1519 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1520 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1521 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1522 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1523 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1524 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1526 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1527 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1528 /* [RW 4] Interrupt mask register #0 read/write */
1529 #define MISC_REG_MISC_INT_MASK 0xa388
1530 /* [RW 1] Parity mask register #0 read/write */
1531 #define MISC_REG_MISC_PRTY_MASK 0xa398
1532 /* [R 1] Parity register #0 read */
1533 #define MISC_REG_MISC_PRTY_STS 0xa38c
1534 /* [RC 1] Parity register #0 read clear */
1535 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390
1536 #define MISC_REG_NIG_WOL_P0 0xa270
1537 #define MISC_REG_NIG_WOL_P1 0xa274
1538 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
1540 #define MISC_REG_PCIE_HOT_RESET 0xa618
1541 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1542 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1543 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1544 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1545 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1546 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1547 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1548 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1549 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1550 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1551 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1552 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1553 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1554 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1555 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1556 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1557 testa_en (reset value 0); */
1558 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1559 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1560 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1561 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1562 /* [R 1] Status of 4 port mode enable input pin. */
1563 #define MISC_REG_PORT4MODE_EN 0xa750
1564 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1565 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1566 * the port4mode_en output is equal to bit[1] of this register; [1] -
1567 * Overwrite value. If bit[0] of this register is 1 this is the value that
1568 * receives the port4mode_en output . */
1569 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720
1570 /* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
1571 write/read zero = the specific block is in reset; addr 0-wr- the write
1572 value will be written to the register; addr 1-set - one will be written
1573 to all the bits that have the value of one in the data written (bits that
1574 have the value of zero will not be change) ; addr 2-clear - zero will be
1575 written to all the bits that have the value of one in the data written
1576 (bits that have the value of zero will not be change); addr 3-ignore;
1577 read ignore from all addr except addr 00; inside order of the bits is:
1578 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1579 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
1580 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
1581 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
1582 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
1583 rst_pxp_rq_rd_wr; 31:17] reserved */
1584 #define MISC_REG_RESET_REG_2 0xa590
1585 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1586 shared with the driver resides */
1587 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1588 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1589 the corresponding SPIO bit will turn off it's drivers and become an
1590 input. This is the reset state of all SPIO pins. The read value of these
1591 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1592 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1593 is written as a '1'; the corresponding SPIO bit will drive low. The read
1594 value of these bits will be a '1' if that last command (#SET; #CLR; or
1595 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1596 these bits is written as a '1'; the corresponding SPIO bit will drive
1597 high (if it has that capability). The read value of these bits will be a
1598 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1599 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1600 each of the eight SPIO pins. This is the result value of the pin; not the
1601 drive value. Writing these bits will have not effect. Each 8 bits field
1602 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1603 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1604 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1605 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1606 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1607 select VAUX supply. (This is an output pin only; it is not controlled by
1608 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1609 field is not applicable for this pin; only the VALUE fields is relevant -
1610 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
1611 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1612 device ID select; read by UMP firmware. */
1613 #define MISC_REG_SPIO 0xa4fc
1614 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1615 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1617 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1618 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1619 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1620 interrupt on the falling edge of corresponding SPIO input (reset value
1621 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1622 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1623 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1624 RO; These bits indicate the old value of the SPIO input value. When the
1625 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1626 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1627 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1628 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1629 RO; These bits indicate the current SPIO interrupt state for each SPIO
1630 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1631 command bit is written. This bit is set when the SPIO input does not
1632 match the current value in #OLD_VALUE (reset value 0). */
1633 #define MISC_REG_SPIO_INT 0xa500
1634 /* [RW 32] reload value for counter 4 if reload; the value will be reload if
1635 the counter reached zero and the reload bit
1636 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
1637 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1638 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1639 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1641 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1642 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1643 loaded; 0-prepare; -unprepare */
1644 #define MISC_REG_UNPREPARED 0xa424
1645 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1646 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1647 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1648 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1649 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1650 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
1651 * not it is the recipient of the message on the MDIO interface. The value
1652 * is compared to the value on ctrl_md_devad. Drives output
1653 * misc_xgxs0_phy_addr. Global register. */
1654 #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
1655 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1656 * Reads from this register will clear bits 31:0. */
1657 #define MSTAT_REG_RX_STAT_GR64_LO 0x200
1658 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
1659 * 31:0. Reads from this register will clear bits 31:0. */
1660 #define MSTAT_REG_TX_STAT_GTXPOK_LO 0
1661 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1662 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1663 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1664 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1665 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1666 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1667 /* [RW 1] Input enable for RX_BMAC0 IF */
1668 #define NIG_REG_BMAC0_IN_EN 0x100ac
1669 /* [RW 1] output enable for TX_BMAC0 IF */
1670 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1671 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1672 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1673 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1674 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1675 /* [RW 1] output enable for RX BRB1 port0 IF */
1676 #define NIG_REG_BRB0_OUT_EN 0x100f8
1677 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1678 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1679 /* [RW 1] output enable for RX BRB1 port1 IF */
1680 #define NIG_REG_BRB1_OUT_EN 0x100fc
1681 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1682 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1683 /* [RW 1] output enable for RX BRB1 LP IF */
1684 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1685 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1686 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
1687 72:73]-vnic_num; 81:74]-sideband_info */
1688 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1689 /* [RW 1] Input enable for TX Debug packet */
1690 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1691 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1692 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1693 First packet may be deleted from the middle. And last packet will be
1694 always deleted till the end. */
1695 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1696 /* [RW 1] Output enable to EMAC0 */
1697 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1698 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1699 to emac for port0; other way to bmac for port0 */
1700 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1701 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1702 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1703 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1704 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1705 /* [RW 1] Input enable for TX UMP management packet port0 IF */
1706 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1707 /* [RW 1] Input enable for RX_EMAC0 IF */
1708 #define NIG_REG_EMAC0_IN_EN 0x100a4
1709 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1710 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1711 /* [R 1] status from emac0. This bit is set when MDINT from either the
1712 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1713 be cleared in the attached PHY device that is driving the MINT pin. */
1714 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1715 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1716 are described in appendix A. In order to access the BMAC0 registers; the
1717 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1718 added to each BMAC register offset */
1719 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1720 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1721 are described in appendix A. In order to access the BMAC0 registers; the
1722 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1723 added to each BMAC register offset */
1724 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1725 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1726 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1727 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1728 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1729 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1730 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
1731 logic for interrupts must be used. Enable per bit of interrupt of
1732 ~latch_status.latch_status */
1733 #define NIG_REG_LATCH_BC_0 0x16210
1734 /* [RW 27] Latch for each interrupt from Unicore.b[0]
1735 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
1736 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
1737 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
1738 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
1739 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
1740 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
1741 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
1742 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
1743 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
1744 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
1745 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
1746 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
1747 #define NIG_REG_LATCH_STATUS_0 0x18000
1748 /* [RW 1] led 10g for port 0 */
1749 #define NIG_REG_LED_10G_P0 0x10320
1750 /* [RW 1] led 10g for port 1 */
1751 #define NIG_REG_LED_10G_P1 0x10324
1752 /* [RW 1] Port0: This bit is set to enable the use of the
1753 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1754 defined below. If this bit is cleared; then the blink rate will be about
1756 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1757 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1758 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1759 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1760 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1761 /* [RW 1] Port0: If set along with the
1762 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1763 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1764 bit; the Traffic LED will blink with the blink rate specified in
1765 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1766 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1768 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1769 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1770 Traffic LED will then be controlled via bit ~nig_registers_
1771 led_control_traffic_p0.led_control_traffic_p0 and bit
1772 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1773 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1774 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1775 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1776 set; the LED will blink with blink rate specified in
1777 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1778 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1780 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1781 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1782 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1783 #define NIG_REG_LED_MODE_P0 0x102f0
1784 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
1785 tsdm enable; b2- usdm enable */
1786 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
1787 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
1788 /* [RW 1] SAFC enable for port0. This register may get 1 only when
1789 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
1791 #define NIG_REG_LLFC_ENABLE_0 0x16208
1792 #define NIG_REG_LLFC_ENABLE_1 0x1620c
1793 /* [RW 16] classes are high-priority for port0 */
1794 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
1795 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
1796 /* [RW 16] classes are low-priority for port0 */
1797 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
1798 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
1799 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
1800 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
1801 #define NIG_REG_LLFC_OUT_EN_1 0x160cc
1802 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
1803 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
1804 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1805 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
1806 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1807 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1808 /* [RW 2] Determine the classification participants. 0: no classification.1:
1809 classification upon VLAN id. 2: classification upon MAC address. 3:
1810 classification upon both VLAN id & MAC addr. */
1811 #define NIG_REG_LLH0_CLS_TYPE 0x16080
1812 /* [RW 32] cm header for llh0 */
1813 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1814 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
1815 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
1816 /* [RW 16] destination TCP address 1. The LLH will look for this address in
1817 all incoming packets. */
1818 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
1819 /* [RW 16] destination UDP address 1 The LLH will look for this address in
1820 all incoming packets. */
1821 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
1822 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1823 /* [RW 8] event id for llh0 */
1824 #define NIG_REG_LLH0_EVENT_ID 0x10084
1825 #define NIG_REG_LLH0_FUNC_EN 0x160fc
1826 #define NIG_REG_LLH0_FUNC_MEM 0x16180
1827 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
1828 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
1829 /* [RW 1] Determine the IP version to look for in
1830 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
1831 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
1832 /* [RW 1] t bit for llh0 */
1833 #define NIG_REG_LLH0_T_BIT 0x10074
1834 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
1835 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
1836 /* [RW 8] init credit counter for port0 in LLH */
1837 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1838 #define NIG_REG_LLH0_XCM_MASK 0x10130
1839 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
1840 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1841 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1842 /* [RW 2] Determine the classification participants. 0: no classification.1:
1843 classification upon VLAN id. 2: classification upon MAC address. 3:
1844 classification upon both VLAN id & MAC addr. */
1845 #define NIG_REG_LLH1_CLS_TYPE 0x16084
1846 /* [RW 32] cm header for llh1 */
1847 #define NIG_REG_LLH1_CM_HEADER 0x10080
1848 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1849 /* [RW 8] event id for llh1 */
1850 #define NIG_REG_LLH1_EVENT_ID 0x10088
1851 #define NIG_REG_LLH1_FUNC_MEM 0x161c0
1852 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
1853 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16
1854 /* [RW 1] When this bit is set; the LLH will classify the packet before
1855 * sending it to the BRB or calculating WoL on it. This bit controls port 1
1856 * only. The legacy llh_multi_function_mode bit controls port 0. */
1857 #define NIG_REG_LLH1_MF_MODE 0x18614
1858 /* [RW 8] init credit counter for port1 in LLH */
1859 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1860 #define NIG_REG_LLH1_XCM_MASK 0x10134
1861 /* [RW 1] When this bit is set; the LLH will expect all packets to be with
1863 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
1864 /* [RW 1] When this bit is set; the LLH will classify the packet before
1865 sending it to the BRB or calculating WoL on it. */
1866 #define NIG_REG_LLH_MF_MODE 0x16024
1867 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1868 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1869 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1870 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1871 /* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
1872 #define NIG_REG_NIG_EMAC1_EN 0x10040
1873 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1874 EMAC0 to strip the CRC from the ingress packets. */
1875 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1876 /* [R 32] Interrupt register #0 read */
1877 #define NIG_REG_NIG_INT_STS_0 0x103b0
1878 #define NIG_REG_NIG_INT_STS_1 0x103c0
1879 /* [R 32] Legacy E1 and E1H location for parity error status register. */
1880 #define NIG_REG_NIG_PRTY_STS 0x103d0
1881 /* [R 32] Parity register #0 read */
1882 #define NIG_REG_NIG_PRTY_STS_0 0x183bc
1883 #define NIG_REG_NIG_PRTY_STS_1 0x183cc
1884 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
1885 * Ethernet header. */
1886 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
1887 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
1888 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
1889 * disabled when this bit is set. */
1890 #define NIG_REG_P0_HWPFC_ENABLE 0x18078
1891 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
1892 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
1893 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1894 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1895 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
1896 * priority field is extracted from the outer-most VLAN in receive packet.
1897 * Only COS 0 and COS 1 are supported in E2. */
1898 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
1899 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
1900 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
1901 * than one bit may be set; allowing multiple priorities to be mapped to one
1903 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
1904 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
1905 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
1906 * than one bit may be set; allowing multiple priorities to be mapped to one
1908 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
1909 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
1910 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
1911 * than one bit may be set; allowing multiple priorities to be mapped to one
1913 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
1914 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
1915 * priority is mapped to COS 3 when the corresponding mask bit is 1. More
1916 * than one bit may be set; allowing multiple priorities to be mapped to one
1918 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
1919 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
1920 * priority is mapped to COS 4 when the corresponding mask bit is 1. More
1921 * than one bit may be set; allowing multiple priorities to be mapped to one
1923 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
1924 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
1925 * priority is mapped to COS 5 when the corresponding mask bit is 1. More
1926 * than one bit may be set; allowing multiple priorities to be mapped to one
1928 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
1929 /* [RW 15] Specify which of the credit registers the client is to be mapped
1930 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
1931 * clients that are not subject to WFQ credit blocking - their
1932 * specifications here are not used. */
1933 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
1934 /* [RW 5] Specify whether the client competes directly in the strict
1935 * priority arbiter. The bits are mapped according to client ID (client IDs
1936 * are defined in tx_arb_priority_client). Default value is set to enable
1937 * strict priorities for clients 0-2 -- management and debug traffic. */
1938 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
1939 /* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
1940 * bits are mapped according to client ID (client IDs are defined in
1941 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
1943 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
1944 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
1946 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
1947 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
1948 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
1949 * when it is time to increment. */
1950 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
1951 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
1952 /* [RW 12] Specify the number of strict priority arbitration slots between
1953 * two round-robin arbitration slots to avoid starvation. A value of 0 means
1954 * no strict priority cycles - the strict priority with anti-starvation
1955 * arbiter becomes a round-robin arbiter. */
1956 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
1957 /* [RW 15] Specify the client number to be assigned to each priority of the
1958 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
1959 * are for priority 0 client; bits [14:12] are for priority 4 client. The
1960 * clients are assigned the following IDs: 0-management; 1-debug traffic
1961 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
1962 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
1963 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
1964 * traffic at priority 3; and COS1 traffic at priority 4. */
1965 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
1966 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
1967 * Ethernet header. */
1968 #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
1969 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
1970 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
1971 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
1972 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
1973 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
1974 * priority field is extracted from the outer-most VLAN in receive packet.
1975 * Only COS 0 and COS 1 are supported in E2. */
1976 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
1977 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
1978 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
1979 * than one bit may be set; allowing multiple priorities to be mapped to one
1981 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
1982 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
1983 * priority is mapped to COS 1 when the corresponding mask bit is 1. More
1984 * than one bit may be set; allowing multiple priorities to be mapped to one
1986 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
1987 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
1988 * priority is mapped to COS 2 when the corresponding mask bit is 1. More
1989 * than one bit may be set; allowing multiple priorities to be mapped to one
1991 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
1992 /* [RW 1] Pause enable for port0. This register may get 1 only when
1993 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
1995 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
1996 #define NIG_REG_PAUSE_ENABLE_1 0x160c4
1997 /* [RW 1] Input enable for RX PBF LP IF */
1998 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1999 /* [RW 1] Value of this register will be transmitted to port swap when
2000 ~nig_registers_strap_override.strap_override =1 */
2001 #define NIG_REG_PORT_SWAP 0x10394
2002 /* [RW 1] PPP enable for port0. This register may get 1 only when
2003 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2005 #define NIG_REG_PPP_ENABLE_0 0x160b0
2006 #define NIG_REG_PPP_ENABLE_1 0x160b4
2007 /* [RW 1] output enable for RX parser descriptor IF */
2008 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
2009 /* [RW 1] Input enable for RX parser request IF */
2010 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
2011 /* [RW 5] control to serdes - CL45 DEVAD */
2012 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
2013 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2014 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
2015 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2016 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
2017 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
2018 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
2019 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2021 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
2022 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
2024 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
2025 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2026 between 1024 and 1522 bytes for port0 */
2027 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
2028 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
2029 between 1523 bytes and above for port0 */
2030 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
2031 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
2033 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
2034 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2035 between 1024 and 1522 bytes for port1 */
2036 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
2037 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
2038 between 1523 bytes and above for port1 */
2039 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
2040 /* [WB_R 64] Rx statistics : User octets received for LP */
2041 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
2042 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
2043 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
2044 /* [RW 1] port swap mux selection. If this register equal to 0 then port
2045 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
2046 ort swap is equal to ~nig_registers_port_swap.port_swap */
2047 #define NIG_REG_STRAP_OVERRIDE 0x10398
2048 /* [RW 1] output enable for RX_XCM0 IF */
2049 #define NIG_REG_XCM0_OUT_EN 0x100f0
2050 /* [RW 1] output enable for RX_XCM1 IF */
2051 #define NIG_REG_XCM1_OUT_EN 0x100f4
2052 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2053 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
2054 /* [RW 5] control to xgxs - CL45 DEVAD */
2055 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
2056 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2057 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
2058 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2059 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2060 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
2061 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2062 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
2063 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2064 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2065 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2066 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2067 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
2068 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
2069 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2070 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2071 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2072 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
2073 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
2074 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2075 /* [RW 31] The weight of COS0 in the ETS command arbiter. */
2076 #define PBF_REG_COS0_WEIGHT 0x15c054
2077 /* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
2078 #define PBF_REG_COS1_UPPER_BOUND 0x15c060
2079 /* [RW 31] The weight of COS1 in the ETS command arbiter. */
2080 #define PBF_REG_COS1_WEIGHT 0x15c058
2081 /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
2083 #define PBF_REG_CREDIT_LB_Q 0x140338
2084 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2086 #define PBF_REG_CREDIT_Q0 0x14033c
2087 /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
2089 #define PBF_REG_CREDIT_Q1 0x140340
2090 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2091 current task in process). */
2092 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2093 /* [RW 1] Disable processing further tasks from port 1 (after ending the
2094 current task in process). */
2095 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2096 /* [RW 1] Disable processing further tasks from port 4 (after ending the
2097 current task in process). */
2098 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2099 #define PBF_REG_DISABLE_PF 0x1402e8
2100 /* [RW 1] Indicates that ETS is performed between the COSes in the command
2101 * arbiter. If reset strict priority w/ anti-starvation will be performed
2103 #define PBF_REG_ETS_ENABLED 0x15c050
2104 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2105 * Ethernet header. */
2106 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2107 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2108 #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2109 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2110 * priority in the command arbiter. */
2111 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2112 #define PBF_REG_IF_ENABLE_REG 0x140044
2113 /* [RW 1] Init bit. When set the initial credits are copied to the credit
2114 registers (except the port credits). Should be set and then reset after
2115 the configuration of the block has ended. */
2116 #define PBF_REG_INIT 0x140000
2117 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
2119 #define PBF_REG_INIT_CRD_LB_Q 0x15c248
2120 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2122 #define PBF_REG_INIT_CRD_Q0 0x15c230
2123 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
2125 #define PBF_REG_INIT_CRD_Q1 0x15c234
2126 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2127 copied to the credit register. Should be set and then reset after the
2128 configuration of the port has ended. */
2129 #define PBF_REG_INIT_P0 0x140004
2130 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
2131 copied to the credit register. Should be set and then reset after the
2132 configuration of the port has ended. */
2133 #define PBF_REG_INIT_P1 0x140008
2134 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
2135 copied to the credit register. Should be set and then reset after the
2136 configuration of the port has ended. */
2137 #define PBF_REG_INIT_P4 0x14000c
2138 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2139 * the LB queue. Reset upon init. */
2140 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2141 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2142 * queue 0. Reset upon init. */
2143 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2144 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2145 * queue 1. Reset upon init. */
2146 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
2147 /* [RW 1] Enable for mac interface 0. */
2148 #define PBF_REG_MAC_IF0_ENABLE 0x140030
2149 /* [RW 1] Enable for mac interface 1. */
2150 #define PBF_REG_MAC_IF1_ENABLE 0x140034
2151 /* [RW 1] Enable for the loopback interface. */
2152 #define PBF_REG_MAC_LB_ENABLE 0x140040
2153 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2154 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
2155 /* [RW 16] The number of strict priority arbitration slots between 2 RR
2156 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2157 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2158 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
2159 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2161 #define PBF_REG_P0_ARB_THRSH 0x1400e4
2162 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2163 #define PBF_REG_P0_CREDIT 0x140200
2164 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2166 #define PBF_REG_P0_INIT_CRD 0x1400d0
2167 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2168 * port 0. Reset upon init. */
2169 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2170 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2171 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
2172 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2173 #define PBF_REG_P0_TASK_CNT 0x140204
2174 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2175 * freed from the task queue of port 0. Reset upon init. */
2176 #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2177 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2178 #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2179 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2180 * buffers in 16 byte lines. */
2181 #define PBF_REG_P1_CREDIT 0x140208
2182 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2183 * buffers in 16 byte lines. */
2184 #define PBF_REG_P1_INIT_CRD 0x1400d4
2185 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2186 * port 1. Reset upon init. */
2187 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2188 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2189 #define PBF_REG_P1_TASK_CNT 0x14020c
2190 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2191 * freed from the task queue of port 1. Reset upon init. */
2192 #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2193 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
2194 #define PBF_REG_P1_TQ_OCCUPANCY 0x140300
2195 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
2196 #define PBF_REG_P4_CREDIT 0x140210
2197 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
2199 #define PBF_REG_P4_INIT_CRD 0x1400e0
2200 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
2201 * port 4. Reset upon init. */
2202 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2203 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2204 #define PBF_REG_P4_TASK_CNT 0x140214
2205 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2206 * freed from the task queue of port 4. Reset upon init. */
2207 #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2208 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
2209 #define PBF_REG_P4_TQ_OCCUPANCY 0x140304
2210 /* [RW 5] Interrupt mask register #0 read/write */
2211 #define PBF_REG_PBF_INT_MASK 0x1401d4
2212 /* [R 5] Interrupt register #0 read */
2213 #define PBF_REG_PBF_INT_STS 0x1401c8
2214 /* [RW 20] Parity mask register #0 read/write */
2215 #define PBF_REG_PBF_PRTY_MASK 0x1401e4
2216 /* [RC 20] Parity register #0 read clear */
2217 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
2218 /* [RW 16] The Ethernet type value for L2 tag 0 */
2219 #define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2220 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2221 * 2B and 14B; in 2B granularity */
2222 #define PBF_REG_TAG_LEN_0 0x15c09c
2223 /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
2224 * queue. Reset upon init. */
2225 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2226 /* [R 32] Cyclic counter for number of 8 byte lines freed from the task
2227 * queue 0. Reset upon init. */
2228 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2229 /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
2230 * Reset upon init. */
2231 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2232 /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
2234 #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2235 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2236 #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2237 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
2238 #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
2239 #define PB_REG_CONTROL 0
2240 /* [RW 2] Interrupt mask register #0 read/write */
2241 #define PB_REG_PB_INT_MASK 0x28
2242 /* [R 2] Interrupt register #0 read */
2243 #define PB_REG_PB_INT_STS 0x1c
2244 /* [RW 4] Parity mask register #0 read/write */
2245 #define PB_REG_PB_PRTY_MASK 0x38
2246 /* [R 4] Parity register #0 read */
2247 #define PB_REG_PB_PRTY_STS 0x2c
2248 /* [RC 4] Parity register #0 read clear */
2249 #define PB_REG_PB_PRTY_STS_CLR 0x30
2250 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2251 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2252 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2253 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2254 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2255 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2256 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2257 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2258 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2259 /* [R 8] Config space A attention dirty bits. Each bit indicates that the
2260 * corresponding PF generates config space A attention. Set by PXP. Reset by
2261 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
2262 * from both paths. */
2263 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2264 /* [R 8] Config space B attention dirty bits. Each bit indicates that the
2265 * corresponding PF generates config space B attention. Set by PXP. Reset by
2266 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
2267 * from both paths. */
2268 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2269 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2271 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
2272 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
2273 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
2274 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
2275 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
2277 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
2278 /* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
2279 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
2280 /* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
2281 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
2282 /* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
2283 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
2284 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2285 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
2286 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
2287 * that the FLR register of the corresponding PF was set. Set by PXP. Reset
2288 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
2289 * from both paths. */
2290 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
2291 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
2292 * to a bit in this register in order to clear the corresponding bit in
2293 * flr_request_pf_7_0 register. Note: register contains bits from both
2295 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
2296 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
2297 * indicates that the FLR register of the corresponding VF was set. Set by
2298 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
2299 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
2300 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
2301 * indicates that the FLR register of the corresponding VF was set. Set by
2302 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
2303 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
2304 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
2305 * indicates that the FLR register of the corresponding VF was set. Set by
2306 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
2307 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
2308 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
2309 * indicates that the FLR register of the corresponding VF was set. Set by
2310 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
2311 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
2312 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
2313 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
2314 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
2315 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
2316 * an uncorrectable error. Bit 4 - Completion with Configuration Request
2317 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
2318 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
2319 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
2320 * and pcie_rx_last not asserted. */
2321 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
2322 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
2323 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
2324 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
2325 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
2326 /* [R 9] Interrupt register #0 read */
2327 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
2328 /* [RC 9] Interrupt register #0 read clear */
2329 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
2330 /* [R 2] Parity register #0 read */
2331 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
2332 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
2333 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
2334 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
2335 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
2336 * if there was a completion error since the last time this register was
2338 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
2339 /* [R 18] Details of first ATS Translation Completion request received with
2340 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
2341 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
2342 * unsupported request. 2 - completer abort. 3 - Illegal value for this
2343 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
2344 * completion error since the last time this register was cleared. */
2345 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
2346 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
2347 * a bit in this register in order to clear the corresponding bit in
2348 * shadow_bme_pf_7_0 register. MCP should never use this unless a
2349 * work-around is needed. Note: register contains bits from both paths. */
2350 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
2351 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
2352 * VF enable register of the corresponding PF is written to 0 and was
2353 * previously 1. Set by PXP. Reset by MCP writing 1 to
2354 * sr_iov_disabled_request_clr. Note: register contains bits from both
2356 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
2357 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
2358 * completion did not return yet. 1 - tag is unused. Same functionality as
2359 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
2360 #define PGLUE_B_REG_TAGS_63_32 0x9244
2361 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
2363 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
2364 /* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
2365 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
2366 /* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
2367 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
2368 /* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
2369 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
2370 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2371 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
2372 /* [R 32] Address [31:0] of first read request not submitted due to error */
2373 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
2374 /* [R 32] Address [63:32] of first read request not submitted due to error */
2375 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
2376 /* [R 31] Details of first read request not submitted due to error. [4:0]
2377 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
2378 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
2380 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
2381 /* [R 26] Details of first read request not submitted due to error. [15:0]
2382 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2383 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2384 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2385 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2386 * indicates if there was a request not submitted due to error since the
2387 * last time this register was cleared. */
2388 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
2389 /* [R 32] Address [31:0] of first write request not submitted due to error */
2390 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
2391 /* [R 32] Address [63:32] of first write request not submitted due to error */
2392 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
2393 /* [R 31] Details of first write request not submitted due to error. [4:0]
2394 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
2396 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
2397 /* [R 26] Details of first write request not submitted due to error. [15:0]
2398 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
2399 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
2400 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
2401 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
2402 * indicates if there was a request not submitted due to error since the
2403 * last time this register was cleared. */
2404 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
2405 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
2406 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
2407 * value (Byte resolution address). */
2408 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
2409 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
2410 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
2411 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
2412 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
2413 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
2414 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
2415 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
2417 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
2418 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
2420 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
2421 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
2423 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
2424 /* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
2425 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
2426 /* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
2427 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
2428 /* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
2429 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
2430 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2431 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
2432 /* [R 26] Details of first target VF request accessing VF GRC space that
2433 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
2434 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
2435 * request accessing VF GRC space that failed permission check since the
2436 * last time this register was cleared. Permission checks are: function
2437 * permission; R/W permission; address range permission. */
2438 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
2439 /* [R 31] Details of first target VF request with length violation (too many
2440 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
2441 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
2442 * valid - indicates if there was a request with length violation since the
2443 * last time this register was cleared. Length violations: length of more
2444 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
2445 * length is more than 1 DW. */
2446 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
2447 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
2448 * that there was a completion with uncorrectable error for the
2449 * corresponding PF. Set by PXP. Reset by MCP writing 1 to
2450 * was_error_pf_7_0_clr. */
2451 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
2452 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
2453 * to a bit in this register in order to clear the corresponding bit in
2454 * flr_request_pf_7_0 register. */
2455 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
2456 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
2457 * indicates that there was a completion with uncorrectable error for the
2458 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2459 * was_error_vf_127_96_clr. */
2460 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
2461 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
2462 * writes 1 to a bit in this register in order to clear the corresponding
2463 * bit in was_error_vf_127_96 register. */
2464 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
2465 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
2466 * indicates that there was a completion with uncorrectable error for the
2467 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2468 * was_error_vf_31_0_clr. */
2469 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
2470 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
2471 * 1 to a bit in this register in order to clear the corresponding bit in
2472 * was_error_vf_31_0 register. */
2473 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
2474 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
2475 * indicates that there was a completion with uncorrectable error for the
2476 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2477 * was_error_vf_63_32_clr. */
2478 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
2479 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
2480 * 1 to a bit in this register in order to clear the corresponding bit in
2481 * was_error_vf_63_32 register. */
2482 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
2483 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
2484 * indicates that there was a completion with uncorrectable error for the
2485 * corresponding VF. Set by PXP. Reset by MCP writing 1 to
2486 * was_error_vf_95_64_clr. */
2487 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
2488 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
2489 * 1 to a bit in this register in order to clear the corresponding bit in
2490 * was_error_vf_95_64 register. */
2491 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
2492 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
2494 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
2495 /* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
2496 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
2497 /* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
2498 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
2499 /* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
2500 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
2501 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
2502 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
2503 #define PRS_REG_A_PRSU_20 0x40134
2504 /* [R 8] debug only: CFC load request current credit. Transaction based. */
2505 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
2506 /* [R 8] debug only: CFC search request current credit. Transaction based. */
2507 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
2508 /* [RW 6] The initial credit for the search message to the CFC interface.
2509 Credit is transaction based. */
2510 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
2511 /* [RW 24] CID for port 0 if no match */
2512 #define PRS_REG_CID_PORT_0 0x400fc
2513 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2514 load response is reset and packet type is 0. Used in packet start message
2516 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
2517 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
2518 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
2519 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
2520 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
2521 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
2522 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
2523 load response is set and packet type is 0. Used in packet start message
2525 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
2526 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
2527 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
2528 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
2529 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
2530 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
2531 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
2532 Used in packet start message to TCM. */
2533 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
2534 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
2535 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
2536 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
2537 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
2539 #define PRS_REG_CM_HDR_TYPE_0 0x40078
2540 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
2541 #define PRS_REG_CM_HDR_TYPE_2 0x40080
2542 #define PRS_REG_CM_HDR_TYPE_3 0x40084
2543 #define PRS_REG_CM_HDR_TYPE_4 0x40088
2544 /* [RW 32] The CM header in case there was not a match on the connection */
2545 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
2546 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
2547 #define PRS_REG_E1HOV_MODE 0x401c8
2548 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
2549 start message to TCM. */
2550 #define PRS_REG_EVENT_ID_1 0x40054
2551 #define PRS_REG_EVENT_ID_2 0x40058
2552 #define PRS_REG_EVENT_ID_3 0x4005c
2553 /* [RW 16] The Ethernet type value for FCoE */
2554 #define PRS_REG_FCOE_TYPE 0x401d0
2555 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
2556 load request message. */
2557 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
2558 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
2559 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
2560 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
2561 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
2562 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
2563 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
2564 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
2565 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2566 * Ethernet header. */
2567 #define PRS_REG_HDRS_AFTER_BASIC 0x40238
2568 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2569 * Ethernet header for port 0 packets. */
2570 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
2571 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
2572 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2573 #define PRS_REG_HDRS_AFTER_TAG_0 0x40248
2574 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
2576 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
2577 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
2578 /* [RW 4] The increment value to send in the CFC load request message */
2579 #define PRS_REG_INC_VALUE 0x40048
2580 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2581 #define PRS_REG_MUST_HAVE_HDRS 0x40254
2582 /* [RW 6] Bit-map indicating which headers must appear in the packet for
2584 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
2585 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
2586 #define PRS_REG_NIC_MODE 0x40138
2587 /* [RW 8] The 8-bit event ID for cases where there is no match on the
2588 connection. Used in packet start message to TCM. */
2589 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
2590 /* [ST 24] The number of input CFC flush packets */
2591 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
2592 /* [ST 32] The number of cycles the Parser halted its operation since it
2593 could not allocate the next serial number */
2594 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
2595 /* [ST 24] The number of input packets */
2596 #define PRS_REG_NUM_OF_PACKETS 0x40124
2597 /* [ST 24] The number of input transparent flush packets */
2598 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
2599 /* [RW 8] Context region for received Ethernet packet with a match and
2600 packet type 0. Used in CFC load request message */
2601 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
2602 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
2603 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
2604 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
2605 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
2606 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
2607 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
2608 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
2609 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
2610 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
2611 /* [R 2] debug only: Number of pending requests for header parsing. */
2612 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
2613 /* [R 1] Interrupt register #0 read */
2614 #define PRS_REG_PRS_INT_STS 0x40188
2615 /* [RW 8] Parity mask register #0 read/write */
2616 #define PRS_REG_PRS_PRTY_MASK 0x401a4
2617 /* [R 8] Parity register #0 read */
2618 #define PRS_REG_PRS_PRTY_STS 0x40198
2619 /* [RC 8] Parity register #0 read clear */
2620 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
2621 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
2623 #define PRS_REG_PURE_REGIONS 0x40024
2624 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
2625 serail number was released by SDM but cannot be used because a previous
2626 serial number was not released. */
2627 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
2628 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
2629 serail number was released by SDM but cannot be used because a previous
2630 serial number was not released. */
2631 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
2632 /* [R 4] debug only: SRC current credit. Transaction based. */
2633 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
2634 /* [RW 16] The Ethernet type value for L2 tag 0 */
2635 #define PRS_REG_TAG_ETHERTYPE_0 0x401d4
2636 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2637 * 2B and 14B; in 2B granularity */
2638 #define PRS_REG_TAG_LEN_0 0x4022c
2639 /* [R 8] debug only: TCM current credit. Cycle based. */
2640 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
2641 /* [R 8] debug only: TSDM current credit. Transaction based. */
2642 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
2643 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
2644 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
2645 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
2646 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
2647 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
2648 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
2649 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
2650 /* [R 6] Debug only: Number of used entries in the data FIFO */
2651 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
2652 /* [R 7] Debug only: Number of used entries in the header FIFO */
2653 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
2654 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
2655 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
2656 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
2657 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
2658 #define PXP2_REG_PGL_CONTROL0 0x120490
2659 #define PXP2_REG_PGL_CONTROL1 0x120514
2660 #define PXP2_REG_PGL_DEBUG 0x120520
2661 /* [RW 32] third dword data of expansion rom request. this register is
2662 special. reading from it provides a vector outstanding read requests. if
2663 a bit is zero it means that a read request on the corresponding tag did
2664 not finish yet (not all completions have arrived for it) */
2665 #define PXP2_REG_PGL_EXP_ROM2 0x120808
2666 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
2667 its[15:0]-address */
2668 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
2669 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
2670 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
2671 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
2672 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
2673 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
2674 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
2675 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
2676 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
2677 its[15:0]-address */
2678 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
2679 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
2680 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
2681 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
2682 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
2683 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
2684 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
2685 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
2686 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
2687 its[15:0]-address */
2688 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
2689 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
2690 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
2691 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
2692 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
2693 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
2694 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
2695 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
2696 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
2697 its[15:0]-address */
2698 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
2699 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
2700 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
2701 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
2702 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
2703 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
2704 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
2705 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
2706 /* [RW 3] this field allows one function to pretend being another function
2707 when accessing any BAR mapped resource within the device. the value of
2708 the field is the number of the function that will be accessed
2709 effectively. after software write to this bit it must read it in order to
2710 know that the new value is updated */
2711 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
2712 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
2713 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
2714 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
2715 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
2716 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
2717 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
2718 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
2719 /* [R 1] this bit indicates that a read request was blocked because of
2720 bus_master_en was deasserted */
2721 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
2722 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
2723 /* [R 18] debug only */
2724 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
2725 /* [R 1] this bit indicates that a write request was blocked because of
2726 bus_master_en was deasserted */
2727 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
2728 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
2729 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
2730 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
2731 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
2732 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
2733 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
2734 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
2735 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
2736 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
2737 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
2738 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
2739 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
2740 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
2741 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
2742 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
2743 #define PXP2_REG_PSWRQ_BW_L28 0x120318
2744 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
2745 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
2746 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
2747 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
2748 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
2749 #define PXP2_REG_PSWRQ_BW_RD 0x120324
2750 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
2751 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
2752 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
2753 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
2754 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
2755 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
2756 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
2757 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
2758 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
2759 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
2760 #define PXP2_REG_PSWRQ_BW_WR 0x120328
2761 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
2762 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
2763 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
2764 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
2765 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
2766 /* [RW 32] Interrupt mask register #0 read/write */
2767 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
2768 /* [R 32] Interrupt register #0 read */
2769 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
2770 #define PXP2_REG_PXP2_INT_STS_1 0x120608
2771 /* [RC 32] Interrupt register #0 read clear */
2772 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
2773 /* [RW 32] Parity mask register #0 read/write */
2774 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
2775 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
2776 /* [R 32] Parity register #0 read */
2777 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
2778 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
2779 /* [RC 32] Parity register #0 read clear */
2780 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
2781 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
2782 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
2783 indication about backpressure) */
2784 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
2785 /* [R 8] Debug only: The blocks counter - number of unused block ids */
2786 #define PXP2_REG_RD_BLK_CNT 0x120418
2787 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
2788 Must be bigger than 6. Normally should not be changed. */
2789 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
2790 /* [RW 2] CDU byte swapping mode configuration for master read requests */
2791 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
2792 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
2793 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
2794 /* [R 1] PSWRD internal memories initialization is done */
2795 #define PXP2_REG_RD_INIT_DONE 0x120370
2796 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2797 allocated for vq10 */
2798 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
2799 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2800 allocated for vq11 */
2801 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
2802 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2803 allocated for vq17 */
2804 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
2805 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2806 allocated for vq18 */
2807 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
2808 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2809 allocated for vq19 */
2810 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
2811 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2812 allocated for vq22 */
2813 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
2814 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2815 allocated for vq25 */
2816 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
2817 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2818 allocated for vq6 */
2819 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
2820 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
2821 allocated for vq9 */
2822 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
2823 /* [RW 2] PBF byte swapping mode configuration for master read requests */
2824 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
2825 /* [R 1] Debug only: Indication if delivery ports are idle */
2826 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
2827 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
2828 /* [RW 2] QM byte swapping mode configuration for master read requests */
2829 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
2830 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
2831 #define PXP2_REG_RD_SR_CNT 0x120414
2832 /* [RW 2] SRC byte swapping mode configuration for master read requests */
2833 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
2834 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
2835 be bigger than 1. Normally should not be changed. */
2836 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
2837 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
2838 #define PXP2_REG_RD_START_INIT 0x12036c
2839 /* [RW 2] TM byte swapping mode configuration for master read requests */
2840 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
2841 /* [RW 10] Bandwidth addition to VQ0 write requests */
2842 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
2843 /* [RW 10] Bandwidth addition to VQ12 read requests */
2844 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
2845 /* [RW 10] Bandwidth addition to VQ13 read requests */
2846 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
2847 /* [RW 10] Bandwidth addition to VQ14 read requests */
2848 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
2849 /* [RW 10] Bandwidth addition to VQ15 read requests */
2850 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
2851 /* [RW 10] Bandwidth addition to VQ16 read requests */
2852 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
2853 /* [RW 10] Bandwidth addition to VQ17 read requests */
2854 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
2855 /* [RW 10] Bandwidth addition to VQ18 read requests */
2856 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
2857 /* [RW 10] Bandwidth addition to VQ19 read requests */
2858 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
2859 /* [RW 10] Bandwidth addition to VQ20 read requests */
2860 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
2861 /* [RW 10] Bandwidth addition to VQ22 read requests */
2862 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
2863 /* [RW 10] Bandwidth addition to VQ23 read requests */
2864 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
2865 /* [RW 10] Bandwidth addition to VQ24 read requests */
2866 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
2867 /* [RW 10] Bandwidth addition to VQ25 read requests */
2868 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
2869 /* [RW 10] Bandwidth addition to VQ26 read requests */
2870 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
2871 /* [RW 10] Bandwidth addition to VQ27 read requests */
2872 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
2873 /* [RW 10] Bandwidth addition to VQ4 read requests */
2874 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
2875 /* [RW 10] Bandwidth addition to VQ5 read requests */
2876 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
2877 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
2878 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
2879 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
2880 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
2881 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
2882 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
2883 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
2884 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
2885 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
2886 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
2887 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
2888 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
2889 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
2890 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
2891 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
2892 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
2893 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
2894 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
2895 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
2896 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
2897 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
2898 #define PXP2_REG_RQ_BW_RD_L22 0x120300
2899 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
2900 #define PXP2_REG_RQ_BW_RD_L23 0x120304
2901 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
2902 #define PXP2_REG_RQ_BW_RD_L24 0x120308
2903 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
2904 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
2905 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
2906 #define PXP2_REG_RQ_BW_RD_L26 0x120310
2907 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
2908 #define PXP2_REG_RQ_BW_RD_L27 0x120314
2909 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
2910 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
2911 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
2912 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
2913 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
2914 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
2915 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
2916 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
2917 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
2918 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
2919 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
2920 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
2921 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
2922 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
2923 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
2924 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
2925 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
2926 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
2927 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
2928 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
2929 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
2930 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
2931 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
2932 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
2933 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
2934 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
2935 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
2936 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
2937 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
2938 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
2939 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
2940 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
2941 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
2942 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2943 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
2944 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2945 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
2946 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2947 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
2948 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2949 /* [RW 10] Bandwidth addition to VQ29 write requests */
2950 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2951 /* [RW 10] Bandwidth addition to VQ30 write requests */
2952 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2953 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2954 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
2955 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2956 #define PXP2_REG_RQ_BW_WR_L30 0x120320
2957 /* [RW 7] Bandwidth upper bound for VQ29 */
2958 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2959 /* [RW 7] Bandwidth upper bound for VQ30 */
2960 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2961 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
2962 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
2963 /* [RW 2] Endian mode for cdu */
2964 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2965 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
2966 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
2967 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2969 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2970 /* [R 1] 1' indicates that the requester has finished its internal
2972 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
2973 /* [RW 2] Endian mode for debug */
2974 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2975 /* [RW 1] When '1'; requests will enter input buffers but wont get out
2977 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2978 /* [RW 4] Determines alignment of write SRs when a request is split into
2979 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
2980 * aligned. 4 - 512B aligned. */
2981 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
2982 /* [RW 4] Determines alignment of read SRs when a request is split into
2983 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
2984 * aligned. 4 - 512B aligned. */
2985 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
2986 /* [RW 1] when set the new alignment method (E2) will be applied; when reset
2987 * the original alignment method (E1 E1H) will be applied */
2988 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
2989 /* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will
2991 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
2992 /* [RW 2] Endian mode for hc */
2993 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2994 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
2995 compatibility needs; Note that different registers are used per mode */
2996 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
2997 /* [WB 53] Onchip address table */
2998 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
2999 /* [WB 53] Onchip address table - B0 */
3000 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
3001 /* [RW 13] Pending read limiter threshold; in Dwords */
3002 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
3003 /* [RW 2] Endian mode for qm */
3004 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
3005 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
3006 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
3007 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3009 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
3010 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */
3011 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
3012 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3013 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3014 #define PXP2_REG_RQ_RD_MBS0 0x120160
3015 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3016 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
3017 #define PXP2_REG_RQ_RD_MBS1 0x120168
3018 /* [RW 2] Endian mode for src */
3019 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
3020 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
3021 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
3022 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3024 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
3025 /* [RW 2] Endian mode for tm */
3026 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
3027 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
3028 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
3029 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3031 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
3032 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
3033 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
3034 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3035 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
3036 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3037 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
3038 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
3039 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
3040 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
3041 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
3042 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
3043 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
3044 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
3045 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
3046 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
3047 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
3048 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
3049 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
3050 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
3051 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
3052 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
3053 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
3054 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
3055 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
3056 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
3057 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
3058 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
3059 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
3060 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
3061 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
3062 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
3063 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
3064 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
3065 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
3066 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
3067 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
3068 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
3069 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
3070 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
3071 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
3072 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
3073 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
3074 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
3075 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
3076 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
3077 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
3078 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
3079 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
3080 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
3081 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
3082 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
3083 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
3084 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
3085 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
3086 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
3087 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
3088 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
3089 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
3090 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
3091 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
3092 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
3093 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
3094 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
3095 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
3096 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
3097 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
3098 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
3099 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
3100 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3101 001:256B; 010: 512B; */
3102 #define PXP2_REG_RQ_WR_MBS0 0x12015c
3103 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3104 001:256B; 010: 512B; */
3105 #define PXP2_REG_RQ_WR_MBS1 0x120164
3106 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3107 buffer reaches this number has_payload will be asserted */
3108 #define PXP2_REG_WR_CDU_MPS 0x1205f0
3109 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3110 buffer reaches this number has_payload will be asserted */
3111 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
3112 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3113 buffer reaches this number has_payload will be asserted */
3114 #define PXP2_REG_WR_DBG_MPS 0x1205e8
3115 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3116 buffer reaches this number has_payload will be asserted */
3117 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
3118 /* [RW 10] if Number of entries in dmae fifo will be higher than this
3119 threshold then has_payload indication will be asserted; the default value
3120 should be equal to > write MBS size! */
3121 #define PXP2_REG_WR_DMAE_TH 0x120368
3122 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3123 buffer reaches this number has_payload will be asserted */
3124 #define PXP2_REG_WR_HC_MPS 0x1205c8
3125 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3126 buffer reaches this number has_payload will be asserted */
3127 #define PXP2_REG_WR_QM_MPS 0x1205dc
3128 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3129 #define PXP2_REG_WR_REV_MODE 0x120670
3130 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3131 buffer reaches this number has_payload will be asserted */
3132 #define PXP2_REG_WR_SRC_MPS 0x1205e4
3133 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3134 buffer reaches this number has_payload will be asserted */
3135 #define PXP2_REG_WR_TM_MPS 0x1205e0
3136 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3137 buffer reaches this number has_payload will be asserted */
3138 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
3139 /* [RW 10] if Number of entries in usdmdp fifo will be higher than this
3140 threshold then has_payload indication will be asserted; the default value
3141 should be equal to > write MBS size! */
3142 #define PXP2_REG_WR_USDMDP_TH 0x120348
3143 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3144 buffer reaches this number has_payload will be asserted */
3145 #define PXP2_REG_WR_USDM_MPS 0x1205cc
3146 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3147 buffer reaches this number has_payload will be asserted */
3148 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
3149 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
3150 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
3151 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
3152 this client is waiting for the arbiter. */
3153 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
3154 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue
3155 block. Should be used for close the gates. */
3156 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
3157 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit
3158 should update according to 'hst_discard_doorbells' register when the state
3160 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
3161 /* [RW 1] When 1; new internal writes arriving to the block are discarded.
3162 Should be used for close the gates. */
3163 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
3164 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1'
3165 means this PSWHST is discarding inputs from this client. Each bit should
3166 update according to 'hst_discard_internal_writes' register when the state
3168 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
3169 /* [WB 160] Used for initialization of the inbound interrupts memory */
3170 #define PXP_REG_HST_INBOUND_INT 0x103800
3171 /* [RW 32] Interrupt mask register #0 read/write */
3172 #define PXP_REG_PXP_INT_MASK_0 0x103074
3173 #define PXP_REG_PXP_INT_MASK_1 0x103084
3174 /* [R 32] Interrupt register #0 read */
3175 #define PXP_REG_PXP_INT_STS_0 0x103068
3176 #define PXP_REG_PXP_INT_STS_1 0x103078
3177 /* [RC 32] Interrupt register #0 read clear */
3178 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
3179 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3180 /* [RW 27] Parity mask register #0 read/write */
3181 #define PXP_REG_PXP_PRTY_MASK 0x103094
3182 /* [R 26] Parity register #0 read */
3183 #define PXP_REG_PXP_PRTY_STS 0x103088
3184 /* [RC 27] Parity register #0 read clear */
3185 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
3186 /* [RW 4] The activity counter initial increment value sent in the load
3188 #define QM_REG_ACTCTRINITVAL_0 0x168040
3189 #define QM_REG_ACTCTRINITVAL_1 0x168044
3190 #define QM_REG_ACTCTRINITVAL_2 0x168048
3191 #define QM_REG_ACTCTRINITVAL_3 0x16804c
3192 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3193 index I represents the physical queue number. The 12 lsbs are ignore and
3194 considered zero so practically there are only 20 bits in this register;
3196 #define QM_REG_BASEADDR 0x168900
3197 /* [RW 32] The base logical address (in bytes) of each physical queue. The
3198 index I represents the physical queue number. The 12 lsbs are ignore and
3199 considered zero so practically there are only 20 bits in this register;
3201 #define QM_REG_BASEADDR_EXT_A 0x16e100
3202 /* [RW 16] The byte credit cost for each task. This value is for both ports */
3203 #define QM_REG_BYTECRDCOST 0x168234
3204 /* [RW 16] The initial byte credit value for both ports. */
3205 #define QM_REG_BYTECRDINITVAL 0x168238
3206 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3207 queue uses port 0 else it uses port 1; queues 31-0 */
3208 #define QM_REG_BYTECRDPORT_LSB 0x168228
3209 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3210 queue uses port 0 else it uses port 1; queues 95-64 */
3211 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3212 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3213 queue uses port 0 else it uses port 1; queues 63-32 */
3214 #define QM_REG_BYTECRDPORT_MSB 0x168224
3215 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
3216 queue uses port 0 else it uses port 1; queues 127-96 */
3217 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
3218 /* [RW 16] The byte credit value that if above the QM is considered almost
3220 #define QM_REG_BYTECREDITAFULLTHR 0x168094
3221 /* [RW 4] The initial credit for interface */
3222 #define QM_REG_CMINITCRD_0 0x1680cc
3223 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8
3224 #define QM_REG_CMINITCRD_1 0x1680d0
3225 #define QM_REG_CMINITCRD_2 0x1680d4
3226 #define QM_REG_CMINITCRD_3 0x1680d8
3227 #define QM_REG_CMINITCRD_4 0x1680dc
3228 #define QM_REG_CMINITCRD_5 0x1680e0
3229 #define QM_REG_CMINITCRD_6 0x1680e4
3230 #define QM_REG_CMINITCRD_7 0x1680e8
3231 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
3233 #define QM_REG_CMINTEN 0x1680ec
3234 /* [RW 12] A bit vector which indicates which one of the queues are tied to
3236 #define QM_REG_CMINTVOQMASK_0 0x1681f4
3237 #define QM_REG_CMINTVOQMASK_1 0x1681f8
3238 #define QM_REG_CMINTVOQMASK_2 0x1681fc
3239 #define QM_REG_CMINTVOQMASK_3 0x168200
3240 #define QM_REG_CMINTVOQMASK_4 0x168204
3241 #define QM_REG_CMINTVOQMASK_5 0x168208
3242 #define QM_REG_CMINTVOQMASK_6 0x16820c
3243 #define QM_REG_CMINTVOQMASK_7 0x168210
3244 /* [RW 20] The number of connections divided by 16 which dictates the size
3245 of each queue which belongs to even function number. */
3246 #define QM_REG_CONNNUM_0 0x168020
3247 /* [R 6] Keep the fill level of the fifo from write client 4 */
3248 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
3249 /* [RW 8] The context regions sent in the CFC load request */
3250 #define QM_REG_CTXREG_0 0x168030
3251 #define QM_REG_CTXREG_1 0x168034
3252 #define QM_REG_CTXREG_2 0x168038
3253 #define QM_REG_CTXREG_3 0x16803c
3254 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
3256 #define QM_REG_ENBYPVOQMASK 0x16823c
3257 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3258 physical queue uses the byte credit; queues 31-0 */
3259 #define QM_REG_ENBYTECRD_LSB 0x168220
3260 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3261 physical queue uses the byte credit; queues 95-64 */
3262 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
3263 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3264 physical queue uses the byte credit; queues 63-32 */
3265 #define QM_REG_ENBYTECRD_MSB 0x16821c
3266 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
3267 physical queue uses the byte credit; queues 127-96 */
3268 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
3269 /* [RW 4] If cleared then the secondary interface will not be served by the
3271 #define QM_REG_ENSEC 0x1680f0
3273 #define QM_REG_FUNCNUMSEL_LSB 0x168230
3275 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
3276 /* [RW 32] A mask register to mask the Almost empty signals which will not
3277 be use for the almost empty indication to the HW block; queues 31:0 */
3278 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
3279 /* [RW 32] A mask register to mask the Almost empty signals which will not
3280 be use for the almost empty indication to the HW block; queues 95-64 */
3281 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
3282 /* [RW 32] A mask register to mask the Almost empty signals which will not
3283 be use for the almost empty indication to the HW block; queues 63:32 */
3284 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
3285 /* [RW 32] A mask register to mask the Almost empty signals which will not
3286 be use for the almost empty indication to the HW block; queues 127-96 */
3287 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
3288 /* [RW 4] The number of outstanding request to CFC */
3289 #define QM_REG_OUTLDREQ 0x168804
3290 /* [RC 1] A flag to indicate that overflow error occurred in one of the
3292 #define QM_REG_OVFERROR 0x16805c
3293 /* [RC 7] the Q where the overflow occurs */
3294 #define QM_REG_OVFQNUM 0x168058
3295 /* [R 16] Pause state for physical queues 15-0 */
3296 #define QM_REG_PAUSESTATE0 0x168410
3297 /* [R 16] Pause state for physical queues 31-16 */
3298 #define QM_REG_PAUSESTATE1 0x168414
3299 /* [R 16] Pause state for physical queues 47-32 */
3300 #define QM_REG_PAUSESTATE2 0x16e684
3301 /* [R 16] Pause state for physical queues 63-48 */
3302 #define QM_REG_PAUSESTATE3 0x16e688
3303 /* [R 16] Pause state for physical queues 79-64 */
3304 #define QM_REG_PAUSESTATE4 0x16e68c
3305 /* [R 16] Pause state for physical queues 95-80 */
3306 #define QM_REG_PAUSESTATE5 0x16e690
3307 /* [R 16] Pause state for physical queues 111-96 */
3308 #define QM_REG_PAUSESTATE6 0x16e694
3309 /* [R 16] Pause state for physical queues 127-112 */
3310 #define QM_REG_PAUSESTATE7 0x16e698
3311 /* [RW 2] The PCI attributes field used in the PCI request. */
3312 #define QM_REG_PCIREQAT 0x168054
3313 #define QM_REG_PF_EN 0x16e70c
3314 /* [R 24] The number of tasks stored in the QM for the PF. only even
3315 * functions are valid in E2 (odd I registers will be hard wired to 0) */
3316 #define QM_REG_PF_USG_CNT_0 0x16e040
3317 /* [R 16] NOT USED */
3318 #define QM_REG_PORT0BYTECRD 0x168300
3319 /* [R 16] The byte credit of port 1 */
3320 #define QM_REG_PORT1BYTECRD 0x168304
3321 /* [RW 3] pci function number of queues 15-0 */
3322 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
3323 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
3324 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
3325 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
3326 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
3327 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
3328 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
3329 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
3330 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
3331 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3332 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3333 #define QM_REG_PTRTBL 0x168a00
3334 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
3335 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read
3336 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
3337 #define QM_REG_PTRTBL_EXT_A 0x16e200
3338 /* [RW 2] Interrupt mask register #0 read/write */
3339 #define QM_REG_QM_INT_MASK 0x168444
3340 /* [R 2] Interrupt register #0 read */
3341 #define QM_REG_QM_INT_STS 0x168438
3342 /* [RW 12] Parity mask register #0 read/write */
3343 #define QM_REG_QM_PRTY_MASK 0x168454
3344 /* [R 12] Parity register #0 read */
3345 #define QM_REG_QM_PRTY_STS 0x168448
3346 /* [RC 12] Parity register #0 read clear */
3347 #define QM_REG_QM_PRTY_STS_CLR 0x16844c
3348 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
3349 #define QM_REG_QSTATUS_HIGH 0x16802c
3350 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
3351 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
3352 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
3353 #define QM_REG_QSTATUS_LOW 0x168028
3354 /* [R 32] Current queues in pipeline: Queues from 64 to 95 */
3355 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
3356 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
3357 #define QM_REG_QTASKCTR_0 0x168308
3358 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
3359 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
3360 /* [RW 4] Queue tied to VOQ */
3361 #define QM_REG_QVOQIDX_0 0x1680f4
3362 #define QM_REG_QVOQIDX_10 0x16811c
3363 #define QM_REG_QVOQIDX_100 0x16e49c
3364 #define QM_REG_QVOQIDX_101 0x16e4a0
3365 #define QM_REG_QVOQIDX_102 0x16e4a4
3366 #define QM_REG_QVOQIDX_103 0x16e4a8
3367 #define QM_REG_QVOQIDX_104 0x16e4ac
3368 #define QM_REG_QVOQIDX_105 0x16e4b0
3369 #define QM_REG_QVOQIDX_106 0x16e4b4
3370 #define QM_REG_QVOQIDX_107 0x16e4b8
3371 #define QM_REG_QVOQIDX_108 0x16e4bc
3372 #define QM_REG_QVOQIDX_109 0x16e4c0
3373 #define QM_REG_QVOQIDX_11 0x168120
3374 #define QM_REG_QVOQIDX_110 0x16e4c4
3375 #define QM_REG_QVOQIDX_111 0x16e4c8
3376 #define QM_REG_QVOQIDX_112 0x16e4cc
3377 #define QM_REG_QVOQIDX_113 0x16e4d0
3378 #define QM_REG_QVOQIDX_114 0x16e4d4
3379 #define QM_REG_QVOQIDX_115 0x16e4d8
3380 #define QM_REG_QVOQIDX_116 0x16e4dc
3381 #define QM_REG_QVOQIDX_117 0x16e4e0
3382 #define QM_REG_QVOQIDX_118 0x16e4e4
3383 #define QM_REG_QVOQIDX_119 0x16e4e8
3384 #define QM_REG_QVOQIDX_12 0x168124
3385 #define QM_REG_QVOQIDX_120 0x16e4ec
3386 #define QM_REG_QVOQIDX_121 0x16e4f0
3387 #define QM_REG_QVOQIDX_122 0x16e4f4
3388 #define QM_REG_QVOQIDX_123 0x16e4f8
3389 #define QM_REG_QVOQIDX_124 0x16e4fc
3390 #define QM_REG_QVOQIDX_125 0x16e500
3391 #define QM_REG_QVOQIDX_126 0x16e504
3392 #define QM_REG_QVOQIDX_127 0x16e508
3393 #define QM_REG_QVOQIDX_13 0x168128
3394 #define QM_REG_QVOQIDX_14 0x16812c
3395 #define QM_REG_QVOQIDX_15 0x168130
3396 #define QM_REG_QVOQIDX_16 0x168134
3397 #define QM_REG_QVOQIDX_17 0x168138
3398 #define QM_REG_QVOQIDX_21 0x168148
3399 #define QM_REG_QVOQIDX_22 0x16814c
3400 #define QM_REG_QVOQIDX_23 0x168150
3401 #define QM_REG_QVOQIDX_24 0x168154
3402 #define QM_REG_QVOQIDX_25 0x168158
3403 #define QM_REG_QVOQIDX_26 0x16815c
3404 #define QM_REG_QVOQIDX_27 0x168160
3405 #define QM_REG_QVOQIDX_28 0x168164
3406 #define QM_REG_QVOQIDX_29 0x168168
3407 #define QM_REG_QVOQIDX_30 0x16816c
3408 #define QM_REG_QVOQIDX_31 0x168170
3409 #define QM_REG_QVOQIDX_32 0x168174
3410 #define QM_REG_QVOQIDX_33 0x168178
3411 #define QM_REG_QVOQIDX_34 0x16817c
3412 #define QM_REG_QVOQIDX_35 0x168180
3413 #define QM_REG_QVOQIDX_36 0x168184
3414 #define QM_REG_QVOQIDX_37 0x168188
3415 #define QM_REG_QVOQIDX_38 0x16818c
3416 #define QM_REG_QVOQIDX_39 0x168190
3417 #define QM_REG_QVOQIDX_40 0x168194
3418 #define QM_REG_QVOQIDX_41 0x168198
3419 #define QM_REG_QVOQIDX_42 0x16819c
3420 #define QM_REG_QVOQIDX_43 0x1681a0
3421 #define QM_REG_QVOQIDX_44 0x1681a4
3422 #define QM_REG_QVOQIDX_45 0x1681a8
3423 #define QM_REG_QVOQIDX_46 0x1681ac
3424 #define QM_REG_QVOQIDX_47 0x1681b0
3425 #define QM_REG_QVOQIDX_48 0x1681b4
3426 #define QM_REG_QVOQIDX_49 0x1681b8
3427 #define QM_REG_QVOQIDX_5 0x168108
3428 #define QM_REG_QVOQIDX_50 0x1681bc
3429 #define QM_REG_QVOQIDX_51 0x1681c0
3430 #define QM_REG_QVOQIDX_52 0x1681c4
3431 #define QM_REG_QVOQIDX_53 0x1681c8
3432 #define QM_REG_QVOQIDX_54 0x1681cc
3433 #define QM_REG_QVOQIDX_55 0x1681d0
3434 #define QM_REG_QVOQIDX_56 0x1681d4
3435 #define QM_REG_QVOQIDX_57 0x1681d8
3436 #define QM_REG_QVOQIDX_58 0x1681dc
3437 #define QM_REG_QVOQIDX_59 0x1681e0
3438 #define QM_REG_QVOQIDX_6 0x16810c
3439 #define QM_REG_QVOQIDX_60 0x1681e4
3440 #define QM_REG_QVOQIDX_61 0x1681e8
3441 #define QM_REG_QVOQIDX_62 0x1681ec
3442 #define QM_REG_QVOQIDX_63 0x1681f0
3443 #define QM_REG_QVOQIDX_64 0x16e40c
3444 #define QM_REG_QVOQIDX_65 0x16e410
3445 #define QM_REG_QVOQIDX_69 0x16e420
3446 #define QM_REG_QVOQIDX_7 0x168110
3447 #define QM_REG_QVOQIDX_70 0x16e424
3448 #define QM_REG_QVOQIDX_71 0x16e428
3449 #define QM_REG_QVOQIDX_72 0x16e42c
3450 #define QM_REG_QVOQIDX_73 0x16e430
3451 #define QM_REG_QVOQIDX_74 0x16e434
3452 #define QM_REG_QVOQIDX_75 0x16e438
3453 #define QM_REG_QVOQIDX_76 0x16e43c
3454 #define QM_REG_QVOQIDX_77 0x16e440
3455 #define QM_REG_QVOQIDX_78 0x16e444
3456 #define QM_REG_QVOQIDX_79 0x16e448
3457 #define QM_REG_QVOQIDX_8 0x168114
3458 #define QM_REG_QVOQIDX_80 0x16e44c
3459 #define QM_REG_QVOQIDX_81 0x16e450
3460 #define QM_REG_QVOQIDX_85 0x16e460
3461 #define QM_REG_QVOQIDX_86 0x16e464
3462 #define QM_REG_QVOQIDX_87 0x16e468
3463 #define QM_REG_QVOQIDX_88 0x16e46c
3464 #define QM_REG_QVOQIDX_89 0x16e470
3465 #define QM_REG_QVOQIDX_9 0x168118
3466 #define QM_REG_QVOQIDX_90 0x16e474
3467 #define QM_REG_QVOQIDX_91 0x16e478
3468 #define QM_REG_QVOQIDX_92 0x16e47c
3469 #define QM_REG_QVOQIDX_93 0x16e480
3470 #define QM_REG_QVOQIDX_94 0x16e484
3471 #define QM_REG_QVOQIDX_95 0x16e488
3472 #define QM_REG_QVOQIDX_96 0x16e48c
3473 #define QM_REG_QVOQIDX_97 0x16e490
3474 #define QM_REG_QVOQIDX_98 0x16e494
3475 #define QM_REG_QVOQIDX_99 0x16e498
3476 /* [RW 1] Initialization bit command */
3477 #define QM_REG_SOFT_RESET 0x168428
3478 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
3479 #define QM_REG_TASKCRDCOST_0 0x16809c
3480 #define QM_REG_TASKCRDCOST_1 0x1680a0
3481 #define QM_REG_TASKCRDCOST_2 0x1680a4
3482 #define QM_REG_TASKCRDCOST_4 0x1680ac
3483 #define QM_REG_TASKCRDCOST_5 0x1680b0
3484 /* [R 6] Keep the fill level of the fifo from write client 3 */
3485 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
3486 /* [R 6] Keep the fill level of the fifo from write client 2 */
3487 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
3488 /* [RC 32] Credit update error register */
3489 #define QM_REG_VOQCRDERRREG 0x168408
3490 /* [R 16] The credit value for each VOQ */
3491 #define QM_REG_VOQCREDIT_0 0x1682d0
3492 #define QM_REG_VOQCREDIT_1 0x1682d4
3493 #define QM_REG_VOQCREDIT_4 0x1682e0
3494 /* [RW 16] The credit value that if above the QM is considered almost full */
3495 #define QM_REG_VOQCREDITAFULLTHR 0x168090
3496 /* [RW 16] The init and maximum credit for each VoQ */
3497 #define QM_REG_VOQINITCREDIT_0 0x168060
3498 #define QM_REG_VOQINITCREDIT_1 0x168064
3499 #define QM_REG_VOQINITCREDIT_2 0x168068
3500 #define QM_REG_VOQINITCREDIT_4 0x168070
3501 #define QM_REG_VOQINITCREDIT_5 0x168074
3502 /* [RW 1] The port of which VOQ belongs */
3503 #define QM_REG_VOQPORT_0 0x1682a0
3504 #define QM_REG_VOQPORT_1 0x1682a4
3505 #define QM_REG_VOQPORT_2 0x1682a8
3506 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3507 #define QM_REG_VOQQMASK_0_LSB 0x168240
3508 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3509 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
3510 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3511 #define QM_REG_VOQQMASK_0_MSB 0x168244
3512 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3513 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
3514 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3515 #define QM_REG_VOQQMASK_10_LSB 0x168290
3516 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3517 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
3518 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3519 #define QM_REG_VOQQMASK_10_MSB 0x168294
3520 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3521 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
3522 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3523 #define QM_REG_VOQQMASK_11_LSB 0x168298
3524 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3525 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
3526 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3527 #define QM_REG_VOQQMASK_11_MSB 0x16829c
3528 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3529 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
3530 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3531 #define QM_REG_VOQQMASK_1_LSB 0x168248
3532 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3533 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
3534 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3535 #define QM_REG_VOQQMASK_1_MSB 0x16824c
3536 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3537 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
3538 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3539 #define QM_REG_VOQQMASK_2_LSB 0x168250
3540 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3541 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
3542 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3543 #define QM_REG_VOQQMASK_2_MSB 0x168254
3544 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3545 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
3546 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3547 #define QM_REG_VOQQMASK_3_LSB 0x168258
3548 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3549 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
3550 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3551 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
3552 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3553 #define QM_REG_VOQQMASK_4_LSB 0x168260
3554 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3555 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
3556 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3557 #define QM_REG_VOQQMASK_4_MSB 0x168264
3558 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3559 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
3560 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3561 #define QM_REG_VOQQMASK_5_LSB 0x168268
3562 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3563 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
3564 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3565 #define QM_REG_VOQQMASK_5_MSB 0x16826c
3566 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3567 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
3568 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3569 #define QM_REG_VOQQMASK_6_LSB 0x168270
3570 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3571 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
3572 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3573 #define QM_REG_VOQQMASK_6_MSB 0x168274
3574 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3575 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
3576 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3577 #define QM_REG_VOQQMASK_7_LSB 0x168278
3578 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3579 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
3580 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3581 #define QM_REG_VOQQMASK_7_MSB 0x16827c
3582 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3583 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
3584 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3585 #define QM_REG_VOQQMASK_8_LSB 0x168280
3586 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3587 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
3588 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
3589 #define QM_REG_VOQQMASK_8_MSB 0x168284
3590 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3591 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
3592 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
3593 #define QM_REG_VOQQMASK_9_LSB 0x168288
3594 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
3595 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
3596 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
3597 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
3598 /* [RW 32] Wrr weights */
3599 #define QM_REG_WRRWEIGHTS_0 0x16880c
3600 #define QM_REG_WRRWEIGHTS_1 0x168810
3601 #define QM_REG_WRRWEIGHTS_10 0x168814
3602 #define QM_REG_WRRWEIGHTS_11 0x168818
3603 #define QM_REG_WRRWEIGHTS_12 0x16881c
3604 #define QM_REG_WRRWEIGHTS_13 0x168820
3605 #define QM_REG_WRRWEIGHTS_14 0x168824
3606 #define QM_REG_WRRWEIGHTS_15 0x168828
3607 #define QM_REG_WRRWEIGHTS_16 0x16e000
3608 #define QM_REG_WRRWEIGHTS_17 0x16e004
3609 #define QM_REG_WRRWEIGHTS_18 0x16e008
3610 #define QM_REG_WRRWEIGHTS_19 0x16e00c
3611 #define QM_REG_WRRWEIGHTS_2 0x16882c
3612 #define QM_REG_WRRWEIGHTS_20 0x16e010
3613 #define QM_REG_WRRWEIGHTS_21 0x16e014
3614 #define QM_REG_WRRWEIGHTS_22 0x16e018
3615 #define QM_REG_WRRWEIGHTS_23 0x16e01c
3616 #define QM_REG_WRRWEIGHTS_24 0x16e020
3617 #define QM_REG_WRRWEIGHTS_25 0x16e024
3618 #define QM_REG_WRRWEIGHTS_26 0x16e028
3619 #define QM_REG_WRRWEIGHTS_27 0x16e02c
3620 #define QM_REG_WRRWEIGHTS_28 0x16e030
3621 #define QM_REG_WRRWEIGHTS_29 0x16e034
3622 #define QM_REG_WRRWEIGHTS_3 0x168830
3623 #define QM_REG_WRRWEIGHTS_30 0x16e038
3624 #define QM_REG_WRRWEIGHTS_31 0x16e03c
3625 #define QM_REG_WRRWEIGHTS_4 0x168834
3626 #define QM_REG_WRRWEIGHTS_5 0x168838
3627 #define QM_REG_WRRWEIGHTS_6 0x16883c
3628 #define QM_REG_WRRWEIGHTS_7 0x168840
3629 #define QM_REG_WRRWEIGHTS_8 0x168844
3630 #define QM_REG_WRRWEIGHTS_9 0x168848
3631 /* [R 6] Keep the fill level of the fifo from write client 1 */
3632 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
3633 /* [W 1] reset to parity interrupt */
3634 #define SEM_FAST_REG_PARITY_RST 0x18840
3635 #define SRC_REG_COUNTFREE0 0x40500
3636 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
3637 ports. If set the searcher support 8 functions. */
3638 #define SRC_REG_E1HMF_ENABLE 0x404cc
3639 #define SRC_REG_FIRSTFREE0 0x40510
3640 #define SRC_REG_KEYRSS0_0 0x40408
3641 #define SRC_REG_KEYRSS0_7 0x40424
3642 #define SRC_REG_KEYRSS1_9 0x40454
3643 #define SRC_REG_KEYSEARCH_0 0x40458
3644 #define SRC_REG_KEYSEARCH_1 0x4045c
3645 #define SRC_REG_KEYSEARCH_2 0x40460
3646 #define SRC_REG_KEYSEARCH_3 0x40464
3647 #define SRC_REG_KEYSEARCH_4 0x40468
3648 #define SRC_REG_KEYSEARCH_5 0x4046c
3649 #define SRC_REG_KEYSEARCH_6 0x40470
3650 #define SRC_REG_KEYSEARCH_7 0x40474
3651 #define SRC_REG_KEYSEARCH_8 0x40478
3652 #define SRC_REG_KEYSEARCH_9 0x4047c
3653 #define SRC_REG_LASTFREE0 0x40530
3654 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
3655 /* [RW 1] Reset internal state machines. */
3656 #define SRC_REG_SOFT_RST 0x4049c
3657 /* [R 3] Interrupt register #0 read */
3658 #define SRC_REG_SRC_INT_STS 0x404ac
3659 /* [RW 3] Parity mask register #0 read/write */
3660 #define SRC_REG_SRC_PRTY_MASK 0x404c8
3661 /* [R 3] Parity register #0 read */
3662 #define SRC_REG_SRC_PRTY_STS 0x404bc
3663 /* [RC 3] Parity register #0 read clear */
3664 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
3665 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
3666 #define TCM_REG_CAM_OCCUP 0x5017c
3667 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3668 disregarded; valid output is deasserted; all other signals are treated as
3669 usual; if 1 - normal activity. */
3670 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
3671 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3672 are disregarded; all other signals are treated as usual; if 1 - normal
3674 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
3675 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3676 disregarded; valid output is deasserted; all other signals are treated as
3677 usual; if 1 - normal activity. */
3678 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
3679 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3680 input is disregarded; all other signals are treated as usual; if 1 -
3682 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
3683 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3684 the initial credit value; read returns the current value of the credit
3685 counter. Must be initialized to 1 at start-up. */
3686 #define TCM_REG_CFC_INIT_CRD 0x50204
3687 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3688 weight 8 (the most prioritised); 1 stands for weight 1(least
3689 prioritised); 2 stands for weight 2; tc. */
3690 #define TCM_REG_CP_WEIGHT 0x500c0
3691 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3692 disregarded; acknowledge output is deasserted; all other signals are
3693 treated as usual; if 1 - normal activity. */
3694 #define TCM_REG_CSEM_IFEN 0x5002c
3695 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
3697 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
3698 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3699 weight 8 (the most prioritised); 1 stands for weight 1(least
3700 prioritised); 2 stands for weight 2; tc. */
3701 #define TCM_REG_CSEM_WEIGHT 0x500bc
3702 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
3703 #define TCM_REG_ERR_EVNT_ID 0x500a0
3704 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3705 #define TCM_REG_ERR_TCM_HDR 0x5009c
3706 /* [RW 8] The Event ID for Timers expiration. */
3707 #define TCM_REG_EXPR_EVNT_ID 0x500a4
3708 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3709 writes the initial credit value; read returns the current value of the
3710 credit counter. Must be initialized to 64 at start-up. */
3711 #define TCM_REG_FIC0_INIT_CRD 0x5020c
3712 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3713 writes the initial credit value; read returns the current value of the
3714 credit counter. Must be initialized to 64 at start-up. */
3715 #define TCM_REG_FIC1_INIT_CRD 0x50210
3716 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3717 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
3718 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
3719 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
3720 #define TCM_REG_GR_ARB_TYPE 0x50114
3721 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3722 highest priority is 3. It is supposed that the Store channel is the
3723 compliment of the other 3 groups. */
3724 #define TCM_REG_GR_LD0_PR 0x5011c
3725 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3726 highest priority is 3. It is supposed that the Store channel is the
3727 compliment of the other 3 groups. */
3728 #define TCM_REG_GR_LD1_PR 0x50120
3729 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
3730 sent to STORM; for a specific connection type. The double REG-pairs are
3731 used to align to STORM context row size of 128 bits. The offset of these
3732 data in the STORM context is always 0. Index _i stands for the connection
3733 type (one of 16). */
3734 #define TCM_REG_N_SM_CTX_LD_0 0x50050
3735 #define TCM_REG_N_SM_CTX_LD_1 0x50054
3736 #define TCM_REG_N_SM_CTX_LD_2 0x50058
3737 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
3738 #define TCM_REG_N_SM_CTX_LD_4 0x50060
3739 #define TCM_REG_N_SM_CTX_LD_5 0x50064
3740 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3741 acknowledge output is deasserted; all other signals are treated as usual;
3742 if 1 - normal activity. */
3743 #define TCM_REG_PBF_IFEN 0x50024
3744 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
3746 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
3747 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3748 weight 8 (the most prioritised); 1 stands for weight 1(least
3749 prioritised); 2 stands for weight 2; tc. */
3750 #define TCM_REG_PBF_WEIGHT 0x500b4
3751 #define TCM_REG_PHYS_QNUM0_0 0x500e0
3752 #define TCM_REG_PHYS_QNUM0_1 0x500e4
3753 #define TCM_REG_PHYS_QNUM1_0 0x500e8
3754 #define TCM_REG_PHYS_QNUM1_1 0x500ec
3755 #define TCM_REG_PHYS_QNUM2_0 0x500f0
3756 #define TCM_REG_PHYS_QNUM2_1 0x500f4
3757 #define TCM_REG_PHYS_QNUM3_0 0x500f8
3758 #define TCM_REG_PHYS_QNUM3_1 0x500fc
3759 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
3760 acknowledge output is deasserted; all other signals are treated as usual;
3761 if 1 - normal activity. */
3762 #define TCM_REG_PRS_IFEN 0x50020
3763 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
3765 #define TCM_REG_PRS_LENGTH_MIS 0x50168
3766 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
3767 weight 8 (the most prioritised); 1 stands for weight 1(least
3768 prioritised); 2 stands for weight 2; tc. */
3769 #define TCM_REG_PRS_WEIGHT 0x500b0
3770 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3771 #define TCM_REG_STOP_EVNT_ID 0x500a8
3772 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
3774 #define TCM_REG_STORM_LENGTH_MIS 0x50160
3775 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3776 disregarded; acknowledge output is deasserted; all other signals are
3777 treated as usual; if 1 - normal activity. */
3778 #define TCM_REG_STORM_TCM_IFEN 0x50010
3779 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3780 weight 8 (the most prioritised); 1 stands for weight 1(least
3781 prioritised); 2 stands for weight 2; tc. */
3782 #define TCM_REG_STORM_WEIGHT 0x500ac
3783 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3784 acknowledge output is deasserted; all other signals are treated as usual;
3785 if 1 - normal activity. */
3786 #define TCM_REG_TCM_CFC_IFEN 0x50040
3787 /* [RW 11] Interrupt mask register #0 read/write */
3788 #define TCM_REG_TCM_INT_MASK 0x501dc
3789 /* [R 11] Interrupt register #0 read */
3790 #define TCM_REG_TCM_INT_STS 0x501d0
3791 /* [RW 27] Parity mask register #0 read/write */
3792 #define TCM_REG_TCM_PRTY_MASK 0x501ec
3793 /* [R 27] Parity register #0 read */
3794 #define TCM_REG_TCM_PRTY_STS 0x501e0
3795 /* [RC 27] Parity register #0 read clear */
3796 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
3797 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
3798 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3799 Is used to determine the number of the AG context REG-pairs written back;
3800 when the input message Reg1WbFlg isn't set. */
3801 #define TCM_REG_TCM_REG0_SZ 0x500d8
3802 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3803 disregarded; valid is deasserted; all other signals are treated as usual;
3804 if 1 - normal activity. */
3805 #define TCM_REG_TCM_STORM0_IFEN 0x50004
3806 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3807 disregarded; valid is deasserted; all other signals are treated as usual;
3808 if 1 - normal activity. */
3809 #define TCM_REG_TCM_STORM1_IFEN 0x50008
3810 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3811 disregarded; valid is deasserted; all other signals are treated as usual;
3812 if 1 - normal activity. */
3813 #define TCM_REG_TCM_TQM_IFEN 0x5000c
3814 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3815 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
3816 /* [RW 28] The CM header for Timers expiration command. */
3817 #define TCM_REG_TM_TCM_HDR 0x50098
3818 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3819 disregarded; acknowledge output is deasserted; all other signals are
3820 treated as usual; if 1 - normal activity. */
3821 #define TCM_REG_TM_TCM_IFEN 0x5001c
3822 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
3823 weight 8 (the most prioritised); 1 stands for weight 1(least
3824 prioritised); 2 stands for weight 2; tc. */
3825 #define TCM_REG_TM_WEIGHT 0x500d0
3826 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3827 the initial credit value; read returns the current value of the credit
3828 counter. Must be initialized to 32 at start-up. */
3829 #define TCM_REG_TQM_INIT_CRD 0x5021c
3830 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3831 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3832 prioritised); 2 stands for weight 2; tc. */
3833 #define TCM_REG_TQM_P_WEIGHT 0x500c8
3834 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
3835 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3836 prioritised); 2 stands for weight 2; tc. */
3837 #define TCM_REG_TQM_S_WEIGHT 0x500cc
3838 /* [RW 28] The CM header value for QM request (primary). */
3839 #define TCM_REG_TQM_TCM_HDR_P 0x50090
3840 /* [RW 28] The CM header value for QM request (secondary). */
3841 #define TCM_REG_TQM_TCM_HDR_S 0x50094
3842 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3843 acknowledge output is deasserted; all other signals are treated as usual;
3844 if 1 - normal activity. */
3845 #define TCM_REG_TQM_TCM_IFEN 0x50014
3846 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3847 acknowledge output is deasserted; all other signals are treated as usual;
3848 if 1 - normal activity. */
3849 #define TCM_REG_TSDM_IFEN 0x50018
3850 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
3852 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
3853 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3854 weight 8 (the most prioritised); 1 stands for weight 1(least
3855 prioritised); 2 stands for weight 2; tc. */
3856 #define TCM_REG_TSDM_WEIGHT 0x500c4
3857 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3858 disregarded; acknowledge output is deasserted; all other signals are
3859 treated as usual; if 1 - normal activity. */
3860 #define TCM_REG_USEM_IFEN 0x50028
3861 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
3863 #define TCM_REG_USEM_LENGTH_MIS 0x50170
3864 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3865 weight 8 (the most prioritised); 1 stands for weight 1(least
3866 prioritised); 2 stands for weight 2; tc. */
3867 #define TCM_REG_USEM_WEIGHT 0x500b8
3868 /* [RW 21] Indirect access to the descriptor table of the XX protection
3869 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
3870 pointer; 20:16] - next pointer. */
3871 #define TCM_REG_XX_DESCR_TABLE 0x50280
3872 #define TCM_REG_XX_DESCR_TABLE_SIZE 32
3873 /* [R 6] Use to read the value of XX protection Free counter. */
3874 #define TCM_REG_XX_FREE 0x50178
3875 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3876 of the Input Stage XX protection buffer by the XX protection pending
3877 messages. Max credit available - 127.Write writes the initial credit
3878 value; read returns the current value of the credit counter. Must be
3879 initialized to 19 at start-up. */
3880 #define TCM_REG_XX_INIT_CRD 0x50220
3881 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
3883 #define TCM_REG_XX_MAX_LL_SZ 0x50044
3884 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3885 protection. ~tcm_registers_xx_free.xx_free is read on read. */
3886 #define TCM_REG_XX_MSG_NUM 0x50224
3887 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3888 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
3889 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3890 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
3892 #define TCM_REG_XX_TABLE 0x50240
3893 /* [RW 4] Load value for cfc ac credit cnt. */
3894 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
3895 /* [RW 4] Load value for cfc cld credit cnt. */
3896 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
3897 /* [RW 8] Client0 context region. */
3898 #define TM_REG_CL0_CONT_REGION 0x164030
3899 /* [RW 8] Client1 context region. */
3900 #define TM_REG_CL1_CONT_REGION 0x164034
3901 /* [RW 8] Client2 context region. */
3902 #define TM_REG_CL2_CONT_REGION 0x164038
3903 /* [RW 2] Client in High priority client number. */
3904 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
3905 /* [RW 4] Load value for clout0 cred cnt. */
3906 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
3907 /* [RW 4] Load value for clout1 cred cnt. */
3908 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
3909 /* [RW 4] Load value for clout2 cred cnt. */
3910 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
3911 /* [RW 1] Enable client0 input. */
3912 #define TM_REG_EN_CL0_INPUT 0x164008
3913 /* [RW 1] Enable client1 input. */
3914 #define TM_REG_EN_CL1_INPUT 0x16400c
3915 /* [RW 1] Enable client2 input. */
3916 #define TM_REG_EN_CL2_INPUT 0x164010
3917 #define TM_REG_EN_LINEAR0_TIMER 0x164014
3918 /* [RW 1] Enable real time counter. */
3919 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
3920 /* [RW 1] Enable for Timers state machines. */
3921 #define TM_REG_EN_TIMERS 0x164000
3922 /* [RW 4] Load value for expiration credit cnt. CFC max number of
3923 outstanding load requests for timers (expiration) context loading. */
3924 #define TM_REG_EXP_CRDCNT_VAL 0x164238
3925 /* [RW 32] Linear0 logic address. */
3926 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
3927 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */
3928 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
3929 /* [ST 16] Linear0 Number of scans counter. */
3930 #define TM_REG_LIN0_NUM_SCANS 0x1640a0
3931 /* [WB 64] Linear0 phy address. */
3932 #define TM_REG_LIN0_PHY_ADDR 0x164270
3933 /* [RW 1] Linear0 physical address valid. */
3934 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
3935 #define TM_REG_LIN0_SCAN_ON 0x1640d0
3936 /* [RW 24] Linear0 array scan timeout. */
3937 #define TM_REG_LIN0_SCAN_TIME 0x16403c
3938 #define TM_REG_LIN0_VNIC_UC 0x164128
3939 /* [RW 32] Linear1 logic address. */
3940 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
3941 /* [WB 64] Linear1 phy address. */
3942 #define TM_REG_LIN1_PHY_ADDR 0x164280
3943 /* [RW 1] Linear1 physical address valid. */
3944 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
3945 /* [RW 6] Linear timer set_clear fifo threshold. */
3946 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
3947 /* [RW 2] Load value for pci arbiter credit cnt. */
3948 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
3949 /* [RW 20] The amount of hardware cycles for each timer tick. */
3950 #define TM_REG_TIMER_TICK_SIZE 0x16401c
3951 /* [RW 8] Timers Context region. */
3952 #define TM_REG_TM_CONTEXT_REGION 0x164044
3953 /* [RW 1] Interrupt mask register #0 read/write */
3954 #define TM_REG_TM_INT_MASK 0x1640fc
3955 /* [R 1] Interrupt register #0 read */
3956 #define TM_REG_TM_INT_STS 0x1640f0
3957 /* [RW 7] Parity mask register #0 read/write */
3958 #define TM_REG_TM_PRTY_MASK 0x16410c
3959 /* [RC 7] Parity register #0 read clear */
3960 #define TM_REG_TM_PRTY_STS_CLR 0x164104
3961 /* [RW 8] The event id for aggregated interrupt 0 */
3962 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
3963 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
3964 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
3965 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
3966 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
3967 /* [RW 1] The T bit for aggregated interrupt 0 */
3968 #define TSDM_REG_AGG_INT_T_0 0x420b8
3969 #define TSDM_REG_AGG_INT_T_1 0x420bc
3970 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3971 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
3972 /* [RW 16] The maximum value of the completion counter #0 */
3973 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
3974 /* [RW 16] The maximum value of the completion counter #1 */
3975 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
3976 /* [RW 16] The maximum value of the completion counter #2 */
3977 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
3978 /* [RW 16] The maximum value of the completion counter #3 */
3979 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
3980 /* [RW 13] The start address in the internal RAM for the completion
3982 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
3983 #define TSDM_REG_ENABLE_IN1 0x42238
3984 #define TSDM_REG_ENABLE_IN2 0x4223c
3985 #define TSDM_REG_ENABLE_OUT1 0x42240
3986 #define TSDM_REG_ENABLE_OUT2 0x42244
3987 /* [RW 4] The initial number of messages that can be sent to the pxp control
3988 interface without receiving any ACK. */
3989 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
3990 /* [ST 32] The number of ACK after placement messages received */
3991 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
3992 /* [ST 32] The number of packet end messages received from the parser */
3993 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
3994 /* [ST 32] The number of requests received from the pxp async if */
3995 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
3996 /* [ST 32] The number of commands received in queue 0 */
3997 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
3998 /* [ST 32] The number of commands received in queue 10 */
3999 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
4000 /* [ST 32] The number of commands received in queue 11 */
4001 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
4002 /* [ST 32] The number of commands received in queue 1 */
4003 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
4004 /* [ST 32] The number of commands received in queue 3 */
4005 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
4006 /* [ST 32] The number of commands received in queue 4 */
4007 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
4008 /* [ST 32] The number of commands received in queue 5 */
4009 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
4010 /* [ST 32] The number of commands received in queue 6 */
4011 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
4012 /* [ST 32] The number of commands received in queue 7 */
4013 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
4014 /* [ST 32] The number of commands received in queue 8 */
4015 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
4016 /* [ST 32] The number of commands received in queue 9 */
4017 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
4018 /* [RW 13] The start address in the internal RAM for the packet end message */
4019 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
4020 /* [RW 13] The start address in the internal RAM for queue counters */
4021 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
4022 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4023 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
4024 /* [R 1] parser fifo empty in sdm_sync block */
4025 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
4026 /* [R 1] parser serial fifo empty in sdm_sync block */
4027 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
4028 /* [RW 32] Tick for timer counter. Applicable only when
4029 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
4030 #define TSDM_REG_TIMER_TICK 0x42000
4031 /* [RW 32] Interrupt mask register #0 read/write */
4032 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
4033 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
4034 /* [R 32] Interrupt register #0 read */
4035 #define TSDM_REG_TSDM_INT_STS_0 0x42290
4036 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
4037 /* [RW 11] Parity mask register #0 read/write */
4038 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
4039 /* [R 11] Parity register #0 read */
4040 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
4041 /* [RC 11] Parity register #0 read clear */
4042 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
4043 /* [RW 5] The number of time_slots in the arbitration cycle */
4044 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
4045 /* [RW 3] The source that is associated with arbitration element 0. Source
4046 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4047 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4048 #define TSEM_REG_ARB_ELEMENT0 0x180020
4049 /* [RW 3] The source that is associated with arbitration element 1. Source
4050 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4051 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4052 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
4053 #define TSEM_REG_ARB_ELEMENT1 0x180024
4054 /* [RW 3] The source that is associated with arbitration element 2. Source
4055 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4056 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4057 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4058 and ~tsem_registers_arb_element1.arb_element1 */
4059 #define TSEM_REG_ARB_ELEMENT2 0x180028
4060 /* [RW 3] The source that is associated with arbitration element 3. Source
4061 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4062 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4063 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
4064 ~tsem_registers_arb_element1.arb_element1 and
4065 ~tsem_registers_arb_element2.arb_element2 */
4066 #define TSEM_REG_ARB_ELEMENT3 0x18002c
4067 /* [RW 3] The source that is associated with arbitration element 4. Source
4068 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4069 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4070 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
4071 and ~tsem_registers_arb_element1.arb_element1 and
4072 ~tsem_registers_arb_element2.arb_element2 and
4073 ~tsem_registers_arb_element3.arb_element3 */
4074 #define TSEM_REG_ARB_ELEMENT4 0x180030
4075 #define TSEM_REG_ENABLE_IN 0x1800a4
4076 #define TSEM_REG_ENABLE_OUT 0x1800a8
4077 /* [RW 32] This address space contains all registers and memories that are
4078 placed in SEM_FAST block. The SEM_FAST registers are described in
4079 appendix B. In order to access the sem_fast registers the base address
4080 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4081 #define TSEM_REG_FAST_MEMORY 0x1a0000
4082 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4084 #define TSEM_REG_FIC0_DISABLE 0x180224
4085 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4087 #define TSEM_REG_FIC1_DISABLE 0x180234
4088 /* [RW 15] Interrupt table Read and write access to it is not possible in
4089 the middle of the work */
4090 #define TSEM_REG_INT_TABLE 0x180400
4091 /* [ST 24] Statistics register. The number of messages that entered through
4093 #define TSEM_REG_MSG_NUM_FIC0 0x180000
4094 /* [ST 24] Statistics register. The number of messages that entered through
4096 #define TSEM_REG_MSG_NUM_FIC1 0x180004
4097 /* [ST 24] Statistics register. The number of messages that were sent to
4099 #define TSEM_REG_MSG_NUM_FOC0 0x180008
4100 /* [ST 24] Statistics register. The number of messages that were sent to
4102 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
4103 /* [ST 24] Statistics register. The number of messages that were sent to
4105 #define TSEM_REG_MSG_NUM_FOC2 0x180010
4106 /* [ST 24] Statistics register. The number of messages that were sent to
4108 #define TSEM_REG_MSG_NUM_FOC3 0x180014
4109 /* [RW 1] Disables input messages from the passive buffer May be updated
4110 during run_time by the microcode */
4111 #define TSEM_REG_PAS_DISABLE 0x18024c
4112 /* [WB 128] Debug only. Passive buffer memory */
4113 #define TSEM_REG_PASSIVE_BUFFER 0x181000
4114 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4115 #define TSEM_REG_PRAM 0x1c0000
4116 /* [R 8] Valid sleeping threads indication have bit per thread */
4117 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4118 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4119 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4120 /* [RW 8] List of free threads . There is a bit per thread. */
4121 #define TSEM_REG_THREADS_LIST 0x1802e4
4122 /* [RC 32] Parity register #0 read clear */
4123 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
4124 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
4125 /* [RW 3] The arbitration scheme of time_slot 0 */
4126 #define TSEM_REG_TS_0_AS 0x180038
4127 /* [RW 3] The arbitration scheme of time_slot 10 */
4128 #define TSEM_REG_TS_10_AS 0x180060
4129 /* [RW 3] The arbitration scheme of time_slot 11 */
4130 #define TSEM_REG_TS_11_AS 0x180064
4131 /* [RW 3] The arbitration scheme of time_slot 12 */
4132 #define TSEM_REG_TS_12_AS 0x180068
4133 /* [RW 3] The arbitration scheme of time_slot 13 */
4134 #define TSEM_REG_TS_13_AS 0x18006c
4135 /* [RW 3] The arbitration scheme of time_slot 14 */
4136 #define TSEM_REG_TS_14_AS 0x180070
4137 /* [RW 3] The arbitration scheme of time_slot 15 */
4138 #define TSEM_REG_TS_15_AS 0x180074
4139 /* [RW 3] The arbitration scheme of time_slot 16 */
4140 #define TSEM_REG_TS_16_AS 0x180078
4141 /* [RW 3] The arbitration scheme of time_slot 17 */
4142 #define TSEM_REG_TS_17_AS 0x18007c
4143 /* [RW 3] The arbitration scheme of time_slot 18 */
4144 #define TSEM_REG_TS_18_AS 0x180080
4145 /* [RW 3] The arbitration scheme of time_slot 1 */
4146 #define TSEM_REG_TS_1_AS 0x18003c
4147 /* [RW 3] The arbitration scheme of time_slot 2 */
4148 #define TSEM_REG_TS_2_AS 0x180040
4149 /* [RW 3] The arbitration scheme of time_slot 3 */
4150 #define TSEM_REG_TS_3_AS 0x180044
4151 /* [RW 3] The arbitration scheme of time_slot 4 */
4152 #define TSEM_REG_TS_4_AS 0x180048
4153 /* [RW 3] The arbitration scheme of time_slot 5 */
4154 #define TSEM_REG_TS_5_AS 0x18004c
4155 /* [RW 3] The arbitration scheme of time_slot 6 */
4156 #define TSEM_REG_TS_6_AS 0x180050
4157 /* [RW 3] The arbitration scheme of time_slot 7 */
4158 #define TSEM_REG_TS_7_AS 0x180054
4159 /* [RW 3] The arbitration scheme of time_slot 8 */
4160 #define TSEM_REG_TS_8_AS 0x180058
4161 /* [RW 3] The arbitration scheme of time_slot 9 */
4162 #define TSEM_REG_TS_9_AS 0x18005c
4163 /* [RW 32] Interrupt mask register #0 read/write */
4164 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4165 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4166 /* [R 32] Interrupt register #0 read */
4167 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4168 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4169 /* [RW 32] Parity mask register #0 read/write */
4170 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4171 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4172 /* [R 32] Parity register #0 read */
4173 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4174 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4175 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4176 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4177 #define TSEM_REG_VFPF_ERR_NUM 0x180380
4178 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4179 * [10:8] of the address should be the offset within the accessed LCID
4180 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4181 * LCID100. The RBC address should be 12'ha64. */
4182 #define UCM_REG_AG_CTX 0xe2000
4183 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4184 #define UCM_REG_CAM_OCCUP 0xe0170
4185 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4186 disregarded; valid output is deasserted; all other signals are treated as
4187 usual; if 1 - normal activity. */
4188 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4189 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4190 are disregarded; all other signals are treated as usual; if 1 - normal
4192 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4193 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4194 disregarded; valid output is deasserted; all other signals are treated as
4195 usual; if 1 - normal activity. */
4196 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4197 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4198 input is disregarded; all other signals are treated as usual; if 1 -
4200 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4201 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4202 the initial credit value; read returns the current value of the credit
4203 counter. Must be initialized to 1 at start-up. */
4204 #define UCM_REG_CFC_INIT_CRD 0xe0204
4205 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4206 weight 8 (the most prioritised); 1 stands for weight 1(least
4207 prioritised); 2 stands for weight 2; tc. */
4208 #define UCM_REG_CP_WEIGHT 0xe00c4
4209 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4210 disregarded; acknowledge output is deasserted; all other signals are
4211 treated as usual; if 1 - normal activity. */
4212 #define UCM_REG_CSEM_IFEN 0xe0028
4213 /* [RC 1] Set when the message length mismatch (relative to last indication)
4214 at the csem interface is detected. */
4215 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4216 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4217 weight 8 (the most prioritised); 1 stands for weight 1(least
4218 prioritised); 2 stands for weight 2; tc. */
4219 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4220 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4221 disregarded; acknowledge output is deasserted; all other signals are
4222 treated as usual; if 1 - normal activity. */
4223 #define UCM_REG_DORQ_IFEN 0xe0030
4224 /* [RC 1] Set when the message length mismatch (relative to last indication)
4225 at the dorq interface is detected. */
4226 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4227 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4228 weight 8 (the most prioritised); 1 stands for weight 1(least
4229 prioritised); 2 stands for weight 2; tc. */
4230 #define UCM_REG_DORQ_WEIGHT 0xe00c0
4231 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
4232 #define UCM_REG_ERR_EVNT_ID 0xe00a4
4233 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4234 #define UCM_REG_ERR_UCM_HDR 0xe00a0
4235 /* [RW 8] The Event ID for Timers expiration. */
4236 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
4237 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4238 writes the initial credit value; read returns the current value of the
4239 credit counter. Must be initialized to 64 at start-up. */
4240 #define UCM_REG_FIC0_INIT_CRD 0xe020c
4241 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4242 writes the initial credit value; read returns the current value of the
4243 credit counter. Must be initialized to 64 at start-up. */
4244 #define UCM_REG_FIC1_INIT_CRD 0xe0210
4245 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4246 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
4247 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
4248 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
4249 #define UCM_REG_GR_ARB_TYPE 0xe0144
4250 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4251 highest priority is 3. It is supposed that the Store channel group is
4252 compliment to the others. */
4253 #define UCM_REG_GR_LD0_PR 0xe014c
4254 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4255 highest priority is 3. It is supposed that the Store channel group is
4256 compliment to the others. */
4257 #define UCM_REG_GR_LD1_PR 0xe0150
4258 /* [RW 2] The queue index for invalidate counter flag decision. */
4259 #define UCM_REG_INV_CFLG_Q 0xe00e4
4260 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4261 sent to STORM; for a specific connection type. the double REG-pairs are
4262 used in order to align to STORM context row size of 128 bits. The offset
4263 of these data in the STORM context is always 0. Index _i stands for the
4264 connection type (one of 16). */
4265 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
4266 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
4267 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
4268 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
4269 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
4270 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
4271 #define UCM_REG_PHYS_QNUM0_0 0xe0110
4272 #define UCM_REG_PHYS_QNUM0_1 0xe0114
4273 #define UCM_REG_PHYS_QNUM1_0 0xe0118
4274 #define UCM_REG_PHYS_QNUM1_1 0xe011c
4275 #define UCM_REG_PHYS_QNUM2_0 0xe0120
4276 #define UCM_REG_PHYS_QNUM2_1 0xe0124
4277 #define UCM_REG_PHYS_QNUM3_0 0xe0128
4278 #define UCM_REG_PHYS_QNUM3_1 0xe012c
4279 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4280 #define UCM_REG_STOP_EVNT_ID 0xe00ac
4281 /* [RC 1] Set when the message length mismatch (relative to last indication)
4282 at the STORM interface is detected. */
4283 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
4284 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4285 disregarded; acknowledge output is deasserted; all other signals are
4286 treated as usual; if 1 - normal activity. */
4287 #define UCM_REG_STORM_UCM_IFEN 0xe0010
4288 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4289 weight 8 (the most prioritised); 1 stands for weight 1(least
4290 prioritised); 2 stands for weight 2; tc. */
4291 #define UCM_REG_STORM_WEIGHT 0xe00b0
4292 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4293 writes the initial credit value; read returns the current value of the
4294 credit counter. Must be initialized to 4 at start-up. */
4295 #define UCM_REG_TM_INIT_CRD 0xe021c
4296 /* [RW 28] The CM header for Timers expiration command. */
4297 #define UCM_REG_TM_UCM_HDR 0xe009c
4298 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4299 disregarded; acknowledge output is deasserted; all other signals are
4300 treated as usual; if 1 - normal activity. */
4301 #define UCM_REG_TM_UCM_IFEN 0xe001c
4302 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4303 weight 8 (the most prioritised); 1 stands for weight 1(least
4304 prioritised); 2 stands for weight 2; tc. */
4305 #define UCM_REG_TM_WEIGHT 0xe00d4
4306 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4307 disregarded; acknowledge output is deasserted; all other signals are
4308 treated as usual; if 1 - normal activity. */
4309 #define UCM_REG_TSEM_IFEN 0xe0024
4310 /* [RC 1] Set when the message length mismatch (relative to last indication)
4311 at the tsem interface is detected. */
4312 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
4313 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4314 weight 8 (the most prioritised); 1 stands for weight 1(least
4315 prioritised); 2 stands for weight 2; tc. */
4316 #define UCM_REG_TSEM_WEIGHT 0xe00b4
4317 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4318 acknowledge output is deasserted; all other signals are treated as usual;
4319 if 1 - normal activity. */
4320 #define UCM_REG_UCM_CFC_IFEN 0xe0044
4321 /* [RW 11] Interrupt mask register #0 read/write */
4322 #define UCM_REG_UCM_INT_MASK 0xe01d4
4323 /* [R 11] Interrupt register #0 read */
4324 #define UCM_REG_UCM_INT_STS 0xe01c8
4325 /* [R 27] Parity register #0 read */
4326 #define UCM_REG_UCM_PRTY_STS 0xe01d8
4327 /* [RC 27] Parity register #0 read clear */
4328 #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
4329 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
4330 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4331 Is used to determine the number of the AG context REG-pairs written back;
4332 when the Reg1WbFlg isn't set. */
4333 #define UCM_REG_UCM_REG0_SZ 0xe00dc
4334 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4335 disregarded; valid is deasserted; all other signals are treated as usual;
4336 if 1 - normal activity. */
4337 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
4338 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4339 disregarded; valid is deasserted; all other signals are treated as usual;
4340 if 1 - normal activity. */
4341 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
4342 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4343 disregarded; acknowledge output is deasserted; all other signals are
4344 treated as usual; if 1 - normal activity. */
4345 #define UCM_REG_UCM_TM_IFEN 0xe0020
4346 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4347 disregarded; valid is deasserted; all other signals are treated as usual;
4348 if 1 - normal activity. */
4349 #define UCM_REG_UCM_UQM_IFEN 0xe000c
4350 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4351 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
4352 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4353 the initial credit value; read returns the current value of the credit
4354 counter. Must be initialized to 32 at start-up. */
4355 #define UCM_REG_UQM_INIT_CRD 0xe0220
4356 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4357 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4358 prioritised); 2 stands for weight 2; tc. */
4359 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
4360 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4361 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4362 prioritised); 2 stands for weight 2; tc. */
4363 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
4364 /* [RW 28] The CM header value for QM request (primary). */
4365 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
4366 /* [RW 28] The CM header value for QM request (secondary). */
4367 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
4368 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4369 acknowledge output is deasserted; all other signals are treated as usual;
4370 if 1 - normal activity. */
4371 #define UCM_REG_UQM_UCM_IFEN 0xe0014
4372 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4373 acknowledge output is deasserted; all other signals are treated as usual;
4374 if 1 - normal activity. */
4375 #define UCM_REG_USDM_IFEN 0xe0018
4376 /* [RC 1] Set when the message length mismatch (relative to last indication)
4377 at the SDM interface is detected. */
4378 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
4379 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4380 weight 8 (the most prioritised); 1 stands for weight 1(least
4381 prioritised); 2 stands for weight 2; tc. */
4382 #define UCM_REG_USDM_WEIGHT 0xe00c8
4383 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
4384 disregarded; acknowledge output is deasserted; all other signals are
4385 treated as usual; if 1 - normal activity. */
4386 #define UCM_REG_XSEM_IFEN 0xe002c
4387 /* [RC 1] Set when the message length mismatch (relative to last indication)
4388 at the xsem interface isdetected. */
4389 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
4390 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
4391 weight 8 (the most prioritised); 1 stands for weight 1(least
4392 prioritised); 2 stands for weight 2; tc. */
4393 #define UCM_REG_XSEM_WEIGHT 0xe00bc
4394 /* [RW 20] Indirect access to the descriptor table of the XX protection
4395 mechanism. The fields are:[5:0] - message length; 14:6] - message
4396 pointer; 19:15] - next pointer. */
4397 #define UCM_REG_XX_DESCR_TABLE 0xe0280
4398 #define UCM_REG_XX_DESCR_TABLE_SIZE 32
4399 /* [R 6] Use to read the XX protection Free counter. */
4400 #define UCM_REG_XX_FREE 0xe016c
4401 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4402 of the Input Stage XX protection buffer by the XX protection pending
4403 messages. Write writes the initial credit value; read returns the current
4404 value of the credit counter. Must be initialized to 12 at start-up. */
4405 #define UCM_REG_XX_INIT_CRD 0xe0224
4406 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4407 protection. ~ucm_registers_xx_free.xx_free read on read. */
4408 #define UCM_REG_XX_MSG_NUM 0xe0228
4409 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4410 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
4411 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4412 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
4414 #define UCM_REG_XX_TABLE 0xe0300
4415 /* [RW 8] The event id for aggregated interrupt 0 */
4416 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
4417 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
4418 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
4419 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
4420 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
4421 #define USDM_REG_AGG_INT_EVENT_6 0xc4050
4422 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4423 or auto-mask-mode (1) */
4424 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
4425 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
4426 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
4427 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
4428 #define USDM_REG_AGG_INT_MODE_6 0xc41d0
4429 /* [RW 1] The T bit for aggregated interrupt 5 */
4430 #define USDM_REG_AGG_INT_T_5 0xc40cc
4431 #define USDM_REG_AGG_INT_T_6 0xc40d0
4432 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4433 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
4434 /* [RW 16] The maximum value of the completion counter #0 */
4435 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
4436 /* [RW 16] The maximum value of the completion counter #1 */
4437 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
4438 /* [RW 16] The maximum value of the completion counter #2 */
4439 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
4440 /* [RW 16] The maximum value of the completion counter #3 */
4441 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
4442 /* [RW 13] The start address in the internal RAM for the completion
4444 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
4445 #define USDM_REG_ENABLE_IN1 0xc4238
4446 #define USDM_REG_ENABLE_IN2 0xc423c
4447 #define USDM_REG_ENABLE_OUT1 0xc4240
4448 #define USDM_REG_ENABLE_OUT2 0xc4244
4449 /* [RW 4] The initial number of messages that can be sent to the pxp control
4450 interface without receiving any ACK. */
4451 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
4452 /* [ST 32] The number of ACK after placement messages received */
4453 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
4454 /* [ST 32] The number of packet end messages received from the parser */
4455 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
4456 /* [ST 32] The number of requests received from the pxp async if */
4457 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
4458 /* [ST 32] The number of commands received in queue 0 */
4459 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
4460 /* [ST 32] The number of commands received in queue 10 */
4461 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
4462 /* [ST 32] The number of commands received in queue 11 */
4463 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
4464 /* [ST 32] The number of commands received in queue 1 */
4465 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
4466 /* [ST 32] The number of commands received in queue 2 */
4467 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
4468 /* [ST 32] The number of commands received in queue 3 */
4469 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
4470 /* [ST 32] The number of commands received in queue 4 */
4471 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
4472 /* [ST 32] The number of commands received in queue 5 */
4473 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
4474 /* [ST 32] The number of commands received in queue 6 */
4475 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
4476 /* [ST 32] The number of commands received in queue 7 */
4477 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
4478 /* [ST 32] The number of commands received in queue 8 */
4479 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
4480 /* [ST 32] The number of commands received in queue 9 */
4481 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
4482 /* [RW 13] The start address in the internal RAM for the packet end message */
4483 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
4484 /* [RW 13] The start address in the internal RAM for queue counters */
4485 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
4486 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4487 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
4488 /* [R 1] parser fifo empty in sdm_sync block */
4489 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
4490 /* [R 1] parser serial fifo empty in sdm_sync block */
4491 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
4492 /* [RW 32] Tick for timer counter. Applicable only when
4493 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
4494 #define USDM_REG_TIMER_TICK 0xc4000
4495 /* [RW 32] Interrupt mask register #0 read/write */
4496 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
4497 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
4498 /* [R 32] Interrupt register #0 read */
4499 #define USDM_REG_USDM_INT_STS_0 0xc4294
4500 #define USDM_REG_USDM_INT_STS_1 0xc42a4
4501 /* [RW 11] Parity mask register #0 read/write */
4502 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
4503 /* [R 11] Parity register #0 read */
4504 #define USDM_REG_USDM_PRTY_STS 0xc42b4
4505 /* [RC 11] Parity register #0 read clear */
4506 #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
4507 /* [RW 5] The number of time_slots in the arbitration cycle */
4508 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
4509 /* [RW 3] The source that is associated with arbitration element 0. Source
4510 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4511 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4512 #define USEM_REG_ARB_ELEMENT0 0x300020
4513 /* [RW 3] The source that is associated with arbitration element 1. Source
4514 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4515 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4516 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
4517 #define USEM_REG_ARB_ELEMENT1 0x300024
4518 /* [RW 3] The source that is associated with arbitration element 2. Source
4519 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4520 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4521 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4522 and ~usem_registers_arb_element1.arb_element1 */
4523 #define USEM_REG_ARB_ELEMENT2 0x300028
4524 /* [RW 3] The source that is associated with arbitration element 3. Source
4525 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4526 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4527 not be equal to register ~usem_registers_arb_element0.arb_element0 and
4528 ~usem_registers_arb_element1.arb_element1 and
4529 ~usem_registers_arb_element2.arb_element2 */
4530 #define USEM_REG_ARB_ELEMENT3 0x30002c
4531 /* [RW 3] The source that is associated with arbitration element 4. Source
4532 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4533 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4534 Could not be equal to register ~usem_registers_arb_element0.arb_element0
4535 and ~usem_registers_arb_element1.arb_element1 and
4536 ~usem_registers_arb_element2.arb_element2 and
4537 ~usem_registers_arb_element3.arb_element3 */
4538 #define USEM_REG_ARB_ELEMENT4 0x300030
4539 #define USEM_REG_ENABLE_IN 0x3000a4
4540 #define USEM_REG_ENABLE_OUT 0x3000a8
4541 /* [RW 32] This address space contains all registers and memories that are
4542 placed in SEM_FAST block. The SEM_FAST registers are described in
4543 appendix B. In order to access the sem_fast registers the base address
4544 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
4545 #define USEM_REG_FAST_MEMORY 0x320000
4546 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
4548 #define USEM_REG_FIC0_DISABLE 0x300224
4549 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
4551 #define USEM_REG_FIC1_DISABLE 0x300234
4552 /* [RW 15] Interrupt table Read and write access to it is not possible in
4553 the middle of the work */
4554 #define USEM_REG_INT_TABLE 0x300400
4555 /* [ST 24] Statistics register. The number of messages that entered through
4557 #define USEM_REG_MSG_NUM_FIC0 0x300000
4558 /* [ST 24] Statistics register. The number of messages that entered through
4560 #define USEM_REG_MSG_NUM_FIC1 0x300004
4561 /* [ST 24] Statistics register. The number of messages that were sent to
4563 #define USEM_REG_MSG_NUM_FOC0 0x300008
4564 /* [ST 24] Statistics register. The number of messages that were sent to
4566 #define USEM_REG_MSG_NUM_FOC1 0x30000c
4567 /* [ST 24] Statistics register. The number of messages that were sent to
4569 #define USEM_REG_MSG_NUM_FOC2 0x300010
4570 /* [ST 24] Statistics register. The number of messages that were sent to
4572 #define USEM_REG_MSG_NUM_FOC3 0x300014
4573 /* [RW 1] Disables input messages from the passive buffer May be updated
4574 during run_time by the microcode */
4575 #define USEM_REG_PAS_DISABLE 0x30024c
4576 /* [WB 128] Debug only. Passive buffer memory */
4577 #define USEM_REG_PASSIVE_BUFFER 0x302000
4578 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4579 #define USEM_REG_PRAM 0x340000
4580 /* [R 16] Valid sleeping threads indication have bit per thread */
4581 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
4582 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
4583 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
4584 /* [RW 16] List of free threads . There is a bit per thread. */
4585 #define USEM_REG_THREADS_LIST 0x3002e4
4586 /* [RW 3] The arbitration scheme of time_slot 0 */
4587 #define USEM_REG_TS_0_AS 0x300038
4588 /* [RW 3] The arbitration scheme of time_slot 10 */
4589 #define USEM_REG_TS_10_AS 0x300060
4590 /* [RW 3] The arbitration scheme of time_slot 11 */
4591 #define USEM_REG_TS_11_AS 0x300064
4592 /* [RW 3] The arbitration scheme of time_slot 12 */
4593 #define USEM_REG_TS_12_AS 0x300068
4594 /* [RW 3] The arbitration scheme of time_slot 13 */
4595 #define USEM_REG_TS_13_AS 0x30006c
4596 /* [RW 3] The arbitration scheme of time_slot 14 */
4597 #define USEM_REG_TS_14_AS 0x300070
4598 /* [RW 3] The arbitration scheme of time_slot 15 */
4599 #define USEM_REG_TS_15_AS 0x300074
4600 /* [RW 3] The arbitration scheme of time_slot 16 */
4601 #define USEM_REG_TS_16_AS 0x300078
4602 /* [RW 3] The arbitration scheme of time_slot 17 */
4603 #define USEM_REG_TS_17_AS 0x30007c
4604 /* [RW 3] The arbitration scheme of time_slot 18 */
4605 #define USEM_REG_TS_18_AS 0x300080
4606 /* [RW 3] The arbitration scheme of time_slot 1 */
4607 #define USEM_REG_TS_1_AS 0x30003c
4608 /* [RW 3] The arbitration scheme of time_slot 2 */
4609 #define USEM_REG_TS_2_AS 0x300040
4610 /* [RW 3] The arbitration scheme of time_slot 3 */
4611 #define USEM_REG_TS_3_AS 0x300044
4612 /* [RW 3] The arbitration scheme of time_slot 4 */
4613 #define USEM_REG_TS_4_AS 0x300048
4614 /* [RW 3] The arbitration scheme of time_slot 5 */
4615 #define USEM_REG_TS_5_AS 0x30004c
4616 /* [RW 3] The arbitration scheme of time_slot 6 */
4617 #define USEM_REG_TS_6_AS 0x300050
4618 /* [RW 3] The arbitration scheme of time_slot 7 */
4619 #define USEM_REG_TS_7_AS 0x300054
4620 /* [RW 3] The arbitration scheme of time_slot 8 */
4621 #define USEM_REG_TS_8_AS 0x300058
4622 /* [RW 3] The arbitration scheme of time_slot 9 */
4623 #define USEM_REG_TS_9_AS 0x30005c
4624 /* [RW 32] Interrupt mask register #0 read/write */
4625 #define USEM_REG_USEM_INT_MASK_0 0x300110
4626 #define USEM_REG_USEM_INT_MASK_1 0x300120
4627 /* [R 32] Interrupt register #0 read */
4628 #define USEM_REG_USEM_INT_STS_0 0x300104
4629 #define USEM_REG_USEM_INT_STS_1 0x300114
4630 /* [RW 32] Parity mask register #0 read/write */
4631 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
4632 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
4633 /* [R 32] Parity register #0 read */
4634 #define USEM_REG_USEM_PRTY_STS_0 0x300124
4635 #define USEM_REG_USEM_PRTY_STS_1 0x300134
4636 /* [RC 32] Parity register #0 read clear */
4637 #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
4638 #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
4639 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4640 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4641 #define USEM_REG_VFPF_ERR_NUM 0x300380
4642 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
4643 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
4644 #define VFC_REG_MEMORIES_RST 0x1943c
4645 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4646 * [12:8] of the address should be the offset within the accessed LCID
4647 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4648 * LCID100. The RBC address should be 13'ha64. */
4649 #define XCM_REG_AG_CTX 0x28000
4650 /* [RW 2] The queue index for registration on Aux1 counter flag. */
4651 #define XCM_REG_AUX1_Q 0x20134
4652 /* [RW 2] Per each decision rule the queue index to register to. */
4653 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
4654 /* [R 5] Used to read the XX protection CAM occupancy counter. */
4655 #define XCM_REG_CAM_OCCUP 0x20244
4656 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4657 disregarded; valid output is deasserted; all other signals are treated as
4658 usual; if 1 - normal activity. */
4659 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
4660 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4661 are disregarded; all other signals are treated as usual; if 1 - normal
4663 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
4664 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4665 disregarded; valid output is deasserted; all other signals are treated as
4666 usual; if 1 - normal activity. */
4667 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
4668 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4669 input is disregarded; all other signals are treated as usual; if 1 -
4671 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
4672 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4673 the initial credit value; read returns the current value of the credit
4674 counter. Must be initialized to 1 at start-up. */
4675 #define XCM_REG_CFC_INIT_CRD 0x20404
4676 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4677 weight 8 (the most prioritised); 1 stands for weight 1(least
4678 prioritised); 2 stands for weight 2; tc. */
4679 #define XCM_REG_CP_WEIGHT 0x200dc
4680 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4681 disregarded; acknowledge output is deasserted; all other signals are
4682 treated as usual; if 1 - normal activity. */
4683 #define XCM_REG_CSEM_IFEN 0x20028
4684 /* [RC 1] Set at message length mismatch (relative to last indication) at
4685 the csem interface. */
4686 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
4687 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4688 weight 8 (the most prioritised); 1 stands for weight 1(least
4689 prioritised); 2 stands for weight 2; tc. */
4690 #define XCM_REG_CSEM_WEIGHT 0x200c4
4691 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4692 disregarded; acknowledge output is deasserted; all other signals are
4693 treated as usual; if 1 - normal activity. */
4694 #define XCM_REG_DORQ_IFEN 0x20030
4695 /* [RC 1] Set at message length mismatch (relative to last indication) at
4696 the dorq interface. */
4697 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
4698 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
4699 weight 8 (the most prioritised); 1 stands for weight 1(least
4700 prioritised); 2 stands for weight 2; tc. */
4701 #define XCM_REG_DORQ_WEIGHT 0x200cc
4702 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
4703 #define XCM_REG_ERR_EVNT_ID 0x200b0
4704 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
4705 #define XCM_REG_ERR_XCM_HDR 0x200ac
4706 /* [RW 8] The Event ID for Timers expiration. */
4707 #define XCM_REG_EXPR_EVNT_ID 0x200b4
4708 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4709 writes the initial credit value; read returns the current value of the
4710 credit counter. Must be initialized to 64 at start-up. */
4711 #define XCM_REG_FIC0_INIT_CRD 0x2040c
4712 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4713 writes the initial credit value; read returns the current value of the
4714 credit counter. Must be initialized to 64 at start-up. */
4715 #define XCM_REG_FIC1_INIT_CRD 0x20410
4716 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
4717 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
4718 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
4719 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
4720 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
4721 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
4722 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
4723 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
4724 #define XCM_REG_GR_ARB_TYPE 0x2020c
4725 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4726 highest priority is 3. It is supposed that the Channel group is the
4727 compliment of the other 3 groups. */
4728 #define XCM_REG_GR_LD0_PR 0x20214
4729 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4730 highest priority is 3. It is supposed that the Channel group is the
4731 compliment of the other 3 groups. */
4732 #define XCM_REG_GR_LD1_PR 0x20218
4733 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
4734 disregarded; acknowledge output is deasserted; all other signals are
4735 treated as usual; if 1 - normal activity. */
4736 #define XCM_REG_NIG0_IFEN 0x20038
4737 /* [RC 1] Set at message length mismatch (relative to last indication) at
4738 the nig0 interface. */
4739 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
4740 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
4741 weight 8 (the most prioritised); 1 stands for weight 1(least
4742 prioritised); 2 stands for weight 2; tc. */
4743 #define XCM_REG_NIG0_WEIGHT 0x200d4
4744 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
4745 disregarded; acknowledge output is deasserted; all other signals are
4746 treated as usual; if 1 - normal activity. */
4747 #define XCM_REG_NIG1_IFEN 0x2003c
4748 /* [RC 1] Set at message length mismatch (relative to last indication) at
4749 the nig1 interface. */
4750 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
4751 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
4752 sent to STORM; for a specific connection type. The double REG-pairs are
4753 used in order to align to STORM context row size of 128 bits. The offset
4754 of these data in the STORM context is always 0. Index _i stands for the
4755 connection type (one of 16). */
4756 #define XCM_REG_N_SM_CTX_LD_0 0x20060
4757 #define XCM_REG_N_SM_CTX_LD_1 0x20064
4758 #define XCM_REG_N_SM_CTX_LD_2 0x20068
4759 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
4760 #define XCM_REG_N_SM_CTX_LD_4 0x20070
4761 #define XCM_REG_N_SM_CTX_LD_5 0x20074
4762 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4763 acknowledge output is deasserted; all other signals are treated as usual;
4764 if 1 - normal activity. */
4765 #define XCM_REG_PBF_IFEN 0x20034
4766 /* [RC 1] Set at message length mismatch (relative to last indication) at
4767 the pbf interface. */
4768 #define XCM_REG_PBF_LENGTH_MIS 0x20234
4769 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4770 weight 8 (the most prioritised); 1 stands for weight 1(least
4771 prioritised); 2 stands for weight 2; tc. */
4772 #define XCM_REG_PBF_WEIGHT 0x200d0
4773 #define XCM_REG_PHYS_QNUM3_0 0x20100
4774 #define XCM_REG_PHYS_QNUM3_1 0x20104
4775 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
4776 #define XCM_REG_STOP_EVNT_ID 0x200b8
4777 /* [RC 1] Set at message length mismatch (relative to last indication) at
4778 the STORM interface. */
4779 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
4780 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4781 weight 8 (the most prioritised); 1 stands for weight 1(least
4782 prioritised); 2 stands for weight 2; tc. */
4783 #define XCM_REG_STORM_WEIGHT 0x200bc
4784 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4785 disregarded; acknowledge output is deasserted; all other signals are
4786 treated as usual; if 1 - normal activity. */
4787 #define XCM_REG_STORM_XCM_IFEN 0x20010
4788 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
4789 writes the initial credit value; read returns the current value of the
4790 credit counter. Must be initialized to 4 at start-up. */
4791 #define XCM_REG_TM_INIT_CRD 0x2041c
4792 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4793 weight 8 (the most prioritised); 1 stands for weight 1(least
4794 prioritised); 2 stands for weight 2; tc. */
4795 #define XCM_REG_TM_WEIGHT 0x200ec
4796 /* [RW 28] The CM header for Timers expiration command. */
4797 #define XCM_REG_TM_XCM_HDR 0x200a8
4798 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4799 disregarded; acknowledge output is deasserted; all other signals are
4800 treated as usual; if 1 - normal activity. */
4801 #define XCM_REG_TM_XCM_IFEN 0x2001c
4802 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
4803 disregarded; acknowledge output is deasserted; all other signals are
4804 treated as usual; if 1 - normal activity. */
4805 #define XCM_REG_TSEM_IFEN 0x20024
4806 /* [RC 1] Set at message length mismatch (relative to last indication) at
4807 the tsem interface. */
4808 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
4809 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
4810 weight 8 (the most prioritised); 1 stands for weight 1(least
4811 prioritised); 2 stands for weight 2; tc. */
4812 #define XCM_REG_TSEM_WEIGHT 0x200c0
4813 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
4814 #define XCM_REG_UNA_GT_NXT_Q 0x20120
4815 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4816 disregarded; acknowledge output is deasserted; all other signals are
4817 treated as usual; if 1 - normal activity. */
4818 #define XCM_REG_USEM_IFEN 0x2002c
4819 /* [RC 1] Message length mismatch (relative to last indication) at the usem
4821 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
4822 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4823 weight 8 (the most prioritised); 1 stands for weight 1(least
4824 prioritised); 2 stands for weight 2; tc. */
4825 #define XCM_REG_USEM_WEIGHT 0x200c8
4826 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
4827 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
4828 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
4829 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
4830 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
4831 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
4832 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
4833 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
4834 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
4835 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
4836 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
4837 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
4838 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4839 acknowledge output is deasserted; all other signals are treated as usual;
4840 if 1 - normal activity. */
4841 #define XCM_REG_XCM_CFC_IFEN 0x20050
4842 /* [RW 14] Interrupt mask register #0 read/write */
4843 #define XCM_REG_XCM_INT_MASK 0x202b4
4844 /* [R 14] Interrupt register #0 read */
4845 #define XCM_REG_XCM_INT_STS 0x202a8
4846 /* [R 30] Parity register #0 read */
4847 #define XCM_REG_XCM_PRTY_STS 0x202b8
4848 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
4849 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4850 Is used to determine the number of the AG context REG-pairs written back;
4851 when the Reg1WbFlg isn't set. */
4852 #define XCM_REG_XCM_REG0_SZ 0x200f4
4853 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4854 disregarded; valid is deasserted; all other signals are treated as usual;
4855 if 1 - normal activity. */
4856 #define XCM_REG_XCM_STORM0_IFEN 0x20004
4857 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4858 disregarded; valid is deasserted; all other signals are treated as usual;
4859 if 1 - normal activity. */
4860 #define XCM_REG_XCM_STORM1_IFEN 0x20008
4861 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
4862 disregarded; acknowledge output is deasserted; all other signals are
4863 treated as usual; if 1 - normal activity. */
4864 #define XCM_REG_XCM_TM_IFEN 0x20020
4865 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4866 disregarded; valid is deasserted; all other signals are treated as usual;
4867 if 1 - normal activity. */
4868 #define XCM_REG_XCM_XQM_IFEN 0x2000c
4869 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
4870 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
4871 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
4872 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
4873 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4874 the initial credit value; read returns the current value of the credit
4875 counter. Must be initialized to 32 at start-up. */
4876 #define XCM_REG_XQM_INIT_CRD 0x20420
4877 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4878 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4879 prioritised); 2 stands for weight 2; tc. */
4880 #define XCM_REG_XQM_P_WEIGHT 0x200e4
4881 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4882 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
4883 prioritised); 2 stands for weight 2; tc. */
4884 #define XCM_REG_XQM_S_WEIGHT 0x200e8
4885 /* [RW 28] The CM header value for QM request (primary). */
4886 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
4887 /* [RW 28] The CM header value for QM request (secondary). */
4888 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
4889 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4890 acknowledge output is deasserted; all other signals are treated as usual;
4891 if 1 - normal activity. */
4892 #define XCM_REG_XQM_XCM_IFEN 0x20014
4893 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4894 acknowledge output is deasserted; all other signals are treated as usual;
4895 if 1 - normal activity. */
4896 #define XCM_REG_XSDM_IFEN 0x20018
4897 /* [RC 1] Set at message length mismatch (relative to last indication) at
4898 the SDM interface. */
4899 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
4900 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4901 weight 8 (the most prioritised); 1 stands for weight 1(least
4902 prioritised); 2 stands for weight 2; tc. */
4903 #define XCM_REG_XSDM_WEIGHT 0x200e0
4904 /* [RW 17] Indirect access to the descriptor table of the XX protection
4905 mechanism. The fields are: [5:0] - message length; 11:6] - message
4906 pointer; 16:12] - next pointer. */
4907 #define XCM_REG_XX_DESCR_TABLE 0x20480
4908 #define XCM_REG_XX_DESCR_TABLE_SIZE 32
4909 /* [R 6] Used to read the XX protection Free counter. */
4910 #define XCM_REG_XX_FREE 0x20240
4911 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
4912 of the Input Stage XX protection buffer by the XX protection pending
4913 messages. Max credit available - 3.Write writes the initial credit value;
4914 read returns the current value of the credit counter. Must be initialized
4915 to 2 at start-up. */
4916 #define XCM_REG_XX_INIT_CRD 0x20424
4917 /* [RW 6] The maximum number of pending messages; which may be stored in XX
4918 protection. ~xcm_registers_xx_free.xx_free read on read. */
4919 #define XCM_REG_XX_MSG_NUM 0x20428
4920 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
4921 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
4922 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
4923 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
4925 #define XCM_REG_XX_TABLE 0x20500
4926 /* [RW 8] The event id for aggregated interrupt 0 */
4927 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
4928 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
4929 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
4930 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
4931 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
4932 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
4933 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
4934 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
4935 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
4936 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
4937 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
4938 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
4939 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
4940 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
4941 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
4942 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
4943 or auto-mask-mode (1) */
4944 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
4945 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
4946 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
4947 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
4948 /* [RW 16] The maximum value of the completion counter #0 */
4949 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
4950 /* [RW 16] The maximum value of the completion counter #1 */
4951 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
4952 /* [RW 16] The maximum value of the completion counter #2 */
4953 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
4954 /* [RW 16] The maximum value of the completion counter #3 */
4955 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
4956 /* [RW 13] The start address in the internal RAM for the completion
4958 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
4959 #define XSDM_REG_ENABLE_IN1 0x166238
4960 #define XSDM_REG_ENABLE_IN2 0x16623c
4961 #define XSDM_REG_ENABLE_OUT1 0x166240
4962 #define XSDM_REG_ENABLE_OUT2 0x166244
4963 /* [RW 4] The initial number of messages that can be sent to the pxp control
4964 interface without receiving any ACK. */
4965 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
4966 /* [ST 32] The number of ACK after placement messages received */
4967 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
4968 /* [ST 32] The number of packet end messages received from the parser */
4969 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
4970 /* [ST 32] The number of requests received from the pxp async if */
4971 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
4972 /* [ST 32] The number of commands received in queue 0 */
4973 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
4974 /* [ST 32] The number of commands received in queue 10 */
4975 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
4976 /* [ST 32] The number of commands received in queue 11 */
4977 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
4978 /* [ST 32] The number of commands received in queue 1 */
4979 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
4980 /* [ST 32] The number of commands received in queue 3 */
4981 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
4982 /* [ST 32] The number of commands received in queue 4 */
4983 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
4984 /* [ST 32] The number of commands received in queue 5 */
4985 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
4986 /* [ST 32] The number of commands received in queue 6 */
4987 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
4988 /* [ST 32] The number of commands received in queue 7 */
4989 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
4990 /* [ST 32] The number of commands received in queue 8 */
4991 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
4992 /* [ST 32] The number of commands received in queue 9 */
4993 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
4994 /* [W 17] Generate an operation after completion; bit-16 is
4995 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and
4996 * bits 4:0 are the T124Param[4:0] */
4997 #define XSDM_REG_OPERATION_GEN 0x1664c4
4998 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
4999 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
5000 /* [R 1] parser fifo empty in sdm_sync block */
5001 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
5002 /* [R 1] parser serial fifo empty in sdm_sync block */
5003 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
5004 /* [RW 32] Tick for timer counter. Applicable only when
5005 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
5006 #define XSDM_REG_TIMER_TICK 0x166000
5007 /* [RW 32] Interrupt mask register #0 read/write */
5008 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
5009 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
5010 /* [R 32] Interrupt register #0 read */
5011 #define XSDM_REG_XSDM_INT_STS_0 0x166290
5012 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
5013 /* [RW 11] Parity mask register #0 read/write */
5014 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
5015 /* [R 11] Parity register #0 read */
5016 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
5017 /* [RC 11] Parity register #0 read clear */
5018 #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
5019 /* [RW 5] The number of time_slots in the arbitration cycle */
5020 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
5021 /* [RW 3] The source that is associated with arbitration element 0. Source
5022 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5023 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5024 #define XSEM_REG_ARB_ELEMENT0 0x280020
5025 /* [RW 3] The source that is associated with arbitration element 1. Source
5026 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5027 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5028 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
5029 #define XSEM_REG_ARB_ELEMENT1 0x280024
5030 /* [RW 3] The source that is associated with arbitration element 2. Source
5031 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5032 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5033 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5034 and ~xsem_registers_arb_element1.arb_element1 */
5035 #define XSEM_REG_ARB_ELEMENT2 0x280028
5036 /* [RW 3] The source that is associated with arbitration element 3. Source
5037 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5038 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5039 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
5040 ~xsem_registers_arb_element1.arb_element1 and
5041 ~xsem_registers_arb_element2.arb_element2 */
5042 #define XSEM_REG_ARB_ELEMENT3 0x28002c
5043 /* [RW 3] The source that is associated with arbitration element 4. Source
5044 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5045 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5046 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
5047 and ~xsem_registers_arb_element1.arb_element1 and
5048 ~xsem_registers_arb_element2.arb_element2 and
5049 ~xsem_registers_arb_element3.arb_element3 */
5050 #define XSEM_REG_ARB_ELEMENT4 0x280030
5051 #define XSEM_REG_ENABLE_IN 0x2800a4
5052 #define XSEM_REG_ENABLE_OUT 0x2800a8
5053 /* [RW 32] This address space contains all registers and memories that are
5054 placed in SEM_FAST block. The SEM_FAST registers are described in
5055 appendix B. In order to access the sem_fast registers the base address
5056 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */
5057 #define XSEM_REG_FAST_MEMORY 0x2a0000
5058 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
5060 #define XSEM_REG_FIC0_DISABLE 0x280224
5061 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
5063 #define XSEM_REG_FIC1_DISABLE 0x280234
5064 /* [RW 15] Interrupt table Read and write access to it is not possible in
5065 the middle of the work */
5066 #define XSEM_REG_INT_TABLE 0x280400
5067 /* [ST 24] Statistics register. The number of messages that entered through
5069 #define XSEM_REG_MSG_NUM_FIC0 0x280000
5070 /* [ST 24] Statistics register. The number of messages that entered through
5072 #define XSEM_REG_MSG_NUM_FIC1 0x280004
5073 /* [ST 24] Statistics register. The number of messages that were sent to
5075 #define XSEM_REG_MSG_NUM_FOC0 0x280008
5076 /* [ST 24] Statistics register. The number of messages that were sent to
5078 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
5079 /* [ST 24] Statistics register. The number of messages that were sent to
5081 #define XSEM_REG_MSG_NUM_FOC2 0x280010
5082 /* [ST 24] Statistics register. The number of messages that were sent to
5084 #define XSEM_REG_MSG_NUM_FOC3 0x280014
5085 /* [RW 1] Disables input messages from the passive buffer May be updated
5086 during run_time by the microcode */
5087 #define XSEM_REG_PAS_DISABLE 0x28024c
5088 /* [WB 128] Debug only. Passive buffer memory */
5089 #define XSEM_REG_PASSIVE_BUFFER 0x282000
5090 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5091 #define XSEM_REG_PRAM 0x2c0000
5092 /* [R 16] Valid sleeping threads indication have bit per thread */
5093 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5094 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
5095 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5096 /* [RW 16] List of free threads . There is a bit per thread. */
5097 #define XSEM_REG_THREADS_LIST 0x2802e4
5098 /* [RW 3] The arbitration scheme of time_slot 0 */
5099 #define XSEM_REG_TS_0_AS 0x280038
5100 /* [RW 3] The arbitration scheme of time_slot 10 */
5101 #define XSEM_REG_TS_10_AS 0x280060
5102 /* [RW 3] The arbitration scheme of time_slot 11 */
5103 #define XSEM_REG_TS_11_AS 0x280064
5104 /* [RW 3] The arbitration scheme of time_slot 12 */
5105 #define XSEM_REG_TS_12_AS 0x280068
5106 /* [RW 3] The arbitration scheme of time_slot 13 */
5107 #define XSEM_REG_TS_13_AS 0x28006c
5108 /* [RW 3] The arbitration scheme of time_slot 14 */
5109 #define XSEM_REG_TS_14_AS 0x280070
5110 /* [RW 3] The arbitration scheme of time_slot 15 */
5111 #define XSEM_REG_TS_15_AS 0x280074
5112 /* [RW 3] The arbitration scheme of time_slot 16 */
5113 #define XSEM_REG_TS_16_AS 0x280078
5114 /* [RW 3] The arbitration scheme of time_slot 17 */
5115 #define XSEM_REG_TS_17_AS 0x28007c
5116 /* [RW 3] The arbitration scheme of time_slot 18 */
5117 #define XSEM_REG_TS_18_AS 0x280080
5118 /* [RW 3] The arbitration scheme of time_slot 1 */
5119 #define XSEM_REG_TS_1_AS 0x28003c
5120 /* [RW 3] The arbitration scheme of time_slot 2 */
5121 #define XSEM_REG_TS_2_AS 0x280040
5122 /* [RW 3] The arbitration scheme of time_slot 3 */
5123 #define XSEM_REG_TS_3_AS 0x280044
5124 /* [RW 3] The arbitration scheme of time_slot 4 */
5125 #define XSEM_REG_TS_4_AS 0x280048
5126 /* [RW 3] The arbitration scheme of time_slot 5 */
5127 #define XSEM_REG_TS_5_AS 0x28004c
5128 /* [RW 3] The arbitration scheme of time_slot 6 */
5129 #define XSEM_REG_TS_6_AS 0x280050
5130 /* [RW 3] The arbitration scheme of time_slot 7 */
5131 #define XSEM_REG_TS_7_AS 0x280054
5132 /* [RW 3] The arbitration scheme of time_slot 8 */
5133 #define XSEM_REG_TS_8_AS 0x280058
5134 /* [RW 3] The arbitration scheme of time_slot 9 */
5135 #define XSEM_REG_TS_9_AS 0x28005c
5136 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5137 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5138 #define XSEM_REG_VFPF_ERR_NUM 0x280380
5139 /* [RW 32] Interrupt mask register #0 read/write */
5140 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
5141 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
5142 /* [R 32] Interrupt register #0 read */
5143 #define XSEM_REG_XSEM_INT_STS_0 0x280104
5144 #define XSEM_REG_XSEM_INT_STS_1 0x280114
5145 /* [RW 32] Parity mask register #0 read/write */
5146 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5147 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
5148 /* [R 32] Parity register #0 read */
5149 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5150 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5151 /* [RC 32] Parity register #0 read clear */
5152 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5153 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
5154 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5155 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
5156 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5157 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
5158 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
5159 #define MCPR_NVM_COMMAND_DONE (1L<<3)
5160 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
5161 #define MCPR_NVM_COMMAND_LAST (1L<<8)
5162 #define MCPR_NVM_COMMAND_WR (1L<<5)
5163 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
5164 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
5165 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
5166 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
5167 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5168 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
5169 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
5170 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
5171 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
5172 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
5173 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
5174 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
5175 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
5176 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
5177 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
5178 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
5179 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
5180 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
5181 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
5182 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
5183 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
5184 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
5185 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
5186 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
5187 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
5188 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
5189 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
5190 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
5191 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
5192 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
5193 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
5194 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
5195 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
5196 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
5197 #define EMAC_LED_1000MB_OVERRIDE (1L<<1)
5198 #define EMAC_LED_100MB_OVERRIDE (1L<<2)
5199 #define EMAC_LED_10MB_OVERRIDE (1L<<3)
5200 #define EMAC_LED_2500MB_OVERRIDE (1L<<12)
5201 #define EMAC_LED_OVERRIDE (1L<<0)
5202 #define EMAC_LED_TRAFFIC (1L<<6)
5203 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
5204 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
5205 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
5206 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
5207 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
5208 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
5209 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
5210 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
5211 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
5212 #define EMAC_MODE_25G_MODE (1L<<5)
5213 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
5214 #define EMAC_MODE_PORT_GMII (2L<<2)
5215 #define EMAC_MODE_PORT_MII (1L<<2)
5216 #define EMAC_MODE_PORT_MII_10M (3L<<2)
5217 #define EMAC_MODE_RESET (1L<<0)
5218 #define EMAC_REG_EMAC_LED 0xc
5219 #define EMAC_REG_EMAC_MAC_MATCH 0x10
5220 #define EMAC_REG_EMAC_MDIO_COMM 0xac
5221 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
5222 #define EMAC_REG_EMAC_MODE 0x0
5223 #define EMAC_REG_EMAC_RX_MODE 0xc8
5224 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
5225 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
5226 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
5227 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
5228 #define EMAC_REG_EMAC_TX_MODE 0xbc
5229 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
5230 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
5231 #define EMAC_REG_RX_PFC_MODE 0x320
5232 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2)
5233 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1)
5234 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
5235 #define EMAC_REG_RX_PFC_PARAM 0x324
5236 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
5237 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16
5238 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
5239 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
5240 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
5241 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
5242 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
5243 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
5244 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
5245 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
5246 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
5247 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
5248 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
5249 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
5250 #define EMAC_RX_MODE_RESET (1L<<0)
5251 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
5252 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
5253 #define EMAC_TX_MODE_FLOW_EN (1L<<4)
5254 #define EMAC_TX_MODE_RESET (1L<<0)
5255 #define MISC_REGISTERS_GPIO_0 0
5256 #define MISC_REGISTERS_GPIO_1 1
5257 #define MISC_REGISTERS_GPIO_2 2
5258 #define MISC_REGISTERS_GPIO_3 3
5259 #define MISC_REGISTERS_GPIO_CLR_POS 16
5260 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
5261 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
5262 #define MISC_REGISTERS_GPIO_HIGH 1
5263 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
5264 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24
5265 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
5266 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1
5267 #define MISC_REGISTERS_GPIO_INT_SET_POS 16
5268 #define MISC_REGISTERS_GPIO_LOW 0
5269 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
5270 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
5271 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
5272 #define MISC_REGISTERS_GPIO_SET_POS 8
5273 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
5274 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
5275 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
5276 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
5277 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
5278 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
5279 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
5280 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
5281 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
5282 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
5283 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
5284 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
5285 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
5286 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
5287 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
5288 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
5289 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
5290 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
5291 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
5292 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
5293 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
5294 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
5295 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
5296 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
5297 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
5298 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
5299 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
5300 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
5301 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
5302 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
5303 #define MISC_REGISTERS_SPIO_4 4
5304 #define MISC_REGISTERS_SPIO_5 5
5305 #define MISC_REGISTERS_SPIO_7 7
5306 #define MISC_REGISTERS_SPIO_CLR_POS 16
5307 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
5308 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
5309 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
5310 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
5311 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
5312 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
5313 #define MISC_REGISTERS_SPIO_SET_POS 8
5314 #define HW_LOCK_DRV_FLAGS 10
5315 #define HW_LOCK_MAX_RESOURCE_VALUE 31
5316 #define HW_LOCK_RESOURCE_GPIO 1
5317 #define HW_LOCK_RESOURCE_MDIO 0
5318 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3
5319 #define HW_LOCK_RESOURCE_RESERVED_08 8
5320 #define HW_LOCK_RESOURCE_SPIO 2
5321 #define HW_LOCK_RESOURCE_UNDI 5
5322 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
5323 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
5324 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
5325 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
5326 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
5327 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
5328 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
5329 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
5330 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
5331 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
5332 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
5333 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
5334 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
5335 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
5336 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
5337 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
5338 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (1<<2)
5339 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (1<<5)
5340 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (1<<9)
5341 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
5342 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (1<<28)
5343 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (1<<31)
5344 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (1<<29)
5345 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (1<<30)
5346 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
5347 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
5348 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
5349 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
5350 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
5351 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
5352 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
5353 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
5354 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
5355 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
5356 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
5357 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
5358 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
5359 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
5360 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
5361 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
5362 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
5363 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
5364 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
5365 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
5366 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
5367 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
5368 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
5369 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
5370 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
5371 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
5372 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
5373 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
5374 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
5375 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
5376 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
5377 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
5378 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
5379 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
5380 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
5382 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3ffe0
5383 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
5385 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
5386 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
5387 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
5388 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
5389 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
5390 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
5391 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
5392 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
5393 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
5394 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
5395 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
5396 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
5397 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
5398 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
5399 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
5400 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
5402 /* storm asserts attention bits */
5403 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
5404 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
5405 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
5406 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
5408 /* mcp error attention bit */
5409 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
5411 /*E1H NIG status sync attention mapped to group 4-7*/
5412 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12
5413 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13
5414 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14
5415 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15
5416 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16
5417 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17
5418 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18
5419 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19
5422 #define LATCHED_ATTN_RBCR 23
5423 #define LATCHED_ATTN_RBCT 24
5424 #define LATCHED_ATTN_RBCN 25
5425 #define LATCHED_ATTN_RBCU 26
5426 #define LATCHED_ATTN_RBCP 27
5427 #define LATCHED_ATTN_TIMEOUT_GRC 28
5428 #define LATCHED_ATTN_RSVD_GRC 29
5429 #define LATCHED_ATTN_ROM_PARITY_MCP 30
5430 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
5431 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
5432 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
5434 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
5435 #define GENERAL_ATTEN_OFFSET(atten_name)\
5436 (1UL << ((94 + atten_name) % 32))
5438 * This file defines GRC base address for every block.
5439 * This file is included by chipsim, asm microcode and cpp microcode.
5440 * These values are used in Design.xml on regBase attribute
5441 * Use the base with the generated offsets of specific registers.
5444 #define GRCBASE_PXPCS 0x000000
5445 #define GRCBASE_PCICONFIG 0x002000
5446 #define GRCBASE_PCIREG 0x002400
5447 #define GRCBASE_EMAC0 0x008000
5448 #define GRCBASE_EMAC1 0x008400
5449 #define GRCBASE_DBU 0x008800
5450 #define GRCBASE_MISC 0x00A000
5451 #define GRCBASE_DBG 0x00C000
5452 #define GRCBASE_NIG 0x010000
5453 #define GRCBASE_XCM 0x020000
5454 #define GRCBASE_PRS 0x040000
5455 #define GRCBASE_SRCH 0x040400
5456 #define GRCBASE_TSDM 0x042000
5457 #define GRCBASE_TCM 0x050000
5458 #define GRCBASE_BRB1 0x060000
5459 #define GRCBASE_MCP 0x080000
5460 #define GRCBASE_UPB 0x0C1000
5461 #define GRCBASE_CSDM 0x0C2000
5462 #define GRCBASE_USDM 0x0C4000
5463 #define GRCBASE_CCM 0x0D0000
5464 #define GRCBASE_UCM 0x0E0000
5465 #define GRCBASE_CDU 0x101000
5466 #define GRCBASE_DMAE 0x102000
5467 #define GRCBASE_PXP 0x103000
5468 #define GRCBASE_CFC 0x104000
5469 #define GRCBASE_HC 0x108000
5470 #define GRCBASE_PXP2 0x120000
5471 #define GRCBASE_PBF 0x140000
5472 #define GRCBASE_XPB 0x161000
5473 #define GRCBASE_MSTAT0 0x162000
5474 #define GRCBASE_MSTAT1 0x162800
5475 #define GRCBASE_TIMERS 0x164000
5476 #define GRCBASE_XSDM 0x166000
5477 #define GRCBASE_QM 0x168000
5478 #define GRCBASE_DQ 0x170000
5479 #define GRCBASE_TSEM 0x180000
5480 #define GRCBASE_CSEM 0x200000
5481 #define GRCBASE_XSEM 0x280000
5482 #define GRCBASE_USEM 0x300000
5483 #define GRCBASE_MISC_AEU GRCBASE_MISC
5486 /* offset of configuration space in the pci core register */
5487 #define PCICFG_OFFSET 0x2000
5488 #define PCICFG_VENDOR_ID_OFFSET 0x00
5489 #define PCICFG_DEVICE_ID_OFFSET 0x02
5490 #define PCICFG_COMMAND_OFFSET 0x04
5491 #define PCICFG_COMMAND_IO_SPACE (1<<0)
5492 #define PCICFG_COMMAND_MEM_SPACE (1<<1)
5493 #define PCICFG_COMMAND_BUS_MASTER (1<<2)
5494 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3)
5495 #define PCICFG_COMMAND_MWI_CYCLES (1<<4)
5496 #define PCICFG_COMMAND_VGA_SNOOP (1<<5)
5497 #define PCICFG_COMMAND_PERR_ENA (1<<6)
5498 #define PCICFG_COMMAND_STEPPING (1<<7)
5499 #define PCICFG_COMMAND_SERR_ENA (1<<8)
5500 #define PCICFG_COMMAND_FAST_B2B (1<<9)
5501 #define PCICFG_COMMAND_INT_DISABLE (1<<10)
5502 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
5503 #define PCICFG_STATUS_OFFSET 0x06
5504 #define PCICFG_REVESION_ID_OFFSET 0x08
5505 #define PCICFG_CACHE_LINE_SIZE 0x0c
5506 #define PCICFG_LATENCY_TIMER 0x0d
5507 #define PCICFG_BAR_1_LOW 0x10
5508 #define PCICFG_BAR_1_HIGH 0x14
5509 #define PCICFG_BAR_2_LOW 0x18
5510 #define PCICFG_BAR_2_HIGH 0x1c
5511 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
5512 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
5513 #define PCICFG_INT_LINE 0x3c
5514 #define PCICFG_INT_PIN 0x3d
5515 #define PCICFG_PM_CAPABILITY 0x48
5516 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
5517 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19)
5518 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20)
5519 #define PCICFG_PM_CAPABILITY_DSI (1<<21)
5520 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
5521 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25)
5522 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26)
5523 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27)
5524 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28)
5525 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29)
5526 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30)
5527 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31)
5528 #define PCICFG_PM_CSR_OFFSET 0x4c
5529 #define PCICFG_PM_CSR_STATE (0x3<<0)
5530 #define PCICFG_PM_CSR_PME_ENABLE (1<<8)
5531 #define PCICFG_PM_CSR_PME_STATUS (1<<15)
5532 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
5533 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
5534 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
5535 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
5536 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
5537 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
5538 #define PCICFG_GRC_ADDRESS 0x78
5539 #define PCICFG_GRC_DATA 0x80
5540 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
5541 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
5542 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
5543 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
5544 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
5546 #define PCICFG_DEVICE_CONTROL 0xb4
5547 #define PCICFG_DEVICE_STATUS 0xb6
5548 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
5549 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1)
5550 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2)
5551 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3)
5552 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4)
5553 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5)
5554 #define PCICFG_LINK_CONTROL 0xbc
5557 #define BAR_USTRORM_INTMEM 0x400000
5558 #define BAR_CSTRORM_INTMEM 0x410000
5559 #define BAR_XSTRORM_INTMEM 0x420000
5560 #define BAR_TSTRORM_INTMEM 0x430000
5562 /* for accessing the IGU in case of status block ACK */
5563 #define BAR_IGU_INTMEM 0x440000
5565 #define BAR_DOORBELL_OFFSET 0x800000
5567 #define BAR_ME_REGISTER 0x450000
5569 /* config_2 offset */
5570 #define GRC_CONFIG_2_SIZE_REG 0x408
5571 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
5572 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
5573 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
5574 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
5575 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
5576 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
5577 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
5578 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
5579 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
5580 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
5581 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
5582 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
5583 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
5584 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
5585 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
5586 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
5587 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
5588 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
5589 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
5590 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
5591 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
5592 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
5593 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
5594 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
5595 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
5596 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
5597 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
5598 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
5599 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
5600 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
5601 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
5602 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
5603 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
5604 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
5605 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
5606 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
5607 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
5608 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
5609 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
5610 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
5612 /* config_3 offset */
5613 #define GRC_CONFIG_3_SIZE_REG 0x40c
5614 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
5615 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
5616 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
5617 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
5618 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
5619 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
5620 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
5622 #define GRC_BAR2_CONFIG 0x4e0
5623 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
5624 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
5625 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
5626 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
5627 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
5628 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
5629 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
5630 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
5631 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
5632 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
5633 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
5634 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
5635 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
5636 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
5637 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
5638 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
5639 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
5640 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
5642 #define PCI_PM_DATA_A 0x410
5643 #define PCI_PM_DATA_B 0x414
5644 #define PCI_ID_VAL1 0x434
5645 #define PCI_ID_VAL2 0x438
5647 #define PXPCS_TL_CONTROL_5 0x814
5648 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/
5649 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/
5650 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/
5651 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/
5652 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/
5653 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/
5654 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/
5655 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/
5656 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/
5657 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/
5658 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/
5659 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/
5660 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/
5661 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/
5662 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/
5663 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/
5664 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/
5665 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/
5666 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/
5667 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/
5668 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/
5669 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/
5670 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/
5671 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/
5672 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/
5673 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/
5674 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/
5675 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/
5676 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/
5677 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
5680 #define PXPCS_TL_FUNC345_STAT 0x854
5681 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */
5682 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\
5683 (1 << 28) /* Unsupported Request Error Status in function4, if \
5684 set, generate pcie_err_attn output when this error is seen. WC */
5685 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\
5686 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \
5687 generate pcie_err_attn output when this error is seen.. WC */
5688 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\
5689 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \
5690 generate pcie_err_attn output when this error is seen.. WC */
5691 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\
5692 (1 << 25) /* Receiver Overflow Status Status in function 4, if \
5693 set, generate pcie_err_attn output when this error is seen.. WC \
5695 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\
5696 (1 << 24) /* Unexpected Completion Status Status in function 4, \
5697 if set, generate pcie_err_attn output when this error is seen. WC \
5699 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\
5700 (1 << 23) /* Receive UR Statusin function 4. If set, generate \
5701 pcie_err_attn output when this error is seen. WC */
5702 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\
5703 (1 << 22) /* Completer Timeout Status Status in function 4, if \
5704 set, generate pcie_err_attn output when this error is seen. WC */
5705 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\
5706 (1 << 21) /* Flow Control Protocol Error Status Status in \
5707 function 4, if set, generate pcie_err_attn output when this error \
5709 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\
5710 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \
5711 generate pcie_err_attn output when this error is seen.. WC */
5712 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */
5713 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\
5714 (1 << 18) /* Unsupported Request Error Status in function3, if \
5715 set, generate pcie_err_attn output when this error is seen. WC */
5716 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\
5717 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \
5718 generate pcie_err_attn output when this error is seen.. WC */
5719 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\
5720 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \
5721 generate pcie_err_attn output when this error is seen.. WC */
5722 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\
5723 (1 << 15) /* Receiver Overflow Status Status in function 3, if \
5724 set, generate pcie_err_attn output when this error is seen.. WC \
5726 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\
5727 (1 << 14) /* Unexpected Completion Status Status in function 3, \
5728 if set, generate pcie_err_attn output when this error is seen. WC \
5730 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\
5731 (1 << 13) /* Receive UR Statusin function 3. If set, generate \
5732 pcie_err_attn output when this error is seen. WC */
5733 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\
5734 (1 << 12) /* Completer Timeout Status Status in function 3, if \
5735 set, generate pcie_err_attn output when this error is seen. WC */
5736 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\
5737 (1 << 11) /* Flow Control Protocol Error Status Status in \
5738 function 3, if set, generate pcie_err_attn output when this error \
5740 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\
5741 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \
5742 generate pcie_err_attn output when this error is seen.. WC */
5743 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */
5744 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\
5745 (1 << 8) /* Unsupported Request Error Status for Function 2, if \
5746 set, generate pcie_err_attn output when this error is seen. WC */
5747 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\
5748 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \
5749 generate pcie_err_attn output when this error is seen.. WC */
5750 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\
5751 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \
5752 generate pcie_err_attn output when this error is seen.. WC */
5753 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\
5754 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \
5755 set, generate pcie_err_attn output when this error is seen.. WC \
5757 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\
5758 (1 << 4) /* Unexpected Completion Status Status for Function 2, \
5759 if set, generate pcie_err_attn output when this error is seen. WC \
5761 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\
5762 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \
5763 pcie_err_attn output when this error is seen. WC */
5764 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\
5765 (1 << 2) /* Completer Timeout Status Status for Function 2, if \
5766 set, generate pcie_err_attn output when this error is seen. WC */
5767 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\
5768 (1 << 1) /* Flow Control Protocol Error Status Status for \
5769 Function 2, if set, generate pcie_err_attn output when this error \
5771 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\
5772 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
5773 generate pcie_err_attn output when this error is seen.. WC */
5776 #define PXPCS_TL_FUNC678_STAT 0x85C
5777 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */
5778 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\
5779 (1 << 28) /* Unsupported Request Error Status in function7, if \
5780 set, generate pcie_err_attn output when this error is seen. WC */
5781 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\
5782 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \
5783 generate pcie_err_attn output when this error is seen.. WC */
5784 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\
5785 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \
5786 generate pcie_err_attn output when this error is seen.. WC */
5787 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\
5788 (1 << 25) /* Receiver Overflow Status Status in function 7, if \
5789 set, generate pcie_err_attn output when this error is seen.. WC \
5791 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\
5792 (1 << 24) /* Unexpected Completion Status Status in function 7, \
5793 if set, generate pcie_err_attn output when this error is seen. WC \
5795 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\
5796 (1 << 23) /* Receive UR Statusin function 7. If set, generate \
5797 pcie_err_attn output when this error is seen. WC */
5798 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\
5799 (1 << 22) /* Completer Timeout Status Status in function 7, if \
5800 set, generate pcie_err_attn output when this error is seen. WC */
5801 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\
5802 (1 << 21) /* Flow Control Protocol Error Status Status in \
5803 function 7, if set, generate pcie_err_attn output when this error \
5805 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\
5806 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \
5807 generate pcie_err_attn output when this error is seen.. WC */
5808 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */
5809 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\
5810 (1 << 18) /* Unsupported Request Error Status in function6, if \
5811 set, generate pcie_err_attn output when this error is seen. WC */
5812 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\
5813 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \
5814 generate pcie_err_attn output when this error is seen.. WC */
5815 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\
5816 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \
5817 generate pcie_err_attn output when this error is seen.. WC */
5818 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\
5819 (1 << 15) /* Receiver Overflow Status Status in function 6, if \
5820 set, generate pcie_err_attn output when this error is seen.. WC \
5822 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\
5823 (1 << 14) /* Unexpected Completion Status Status in function 6, \
5824 if set, generate pcie_err_attn output when this error is seen. WC \
5826 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\
5827 (1 << 13) /* Receive UR Statusin function 6. If set, generate \
5828 pcie_err_attn output when this error is seen. WC */
5829 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\
5830 (1 << 12) /* Completer Timeout Status Status in function 6, if \
5831 set, generate pcie_err_attn output when this error is seen. WC */
5832 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\
5833 (1 << 11) /* Flow Control Protocol Error Status Status in \
5834 function 6, if set, generate pcie_err_attn output when this error \
5836 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\
5837 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \
5838 generate pcie_err_attn output when this error is seen.. WC */
5839 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */
5840 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\
5841 (1 << 8) /* Unsupported Request Error Status for Function 5, if \
5842 set, generate pcie_err_attn output when this error is seen. WC */
5843 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\
5844 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \
5845 generate pcie_err_attn output when this error is seen.. WC */
5846 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\
5847 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \
5848 generate pcie_err_attn output when this error is seen.. WC */
5849 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\
5850 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \
5851 set, generate pcie_err_attn output when this error is seen.. WC \
5853 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\
5854 (1 << 4) /* Unexpected Completion Status Status for Function 5, \
5855 if set, generate pcie_err_attn output when this error is seen. WC \
5857 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\
5858 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \
5859 pcie_err_attn output when this error is seen. WC */
5860 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\
5861 (1 << 2) /* Completer Timeout Status Status for Function 5, if \
5862 set, generate pcie_err_attn output when this error is seen. WC */
5863 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\
5864 (1 << 1) /* Flow Control Protocol Error Status Status for \
5865 Function 5, if set, generate pcie_err_attn output when this error \
5867 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\
5868 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
5869 generate pcie_err_attn output when this error is seen.. WC */
5872 #define BAR_USTRORM_INTMEM 0x400000
5873 #define BAR_CSTRORM_INTMEM 0x410000
5874 #define BAR_XSTRORM_INTMEM 0x420000
5875 #define BAR_TSTRORM_INTMEM 0x430000
5877 /* for accessing the IGU in case of status block ACK */
5878 #define BAR_IGU_INTMEM 0x440000
5880 #define BAR_DOORBELL_OFFSET 0x800000
5882 #define BAR_ME_REGISTER 0x450000
5883 #define ME_REG_PF_NUM_SHIFT 0
5884 #define ME_REG_PF_NUM\
5885 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */
5886 #define ME_REG_VF_VALID (1<<8)
5887 #define ME_REG_VF_NUM_SHIFT 9
5888 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
5889 #define ME_REG_VF_ERR (0x1<<3)
5890 #define ME_REG_ABS_PF_NUM_SHIFT 16
5891 #define ME_REG_ABS_PF_NUM\
5892 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */
5895 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
5896 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
5897 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
5898 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
5899 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
5901 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
5902 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
5903 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
5904 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
5905 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
5906 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
5907 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
5908 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
5909 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
5910 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
5911 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
5912 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
5913 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
5914 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
5915 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
5916 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
5918 #define MDIO_REG_BANK_RX0 0x80b0
5919 #define MDIO_RX0_RX_STATUS 0x10
5920 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
5921 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
5922 #define MDIO_RX0_RX_EQ_BOOST 0x1c
5923 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5924 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
5926 #define MDIO_REG_BANK_RX1 0x80c0
5927 #define MDIO_RX1_RX_EQ_BOOST 0x1c
5928 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5929 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
5931 #define MDIO_REG_BANK_RX2 0x80d0
5932 #define MDIO_RX2_RX_EQ_BOOST 0x1c
5933 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5934 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
5936 #define MDIO_REG_BANK_RX3 0x80e0
5937 #define MDIO_RX3_RX_EQ_BOOST 0x1c
5938 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5939 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
5941 #define MDIO_REG_BANK_RX_ALL 0x80f0
5942 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
5943 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
5944 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
5946 #define MDIO_REG_BANK_TX0 0x8060
5947 #define MDIO_TX0_TX_DRIVER 0x17
5948 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5949 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5950 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5951 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5952 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5953 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5954 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5955 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5956 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5958 #define MDIO_REG_BANK_TX1 0x8070
5959 #define MDIO_TX1_TX_DRIVER 0x17
5960 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5961 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5962 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5963 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5964 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5965 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5966 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5967 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5968 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5970 #define MDIO_REG_BANK_TX2 0x8080
5971 #define MDIO_TX2_TX_DRIVER 0x17
5972 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5973 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5974 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5975 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5976 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5977 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5978 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5979 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5980 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5982 #define MDIO_REG_BANK_TX3 0x8090
5983 #define MDIO_TX3_TX_DRIVER 0x17
5984 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
5985 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
5986 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
5987 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
5988 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
5989 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
5990 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
5991 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
5992 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
5994 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
5995 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
5997 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
5998 #define MDIO_BLOCK1_LANE_CTRL0 0x15
5999 #define MDIO_BLOCK1_LANE_CTRL1 0x16
6000 #define MDIO_BLOCK1_LANE_CTRL2 0x17
6001 #define MDIO_BLOCK1_LANE_PRBS 0x19
6003 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
6004 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
6005 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
6006 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
6007 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
6008 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
6009 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
6010 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
6011 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
6012 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
6014 #define MDIO_REG_BANK_GP_STATUS 0x8120
6015 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
6016 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
6017 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
6018 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
6019 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
6020 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
6021 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
6022 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
6023 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
6024 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
6025 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
6026 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
6027 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
6028 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
6029 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
6030 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
6031 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
6032 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
6033 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
6034 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
6035 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
6036 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
6037 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
6038 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
6039 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
6042 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
6043 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
6044 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
6045 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
6046 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
6047 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
6048 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
6050 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
6051 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
6052 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
6053 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
6054 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
6055 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
6056 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
6057 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
6058 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
6059 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
6060 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
6061 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
6062 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
6063 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
6064 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
6065 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
6066 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
6067 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
6068 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
6069 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
6070 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
6071 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
6072 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
6073 #define MDIO_SERDES_DIGITAL_MISC1 0x18
6074 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
6075 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
6076 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
6077 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
6078 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
6079 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
6080 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
6081 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
6082 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
6083 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
6084 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
6085 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
6086 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
6087 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
6088 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
6089 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
6090 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
6091 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
6093 #define MDIO_REG_BANK_OVER_1G 0x8320
6094 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
6095 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
6096 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
6097 #define MDIO_OVER_1G_UP1 0x19
6098 #define MDIO_OVER_1G_UP1_2_5G 0x0001
6099 #define MDIO_OVER_1G_UP1_5G 0x0002
6100 #define MDIO_OVER_1G_UP1_6G 0x0004
6101 #define MDIO_OVER_1G_UP1_10G 0x0010
6102 #define MDIO_OVER_1G_UP1_10GH 0x0008
6103 #define MDIO_OVER_1G_UP1_12G 0x0020
6104 #define MDIO_OVER_1G_UP1_12_5G 0x0040
6105 #define MDIO_OVER_1G_UP1_13G 0x0080
6106 #define MDIO_OVER_1G_UP1_15G 0x0100
6107 #define MDIO_OVER_1G_UP1_16G 0x0200
6108 #define MDIO_OVER_1G_UP2 0x1A
6109 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
6110 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
6111 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
6112 #define MDIO_OVER_1G_UP3 0x1B
6113 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
6114 #define MDIO_OVER_1G_LP_UP1 0x1C
6115 #define MDIO_OVER_1G_LP_UP2 0x1D
6116 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
6117 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
6118 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
6119 #define MDIO_OVER_1G_LP_UP3 0x1E
6121 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
6122 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
6123 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
6124 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
6126 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
6127 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
6128 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
6129 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
6131 #define MDIO_REG_BANK_CL73_USERB0 0x8370
6132 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
6133 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
6134 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
6135 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
6136 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
6137 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
6138 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
6139 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
6140 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
6141 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
6142 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
6144 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
6145 #define MDIO_AER_BLOCK_AER_REG 0x1E
6147 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
6148 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
6149 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
6150 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
6151 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
6152 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
6153 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
6154 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
6155 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
6156 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
6157 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
6158 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
6159 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
6160 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
6161 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
6162 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
6163 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
6164 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
6165 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
6166 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
6167 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
6168 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
6169 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
6170 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
6171 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
6172 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
6173 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
6174 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
6175 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
6176 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
6177 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
6178 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
6179 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
6180 Theotherbitsarereservedandshouldbezero*/
6181 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
6184 #define MDIO_PMA_DEVAD 0x1
6186 #define MDIO_PMA_REG_CTRL 0x0
6187 #define MDIO_PMA_REG_STATUS 0x1
6188 #define MDIO_PMA_REG_10G_CTRL2 0x7
6189 #define MDIO_PMA_REG_RX_SD 0xa
6191 #define MDIO_PMA_REG_BCM_CTRL 0x0096
6192 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
6193 #define MDIO_PMA_REG_RX_ALARM_CTRL 0x9000
6194 #define MDIO_PMA_REG_TX_ALARM_CTRL 0x9001
6195 #define MDIO_PMA_REG_LASI_CTRL 0x9002
6196 #define MDIO_PMA_REG_RX_ALARM 0x9003
6197 #define MDIO_PMA_REG_TX_ALARM 0x9004
6198 #define MDIO_PMA_REG_LASI_STATUS 0x9005
6199 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
6200 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
6201 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
6202 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
6203 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
6204 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
6205 #define MDIO_PMA_REG_GEN_CTRL 0xca10
6206 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
6207 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
6208 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
6209 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
6210 #define MDIO_PMA_REG_ROM_VER1 0xca19
6211 #define MDIO_PMA_REG_ROM_VER2 0xca1a
6212 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
6213 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
6214 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
6215 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
6216 #define MDIO_PMA_REG_LRM_MODE 0xca3f
6217 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
6218 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
6220 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
6221 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
6222 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
6223 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
6224 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
6225 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
6226 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
6227 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
6228 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
6229 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
6230 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
6231 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
6233 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
6234 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
6235 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
6236 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
6237 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
6238 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
6239 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
6240 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
6241 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
6243 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
6245 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
6246 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
6247 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
6248 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
6250 #define MDIO_PMA_REG_7101_RESET 0xc000
6251 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
6252 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
6253 #define MDIO_PMA_REG_7101_VER1 0xc026
6254 #define MDIO_PMA_REG_7101_VER2 0xc027
6256 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
6257 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
6258 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
6259 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
6260 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
6261 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
6262 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
6263 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
6264 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
6265 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
6268 #define MDIO_WIS_DEVAD 0x2
6270 #define MDIO_WIS_REG_LASI_CNTL 0x9002
6271 #define MDIO_WIS_REG_LASI_STATUS 0x9005
6273 #define MDIO_PCS_DEVAD 0x3
6274 #define MDIO_PCS_REG_STATUS 0x0020
6275 #define MDIO_PCS_REG_LASI_STATUS 0x9005
6276 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
6277 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
6278 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
6279 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
6280 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
6281 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
6282 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
6283 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
6284 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
6287 #define MDIO_XS_DEVAD 0x4
6288 #define MDIO_XS_PLL_SEQUENCER 0x8000
6289 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
6291 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
6292 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
6293 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
6294 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
6295 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
6297 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
6299 #define MDIO_AN_DEVAD 0x7
6301 #define MDIO_AN_REG_CTRL 0x0000
6302 #define MDIO_AN_REG_STATUS 0x0001
6303 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
6304 #define MDIO_AN_REG_ADV_PAUSE 0x0010
6305 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
6306 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
6307 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
6308 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
6309 #define MDIO_AN_REG_ADV 0x0011
6310 #define MDIO_AN_REG_ADV2 0x0012
6311 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
6312 #define MDIO_AN_REG_MASTER_STATUS 0x0021
6314 #define MDIO_AN_REG_LINK_STATUS 0x8304
6315 #define MDIO_AN_REG_CL37_CL73 0x8370
6316 #define MDIO_AN_REG_CL37_AN 0xffe0
6317 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
6318 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
6320 #define MDIO_AN_REG_8073_2_5G 0x8329
6321 #define MDIO_AN_REG_8073_BAM 0x8350
6323 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
6324 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
6325 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
6326 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
6327 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
6328 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
6329 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
6330 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
6331 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
6332 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
6335 #define MDIO_CTL_DEVAD 0x1e
6336 #define MDIO_CTL_REG_84823_MEDIA 0x401a
6337 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
6338 /* These pins configure the BCM84823 interface to MAC after reset. */
6339 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
6340 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
6341 /* These pins configure the BCM84823 interface to Line after reset. */
6342 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
6343 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
6344 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
6345 /* When this pin is active high during reset, 10GBASE-T core is power
6346 * down, When it is active low the 10GBASE-T is power up
6348 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
6349 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
6350 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
6351 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
6352 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
6353 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
6354 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
6356 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
6357 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
6360 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
6361 #define MDIO_84833_SUPER_ISOLATE 0x8000
6362 /* These are mailbox register set used by 84833. */
6363 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
6364 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
6365 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
6366 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
6367 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
6369 /* Mailbox command set used by 84833. */
6370 #define PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE 0x2
6371 /* Mailbox status set used by 84833. */
6372 #define PHY84833_CMD_RECEIVED 0x0001
6373 #define PHY84833_CMD_IN_PROGRESS 0x0002
6374 #define PHY84833_CMD_COMPLETE_PASS 0x0004
6375 #define PHY84833_CMD_COMPLETE_ERROR 0x0008
6376 #define PHY84833_CMD_OPEN_FOR_CMDS 0x0010
6377 #define PHY84833_CMD_SYSTEM_BOOT 0x0020
6378 #define PHY84833_CMD_NOT_OPEN_FOR_CMDS 0x0040
6379 #define PHY84833_CMD_CLEAR_COMPLETE 0x0080
6380 #define PHY84833_CMD_OPEN_OVERRIDE 0xa5a5
6382 #define IGU_FUNC_BASE 0x0400
6384 #define IGU_ADDR_MSIX 0x0000
6385 #define IGU_ADDR_INT_ACK 0x0200
6386 #define IGU_ADDR_PROD_UPD 0x0201
6387 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
6388 #define IGU_ADDR_ATTN_BITS_SET 0x0203
6389 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
6390 #define IGU_ADDR_COALESCE_NOW 0x0205
6391 #define IGU_ADDR_SIMD_MASK 0x0206
6392 #define IGU_ADDR_SIMD_NOMASK 0x0207
6393 #define IGU_ADDR_MSI_CTL 0x0210
6394 #define IGU_ADDR_MSI_ADDR_LO 0x0211
6395 #define IGU_ADDR_MSI_ADDR_HI 0x0212
6396 #define IGU_ADDR_MSI_DATA 0x0213
6398 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
6399 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1
6400 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2
6401 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3
6403 #define COMMAND_REG_INT_ACK 0x0
6404 #define COMMAND_REG_PROD_UPD 0x4
6405 #define COMMAND_REG_ATTN_BITS_UPD 0x8
6406 #define COMMAND_REG_ATTN_BITS_SET 0xc
6407 #define COMMAND_REG_ATTN_BITS_CLR 0x10
6408 #define COMMAND_REG_COALESCE_NOW 0x14
6409 #define COMMAND_REG_SIMD_MASK 0x18
6410 #define COMMAND_REG_SIMD_NOMASK 0x1c
6413 #define IGU_MEM_BASE 0x0000
6415 #define IGU_MEM_MSIX_BASE 0x0000
6416 #define IGU_MEM_MSIX_UPPER 0x007f
6417 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
6419 #define IGU_MEM_PBA_MSIX_BASE 0x0200
6420 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
6422 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
6423 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
6425 #define IGU_CMD_INT_ACK_BASE 0x0400
6426 #define IGU_CMD_INT_ACK_UPPER\
6427 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6428 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
6430 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
6431 #define IGU_CMD_E2_PROD_UPD_UPPER\
6432 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
6433 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
6435 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
6436 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
6437 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
6439 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
6440 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
6441 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
6442 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
6444 #define IGU_REG_RESERVED_UPPER 0x05ff
6445 /* Fields of IGU PF CONFIGRATION REGISTER */
6446 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
6447 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
6448 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
6449 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
6450 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
6451 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
6453 /* Fields of IGU VF CONFIGRATION REGISTER */
6454 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
6455 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
6456 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
6457 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */
6458 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
6461 #define IGU_BC_DSB_NUM_SEGS 5
6462 #define IGU_BC_NDSB_NUM_SEGS 2
6463 #define IGU_NORM_DSB_NUM_SEGS 2
6464 #define IGU_NORM_NDSB_NUM_SEGS 1
6465 #define IGU_BC_BASE_DSB_PROD 128
6466 #define IGU_NORM_BASE_DSB_PROD 136
6468 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
6469 [5:2] = 0; [1:0] = PF number) */
6470 #define IGU_FID_ENCODE_IS_PF (0x1<<6)
6471 #define IGU_FID_ENCODE_IS_PF_SHIFT 6
6472 #define IGU_FID_VF_NUM_MASK (0x3f)
6473 #define IGU_FID_PF_NUM_MASK (0x7)
6475 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
6476 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
6477 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1
6478 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
6479 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7
6482 #define CDU_REGION_NUMBER_XCM_AG 2
6483 #define CDU_REGION_NUMBER_UCM_AG 4
6487 * String-to-compress [31:8] = CID (all 24 bits)
6488 * String-to-compress [7:4] = Region
6489 * String-to-compress [3:0] = Type
6491 #define CDU_VALID_DATA(_cid, _region, _type)\
6492 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
6493 #define CDU_CRC8(_cid, _region, _type)\
6494 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
6495 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\
6496 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
6497 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\
6498 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
6499 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
6501 /******************************************************************************
6503 * Calculates crc 8 on a word value: polynomial 0-1-2-8
6504 * Code was translated from Verilog.
6506 *****************************************************************************/
6507 static inline u8 calc_crc8(u32 data, u8 crc)
6515 /* split the data into 31 bits */
6516 for (i = 0; i < 32; i++) {
6517 D[i] = (u8)(data & 1);
6521 /* split the crc into 8 bits */
6522 for (i = 0; i < 8; i++) {
6527 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^
6528 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^
6530 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^
6531 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
6532 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^
6534 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^
6535 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^
6536 C[0] ^ C[1] ^ C[4] ^ C[5];
6537 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^
6538 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^
6539 C[1] ^ C[2] ^ C[5] ^ C[6];
6540 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^
6541 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^
6542 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7];
6543 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^
6544 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^
6546 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^
6547 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^
6549 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^
6550 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^
6554 for (i = 0; i < 8; i++)
6555 crc_res |= (NewCRC[i] << i);
6561 #endif /* BNX2X_REG_H */
git.openpandora.org / pandora-kernel.git / blob