drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2009 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28
  29 /********************************************************/
  30 #define ETH_HLEN                        14
  31 #define ETH_OVREHEAD            (ETH_HLEN + 8 + 8)/* 16 for CRC + VLAN + LLC */
  32 #define ETH_MIN_PACKET_SIZE             60
  33 #define ETH_MAX_PACKET_SIZE             1500
  34 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  35 #define MDIO_ACCESS_TIMEOUT             1000
  36 #define BMAC_CONTROL_RX_ENABLE  2
  37
  38 /***********************************************************/
  39 /*                      Shortcut definitions               */
  40 /***********************************************************/
  41
  42 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  43
  44 #define NIG_STATUS_EMAC0_MI_INT \
  45                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  46 #define NIG_STATUS_XGXS0_LINK10G \
  47                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  48 #define NIG_STATUS_XGXS0_LINK_STATUS \
  49                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  50 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  51                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  52 #define NIG_STATUS_SERDES0_LINK_STATUS \
  53                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  54 #define NIG_MASK_MI_INT \
  55                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  56 #define NIG_MASK_XGXS0_LINK10G \
  57                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  58 #define NIG_MASK_XGXS0_LINK_STATUS \
  59                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  60 #define NIG_MASK_SERDES0_LINK_STATUS \
  61                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  62
  63 #define MDIO_AN_CL73_OR_37_COMPLETE \
  64                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  65                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  66
  67 #define XGXS_RESET_BITS \
  68         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  69          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  70          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  71          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  72          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  73
  74 #define SERDES_RESET_BITS \
  75         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  76          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  77          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  78          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  79
  80 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  81 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  82 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  83 #define AUTONEG_PARALLEL \
  84                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  85 #define AUTONEG_SGMII_FIBER_AUTODET \
  86                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  87 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  88
  89 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
  90                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
  91 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
  92                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
  93 #define GP_STATUS_SPEED_MASK \
  94                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
  95 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
  96 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
  97 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
  98 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
  99 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 100 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 101 #define GP_STATUS_10G_HIG \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 103 #define GP_STATUS_10G_CX4 \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 105 #define GP_STATUS_12G_HIG \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
 107 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
 108 #define GP_STATUS_13G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
 109 #define GP_STATUS_15G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
 110 #define GP_STATUS_16G   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
 111 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 112 #define GP_STATUS_10G_KX4 \
 113                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 114
 115 #define LINK_10THD                      LINK_STATUS_SPEED_AND_DUPLEX_10THD
 116 #define LINK_10TFD                      LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 117 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 118 #define LINK_100T4                      LINK_STATUS_SPEED_AND_DUPLEX_100T4
 119 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 120 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 121 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 122 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 123 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 124 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 125 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 126 #define LINK_10GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 127 #define LINK_10GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 128 #define LINK_12GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
 129 #define LINK_12GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
 130 #define LINK_12_5GTFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
 131 #define LINK_12_5GXFD           LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
 132 #define LINK_13GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
 133 #define LINK_13GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
 134 #define LINK_15GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
 135 #define LINK_15GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
 136 #define LINK_16GTFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
 137 #define LINK_16GXFD                     LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
 138
 139 #define PHY_XGXS_FLAG                   0x1
 140 #define PHY_SGMII_FLAG                  0x2
 141 #define PHY_SERDES_FLAG                 0x4
 142
 143 /* */
 144 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 145         #define SFP_EEPROM_CON_TYPE_VAL_LC              0x7
 146         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 147
 148
 149 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 150         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 151         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 152         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 153
 154 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 155         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 156         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE      0x8
 157
 158 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 159         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 160 #define SFP_EEPROM_OPTIONS_SIZE                 2
 161
 162 #define EDC_MODE_LINEAR                         0x0022
 163 #define EDC_MODE_LIMITING                               0x0044
 164 #define EDC_MODE_PASSIVE_DAC                    0x0055
 165
 166
 167 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 168 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 169 /**********************************************************/
 170 /*                     INTERFACE                          */
 171 /**********************************************************/
 172
 173 #define CL45_WR_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
 174         bnx2x_cl45_write(_bp, _phy, \
 175                 (_phy)->def_md_devad, \
 176                 (_bank + (_addr & 0xf)), \
 177                 _val)
 178
 179 #define CL45_RD_OVER_CL22(_bp, _phy, _bank, _addr, _val) \
 180         bnx2x_cl45_read(_bp, _phy, \
 181                 (_phy)->def_md_devad, \
 182                 (_bank + (_addr & 0xf)), \
 183                 _val)
 184
 185 static u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
 186                           u8 devad, u16 reg, u16 *ret_val);
 187
 188 static u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
 189                            u8 devad, u16 reg, u16 val);
 190
 191 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 192 {
 193         u32 val = REG_RD(bp, reg);
 194
 195         val |= bits;
 196         REG_WR(bp, reg, val);
 197         return val;
 198 }
 199
 200 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 201 {
 202         u32 val = REG_RD(bp, reg);
 203
 204         val &= ~bits;
 205         REG_WR(bp, reg, val);
 206         return val;
 207 }
 208
 209 /******************************************************************/
 210 /*                              ETS section                       */
 211 /******************************************************************/
 212 void bnx2x_ets_disabled(struct link_params *params)
 213 {
 214         /* ETS disabled configuration*/
 215         struct bnx2x *bp = params->bp;
 216
 217         DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
 218
 219         /**
 220          * mapping between entry  priority to client number (0,1,2 -debug and
 221          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 222          * 3bits client num.
 223          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 224          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 225          */
 226
 227         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 228         /**
 229          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 230          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 231          * COS0 entry, 4 - COS1 entry.
 232          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 233          * bit4   bit3    bit2   bit1     bit0
 234          * MCP and debug are strict
 235          */
 236
 237         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 238         /* defines which entries (clients) are subjected to WFQ arbitration */
 239         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 240         /**
 241         * For strict priority entries defines the number of consecutive
 242         * slots for the highest priority.
 243         */
 244         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 245         /**
 246          * mapping between the CREDIT_WEIGHT registers and actual client
 247          * numbers
 248          */
 249         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 250         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 251         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 252
 253         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 254         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 255         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 256         /* ETS mode disable */
 257         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 258         /**
 259          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 260          * weight for COS0/COS1.
 261          */
 262         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 263         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 264         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 265         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 266         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 267         /* Defines the number of consecutive slots for the strict priority */
 268         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 269 }
 270
 271 void bnx2x_ets_bw_limit_common(const struct link_params *params)
 272 {
 273         /* ETS disabled configuration */
 274         struct bnx2x *bp = params->bp;
 275         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 276         /**
 277         * defines which entries (clients) are subjected to WFQ arbitration
 278         * COS0 0x8
 279         * COS1 0x10
 280         */
 281         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
 282         /**
 283         * mapping between the ARB_CREDIT_WEIGHT registers and actual
 284         * client numbers (WEIGHT_0 does not actually have to represent
 285         * client 0)
 286         *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 287         *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
 288         */
 289         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
 290
 291         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
 292                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 293         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
 294                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 295
 296         /* ETS mode enabled*/
 297         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
 298
 299         /* Defines the number of consecutive slots for the strict priority */
 300         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 301         /**
 302         * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 303         * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
 304         * entry, 4 - COS1 entry.
 305         * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 306         * bit4   bit3     bit2     bit1    bit0
 307         * MCP and debug are strict
 308         */
 309         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 310
 311         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
 312         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
 313                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 314         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
 315                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
 316 }
 317
 318 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
 319                         const u32 cos1_bw)
 320 {
 321         /* ETS disabled configuration*/
 322         struct bnx2x *bp = params->bp;
 323         const u32 total_bw = cos0_bw + cos1_bw;
 324         u32 cos0_credit_weight = 0;
 325         u32 cos1_credit_weight = 0;
 326
 327         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
 328
 329         if ((0 == total_bw) ||
 330             (0 == cos0_bw) ||
 331             (0 == cos1_bw)) {
 332                 DP(NETIF_MSG_LINK,
 333                    "bnx2x_ets_bw_limit: Total BW can't be zero\n");
 334                 return;
 335         }
 336
 337         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 338                 total_bw;
 339         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
 340                 total_bw;
 341
 342         bnx2x_ets_bw_limit_common(params);
 343
 344         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
 345         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
 346
 347         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
 348         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
 349 }
 350
 351 u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
 352 {
 353         /* ETS disabled configuration*/
 354         struct bnx2x *bp = params->bp;
 355         u32 val = 0;
 356
 357         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
 358         /**
 359          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 360          * as strict.  Bits 0,1,2 - debug and management entries,
 361          * 3 - COS0 entry, 4 - COS1 entry.
 362          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
 363          *  bit4   bit3   bit2      bit1     bit0
 364          * MCP and debug are strict
 365          */
 366         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
 367         /**
 368          * For strict priority entries defines the number of consecutive slots
 369          * for the highest priority.
 370          */
 371         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 372         /* ETS mode disable */
 373         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 374         /* Defines the number of consecutive slots for the strict priority */
 375         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
 376
 377         /* Defines the number of consecutive slots for the strict priority */
 378         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
 379
 380         /**
 381         * mapping between entry  priority to client number (0,1,2 -debug and
 382         * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 383         * 3bits client num.
 384         *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 385         * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
 386         * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
 387         */
 388         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
 389         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
 390
 391         return 0;
 392 }
 393 /******************************************************************/
 394 /*                      ETS section                               */
 395 /******************************************************************/
 396
 397 static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
 398                                      u32 pfc_frames_sent[2],
 399                                      u32 pfc_frames_received[2])
 400 {
 401         /* Read pfc statistic */
 402         struct bnx2x *bp = params->bp;
 403         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 404                 NIG_REG_INGRESS_BMAC0_MEM;
 405
 406         DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
 407
 408         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
 409                                         pfc_frames_sent, 2);
 410
 411         REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
 412                                         pfc_frames_received, 2);
 413
 414 }
 415 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
 416                                     u32 pfc_frames_sent[2],
 417                                     u32 pfc_frames_received[2])
 418 {
 419         /* Read pfc statistic */
 420         struct bnx2x *bp = params->bp;
 421         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 422         u32 val_xon = 0;
 423         u32 val_xoff = 0;
 424
 425         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
 426
 427         /* PFC received frames */
 428         val_xoff = REG_RD(bp, emac_base +
 429                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
 430         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
 431         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
 432         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
 433
 434         pfc_frames_received[0] = val_xon + val_xoff;
 435
 436         /* PFC received sent */
 437         val_xoff = REG_RD(bp, emac_base +
 438                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
 439         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
 440         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
 441         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
 442
 443         pfc_frames_sent[0] = val_xon + val_xoff;
 444 }
 445
 446 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
 447                          u32 pfc_frames_sent[2],
 448                          u32 pfc_frames_received[2])
 449 {
 450         /* Read pfc statistic */
 451         struct bnx2x *bp = params->bp;
 452         u32 val = 0;
 453         DP(NETIF_MSG_LINK, "pfc statistic\n");
 454
 455         if (!vars->link_up)
 456                 return;
 457
 458         val = REG_RD(bp, MISC_REG_RESET_REG_2);
 459         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
 460             == 0) {
 461                 DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
 462                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
 463                                         pfc_frames_received);
 464         } else {
 465                 DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
 466                 bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
 467                                          pfc_frames_received);
 468         }
 469 }
 470 /******************************************************************/
 471 /*                      MAC/PBF section                           */
 472 /******************************************************************/
 473 static void bnx2x_emac_init(struct link_params *params,
 474                            struct link_vars *vars)
 475 {
 476         /* reset and unreset the emac core */
 477         struct bnx2x *bp = params->bp;
 478         u8 port = params->port;
 479         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 480         u32 val;
 481         u16 timeout;
 482
 483         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
 484                    (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 485         udelay(5);
 486         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 487                    (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
 488
 489         /* init emac - use read-modify-write */
 490         /* self clear reset */
 491         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 492         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
 493
 494         timeout = 200;
 495         do {
 496                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 497                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
 498                 if (!timeout) {
 499                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
 500                         return;
 501                 }
 502                 timeout--;
 503         } while (val & EMAC_MODE_RESET);
 504
 505         /* Set mac address */
 506         val = ((params->mac_addr[0] << 8) |
 507                 params->mac_addr[1]);
 508         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
 509
 510         val = ((params->mac_addr[2] << 24) |
 511                (params->mac_addr[3] << 16) |
 512                (params->mac_addr[4] << 8) |
 513                 params->mac_addr[5]);
 514         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
 515 }
 516
 517 static u8 bnx2x_emac_enable(struct link_params *params,
 518                           struct link_vars *vars, u8 lb)
 519 {
 520         struct bnx2x *bp = params->bp;
 521         u8 port = params->port;
 522         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
 523         u32 val;
 524
 525         DP(NETIF_MSG_LINK, "enabling EMAC\n");
 526
 527         /* enable emac and not bmac */
 528         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
 529
 530         /* for paladium */
 531         if (CHIP_REV_IS_EMUL(bp)) {
 532                 /* Use lane 1 (of lanes 0-3) */
 533                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
 534                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
 535                             port*4, 1);
 536         }
 537         /* for fpga */
 538         else
 539
 540         if (CHIP_REV_IS_FPGA(bp)) {
 541                 /* Use lane 1 (of lanes 0-3) */
 542                 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
 543
 544                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
 545                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
 546                             0);
 547         } else
 548         /* ASIC */
 549         if (vars->phy_flags & PHY_XGXS_FLAG) {
 550                 u32 ser_lane = ((params->lane_config &
 551                             PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
 552                             PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
 553
 554                 DP(NETIF_MSG_LINK, "XGXS\n");
 555                 /* select the master lanes (out of 0-3) */
 556                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
 557                            port*4, ser_lane);
 558                 /* select XGXS */
 559                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
 560                            port*4, 1);
 561
 562         } else { /* SerDes */
 563                 DP(NETIF_MSG_LINK, "SerDes\n");
 564                 /* select SerDes */
 565                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
 566                            port*4, 0);
 567         }
 568
 569         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 570                     EMAC_RX_MODE_RESET);
 571         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 572                     EMAC_TX_MODE_RESET);
 573
 574         if (CHIP_REV_IS_SLOW(bp)) {
 575                 /* config GMII mode */
 576                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 577                 EMAC_WR(bp, EMAC_REG_EMAC_MODE,
 578                             (val | EMAC_MODE_PORT_GMII));
 579         } else { /* ASIC */
 580                 /* pause enable/disable */
 581                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
 582                                EMAC_RX_MODE_FLOW_EN);
 583
 584                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
 585                                (EMAC_TX_MODE_EXT_PAUSE_EN |
 586                                 EMAC_TX_MODE_FLOW_EN));
 587                 if (!(params->feature_config_flags &
 588                       FEATURE_CONFIG_PFC_ENABLED)) {
 589                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
 590                                 bnx2x_bits_en(bp, emac_base +
 591                                               EMAC_REG_EMAC_RX_MODE,
 592                                               EMAC_RX_MODE_FLOW_EN);
 593
 594                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
 595                                 bnx2x_bits_en(bp, emac_base +
 596                                               EMAC_REG_EMAC_TX_MODE,
 597                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
 598                                                EMAC_TX_MODE_FLOW_EN));
 599                 } else
 600                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
 601                                       EMAC_TX_MODE_FLOW_EN);
 602         }
 603
 604         /* KEEP_VLAN_TAG, promiscuous */
 605         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
 606         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
 607
 608         /**
 609         * Setting this bit causes MAC control frames (except for pause
 610         * frames) to be passed on for processing. This setting has no
 611         * affect on the operation of the pause frames. This bit effects
 612         * all packets regardless of RX Parser packet sorting logic.
 613         * Turn the PFC off to make sure we are in Xon state before
 614         * enabling it.
 615         */
 616         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
 617         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 618                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 619                 /* Enable PFC again */
 620                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
 621                         EMAC_REG_RX_PFC_MODE_RX_EN |
 622                         EMAC_REG_RX_PFC_MODE_TX_EN |
 623                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
 624
 625                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
 626                         ((0x0101 <<
 627                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
 628                          (0x00ff <<
 629                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
 630                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
 631         }
 632         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
 633
 634         /* Set Loopback */
 635         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
 636         if (lb)
 637                 val |= 0x810;
 638         else
 639                 val &= ~0x810;
 640         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
 641
 642         /* enable emac */
 643         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
 644
 645         /* enable emac for jumbo packets */
 646         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
 647                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
 648                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
 649
 650         /* strip CRC */
 651         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
 652
 653         /* disable the NIG in/out to the bmac */
 654         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
 655         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
 656         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
 657
 658         /* enable the NIG in/out to the emac */
 659         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
 660         val = 0;
 661         if ((params->feature_config_flags &
 662               FEATURE_CONFIG_PFC_ENABLED) ||
 663             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 664                 val = 1;
 665
 666         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
 667         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
 668
 669         if (CHIP_REV_IS_EMUL(bp)) {
 670                 /* take the BigMac out of reset */
 671                 REG_WR(bp,
 672                            GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
 673                            (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
 674
 675                 /* enable access for bmac registers */
 676                 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
 677         } else
 678                 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
 679
 680         vars->mac_type = MAC_TYPE_EMAC;
 681         return 0;
 682 }
 683
 684 static void bnx2x_update_pfc_bmac1(struct link_params *params,
 685                                    struct link_vars *vars)
 686 {
 687         u32 wb_data[2];
 688         struct bnx2x *bp = params->bp;
 689         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 690                 NIG_REG_INGRESS_BMAC0_MEM;
 691
 692         u32 val = 0x14;
 693         if ((!(params->feature_config_flags &
 694               FEATURE_CONFIG_PFC_ENABLED)) &&
 695                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 696                 /* Enable BigMAC to react on received Pause packets */
 697                 val |= (1<<5);
 698         wb_data[0] = val;
 699         wb_data[1] = 0;
 700         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
 701
 702         /* tx control */
 703         val = 0xc0;
 704         if (!(params->feature_config_flags &
 705               FEATURE_CONFIG_PFC_ENABLED) &&
 706                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 707                 val |= 0x800000;
 708         wb_data[0] = val;
 709         wb_data[1] = 0;
 710         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
 711 }
 712
 713 static void bnx2x_update_pfc_bmac2(struct link_params *params,
 714                                    struct link_vars *vars,
 715                                    u8 is_lb)
 716 {
 717         /*
 718          * Set rx control: Strip CRC and enable BigMAC to relay
 719          * control packets to the system as well
 720          */
 721         u32 wb_data[2];
 722         struct bnx2x *bp = params->bp;
 723         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
 724                 NIG_REG_INGRESS_BMAC0_MEM;
 725         u32 val = 0x14;
 726
 727         if ((!(params->feature_config_flags &
 728               FEATURE_CONFIG_PFC_ENABLED)) &&
 729                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
 730                 /* Enable BigMAC to react on received Pause packets */
 731                 val |= (1<<5);
 732         wb_data[0] = val;
 733         wb_data[1] = 0;
 734         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL,
 735                         wb_data, 2);
 736         udelay(30);
 737
 738         /* Tx control */
 739         val = 0xc0;
 740         if (!(params->feature_config_flags &
 741                                 FEATURE_CONFIG_PFC_ENABLED) &&
 742             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
 743                 val |= 0x800000;
 744         wb_data[0] = val;
 745         wb_data[1] = 0;
 746         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
 747
 748         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
 749                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
 750                 /* Enable PFC RX & TX & STATS and set 8 COS  */
 751                 wb_data[0] = 0x0;
 752                 wb_data[0] |= (1<<0);  /* RX */
 753                 wb_data[0] |= (1<<1);  /* TX */
 754                 wb_data[0] |= (1<<2);  /* Force initial Xon */
 755                 wb_data[0] |= (1<<3);  /* 8 cos */
 756                 wb_data[0] |= (1<<5);  /* STATS */
 757                 wb_data[1] = 0;
 758                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
 759                             wb_data, 2);
 760                 /* Clear the force Xon */
 761                 wb_data[0] &= ~(1<<2);
 762         } else {
 763                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
 764                 /* disable PFC RX & TX & STATS and set 8 COS */
 765                 wb_data[0] = 0x8;
 766                 wb_data[1] = 0;
 767         }
 768
 769         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
 770
 771         /**
 772         * Set Time (based unit is 512 bit time) between automatic
 773         * re-sending of PP packets amd enable automatic re-send of
 774         * Per-Priroity Packet as long as pp_gen is asserted and
 775         * pp_disable is low.
 776         */
 777         val = 0x8000;
 778         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 779                 val |= (1<<16); /* enable automatic re-send */
 780
 781         wb_data[0] = val;
 782         wb_data[1] = 0;
 783         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
 784                         wb_data, 2);
 785
 786         /* mac control */
 787         val = 0x3; /* Enable RX and TX */
 788         if (is_lb) {
 789                 val |= 0x4; /* Local loopback */
 790                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
 791         }
 792         /* When PFC enabled, Pass pause frames towards the NIG. */
 793         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
 794                 val |= ((1<<6)|(1<<5));
 795
 796         wb_data[0] = val;
 797         wb_data[1] = 0;
 798         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
 799                         wb_data, 2);
 800 }
 801
 802 static void bnx2x_update_pfc_brb(struct link_params *params,
 803                 struct link_vars *vars,
 804                 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 805 {
 806         struct bnx2x *bp = params->bp;
 807         int set_pfc = params->feature_config_flags &
 808                 FEATURE_CONFIG_PFC_ENABLED;
 809
 810         /* default - pause configuration */
 811         u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 812         u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 813         u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 814         u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 815
 816         if (set_pfc && pfc_params)
 817                 /* First COS */
 818                 if (!pfc_params->cos0_pauseable) {
 819                         pause_xoff_th =
 820                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 821                         pause_xon_th =
 822                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 823                         full_xoff_th =
 824                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 825                         full_xon_th =
 826                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 827                 }
 828         /* The number of free blocks below which the pause signal to class 0
 829            of MAC #n is asserted. n=0,1 */
 830         REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
 831         /* The number of free blocks above which the pause signal to class 0
 832            of MAC #n is de-asserted. n=0,1 */
 833         REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
 834         /* The number of free blocks below which the full signal to class 0
 835            of MAC #n is asserted. n=0,1 */
 836         REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
 837         /* The number of free blocks above which the full signal to class 0
 838            of MAC #n is de-asserted. n=0,1 */
 839         REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
 840
 841         if (set_pfc && pfc_params) {
 842                 /* Second COS */
 843                 if (pfc_params->cos1_pauseable) {
 844                         pause_xoff_th =
 845                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
 846                         pause_xon_th =
 847                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
 848                         full_xoff_th =
 849                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
 850                         full_xon_th =
 851                           PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
 852                 } else {
 853                         pause_xoff_th =
 854                           PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
 855                         pause_xon_th =
 856                           PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
 857                         full_xoff_th =
 858                           PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
 859                         full_xon_th =
 860                           PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
 861                 }
 862                 /**
 863                  * The number of free blocks below which the pause signal to
 864                  * class 1 of MAC #n is asserted. n=0,1
 865                  **/
 866                 REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
 867                 /**
 868                  * The number of free blocks above which the pause signal to
 869                  * class 1 of MAC #n is de-asserted. n=0,1
 870                  **/
 871                 REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
 872                 /**
 873                  * The number of free blocks below which the full signal to
 874                  * class 1 of MAC #n is asserted. n=0,1
 875                  **/
 876                 REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
 877                 /**
 878                  * The number of free blocks above which the full signal to
 879                  * class 1 of MAC #n is de-asserted. n=0,1
 880                  **/
 881                 REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
 882         }
 883 }
 884
 885 static void bnx2x_update_pfc_nig(struct link_params *params,
 886                 struct link_vars *vars,
 887                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
 888 {
 889         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
 890         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
 891         u32 pkt_priority_to_cos = 0;
 892         u32 val;
 893         struct bnx2x *bp = params->bp;
 894         int port = params->port;
 895         int set_pfc = params->feature_config_flags &
 896                 FEATURE_CONFIG_PFC_ENABLED;
 897         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
 898
 899         /**
 900          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
 901          * MAC control frames (that are not pause packets)
 902          * will be forwarded to the XCM.
 903          */
 904         xcm_mask = REG_RD(bp,
 905                                 port ? NIG_REG_LLH1_XCM_MASK :
 906                                 NIG_REG_LLH0_XCM_MASK);
 907         /**
 908          * nig params will override non PFC params, since it's possible to
 909          * do transition from PFC to SAFC
 910          */
 911         if (set_pfc) {
 912                 pause_enable = 0;
 913                 llfc_out_en = 0;
 914                 llfc_enable = 0;
 915                 ppp_enable = 1;
 916                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 917                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 918                 xcm0_out_en = 0;
 919                 p0_hwpfc_enable = 1;
 920         } else  {
 921                 if (nig_params) {
 922                         llfc_out_en = nig_params->llfc_out_en;
 923                         llfc_enable = nig_params->llfc_enable;
 924                         pause_enable = nig_params->pause_enable;
 925                 } else  /*defaul non PFC mode - PAUSE */
 926                         pause_enable = 1;
 927
 928                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
 929                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
 930                 xcm0_out_en = 1;
 931         }
 932
 933         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
 934                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
 935         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
 936                NIG_REG_LLFC_ENABLE_0, llfc_enable);
 937         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
 938                NIG_REG_PAUSE_ENABLE_0, pause_enable);
 939
 940         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
 941                NIG_REG_PPP_ENABLE_0, ppp_enable);
 942
 943         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
 944                NIG_REG_LLH0_XCM_MASK, xcm_mask);
 945
 946         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
 947
 948         /* output enable for RX_XCM # IF */
 949         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
 950
 951         /* HW PFC TX enable */
 952         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
 953
 954         /* 0x2 = BMAC, 0x1= EMAC */
 955         switch (vars->mac_type) {
 956         case MAC_TYPE_EMAC:
 957                 val = 1;
 958                 break;
 959         case MAC_TYPE_BMAC:
 960                 val = 0;
 961                 break;
 962         default:
 963                 val = 0;
 964                 break;
 965         }
 966         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
 967
 968         if (nig_params) {
 969                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
 970
 971                 REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
 972                        NIG_REG_P0_RX_COS0_PRIORITY_MASK,
 973                        nig_params->rx_cos0_priority_mask);
 974
 975                 REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
 976                        NIG_REG_P0_RX_COS1_PRIORITY_MASK,
 977                        nig_params->rx_cos1_priority_mask);
 978
 979                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
 980                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
 981                        nig_params->llfc_high_priority_classes);
 982
 983                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
 984                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
 985                        nig_params->llfc_low_priority_classes);
 986         }
 987         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
 988                NIG_REG_P0_PKT_PRIORITY_TO_COS,
 989                pkt_priority_to_cos);
 990 }
 991
 992
 993 void bnx2x_update_pfc(struct link_params *params,
 994                       struct link_vars *vars,
 995                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
 996 {
 997         /**
 998          * The PFC and pause are orthogonal to one another, meaning when
 999          * PFC is enabled, the pause are disabled, and when PFC is
1000          * disabled, pause are set according to the pause result.
1001          */
1002         u32 val;
1003         struct bnx2x *bp = params->bp;
1004
1005         /* update NIG params */
1006         bnx2x_update_pfc_nig(params, vars, pfc_params);
1007
1008         /* update BRB params */
1009         bnx2x_update_pfc_brb(params, vars, pfc_params);
1010
1011         if (!vars->link_up)
1012                 return;
1013
1014         val = REG_RD(bp, MISC_REG_RESET_REG_2);
1015         if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
1016             == 0) {
1017                 DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
1018                 bnx2x_emac_enable(params, vars, 0);
1019                 return;
1020         }
1021
1022         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
1023         if (CHIP_IS_E2(bp))
1024                 bnx2x_update_pfc_bmac2(params, vars, 0);
1025         else
1026                 bnx2x_update_pfc_bmac1(params, vars);
1027
1028         val = 0;
1029         if ((params->feature_config_flags &
1030               FEATURE_CONFIG_PFC_ENABLED) ||
1031             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1032                 val = 1;
1033         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
1034 }
1035
1036 static u8 bnx2x_bmac1_enable(struct link_params *params,
1037                              struct link_vars *vars,
1038                           u8 is_lb)
1039 {
1040         struct bnx2x *bp = params->bp;
1041         u8 port = params->port;
1042         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1043                                NIG_REG_INGRESS_BMAC0_MEM;
1044         u32 wb_data[2];
1045         u32 val;
1046
1047         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
1048
1049         /* XGXS control */
1050         wb_data[0] = 0x3c;
1051         wb_data[1] = 0;
1052         REG_WR_DMAE(bp, bmac_addr +
1053                       BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
1054                       wb_data, 2);
1055
1056         /* tx MAC SA */
1057         wb_data[0] = ((params->mac_addr[2] << 24) |
1058                        (params->mac_addr[3] << 16) |
1059                        (params->mac_addr[4] << 8) |
1060                         params->mac_addr[5]);
1061         wb_data[1] = ((params->mac_addr[0] << 8) |
1062                         params->mac_addr[1]);
1063         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
1064                     wb_data, 2);
1065
1066         /* mac control */
1067         val = 0x3;
1068         if (is_lb) {
1069                 val |= 0x4;
1070                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1071         }
1072         wb_data[0] = val;
1073         wb_data[1] = 0;
1074         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
1075                     wb_data, 2);
1076
1077         /* set rx mtu */
1078         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1079         wb_data[1] = 0;
1080         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
1081                         wb_data, 2);
1082
1083         bnx2x_update_pfc_bmac1(params, vars);
1084
1085         /* set tx mtu */
1086         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1087         wb_data[1] = 0;
1088         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
1089                         wb_data, 2);
1090
1091         /* set cnt max size */
1092         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1093         wb_data[1] = 0;
1094         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
1095                     wb_data, 2);
1096
1097         /* configure safc */
1098         wb_data[0] = 0x1000200;
1099         wb_data[1] = 0;
1100         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
1101                     wb_data, 2);
1102         /* fix for emulation */
1103         if (CHIP_REV_IS_EMUL(bp)) {
1104                 wb_data[0] = 0xf000;
1105                 wb_data[1] = 0;
1106                 REG_WR_DMAE(bp,
1107                             bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
1108                             wb_data, 2);
1109         }
1110
1111
1112         return 0;
1113 }
1114
1115 static u8 bnx2x_bmac2_enable(struct link_params *params,
1116                              struct link_vars *vars,
1117                              u8 is_lb)
1118 {
1119         struct bnx2x *bp = params->bp;
1120         u8 port = params->port;
1121         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1122                                NIG_REG_INGRESS_BMAC0_MEM;
1123         u32 wb_data[2];
1124
1125         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
1126
1127         wb_data[0] = 0;
1128         wb_data[1] = 0;
1129         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL,
1130                         wb_data, 2);
1131         udelay(30);
1132
1133         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
1134         wb_data[0] = 0x3c;
1135         wb_data[1] = 0;
1136         REG_WR_DMAE(bp, bmac_addr +
1137                         BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
1138                         wb_data, 2);
1139
1140         udelay(30);
1141
1142         /* tx MAC SA */
1143         wb_data[0] = ((params->mac_addr[2] << 24) |
1144                        (params->mac_addr[3] << 16) |
1145                        (params->mac_addr[4] << 8) |
1146                         params->mac_addr[5]);
1147         wb_data[1] = ((params->mac_addr[0] << 8) |
1148                         params->mac_addr[1]);
1149         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
1150                         wb_data, 2);
1151
1152         udelay(30);
1153
1154         /* Configure SAFC */
1155         wb_data[0] = 0x1000200;
1156         wb_data[1] = 0;
1157         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
1158                         wb_data, 2);
1159         udelay(30);
1160
1161         /* set rx mtu */
1162         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1163         wb_data[1] = 0;
1164         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE,
1165                         wb_data, 2);
1166         udelay(30);
1167
1168         /* set tx mtu */
1169         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
1170         wb_data[1] = 0;
1171         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE,
1172                         wb_data, 2);
1173         udelay(30);
1174         /* set cnt max size */
1175         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
1176         wb_data[1] = 0;
1177         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE,
1178                         wb_data, 2);
1179         udelay(30);
1180         bnx2x_update_pfc_bmac2(params, vars, is_lb);
1181
1182         return 0;
1183 }
1184
1185 static u8 bnx2x_bmac_enable(struct link_params *params,
1186                             struct link_vars *vars,
1187                             u8 is_lb)
1188 {
1189         u8 rc, port = params->port;
1190         struct bnx2x *bp = params->bp;
1191         u32 val;
1192         /* reset and unreset the BigMac */
1193         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1194                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1195         msleep(1);
1196
1197         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1198                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1199
1200         /* enable access for bmac registers */
1201         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
1202
1203         /* Enable BMAC according to BMAC type*/
1204         if (CHIP_IS_E2(bp))
1205                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
1206         else
1207                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
1208         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
1209         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
1210         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
1211         val = 0;
1212         if ((params->feature_config_flags &
1213               FEATURE_CONFIG_PFC_ENABLED) ||
1214             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1215                 val = 1;
1216         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
1217         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
1218         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
1219         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
1220         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
1221         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
1222
1223         vars->mac_type = MAC_TYPE_BMAC;
1224         return rc;
1225 }
1226
1227
1228 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
1229 {
1230         struct bnx2x *bp = params->bp;
1231
1232         REG_WR(bp, params->shmem_base +
1233                    offsetof(struct shmem_region,
1234                             port_mb[params->port].link_status),
1235                         link_status);
1236 }
1237
1238 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
1239 {
1240         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
1241                 NIG_REG_INGRESS_BMAC0_MEM;
1242         u32 wb_data[2];
1243         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
1244
1245         /* Only if the bmac is out of reset */
1246         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1247                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
1248             nig_bmac_enable) {
1249
1250                 if (CHIP_IS_E2(bp)) {
1251                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1252                         REG_RD_DMAE(bp, bmac_addr +
1253                                         BIGMAC2_REGISTER_BMAC_CONTROL,
1254                                         wb_data, 2);
1255                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1256                         REG_WR_DMAE(bp, bmac_addr +
1257                                         BIGMAC2_REGISTER_BMAC_CONTROL,
1258                                         wb_data, 2);
1259                 } else {
1260                         /* Clear Rx Enable bit in BMAC_CONTROL register */
1261                         REG_RD_DMAE(bp, bmac_addr +
1262                                         BIGMAC_REGISTER_BMAC_CONTROL,
1263                                         wb_data, 2);
1264                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
1265                         REG_WR_DMAE(bp, bmac_addr +
1266                                         BIGMAC_REGISTER_BMAC_CONTROL,
1267                                         wb_data, 2);
1268                 }
1269                 msleep(1);
1270         }
1271 }
1272
1273 static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
1274                          u32 line_speed)
1275 {
1276         struct bnx2x *bp = params->bp;
1277         u8 port = params->port;
1278         u32 init_crd, crd;
1279         u32 count = 1000;
1280
1281         /* disable port */
1282         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
1283
1284         /* wait for init credit */
1285         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
1286         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1287         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
1288
1289         while ((init_crd != crd) && count) {
1290                 msleep(5);
1291
1292                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1293                 count--;
1294         }
1295         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
1296         if (init_crd != crd) {
1297                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
1298                           init_crd, crd);
1299                 return -EINVAL;
1300         }
1301
1302         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
1303             line_speed == SPEED_10 ||
1304             line_speed == SPEED_100 ||
1305             line_speed == SPEED_1000 ||
1306             line_speed == SPEED_2500) {
1307                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
1308                 /* update threshold */
1309                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
1310                 /* update init credit */
1311                 init_crd = 778;         /* (800-18-4) */
1312
1313         } else {
1314                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
1315                               ETH_OVREHEAD)/16;
1316                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
1317                 /* update threshold */
1318                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
1319                 /* update init credit */
1320                 switch (line_speed) {
1321                 case SPEED_10000:
1322                         init_crd = thresh + 553 - 22;
1323                         break;
1324
1325                 case SPEED_12000:
1326                         init_crd = thresh + 664 - 22;
1327                         break;
1328
1329                 case SPEED_13000:
1330                         init_crd = thresh + 742 - 22;
1331                         break;
1332
1333                 case SPEED_16000:
1334                         init_crd = thresh + 778 - 22;
1335                         break;
1336                 default:
1337                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1338                                   line_speed);
1339                         return -EINVAL;
1340                 }
1341         }
1342         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
1343         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
1344                  line_speed, init_crd);
1345
1346         /* probe the credit changes */
1347         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
1348         msleep(5);
1349         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
1350
1351         /* enable port */
1352         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
1353         return 0;
1354 }
1355
1356 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
1357                                u32 mdc_mdio_access, u8 port)
1358 {
1359         u32 emac_base = 0;
1360         switch (mdc_mdio_access) {
1361         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
1362                 break;
1363         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
1364                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1365                         emac_base = GRCBASE_EMAC1;
1366                 else
1367                         emac_base = GRCBASE_EMAC0;
1368                 break;
1369         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
1370                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
1371                         emac_base = GRCBASE_EMAC0;
1372                 else
1373                         emac_base = GRCBASE_EMAC1;
1374                 break;
1375         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
1376                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1377                 break;
1378         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
1379                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
1380                 break;
1381         default:
1382                 break;
1383         }
1384         return emac_base;
1385
1386 }
1387
1388 u8 bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
1389                     u8 devad, u16 reg, u16 val)
1390 {
1391         u32 tmp, saved_mode;
1392         u8 i, rc = 0;
1393
1394         /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1395          * (a value of 49==0x31) and make sure that the AUTO poll is off
1396          */
1397
1398         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1399         tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
1400                              EMAC_MDIO_MODE_CLOCK_CNT);
1401         tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
1402                 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1403         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
1404         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1405         udelay(40);
1406
1407         /* address */
1408
1409         tmp = ((phy->addr << 21) | (devad << 16) | reg |
1410                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1411                EMAC_MDIO_COMM_START_BUSY);
1412         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1413
1414         for (i = 0; i < 50; i++) {
1415                 udelay(10);
1416
1417                 tmp = REG_RD(bp, phy->mdio_ctrl +
1418                                    EMAC_REG_EMAC_MDIO_COMM);
1419                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1420                         udelay(5);
1421                         break;
1422                 }
1423         }
1424         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1425                 DP(NETIF_MSG_LINK, "write phy register failed\n");
1426                 rc = -EFAULT;
1427         } else {
1428                 /* data */
1429                 tmp = ((phy->addr << 21) | (devad << 16) | val |
1430                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
1431                        EMAC_MDIO_COMM_START_BUSY);
1432                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
1433
1434                 for (i = 0; i < 50; i++) {
1435                         udelay(10);
1436
1437                         tmp = REG_RD(bp, phy->mdio_ctrl +
1438                                          EMAC_REG_EMAC_MDIO_COMM);
1439                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
1440                                 udelay(5);
1441                                 break;
1442                         }
1443                 }
1444                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
1445                         DP(NETIF_MSG_LINK, "write phy register failed\n");
1446                         rc = -EFAULT;
1447                 }
1448         }
1449
1450         /* Restore the saved mode */
1451         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1452
1453         return rc;
1454 }
1455
1456 u8 bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
1457                    u8 devad, u16 reg, u16 *ret_val)
1458 {
1459         u32 val, saved_mode;
1460         u16 i;
1461         u8 rc = 0;
1462
1463         /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
1464          * (a value of 49==0x31) and make sure that the AUTO poll is off
1465          */
1466
1467         saved_mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1468         val = saved_mode & ~((EMAC_MDIO_MODE_AUTO_POLL |
1469                              EMAC_MDIO_MODE_CLOCK_CNT));
1470         val |= (EMAC_MDIO_MODE_CLAUSE_45 |
1471                 (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
1472         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
1473         REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
1474         udelay(40);
1475
1476         /* address */
1477         val = ((phy->addr << 21) | (devad << 16) | reg |
1478                EMAC_MDIO_COMM_COMMAND_ADDRESS |
1479                EMAC_MDIO_COMM_START_BUSY);
1480         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1481
1482         for (i = 0; i < 50; i++) {
1483                 udelay(10);
1484
1485                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
1486                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1487                         udelay(5);
1488                         break;
1489                 }
1490         }
1491         if (val & EMAC_MDIO_COMM_START_BUSY) {
1492                 DP(NETIF_MSG_LINK, "read phy register failed\n");
1493
1494                 *ret_val = 0;
1495                 rc = -EFAULT;
1496
1497         } else {
1498                 /* data */
1499                 val = ((phy->addr << 21) | (devad << 16) |
1500                        EMAC_MDIO_COMM_COMMAND_READ_45 |
1501                        EMAC_MDIO_COMM_START_BUSY);
1502                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
1503
1504                 for (i = 0; i < 50; i++) {
1505                         udelay(10);
1506
1507                         val = REG_RD(bp, phy->mdio_ctrl +
1508                                           EMAC_REG_EMAC_MDIO_COMM);
1509                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
1510                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
1511                                 break;
1512                         }
1513                 }
1514                 if (val & EMAC_MDIO_COMM_START_BUSY) {
1515                         DP(NETIF_MSG_LINK, "read phy register failed\n");
1516
1517                         *ret_val = 0;
1518                         rc = -EFAULT;
1519                 }
1520         }
1521
1522         /* Restore the saved mode */
1523         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
1524
1525         return rc;
1526 }
1527
1528 u8 bnx2x_phy_read(struct link_params *params, u8 phy_addr,
1529                   u8 devad, u16 reg, u16 *ret_val)
1530 {
1531         u8 phy_index;
1532         /**
1533          * Probe for the phy according to the given phy_addr, and execute
1534          * the read request on it
1535          */
1536         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1537                 if (params->phy[phy_index].addr == phy_addr) {
1538                         return bnx2x_cl45_read(params->bp,
1539                                                &params->phy[phy_index], devad,
1540                                                reg, ret_val);
1541                 }
1542         }
1543         return -EINVAL;
1544 }
1545
1546 u8 bnx2x_phy_write(struct link_params *params, u8 phy_addr,
1547                    u8 devad, u16 reg, u16 val)
1548 {
1549         u8 phy_index;
1550         /**
1551          * Probe for the phy according to the given phy_addr, and execute
1552          * the write request on it
1553          */
1554         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
1555                 if (params->phy[phy_index].addr == phy_addr) {
1556                         return bnx2x_cl45_write(params->bp,
1557                                                 &params->phy[phy_index], devad,
1558                                                 reg, val);
1559                 }
1560         }
1561         return -EINVAL;
1562 }
1563
1564 static void bnx2x_set_aer_mmd_xgxs(struct link_params *params,
1565                                    struct bnx2x_phy *phy)
1566 {
1567         u32 ser_lane;
1568         u16 offset, aer_val;
1569         struct bnx2x *bp = params->bp;
1570         ser_lane = ((params->lane_config &
1571                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1572                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1573
1574         offset = phy->addr + ser_lane;
1575         if (CHIP_IS_E2(bp))
1576                 aer_val = 0x2800 + offset - 1;
1577         else
1578                 aer_val = 0x3800 + offset;
1579         CL45_WR_OVER_CL22(bp, phy,
1580                                 MDIO_REG_BANK_AER_BLOCK,
1581                                 MDIO_AER_BLOCK_AER_REG, aer_val);
1582 }
1583 static void bnx2x_set_aer_mmd_serdes(struct bnx2x *bp,
1584                                      struct bnx2x_phy *phy)
1585 {
1586         CL45_WR_OVER_CL22(bp, phy,
1587                                 MDIO_REG_BANK_AER_BLOCK,
1588                                 MDIO_AER_BLOCK_AER_REG, 0x3800);
1589 }
1590
1591 /******************************************************************/
1592 /*                      Internal phy section                      */
1593 /******************************************************************/
1594
1595 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
1596 {
1597         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1598
1599         /* Set Clause 22 */
1600         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
1601         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
1602         udelay(500);
1603         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
1604         udelay(500);
1605          /* Set Clause 45 */
1606         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
1607 }
1608
1609 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
1610 {
1611         u32 val;
1612
1613         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
1614
1615         val = SERDES_RESET_BITS << (port*16);
1616
1617         /* reset and unreset the SerDes/XGXS */
1618         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1619         udelay(500);
1620         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1621
1622         bnx2x_set_serdes_access(bp, port);
1623
1624         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD +
1625                      port*0x10,
1626                      DEFAULT_PHY_DEV_ADDR);
1627 }
1628
1629 static void bnx2x_xgxs_deassert(struct link_params *params)
1630 {
1631         struct bnx2x *bp = params->bp;
1632         u8 port;
1633         u32 val;
1634         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
1635         port = params->port;
1636
1637         val = XGXS_RESET_BITS << (port*16);
1638
1639         /* reset and unreset the SerDes/XGXS */
1640         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
1641         udelay(500);
1642         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
1643
1644         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
1645                      port*0x18, 0);
1646         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
1647                      params->phy[INT_PHY].def_md_devad);
1648 }
1649
1650
1651 void bnx2x_link_status_update(struct link_params *params,
1652                             struct link_vars   *vars)
1653 {
1654         struct bnx2x *bp = params->bp;
1655         u8 link_10g;
1656         u8 port = params->port;
1657
1658         vars->link_status = REG_RD(bp, params->shmem_base +
1659                                           offsetof(struct shmem_region,
1660                                            port_mb[port].link_status));
1661
1662         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
1663
1664         if (vars->link_up) {
1665                 DP(NETIF_MSG_LINK, "phy link up\n");
1666
1667                 vars->phy_link_up = 1;
1668                 vars->duplex = DUPLEX_FULL;
1669                 switch (vars->link_status &
1670                                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
1671                         case LINK_10THD:
1672                                 vars->duplex = DUPLEX_HALF;
1673                                 /* fall thru */
1674                         case LINK_10TFD:
1675                                 vars->line_speed = SPEED_10;
1676                                 break;
1677
1678                         case LINK_100TXHD:
1679                                 vars->duplex = DUPLEX_HALF;
1680                                 /* fall thru */
1681                         case LINK_100T4:
1682                         case LINK_100TXFD:
1683                                 vars->line_speed = SPEED_100;
1684                                 break;
1685
1686                         case LINK_1000THD:
1687                                 vars->duplex = DUPLEX_HALF;
1688                                 /* fall thru */
1689                         case LINK_1000TFD:
1690                                 vars->line_speed = SPEED_1000;
1691                                 break;
1692
1693                         case LINK_2500THD:
1694                                 vars->duplex = DUPLEX_HALF;
1695                                 /* fall thru */
1696                         case LINK_2500TFD:
1697                                 vars->line_speed = SPEED_2500;
1698                                 break;
1699
1700                         case LINK_10GTFD:
1701                                 vars->line_speed = SPEED_10000;
1702                                 break;
1703
1704                         case LINK_12GTFD:
1705                                 vars->line_speed = SPEED_12000;
1706                                 break;
1707
1708                         case LINK_12_5GTFD:
1709                                 vars->line_speed = SPEED_12500;
1710                                 break;
1711
1712                         case LINK_13GTFD:
1713                                 vars->line_speed = SPEED_13000;
1714                                 break;
1715
1716                         case LINK_15GTFD:
1717                                 vars->line_speed = SPEED_15000;
1718                                 break;
1719
1720                         case LINK_16GTFD:
1721                                 vars->line_speed = SPEED_16000;
1722                                 break;
1723
1724                         default:
1725                                 break;
1726                 }
1727                 vars->flow_ctrl = 0;
1728                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
1729                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
1730
1731                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
1732                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
1733
1734                 if (!vars->flow_ctrl)
1735                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1736
1737                 if (vars->line_speed &&
1738                     ((vars->line_speed == SPEED_10) ||
1739                      (vars->line_speed == SPEED_100))) {
1740                         vars->phy_flags |= PHY_SGMII_FLAG;
1741                 } else {
1742                         vars->phy_flags &= ~PHY_SGMII_FLAG;
1743                 }
1744
1745                 /* anything 10 and over uses the bmac */
1746                 link_10g = ((vars->line_speed == SPEED_10000) ||
1747                             (vars->line_speed == SPEED_12000) ||
1748                             (vars->line_speed == SPEED_12500) ||
1749                             (vars->line_speed == SPEED_13000) ||
1750                             (vars->line_speed == SPEED_15000) ||
1751                             (vars->line_speed == SPEED_16000));
1752                 if (link_10g)
1753                         vars->mac_type = MAC_TYPE_BMAC;
1754                 else
1755                         vars->mac_type = MAC_TYPE_EMAC;
1756
1757         } else { /* link down */
1758                 DP(NETIF_MSG_LINK, "phy link down\n");
1759
1760                 vars->phy_link_up = 0;
1761
1762                 vars->line_speed = 0;
1763                 vars->duplex = DUPLEX_FULL;
1764                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
1765
1766                 /* indicate no mac active */
1767                 vars->mac_type = MAC_TYPE_NONE;
1768         }
1769
1770         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x\n",
1771                  vars->link_status, vars->phy_link_up);
1772         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
1773                  vars->line_speed, vars->duplex, vars->flow_ctrl);
1774 }
1775
1776
1777 static void bnx2x_set_master_ln(struct link_params *params,
1778                                 struct bnx2x_phy *phy)
1779 {
1780         struct bnx2x *bp = params->bp;
1781         u16 new_master_ln, ser_lane;
1782         ser_lane =  ((params->lane_config &
1783                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1784                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1785
1786         /* set the master_ln for AN */
1787         CL45_RD_OVER_CL22(bp, phy,
1788                               MDIO_REG_BANK_XGXS_BLOCK2,
1789                               MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1790                               &new_master_ln);
1791
1792         CL45_WR_OVER_CL22(bp, phy,
1793                               MDIO_REG_BANK_XGXS_BLOCK2 ,
1794                               MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
1795                               (new_master_ln | ser_lane));
1796 }
1797
1798 static u8 bnx2x_reset_unicore(struct link_params *params,
1799                               struct bnx2x_phy *phy,
1800                               u8 set_serdes)
1801 {
1802         struct bnx2x *bp = params->bp;
1803         u16 mii_control;
1804         u16 i;
1805
1806         CL45_RD_OVER_CL22(bp, phy,
1807                               MDIO_REG_BANK_COMBO_IEEE0,
1808                               MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
1809
1810         /* reset the unicore */
1811         CL45_WR_OVER_CL22(bp, phy,
1812                               MDIO_REG_BANK_COMBO_IEEE0,
1813                               MDIO_COMBO_IEEE0_MII_CONTROL,
1814                               (mii_control |
1815                                MDIO_COMBO_IEEO_MII_CONTROL_RESET));
1816         if (set_serdes)
1817                 bnx2x_set_serdes_access(bp, params->port);
1818
1819         /* wait for the reset to self clear */
1820         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
1821                 udelay(5);
1822
1823                 /* the reset erased the previous bank value */
1824                 CL45_RD_OVER_CL22(bp, phy,
1825                               MDIO_REG_BANK_COMBO_IEEE0,
1826                               MDIO_COMBO_IEEE0_MII_CONTROL,
1827                               &mii_control);
1828
1829                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
1830                         udelay(5);
1831                         return 0;
1832                 }
1833         }
1834
1835         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
1836         return -EINVAL;
1837
1838 }
1839
1840 static void bnx2x_set_swap_lanes(struct link_params *params,
1841                                  struct bnx2x_phy *phy)
1842 {
1843         struct bnx2x *bp = params->bp;
1844         /* Each two bits represents a lane number:
1845            No swap is 0123 => 0x1b no need to enable the swap */
1846         u16 ser_lane, rx_lane_swap, tx_lane_swap;
1847
1848         ser_lane = ((params->lane_config &
1849                          PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1850                         PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1851         rx_lane_swap = ((params->lane_config &
1852                              PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1853                             PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1854         tx_lane_swap = ((params->lane_config &
1855                              PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1856                             PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1857
1858         if (rx_lane_swap != 0x1b) {
1859                 CL45_WR_OVER_CL22(bp, phy,
1860                                     MDIO_REG_BANK_XGXS_BLOCK2,
1861                                     MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1862                                     (rx_lane_swap |
1863                                     MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1864                                     MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1865         } else {
1866                 CL45_WR_OVER_CL22(bp, phy,
1867                                       MDIO_REG_BANK_XGXS_BLOCK2,
1868                                       MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1869         }
1870
1871         if (tx_lane_swap != 0x1b) {
1872                 CL45_WR_OVER_CL22(bp, phy,
1873                                       MDIO_REG_BANK_XGXS_BLOCK2,
1874                                       MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1875                                       (tx_lane_swap |
1876                                        MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1877         } else {
1878                 CL45_WR_OVER_CL22(bp, phy,
1879                                       MDIO_REG_BANK_XGXS_BLOCK2,
1880                                       MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1881         }
1882 }
1883
1884 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
1885                                          struct link_params *params)
1886 {
1887         struct bnx2x *bp = params->bp;
1888         u16 control2;
1889         CL45_RD_OVER_CL22(bp, phy,
1890                               MDIO_REG_BANK_SERDES_DIGITAL,
1891                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1892                               &control2);
1893         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
1894                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1895         else
1896                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1897         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
1898                 phy->speed_cap_mask, control2);
1899         CL45_WR_OVER_CL22(bp, phy,
1900                               MDIO_REG_BANK_SERDES_DIGITAL,
1901                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1902                               control2);
1903
1904         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
1905              (phy->speed_cap_mask &
1906                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
1907                 DP(NETIF_MSG_LINK, "XGXS\n");
1908
1909                 CL45_WR_OVER_CL22(bp, phy,
1910                                 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1911                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1912                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1913
1914                 CL45_RD_OVER_CL22(bp, phy,
1915                                 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1916                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1917                                 &control2);
1918
1919
1920                 control2 |=
1921                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1922
1923                 CL45_WR_OVER_CL22(bp, phy,
1924                                 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1925                                 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1926                                 control2);
1927
1928                 /* Disable parallel detection of HiG */
1929                 CL45_WR_OVER_CL22(bp, phy,
1930                                 MDIO_REG_BANK_XGXS_BLOCK2,
1931                                 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1932                                 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1933                                 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1934         }
1935 }
1936
1937 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
1938                               struct link_params *params,
1939                             struct link_vars *vars,
1940                             u8 enable_cl73)
1941 {
1942         struct bnx2x *bp = params->bp;
1943         u16 reg_val;
1944
1945         /* CL37 Autoneg */
1946         CL45_RD_OVER_CL22(bp, phy,
1947                               MDIO_REG_BANK_COMBO_IEEE0,
1948                               MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
1949
1950         /* CL37 Autoneg Enabled */
1951         if (vars->line_speed == SPEED_AUTO_NEG)
1952                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1953         else /* CL37 Autoneg Disabled */
1954                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1955                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1956
1957         CL45_WR_OVER_CL22(bp, phy,
1958                               MDIO_REG_BANK_COMBO_IEEE0,
1959                               MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1960
1961         /* Enable/Disable Autodetection */
1962
1963         CL45_RD_OVER_CL22(bp, phy,
1964                               MDIO_REG_BANK_SERDES_DIGITAL,
1965                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
1966         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
1967                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
1968         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
1969         if (vars->line_speed == SPEED_AUTO_NEG)
1970                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1971         else
1972                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1973
1974         CL45_WR_OVER_CL22(bp, phy,
1975                               MDIO_REG_BANK_SERDES_DIGITAL,
1976                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1977
1978         /* Enable TetonII and BAM autoneg */
1979         CL45_RD_OVER_CL22(bp, phy,
1980                               MDIO_REG_BANK_BAM_NEXT_PAGE,
1981                               MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1982                           &reg_val);
1983         if (vars->line_speed == SPEED_AUTO_NEG) {
1984                 /* Enable BAM aneg Mode and TetonII aneg Mode */
1985                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1986                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1987         } else {
1988                 /* TetonII and BAM Autoneg Disabled */
1989                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1990                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1991         }
1992         CL45_WR_OVER_CL22(bp, phy,
1993                               MDIO_REG_BANK_BAM_NEXT_PAGE,
1994                               MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1995                               reg_val);
1996
1997         if (enable_cl73) {
1998                 /* Enable Cl73 FSM status bits */
1999                 CL45_WR_OVER_CL22(bp, phy,
2000                                       MDIO_REG_BANK_CL73_USERB0,
2001                                     MDIO_CL73_USERB0_CL73_UCTRL,
2002                                       0xe);
2003
2004                 /* Enable BAM Station Manager*/
2005                 CL45_WR_OVER_CL22(bp, phy,
2006                         MDIO_REG_BANK_CL73_USERB0,
2007                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
2008                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
2009                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
2010                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
2011
2012                 /* Advertise CL73 link speeds */
2013                 CL45_RD_OVER_CL22(bp, phy,
2014                                               MDIO_REG_BANK_CL73_IEEEB1,
2015                                               MDIO_CL73_IEEEB1_AN_ADV2,
2016                                               &reg_val);
2017                 if (phy->speed_cap_mask &
2018                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2019                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
2020                 if (phy->speed_cap_mask &
2021                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2022                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
2023
2024                 CL45_WR_OVER_CL22(bp, phy,
2025                                               MDIO_REG_BANK_CL73_IEEEB1,
2026                                               MDIO_CL73_IEEEB1_AN_ADV2,
2027                                       reg_val);
2028
2029                 /* CL73 Autoneg Enabled */
2030                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
2031
2032         } else /* CL73 Autoneg Disabled */
2033                 reg_val = 0;
2034
2035         CL45_WR_OVER_CL22(bp, phy,
2036                               MDIO_REG_BANK_CL73_IEEEB0,
2037                               MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
2038 }
2039
2040 /* program SerDes, forced speed */
2041 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
2042                                  struct link_params *params,
2043                                struct link_vars *vars)
2044 {
2045         struct bnx2x *bp = params->bp;
2046         u16 reg_val;
2047
2048         /* program duplex, disable autoneg and sgmii*/
2049         CL45_RD_OVER_CL22(bp, phy,
2050                               MDIO_REG_BANK_COMBO_IEEE0,
2051                               MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
2052         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
2053                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2054                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
2055         if (phy->req_duplex == DUPLEX_FULL)
2056                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2057         CL45_WR_OVER_CL22(bp, phy,
2058                               MDIO_REG_BANK_COMBO_IEEE0,
2059                               MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
2060
2061         /* program speed
2062            - needed only if the speed is greater than 1G (2.5G or 10G) */
2063         CL45_RD_OVER_CL22(bp, phy,
2064                                       MDIO_REG_BANK_SERDES_DIGITAL,
2065                                       MDIO_SERDES_DIGITAL_MISC1, &reg_val);
2066         /* clearing the speed value before setting the right speed */
2067         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
2068
2069         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
2070                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2071
2072         if (!((vars->line_speed == SPEED_1000) ||
2073               (vars->line_speed == SPEED_100) ||
2074               (vars->line_speed == SPEED_10))) {
2075
2076                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
2077                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
2078                 if (vars->line_speed == SPEED_10000)
2079                         reg_val |=
2080                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
2081                 if (vars->line_speed == SPEED_13000)
2082                         reg_val |=
2083                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
2084         }
2085
2086         CL45_WR_OVER_CL22(bp, phy,
2087                                       MDIO_REG_BANK_SERDES_DIGITAL,
2088                                       MDIO_SERDES_DIGITAL_MISC1, reg_val);
2089
2090 }
2091
2092 static void bnx2x_set_brcm_cl37_advertisment(struct bnx2x_phy *phy,
2093                                              struct link_params *params)
2094 {
2095         struct bnx2x *bp = params->bp;
2096         u16 val = 0;
2097
2098         /* configure the 48 bits for BAM AN */
2099
2100         /* set extended capabilities */
2101         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2102                 val |= MDIO_OVER_1G_UP1_2_5G;
2103         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2104                 val |= MDIO_OVER_1G_UP1_10G;
2105         CL45_WR_OVER_CL22(bp, phy,
2106                               MDIO_REG_BANK_OVER_1G,
2107                               MDIO_OVER_1G_UP1, val);
2108
2109         CL45_WR_OVER_CL22(bp, phy,
2110                               MDIO_REG_BANK_OVER_1G,
2111                               MDIO_OVER_1G_UP3, 0x400);
2112 }
2113
2114 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
2115                                      struct link_params *params, u16 *ieee_fc)
2116 {
2117         struct bnx2x *bp = params->bp;
2118         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
2119         /* resolve pause mode and advertisement
2120          * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
2121
2122         switch (phy->req_flow_ctrl) {
2123         case BNX2X_FLOW_CTRL_AUTO:
2124                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
2125                         *ieee_fc |=
2126                              MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2127                 } else {
2128                         *ieee_fc |=
2129                        MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2130                 }
2131                 break;
2132         case BNX2X_FLOW_CTRL_TX:
2133                 *ieee_fc |=
2134                        MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
2135                 break;
2136
2137         case BNX2X_FLOW_CTRL_RX:
2138         case BNX2X_FLOW_CTRL_BOTH:
2139                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
2140                 break;
2141
2142         case BNX2X_FLOW_CTRL_NONE:
2143         default:
2144                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
2145                 break;
2146         }
2147         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
2148 }
2149
2150 static void bnx2x_set_ieee_aneg_advertisment(struct bnx2x_phy *phy,
2151                                              struct link_params *params,
2152                                            u16 ieee_fc)
2153 {
2154         struct bnx2x *bp = params->bp;
2155         u16 val;
2156         /* for AN, we are always publishing full duplex */
2157
2158         CL45_WR_OVER_CL22(bp, phy,
2159                               MDIO_REG_BANK_COMBO_IEEE0,
2160                               MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
2161         CL45_RD_OVER_CL22(bp, phy,
2162                               MDIO_REG_BANK_CL73_IEEEB1,
2163                               MDIO_CL73_IEEEB1_AN_ADV1, &val);
2164         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
2165         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
2166         CL45_WR_OVER_CL22(bp, phy,
2167                               MDIO_REG_BANK_CL73_IEEEB1,
2168                               MDIO_CL73_IEEEB1_AN_ADV1, val);
2169 }
2170
2171 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
2172                                   struct link_params *params,
2173                                   u8 enable_cl73)
2174 {
2175         struct bnx2x *bp = params->bp;
2176         u16 mii_control;
2177
2178         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
2179         /* Enable and restart BAM/CL37 aneg */
2180
2181         if (enable_cl73) {
2182                 CL45_RD_OVER_CL22(bp, phy,
2183                                       MDIO_REG_BANK_CL73_IEEEB0,
2184                                       MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2185                                       &mii_control);
2186
2187                 CL45_WR_OVER_CL22(bp, phy,
2188                                 MDIO_REG_BANK_CL73_IEEEB0,
2189                                 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2190                                 (mii_control |
2191                                 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
2192                                 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
2193         } else {
2194
2195                 CL45_RD_OVER_CL22(bp, phy,
2196                                       MDIO_REG_BANK_COMBO_IEEE0,
2197                                       MDIO_COMBO_IEEE0_MII_CONTROL,
2198                                       &mii_control);
2199                 DP(NETIF_MSG_LINK,
2200                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
2201                          mii_control);
2202                 CL45_WR_OVER_CL22(bp, phy,
2203                                       MDIO_REG_BANK_COMBO_IEEE0,
2204                                       MDIO_COMBO_IEEE0_MII_CONTROL,
2205                                       (mii_control |
2206                                        MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2207                                        MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
2208         }
2209 }
2210
2211 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
2212                                            struct link_params *params,
2213                                          struct link_vars *vars)
2214 {
2215         struct bnx2x *bp = params->bp;
2216         u16 control1;
2217
2218         /* in SGMII mode, the unicore is always slave */
2219
2220         CL45_RD_OVER_CL22(bp, phy,
2221                               MDIO_REG_BANK_SERDES_DIGITAL,
2222                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2223                       &control1);
2224         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
2225         /* set sgmii mode (and not fiber) */
2226         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
2227                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
2228                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
2229         CL45_WR_OVER_CL22(bp, phy,
2230                               MDIO_REG_BANK_SERDES_DIGITAL,
2231                               MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
2232                               control1);
2233
2234         /* if forced speed */
2235         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
2236                 /* set speed, disable autoneg */
2237                 u16 mii_control;
2238
2239                 CL45_RD_OVER_CL22(bp, phy,
2240                                       MDIO_REG_BANK_COMBO_IEEE0,
2241                                       MDIO_COMBO_IEEE0_MII_CONTROL,
2242                                       &mii_control);
2243                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
2244                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
2245                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
2246
2247                 switch (vars->line_speed) {
2248                 case SPEED_100:
2249                         mii_control |=
2250                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
2251                         break;
2252                 case SPEED_1000:
2253                         mii_control |=
2254                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
2255                         break;
2256                 case SPEED_10:
2257                         /* there is nothing to set for 10M */
2258                         break;
2259                 default:
2260                         /* invalid speed for SGMII */
2261                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2262                                   vars->line_speed);
2263                         break;
2264                 }
2265
2266                 /* setting the full duplex */
2267                 if (phy->req_duplex == DUPLEX_FULL)
2268                         mii_control |=
2269                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
2270                 CL45_WR_OVER_CL22(bp, phy,
2271                                       MDIO_REG_BANK_COMBO_IEEE0,
2272                                       MDIO_COMBO_IEEE0_MII_CONTROL,
2273                                       mii_control);
2274
2275         } else { /* AN mode */
2276                 /* enable and restart AN */
2277                 bnx2x_restart_autoneg(phy, params, 0);
2278         }
2279 }
2280
2281
2282 /*
2283  * link management
2284  */
2285
2286 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
2287 {                                               /*  LD      LP   */
2288         switch (pause_result) {                 /* ASYM P ASYM P */
2289         case 0xb:                               /*   1  0   1  1 */
2290                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
2291                 break;
2292
2293         case 0xe:                               /*   1  1   1  0 */
2294                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
2295                 break;
2296
2297         case 0x5:                               /*   0  1   0  1 */
2298         case 0x7:                               /*   0  1   1  1 */
2299         case 0xd:                               /*   1  1   0  1 */
2300         case 0xf:                               /*   1  1   1  1 */
2301                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
2302                 break;
2303
2304         default:
2305                 break;
2306         }
2307         if (pause_result & (1<<0))
2308                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
2309         if (pause_result & (1<<1))
2310                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
2311 }
2312
2313 static u8 bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
2314                                             struct link_params *params)
2315 {
2316         struct bnx2x *bp = params->bp;
2317         u16 pd_10g, status2_1000x;
2318         if (phy->req_line_speed != SPEED_AUTO_NEG)
2319                 return 0;
2320         CL45_RD_OVER_CL22(bp, phy,
2321                               MDIO_REG_BANK_SERDES_DIGITAL,
2322                               MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2323                               &status2_1000x);
2324         CL45_RD_OVER_CL22(bp, phy,
2325                               MDIO_REG_BANK_SERDES_DIGITAL,
2326                               MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
2327                               &status2_1000x);
2328         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
2329                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
2330                          params->port);
2331                 return 1;
2332         }
2333
2334         CL45_RD_OVER_CL22(bp, phy,
2335                               MDIO_REG_BANK_10G_PARALLEL_DETECT,
2336                               MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
2337                               &pd_10g);
2338
2339         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
2340                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
2341                          params->port);
2342                 return 1;
2343         }
2344         return 0;
2345 }
2346
2347 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
2348                                     struct link_params *params,
2349                                     struct link_vars *vars,
2350                                     u32 gp_status)
2351 {
2352         struct bnx2x *bp = params->bp;
2353         u16 ld_pause;   /* local driver */
2354         u16 lp_pause;   /* link partner */
2355         u16 pause_result;
2356
2357         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2358
2359         /* resolve from gp_status in case of AN complete and not sgmii */
2360         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
2361                 vars->flow_ctrl = phy->req_flow_ctrl;
2362         else if (phy->req_line_speed != SPEED_AUTO_NEG)
2363                 vars->flow_ctrl = params->req_fc_auto_adv;
2364         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
2365                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
2366                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
2367                         vars->flow_ctrl = params->req_fc_auto_adv;
2368                         return;
2369                 }
2370                 if ((gp_status &
2371                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2372                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
2373                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
2374                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
2375
2376                         CL45_RD_OVER_CL22(bp, phy,
2377                                               MDIO_REG_BANK_CL73_IEEEB1,
2378                                               MDIO_CL73_IEEEB1_AN_ADV1,
2379                                               &ld_pause);
2380                         CL45_RD_OVER_CL22(bp, phy,
2381                                              MDIO_REG_BANK_CL73_IEEEB1,
2382                                              MDIO_CL73_IEEEB1_AN_LP_ADV1,
2383                                              &lp_pause);
2384                         pause_result = (ld_pause &
2385                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
2386                                         >> 8;
2387                         pause_result |= (lp_pause &
2388                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
2389                                         >> 10;
2390                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
2391                                  pause_result);
2392                 } else {
2393                         CL45_RD_OVER_CL22(bp, phy,
2394                                               MDIO_REG_BANK_COMBO_IEEE0,
2395                                               MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
2396                                               &ld_pause);
2397                         CL45_RD_OVER_CL22(bp, phy,
2398                                MDIO_REG_BANK_COMBO_IEEE0,
2399                                MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
2400                                &lp_pause);
2401                         pause_result = (ld_pause &
2402                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
2403                         pause_result |= (lp_pause &
2404                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
2405                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
2406                                  pause_result);
2407                 }
2408                 bnx2x_pause_resolve(vars, pause_result);
2409         }
2410         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
2411 }
2412
2413 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
2414                                          struct link_params *params)
2415 {
2416         struct bnx2x *bp = params->bp;
2417         u16 rx_status, ustat_val, cl37_fsm_recieved;
2418         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
2419         /* Step 1: Make sure signal is detected */
2420         CL45_RD_OVER_CL22(bp, phy,
2421                               MDIO_REG_BANK_RX0,
2422                               MDIO_RX0_RX_STATUS,
2423                               &rx_status);
2424         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
2425             (MDIO_RX0_RX_STATUS_SIGDET)) {
2426                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
2427                              "rx_status(0x80b0) = 0x%x\n", rx_status);
2428                 CL45_WR_OVER_CL22(bp, phy,
2429                                       MDIO_REG_BANK_CL73_IEEEB0,
2430                                       MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2431                                       MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
2432                 return;
2433         }
2434         /* Step 2: Check CL73 state machine */
2435         CL45_RD_OVER_CL22(bp, phy,
2436                               MDIO_REG_BANK_CL73_USERB0,
2437                               MDIO_CL73_USERB0_CL73_USTAT1,
2438                               &ustat_val);
2439         if ((ustat_val &
2440              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2441               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
2442             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
2443               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
2444                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
2445                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
2446                 return;
2447         }
2448         /* Step 3: Check CL37 Message Pages received to indicate LP
2449         supports only CL37 */
2450         CL45_RD_OVER_CL22(bp, phy,
2451                               MDIO_REG_BANK_REMOTE_PHY,
2452                               MDIO_REMOTE_PHY_MISC_RX_STATUS,
2453                               &cl37_fsm_recieved);
2454         if ((cl37_fsm_recieved &
2455              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2456              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
2457             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
2458               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
2459                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
2460                              "misc_rx_status(0x8330) = 0x%x\n",
2461                          cl37_fsm_recieved);
2462                 return;
2463         }
2464         /* The combined cl37/cl73 fsm state information indicating that we are
2465         connected to a device which does not support cl73, but does support
2466         cl37 BAM. In this case we disable cl73 and restart cl37 auto-neg */
2467         /* Disable CL73 */
2468         CL45_WR_OVER_CL22(bp, phy,
2469                               MDIO_REG_BANK_CL73_IEEEB0,
2470                               MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
2471                               0);
2472         /* Restart CL37 autoneg */
2473         bnx2x_restart_autoneg(phy, params, 0);
2474         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
2475 }
2476
2477 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
2478                                   struct link_params *params,
2479                                   struct link_vars *vars,
2480                                   u32 gp_status)
2481 {
2482         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
2483                 vars->link_status |=
2484                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
2485
2486         if (bnx2x_direct_parallel_detect_used(phy, params))
2487                 vars->link_status |=
2488                         LINK_STATUS_PARALLEL_DETECTION_USED;
2489 }
2490
2491 static u8 bnx2x_link_settings_status(struct bnx2x_phy *phy,
2492                                      struct link_params *params,
2493                                      struct link_vars *vars)
2494 {
2495         struct bnx2x *bp = params->bp;
2496         u16 new_line_speed , gp_status;
2497         u8 rc = 0;
2498
2499         /* Read gp_status */
2500         CL45_RD_OVER_CL22(bp, phy,
2501                                 MDIO_REG_BANK_GP_STATUS,
2502                                 MDIO_GP_STATUS_TOP_AN_STATUS1,
2503                                 &gp_status);
2504
2505         if (phy->req_line_speed == SPEED_AUTO_NEG)
2506                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
2507         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
2508                 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
2509                          gp_status);
2510
2511                 vars->phy_link_up = 1;
2512                 vars->link_status |= LINK_STATUS_LINK_UP;
2513
2514                 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
2515                         vars->duplex = DUPLEX_FULL;
2516                 else
2517                         vars->duplex = DUPLEX_HALF;
2518
2519                 if (SINGLE_MEDIA_DIRECT(params)) {
2520                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
2521                         if (phy->req_line_speed == SPEED_AUTO_NEG)
2522                                 bnx2x_xgxs_an_resolve(phy, params, vars,
2523                                                       gp_status);
2524                 }
2525
2526                 switch (gp_status & GP_STATUS_SPEED_MASK) {
2527                 case GP_STATUS_10M:
2528                         new_line_speed = SPEED_10;
2529                         if (vars->duplex == DUPLEX_FULL)
2530                                 vars->link_status |= LINK_10TFD;
2531                         else
2532                                 vars->link_status |= LINK_10THD;
2533                         break;
2534
2535                 case GP_STATUS_100M:
2536                         new_line_speed = SPEED_100;
2537                         if (vars->duplex == DUPLEX_FULL)
2538                                 vars->link_status |= LINK_100TXFD;
2539                         else
2540                                 vars->link_status |= LINK_100TXHD;
2541                         break;
2542
2543                 case GP_STATUS_1G:
2544                 case GP_STATUS_1G_KX:
2545                         new_line_speed = SPEED_1000;
2546                         if (vars->duplex == DUPLEX_FULL)
2547                                 vars->link_status |= LINK_1000TFD;
2548                         else
2549                                 vars->link_status |= LINK_1000THD;
2550                         break;
2551
2552                 case GP_STATUS_2_5G:
2553                         new_line_speed = SPEED_2500;
2554                         if (vars->duplex == DUPLEX_FULL)
2555                                 vars->link_status |= LINK_2500TFD;
2556                         else
2557                                 vars->link_status |= LINK_2500THD;
2558                         break;
2559
2560                 case GP_STATUS_5G:
2561                 case GP_STATUS_6G:
2562                         DP(NETIF_MSG_LINK,
2563                                  "link speed unsupported  gp_status 0x%x\n",
2564                                   gp_status);
2565                         return -EINVAL;
2566
2567                 case GP_STATUS_10G_KX4:
2568                 case GP_STATUS_10G_HIG:
2569                 case GP_STATUS_10G_CX4:
2570                         new_line_speed = SPEED_10000;
2571                         vars->link_status |= LINK_10GTFD;
2572                         break;
2573
2574                 case GP_STATUS_12G_HIG:
2575                         new_line_speed = SPEED_12000;
2576                         vars->link_status |= LINK_12GTFD;
2577                         break;
2578
2579                 case GP_STATUS_12_5G:
2580                         new_line_speed = SPEED_12500;
2581                         vars->link_status |= LINK_12_5GTFD;
2582                         break;
2583
2584                 case GP_STATUS_13G:
2585                         new_line_speed = SPEED_13000;
2586                         vars->link_status |= LINK_13GTFD;
2587                         break;
2588
2589                 case GP_STATUS_15G:
2590                         new_line_speed = SPEED_15000;
2591                         vars->link_status |= LINK_15GTFD;
2592                         break;
2593
2594                 case GP_STATUS_16G:
2595                         new_line_speed = SPEED_16000;
2596                         vars->link_status |= LINK_16GTFD;
2597                         break;
2598
2599                 default:
2600                         DP(NETIF_MSG_LINK,
2601                                   "link speed unsupported gp_status 0x%x\n",
2602                                   gp_status);
2603                         return -EINVAL;
2604                 }
2605
2606                 vars->line_speed = new_line_speed;
2607
2608         } else { /* link_down */
2609                 DP(NETIF_MSG_LINK, "phy link down\n");
2610
2611                 vars->phy_link_up = 0;
2612
2613                 vars->duplex = DUPLEX_FULL;
2614                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2615                 vars->mac_type = MAC_TYPE_NONE;
2616
2617                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
2618                     SINGLE_MEDIA_DIRECT(params)) {
2619                         /* Check signal is detected */
2620                         bnx2x_check_fallback_to_cl37(phy, params);
2621                 }
2622         }
2623
2624         DP(NETIF_MSG_LINK, "gp_status 0x%x  phy_link_up %x line_speed %x\n",
2625                  gp_status, vars->phy_link_up, vars->line_speed);
2626         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
2627                    vars->duplex, vars->flow_ctrl, vars->link_status);
2628         return rc;
2629 }
2630
2631 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
2632 {
2633         struct bnx2x *bp = params->bp;
2634         struct bnx2x_phy *phy = &params->phy[INT_PHY];
2635         u16 lp_up2;
2636         u16 tx_driver;
2637         u16 bank;
2638
2639         /* read precomp */
2640         CL45_RD_OVER_CL22(bp, phy,
2641                               MDIO_REG_BANK_OVER_1G,
2642                               MDIO_OVER_1G_LP_UP2, &lp_up2);
2643
2644         /* bits [10:7] at lp_up2, positioned at [15:12] */
2645         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
2646                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
2647                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
2648
2649         if (lp_up2 == 0)
2650                 return;
2651
2652         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
2653               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
2654                 CL45_RD_OVER_CL22(bp, phy,
2655                                       bank,
2656                                       MDIO_TX0_TX_DRIVER, &tx_driver);
2657
2658                 /* replace tx_driver bits [15:12] */
2659                 if (lp_up2 !=
2660                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
2661                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
2662                         tx_driver |= lp_up2;
2663                         CL45_WR_OVER_CL22(bp, phy,
2664                                               bank,
2665                                               MDIO_TX0_TX_DRIVER, tx_driver);
2666                 }
2667         }
2668 }
2669
2670 static u8 bnx2x_emac_program(struct link_params *params,
2671                              struct link_vars *vars)
2672 {
2673         struct bnx2x *bp = params->bp;
2674         u8 port = params->port;
2675         u16 mode = 0;
2676
2677         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
2678         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
2679                      EMAC_REG_EMAC_MODE,
2680                      (EMAC_MODE_25G_MODE |
2681                      EMAC_MODE_PORT_MII_10M |
2682                      EMAC_MODE_HALF_DUPLEX));
2683         switch (vars->line_speed) {
2684         case SPEED_10:
2685                 mode |= EMAC_MODE_PORT_MII_10M;
2686                 break;
2687
2688         case SPEED_100:
2689                 mode |= EMAC_MODE_PORT_MII;
2690                 break;
2691
2692         case SPEED_1000:
2693                 mode |= EMAC_MODE_PORT_GMII;
2694                 break;
2695
2696         case SPEED_2500:
2697                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
2698                 break;
2699
2700         default:
2701                 /* 10G not valid for EMAC */
2702                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2703                            vars->line_speed);
2704                 return -EINVAL;
2705         }
2706
2707         if (vars->duplex == DUPLEX_HALF)
2708                 mode |= EMAC_MODE_HALF_DUPLEX;
2709         bnx2x_bits_en(bp,
2710                     GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
2711                     mode);
2712
2713         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
2714         return 0;
2715 }
2716
2717 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
2718                                   struct link_params *params)
2719 {
2720
2721         u16 bank, i = 0;
2722         struct bnx2x *bp = params->bp;
2723
2724         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
2725               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
2726                         CL45_WR_OVER_CL22(bp, phy,
2727                                           bank,
2728                                           MDIO_RX0_RX_EQ_BOOST,
2729                                           phy->rx_preemphasis[i]);
2730         }
2731
2732         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
2733                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
2734                         CL45_WR_OVER_CL22(bp, phy,
2735                                           bank,
2736                                           MDIO_TX0_TX_DRIVER,
2737                                           phy->tx_preemphasis[i]);
2738         }
2739 }
2740
2741 static void bnx2x_init_internal_phy(struct bnx2x_phy *phy,
2742                                     struct link_params *params,
2743                                     struct link_vars *vars)
2744 {
2745         struct bnx2x *bp = params->bp;
2746         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
2747                           (params->loopback_mode == LOOPBACK_XGXS));
2748         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2749                 if (SINGLE_MEDIA_DIRECT(params) &&
2750                     (params->feature_config_flags &
2751                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
2752                         bnx2x_set_preemphasis(phy, params);
2753
2754                 /* forced speed requested? */
2755                 if (vars->line_speed != SPEED_AUTO_NEG ||
2756                     (SINGLE_MEDIA_DIRECT(params) &&
2757                           params->loopback_mode == LOOPBACK_EXT)) {
2758                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2759
2760                         /* disable autoneg */
2761                         bnx2x_set_autoneg(phy, params, vars, 0);
2762
2763                         /* program speed and duplex */
2764                         bnx2x_program_serdes(phy, params, vars);
2765
2766                 } else { /* AN_mode */
2767                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2768
2769                         /* AN enabled */
2770                         bnx2x_set_brcm_cl37_advertisment(phy, params);
2771
2772                         /* program duplex & pause advertisement (for aneg) */
2773                         bnx2x_set_ieee_aneg_advertisment(phy, params,
2774                                                        vars->ieee_fc);
2775
2776                         /* enable autoneg */
2777                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
2778
2779                         /* enable and restart AN */
2780                         bnx2x_restart_autoneg(phy, params, enable_cl73);
2781                 }
2782
2783         } else { /* SGMII mode */
2784                 DP(NETIF_MSG_LINK, "SGMII\n");
2785
2786                 bnx2x_initialize_sgmii_process(phy, params, vars);
2787         }
2788 }
2789
2790 static u8 bnx2x_init_serdes(struct bnx2x_phy *phy,
2791                             struct link_params *params,
2792                             struct link_vars *vars)
2793 {
2794         u8 rc;
2795         vars->phy_flags |= PHY_SGMII_FLAG;
2796         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2797         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2798         rc = bnx2x_reset_unicore(params, phy, 1);
2799         /* reset the SerDes and wait for reset bit return low */
2800         if (rc != 0)
2801                 return rc;
2802         bnx2x_set_aer_mmd_serdes(params->bp, phy);
2803
2804         return rc;
2805 }
2806
2807 static u8 bnx2x_init_xgxs(struct bnx2x_phy *phy,
2808                           struct link_params *params,
2809                           struct link_vars *vars)
2810 {
2811         u8 rc;
2812         vars->phy_flags = PHY_XGXS_FLAG;
2813         if ((phy->req_line_speed &&
2814              ((phy->req_line_speed == SPEED_100) ||
2815               (phy->req_line_speed == SPEED_10))) ||
2816             (!phy->req_line_speed &&
2817              (phy->speed_cap_mask >=
2818               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
2819              (phy->speed_cap_mask <
2820               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2821              ))
2822                 vars->phy_flags |= PHY_SGMII_FLAG;
2823         else
2824                 vars->phy_flags &= ~PHY_SGMII_FLAG;
2825
2826         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
2827         bnx2x_set_aer_mmd_xgxs(params, phy);
2828         bnx2x_set_master_ln(params, phy);
2829
2830         rc = bnx2x_reset_unicore(params, phy, 0);
2831         /* reset the SerDes and wait for reset bit return low */
2832         if (rc != 0)
2833                 return rc;
2834
2835         bnx2x_set_aer_mmd_xgxs(params, phy);
2836
2837         /* setting the masterLn_def again after the reset */
2838         bnx2x_set_master_ln(params, phy);
2839         bnx2x_set_swap_lanes(params, phy);
2840
2841         return rc;
2842 }
2843
2844 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
2845                                      struct bnx2x_phy *phy)
2846 {
2847         u16 cnt, ctrl;
2848         /* Wait for soft reset to get cleared upto 1 sec */
2849         for (cnt = 0; cnt < 1000; cnt++) {
2850                 bnx2x_cl45_read(bp, phy,
2851                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, &ctrl);
2852                 if (!(ctrl & (1<<15)))
2853                         break;
2854                 msleep(1);
2855         }
2856         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
2857         return cnt;
2858 }
2859
2860 static void bnx2x_link_int_enable(struct link_params *params)
2861 {
2862         u8 port = params->port;
2863         u32 mask;
2864         struct bnx2x *bp = params->bp;
2865
2866         /* setting the status to report on link up
2867            for either XGXS or SerDes */
2868
2869         if (params->switch_cfg == SWITCH_CFG_10G) {
2870                 mask = (NIG_MASK_XGXS0_LINK10G |
2871                         NIG_MASK_XGXS0_LINK_STATUS);
2872                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
2873                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2874                         params->phy[INT_PHY].type !=
2875                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
2876                         mask |= NIG_MASK_MI_INT;
2877                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2878                 }
2879
2880         } else { /* SerDes */
2881                 mask = NIG_MASK_SERDES0_LINK_STATUS;
2882                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
2883                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
2884                         params->phy[INT_PHY].type !=
2885                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
2886                         mask |= NIG_MASK_MI_INT;
2887                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
2888                 }
2889         }
2890         bnx2x_bits_en(bp,
2891                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
2892                       mask);
2893
2894         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
2895                  (params->switch_cfg == SWITCH_CFG_10G),
2896                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
2897         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
2898                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
2899                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
2900                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
2901         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
2902            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
2903            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
2904 }
2905
2906 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
2907                                      u8 exp_mi_int)
2908 {
2909         u32 latch_status = 0;
2910
2911         /**
2912          * Disable the MI INT ( external phy int ) by writing 1 to the
2913          * status register. Link down indication is high-active-signal,
2914          * so in this case we need to write the status to clear the XOR
2915          */
2916         /* Read Latched signals */
2917         latch_status = REG_RD(bp,
2918                                     NIG_REG_LATCH_STATUS_0 + port*8);
2919         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
2920         /* Handle only those with latched-signal=up.*/
2921         if (exp_mi_int)
2922                 bnx2x_bits_en(bp,
2923                               NIG_REG_STATUS_INTERRUPT_PORT0
2924                               + port*4,
2925                               NIG_STATUS_EMAC0_MI_INT);
2926         else
2927                 bnx2x_bits_dis(bp,
2928                                NIG_REG_STATUS_INTERRUPT_PORT0
2929                                + port*4,
2930                                NIG_STATUS_EMAC0_MI_INT);
2931
2932         if (latch_status & 1) {
2933
2934                 /* For all latched-signal=up : Re-Arm Latch signals */
2935                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
2936                              (latch_status & 0xfffe) | (latch_status & 1));
2937         }
2938         /* For all latched-signal=up,Write original_signal to status */
2939 }
2940
2941 static void bnx2x_link_int_ack(struct link_params *params,
2942                              struct link_vars *vars, u8 is_10g)
2943 {
2944         struct bnx2x *bp = params->bp;
2945         u8 port = params->port;
2946
2947         /* first reset all status
2948          * we assume only one line will be change at a time */
2949         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2950                      (NIG_STATUS_XGXS0_LINK10G |
2951                       NIG_STATUS_XGXS0_LINK_STATUS |
2952                       NIG_STATUS_SERDES0_LINK_STATUS));
2953         if (vars->phy_link_up) {
2954                 if (is_10g) {
2955                         /* Disable the 10G link interrupt
2956                          * by writing 1 to the status register
2957                          */
2958                         DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
2959                         bnx2x_bits_en(bp,
2960                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2961                                       NIG_STATUS_XGXS0_LINK10G);
2962
2963                 } else if (params->switch_cfg == SWITCH_CFG_10G) {
2964                         /* Disable the link interrupt
2965                          * by writing 1 to the relevant lane
2966                          * in the status register
2967                          */
2968                         u32 ser_lane = ((params->lane_config &
2969                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2970                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2971
2972                         DP(NETIF_MSG_LINK, "%d speed XGXS phy link up\n",
2973                                  vars->line_speed);
2974                         bnx2x_bits_en(bp,
2975                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2976                                       ((1 << ser_lane) <<
2977                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
2978
2979                 } else { /* SerDes */
2980                         DP(NETIF_MSG_LINK, "SerDes phy link up\n");
2981                         /* Disable the link interrupt
2982                          * by writing 1 to the status register
2983                          */
2984                         bnx2x_bits_en(bp,
2985                                       NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
2986                                       NIG_STATUS_SERDES0_LINK_STATUS);
2987                 }
2988
2989         }
2990 }
2991
2992 static u8 bnx2x_format_ver(u32 num, u8 *str, u16 *len)
2993 {
2994         u8 *str_ptr = str;
2995         u32 mask = 0xf0000000;
2996         u8 shift = 8*4;
2997         u8 digit;
2998         u8 remove_leading_zeros = 1;
2999         if (*len < 10) {
3000                 /* Need more than 10chars for this format */
3001                 *str_ptr = '\0';
3002                 (*len)--;
3003                 return -EINVAL;
3004         }
3005         while (shift > 0) {
3006
3007                 shift -= 4;
3008                 digit = ((num & mask) >> shift);
3009                 if (digit == 0 && remove_leading_zeros) {
3010                         mask = mask >> 4;
3011                         continue;
3012                 } else if (digit < 0xa)
3013                         *str_ptr = digit + '0';
3014                 else
3015                         *str_ptr = digit - 0xa + 'a';
3016                 remove_leading_zeros = 0;
3017                 str_ptr++;
3018                 (*len)--;
3019                 mask = mask >> 4;
3020                 if (shift == 4*4) {
3021                         *str_ptr = '.';
3022                         str_ptr++;
3023                         (*len)--;
3024                         remove_leading_zeros = 1;
3025                 }
3026         }
3027         return 0;
3028 }
3029
3030
3031 static u8 bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
3032 {
3033         str[0] = '\0';
3034         (*len)--;
3035         return 0;
3036 }
3037
3038 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3039                               u8 *version, u16 len)
3040 {
3041         struct bnx2x *bp;
3042         u32 spirom_ver = 0;
3043         u8 status = 0;
3044         u8 *ver_p = version;
3045         u16 remain_len = len;
3046         if (version == NULL || params == NULL)
3047                 return -EINVAL;
3048         bp = params->bp;
3049
3050         /* Extract first external phy*/
3051         version[0] = '\0';
3052         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
3053
3054         if (params->phy[EXT_PHY1].format_fw_ver) {
3055                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
3056                                                               ver_p,
3057                                                               &remain_len);
3058                 ver_p += (len - remain_len);
3059         }
3060         if ((params->num_phys == MAX_PHYS) &&
3061             (params->phy[EXT_PHY2].ver_addr != 0)) {
3062                 spirom_ver = REG_RD(bp,
3063                                           params->phy[EXT_PHY2].ver_addr);
3064                 if (params->phy[EXT_PHY2].format_fw_ver) {
3065                         *ver_p = '/';
3066                         ver_p++;
3067                         remain_len--;
3068                         status |= params->phy[EXT_PHY2].format_fw_ver(
3069                                 spirom_ver,
3070                                 ver_p,
3071                                 &remain_len);
3072                         ver_p = version + (len - remain_len);
3073                 }
3074         }
3075         *ver_p = '\0';
3076         return status;
3077 }
3078
3079 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
3080                                     struct link_params *params)
3081 {
3082         u8 port = params->port;
3083         struct bnx2x *bp = params->bp;
3084
3085         if (phy->req_line_speed != SPEED_1000) {
3086                 u32 md_devad;
3087
3088                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3089
3090                 /* change the uni_phy_addr in the nig */
3091                 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3092                                           port*0x18));
3093
3094                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3095
3096                 bnx2x_cl45_write(bp, phy,
3097                                5,
3098                                (MDIO_REG_BANK_AER_BLOCK +
3099                                 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3100                                0x2800);
3101
3102                 bnx2x_cl45_write(bp, phy,
3103                                5,
3104                                (MDIO_REG_BANK_CL73_IEEEB0 +
3105                                 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3106                                0x6041);
3107                 msleep(200);
3108                 /* set aer mmd back */
3109                 bnx2x_set_aer_mmd_xgxs(params, phy);
3110
3111                 /* and md_devad */
3112                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3113                             md_devad);
3114
3115         } else {
3116                 u16 mii_ctrl;
3117                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3118                 bnx2x_cl45_read(bp, phy, 5,
3119                                 (MDIO_REG_BANK_COMBO_IEEE0 +
3120                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3121                                 &mii_ctrl);
3122                 bnx2x_cl45_write(bp, phy, 5,
3123                                  (MDIO_REG_BANK_COMBO_IEEE0 +
3124                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
3125                                  mii_ctrl |
3126                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
3127         }
3128 }
3129
3130 u8 bnx2x_set_led(struct link_params *params,
3131                  struct link_vars *vars, u8 mode, u32 speed)
3132 {
3133         u8 port = params->port;
3134         u16 hw_led_mode = params->hw_led_mode;
3135         u8 rc = 0, phy_idx;
3136         u32 tmp;
3137         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3138         struct bnx2x *bp = params->bp;
3139         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3140         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3141                  speed, hw_led_mode);
3142         /* In case */
3143         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
3144                 if (params->phy[phy_idx].set_link_led) {
3145                         params->phy[phy_idx].set_link_led(
3146                                 &params->phy[phy_idx], params, mode);
3147                 }
3148         }
3149
3150         switch (mode) {
3151         case LED_MODE_FRONT_PANEL_OFF:
3152         case LED_MODE_OFF:
3153                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3154                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3155                            SHARED_HW_CFG_LED_MAC1);
3156
3157                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3158                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
3159                 break;
3160
3161         case LED_MODE_OPER:
3162                 /**
3163                  * For all other phys, OPER mode is same as ON, so in case
3164                  * link is down, do nothing
3165                  **/
3166                 if (!vars->link_up)
3167                         break;
3168         case LED_MODE_ON:
3169                 if (SINGLE_MEDIA_DIRECT(params)) {
3170                         /**
3171                         * This is a work-around for HW issue found when link
3172                         * is up in CL73
3173                         */
3174                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
3175                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
3176                 } else {
3177                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3178                                    hw_led_mode);
3179                 }
3180
3181                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
3182                            port*4, 0);
3183                 /* Set blinking rate to ~15.9Hz */
3184                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3185                            LED_BLINK_RATE_VAL);
3186                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3187                            port*4, 1);
3188                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
3189                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
3190                             (tmp & (~EMAC_LED_OVERRIDE)));
3191
3192                 if (CHIP_IS_E1(bp) &&
3193                     ((speed == SPEED_2500) ||
3194                      (speed == SPEED_1000) ||
3195                      (speed == SPEED_100) ||
3196                      (speed == SPEED_10))) {
3197                         /* On Everest 1 Ax chip versions for speeds less than
3198                         10G LED scheme is different */
3199                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3200                                    + port*4, 1);
3201                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3202                                    port*4, 0);
3203                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3204                                    port*4, 1);
3205                 }
3206                 break;
3207
3208         default:
3209                 rc = -EINVAL;
3210                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3211                          mode);
3212                 break;
3213         }
3214         return rc;
3215
3216 }
3217
3218 /**
3219  * This function comes to reflect the actual link state read DIRECTLY from the
3220  * HW
3221  */
3222 u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars,
3223                    u8 is_serdes)
3224 {
3225         struct bnx2x *bp = params->bp;
3226         u16 gp_status = 0, phy_index = 0;
3227         u8 ext_phy_link_up = 0, serdes_phy_type;
3228         struct link_vars temp_vars;
3229
3230         CL45_RD_OVER_CL22(bp, &params->phy[INT_PHY],
3231                               MDIO_REG_BANK_GP_STATUS,
3232                               MDIO_GP_STATUS_TOP_AN_STATUS1,
3233                               &gp_status);
3234         /* link is up only if both local phy and external phy are up */
3235         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
3236                 return -ESRCH;
3237
3238         switch (params->num_phys) {
3239         case 1:
3240                 /* No external PHY */
3241                 return 0;
3242         case 2:
3243                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
3244                         &params->phy[EXT_PHY1],
3245                         params, &temp_vars);
3246                 break;
3247         case 3: /* Dual Media */
3248                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3249                       phy_index++) {
3250                         serdes_phy_type = ((params->phy[phy_index].media_type ==
3251                                             ETH_PHY_SFP_FIBER) ||
3252                                            (params->phy[phy_index].media_type ==
3253                                             ETH_PHY_XFP_FIBER));
3254
3255                         if (is_serdes != serdes_phy_type)
3256                                 continue;
3257                         if (params->phy[phy_index].read_status) {
3258                                 ext_phy_link_up |=
3259                                         params->phy[phy_index].read_status(
3260                                                 &params->phy[phy_index],
3261                                                 params, &temp_vars);
3262                         }
3263                 }
3264                 break;
3265         }
3266         if (ext_phy_link_up)
3267                 return 0;
3268         return -ESRCH;
3269 }
3270
3271 static u8 bnx2x_link_initialize(struct link_params *params,
3272                                 struct link_vars *vars)
3273 {
3274         u8 rc = 0;
3275         u8 phy_index, non_ext_phy;
3276         struct bnx2x *bp = params->bp;
3277         /**
3278         * In case of external phy existence, the line speed would be the
3279         * line speed linked up by the external phy. In case it is direct
3280         * only, then the line_speed during initialization will be
3281         * equal to the req_line_speed
3282         */
3283         vars->line_speed = params->phy[INT_PHY].req_line_speed;
3284
3285         /**
3286          * Initialize the internal phy in case this is a direct board
3287          * (no external phys), or this board has external phy which requires
3288          * to first.
3289          */
3290
3291         if (params->phy[INT_PHY].config_init)
3292                 params->phy[INT_PHY].config_init(
3293                         &params->phy[INT_PHY],
3294                         params, vars);
3295
3296         /* init ext phy and enable link state int */
3297         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
3298                        (params->loopback_mode == LOOPBACK_XGXS));
3299
3300         if (non_ext_phy ||
3301             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
3302             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3303                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
3304                 if (vars->line_speed == SPEED_AUTO_NEG)
3305                         bnx2x_set_parallel_detection(phy, params);
3306                 bnx2x_init_internal_phy(phy, params, vars);
3307         }
3308
3309         /* Init external phy*/
3310         if (!non_ext_phy)
3311                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3312                       phy_index++) {
3313                         /**
3314                          * No need to initialize second phy in case of first
3315                          * phy only selection. In case of second phy, we do
3316                          * need to initialize the first phy, since they are
3317                          * connected.
3318                          **/
3319                         if (phy_index == EXT_PHY2 &&
3320                             (bnx2x_phy_selection(params) ==
3321                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
3322                                 DP(NETIF_MSG_LINK, "Not initializing"
3323                                                    "second phy\n");
3324                                 continue;
3325                         }
3326                         params->phy[phy_index].config_init(
3327                                 &params->phy[phy_index],
3328                                 params, vars);
3329                 }
3330
3331         /* Reset the interrupt indication after phy was initialized */
3332         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
3333                        params->port*4,
3334                        (NIG_STATUS_XGXS0_LINK10G |
3335                         NIG_STATUS_XGXS0_LINK_STATUS |
3336                         NIG_STATUS_SERDES0_LINK_STATUS |
3337                         NIG_MASK_MI_INT));
3338         return rc;
3339 }
3340
3341 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
3342                                  struct link_params *params)
3343 {
3344         /* reset the SerDes/XGXS */
3345         REG_WR(params->bp, GRCBASE_MISC +
3346                      MISC_REGISTERS_RESET_REG_3_CLEAR,
3347                      (0x1ff << (params->port*16)));
3348 }
3349
3350 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
3351                                         struct link_params *params)
3352 {
3353         struct bnx2x *bp = params->bp;
3354         u8 gpio_port;
3355         /* HW reset */
3356         if (CHIP_IS_E2(bp))
3357                 gpio_port = BP_PATH(bp);
3358         else
3359                 gpio_port = params->port;
3360         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3361                             MISC_REGISTERS_GPIO_OUTPUT_LOW,
3362                             gpio_port);
3363         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
3364                             MISC_REGISTERS_GPIO_OUTPUT_LOW,
3365                             gpio_port);
3366         DP(NETIF_MSG_LINK, "reset external PHY\n");
3367 }
3368
3369 static u8 bnx2x_update_link_down(struct link_params *params,
3370                                struct link_vars *vars)
3371 {
3372         struct bnx2x *bp = params->bp;
3373         u8 port = params->port;
3374
3375         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
3376         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
3377
3378         /* indicate no mac active */
3379         vars->mac_type = MAC_TYPE_NONE;
3380
3381         /* update shared memory */
3382         vars->link_status = 0;
3383         vars->line_speed = 0;
3384         bnx2x_update_mng(params, vars->link_status);
3385
3386         /* activate nig drain */
3387         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3388
3389         /* disable emac */
3390         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3391
3392         msleep(10);
3393
3394         /* reset BigMac */
3395         bnx2x_bmac_rx_disable(bp, params->port);
3396         REG_WR(bp, GRCBASE_MISC +
3397                    MISC_REGISTERS_RESET_REG_2_CLEAR,
3398                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3399         return 0;
3400 }
3401
3402 static u8 bnx2x_update_link_up(struct link_params *params,
3403                              struct link_vars *vars,
3404                              u8 link_10g)
3405 {
3406         struct bnx2x *bp = params->bp;
3407         u8 port = params->port;
3408         u8 rc = 0;
3409
3410         vars->link_status |= LINK_STATUS_LINK_UP;
3411
3412         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
3413                 vars->link_status |=
3414                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
3415
3416         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
3417                 vars->link_status |=
3418                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
3419
3420         if (link_10g) {
3421                 bnx2x_bmac_enable(params, vars, 0);
3422                 bnx2x_set_led(params, vars,
3423                               LED_MODE_OPER, SPEED_10000);
3424         } else {
3425                 rc = bnx2x_emac_program(params, vars);
3426
3427                 bnx2x_emac_enable(params, vars, 0);
3428
3429                 /* AN complete? */
3430                 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
3431                     && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
3432                     SINGLE_MEDIA_DIRECT(params))
3433                         bnx2x_set_gmii_tx_driver(params);
3434         }
3435
3436         /* PBF - link up */
3437         if (!(CHIP_IS_E2(bp)))
3438                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
3439                                        vars->line_speed);
3440
3441         /* disable drain */
3442         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
3443
3444         /* update shared memory */
3445         bnx2x_update_mng(params, vars->link_status);
3446         msleep(20);
3447         return rc;
3448 }
3449 /**
3450  * The bnx2x_link_update function should be called upon link
3451  * interrupt.
3452  * Link is considered up as follows:
3453  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
3454  *   to be up
3455  * - SINGLE_MEDIA - The link between the 577xx and the external
3456  *   phy (XGXS) need to up as well as the external link of the
3457  *   phy (PHY_EXT1)
3458  * - DUAL_MEDIA - The link between the 577xx and the first
3459  *   external phy needs to be up, and at least one of the 2
3460  *   external phy link must be up.
3461  */
3462 u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
3463 {
3464         struct bnx2x *bp = params->bp;
3465         struct link_vars phy_vars[MAX_PHYS];
3466         u8 port = params->port;
3467         u8 link_10g, phy_index;
3468         u8 ext_phy_link_up = 0, cur_link_up, rc = 0;
3469         u8 is_mi_int = 0;
3470         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
3471         u8 active_external_phy = INT_PHY;
3472         vars->link_status = 0;
3473         for (phy_index = INT_PHY; phy_index < params->num_phys;
3474               phy_index++) {
3475                 phy_vars[phy_index].flow_ctrl = 0;
3476                 phy_vars[phy_index].link_status = 0;
3477                 phy_vars[phy_index].line_speed = 0;
3478                 phy_vars[phy_index].duplex = DUPLEX_FULL;
3479                 phy_vars[phy_index].phy_link_up = 0;
3480                 phy_vars[phy_index].link_up = 0;
3481         }
3482
3483         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
3484                  port, (vars->phy_flags & PHY_XGXS_FLAG),
3485                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3486
3487         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
3488                                     port*0x18) > 0);
3489         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
3490                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3491                  is_mi_int,
3492                  REG_RD(bp,
3493                             NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
3494
3495         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3496           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3497           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3498
3499         /* disable emac */
3500         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
3501
3502         /**
3503         * Step 1:
3504         * Check external link change only for external phys, and apply
3505         * priority selection between them in case the link on both phys
3506         * is up. Note that the instead of the common vars, a temporary
3507         * vars argument is used since each phy may have different link/
3508         * speed/duplex result
3509         */
3510         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3511               phy_index++) {
3512                 struct bnx2x_phy *phy = &params->phy[phy_index];
3513                 if (!phy->read_status)
3514                         continue;
3515                 /* Read link status and params of this ext phy */
3516                 cur_link_up = phy->read_status(phy, params,
3517                                                &phy_vars[phy_index]);
3518                 if (cur_link_up) {
3519                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
3520                                    phy_index);
3521                 } else {
3522                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
3523                                    phy_index);
3524                         continue;
3525                 }
3526
3527                 if (!ext_phy_link_up) {
3528                         ext_phy_link_up = 1;
3529                         active_external_phy = phy_index;
3530                 } else {
3531                         switch (bnx2x_phy_selection(params)) {
3532                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
3533                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
3534                         /**
3535                          * In this option, the first PHY makes sure to pass the
3536                          * traffic through itself only.
3537                          * Its not clear how to reset the link on the second phy
3538                          **/
3539                                 active_external_phy = EXT_PHY1;
3540                                 break;
3541                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
3542                         /**
3543                          * In this option, the first PHY makes sure to pass the
3544                          * traffic through the second PHY.
3545                          **/
3546                                 active_external_phy = EXT_PHY2;
3547                                 break;
3548                         default:
3549                         /**
3550                          * Link indication on both PHYs with the following cases
3551                          * is invalid:
3552                          * - FIRST_PHY means that second phy wasn't initialized,
3553                          * hence its link is expected to be down
3554                          * - SECOND_PHY means that first phy should not be able
3555                          * to link up by itself (using configuration)
3556                          * - DEFAULT should be overriden during initialiazation
3557                          **/
3558                                 DP(NETIF_MSG_LINK, "Invalid link indication"
3559                                            "mpc=0x%x. DISABLING LINK !!!\n",
3560                                            params->multi_phy_config);
3561                                 ext_phy_link_up = 0;
3562                                 break;
3563                         }
3564                 }
3565         }
3566         prev_line_speed = vars->line_speed;
3567         /**
3568         * Step 2:
3569         * Read the status of the internal phy. In case of
3570         * DIRECT_SINGLE_MEDIA board, this link is the external link,
3571         * otherwise this is the link between the 577xx and the first
3572         * external phy
3573         */
3574         if (params->phy[INT_PHY].read_status)
3575                 params->phy[INT_PHY].read_status(
3576                         &params->phy[INT_PHY],
3577                         params, vars);
3578         /**
3579          * The INT_PHY flow control reside in the vars. This include the
3580          * case where the speed or flow control are not set to AUTO.
3581          * Otherwise, the active external phy flow control result is set
3582          * to the vars. The ext_phy_line_speed is needed to check if the
3583          * speed is different between the internal phy and external phy.
3584          * This case may be result of intermediate link speed change.
3585          */
3586         if (active_external_phy > INT_PHY) {
3587                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
3588                 /**
3589                  * Link speed is taken from the XGXS. AN and FC result from
3590                  * the external phy.
3591                  */
3592                 vars->link_status |= phy_vars[active_external_phy].link_status;
3593
3594                 /**
3595                  * if active_external_phy is first PHY and link is up - disable
3596                  * disable TX on second external PHY
3597                  */
3598                 if (active_external_phy == EXT_PHY1) {
3599                         if (params->phy[EXT_PHY2].phy_specific_func) {
3600                                 DP(NETIF_MSG_LINK, "Disabling TX on"
3601                                                    " EXT_PHY2\n");
3602                                 params->phy[EXT_PHY2].phy_specific_func(
3603                                         &params->phy[EXT_PHY2],
3604                                         params, DISABLE_TX);
3605                         }
3606                 }
3607
3608                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
3609                 vars->duplex = phy_vars[active_external_phy].duplex;
3610                 if (params->phy[active_external_phy].supported &
3611                     SUPPORTED_FIBRE)
3612                         vars->link_status |= LINK_STATUS_SERDES_LINK;
3613                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
3614                            active_external_phy);
3615         }
3616
3617         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
3618               phy_index++) {
3619                 if (params->phy[phy_index].flags &
3620                     FLAGS_REARM_LATCH_SIGNAL) {
3621                         bnx2x_rearm_latch_signal(bp, port,
3622                                                  phy_index ==
3623                                                  active_external_phy);
3624                         break;
3625                 }
3626         }
3627         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
3628                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
3629                    vars->link_status, ext_phy_line_speed);
3630         /**
3631          * Upon link speed change set the NIG into drain mode. Comes to
3632          * deals with possible FIFO glitch due to clk change when speed
3633          * is decreased without link down indicator
3634          */
3635
3636         if (vars->phy_link_up) {
3637                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
3638                     (ext_phy_line_speed != vars->line_speed)) {
3639                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
3640                                    " different than the external"
3641                                    " link speed %d\n", vars->line_speed,
3642                                    ext_phy_line_speed);
3643                         vars->phy_link_up = 0;
3644                 } else if (prev_line_speed != vars->line_speed) {
3645                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
3646                                      + params->port*4, 0);
3647                         msleep(1);
3648                 }
3649         }
3650
3651         /* anything 10 and over uses the bmac */
3652         link_10g = ((vars->line_speed == SPEED_10000) ||
3653                     (vars->line_speed == SPEED_12000) ||
3654                     (vars->line_speed == SPEED_12500) ||
3655                     (vars->line_speed == SPEED_13000) ||
3656                     (vars->line_speed == SPEED_15000) ||
3657                     (vars->line_speed == SPEED_16000));
3658
3659         bnx2x_link_int_ack(params, vars, link_10g);
3660
3661         /**
3662         * In case external phy link is up, and internal link is down
3663         * (not initialized yet probably after link initialization, it
3664         * needs to be initialized.
3665         * Note that after link down-up as result of cable plug, the xgxs
3666         * link would probably become up again without the need
3667         * initialize it
3668         */
3669         if (!(SINGLE_MEDIA_DIRECT(params))) {
3670                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
3671                            " init_preceding = %d\n", ext_phy_link_up,
3672                            vars->phy_link_up,
3673                            params->phy[EXT_PHY1].flags &
3674                            FLAGS_INIT_XGXS_FIRST);
3675                 if (!(params->phy[EXT_PHY1].flags &
3676                       FLAGS_INIT_XGXS_FIRST)
3677                     && ext_phy_link_up && !vars->phy_link_up) {
3678                         vars->line_speed = ext_phy_line_speed;
3679                         if (vars->line_speed < SPEED_1000)
3680                                 vars->phy_flags |= PHY_SGMII_FLAG;
3681                         else
3682                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
3683                         bnx2x_init_internal_phy(&params->phy[INT_PHY],
3684                                                 params,
3685                                                 vars);
3686                 }
3687         }
3688         /**
3689          *  Link is up only if both local phy and external phy (in case of
3690          *  non-direct board) are up
3691          */
3692         vars->link_up = (vars->phy_link_up &&
3693                          (ext_phy_link_up ||
3694                           SINGLE_MEDIA_DIRECT(params)));
3695
3696         if (vars->link_up)
3697                 rc = bnx2x_update_link_up(params, vars, link_10g);
3698         else
3699                 rc = bnx2x_update_link_down(params, vars);
3700
3701         return rc;
3702 }
3703
3704
3705 /*****************************************************************************/
3706 /*                          External Phy section                             */
3707 /*****************************************************************************/
3708 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
3709 {
3710         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3711                             MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
3712         msleep(1);
3713         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
3714                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
3715 }
3716
3717 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
3718                                       u32 spirom_ver, u32 ver_addr)
3719 {
3720         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
3721                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
3722
3723         if (ver_addr)
3724                 REG_WR(bp, ver_addr, spirom_ver);
3725 }
3726
3727 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
3728                                       struct bnx2x_phy *phy,
3729                                       u8 port)
3730 {
3731         u16 fw_ver1, fw_ver2;
3732
3733         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3734                       MDIO_PMA_REG_ROM_VER1, &fw_ver1);
3735         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
3736                       MDIO_PMA_REG_ROM_VER2, &fw_ver2);
3737         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
3738                                   phy->ver_addr);
3739 }
3740
3741 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3742                                     struct bnx2x_phy *phy,
3743                                     struct link_vars *vars)
3744 {
3745         u16 val;
3746         struct bnx2x *bp = params->bp;
3747         /* read modify write pause advertizing */
3748         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3749
3750         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3751
3752         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3753         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3754         if ((vars->ieee_fc &
3755             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3756             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3757                 val |=  MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3758         }
3759         if ((vars->ieee_fc &
3760             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3761             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3762                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3763         }
3764         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3765         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3766 }
3767
3768 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3769                                    struct link_params *params,
3770                                    struct link_vars *vars)
3771 {
3772         struct bnx2x *bp = params->bp;
3773         u16 ld_pause;           /* local */
3774         u16 lp_pause;           /* link partner */
3775         u16 pause_result;
3776         u8 ret = 0;
3777         /* read twice */
3778
3779         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3780
3781         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3782                 vars->flow_ctrl = phy->req_flow_ctrl;
3783         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3784                 vars->flow_ctrl = params->req_fc_auto_adv;
3785         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3786                 ret = 1;
3787                 bnx2x_cl45_read(bp, phy,
3788                               MDIO_AN_DEVAD,
3789                               MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3790                 bnx2x_cl45_read(bp, phy,
3791                               MDIO_AN_DEVAD,
3792                               MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3793                 pause_result = (ld_pause &
3794                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3795                 pause_result |= (lp_pause &
3796                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3797                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3798                    pause_result);
3799                 bnx2x_pause_resolve(vars, pause_result);
3800         }
3801         return ret;
3802 }
3803
3804 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
3805                                        struct bnx2x_phy *phy,
3806                                        struct link_vars *vars)
3807 {
3808         u16 val;
3809         bnx2x_cl45_read(bp, phy,
3810                         MDIO_AN_DEVAD,
3811                         MDIO_AN_REG_STATUS, &val);
3812         bnx2x_cl45_read(bp, phy,
3813                         MDIO_AN_DEVAD,
3814                         MDIO_AN_REG_STATUS, &val);
3815         if (val & (1<<5))
3816                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
3817         if ((val & (1<<0)) == 0)
3818                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
3819 }
3820
3821 /******************************************************************/
3822 /*              common BCM8073/BCM8727 PHY SECTION                */
3823 /******************************************************************/
3824 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
3825                                   struct link_params *params,
3826                                   struct link_vars *vars)
3827 {
3828         struct bnx2x *bp = params->bp;
3829         if (phy->req_line_speed == SPEED_10 ||
3830             phy->req_line_speed == SPEED_100) {
3831                 vars->flow_ctrl = phy->req_flow_ctrl;
3832                 return;
3833         }
3834
3835         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
3836             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
3837                 u16 pause_result;
3838                 u16 ld_pause;           /* local */
3839                 u16 lp_pause;           /* link partner */
3840                 bnx2x_cl45_read(bp, phy,
3841                                 MDIO_AN_DEVAD,
3842                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3843
3844                 bnx2x_cl45_read(bp, phy,
3845                                 MDIO_AN_DEVAD,
3846                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3847                 pause_result = (ld_pause &
3848                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
3849                 pause_result |= (lp_pause &
3850                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
3851
3852                 bnx2x_pause_resolve(vars, pause_result);
3853                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
3854                            pause_result);
3855         }
3856 }
3857
3858 static void bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
3859                                               struct bnx2x_phy *phy,
3860                                               u8 port)
3861 {
3862         /* Boot port from external ROM  */
3863         /* EDC grst */
3864         bnx2x_cl45_write(bp, phy,
3865                        MDIO_PMA_DEVAD,
3866                        MDIO_PMA_REG_GEN_CTRL,
3867                        0x0001);
3868
3869         /* ucode reboot and rst */
3870         bnx2x_cl45_write(bp, phy,
3871                        MDIO_PMA_DEVAD,
3872                        MDIO_PMA_REG_GEN_CTRL,
3873                        0x008c);
3874
3875         bnx2x_cl45_write(bp, phy,
3876                        MDIO_PMA_DEVAD,
3877                        MDIO_PMA_REG_MISC_CTRL1, 0x0001);
3878
3879         /* Reset internal microprocessor */
3880         bnx2x_cl45_write(bp, phy,
3881                        MDIO_PMA_DEVAD,
3882                        MDIO_PMA_REG_GEN_CTRL,
3883                        MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
3884
3885         /* Release srst bit */
3886         bnx2x_cl45_write(bp, phy,
3887                        MDIO_PMA_DEVAD,
3888                        MDIO_PMA_REG_GEN_CTRL,
3889                        MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
3890
3891         /* wait for 120ms for code download via SPI port */
3892         msleep(120);
3893
3894         /* Clear ser_boot_ctl bit */
3895         bnx2x_cl45_write(bp, phy,
3896                        MDIO_PMA_DEVAD,
3897                        MDIO_PMA_REG_MISC_CTRL1, 0x0000);
3898         bnx2x_save_bcm_spirom_ver(bp, phy, port);
3899 }
3900
3901 static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
3902                                                struct bnx2x_phy *phy)
3903 {
3904         u16 val;
3905         bnx2x_cl45_read(bp, phy,
3906                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);
3907
3908         if (val == 0) {
3909                 /* Mustn't set low power mode in 8073 A0 */
3910                 return;
3911         }
3912
3913         /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
3914         bnx2x_cl45_read(bp, phy,
3915                         MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3916         val &= ~(1<<13);
3917         bnx2x_cl45_write(bp, phy,
3918                        MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3919
3920         /* PLL controls */
3921         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
3922         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
3923         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
3924         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
3925         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);
3926
3927         /* Tx Controls */
3928         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
3929         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
3930         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);
3931
3932         /* Rx Controls */
3933         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
3934         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
3935         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);
3936
3937         /* Enable PLL sequencer  (use read-modify-write to set bit 13) */
3938         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
3939         val |= (1<<13);
3940         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
3941 }
3942
3943 /******************************************************************/
3944 /*                      BCM8073 PHY SECTION                       */
3945 /******************************************************************/
3946 static u8 bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
3947 {
3948         /* This is only required for 8073A1, version 102 only */
3949         u16 val;
3950
3951         /* Read 8073 HW revision*/
3952         bnx2x_cl45_read(bp, phy,
3953                       MDIO_PMA_DEVAD,
3954                       MDIO_PMA_REG_8073_CHIP_REV, &val);
3955
3956         if (val != 1) {
3957                 /* No need to workaround in 8073 A1 */
3958                 return 0;
3959         }
3960
3961         bnx2x_cl45_read(bp, phy,
3962                       MDIO_PMA_DEVAD,
3963                       MDIO_PMA_REG_ROM_VER2, &val);
3964
3965         /* SNR should be applied only for version 0x102 */
3966         if (val != 0x102)
3967                 return 0;
3968
3969         return 1;
3970 }
3971
3972 static u8 bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
3973 {
3974         u16 val, cnt, cnt1 ;
3975
3976         bnx2x_cl45_read(bp, phy,
3977                       MDIO_PMA_DEVAD,
3978                       MDIO_PMA_REG_8073_CHIP_REV, &val);
3979
3980         if (val > 0) {
3981                 /* No need to workaround in 8073 A1 */
3982                 return 0;
3983         }
3984         /* XAUI workaround in 8073 A0: */
3985
3986         /* After loading the boot ROM and restarting Autoneg,
3987         poll Dev1, Reg $C820: */
3988
3989         for (cnt = 0; cnt < 1000; cnt++) {
3990                 bnx2x_cl45_read(bp, phy,
3991                               MDIO_PMA_DEVAD,
3992                               MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
3993                               &val);
3994                   /* If bit [14] = 0 or bit [13] = 0, continue on with
3995                    system initialization (XAUI work-around not required,
3996                     as these bits indicate 2.5G or 1G link up). */
3997                 if (!(val & (1<<14)) || !(val & (1<<13))) {
3998                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
3999                         return 0;
4000                 } else if (!(val & (1<<15))) {
4001                         DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
4002                          /* If bit 15 is 0, then poll Dev1, Reg $C841 until
4003                           it's MSB (bit 15) goes to 1 (indicating that the
4004                           XAUI workaround has completed),
4005                           then continue on with system initialization.*/
4006                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
4007                                 bnx2x_cl45_read(bp, phy,
4008                                         MDIO_PMA_DEVAD,
4009                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
4010                                 if (val & (1<<15)) {
4011                                         DP(NETIF_MSG_LINK,
4012                                           "XAUI workaround has completed\n");
4013                                         return 0;
4014                                  }
4015                                  msleep(3);
4016                         }
4017                         break;
4018                 }
4019                 msleep(3);
4020         }
4021         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
4022         return -EINVAL;
4023 }
4024
4025 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
4026 {
4027         /* Force KR or KX */
4028         bnx2x_cl45_write(bp, phy,
4029                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
4030         bnx2x_cl45_write(bp, phy,
4031                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
4032         bnx2x_cl45_write(bp, phy,
4033                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
4034         bnx2x_cl45_write(bp, phy,
4035                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
4036 }
4037
4038 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
4039                                       struct bnx2x_phy *phy,
4040                                       struct link_vars *vars)
4041 {
4042         u16 cl37_val;
4043         struct bnx2x *bp = params->bp;
4044         bnx2x_cl45_read(bp, phy,
4045                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
4046
4047         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4048         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4049         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4050         if ((vars->ieee_fc &
4051             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
4052             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
4053                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
4054         }
4055         if ((vars->ieee_fc &
4056             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4057             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4058                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4059         }
4060         if ((vars->ieee_fc &
4061             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4062             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4063                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4064         }
4065         DP(NETIF_MSG_LINK,
4066                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
4067
4068         bnx2x_cl45_write(bp, phy,
4069                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
4070         msleep(500);
4071 }
4072
4073 static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,
4074                                  struct link_params *params,
4075                                  struct link_vars *vars)
4076 {
4077         struct bnx2x *bp = params->bp;
4078         u16 val = 0, tmp1;
4079         u8 gpio_port;
4080         DP(NETIF_MSG_LINK, "Init 8073\n");
4081
4082         if (CHIP_IS_E2(bp))
4083                 gpio_port = BP_PATH(bp);
4084         else
4085                 gpio_port = params->port;
4086         /* Restore normal power mode*/
4087         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4088                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4089
4090         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4091                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
4092
4093         /* enable LASI */
4094         bnx2x_cl45_write(bp, phy,
4095                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL, (1<<2));
4096         bnx2x_cl45_write(bp, phy,
4097                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,  0x0004);
4098
4099         bnx2x_8073_set_pause_cl37(params, phy, vars);
4100
4101         bnx2x_8073_set_xaui_low_power_mode(bp, phy);
4102
4103         bnx2x_cl45_read(bp, phy,
4104                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
4105
4106         bnx2x_cl45_read(bp, phy,
4107                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
4108
4109         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
4110
4111         /* Enable CL37 BAM */
4112         if (REG_RD(bp, params->shmem_base +
4113                          offsetof(struct shmem_region, dev_info.
4114                                   port_hw_config[params->port].default_cfg)) &
4115             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4116
4117                 bnx2x_cl45_read(bp, phy,
4118                                 MDIO_AN_DEVAD,
4119                                 MDIO_AN_REG_8073_BAM, &val);
4120                 bnx2x_cl45_write(bp, phy,
4121                                  MDIO_AN_DEVAD,
4122                                  MDIO_AN_REG_8073_BAM, val | 1);
4123                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
4124         }
4125         if (params->loopback_mode == LOOPBACK_EXT) {
4126                 bnx2x_807x_force_10G(bp, phy);
4127                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
4128                 return 0;
4129         } else {
4130                 bnx2x_cl45_write(bp, phy,
4131                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
4132         }
4133         if (phy->req_line_speed != SPEED_AUTO_NEG) {
4134                 if (phy->req_line_speed == SPEED_10000) {
4135                         val = (1<<7);
4136                 } else if (phy->req_line_speed ==  SPEED_2500) {
4137                         val = (1<<5);
4138                         /* Note that 2.5G works only
4139                         when used with 1G advertisment */
4140                 } else
4141                         val = (1<<5);
4142         } else {
4143                 val = 0;
4144                 if (phy->speed_cap_mask &
4145                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4146                         val |= (1<<7);
4147
4148                 /* Note that 2.5G works only when
4149                 used with 1G advertisment */
4150                 if (phy->speed_cap_mask &
4151                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
4152                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
4153                         val |= (1<<5);
4154                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
4155         }
4156
4157         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
4158         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
4159
4160         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
4161              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
4162             (phy->req_line_speed == SPEED_2500)) {
4163                 u16 phy_ver;
4164                 /* Allow 2.5G for A1 and above */
4165                 bnx2x_cl45_read(bp, phy,
4166                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
4167                                 &phy_ver);
4168                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
4169                 if (phy_ver > 0)
4170                         tmp1 |= 1;
4171                 else
4172                         tmp1 &= 0xfffe;
4173         } else {
4174                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
4175                 tmp1 &= 0xfffe;
4176         }
4177
4178         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
4179         /* Add support for CL37 (passive mode) II */
4180
4181         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
4182         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
4183                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
4184                                   0x20 : 0x40)));
4185
4186         /* Add support for CL37 (passive mode) III */
4187         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
4188
4189         /* The SNR will improve about 2db by changing
4190         BW and FEE main tap. Rest commands are executed
4191         after link is up*/
4192         if (bnx2x_8073_is_snr_needed(bp, phy))
4193                 bnx2x_cl45_write(bp, phy,
4194                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
4195                                  0xFB0C);
4196
4197         /* Enable FEC (Forware Error Correction) Request in the AN */
4198         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
4199         tmp1 |= (1<<15);
4200         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
4201
4202         bnx2x_ext_phy_set_pause(params, phy, vars);
4203
4204         /* Restart autoneg */
4205         msleep(500);
4206         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
4207         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
4208                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
4209         return 0;
4210 }
4211
4212 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
4213                                  struct link_params *params,
4214                                  struct link_vars *vars)
4215 {
4216         struct bnx2x *bp = params->bp;
4217         u8 link_up = 0;
4218         u16 val1, val2;
4219         u16 link_status = 0;
4220         u16 an1000_status = 0;
4221
4222         bnx2x_cl45_read(bp, phy,
4223                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
4224
4225         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
4226
4227         /* clear the interrupt LASI status register */
4228         bnx2x_cl45_read(bp, phy,
4229                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4230         bnx2x_cl45_read(bp, phy,
4231                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
4232         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
4233         /* Clear MSG-OUT */
4234         bnx2x_cl45_read(bp, phy,
4235                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
4236
4237         /* Check the LASI */
4238         bnx2x_cl45_read(bp, phy,
4239                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
4240
4241         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
4242
4243         /* Check the link status */
4244         bnx2x_cl45_read(bp, phy,
4245                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
4246         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
4247
4248         bnx2x_cl45_read(bp, phy,
4249                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4250         bnx2x_cl45_read(bp, phy,
4251                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4252         link_up = ((val1 & 4) == 4);
4253         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
4254
4255         if (link_up &&
4256              ((phy->req_line_speed != SPEED_10000))) {
4257                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
4258                         return 0;
4259         }
4260         bnx2x_cl45_read(bp, phy,
4261                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4262         bnx2x_cl45_read(bp, phy,
4263                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
4264
4265         /* Check the link status on 1.1.2 */
4266         bnx2x_cl45_read(bp, phy,
4267                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
4268         bnx2x_cl45_read(bp, phy,
4269                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
4270         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
4271                    "an_link_status=0x%x\n", val2, val1, an1000_status);
4272
4273         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
4274         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
4275                 /* The SNR will improve about 2dbby
4276                 changing the BW and FEE main tap.*/
4277                 /* The 1st write to change FFE main
4278                 tap is set before restart AN */
4279                 /* Change PLL Bandwidth in EDC
4280                 register */
4281                 bnx2x_cl45_write(bp, phy,
4282                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
4283                                  0x26BC);
4284
4285                 /* Change CDR Bandwidth in EDC register */
4286                 bnx2x_cl45_write(bp, phy,
4287                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
4288                                  0x0333);
4289         }
4290         bnx2x_cl45_read(bp, phy,
4291                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
4292                         &link_status);
4293
4294         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
4295         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
4296                 link_up = 1;
4297                 vars->line_speed = SPEED_10000;
4298                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
4299                            params->port);
4300         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
4301                 link_up = 1;
4302                 vars->line_speed = SPEED_2500;
4303                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
4304                            params->port);
4305         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
4306                 link_up = 1;
4307                 vars->line_speed = SPEED_1000;
4308                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
4309                            params->port);
4310         } else {
4311                 link_up = 0;
4312                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
4313                            params->port);
4314         }
4315
4316         if (link_up) {
4317                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
4318                 bnx2x_8073_resolve_fc(phy, params, vars);
4319         }
4320         return link_up;
4321 }
4322
4323 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
4324                                   struct link_params *params)
4325 {
4326         struct bnx2x *bp = params->bp;
4327         u8 gpio_port;
4328         if (CHIP_IS_E2(bp))
4329                 gpio_port = BP_PATH(bp);
4330         else
4331                 gpio_port = params->port;
4332         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
4333            gpio_port);
4334         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4335                             MISC_REGISTERS_GPIO_OUTPUT_LOW,
4336                             gpio_port);
4337 }
4338
4339 /******************************************************************/
4340 /*                      BCM8705 PHY SECTION                       */
4341 /******************************************************************/
4342 static u8 bnx2x_8705_config_init(struct bnx2x_phy *phy,
4343                                  struct link_params *params,
4344                                  struct link_vars *vars)
4345 {
4346         struct bnx2x *bp = params->bp;
4347         DP(NETIF_MSG_LINK, "init 8705\n");
4348         /* Restore normal power mode*/
4349         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4350                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
4351         /* HW reset */
4352         bnx2x_ext_phy_hw_reset(bp, params->port);
4353         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
4354         bnx2x_wait_reset_complete(bp, phy);
4355
4356         bnx2x_cl45_write(bp, phy,
4357                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
4358         bnx2x_cl45_write(bp, phy,
4359                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
4360         bnx2x_cl45_write(bp, phy,
4361                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
4362         bnx2x_cl45_write(bp, phy,
4363                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
4364         /* BCM8705 doesn't have microcode, hence the 0 */
4365         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
4366         return 0;
4367 }
4368
4369 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
4370                                  struct link_params *params,
4371                                  struct link_vars *vars)
4372 {
4373         u8 link_up = 0;
4374         u16 val1, rx_sd;
4375         struct bnx2x *bp = params->bp;
4376         DP(NETIF_MSG_LINK, "read status 8705\n");
4377         bnx2x_cl45_read(bp, phy,
4378                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4379         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4380
4381         bnx2x_cl45_read(bp, phy,
4382                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
4383         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
4384
4385         bnx2x_cl45_read(bp, phy,
4386                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
4387
4388         bnx2x_cl45_read(bp, phy,
4389                       MDIO_PMA_DEVAD, 0xc809, &val1);
4390         bnx2x_cl45_read(bp, phy,
4391                       MDIO_PMA_DEVAD, 0xc809, &val1);
4392
4393         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
4394         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
4395         if (link_up) {
4396                 vars->line_speed = SPEED_10000;
4397                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
4398         }
4399         return link_up;
4400 }
4401
4402 /******************************************************************/
4403 /*                      SFP+ module Section                       */
4404 /******************************************************************/
4405 static void bnx2x_sfp_set_transmitter(struct bnx2x *bp,
4406                                       struct bnx2x_phy *phy,
4407                                       u8 port,
4408                                       u8 tx_en)
4409 {
4410         u16 val;
4411
4412         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x\n",
4413                  tx_en, port);
4414         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
4415         bnx2x_cl45_read(bp, phy,
4416                       MDIO_PMA_DEVAD,
4417                       MDIO_PMA_REG_PHY_IDENTIFIER,
4418                       &val);
4419
4420         if (tx_en)
4421                 val &= ~(1<<15);
4422         else
4423                 val |= (1<<15);
4424
4425         bnx2x_cl45_write(bp, phy,
4426                        MDIO_PMA_DEVAD,
4427                        MDIO_PMA_REG_PHY_IDENTIFIER,
4428                        val);
4429 }
4430
4431 static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4432                                             struct link_params *params,
4433                                           u16 addr, u8 byte_cnt, u8 *o_buf)
4434 {
4435         struct bnx2x *bp = params->bp;
4436         u16 val = 0;
4437         u16 i;
4438         if (byte_cnt > 16) {
4439                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4440                             " is limited to 0xf\n");
4441                 return -EINVAL;
4442         }
4443         /* Set the read command byte count */
4444         bnx2x_cl45_write(bp, phy,
4445                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4446                        (byte_cnt | 0xa000));
4447
4448         /* Set the read command address */
4449         bnx2x_cl45_write(bp, phy,
4450                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4451                        addr);
4452
4453         /* Activate read command */
4454         bnx2x_cl45_write(bp, phy,
4455                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4456                        0x2c0f);
4457
4458         /* Wait up to 500us for command complete status */
4459         for (i = 0; i < 100; i++) {
4460                 bnx2x_cl45_read(bp, phy,
4461                               MDIO_PMA_DEVAD,
4462                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4463                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4464                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4465                         break;
4466                 udelay(5);
4467         }
4468
4469         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4470                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4471                 DP(NETIF_MSG_LINK,
4472                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4473                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4474                 return -EINVAL;
4475         }
4476
4477         /* Read the buffer */
4478         for (i = 0; i < byte_cnt; i++) {
4479                 bnx2x_cl45_read(bp, phy,
4480                               MDIO_PMA_DEVAD,
4481                               MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
4482                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
4483         }
4484
4485         for (i = 0; i < 100; i++) {
4486                 bnx2x_cl45_read(bp, phy,
4487                               MDIO_PMA_DEVAD,
4488                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4489                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4490                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4491                         return 0;
4492                 msleep(1);
4493         }
4494         return -EINVAL;
4495 }
4496
4497 static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4498                                             struct link_params *params,
4499                                           u16 addr, u8 byte_cnt, u8 *o_buf)
4500 {
4501         struct bnx2x *bp = params->bp;
4502         u16 val, i;
4503
4504         if (byte_cnt > 16) {
4505                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
4506                             " is limited to 0xf\n");
4507                 return -EINVAL;
4508         }
4509
4510         /* Need to read from 1.8000 to clear it */
4511         bnx2x_cl45_read(bp, phy,
4512                       MDIO_PMA_DEVAD,
4513                       MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4514                       &val);
4515
4516         /* Set the read command byte count */
4517         bnx2x_cl45_write(bp, phy,
4518                        MDIO_PMA_DEVAD,
4519                        MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
4520                        ((byte_cnt < 2) ? 2 : byte_cnt));
4521
4522         /* Set the read command address */
4523         bnx2x_cl45_write(bp, phy,
4524                        MDIO_PMA_DEVAD,
4525                        MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
4526                        addr);
4527         /* Set the destination address */
4528         bnx2x_cl45_write(bp, phy,
4529                        MDIO_PMA_DEVAD,
4530                        0x8004,
4531                        MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
4532
4533         /* Activate read command */
4534         bnx2x_cl45_write(bp, phy,
4535                        MDIO_PMA_DEVAD,
4536                        MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
4537                        0x8002);
4538         /* Wait appropriate time for two-wire command to finish before
4539         polling the status register */
4540         msleep(1);
4541
4542         /* Wait up to 500us for command complete status */
4543         for (i = 0; i < 100; i++) {
4544                 bnx2x_cl45_read(bp, phy,
4545                               MDIO_PMA_DEVAD,
4546                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4547                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4548                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
4549                         break;
4550                 udelay(5);
4551         }
4552
4553         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
4554                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
4555                 DP(NETIF_MSG_LINK,
4556                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
4557                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
4558                 return -EINVAL;
4559         }
4560
4561         /* Read the buffer */
4562         for (i = 0; i < byte_cnt; i++) {
4563                 bnx2x_cl45_read(bp, phy,
4564                               MDIO_PMA_DEVAD,
4565                               MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
4566                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
4567         }
4568
4569         for (i = 0; i < 100; i++) {
4570                 bnx2x_cl45_read(bp, phy,
4571                               MDIO_PMA_DEVAD,
4572                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
4573                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
4574                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
4575                         return 0;
4576                 msleep(1);
4577         }
4578
4579         return -EINVAL;
4580 }
4581
4582 static u8 bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
4583                                        struct link_params *params, u16 addr,
4584                                        u8 byte_cnt, u8 *o_buf)
4585 {
4586         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4587                 return bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
4588                                                        byte_cnt, o_buf);
4589         else if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4590                 return bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
4591                                                        byte_cnt, o_buf);
4592         return -EINVAL;
4593 }
4594
4595 static u8 bnx2x_get_edc_mode(struct bnx2x_phy *phy,
4596                              struct link_params *params,
4597                                   u16 *edc_mode)
4598 {
4599         struct bnx2x *bp = params->bp;
4600         u8 val, check_limiting_mode = 0;
4601         *edc_mode = EDC_MODE_LIMITING;
4602
4603         /* First check for copper cable */
4604         if (bnx2x_read_sfp_module_eeprom(phy,
4605                                          params,
4606                                          SFP_EEPROM_CON_TYPE_ADDR,
4607                                          1,
4608                                          &val) != 0) {
4609                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
4610                 return -EINVAL;
4611         }
4612
4613         switch (val) {
4614         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
4615         {
4616                 u8 copper_module_type;
4617
4618                 /* Check if its active cable( includes SFP+ module)
4619                 of passive cable*/
4620                 if (bnx2x_read_sfp_module_eeprom(phy,
4621                                                params,
4622                                                SFP_EEPROM_FC_TX_TECH_ADDR,
4623                                                1,
4624                                                &copper_module_type) !=
4625                     0) {
4626                         DP(NETIF_MSG_LINK,
4627                                 "Failed to read copper-cable-type"
4628                                 " from SFP+ EEPROM\n");
4629                         return -EINVAL;
4630                 }
4631
4632                 if (copper_module_type &
4633                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
4634                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
4635                         check_limiting_mode = 1;
4636                 } else if (copper_module_type &
4637                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
4638                                 DP(NETIF_MSG_LINK, "Passive Copper"
4639                                             " cable detected\n");
4640                                 *edc_mode =
4641                                       EDC_MODE_PASSIVE_DAC;
4642                 } else {
4643                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
4644                                      "type 0x%x !!!\n", copper_module_type);
4645                         return -EINVAL;
4646                 }
4647                 break;
4648         }
4649         case SFP_EEPROM_CON_TYPE_VAL_LC:
4650                 DP(NETIF_MSG_LINK, "Optic module detected\n");
4651                 check_limiting_mode = 1;
4652                 break;
4653         default:
4654                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
4655                          val);
4656                 return -EINVAL;
4657         }
4658
4659         if (check_limiting_mode) {
4660                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
4661                 if (bnx2x_read_sfp_module_eeprom(phy,
4662                                                  params,
4663                                                  SFP_EEPROM_OPTIONS_ADDR,
4664                                                  SFP_EEPROM_OPTIONS_SIZE,
4665                                                  options) != 0) {
4666                         DP(NETIF_MSG_LINK, "Failed to read Option"
4667                                 " field from module EEPROM\n");
4668                         return -EINVAL;
4669                 }
4670                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
4671                         *edc_mode = EDC_MODE_LINEAR;
4672                 else
4673                         *edc_mode = EDC_MODE_LIMITING;
4674         }
4675         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
4676         return 0;
4677 }
4678 /* This function read the relevant field from the module ( SFP+ ),
4679         and verify it is compliant with this board */
4680 static u8 bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
4681                                   struct link_params *params)
4682 {
4683         struct bnx2x *bp = params->bp;
4684         u32 val, cmd;
4685         u32 fw_resp, fw_cmd_param;
4686         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
4687         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
4688         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
4689         val = REG_RD(bp, params->shmem_base +
4690                          offsetof(struct shmem_region, dev_info.
4691                                   port_feature_config[params->port].config));
4692         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4693             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
4694                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
4695                 return 0;
4696         }
4697
4698         if (params->feature_config_flags &
4699             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
4700                 /* Use specific phy request */
4701                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
4702         } else if (params->feature_config_flags &
4703                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
4704                 /* Use first phy request only in case of non-dual media*/
4705                 if (DUAL_MEDIA(params)) {
4706                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4707                            "verification\n");
4708                         return -EINVAL;
4709                 }
4710                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
4711         } else {
4712                 /* No support in OPT MDL detection */
4713                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
4714                           "verification\n");
4715                 return -EINVAL;
4716         }
4717
4718         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
4719         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
4720         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
4721                 DP(NETIF_MSG_LINK, "Approved module\n");
4722                 return 0;
4723         }
4724
4725         /* format the warning message */
4726         if (bnx2x_read_sfp_module_eeprom(phy,
4727                                          params,
4728                                        SFP_EEPROM_VENDOR_NAME_ADDR,
4729                                        SFP_EEPROM_VENDOR_NAME_SIZE,
4730                                        (u8 *)vendor_name))
4731                 vendor_name[0] = '\0';
4732         else
4733                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
4734         if (bnx2x_read_sfp_module_eeprom(phy,
4735                                          params,
4736                                        SFP_EEPROM_PART_NO_ADDR,
4737                                        SFP_EEPROM_PART_NO_SIZE,
4738                                        (u8 *)vendor_pn))
4739                 vendor_pn[0] = '\0';
4740         else
4741                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
4742
4743         netdev_info(bp->dev, "Warning: Unqualified SFP+ module detected,"
4744                              " Port %d from %s part number %s\n",
4745                     params->port, vendor_name, vendor_pn);
4746         phy->flags |= FLAGS_SFP_NOT_APPROVED;
4747         return -EINVAL;
4748 }
4749
4750 static u8 bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
4751                                                 struct link_params *params)
4752
4753 {
4754         u8 val;
4755         struct bnx2x *bp = params->bp;
4756         u16 timeout;
4757         /* Initialization time after hot-plug may take up to 300ms for some
4758         phys type ( e.g. JDSU ) */
4759         for (timeout = 0; timeout < 60; timeout++) {
4760                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
4761                     == 0) {
4762                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
4763                                      "took %d ms\n", timeout * 5);
4764                         return 0;
4765                 }
4766                 msleep(5);
4767         }
4768         return -EINVAL;
4769 }
4770
4771 static void bnx2x_8727_power_module(struct bnx2x *bp,
4772                                     struct bnx2x_phy *phy,
4773                                     u8 is_power_up) {
4774         /* Make sure GPIOs are not using for LED mode */
4775         u16 val;
4776         /*
4777          * In the GPIO register, bit 4 is use to detemine if the GPIOs are
4778          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
4779          * output
4780          * Bits 0-1 determine the gpios value for OUTPUT in case bit 4 val is 0
4781          * Bits 8-9 determine the gpios value for INPUT in case bit 4 val is 1
4782          * where the 1st bit is the over-current(only input), and 2nd bit is
4783          * for power( only output )
4784         */
4785
4786         /*
4787          * In case of NOC feature is disabled and power is up, set GPIO control
4788          *  as input to enable listening of over-current indication
4789          */
4790         if (phy->flags & FLAGS_NOC)
4791                 return;
4792         if (!(phy->flags &
4793               FLAGS_NOC) && is_power_up)
4794                 val = (1<<4);
4795         else
4796                 /*
4797                  * Set GPIO control to OUTPUT, and set the power bit
4798                  * to according to the is_power_up
4799                  */
4800                 val = ((!(is_power_up)) << 1);
4801
4802         bnx2x_cl45_write(bp, phy,
4803                          MDIO_PMA_DEVAD,
4804                          MDIO_PMA_REG_8727_GPIO_CTRL,
4805                          val);
4806 }
4807
4808 static u8 bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
4809                                        struct bnx2x_phy *phy,
4810                                        u16 edc_mode)
4811 {
4812         u16 cur_limiting_mode;
4813
4814         bnx2x_cl45_read(bp, phy,
4815                       MDIO_PMA_DEVAD,
4816                       MDIO_PMA_REG_ROM_VER2,
4817                       &cur_limiting_mode);
4818         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
4819                  cur_limiting_mode);
4820
4821         if (edc_mode == EDC_MODE_LIMITING) {
4822                 DP(NETIF_MSG_LINK,
4823                          "Setting LIMITING MODE\n");
4824                 bnx2x_cl45_write(bp, phy,
4825                                  MDIO_PMA_DEVAD,
4826                                  MDIO_PMA_REG_ROM_VER2,
4827                                  EDC_MODE_LIMITING);
4828         } else { /* LRM mode ( default )*/
4829
4830                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
4831
4832                 /* Changing to LRM mode takes quite few seconds.
4833                 So do it only if current mode is limiting
4834                 ( default is LRM )*/
4835                 if (cur_limiting_mode != EDC_MODE_LIMITING)
4836                         return 0;
4837
4838                 bnx2x_cl45_write(bp, phy,
4839                                MDIO_PMA_DEVAD,
4840                                MDIO_PMA_REG_LRM_MODE,
4841                                0);
4842                 bnx2x_cl45_write(bp, phy,
4843                                MDIO_PMA_DEVAD,
4844                                MDIO_PMA_REG_ROM_VER2,
4845                                0x128);
4846                 bnx2x_cl45_write(bp, phy,
4847                                MDIO_PMA_DEVAD,
4848                                MDIO_PMA_REG_MISC_CTRL0,
4849                                0x4008);
4850                 bnx2x_cl45_write(bp, phy,
4851                                MDIO_PMA_DEVAD,
4852                                MDIO_PMA_REG_LRM_MODE,
4853                                0xaaaa);
4854         }
4855         return 0;
4856 }
4857
4858 static u8 bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
4859                                        struct bnx2x_phy *phy,
4860                                         u16 edc_mode)
4861 {
4862         u16 phy_identifier;
4863         u16 rom_ver2_val;
4864         bnx2x_cl45_read(bp, phy,
4865                        MDIO_PMA_DEVAD,
4866                        MDIO_PMA_REG_PHY_IDENTIFIER,
4867                        &phy_identifier);
4868
4869         bnx2x_cl45_write(bp, phy,
4870                        MDIO_PMA_DEVAD,
4871                        MDIO_PMA_REG_PHY_IDENTIFIER,
4872                        (phy_identifier & ~(1<<9)));
4873
4874         bnx2x_cl45_read(bp, phy,
4875                       MDIO_PMA_DEVAD,
4876                       MDIO_PMA_REG_ROM_VER2,
4877                       &rom_ver2_val);
4878         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
4879         bnx2x_cl45_write(bp, phy,
4880                        MDIO_PMA_DEVAD,
4881                        MDIO_PMA_REG_ROM_VER2,
4882                        (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
4883
4884         bnx2x_cl45_write(bp, phy,
4885                        MDIO_PMA_DEVAD,
4886                        MDIO_PMA_REG_PHY_IDENTIFIER,
4887                        (phy_identifier | (1<<9)));
4888
4889         return 0;
4890 }
4891
4892 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
4893                                      struct link_params *params,
4894                                      u32 action)
4895 {
4896         struct bnx2x *bp = params->bp;
4897
4898         switch (action) {
4899         case DISABLE_TX:
4900                 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4901                 break;
4902         case ENABLE_TX:
4903                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
4904                         bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4905                 break;
4906         default:
4907                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
4908                    action);
4909                 return;
4910         }
4911 }
4912
4913 static u8 bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
4914                                      struct link_params *params)
4915 {
4916         struct bnx2x *bp = params->bp;
4917         u16 edc_mode;
4918         u8 rc = 0;
4919
4920         u32 val = REG_RD(bp, params->shmem_base +
4921                              offsetof(struct shmem_region, dev_info.
4922                                      port_feature_config[params->port].config));
4923
4924         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
4925                  params->port);
4926
4927         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
4928                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
4929                 return -EINVAL;
4930         } else if (bnx2x_verify_sfp_module(phy, params) !=
4931                    0) {
4932                 /* check SFP+ module compatibility */
4933                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
4934                 rc = -EINVAL;
4935                 /* Turn on fault module-detected led */
4936                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4937                                   MISC_REGISTERS_GPIO_HIGH,
4938                                   params->port);
4939                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) &&
4940                     ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
4941                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN)) {
4942                         /* Shutdown SFP+ module */
4943                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
4944                         bnx2x_8727_power_module(bp, phy, 0);
4945                         return rc;
4946                 }
4947         } else {
4948                 /* Turn off fault module-detected led */
4949                 DP(NETIF_MSG_LINK, "Turn off fault module-detected led\n");
4950                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4951                                           MISC_REGISTERS_GPIO_LOW,
4952                                           params->port);
4953         }
4954
4955         /* power up the SFP module */
4956         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727)
4957                 bnx2x_8727_power_module(bp, phy, 1);
4958
4959         /* Check and set limiting mode / LRM mode on 8726.
4960         On 8727 it is done automatically */
4961         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726)
4962                 bnx2x_8726_set_limiting_mode(bp, phy, edc_mode);
4963         else
4964                 bnx2x_8727_set_limiting_mode(bp, phy, edc_mode);
4965         /*
4966          * Enable transmit for this module if the module is approved, or
4967          * if unapproved modules should also enable the Tx laser
4968          */
4969         if (rc == 0 ||
4970             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
4971             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
4972                 bnx2x_sfp_set_transmitter(bp, phy, params->port, 1);
4973         else
4974                 bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
4975
4976         return rc;
4977 }
4978
4979 void bnx2x_handle_module_detect_int(struct link_params *params)
4980 {
4981         struct bnx2x *bp = params->bp;
4982         struct bnx2x_phy *phy = &params->phy[EXT_PHY1];
4983         u32 gpio_val;
4984         u8 port = params->port;
4985
4986         /* Set valid module led off */
4987         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4988                           MISC_REGISTERS_GPIO_HIGH,
4989                           params->port);
4990
4991         /* Get current gpio val refelecting module plugged in / out*/
4992         gpio_val = bnx2x_get_gpio(bp, MISC_REGISTERS_GPIO_3, port);
4993
4994         /* Call the handling function in case module is detected */
4995         if (gpio_val == 0) {
4996
4997                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
4998                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
4999                                    port);
5000
5001                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5002                         bnx2x_sfp_module_detection(phy, params);
5003                 else
5004                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5005         } else {
5006                 u32 val = REG_RD(bp, params->shmem_base +
5007                                      offsetof(struct shmem_region, dev_info.
5008                                               port_feature_config[params->port].
5009                                               config));
5010
5011                 bnx2x_set_gpio_int(bp, MISC_REGISTERS_GPIO_3,
5012                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
5013                                    port);
5014                 /* Module was plugged out. */
5015                 /* Disable transmit for this module */
5016                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5017                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5018                         bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5019         }
5020 }
5021
5022 /******************************************************************/
5023 /*              common BCM8706/BCM8726 PHY SECTION                */
5024 /******************************************************************/
5025 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
5026                                       struct link_params *params,
5027                                       struct link_vars *vars)
5028 {
5029         u8 link_up = 0;
5030         u16 val1, val2, rx_sd, pcs_status;
5031         struct bnx2x *bp = params->bp;
5032         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
5033         /* Clear RX Alarm*/
5034         bnx2x_cl45_read(bp, phy,
5035                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &val2);
5036         /* clear LASI indication*/
5037         bnx2x_cl45_read(bp, phy,
5038                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5039         bnx2x_cl45_read(bp, phy,
5040                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
5041         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
5042
5043         bnx2x_cl45_read(bp, phy,
5044                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
5045         bnx2x_cl45_read(bp, phy,
5046                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
5047         bnx2x_cl45_read(bp, phy,
5048                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5049         bnx2x_cl45_read(bp, phy,
5050                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
5051
5052         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
5053                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
5054         /* link is up if both bit 0 of pmd_rx_sd and
5055          * bit 0 of pcs_status are set, or if the autoneg bit
5056          * 1 is set
5057          */
5058         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
5059         if (link_up) {
5060                 if (val2 & (1<<1))
5061                         vars->line_speed = SPEED_1000;
5062                 else
5063                         vars->line_speed = SPEED_10000;
5064                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5065         }
5066         return link_up;
5067 }
5068
5069 /******************************************************************/
5070 /*                      BCM8706 PHY SECTION                       */
5071 /******************************************************************/
5072 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
5073                                  struct link_params *params,
5074                                  struct link_vars *vars)
5075 {
5076         u16 cnt, val;
5077         struct bnx2x *bp = params->bp;
5078         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5079                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5080         /* HW reset */
5081         bnx2x_ext_phy_hw_reset(bp, params->port);
5082         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
5083         bnx2x_wait_reset_complete(bp, phy);
5084
5085         /* Wait until fw is loaded */
5086         for (cnt = 0; cnt < 100; cnt++) {
5087                 bnx2x_cl45_read(bp, phy,
5088                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
5089                 if (val)
5090                         break;
5091                 msleep(10);
5092         }
5093         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
5094         if ((params->feature_config_flags &
5095              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5096                 u8 i;
5097                 u16 reg;
5098                 for (i = 0; i < 4; i++) {
5099                         reg = MDIO_XS_8706_REG_BANK_RX0 +
5100                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
5101                                    MDIO_XS_8706_REG_BANK_RX0);
5102                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
5103                         /* Clear first 3 bits of the control */
5104                         val &= ~0x7;
5105                         /* Set control bits according to configuration */
5106                         val |= (phy->rx_preemphasis[i] & 0x7);
5107                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
5108                                    " reg 0x%x <-- val 0x%x\n", reg, val);
5109                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
5110                 }
5111         }
5112         /* Force speed */
5113         if (phy->req_line_speed == SPEED_10000) {
5114                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
5115
5116                 bnx2x_cl45_write(bp, phy,
5117                                  MDIO_PMA_DEVAD,
5118                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
5119                 bnx2x_cl45_write(bp, phy,
5120                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5121         } else {
5122                 /* Force 1Gbps using autoneg with 1G advertisment */
5123
5124                 /* Allow CL37 through CL73 */
5125                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
5126                 bnx2x_cl45_write(bp, phy,
5127                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5128
5129                 /* Enable Full-Duplex advertisment on CL37 */
5130                 bnx2x_cl45_write(bp, phy,
5131                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
5132                 /* Enable CL37 AN */
5133                 bnx2x_cl45_write(bp, phy,
5134                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5135                 /* 1G support */
5136                 bnx2x_cl45_write(bp, phy,
5137                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
5138
5139                 /* Enable clause 73 AN */
5140                 bnx2x_cl45_write(bp, phy,
5141                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5142                 bnx2x_cl45_write(bp, phy,
5143                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5144                                  0x0400);
5145                 bnx2x_cl45_write(bp, phy,
5146                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5147                                  0x0004);
5148         }
5149         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5150         return 0;
5151 }
5152
5153 static u8 bnx2x_8706_read_status(struct bnx2x_phy *phy,
5154                                  struct link_params *params,
5155                                  struct link_vars *vars)
5156 {
5157         return bnx2x_8706_8726_read_status(phy, params, vars);
5158 }
5159
5160 /******************************************************************/
5161 /*                      BCM8726 PHY SECTION                       */
5162 /******************************************************************/
5163 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
5164                                        struct link_params *params)
5165 {
5166         struct bnx2x *bp = params->bp;
5167         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
5168         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
5169 }
5170
5171 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
5172                                          struct link_params *params)
5173 {
5174         struct bnx2x *bp = params->bp;
5175         /* Need to wait 100ms after reset */
5176         msleep(100);
5177
5178         /* Micro controller re-boot */
5179         bnx2x_cl45_write(bp, phy,
5180                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
5181
5182         /* Set soft reset */
5183         bnx2x_cl45_write(bp, phy,
5184                        MDIO_PMA_DEVAD,
5185                        MDIO_PMA_REG_GEN_CTRL,
5186                        MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
5187
5188         bnx2x_cl45_write(bp, phy,
5189                        MDIO_PMA_DEVAD,
5190                        MDIO_PMA_REG_MISC_CTRL1, 0x0001);
5191
5192         bnx2x_cl45_write(bp, phy,
5193                        MDIO_PMA_DEVAD,
5194                        MDIO_PMA_REG_GEN_CTRL,
5195                        MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
5196
5197         /* wait for 150ms for microcode load */
5198         msleep(150);
5199
5200         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
5201         bnx2x_cl45_write(bp, phy,
5202                        MDIO_PMA_DEVAD,
5203                        MDIO_PMA_REG_MISC_CTRL1, 0x0000);
5204
5205         msleep(200);
5206         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
5207 }
5208
5209 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
5210                                  struct link_params *params,
5211                                  struct link_vars *vars)
5212 {
5213         struct bnx2x *bp = params->bp;
5214         u16 val1;
5215         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
5216         if (link_up) {
5217                 bnx2x_cl45_read(bp, phy,
5218                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
5219                                 &val1);
5220                 if (val1 & (1<<15)) {
5221                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
5222                         link_up = 0;
5223                         vars->line_speed = 0;
5224                 }
5225         }
5226         return link_up;
5227 }
5228
5229
5230 static u8 bnx2x_8726_config_init(struct bnx2x_phy *phy,
5231                                  struct link_params *params,
5232                                  struct link_vars *vars)
5233 {
5234         struct bnx2x *bp = params->bp;
5235         u32 val;
5236         u32 swap_val, swap_override, aeu_gpio_mask, offset;
5237         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
5238         /* Restore normal power mode*/
5239         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
5240                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5241
5242         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5243                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
5244
5245         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
5246         bnx2x_wait_reset_complete(bp, phy);
5247
5248         bnx2x_8726_external_rom_boot(phy, params);
5249
5250         /* Need to call module detected on initialization since
5251         the module detection triggered by actual module
5252         insertion might occur before driver is loaded, and when
5253         driver is loaded, it reset all registers, including the
5254         transmitter */
5255         bnx2x_sfp_module_detection(phy, params);
5256
5257         if (phy->req_line_speed == SPEED_1000) {
5258                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5259                 bnx2x_cl45_write(bp, phy,
5260                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5261                 bnx2x_cl45_write(bp, phy,
5262                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5263                 bnx2x_cl45_write(bp, phy,
5264                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x5);
5265                 bnx2x_cl45_write(bp, phy,
5266                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5267                                  0x400);
5268         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5269                    (phy->speed_cap_mask &
5270                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
5271                    ((phy->speed_cap_mask &
5272                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5273                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5274                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5275                 /* Set Flow control */
5276                 bnx2x_ext_phy_set_pause(params, phy, vars);
5277                 bnx2x_cl45_write(bp, phy,
5278                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
5279                 bnx2x_cl45_write(bp, phy,
5280                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
5281                 bnx2x_cl45_write(bp, phy,
5282                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
5283                 bnx2x_cl45_write(bp, phy,
5284                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
5285                 bnx2x_cl45_write(bp, phy,
5286                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
5287                 /* Enable RX-ALARM control to receive
5288                 interrupt for 1G speed change */
5289                 bnx2x_cl45_write(bp, phy,
5290                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x4);
5291                 bnx2x_cl45_write(bp, phy,
5292                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5293                                  0x400);
5294
5295         } else { /* Default 10G. Set only LASI control */
5296                 bnx2x_cl45_write(bp, phy,
5297                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 1);
5298         }
5299
5300         /* Set TX PreEmphasis if needed */
5301         if ((params->feature_config_flags &
5302              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5303                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
5304                          "TX_CTRL2 0x%x\n",
5305                          phy->tx_preemphasis[0],
5306                          phy->tx_preemphasis[1]);
5307                 bnx2x_cl45_write(bp, phy,
5308                                  MDIO_PMA_DEVAD,
5309                                  MDIO_PMA_REG_8726_TX_CTRL1,
5310                                  phy->tx_preemphasis[0]);
5311
5312                 bnx2x_cl45_write(bp, phy,
5313                                  MDIO_PMA_DEVAD,
5314                                  MDIO_PMA_REG_8726_TX_CTRL2,
5315                                  phy->tx_preemphasis[1]);
5316         }
5317
5318         /* Set GPIO3 to trigger SFP+ module insertion/removal */
5319         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
5320                             MISC_REGISTERS_GPIO_INPUT_HI_Z, params->port);
5321
5322         /* The GPIO should be swapped if the swap register is set and active */
5323         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5324         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5325
5326         /* Select function upon port-swap configuration */
5327         if (params->port == 0) {
5328                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
5329                 aeu_gpio_mask = (swap_val && swap_override) ?
5330                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
5331                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
5332         } else {
5333                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
5334                 aeu_gpio_mask = (swap_val && swap_override) ?
5335                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
5336                         AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
5337         }
5338         val = REG_RD(bp, offset);
5339         /* add GPIO3 to group */
5340         val |= aeu_gpio_mask;
5341         REG_WR(bp, offset, val);
5342         return 0;
5343
5344 }
5345
5346 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
5347                                   struct link_params *params)
5348 {
5349         struct bnx2x *bp = params->bp;
5350         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
5351         /* Set serial boot control for external load */
5352         bnx2x_cl45_write(bp, phy,
5353                          MDIO_PMA_DEVAD,
5354                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
5355 }
5356
5357 /******************************************************************/
5358 /*                      BCM8727 PHY SECTION                       */
5359 /******************************************************************/
5360
5361 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
5362                                     struct link_params *params, u8 mode)
5363 {
5364         struct bnx2x *bp = params->bp;
5365         u16 led_mode_bitmask = 0;
5366         u16 gpio_pins_bitmask = 0;
5367         u16 val;
5368         /* Only NOC flavor requires to set the LED specifically */
5369         if (!(phy->flags & FLAGS_NOC))
5370                 return;
5371         switch (mode) {
5372         case LED_MODE_FRONT_PANEL_OFF:
5373         case LED_MODE_OFF:
5374                 led_mode_bitmask = 0;
5375                 gpio_pins_bitmask = 0x03;
5376                 break;
5377         case LED_MODE_ON:
5378                 led_mode_bitmask = 0;
5379                 gpio_pins_bitmask = 0x02;
5380                 break;
5381         case LED_MODE_OPER:
5382                 led_mode_bitmask = 0x60;
5383                 gpio_pins_bitmask = 0x11;
5384                 break;
5385         }
5386         bnx2x_cl45_read(bp, phy,
5387                         MDIO_PMA_DEVAD,
5388                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5389                         &val);
5390         val &= 0xff8f;
5391         val |= led_mode_bitmask;
5392         bnx2x_cl45_write(bp, phy,
5393                          MDIO_PMA_DEVAD,
5394                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5395                          val);
5396         bnx2x_cl45_read(bp, phy,
5397                         MDIO_PMA_DEVAD,
5398                         MDIO_PMA_REG_8727_GPIO_CTRL,
5399                         &val);
5400         val &= 0xffe0;
5401         val |= gpio_pins_bitmask;
5402         bnx2x_cl45_write(bp, phy,
5403                          MDIO_PMA_DEVAD,
5404                          MDIO_PMA_REG_8727_GPIO_CTRL,
5405                          val);
5406 }
5407 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
5408                                 struct link_params *params) {
5409         u32 swap_val, swap_override;
5410         u8 port;
5411         /**
5412          * The PHY reset is controlled by GPIO 1. Fake the port number
5413          * to cancel the swap done in set_gpio()
5414          */
5415         struct bnx2x *bp = params->bp;
5416         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
5417         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
5418         port = (swap_val && swap_override) ^ 1;
5419         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
5420                             MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
5421 }
5422
5423 static u8 bnx2x_8727_config_init(struct bnx2x_phy *phy,
5424                                  struct link_params *params,
5425                                  struct link_vars *vars)
5426 {
5427         u16 tmp1, val, mod_abs;
5428         u16 rx_alarm_ctrl_val;
5429         u16 lasi_ctrl_val;
5430         struct bnx2x *bp = params->bp;
5431         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
5432
5433         bnx2x_wait_reset_complete(bp, phy);
5434         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
5435         lasi_ctrl_val = 0x0004;
5436
5437         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
5438         /* enable LASI */
5439         bnx2x_cl45_write(bp, phy,
5440                          MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5441                          rx_alarm_ctrl_val);
5442
5443         bnx2x_cl45_write(bp, phy,
5444                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, lasi_ctrl_val);
5445
5446         /* Initially configure  MOD_ABS to interrupt when
5447         module is presence( bit 8) */
5448         bnx2x_cl45_read(bp, phy,
5449                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5450         /* Set EDC off by setting OPTXLOS signal input to low
5451         (bit 9).
5452         When the EDC is off it locks onto a reference clock and
5453         avoids becoming 'lost'.*/
5454         mod_abs &= ~(1<<8);
5455         if (!(phy->flags & FLAGS_NOC))
5456                 mod_abs &= ~(1<<9);
5457         bnx2x_cl45_write(bp, phy,
5458                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5459
5460
5461         /* Make MOD_ABS give interrupt on change */
5462         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
5463                         &val);
5464         val |= (1<<12);
5465         if (phy->flags & FLAGS_NOC)
5466                 val |= (3<<5);
5467
5468         /**
5469          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
5470          * status which reflect SFP+ module over-current
5471          */
5472         if (!(phy->flags & FLAGS_NOC))
5473                 val &= 0xff8f; /* Reset bits 4-6 */
5474         bnx2x_cl45_write(bp, phy,
5475                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
5476
5477         bnx2x_8727_power_module(bp, phy, 1);
5478
5479         bnx2x_cl45_read(bp, phy,
5480                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
5481
5482         bnx2x_cl45_read(bp, phy,
5483                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM, &tmp1);
5484
5485         /* Set option 1G speed */
5486         if (phy->req_line_speed == SPEED_1000) {
5487                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
5488                 bnx2x_cl45_write(bp, phy,
5489                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
5490                 bnx2x_cl45_write(bp, phy,
5491                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
5492                 bnx2x_cl45_read(bp, phy,
5493                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
5494                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
5495                 /**
5496                  * Power down the XAUI until link is up in case of dual-media
5497                  * and 1G
5498                  */
5499                 if (DUAL_MEDIA(params)) {
5500                         bnx2x_cl45_read(bp, phy,
5501                                         MDIO_PMA_DEVAD,
5502                                         MDIO_PMA_REG_8727_PCS_GP, &val);
5503                         val |= (3<<10);
5504                         bnx2x_cl45_write(bp, phy,
5505                                          MDIO_PMA_DEVAD,
5506                                          MDIO_PMA_REG_8727_PCS_GP, val);
5507                 }
5508         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5509                    ((phy->speed_cap_mask &
5510                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
5511                    ((phy->speed_cap_mask &
5512                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
5513                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5514
5515                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
5516                 bnx2x_cl45_write(bp, phy,
5517                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
5518                 bnx2x_cl45_write(bp, phy,
5519                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
5520         } else {
5521                 /**
5522                  * Since the 8727 has only single reset pin, need to set the 10G
5523                  * registers although it is default
5524                  */
5525                 bnx2x_cl45_write(bp, phy,
5526                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
5527                                  0x0020);
5528                 bnx2x_cl45_write(bp, phy,
5529                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
5530                 bnx2x_cl45_write(bp, phy,
5531                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
5532                 bnx2x_cl45_write(bp, phy,
5533                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
5534                                  0x0008);
5535         }
5536
5537         /* Set 2-wire transfer rate of SFP+ module EEPROM
5538          * to 100Khz since some DACs(direct attached cables) do
5539          * not work at 400Khz.
5540          */
5541         bnx2x_cl45_write(bp, phy,
5542                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
5543                          0xa001);
5544
5545         /* Set TX PreEmphasis if needed */
5546         if ((params->feature_config_flags &
5547              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
5548                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
5549                            phy->tx_preemphasis[0],
5550                            phy->tx_preemphasis[1]);
5551                 bnx2x_cl45_write(bp, phy,
5552                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
5553                                  phy->tx_preemphasis[0]);
5554
5555                 bnx2x_cl45_write(bp, phy,
5556                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
5557                                  phy->tx_preemphasis[1]);
5558         }
5559
5560         return 0;
5561 }
5562
5563 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
5564                                       struct link_params *params)
5565 {
5566         struct bnx2x *bp = params->bp;
5567         u16 mod_abs, rx_alarm_status;
5568         u32 val = REG_RD(bp, params->shmem_base +
5569                              offsetof(struct shmem_region, dev_info.
5570                                       port_feature_config[params->port].
5571                                       config));
5572         bnx2x_cl45_read(bp, phy,
5573                       MDIO_PMA_DEVAD,
5574                       MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
5575         if (mod_abs & (1<<8)) {
5576
5577                 /* Module is absent */
5578                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5579                             "show module is absent\n");
5580
5581                 /* 1. Set mod_abs to detect next module
5582                 presence event
5583                    2. Set EDC off by setting OPTXLOS signal input to low
5584                         (bit 9).
5585                         When the EDC is off it locks onto a reference clock and
5586                         avoids becoming 'lost'.*/
5587                 mod_abs &= ~(1<<8);
5588                 if (!(phy->flags & FLAGS_NOC))
5589                         mod_abs &= ~(1<<9);
5590                 bnx2x_cl45_write(bp, phy,
5591                                MDIO_PMA_DEVAD,
5592                                MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5593
5594                 /* Clear RX alarm since it stays up as long as
5595                 the mod_abs wasn't changed */
5596                 bnx2x_cl45_read(bp, phy,
5597                               MDIO_PMA_DEVAD,
5598                               MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5599
5600         } else {
5601                 /* Module is present */
5602                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
5603                             "show module is present\n");
5604                 /* First thing, disable transmitter,
5605                 and if the module is ok, the
5606                 module_detection will enable it*/
5607
5608                 /* 1. Set mod_abs to detect next module
5609                 absent event ( bit 8)
5610                    2. Restore the default polarity of the OPRXLOS signal and
5611                 this signal will then correctly indicate the presence or
5612                 absence of the Rx signal. (bit 9) */
5613                 mod_abs |= (1<<8);
5614                 if (!(phy->flags & FLAGS_NOC))
5615                         mod_abs |= (1<<9);
5616                 bnx2x_cl45_write(bp, phy,
5617                                  MDIO_PMA_DEVAD,
5618                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
5619
5620                 /* Clear RX alarm since it stays up as long as
5621                 the mod_abs wasn't changed. This is need to be done
5622                 before calling the module detection, otherwise it will clear
5623                 the link update alarm */
5624                 bnx2x_cl45_read(bp, phy,
5625                                 MDIO_PMA_DEVAD,
5626                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5627
5628
5629                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
5630                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
5631                         bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5632
5633                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
5634                         bnx2x_sfp_module_detection(phy, params);
5635                 else
5636                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
5637         }
5638
5639         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
5640                  rx_alarm_status);
5641         /* No need to check link status in case of
5642         module plugged in/out */
5643 }
5644
5645 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
5646                                  struct link_params *params,
5647                                  struct link_vars *vars)
5648
5649 {
5650         struct bnx2x *bp = params->bp;
5651         u8 link_up = 0;
5652         u16 link_status = 0;
5653         u16 rx_alarm_status, lasi_ctrl, val1;
5654
5655         /* If PHY is not initialized, do not check link status */
5656         bnx2x_cl45_read(bp, phy,
5657                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL,
5658                         &lasi_ctrl);
5659         if (!lasi_ctrl)
5660                 return 0;
5661
5662         /* Check the LASI */
5663         bnx2x_cl45_read(bp, phy,
5664                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM,
5665                         &rx_alarm_status);
5666         vars->line_speed = 0;
5667         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
5668
5669         bnx2x_cl45_read(bp, phy,
5670                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
5671
5672         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
5673
5674         /* Clear MSG-OUT */
5675         bnx2x_cl45_read(bp, phy,
5676                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
5677
5678         /**
5679          * If a module is present and there is need to check
5680          * for over current
5681          */
5682         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
5683                 /* Check over-current using 8727 GPIO0 input*/
5684                 bnx2x_cl45_read(bp, phy,
5685                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
5686                                 &val1);
5687
5688                 if ((val1 & (1<<8)) == 0) {
5689                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
5690                                        " on port %d\n", params->port);
5691                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
5692                                             " been detected and the power to "
5693                                             "that SFP+ module has been removed"
5694                                             " to prevent failure of the card."
5695                                             " Please remove the SFP+ module and"
5696                                             " restart the system to clear this"
5697                                             " error.\n",
5698                                    params->port);
5699
5700                         /*
5701                          * Disable all RX_ALARMs except for
5702                          * mod_abs
5703                          */
5704                         bnx2x_cl45_write(bp, phy,
5705                                          MDIO_PMA_DEVAD,
5706                                          MDIO_PMA_REG_RX_ALARM_CTRL, (1<<5));
5707
5708                         bnx2x_cl45_read(bp, phy,
5709                                         MDIO_PMA_DEVAD,
5710                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5711                         /* Wait for module_absent_event */
5712                         val1 |= (1<<8);
5713                         bnx2x_cl45_write(bp, phy,
5714                                          MDIO_PMA_DEVAD,
5715                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
5716                         /* Clear RX alarm */
5717                         bnx2x_cl45_read(bp, phy,
5718                                 MDIO_PMA_DEVAD,
5719                                 MDIO_PMA_REG_RX_ALARM, &rx_alarm_status);
5720                         return 0;
5721                 }
5722         } /* Over current check */
5723
5724         /* When module absent bit is set, check module */
5725         if (rx_alarm_status & (1<<5)) {
5726                 bnx2x_8727_handle_mod_abs(phy, params);
5727                 /* Enable all mod_abs and link detection bits */
5728                 bnx2x_cl45_write(bp, phy,
5729                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_ALARM_CTRL,
5730                                  ((1<<5) | (1<<2)));
5731         }
5732         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
5733         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
5734         /* If transmitter is disabled, ignore false link up indication */
5735         bnx2x_cl45_read(bp, phy,
5736                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
5737         if (val1 & (1<<15)) {
5738                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
5739                 return 0;
5740         }
5741
5742         bnx2x_cl45_read(bp, phy,
5743                         MDIO_PMA_DEVAD,
5744                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
5745
5746         /* Bits 0..2 --> speed detected,
5747            bits 13..15--> link is down */
5748         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
5749                 link_up = 1;
5750                 vars->line_speed = SPEED_10000;
5751         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
5752                 link_up = 1;
5753                 vars->line_speed = SPEED_1000;
5754                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
5755                            params->port);
5756         } else {
5757                 link_up = 0;
5758                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
5759                            params->port);
5760         }
5761         if (link_up)
5762                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
5763
5764         if ((DUAL_MEDIA(params)) &&
5765             (phy->req_line_speed == SPEED_1000)) {
5766                 bnx2x_cl45_read(bp, phy,
5767                                 MDIO_PMA_DEVAD,
5768                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
5769                 /**
5770                  * In case of dual-media board and 1G, power up the XAUI side,
5771                  * otherwise power it down. For 10G it is done automatically
5772                  */
5773                 if (link_up)
5774                         val1 &= ~(3<<10);
5775                 else
5776                         val1 |= (3<<10);
5777                 bnx2x_cl45_write(bp, phy,
5778                                  MDIO_PMA_DEVAD,
5779                                  MDIO_PMA_REG_8727_PCS_GP, val1);
5780         }
5781         return link_up;
5782 }
5783
5784 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
5785                                   struct link_params *params)
5786 {
5787         struct bnx2x *bp = params->bp;
5788         /* Disable Transmitter */
5789         bnx2x_sfp_set_transmitter(bp, phy, params->port, 0);
5790         /* Clear LASI */
5791         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0);
5792
5793 }
5794
5795 /******************************************************************/
5796 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
5797 /******************************************************************/
5798 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
5799                                            struct link_params *params)
5800 {
5801         u16 val, fw_ver1, fw_ver2, cnt;
5802         struct bnx2x *bp = params->bp;
5803
5804         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
5805         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
5806         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
5807         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5808         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
5809         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
5810         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
5811
5812         for (cnt = 0; cnt < 100; cnt++) {
5813                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5814                 if (val & 1)
5815                         break;
5816                 udelay(5);
5817         }
5818         if (cnt == 100) {
5819                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
5820                 bnx2x_save_spirom_version(bp, params->port, 0,
5821                                           phy->ver_addr);
5822                 return;
5823         }
5824
5825
5826         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
5827         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
5828         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
5829         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
5830         for (cnt = 0; cnt < 100; cnt++) {
5831                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
5832                 if (val & 1)
5833                         break;
5834                 udelay(5);
5835         }
5836         if (cnt == 100) {
5837                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
5838                 bnx2x_save_spirom_version(bp, params->port, 0,
5839                                           phy->ver_addr);
5840                 return;
5841         }
5842
5843         /* lower 16 bits of the register SPI_FW_STATUS */
5844         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
5845         /* upper 16 bits of register SPI_FW_STATUS */
5846         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
5847
5848         bnx2x_save_spirom_version(bp, params->port, (fw_ver2<<16) | fw_ver1,
5849                                   phy->ver_addr);
5850 }
5851
5852 static void bnx2x_848xx_set_led(struct bnx2x *bp,
5853                                 struct bnx2x_phy *phy)
5854 {
5855         u16 val;
5856
5857         /* PHYC_CTL_LED_CTL */
5858         bnx2x_cl45_read(bp, phy,
5859                         MDIO_PMA_DEVAD,
5860                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
5861         val &= 0xFE00;
5862         val |= 0x0092;
5863
5864         bnx2x_cl45_write(bp, phy,
5865                          MDIO_PMA_DEVAD,
5866                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
5867
5868         bnx2x_cl45_write(bp, phy,
5869                          MDIO_PMA_DEVAD,
5870                          MDIO_PMA_REG_8481_LED1_MASK,
5871                          0x80);
5872
5873         bnx2x_cl45_write(bp, phy,
5874                          MDIO_PMA_DEVAD,
5875                          MDIO_PMA_REG_8481_LED2_MASK,
5876                          0x18);
5877
5878         bnx2x_cl45_write(bp, phy,
5879                          MDIO_PMA_DEVAD,
5880                          MDIO_PMA_REG_8481_LED3_MASK,
5881                          0x0040);
5882
5883         /* 'Interrupt Mask' */
5884         bnx2x_cl45_write(bp, phy,
5885                          MDIO_AN_DEVAD,
5886                          0xFFFB, 0xFFFD);
5887 }
5888
5889 static u8 bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
5890                                       struct link_params *params,
5891                                       struct link_vars *vars)
5892 {
5893         struct bnx2x *bp = params->bp;
5894         u16 autoneg_val, an_1000_val, an_10_100_val;
5895
5896         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
5897                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
5898
5899         bnx2x_cl45_write(bp, phy,
5900                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
5901
5902         bnx2x_848xx_set_led(bp, phy);
5903
5904         /* set 1000 speed advertisement */
5905         bnx2x_cl45_read(bp, phy,
5906                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
5907                         &an_1000_val);
5908
5909         bnx2x_ext_phy_set_pause(params, phy, vars);
5910         bnx2x_cl45_read(bp, phy,
5911                         MDIO_AN_DEVAD,
5912                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
5913                         &an_10_100_val);
5914         bnx2x_cl45_read(bp, phy,
5915                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
5916                         &autoneg_val);
5917         /* Disable forced speed */
5918         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
5919         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
5920
5921         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5922              (phy->speed_cap_mask &
5923              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5924             (phy->req_line_speed == SPEED_1000)) {
5925                 an_1000_val |= (1<<8);
5926                 autoneg_val |= (1<<9 | 1<<12);
5927                 if (phy->req_duplex == DUPLEX_FULL)
5928                         an_1000_val |= (1<<9);
5929                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
5930         } else
5931                 an_1000_val &= ~((1<<8) | (1<<9));
5932
5933         bnx2x_cl45_write(bp, phy,
5934                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
5935                          an_1000_val);
5936
5937         /* set 10 speed advertisement */
5938         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5939              (phy->speed_cap_mask &
5940              (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
5941               PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
5942                 an_10_100_val |= (1<<7);
5943                 /* Enable autoneg and restart autoneg for legacy speeds */
5944                 autoneg_val |= (1<<9 | 1<<12);
5945
5946                 if (phy->req_duplex == DUPLEX_FULL)
5947                         an_10_100_val |= (1<<8);
5948                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
5949         }
5950         /* set 10 speed advertisement */
5951         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5952             (phy->speed_cap_mask &
5953           (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
5954            PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
5955                 an_10_100_val |= (1<<5);
5956                 autoneg_val |= (1<<9 | 1<<12);
5957                 if (phy->req_duplex == DUPLEX_FULL)
5958                         an_10_100_val |= (1<<6);
5959                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
5960         }
5961
5962         /* Only 10/100 are allowed to work in FORCE mode */
5963         if (phy->req_line_speed == SPEED_100) {
5964                 autoneg_val |= (1<<13);
5965                 /* Enabled AUTO-MDIX when autoneg is disabled */
5966                 bnx2x_cl45_write(bp, phy,
5967                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
5968                                  (1<<15 | 1<<9 | 7<<0));
5969                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
5970         }
5971         if (phy->req_line_speed == SPEED_10) {
5972                 /* Enabled AUTO-MDIX when autoneg is disabled */
5973                 bnx2x_cl45_write(bp, phy,
5974                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
5975                                  (1<<15 | 1<<9 | 7<<0));
5976                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
5977         }
5978
5979         bnx2x_cl45_write(bp, phy,
5980                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
5981                          an_10_100_val);
5982
5983         if (phy->req_duplex == DUPLEX_FULL)
5984                 autoneg_val |= (1<<8);
5985
5986         bnx2x_cl45_write(bp, phy,
5987                          MDIO_AN_DEVAD,
5988                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
5989
5990         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
5991             (phy->speed_cap_mask &
5992              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
5993                 (phy->req_line_speed == SPEED_10000)) {
5994                 DP(NETIF_MSG_LINK, "Advertising 10G\n");
5995                 /* Restart autoneg for 10G*/
5996
5997                 bnx2x_cl45_write(bp, phy,
5998                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
5999                                  0x3200);
6000         } else if (phy->req_line_speed != SPEED_10 &&
6001                    phy->req_line_speed != SPEED_100) {
6002                 bnx2x_cl45_write(bp, phy,
6003                                  MDIO_AN_DEVAD,
6004                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
6005                                  1);
6006         }
6007         /* Save spirom version */
6008         bnx2x_save_848xx_spirom_version(phy, params);
6009
6010         return 0;
6011 }
6012
6013 static u8 bnx2x_8481_config_init(struct bnx2x_phy *phy,
6014                                  struct link_params *params,
6015                                  struct link_vars *vars)
6016 {
6017         struct bnx2x *bp = params->bp;
6018         /* Restore normal power mode*/
6019         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6020                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6021
6022         /* HW reset */
6023         bnx2x_ext_phy_hw_reset(bp, params->port);
6024         bnx2x_wait_reset_complete(bp, phy);
6025
6026         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
6027         return bnx2x_848xx_cmn_config_init(phy, params, vars);
6028 }
6029
6030 static u8 bnx2x_848x3_config_init(struct bnx2x_phy *phy,
6031                                   struct link_params *params,
6032                                   struct link_vars *vars)
6033 {
6034         struct bnx2x *bp = params->bp;
6035         u8 port, initialize = 1;
6036         u16 val;
6037         u16 temp;
6038         u32 actual_phy_selection;
6039         u8 rc = 0;
6040
6041         /* This is just for MDIO_CTL_REG_84823_MEDIA register. */
6042
6043         msleep(1);
6044         if (CHIP_IS_E2(bp))
6045                 port = BP_PATH(bp);
6046         else
6047                 port = params->port;
6048         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6049                        MISC_REGISTERS_GPIO_OUTPUT_HIGH,
6050                        port);
6051         bnx2x_wait_reset_complete(bp, phy);
6052         /* Wait for GPHY to come out of reset */
6053         msleep(50);
6054         /* BCM84823 requires that XGXS links up first @ 10G for normal
6055         behavior */
6056         temp = vars->line_speed;
6057         vars->line_speed = SPEED_10000;
6058         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
6059         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
6060         vars->line_speed = temp;
6061
6062         /* Set dual-media configuration according to configuration */
6063
6064         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
6065                         MDIO_CTL_REG_84823_MEDIA, &val);
6066         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
6067                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
6068                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
6069                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
6070                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
6071         val |= MDIO_CTL_REG_84823_CTRL_MAC_XFI |
6072                 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L;
6073
6074         actual_phy_selection = bnx2x_phy_selection(params);
6075
6076         switch (actual_phy_selection) {
6077         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6078                 /* Do nothing. Essentialy this is like the priority copper */
6079                 break;
6080         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6081                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
6082                 break;
6083         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6084                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
6085                 break;
6086         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
6087                 /* Do nothing here. The first PHY won't be initialized at all */
6088                 break;
6089         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
6090                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
6091                 initialize = 0;
6092                 break;
6093         }
6094         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
6095                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
6096
6097         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
6098                          MDIO_CTL_REG_84823_MEDIA, val);
6099         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
6100                    params->multi_phy_config, val);
6101
6102         if (initialize)
6103                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
6104         else
6105                 bnx2x_save_848xx_spirom_version(phy, params);
6106         return rc;
6107 }
6108
6109 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
6110                                        struct link_params *params,
6111                                        struct link_vars *vars)
6112 {
6113         struct bnx2x *bp = params->bp;
6114         u16 val, val1, val2;
6115         u8 link_up = 0;
6116
6117         /* Check 10G-BaseT link status */
6118         /* Check PMD signal ok */
6119         bnx2x_cl45_read(bp, phy,
6120                         MDIO_AN_DEVAD, 0xFFFA, &val1);
6121         bnx2x_cl45_read(bp, phy,
6122                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
6123                         &val2);
6124         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
6125
6126         /* Check link 10G */
6127         if (val2 & (1<<11)) {
6128                 vars->line_speed = SPEED_10000;
6129                 link_up = 1;
6130                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6131         } else { /* Check Legacy speed link */
6132                 u16 legacy_status, legacy_speed;
6133
6134                 /* Enable expansion register 0x42 (Operation mode status) */
6135                 bnx2x_cl45_write(bp, phy,
6136                                  MDIO_AN_DEVAD,
6137                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
6138
6139                 /* Get legacy speed operation status */
6140                 bnx2x_cl45_read(bp, phy,
6141                                 MDIO_AN_DEVAD,
6142                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
6143                                 &legacy_status);
6144
6145                 DP(NETIF_MSG_LINK, "Legacy speed status"
6146                              " = 0x%x\n", legacy_status);
6147                 link_up = ((legacy_status & (1<<11)) == (1<<11));
6148                 if (link_up) {
6149                         legacy_speed = (legacy_status & (3<<9));
6150                         if (legacy_speed == (0<<9))
6151                                 vars->line_speed = SPEED_10;
6152                         else if (legacy_speed == (1<<9))
6153                                 vars->line_speed = SPEED_100;
6154                         else if (legacy_speed == (2<<9))
6155                                 vars->line_speed = SPEED_1000;
6156                         else /* Should not happen */
6157                                 vars->line_speed = 0;
6158
6159                         if (legacy_status & (1<<8))
6160                                 vars->duplex = DUPLEX_FULL;
6161                         else
6162                                 vars->duplex = DUPLEX_HALF;
6163
6164                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
6165                                    " is_duplex_full= %d\n", vars->line_speed,
6166                                    (vars->duplex == DUPLEX_FULL));
6167                         /* Check legacy speed AN resolution */
6168                         bnx2x_cl45_read(bp, phy,
6169                                         MDIO_AN_DEVAD,
6170                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
6171                                         &val);
6172                         if (val & (1<<5))
6173                                 vars->link_status |=
6174                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6175                         bnx2x_cl45_read(bp, phy,
6176                                         MDIO_AN_DEVAD,
6177                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
6178                                         &val);
6179                         if ((val & (1<<0)) == 0)
6180                                 vars->link_status |=
6181                                         LINK_STATUS_PARALLEL_DETECTION_USED;
6182                 }
6183         }
6184         if (link_up) {
6185                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
6186                            vars->line_speed);
6187                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6188         }
6189
6190         return link_up;
6191 }
6192
6193 static u8 bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
6194 {
6195         u8 status = 0;
6196         u32 spirom_ver;
6197         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
6198         status = bnx2x_format_ver(spirom_ver, str, len);
6199         return status;
6200 }
6201
6202 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
6203                                 struct link_params *params)
6204 {
6205         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6206                             MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
6207         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6208                             MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
6209 }
6210
6211 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
6212                                         struct link_params *params)
6213 {
6214         bnx2x_cl45_write(params->bp, phy,
6215                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6216         bnx2x_cl45_write(params->bp, phy,
6217                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
6218 }
6219
6220 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
6221                                    struct link_params *params)
6222 {
6223         struct bnx2x *bp = params->bp;
6224         u8 port;
6225         if (CHIP_IS_E2(bp))
6226                 port = BP_PATH(bp);
6227         else
6228                 port = params->port;
6229         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
6230                             MISC_REGISTERS_GPIO_OUTPUT_LOW,
6231                             port);
6232 }
6233
6234 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
6235                                      struct link_params *params, u8 mode)
6236 {
6237         struct bnx2x *bp = params->bp;
6238         u16 val;
6239
6240         switch (mode) {
6241         case LED_MODE_OFF:
6242
6243                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", params->port);
6244
6245                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6246                     SHARED_HW_CFG_LED_EXTPHY1) {
6247
6248                         /* Set LED masks */
6249                         bnx2x_cl45_write(bp, phy,
6250                                         MDIO_PMA_DEVAD,
6251                                         MDIO_PMA_REG_8481_LED1_MASK,
6252                                         0x0);
6253
6254                         bnx2x_cl45_write(bp, phy,
6255                                         MDIO_PMA_DEVAD,
6256                                         MDIO_PMA_REG_8481_LED2_MASK,
6257                                         0x0);
6258
6259                         bnx2x_cl45_write(bp, phy,
6260                                         MDIO_PMA_DEVAD,
6261                                         MDIO_PMA_REG_8481_LED3_MASK,
6262                                         0x0);
6263
6264                         bnx2x_cl45_write(bp, phy,
6265                                         MDIO_PMA_DEVAD,
6266                                         MDIO_PMA_REG_8481_LED5_MASK,
6267                                         0x0);
6268
6269                 } else {
6270                         bnx2x_cl45_write(bp, phy,
6271                                          MDIO_PMA_DEVAD,
6272                                          MDIO_PMA_REG_8481_LED1_MASK,
6273                                          0x0);
6274                 }
6275                 break;
6276         case LED_MODE_FRONT_PANEL_OFF:
6277
6278                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
6279                    params->port);
6280
6281                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6282                     SHARED_HW_CFG_LED_EXTPHY1) {
6283
6284                         /* Set LED masks */
6285                         bnx2x_cl45_write(bp, phy,
6286                                         MDIO_PMA_DEVAD,
6287                                         MDIO_PMA_REG_8481_LED1_MASK,
6288                                         0x0);
6289
6290                         bnx2x_cl45_write(bp, phy,
6291                                         MDIO_PMA_DEVAD,
6292                                         MDIO_PMA_REG_8481_LED2_MASK,
6293                                         0x0);
6294
6295                         bnx2x_cl45_write(bp, phy,
6296                                         MDIO_PMA_DEVAD,
6297                                         MDIO_PMA_REG_8481_LED3_MASK,
6298                                         0x0);
6299
6300                         bnx2x_cl45_write(bp, phy,
6301                                         MDIO_PMA_DEVAD,
6302                                         MDIO_PMA_REG_8481_LED5_MASK,
6303                                         0x20);
6304
6305                 } else {
6306                         bnx2x_cl45_write(bp, phy,
6307                                          MDIO_PMA_DEVAD,
6308                                          MDIO_PMA_REG_8481_LED1_MASK,
6309                                          0x0);
6310                 }
6311                 break;
6312         case LED_MODE_ON:
6313
6314                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", params->port);
6315
6316                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6317                     SHARED_HW_CFG_LED_EXTPHY1) {
6318                         /* Set control reg */
6319                         bnx2x_cl45_read(bp, phy,
6320                                         MDIO_PMA_DEVAD,
6321                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6322                                         &val);
6323                         val &= 0x8000;
6324                         val |= 0x2492;
6325
6326                         bnx2x_cl45_write(bp, phy,
6327                                         MDIO_PMA_DEVAD,
6328                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6329                                         val);
6330
6331                         /* Set LED masks */
6332                         bnx2x_cl45_write(bp, phy,
6333                                         MDIO_PMA_DEVAD,
6334                                         MDIO_PMA_REG_8481_LED1_MASK,
6335                                         0x0);
6336
6337                         bnx2x_cl45_write(bp, phy,
6338                                         MDIO_PMA_DEVAD,
6339                                         MDIO_PMA_REG_8481_LED2_MASK,
6340                                         0x20);
6341
6342                         bnx2x_cl45_write(bp, phy,
6343                                         MDIO_PMA_DEVAD,
6344                                         MDIO_PMA_REG_8481_LED3_MASK,
6345                                         0x20);
6346
6347                         bnx2x_cl45_write(bp, phy,
6348                                         MDIO_PMA_DEVAD,
6349                                         MDIO_PMA_REG_8481_LED5_MASK,
6350                                         0x0);
6351                 } else {
6352                         bnx2x_cl45_write(bp, phy,
6353                                         MDIO_PMA_DEVAD,
6354                                         MDIO_PMA_REG_8481_LED1_MASK,
6355                                         0x20);
6356                 }
6357                 break;
6358
6359         case LED_MODE_OPER:
6360
6361                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", params->port);
6362
6363                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
6364                     SHARED_HW_CFG_LED_EXTPHY1) {
6365
6366                         /* Set control reg */
6367                         bnx2x_cl45_read(bp, phy,
6368                                         MDIO_PMA_DEVAD,
6369                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
6370                                         &val);
6371
6372                         if (!((val &
6373                               MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
6374                            >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)){
6375                                 DP(NETIF_MSG_LINK, "Seting LINK_SIGNAL\n");
6376                                 bnx2x_cl45_write(bp, phy,
6377                                                  MDIO_PMA_DEVAD,
6378                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
6379                                                  0xa492);
6380                         }
6381
6382                         /* Set LED masks */
6383                         bnx2x_cl45_write(bp, phy,
6384                                         MDIO_PMA_DEVAD,
6385                                         MDIO_PMA_REG_8481_LED1_MASK,
6386                                         0x10);
6387
6388                         bnx2x_cl45_write(bp, phy,
6389                                         MDIO_PMA_DEVAD,
6390                                         MDIO_PMA_REG_8481_LED2_MASK,
6391                                         0x80);
6392
6393                         bnx2x_cl45_write(bp, phy,
6394                                         MDIO_PMA_DEVAD,
6395                                         MDIO_PMA_REG_8481_LED3_MASK,
6396                                         0x98);
6397
6398                         bnx2x_cl45_write(bp, phy,
6399                                         MDIO_PMA_DEVAD,
6400                                         MDIO_PMA_REG_8481_LED5_MASK,
6401                                         0x40);
6402
6403                 } else {
6404                         bnx2x_cl45_write(bp, phy,
6405                                          MDIO_PMA_DEVAD,
6406                                          MDIO_PMA_REG_8481_LED1_MASK,
6407                                          0x80);
6408                 }
6409                 break;
6410         }
6411 }
6412 /******************************************************************/
6413 /*                      SFX7101 PHY SECTION                       */
6414 /******************************************************************/
6415 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
6416                                        struct link_params *params)
6417 {
6418         struct bnx2x *bp = params->bp;
6419         /* SFX7101_XGXS_TEST1 */
6420         bnx2x_cl45_write(bp, phy,
6421                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
6422 }
6423
6424 static u8 bnx2x_7101_config_init(struct bnx2x_phy *phy,
6425                                  struct link_params *params,
6426                                  struct link_vars *vars)
6427 {
6428         u16 fw_ver1, fw_ver2, val;
6429         struct bnx2x *bp = params->bp;
6430         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
6431
6432         /* Restore normal power mode*/
6433         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6434                             MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
6435         /* HW reset */
6436         bnx2x_ext_phy_hw_reset(bp, params->port);
6437         bnx2x_wait_reset_complete(bp, phy);
6438
6439         bnx2x_cl45_write(bp, phy,
6440                          MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_CTRL, 0x1);
6441         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
6442         bnx2x_cl45_write(bp, phy,
6443                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
6444
6445         bnx2x_ext_phy_set_pause(params, phy, vars);
6446         /* Restart autoneg */
6447         bnx2x_cl45_read(bp, phy,
6448                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
6449         val |= 0x200;
6450         bnx2x_cl45_write(bp, phy,
6451                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
6452
6453         /* Save spirom version */
6454         bnx2x_cl45_read(bp, phy,
6455                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
6456
6457         bnx2x_cl45_read(bp, phy,
6458                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
6459         bnx2x_save_spirom_version(bp, params->port,
6460                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
6461         return 0;
6462 }
6463
6464 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
6465                                  struct link_params *params,
6466                                  struct link_vars *vars)
6467 {
6468         struct bnx2x *bp = params->bp;
6469         u8 link_up;
6470         u16 val1, val2;
6471         bnx2x_cl45_read(bp, phy,
6472                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val2);
6473         bnx2x_cl45_read(bp, phy,
6474                         MDIO_PMA_DEVAD, MDIO_PMA_REG_LASI_STATUS, &val1);
6475         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
6476                    val2, val1);
6477         bnx2x_cl45_read(bp, phy,
6478                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
6479         bnx2x_cl45_read(bp, phy,
6480                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
6481         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
6482                    val2, val1);
6483         link_up = ((val1 & 4) == 4);
6484         /* if link is up
6485          * print the AN outcome of the SFX7101 PHY
6486          */
6487         if (link_up) {
6488                 bnx2x_cl45_read(bp, phy,
6489                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
6490                                 &val2);
6491                 vars->line_speed = SPEED_10000;
6492                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
6493                            val2, (val2 & (1<<14)));
6494                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
6495                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
6496         }
6497         return link_up;
6498 }
6499
6500
6501 static u8 bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6502 {
6503         if (*len < 5)
6504                 return -EINVAL;
6505         str[0] = (spirom_ver & 0xFF);
6506         str[1] = (spirom_ver & 0xFF00) >> 8;
6507         str[2] = (spirom_ver & 0xFF0000) >> 16;
6508         str[3] = (spirom_ver & 0xFF000000) >> 24;
6509         str[4] = '\0';
6510         *len -= 5;
6511         return 0;
6512 }
6513
6514 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
6515 {
6516         u16 val, cnt;
6517
6518         bnx2x_cl45_read(bp, phy,
6519                       MDIO_PMA_DEVAD,
6520                       MDIO_PMA_REG_7101_RESET, &val);
6521
6522         for (cnt = 0; cnt < 10; cnt++) {
6523                 msleep(50);
6524                 /* Writes a self-clearing reset */
6525                 bnx2x_cl45_write(bp, phy,
6526                                MDIO_PMA_DEVAD,
6527                                MDIO_PMA_REG_7101_RESET,
6528                                (val | (1<<15)));
6529                 /* Wait for clear */
6530                 bnx2x_cl45_read(bp, phy,
6531                               MDIO_PMA_DEVAD,
6532                               MDIO_PMA_REG_7101_RESET, &val);
6533
6534                 if ((val & (1<<15)) == 0)
6535                         break;
6536         }
6537 }
6538
6539 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
6540                                 struct link_params *params) {
6541         /* Low power mode is controlled by GPIO 2 */
6542         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
6543                             MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6544         /* The PHY reset is controlled by GPIO 1 */
6545         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
6546                             MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
6547 }
6548
6549 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
6550                                     struct link_params *params, u8 mode)
6551 {
6552         u16 val = 0;
6553         struct bnx2x *bp = params->bp;
6554         switch (mode) {
6555         case LED_MODE_FRONT_PANEL_OFF:
6556         case LED_MODE_OFF:
6557                 val = 2;
6558                 break;
6559         case LED_MODE_ON:
6560                 val = 1;
6561                 break;
6562         case LED_MODE_OPER:
6563                 val = 0;
6564                 break;
6565         }
6566         bnx2x_cl45_write(bp, phy,
6567                          MDIO_PMA_DEVAD,
6568                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
6569                          val);
6570 }
6571
6572 /******************************************************************/
6573 /*                      STATIC PHY DECLARATION                    */
6574 /******************************************************************/
6575
6576 static struct bnx2x_phy phy_null = {
6577         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
6578         .addr           = 0,
6579         .flags          = FLAGS_INIT_XGXS_FIRST,
6580         .def_md_devad   = 0,
6581         .reserved       = 0,
6582         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6583         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6584         .mdio_ctrl      = 0,
6585         .supported      = 0,
6586         .media_type     = ETH_PHY_NOT_PRESENT,
6587         .ver_addr       = 0,
6588         .req_flow_ctrl  = 0,
6589         .req_line_speed = 0,
6590         .speed_cap_mask = 0,
6591         .req_duplex     = 0,
6592         .rsrv           = 0,
6593         .config_init    = (config_init_t)NULL,
6594         .read_status    = (read_status_t)NULL,
6595         .link_reset     = (link_reset_t)NULL,
6596         .config_loopback = (config_loopback_t)NULL,
6597         .format_fw_ver  = (format_fw_ver_t)NULL,
6598         .hw_reset       = (hw_reset_t)NULL,
6599         .set_link_led   = (set_link_led_t)NULL,
6600         .phy_specific_func = (phy_specific_func_t)NULL
6601 };
6602
6603 static struct bnx2x_phy phy_serdes = {
6604         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
6605         .addr           = 0xff,
6606         .flags          = 0,
6607         .def_md_devad   = 0,
6608         .reserved       = 0,
6609         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6610         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6611         .mdio_ctrl      = 0,
6612         .supported      = (SUPPORTED_10baseT_Half |
6613                            SUPPORTED_10baseT_Full |
6614                            SUPPORTED_100baseT_Half |
6615                            SUPPORTED_100baseT_Full |
6616                            SUPPORTED_1000baseT_Full |
6617                            SUPPORTED_2500baseX_Full |
6618                            SUPPORTED_TP |
6619                            SUPPORTED_Autoneg |
6620                            SUPPORTED_Pause |
6621                            SUPPORTED_Asym_Pause),
6622         .media_type     = ETH_PHY_UNSPECIFIED,
6623         .ver_addr       = 0,
6624         .req_flow_ctrl  = 0,
6625         .req_line_speed = 0,
6626         .speed_cap_mask = 0,
6627         .req_duplex     = 0,
6628         .rsrv           = 0,
6629         .config_init    = (config_init_t)bnx2x_init_serdes,
6630         .read_status    = (read_status_t)bnx2x_link_settings_status,
6631         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
6632         .config_loopback = (config_loopback_t)NULL,
6633         .format_fw_ver  = (format_fw_ver_t)NULL,
6634         .hw_reset       = (hw_reset_t)NULL,
6635         .set_link_led   = (set_link_led_t)NULL,
6636         .phy_specific_func = (phy_specific_func_t)NULL
6637 };
6638
6639 static struct bnx2x_phy phy_xgxs = {
6640         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
6641         .addr           = 0xff,
6642         .flags          = 0,
6643         .def_md_devad   = 0,
6644         .reserved       = 0,
6645         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6646         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6647         .mdio_ctrl      = 0,
6648         .supported      = (SUPPORTED_10baseT_Half |
6649                            SUPPORTED_10baseT_Full |
6650                            SUPPORTED_100baseT_Half |
6651                            SUPPORTED_100baseT_Full |
6652                            SUPPORTED_1000baseT_Full |
6653                            SUPPORTED_2500baseX_Full |
6654                            SUPPORTED_10000baseT_Full |
6655                            SUPPORTED_FIBRE |
6656                            SUPPORTED_Autoneg |
6657                            SUPPORTED_Pause |
6658                            SUPPORTED_Asym_Pause),
6659         .media_type     = ETH_PHY_UNSPECIFIED,
6660         .ver_addr       = 0,
6661         .req_flow_ctrl  = 0,
6662         .req_line_speed = 0,
6663         .speed_cap_mask = 0,
6664         .req_duplex     = 0,
6665         .rsrv           = 0,
6666         .config_init    = (config_init_t)bnx2x_init_xgxs,
6667         .read_status    = (read_status_t)bnx2x_link_settings_status,
6668         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
6669         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
6670         .format_fw_ver  = (format_fw_ver_t)NULL,
6671         .hw_reset       = (hw_reset_t)NULL,
6672         .set_link_led   = (set_link_led_t)NULL,
6673         .phy_specific_func = (phy_specific_func_t)NULL
6674 };
6675
6676 static struct bnx2x_phy phy_7101 = {
6677         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
6678         .addr           = 0xff,
6679         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
6680         .def_md_devad   = 0,
6681         .reserved       = 0,
6682         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6683         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6684         .mdio_ctrl      = 0,
6685         .supported      = (SUPPORTED_10000baseT_Full |
6686                            SUPPORTED_TP |
6687                            SUPPORTED_Autoneg |
6688                            SUPPORTED_Pause |
6689                            SUPPORTED_Asym_Pause),
6690         .media_type     = ETH_PHY_BASE_T,
6691         .ver_addr       = 0,
6692         .req_flow_ctrl  = 0,
6693         .req_line_speed = 0,
6694         .speed_cap_mask = 0,
6695         .req_duplex     = 0,
6696         .rsrv           = 0,
6697         .config_init    = (config_init_t)bnx2x_7101_config_init,
6698         .read_status    = (read_status_t)bnx2x_7101_read_status,
6699         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
6700         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
6701         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
6702         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
6703         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
6704         .phy_specific_func = (phy_specific_func_t)NULL
6705 };
6706 static struct bnx2x_phy phy_8073 = {
6707         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
6708         .addr           = 0xff,
6709         .flags          = FLAGS_HW_LOCK_REQUIRED,
6710         .def_md_devad   = 0,
6711         .reserved       = 0,
6712         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6713         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6714         .mdio_ctrl      = 0,
6715         .supported      = (SUPPORTED_10000baseT_Full |
6716                            SUPPORTED_2500baseX_Full |
6717                            SUPPORTED_1000baseT_Full |
6718                            SUPPORTED_FIBRE |
6719                            SUPPORTED_Autoneg |
6720                            SUPPORTED_Pause |
6721                            SUPPORTED_Asym_Pause),
6722         .media_type     = ETH_PHY_UNSPECIFIED,
6723         .ver_addr       = 0,
6724         .req_flow_ctrl  = 0,
6725         .req_line_speed = 0,
6726         .speed_cap_mask = 0,
6727         .req_duplex     = 0,
6728         .rsrv           = 0,
6729         .config_init    = (config_init_t)bnx2x_8073_config_init,
6730         .read_status    = (read_status_t)bnx2x_8073_read_status,
6731         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
6732         .config_loopback = (config_loopback_t)NULL,
6733         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
6734         .hw_reset       = (hw_reset_t)NULL,
6735         .set_link_led   = (set_link_led_t)NULL,
6736         .phy_specific_func = (phy_specific_func_t)NULL
6737 };
6738 static struct bnx2x_phy phy_8705 = {
6739         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
6740         .addr           = 0xff,
6741         .flags          = FLAGS_INIT_XGXS_FIRST,
6742         .def_md_devad   = 0,
6743         .reserved       = 0,
6744         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6745         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6746         .mdio_ctrl      = 0,
6747         .supported      = (SUPPORTED_10000baseT_Full |
6748                            SUPPORTED_FIBRE |
6749                            SUPPORTED_Pause |
6750                            SUPPORTED_Asym_Pause),
6751         .media_type     = ETH_PHY_XFP_FIBER,
6752         .ver_addr       = 0,
6753         .req_flow_ctrl  = 0,
6754         .req_line_speed = 0,
6755         .speed_cap_mask = 0,
6756         .req_duplex     = 0,
6757         .rsrv           = 0,
6758         .config_init    = (config_init_t)bnx2x_8705_config_init,
6759         .read_status    = (read_status_t)bnx2x_8705_read_status,
6760         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
6761         .config_loopback = (config_loopback_t)NULL,
6762         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
6763         .hw_reset       = (hw_reset_t)NULL,
6764         .set_link_led   = (set_link_led_t)NULL,
6765         .phy_specific_func = (phy_specific_func_t)NULL
6766 };
6767 static struct bnx2x_phy phy_8706 = {
6768         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
6769         .addr           = 0xff,
6770         .flags          = FLAGS_INIT_XGXS_FIRST,
6771         .def_md_devad   = 0,
6772         .reserved       = 0,
6773         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6774         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6775         .mdio_ctrl      = 0,
6776         .supported      = (SUPPORTED_10000baseT_Full |
6777                            SUPPORTED_1000baseT_Full |
6778                            SUPPORTED_FIBRE |
6779                            SUPPORTED_Pause |
6780                            SUPPORTED_Asym_Pause),
6781         .media_type     = ETH_PHY_SFP_FIBER,
6782         .ver_addr       = 0,
6783         .req_flow_ctrl  = 0,
6784         .req_line_speed = 0,
6785         .speed_cap_mask = 0,
6786         .req_duplex     = 0,
6787         .rsrv           = 0,
6788         .config_init    = (config_init_t)bnx2x_8706_config_init,
6789         .read_status    = (read_status_t)bnx2x_8706_read_status,
6790         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
6791         .config_loopback = (config_loopback_t)NULL,
6792         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
6793         .hw_reset       = (hw_reset_t)NULL,
6794         .set_link_led   = (set_link_led_t)NULL,
6795         .phy_specific_func = (phy_specific_func_t)NULL
6796 };
6797
6798 static struct bnx2x_phy phy_8726 = {
6799         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
6800         .addr           = 0xff,
6801         .flags          = (FLAGS_HW_LOCK_REQUIRED |
6802                            FLAGS_INIT_XGXS_FIRST),
6803         .def_md_devad   = 0,
6804         .reserved       = 0,
6805         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6806         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6807         .mdio_ctrl      = 0,
6808         .supported      = (SUPPORTED_10000baseT_Full |
6809                            SUPPORTED_1000baseT_Full |
6810                            SUPPORTED_Autoneg |
6811                            SUPPORTED_FIBRE |
6812                            SUPPORTED_Pause |
6813                            SUPPORTED_Asym_Pause),
6814         .media_type     = ETH_PHY_SFP_FIBER,
6815         .ver_addr       = 0,
6816         .req_flow_ctrl  = 0,
6817         .req_line_speed = 0,
6818         .speed_cap_mask = 0,
6819         .req_duplex     = 0,
6820         .rsrv           = 0,
6821         .config_init    = (config_init_t)bnx2x_8726_config_init,
6822         .read_status    = (read_status_t)bnx2x_8726_read_status,
6823         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
6824         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
6825         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
6826         .hw_reset       = (hw_reset_t)NULL,
6827         .set_link_led   = (set_link_led_t)NULL,
6828         .phy_specific_func = (phy_specific_func_t)NULL
6829 };
6830
6831 static struct bnx2x_phy phy_8727 = {
6832         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
6833         .addr           = 0xff,
6834         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
6835         .def_md_devad   = 0,
6836         .reserved       = 0,
6837         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6838         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6839         .mdio_ctrl      = 0,
6840         .supported      = (SUPPORTED_10000baseT_Full |
6841                            SUPPORTED_1000baseT_Full |
6842                            SUPPORTED_FIBRE |
6843                            SUPPORTED_Pause |
6844                            SUPPORTED_Asym_Pause),
6845         .media_type     = ETH_PHY_SFP_FIBER,
6846         .ver_addr       = 0,
6847         .req_flow_ctrl  = 0,
6848         .req_line_speed = 0,
6849         .speed_cap_mask = 0,
6850         .req_duplex     = 0,
6851         .rsrv           = 0,
6852         .config_init    = (config_init_t)bnx2x_8727_config_init,
6853         .read_status    = (read_status_t)bnx2x_8727_read_status,
6854         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
6855         .config_loopback = (config_loopback_t)NULL,
6856         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
6857         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
6858         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
6859         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
6860 };
6861 static struct bnx2x_phy phy_8481 = {
6862         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
6863         .addr           = 0xff,
6864         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
6865                           FLAGS_REARM_LATCH_SIGNAL,
6866         .def_md_devad   = 0,
6867         .reserved       = 0,
6868         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6869         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6870         .mdio_ctrl      = 0,
6871         .supported      = (SUPPORTED_10baseT_Half |
6872                            SUPPORTED_10baseT_Full |
6873                            SUPPORTED_100baseT_Half |
6874                            SUPPORTED_100baseT_Full |
6875                            SUPPORTED_1000baseT_Full |
6876                            SUPPORTED_10000baseT_Full |
6877                            SUPPORTED_TP |
6878                            SUPPORTED_Autoneg |
6879                            SUPPORTED_Pause |
6880                            SUPPORTED_Asym_Pause),
6881         .media_type     = ETH_PHY_BASE_T,
6882         .ver_addr       = 0,
6883         .req_flow_ctrl  = 0,
6884         .req_line_speed = 0,
6885         .speed_cap_mask = 0,
6886         .req_duplex     = 0,
6887         .rsrv           = 0,
6888         .config_init    = (config_init_t)bnx2x_8481_config_init,
6889         .read_status    = (read_status_t)bnx2x_848xx_read_status,
6890         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
6891         .config_loopback = (config_loopback_t)NULL,
6892         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
6893         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
6894         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
6895         .phy_specific_func = (phy_specific_func_t)NULL
6896 };
6897
6898 static struct bnx2x_phy phy_84823 = {
6899         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
6900         .addr           = 0xff,
6901         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
6902                           FLAGS_REARM_LATCH_SIGNAL,
6903         .def_md_devad   = 0,
6904         .reserved       = 0,
6905         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6906         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
6907         .mdio_ctrl      = 0,
6908         .supported      = (SUPPORTED_10baseT_Half |
6909                            SUPPORTED_10baseT_Full |
6910                            SUPPORTED_100baseT_Half |
6911                            SUPPORTED_100baseT_Full |
6912                            SUPPORTED_1000baseT_Full |
6913                            SUPPORTED_10000baseT_Full |
6914                            SUPPORTED_TP |
6915                            SUPPORTED_Autoneg |
6916                            SUPPORTED_Pause |
6917                            SUPPORTED_Asym_Pause),
6918         .media_type     = ETH_PHY_BASE_T,
6919         .ver_addr       = 0,
6920         .req_flow_ctrl  = 0,
6921         .req_line_speed = 0,
6922         .speed_cap_mask = 0,
6923         .req_duplex     = 0,
6924         .rsrv           = 0,
6925         .config_init    = (config_init_t)bnx2x_848x3_config_init,
6926         .read_status    = (read_status_t)bnx2x_848xx_read_status,
6927         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
6928         .config_loopback = (config_loopback_t)NULL,
6929         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
6930         .hw_reset       = (hw_reset_t)NULL,
6931         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
6932         .phy_specific_func = (phy_specific_func_t)NULL
6933 };
6934
6935 /*****************************************************************/
6936 /*                                                               */
6937 /* Populate the phy according. Main function: bnx2x_populate_phy   */
6938 /*                                                               */
6939 /*****************************************************************/
6940
6941 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
6942                                      struct bnx2x_phy *phy, u8 port,
6943                                      u8 phy_index)
6944 {
6945         /* Get the 4 lanes xgxs config rx and tx */
6946         u32 rx = 0, tx = 0, i;
6947         for (i = 0; i < 2; i++) {
6948                 /**
6949                  * INT_PHY and EXT_PHY1 share the same value location in the
6950                  * shmem. When num_phys is greater than 1, than this value
6951                  * applies only to EXT_PHY1
6952                  */
6953                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
6954                         rx = REG_RD(bp, shmem_base +
6955                                     offsetof(struct shmem_region,
6956                            dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
6957
6958                         tx = REG_RD(bp, shmem_base +
6959                                     offsetof(struct shmem_region,
6960                            dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
6961                 } else {
6962                         rx = REG_RD(bp, shmem_base +
6963                                     offsetof(struct shmem_region,
6964                           dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
6965
6966                         tx = REG_RD(bp, shmem_base +
6967                                     offsetof(struct shmem_region,
6968                           dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
6969                 }
6970
6971                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
6972                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
6973
6974                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
6975                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
6976         }
6977 }
6978
6979 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
6980                                     u8 phy_index, u8 port)
6981 {
6982         u32 ext_phy_config = 0;
6983         switch (phy_index) {
6984         case EXT_PHY1:
6985                 ext_phy_config = REG_RD(bp, shmem_base +
6986                                               offsetof(struct shmem_region,
6987                         dev_info.port_hw_config[port].external_phy_config));
6988                 break;
6989         case EXT_PHY2:
6990                 ext_phy_config = REG_RD(bp, shmem_base +
6991                                               offsetof(struct shmem_region,
6992                         dev_info.port_hw_config[port].external_phy_config2));
6993                 break;
6994         default:
6995                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
6996                 return -EINVAL;
6997         }
6998
6999         return ext_phy_config;
7000 }
7001 static u8 bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
7002                                  struct bnx2x_phy *phy)
7003 {
7004         u32 phy_addr;
7005         u32 chip_id;
7006         u32 switch_cfg = (REG_RD(bp, shmem_base +
7007                                        offsetof(struct shmem_region,
7008                         dev_info.port_feature_config[port].link_config)) &
7009                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
7010         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
7011         switch (switch_cfg) {
7012         case SWITCH_CFG_1G:
7013                 phy_addr = REG_RD(bp,
7014                                         NIG_REG_SERDES0_CTRL_PHY_ADDR +
7015                                         port * 0x10);
7016                 *phy = phy_serdes;
7017                 break;
7018         case SWITCH_CFG_10G:
7019                 phy_addr = REG_RD(bp,
7020                                         NIG_REG_XGXS0_CTRL_PHY_ADDR +
7021                                         port * 0x18);
7022                 *phy = phy_xgxs;
7023                 break;
7024         default:
7025                 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
7026                 return -EINVAL;
7027         }
7028         phy->addr = (u8)phy_addr;
7029         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
7030                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
7031                                             port);
7032         if (CHIP_IS_E2(bp))
7033                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
7034         else
7035                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
7036
7037         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
7038                    port, phy->addr, phy->mdio_ctrl);
7039
7040         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
7041         return 0;
7042 }
7043
7044 static u8 bnx2x_populate_ext_phy(struct bnx2x *bp,
7045                                  u8 phy_index,
7046                                  u32 shmem_base,
7047                                  u32 shmem2_base,
7048                                  u8 port,
7049                                  struct bnx2x_phy *phy)
7050 {
7051         u32 ext_phy_config, phy_type, config2;
7052         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
7053         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
7054                                                   phy_index, port);
7055         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7056         /* Select the phy type */
7057         switch (phy_type) {
7058         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7059                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
7060                 *phy = phy_8073;
7061                 break;
7062         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
7063                 *phy = phy_8705;
7064                 break;
7065         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
7066                 *phy = phy_8706;
7067                 break;
7068         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7069                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7070                 *phy = phy_8726;
7071                 break;
7072         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7073                 /* BCM8727_NOC => BCM8727 no over current */
7074                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7075                 *phy = phy_8727;
7076                 phy->flags |= FLAGS_NOC;
7077                 break;
7078         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7079                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
7080                 *phy = phy_8727;
7081                 break;
7082         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
7083                 *phy = phy_8481;
7084                 break;
7085         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
7086                 *phy = phy_84823;
7087                 break;
7088         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
7089                 *phy = phy_7101;
7090                 break;
7091         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7092                 *phy = phy_null;
7093                 return -EINVAL;
7094         default:
7095                 *phy = phy_null;
7096                 return 0;
7097         }
7098
7099         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
7100         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
7101
7102         /**
7103         * The shmem address of the phy version is located on different
7104         * structures. In case this structure is too old, do not set
7105         * the address
7106         */
7107         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
7108                                         dev_info.shared_hw_config.config2));
7109         if (phy_index == EXT_PHY1) {
7110                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
7111                                 port_mb[port].ext_phy_fw_version);
7112
7113         /* Check specific mdc mdio settings */
7114         if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
7115                 mdc_mdio_access = config2 &
7116                 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
7117         } else {
7118                 u32 size = REG_RD(bp, shmem2_base);
7119
7120                 if (size >
7121                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
7122                         phy->ver_addr = shmem2_base +
7123                             offsetof(struct shmem2_region,
7124                                      ext_phy_fw_version2[port]);
7125                 }
7126                 /* Check specific mdc mdio settings */
7127                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
7128                         mdc_mdio_access = (config2 &
7129                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
7130                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
7131                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
7132         }
7133         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
7134
7135         /**
7136          * In case mdc/mdio_access of the external phy is different than the
7137          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
7138          * to prevent one port interfere with another port's CL45 operations.
7139          */
7140         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
7141                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
7142         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
7143                    phy_type, port, phy_index);
7144         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
7145                    phy->addr, phy->mdio_ctrl);
7146         return 0;
7147 }
7148
7149 static u8 bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
7150                              u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
7151 {
7152         u8 status = 0;
7153         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
7154         if (phy_index == INT_PHY)
7155                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
7156         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
7157                                         port, phy);
7158         return status;
7159 }
7160
7161 static void bnx2x_phy_def_cfg(struct link_params *params,
7162                               struct bnx2x_phy *phy,
7163                               u8 phy_index)
7164 {
7165         struct bnx2x *bp = params->bp;
7166         u32 link_config;
7167         /* Populate the default phy configuration for MF mode */
7168         if (phy_index == EXT_PHY2) {
7169                 link_config = REG_RD(bp, params->shmem_base +
7170                                          offsetof(struct shmem_region, dev_info.
7171                         port_feature_config[params->port].link_config2));
7172                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7173                                         offsetof(struct shmem_region, dev_info.
7174                         port_hw_config[params->port].speed_capability_mask2));
7175         } else {
7176                 link_config = REG_RD(bp, params->shmem_base +
7177                                 offsetof(struct shmem_region, dev_info.
7178                                 port_feature_config[params->port].link_config));
7179                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
7180                                 offsetof(struct shmem_region, dev_info.
7181                            port_hw_config[params->port].speed_capability_mask));
7182         }
7183         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
7184                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
7185
7186         phy->req_duplex = DUPLEX_FULL;
7187         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
7188         case PORT_FEATURE_LINK_SPEED_10M_HALF:
7189                 phy->req_duplex = DUPLEX_HALF;
7190         case PORT_FEATURE_LINK_SPEED_10M_FULL:
7191                 phy->req_line_speed = SPEED_10;
7192                 break;
7193         case PORT_FEATURE_LINK_SPEED_100M_HALF:
7194                 phy->req_duplex = DUPLEX_HALF;
7195         case PORT_FEATURE_LINK_SPEED_100M_FULL:
7196                 phy->req_line_speed = SPEED_100;
7197                 break;
7198         case PORT_FEATURE_LINK_SPEED_1G:
7199                 phy->req_line_speed = SPEED_1000;
7200                 break;
7201         case PORT_FEATURE_LINK_SPEED_2_5G:
7202                 phy->req_line_speed = SPEED_2500;
7203                 break;
7204         case PORT_FEATURE_LINK_SPEED_10G_CX4:
7205                 phy->req_line_speed = SPEED_10000;
7206                 break;
7207         default:
7208                 phy->req_line_speed = SPEED_AUTO_NEG;
7209                 break;
7210         }
7211
7212         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
7213         case PORT_FEATURE_FLOW_CONTROL_AUTO:
7214                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
7215                 break;
7216         case PORT_FEATURE_FLOW_CONTROL_TX:
7217                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
7218                 break;
7219         case PORT_FEATURE_FLOW_CONTROL_RX:
7220                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
7221                 break;
7222         case PORT_FEATURE_FLOW_CONTROL_BOTH:
7223                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
7224                 break;
7225         default:
7226                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7227                 break;
7228         }
7229 }
7230
7231 u32 bnx2x_phy_selection(struct link_params *params)
7232 {
7233         u32 phy_config_swapped, prio_cfg;
7234         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
7235
7236         phy_config_swapped = params->multi_phy_config &
7237                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7238
7239         prio_cfg = params->multi_phy_config &
7240                         PORT_HW_CFG_PHY_SELECTION_MASK;
7241
7242         if (phy_config_swapped) {
7243                 switch (prio_cfg) {
7244                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7245                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
7246                      break;
7247                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7248                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
7249                      break;
7250                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
7251                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
7252                      break;
7253                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
7254                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
7255                      break;
7256                 }
7257         } else
7258                 return_cfg = prio_cfg;
7259
7260         return return_cfg;
7261 }
7262
7263
7264 u8 bnx2x_phy_probe(struct link_params *params)
7265 {
7266         u8 phy_index, actual_phy_idx, link_cfg_idx;
7267         u32 phy_config_swapped;
7268         struct bnx2x *bp = params->bp;
7269         struct bnx2x_phy *phy;
7270         params->num_phys = 0;
7271         DP(NETIF_MSG_LINK, "Begin phy probe\n");
7272         phy_config_swapped = params->multi_phy_config &
7273                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7274
7275         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7276               phy_index++) {
7277                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7278                 actual_phy_idx = phy_index;
7279                 if (phy_config_swapped) {
7280                         if (phy_index == EXT_PHY1)
7281                                 actual_phy_idx = EXT_PHY2;
7282                         else if (phy_index == EXT_PHY2)
7283                                 actual_phy_idx = EXT_PHY1;
7284                 }
7285                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
7286                                " actual_phy_idx %x\n", phy_config_swapped,
7287                            phy_index, actual_phy_idx);
7288                 phy = &params->phy[actual_phy_idx];
7289                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
7290                                        params->shmem2_base, params->port,
7291                                        phy) != 0) {
7292                         params->num_phys = 0;
7293                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
7294                                    phy_index);
7295                         for (phy_index = INT_PHY;
7296                               phy_index < MAX_PHYS;
7297                               phy_index++)
7298                                 *phy = phy_null;
7299                         return -EINVAL;
7300                 }
7301                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
7302                         break;
7303
7304                 bnx2x_phy_def_cfg(params, phy, phy_index);
7305                 params->num_phys++;
7306         }
7307
7308         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
7309         return 0;
7310 }
7311
7312 static void set_phy_vars(struct link_params *params)
7313 {
7314         struct bnx2x *bp = params->bp;
7315         u8 actual_phy_idx, phy_index, link_cfg_idx;
7316         u8 phy_config_swapped = params->multi_phy_config &
7317                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
7318         for (phy_index = INT_PHY; phy_index < params->num_phys;
7319               phy_index++) {
7320                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
7321                 actual_phy_idx = phy_index;
7322                 if (phy_config_swapped) {
7323                         if (phy_index == EXT_PHY1)
7324                                 actual_phy_idx = EXT_PHY2;
7325                         else if (phy_index == EXT_PHY2)
7326                                 actual_phy_idx = EXT_PHY1;
7327                 }
7328                 params->phy[actual_phy_idx].req_flow_ctrl  =
7329                         params->req_flow_ctrl[link_cfg_idx];
7330
7331                 params->phy[actual_phy_idx].req_line_speed =
7332                         params->req_line_speed[link_cfg_idx];
7333
7334                 params->phy[actual_phy_idx].speed_cap_mask =
7335                         params->speed_cap_mask[link_cfg_idx];
7336
7337                 params->phy[actual_phy_idx].req_duplex =
7338                         params->req_duplex[link_cfg_idx];
7339
7340                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
7341                            " speed_cap_mask %x\n",
7342                            params->phy[actual_phy_idx].req_flow_ctrl,
7343                            params->phy[actual_phy_idx].req_line_speed,
7344                            params->phy[actual_phy_idx].speed_cap_mask);
7345         }
7346 }
7347
7348 u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
7349 {
7350         struct bnx2x *bp = params->bp;
7351         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
7352         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
7353                    params->req_line_speed[0], params->req_flow_ctrl[0]);
7354         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
7355                    params->req_line_speed[1], params->req_flow_ctrl[1]);
7356         vars->link_status = 0;
7357         vars->phy_link_up = 0;
7358         vars->link_up = 0;
7359         vars->line_speed = 0;
7360         vars->duplex = DUPLEX_FULL;
7361         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7362         vars->mac_type = MAC_TYPE_NONE;
7363         vars->phy_flags = 0;
7364
7365         /* disable attentions */
7366         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
7367                        (NIG_MASK_XGXS0_LINK_STATUS |
7368                         NIG_MASK_XGXS0_LINK10G |
7369                         NIG_MASK_SERDES0_LINK_STATUS |
7370                         NIG_MASK_MI_INT));
7371
7372         bnx2x_emac_init(params, vars);
7373
7374         if (params->num_phys == 0) {
7375                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
7376                 return -EINVAL;
7377         }
7378         set_phy_vars(params);
7379
7380         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
7381         if (CHIP_REV_IS_FPGA(bp)) {
7382
7383                 vars->link_up = 1;
7384                 vars->line_speed = SPEED_10000;
7385                 vars->duplex = DUPLEX_FULL;
7386                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7387                 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
7388                 /* enable on E1.5 FPGA */
7389                 if (CHIP_IS_E1H(bp)) {
7390                         vars->flow_ctrl |=
7391                                         (BNX2X_FLOW_CTRL_TX |
7392                                          BNX2X_FLOW_CTRL_RX);
7393                         vars->link_status |=
7394                                         (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
7395                                          LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
7396                 }
7397
7398                 bnx2x_emac_enable(params, vars, 0);
7399                 if (!(CHIP_IS_E2(bp)))
7400                         bnx2x_pbf_update(params, vars->flow_ctrl,
7401                                          vars->line_speed);
7402                 /* disable drain */
7403                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
7404
7405                 /* update shared memory */
7406                 bnx2x_update_mng(params, vars->link_status);
7407
7408                 return 0;
7409
7410         } else
7411         if (CHIP_REV_IS_EMUL(bp)) {
7412
7413                 vars->link_up = 1;
7414                 vars->line_speed = SPEED_10000;
7415                 vars->duplex = DUPLEX_FULL;
7416                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7417                 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
7418
7419                 bnx2x_bmac_enable(params, vars, 0);
7420
7421                 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
7422                 /* Disable drain */
7423                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
7424                                     + params->port*4, 0);
7425
7426                 /* update shared memory */
7427                 bnx2x_update_mng(params, vars->link_status);
7428
7429                 return 0;
7430
7431         } else
7432         if (params->loopback_mode == LOOPBACK_BMAC) {
7433
7434                 vars->link_up = 1;
7435                 vars->line_speed = SPEED_10000;
7436                 vars->duplex = DUPLEX_FULL;
7437                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7438                 vars->mac_type = MAC_TYPE_BMAC;
7439
7440                 vars->phy_flags = PHY_XGXS_FLAG;
7441
7442                 bnx2x_xgxs_deassert(params);
7443
7444                 /* set bmac loopback */
7445                 bnx2x_bmac_enable(params, vars, 1);
7446
7447                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7448                     params->port*4, 0);
7449
7450         } else if (params->loopback_mode == LOOPBACK_EMAC) {
7451
7452                 vars->link_up = 1;
7453                 vars->line_speed = SPEED_1000;
7454                 vars->duplex = DUPLEX_FULL;
7455                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7456                 vars->mac_type = MAC_TYPE_EMAC;
7457
7458                 vars->phy_flags = PHY_XGXS_FLAG;
7459
7460                 bnx2x_xgxs_deassert(params);
7461                 /* set bmac loopback */
7462                 bnx2x_emac_enable(params, vars, 1);
7463                 bnx2x_emac_program(params, vars);
7464                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7465                     params->port*4, 0);
7466
7467         } else if ((params->loopback_mode == LOOPBACK_XGXS) ||
7468                    (params->loopback_mode == LOOPBACK_EXT_PHY)) {
7469
7470                 vars->link_up = 1;
7471                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
7472                 vars->duplex = DUPLEX_FULL;
7473                 if (params->req_line_speed[0] == SPEED_1000) {
7474                         vars->line_speed = SPEED_1000;
7475                         vars->mac_type = MAC_TYPE_EMAC;
7476                 } else {
7477                         vars->line_speed = SPEED_10000;
7478                         vars->mac_type = MAC_TYPE_BMAC;
7479                 }
7480
7481                 bnx2x_xgxs_deassert(params);
7482                 bnx2x_link_initialize(params, vars);
7483
7484                 if (params->req_line_speed[0] == SPEED_1000) {
7485                         bnx2x_emac_program(params, vars);
7486                         bnx2x_emac_enable(params, vars, 0);
7487                 } else
7488                 bnx2x_bmac_enable(params, vars, 0);
7489
7490                 if (params->loopback_mode == LOOPBACK_XGXS) {
7491                         /* set 10G XGXS loopback */
7492                         params->phy[INT_PHY].config_loopback(
7493                                 &params->phy[INT_PHY],
7494                                 params);
7495
7496                 } else {
7497                         /* set external phy loopback */
7498                         u8 phy_index;
7499                         for (phy_index = EXT_PHY1;
7500                               phy_index < params->num_phys; phy_index++) {
7501                                 if (params->phy[phy_index].config_loopback)
7502                                         params->phy[phy_index].config_loopback(
7503                                                 &params->phy[phy_index],
7504                                                 params);
7505                         }
7506                 }
7507
7508                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
7509                             params->port*4, 0);
7510
7511                 bnx2x_set_led(params, vars,
7512                               LED_MODE_OPER, vars->line_speed);
7513         } else
7514         /* No loopback */
7515         {
7516                 if (params->switch_cfg == SWITCH_CFG_10G)
7517                         bnx2x_xgxs_deassert(params);
7518                 else
7519                         bnx2x_serdes_deassert(bp, params->port);
7520
7521                 bnx2x_link_initialize(params, vars);
7522                 msleep(30);
7523                 bnx2x_link_int_enable(params);
7524         }
7525         return 0;
7526 }
7527 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
7528                   u8 reset_ext_phy)
7529 {
7530         struct bnx2x *bp = params->bp;
7531         u8 phy_index, port = params->port, clear_latch_ind = 0;
7532         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
7533         /* disable attentions */
7534         vars->link_status = 0;
7535         bnx2x_update_mng(params, vars->link_status);
7536         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
7537                      (NIG_MASK_XGXS0_LINK_STATUS |
7538                       NIG_MASK_XGXS0_LINK10G |
7539                       NIG_MASK_SERDES0_LINK_STATUS |
7540                       NIG_MASK_MI_INT));
7541
7542         /* activate nig drain */
7543         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7544
7545         /* disable nig egress interface */
7546         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7547         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7548
7549         /* Stop BigMac rx */
7550         bnx2x_bmac_rx_disable(bp, port);
7551
7552         /* disable emac */
7553         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7554
7555         msleep(10);
7556         /* The PHY reset is controled by GPIO 1
7557          * Hold it as vars low
7558          */
7559          /* clear link led */
7560         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
7561
7562         if (reset_ext_phy) {
7563                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7564                       phy_index++) {
7565                         if (params->phy[phy_index].link_reset)
7566                                 params->phy[phy_index].link_reset(
7567                                         &params->phy[phy_index],
7568                                         params);
7569                         if (params->phy[phy_index].flags &
7570                             FLAGS_REARM_LATCH_SIGNAL)
7571                                 clear_latch_ind = 1;
7572                 }
7573         }
7574
7575         if (clear_latch_ind) {
7576                 /* Clear latching indication */
7577                 bnx2x_rearm_latch_signal(bp, port, 0);
7578                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
7579                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
7580         }
7581         if (params->phy[INT_PHY].link_reset)
7582                 params->phy[INT_PHY].link_reset(
7583                         &params->phy[INT_PHY], params);
7584         /* reset BigMac */
7585         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7586                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
7587
7588         /* disable nig ingress interface */
7589         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
7590         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
7591         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
7592         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
7593         vars->link_up = 0;
7594         return 0;
7595 }
7596
7597 /****************************************************************************/
7598 /*                              Common function                             */
7599 /****************************************************************************/
7600 static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
7601                                      u32 shmem_base_path[],
7602                                      u32 shmem2_base_path[], u8 phy_index,
7603                                      u32 chip_id)
7604 {
7605         struct bnx2x_phy phy[PORT_MAX];
7606         struct bnx2x_phy *phy_blk[PORT_MAX];
7607         u16 val;
7608         s8 port;
7609         s8 port_of_path = 0;
7610
7611         bnx2x_ext_phy_hw_reset(bp, 0);
7612         /* PART1 - Reset both phys */
7613         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7614                 u32 shmem_base, shmem2_base;
7615                 /* In E2, same phy is using for port0 of the two paths */
7616                 if (CHIP_IS_E2(bp)) {
7617                         shmem_base = shmem_base_path[port];
7618                         shmem2_base = shmem2_base_path[port];
7619                         port_of_path = 0;
7620                 } else {
7621                         shmem_base = shmem_base_path[0];
7622                         shmem2_base = shmem2_base_path[0];
7623                         port_of_path = port;
7624                 }
7625
7626                 /* Extract the ext phy address for the port */
7627                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7628                                        port_of_path, &phy[port]) !=
7629                     0) {
7630                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
7631                         return -EINVAL;
7632                 }
7633                 /* disable attentions */
7634                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7635                                port_of_path*4,
7636                              (NIG_MASK_XGXS0_LINK_STATUS |
7637                               NIG_MASK_XGXS0_LINK10G |
7638                               NIG_MASK_SERDES0_LINK_STATUS |
7639                               NIG_MASK_MI_INT));
7640
7641                 /* Need to take the phy out of low power mode in order
7642                         to write to access its registers */
7643                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7644                                   MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7645
7646                 /* Reset the phy */
7647                 bnx2x_cl45_write(bp, &phy[port],
7648                                MDIO_PMA_DEVAD,
7649                                MDIO_PMA_REG_CTRL,
7650                                1<<15);
7651         }
7652
7653         /* Add delay of 150ms after reset */
7654         msleep(150);
7655
7656         if (phy[PORT_0].addr & 0x1) {
7657                 phy_blk[PORT_0] = &(phy[PORT_1]);
7658                 phy_blk[PORT_1] = &(phy[PORT_0]);
7659         } else {
7660                 phy_blk[PORT_0] = &(phy[PORT_0]);
7661                 phy_blk[PORT_1] = &(phy[PORT_1]);
7662         }
7663
7664         /* PART2 - Download firmware to both phys */
7665         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7666                 u16 fw_ver1;
7667                 if (CHIP_IS_E2(bp))
7668                         port_of_path = 0;
7669                 else
7670                         port_of_path = port;
7671
7672                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7673                            phy_blk[port]->addr);
7674                 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7675                                                   port_of_path);
7676
7677                 bnx2x_cl45_read(bp, phy_blk[port],
7678                               MDIO_PMA_DEVAD,
7679                               MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7680                 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7681                         DP(NETIF_MSG_LINK,
7682                                  "bnx2x_8073_common_init_phy port %x:"
7683                                  "Download failed. fw version = 0x%x\n",
7684                                  port, fw_ver1);
7685                         return -EINVAL;
7686                 }
7687
7688                 /* Only set bit 10 = 1 (Tx power down) */
7689                 bnx2x_cl45_read(bp, phy_blk[port],
7690                               MDIO_PMA_DEVAD,
7691                               MDIO_PMA_REG_TX_POWER_DOWN, &val);
7692
7693                 /* Phase1 of TX_POWER_DOWN reset */
7694                 bnx2x_cl45_write(bp, phy_blk[port],
7695                                MDIO_PMA_DEVAD,
7696                                MDIO_PMA_REG_TX_POWER_DOWN,
7697                                (val | 1<<10));
7698         }
7699
7700         /* Toggle Transmitter: Power down and then up with 600ms
7701            delay between */
7702         msleep(600);
7703
7704         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
7705         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7706                 /* Phase2 of POWER_DOWN_RESET */
7707                 /* Release bit 10 (Release Tx power down) */
7708                 bnx2x_cl45_read(bp, phy_blk[port],
7709                               MDIO_PMA_DEVAD,
7710                               MDIO_PMA_REG_TX_POWER_DOWN, &val);
7711
7712                 bnx2x_cl45_write(bp, phy_blk[port],
7713                                MDIO_PMA_DEVAD,
7714                                MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
7715                 msleep(15);
7716
7717                 /* Read modify write the SPI-ROM version select register */
7718                 bnx2x_cl45_read(bp, phy_blk[port],
7719                               MDIO_PMA_DEVAD,
7720                               MDIO_PMA_REG_EDC_FFE_MAIN, &val);
7721                 bnx2x_cl45_write(bp, phy_blk[port],
7722                               MDIO_PMA_DEVAD,
7723                               MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
7724
7725                 /* set GPIO2 back to LOW */
7726                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7727                                   MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7728         }
7729         return 0;
7730 }
7731 static u8 bnx2x_8726_common_init_phy(struct bnx2x *bp,
7732                                      u32 shmem_base_path[],
7733                                      u32 shmem2_base_path[], u8 phy_index,
7734                                      u32 chip_id)
7735 {
7736         u32 val;
7737         s8 port;
7738         struct bnx2x_phy phy;
7739         /* Use port1 because of the static port-swap */
7740         /* Enable the module detection interrupt */
7741         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
7742         val |= ((1<<MISC_REGISTERS_GPIO_3)|
7743                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
7744         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
7745
7746         bnx2x_ext_phy_hw_reset(bp, 0);
7747         msleep(5);
7748         for (port = 0; port < PORT_MAX; port++) {
7749                 u32 shmem_base, shmem2_base;
7750
7751                 /* In E2, same phy is using for port0 of the two paths */
7752                 if (CHIP_IS_E2(bp)) {
7753                         shmem_base = shmem_base_path[port];
7754                         shmem2_base = shmem2_base_path[port];
7755                 } else {
7756                         shmem_base = shmem_base_path[0];
7757                         shmem2_base = shmem2_base_path[0];
7758                 }
7759                 /* Extract the ext phy address for the port */
7760                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7761                                        port, &phy) !=
7762                     0) {
7763                         DP(NETIF_MSG_LINK, "populate phy failed\n");
7764                         return -EINVAL;
7765                 }
7766
7767                 /* Reset phy*/
7768                 bnx2x_cl45_write(bp, &phy,
7769                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
7770
7771
7772                 /* Set fault module detected LED on */
7773                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
7774                                   MISC_REGISTERS_GPIO_HIGH,
7775                                   port);
7776         }
7777
7778         return 0;
7779 }
7780 static u8 bnx2x_8727_common_init_phy(struct bnx2x *bp,
7781                                      u32 shmem_base_path[],
7782                                      u32 shmem2_base_path[], u8 phy_index,
7783                                      u32 chip_id)
7784 {
7785         s8 port;
7786         u32 swap_val, swap_override;
7787         struct bnx2x_phy phy[PORT_MAX];
7788         struct bnx2x_phy *phy_blk[PORT_MAX];
7789         s8 port_of_path;
7790         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
7791         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
7792
7793         port = 1;
7794
7795         bnx2x_ext_phy_hw_reset(bp, port ^ (swap_val && swap_override));
7796
7797         /* Calculate the port based on port swap */
7798         port ^= (swap_val && swap_override);
7799
7800         msleep(5);
7801
7802         /* PART1 - Reset both phys */
7803         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7804                 u32 shmem_base, shmem2_base;
7805
7806                 /* In E2, same phy is using for port0 of the two paths */
7807                 if (CHIP_IS_E2(bp)) {
7808                         shmem_base = shmem_base_path[port];
7809                         shmem2_base = shmem2_base_path[port];
7810                         port_of_path = 0;
7811                 } else {
7812                         shmem_base = shmem_base_path[0];
7813                         shmem2_base = shmem2_base_path[0];
7814                         port_of_path = port;
7815                 }
7816
7817                 /* Extract the ext phy address for the port */
7818                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7819                                        port_of_path, &phy[port]) !=
7820                                        0) {
7821                         DP(NETIF_MSG_LINK, "populate phy failed\n");
7822                         return -EINVAL;
7823                 }
7824                 /* disable attentions */
7825                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
7826                                port_of_path*4,
7827                                (NIG_MASK_XGXS0_LINK_STATUS |
7828                                 NIG_MASK_XGXS0_LINK10G |
7829                                 NIG_MASK_SERDES0_LINK_STATUS |
7830                                 NIG_MASK_MI_INT));
7831
7832
7833                 /* Reset the phy */
7834                 bnx2x_cl45_write(bp, &phy[port],
7835                                MDIO_PMA_DEVAD,
7836                                MDIO_PMA_REG_CTRL,
7837                                1<<15);
7838         }
7839
7840         /* Add delay of 150ms after reset */
7841         msleep(150);
7842         if (phy[PORT_0].addr & 0x1) {
7843                 phy_blk[PORT_0] = &(phy[PORT_1]);
7844                 phy_blk[PORT_1] = &(phy[PORT_0]);
7845         } else {
7846                 phy_blk[PORT_0] = &(phy[PORT_0]);
7847                 phy_blk[PORT_1] = &(phy[PORT_1]);
7848         }
7849         /* PART2 - Download firmware to both phys */
7850         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
7851                 u16 fw_ver1;
7852                  if (CHIP_IS_E2(bp))
7853                         port_of_path = 0;
7854                 else
7855                         port_of_path = port;
7856                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
7857                            phy_blk[port]->addr);
7858                 bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
7859                                                   port_of_path);
7860                 bnx2x_cl45_read(bp, phy_blk[port],
7861                               MDIO_PMA_DEVAD,
7862                               MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7863                 if (fw_ver1 == 0 || fw_ver1 == 0x4321) {
7864                         DP(NETIF_MSG_LINK,
7865                                  "bnx2x_8727_common_init_phy port %x:"
7866                                  "Download failed. fw version = 0x%x\n",
7867                                  port, fw_ver1);
7868                         return -EINVAL;
7869                 }
7870         }
7871
7872         return 0;
7873 }
7874
7875 static u8 bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
7876                                     u32 shmem2_base_path[], u8 phy_index,
7877                                     u32 ext_phy_type, u32 chip_id)
7878 {
7879         u8 rc = 0;
7880
7881         switch (ext_phy_type) {
7882         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
7883                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
7884                                                 shmem2_base_path,
7885                                                 phy_index, chip_id);
7886                 break;
7887
7888         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7889         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
7890                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
7891                                                 shmem2_base_path,
7892                                                 phy_index, chip_id);
7893                 break;
7894
7895         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7896                 /* GPIO1 affects both ports, so there's need to pull
7897                 it for single port alone */
7898                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
7899                                                 shmem2_base_path,
7900                                                 phy_index, chip_id);
7901                 break;
7902         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
7903                 rc = -EINVAL;
7904                 break;
7905         default:
7906                 DP(NETIF_MSG_LINK,
7907                          "bnx2x_common_init_phy: ext_phy 0x%x not required\n",
7908                          ext_phy_type);
7909                 break;
7910         }
7911
7912         return rc;
7913 }
7914
7915 u8 bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
7916                          u32 shmem2_base_path[], u32 chip_id)
7917 {
7918         u8 rc = 0;
7919         u8 phy_index;
7920         u32 ext_phy_type, ext_phy_config;
7921         DP(NETIF_MSG_LINK, "Begin common phy init\n");
7922
7923         if (CHIP_REV_IS_EMUL(bp))
7924                 return 0;
7925
7926         /* Read the ext_phy_type for arbitrary port(0) */
7927         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
7928               phy_index++) {
7929                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
7930                                                           shmem_base_path[0],
7931                                                           phy_index, 0);
7932                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
7933                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
7934                                                 shmem2_base_path,
7935                                                 phy_index, ext_phy_type,
7936                                                 chip_id);
7937         }
7938         return rc;
7939 }
7940
7941 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
7942 {
7943         u8 phy_index;
7944         struct bnx2x_phy phy;
7945         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
7946               phy_index++) {
7947                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7948                                        0, &phy) != 0) {
7949                         DP(NETIF_MSG_LINK, "populate phy failed\n");
7950                         return 0;
7951                 }
7952
7953                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
7954                         return 1;
7955         }
7956         return 0;
7957 }
7958
7959 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
7960                              u32 shmem_base,
7961                              u32 shmem2_base,
7962                              u8 port)
7963 {
7964         u8 phy_index, fan_failure_det_req = 0;
7965         struct bnx2x_phy phy;
7966         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
7967               phy_index++) {
7968                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
7969                                        port, &phy)
7970                     != 0) {
7971                         DP(NETIF_MSG_LINK, "populate phy failed\n");
7972                         return 0;
7973                 }
7974                 fan_failure_det_req |= (phy.flags &
7975                                         FLAGS_FAN_FAILURE_DET_REQ);
7976         }
7977         return fan_failure_det_req;
7978 }
7979
7980 void bnx2x_hw_reset_phy(struct link_params *params)
7981 {
7982         u8 phy_index;
7983         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
7984               phy_index++) {
7985                 if (params->phy[phy_index].hw_reset) {
7986                         params->phy[phy_index].hw_reset(
7987                                 &params->phy[phy_index],
7988                                 params);
7989                         params->phy[phy_index] = phy_null;
7990                 }
7991         }
7992 }