drivers/net/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2011 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30
  31 /********************************************************/
  32 #define ETH_HLEN                        14
  33 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  34 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  35 #define ETH_MIN_PACKET_SIZE             60
  36 #define ETH_MAX_PACKET_SIZE             1500
  37 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  38 #define MDIO_ACCESS_TIMEOUT             1000
  39 #define BMAC_CONTROL_RX_ENABLE          2
  40 #define WC_LANE_MAX                     4
  41 #define I2C_SWITCH_WIDTH                2
  42 #define I2C_BSC0                        0
  43 #define I2C_BSC1                        1
  44 #define I2C_WA_RETRY_CNT                3
  45 #define MCPR_IMC_COMMAND_READ_OP        1
  46 #define MCPR_IMC_COMMAND_WRITE_OP       2
  47
  48 /***********************************************************/
  49 /*                      Shortcut definitions               */
  50 /***********************************************************/
  51
  52 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  53
  54 #define NIG_STATUS_EMAC0_MI_INT \
  55                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  56 #define NIG_STATUS_XGXS0_LINK10G \
  57                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  58 #define NIG_STATUS_XGXS0_LINK_STATUS \
  59                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  60 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  62 #define NIG_STATUS_SERDES0_LINK_STATUS \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  64 #define NIG_MASK_MI_INT \
  65                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  66 #define NIG_MASK_XGXS0_LINK10G \
  67                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  68 #define NIG_MASK_XGXS0_LINK_STATUS \
  69                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  70 #define NIG_MASK_SERDES0_LINK_STATUS \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  72
  73 #define MDIO_AN_CL73_OR_37_COMPLETE \
  74                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  75                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  76
  77 #define XGXS_RESET_BITS \
  78         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  79          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  80          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  81          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  82          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  83
  84 #define SERDES_RESET_BITS \
  85         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  89
  90 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  91 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  92 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  93 #define AUTONEG_PARALLEL \
  94                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
  95 #define AUTONEG_SGMII_FIBER_AUTODET \
  96                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
  97 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
  98
  99 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 100                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 101 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 102                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 103 #define GP_STATUS_SPEED_MASK \
 104                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 105 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 106 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 107 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 108 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 109 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 110 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 111 #define GP_STATUS_10G_HIG \
 112                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 113 #define GP_STATUS_10G_CX4 \
 114                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 115 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 116 #define GP_STATUS_10G_KX4 \
 117                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 118 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 119 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 120 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 121 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 122 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 123 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 124 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 125 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 126 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 127 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 128 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 129 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 130 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 131 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 132 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 133 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 134 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 135 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 136 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 137
 138
 139
 140 /* */
 141 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 142         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 143         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 144
 145
 146 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 147         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 148         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 149         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 150
 151 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 152         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 153         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 154
 155 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 156         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 157 #define SFP_EEPROM_OPTIONS_SIZE                 2
 158
 159 #define EDC_MODE_LINEAR                         0x0022
 160 #define EDC_MODE_LIMITING                               0x0044
 161 #define EDC_MODE_PASSIVE_DAC                    0x0055
 162
 163
 164 /* BRB thresholds for E2*/
 165 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE             170
 166 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE         0
 167
 168 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE              250
 169 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE          0
 170
 171 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE              10
 172 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE          90
 173
 174 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE                       50
 175 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE           250
 176
 177 /* BRB thresholds for E3A0 */
 178 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE           290
 179 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE               0
 180
 181 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE            410
 182 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE                0
 183
 184 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE            10
 185 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE                170
 186
 187 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE             50
 188 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE         410
 189
 190
 191 /* BRB thresholds for E3B0 2 port mode*/
 192 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                1025
 193 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 194
 195 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE         1025
 196 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 197
 198 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 199 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     1025
 200
 201 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE          50
 202 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE      1025
 203
 204 /* only for E3B0*/
 205 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR                        1025
 206 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR                 1025
 207
 208 /* Lossy +Lossless GUARANTIED == GUART */
 209 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART                  284
 210 /* Lossless +Lossless*/
 211 #define PFC_E3B0_2P_PAUSE_LB_GUART                      236
 212 /* Lossy +Lossy*/
 213 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART                  342
 214
 215 /* Lossy +Lossless*/
 216 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART               284
 217 /* Lossless +Lossless*/
 218 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART           236
 219 /* Lossy +Lossy*/
 220 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART               336
 221 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 222
 223 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART             0
 224 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST                0
 225
 226 /* BRB thresholds for E3B0 4 port mode */
 227 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE                304
 228 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE    0
 229
 230 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE         384
 231 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE     0
 232
 233 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE         10
 234 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE     304
 235
 236 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE          50
 237 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE      384
 238
 239
 240 /* only for E3B0*/
 241 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR                        304
 242 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR                 384
 243 #define PFC_E3B0_4P_LB_GUART                            120
 244
 245 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART             120
 246 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST                80
 247
 248 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART             80
 249 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST                120
 250
 251 #define DCBX_INVALID_COS                                        (0xFF)
 252
 253 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 254 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 255 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 256 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 257 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 258
 259 #define MAX_PACKET_SIZE                                 (9700)
 260 #define WC_UC_TIMEOUT                                   100
 261
 262 /**********************************************************/
 263 /*                     INTERFACE                          */
 264 /**********************************************************/
 265
 266 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 267         bnx2x_cl45_write(_bp, _phy, \
 268                 (_phy)->def_md_devad, \
 269                 (_bank + (_addr & 0xf)), \
 270                 _val)
 271
 272 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 273         bnx2x_cl45_read(_bp, _phy, \
 274                 (_phy)->def_md_devad, \
 275                 (_bank + (_addr & 0xf)), \
 276                 _val)
 277
 278 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 279 {
 280         u32 val = REG_RD(bp, reg);
 281
 282         val |= bits;
 283         REG_WR(bp, reg, val);
 284         return val;
 285 }
 286
 287 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 288 {
 289         u32 val = REG_RD(bp, reg);
 290
 291         val &= ~bits;
 292         REG_WR(bp, reg, val);
 293         return val;
 294 }
 295
 296 /******************************************************************/
 297 /*                      EPIO/GPIO section                         */
 298 /******************************************************************/
 299 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 300 {
 301         u32 epio_mask, gp_oenable;
 302         *en = 0;
 303         /* Sanity check */
 304         if (epio_pin > 31) {
 305                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 306                 return;
 307         }
 308
 309         epio_mask = 1 << epio_pin;
 310         /* Set this EPIO to output */
 311         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 312         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 313
 314         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 315 }
 316 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 317 {
 318         u32 epio_mask, gp_output, gp_oenable;
 319
 320         /* Sanity check */
 321         if (epio_pin > 31) {
 322                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 323                 return;
 324         }
 325         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 326         epio_mask = 1 << epio_pin;
 327         /* Set this EPIO to output */
 328         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 329         if (en)
 330                 gp_output |= epio_mask;
 331         else
 332                 gp_output &= ~epio_mask;
 333
 334         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 335
 336         /* Set the value for this EPIO */
 337         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 338         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 339 }
 340
 341 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 342 {
 343         if (pin_cfg == PIN_CFG_NA)
 344                 return;
 345         if (pin_cfg >= PIN_CFG_EPIO0) {
 346                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 347         } else {
 348                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 349                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 350                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 351         }
 352 }
 353
 354 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 355 {
 356         if (pin_cfg == PIN_CFG_NA)
 357                 return -EINVAL;
 358         if (pin_cfg >= PIN_CFG_EPIO0) {
 359                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 360         } else {
 361                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 362                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 363                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 364         }
 365         return 0;
 366
 367 }
 368 /******************************************************************/
 369 /*                              ETS section                       */
 370 /******************************************************************/
 371 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 372 {
 373         /* ETS disabled configuration*/
 374         struct bnx2x *bp = params->bp;
 375
 376         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 377
 378         /*
 379          * mapping between entry  priority to client number (0,1,2 -debug and
 380          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 381          * 3bits client num.
 382          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 383          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 384          */
 385
 386         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 387         /*
 388          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 389          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 390          * COS0 entry, 4 - COS1 entry.
 391          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 392          * bit4   bit3    bit2   bit1     bit0
 393          * MCP and debug are strict
 394          */
 395
 396         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 397         /* defines which entries (clients) are subjected to WFQ arbitration */
 398         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 399         /*
 400          * For strict priority entries defines the number of consecutive
 401          * slots for the highest priority.
 402          */
 403         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 404         /*
 405          * mapping between the CREDIT_WEIGHT registers and actual client
 406          * numbers
 407          */
 408         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 409         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 410         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 411
 412         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 413         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 414         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 415         /* ETS mode disable */
 416         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 417         /*
 418          * If ETS mode is enabled (there is no strict priority) defines a WFQ
 419          * weight for COS0/COS1.
 420          */
 421         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 422         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 423         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 424         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 425         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 426         /* Defines the number of consecutive slots for the strict priority */
 427         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 428 }
 429 /******************************************************************************
 430 * Description:
 431 *       Getting min_w_val will be set according to line speed .
 432 *.
 433 ******************************************************************************/
 434 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 435 {
 436         u32 min_w_val = 0;
 437         /* Calculate min_w_val.*/
 438         if (vars->link_up) {
 439                 if (SPEED_20000 == vars->line_speed)
 440                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 441                 else
 442                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 443         } else
 444                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 445         /**
 446          *  If the link isn't up (static configuration for example ) The
 447          *  link will be according to 20GBPS.
 448         */
 449         return min_w_val;
 450 }
 451 /******************************************************************************
 452 * Description:
 453 *       Getting credit upper bound form min_w_val.
 454 *.
 455 ******************************************************************************/
 456 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 457 {
 458         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 459                                                 MAX_PACKET_SIZE);
 460         return credit_upper_bound;
 461 }
 462 /******************************************************************************
 463 * Description:
 464 *       Set credit upper bound for NIG.
 465 *.
 466 ******************************************************************************/
 467 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 468         const struct link_params *params,
 469         const u32 min_w_val)
 470 {
 471         struct bnx2x *bp = params->bp;
 472         const u8 port = params->port;
 473         const u32 credit_upper_bound =
 474             bnx2x_ets_get_credit_upper_bound(min_w_val);
 475
 476         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 477                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 478         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 479                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 480         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 481                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 482         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 483                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 484         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 485                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 486         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 487                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 488
 489         if (0 == port) {
 490                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 491                         credit_upper_bound);
 492                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 493                         credit_upper_bound);
 494                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 495                         credit_upper_bound);
 496         }
 497 }
 498 /******************************************************************************
 499 * Description:
 500 *       Will return the NIG ETS registers to init values.Except
 501 *       credit_upper_bound.
 502 *       That isn't used in this configuration (No WFQ is enabled) and will be
 503 *       configured acording to spec
 504 *.
 505 ******************************************************************************/
 506 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 507                                         const struct link_vars *vars)
 508 {
 509         struct bnx2x *bp = params->bp;
 510         const u8 port = params->port;
 511         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 512         /**
 513          * mapping between entry  priority to client number (0,1,2 -debug and
 514          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 515          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 516          * reset value or init tool
 517          */
 518         if (port) {
 519                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 520                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 521         } else {
 522                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 523                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 524         }
 525         /**
 526         * For strict priority entries defines the number of consecutive
 527         * slots for the highest priority.
 528         */
 529         /* TODO_ETS - Should be done by reset value or init tool */
 530         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 531                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 532         /**
 533          * mapping between the CREDIT_WEIGHT registers and actual client
 534          * numbers
 535          */
 536         /* TODO_ETS - Should be done by reset value or init tool */
 537         if (port) {
 538                 /*Port 1 has 6 COS*/
 539                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 540                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 541         } else {
 542                 /*Port 0 has 9 COS*/
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 544                        0x43210876);
 545                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 546         }
 547
 548         /**
 549          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
 550          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 551          * COS0 entry, 4 - COS1 entry.
 552          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 553          * bit4   bit3    bit2   bit1     bit0
 554          * MCP and debug are strict
 555          */
 556         if (port)
 557                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 558         else
 559                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 560         /* defines which entries (clients) are subjected to WFQ arbitration */
 561         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 562                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 563
 564         /**
 565         * Please notice the register address are note continuous and a
 566         * for here is note appropriate.In 2 port mode port0 only COS0-5
 567         * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 568         * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 569         * are never used for WFQ
 570         */
 571         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 572                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 573         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 574                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 575         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 576                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 577         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 578                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 579         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 580                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 581         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 582                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 583         if (0 == port) {
 584                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 585                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 586                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 587         }
 588
 589         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 590 }
 591 /******************************************************************************
 592 * Description:
 593 *       Set credit upper bound for PBF.
 594 *.
 595 ******************************************************************************/
 596 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 597         const struct link_params *params,
 598         const u32 min_w_val)
 599 {
 600         struct bnx2x *bp = params->bp;
 601         const u32 credit_upper_bound =
 602             bnx2x_ets_get_credit_upper_bound(min_w_val);
 603         const u8 port = params->port;
 604         u32 base_upper_bound = 0;
 605         u8 max_cos = 0;
 606         u8 i = 0;
 607         /**
 608         * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 609         * port mode port1 has COS0-2 that can be used for WFQ.
 610         */
 611         if (0 == port) {
 612                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 613                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 614         } else {
 615                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 616                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 617         }
 618
 619         for (i = 0; i < max_cos; i++)
 620                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 621 }
 622
 623 /******************************************************************************
 624 * Description:
 625 *       Will return the PBF ETS registers to init values.Except
 626 *       credit_upper_bound.
 627 *       That isn't used in this configuration (No WFQ is enabled) and will be
 628 *       configured acording to spec
 629 *.
 630 ******************************************************************************/
 631 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 632 {
 633         struct bnx2x *bp = params->bp;
 634         const u8 port = params->port;
 635         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 636         u8 i = 0;
 637         u32 base_weight = 0;
 638         u8 max_cos = 0;
 639
 640         /**
 641          * mapping between entry  priority to client number 0 - COS0
 642          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 643          * TODO_ETS - Should be done by reset value or init tool
 644          */
 645         if (port)
 646                 /*  0x688 (|011|0 10|00 1|000) */
 647                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 648         else
 649                 /*  (10 1|100 |011|0 10|00 1|000) */
 650                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 651
 652         /* TODO_ETS - Should be done by reset value or init tool */
 653         if (port)
 654                 /* 0x688 (|011|0 10|00 1|000)*/
 655                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 656         else
 657         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 658         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 659
 660         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 661                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 662
 663
 664         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 665                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 666
 667         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 668                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 669         /**
 670         * In 2 port mode port0 has COS0-5 that can be used for WFQ.
 671         * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 672         */
 673         if (0 == port) {
 674                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 675                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 676         } else {
 677                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 678                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 679         }
 680
 681         for (i = 0; i < max_cos; i++)
 682                 REG_WR(bp, base_weight + (0x4 * i), 0);
 683
 684         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 685 }
 686 /******************************************************************************
 687 * Description:
 688 *       E3B0 disable will return basicly the values to init values.
 689 *.
 690 ******************************************************************************/
 691 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 692                                    const struct link_vars *vars)
 693 {
 694         struct bnx2x *bp = params->bp;
 695
 696         if (!CHIP_IS_E3B0(bp)) {
 697                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
 698                                    "\n");
 699                 return -EINVAL;
 700         }
 701
 702         bnx2x_ets_e3b0_nig_disabled(params, vars);
 703
 704         bnx2x_ets_e3b0_pbf_disabled(params);
 705
 706         return 0;
 707 }
 708
 709 /******************************************************************************
 710 * Description:
 711 *       Disable will return basicly the values to init values.
 712 *.
 713 ******************************************************************************/
 714 int bnx2x_ets_disabled(struct link_params *params,
 715                       struct link_vars *vars)
 716 {
 717         struct bnx2x *bp = params->bp;
 718         int bnx2x_status = 0;
 719
 720         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 721                 bnx2x_ets_e2e3a0_disabled(params);
 722         else if (CHIP_IS_E3B0(bp))
 723                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 724         else {
 725                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 726                 return -EINVAL;
 727         }
 728
 729         return bnx2x_status;
 730 }
 731
 732 /******************************************************************************
 733 * Description
 734 *       Set the COS mappimg to SP and BW until this point all the COS are not
 735 *       set as SP or BW.
 736 ******************************************************************************/
 737 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 738                                   const struct bnx2x_ets_params *ets_params,
 739                                   const u8 cos_sp_bitmap,
 740                                   const u8 cos_bw_bitmap)
 741 {
 742         struct bnx2x *bp = params->bp;
 743         const u8 port = params->port;
 744         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 745         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 746         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 747         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 748
 749         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 750                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 751
 752         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 753                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 754
 755         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 756                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 757                nig_cli_subject2wfq_bitmap);
 758
 759         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 760                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 761                pbf_cli_subject2wfq_bitmap);
 762
 763         return 0;
 764 }
 765
 766 /******************************************************************************
 767 * Description:
 768 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 769 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 770 ******************************************************************************/
 771 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 772                                      const u8 cos_entry,
 773                                      const u32 min_w_val_nig,
 774                                      const u32 min_w_val_pbf,
 775                                      const u16 total_bw,
 776                                      const u8 bw,
 777                                      const u8 port)
 778 {
 779         u32 nig_reg_adress_crd_weight = 0;
 780         u32 pbf_reg_adress_crd_weight = 0;
 781         /* Calculate and set BW for this COS*/
 782         const u32 cos_bw_nig = (bw * min_w_val_nig) / total_bw;
 783         const u32 cos_bw_pbf = (bw * min_w_val_pbf) / total_bw;
 784
 785         switch (cos_entry) {
 786         case 0:
 787             nig_reg_adress_crd_weight =
 788                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 789                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 790              pbf_reg_adress_crd_weight = (port) ?
 791                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 792              break;
 793         case 1:
 794              nig_reg_adress_crd_weight = (port) ?
 795                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 796                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 797              pbf_reg_adress_crd_weight = (port) ?
 798                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 799              break;
 800         case 2:
 801              nig_reg_adress_crd_weight = (port) ?
 802                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 803                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 804
 805                  pbf_reg_adress_crd_weight = (port) ?
 806                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 807              break;
 808         case 3:
 809             if (port)
 810                         return -EINVAL;
 811              nig_reg_adress_crd_weight =
 812                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 813              pbf_reg_adress_crd_weight =
 814                  PBF_REG_COS3_WEIGHT_P0;
 815              break;
 816         case 4:
 817             if (port)
 818                 return -EINVAL;
 819              nig_reg_adress_crd_weight =
 820                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 821              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 822              break;
 823         case 5:
 824             if (port)
 825                 return -EINVAL;
 826              nig_reg_adress_crd_weight =
 827                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 828              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 829              break;
 830         }
 831
 832         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 833
 834         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 835
 836         return 0;
 837 }
 838 /******************************************************************************
 839 * Description:
 840 *       Calculate the total BW.A value of 0 isn't legal.
 841 *.
 842 ******************************************************************************/
 843 static int bnx2x_ets_e3b0_get_total_bw(
 844         const struct link_params *params,
 845         const struct bnx2x_ets_params *ets_params,
 846         u16 *total_bw)
 847 {
 848         struct bnx2x *bp = params->bp;
 849         u8 cos_idx = 0;
 850
 851         *total_bw = 0 ;
 852         /* Calculate total BW requested */
 853         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 854                 if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) {
 855
 856                         if (0 == ets_params->cos[cos_idx].params.bw_params.bw) {
 857                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 858                                                    "was set to 0\n");
 859                         return -EINVAL;
 860                 }
 861                 *total_bw +=
 862                     ets_params->cos[cos_idx].params.bw_params.bw;
 863             }
 864         }
 865
 866         /*Check taotl BW is valid */
 867         if ((100 != *total_bw) || (0 == *total_bw)) {
 868                 if (0 == *total_bw) {
 869                         DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW"
 870                                            "shouldn't be 0\n");
 871                         return -EINVAL;
 872                 }
 873                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW should be"
 874                                    "100\n");
 875                 /**
 876                 *   We can handle a case whre the BW isn't 100 this can happen
 877                 *   if the TC are joined.
 878                 */
 879         }
 880         return 0;
 881 }
 882
 883 /******************************************************************************
 884 * Description:
 885 *       Invalidate all the sp_pri_to_cos.
 886 *.
 887 ******************************************************************************/
 888 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 889 {
 890         u8 pri = 0;
 891         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 892                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 893 }
 894 /******************************************************************************
 895 * Description:
 896 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 897 *       according to sp_pri_to_cos.
 898 *.
 899 ******************************************************************************/
 900 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 901                                             u8 *sp_pri_to_cos, const u8 pri,
 902                                             const u8 cos_entry)
 903 {
 904         struct bnx2x *bp = params->bp;
 905         const u8 port = params->port;
 906         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 907                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 908
 909         if (DCBX_INVALID_COS != sp_pri_to_cos[pri]) {
 910                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 911                                    "parameter There can't be two COS's with"
 912                                    "the same strict pri\n");
 913                 return -EINVAL;
 914         }
 915
 916         if (pri > max_num_of_cos) {
 917                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid"
 918                                "parameter Illegal strict priority\n");
 919             return -EINVAL;
 920         }
 921
 922         sp_pri_to_cos[pri] = cos_entry;
 923         return 0;
 924
 925 }
 926
 927 /******************************************************************************
 928 * Description:
 929 *       Returns the correct value according to COS and priority in
 930 *       the sp_pri_cli register.
 931 *.
 932 ******************************************************************************/
 933 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 934                                          const u8 pri_set,
 935                                          const u8 pri_offset,
 936                                          const u8 entry_size)
 937 {
 938         u64 pri_cli_nig = 0;
 939         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 940                                                     (pri_set + pri_offset));
 941
 942         return pri_cli_nig;
 943 }
 944 /******************************************************************************
 945 * Description:
 946 *       Returns the correct value according to COS and priority in the
 947 *       sp_pri_cli register for NIG.
 948 *.
 949 ******************************************************************************/
 950 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 951 {
 952         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 953         const u8 nig_cos_offset = 3;
 954         const u8 nig_pri_offset = 3;
 955
 956         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
 957                 nig_pri_offset, 4);
 958
 959 }
 960 /******************************************************************************
 961 * Description:
 962 *       Returns the correct value according to COS and priority in the
 963 *       sp_pri_cli register for PBF.
 964 *.
 965 ******************************************************************************/
 966 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
 967 {
 968         const u8 pbf_cos_offset = 0;
 969         const u8 pbf_pri_offset = 0;
 970
 971         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
 972                 pbf_pri_offset, 3);
 973
 974 }
 975
 976 /******************************************************************************
 977 * Description:
 978 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 979 *       according to sp_pri_to_cos.(which COS has higher priority)
 980 *.
 981 ******************************************************************************/
 982 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
 983                                              u8 *sp_pri_to_cos)
 984 {
 985         struct bnx2x *bp = params->bp;
 986         u8 i = 0;
 987         const u8 port = params->port;
 988         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 989         u64 pri_cli_nig = 0x210;
 990         u32 pri_cli_pbf = 0x0;
 991         u8 pri_set = 0;
 992         u8 pri_bitmask = 0;
 993         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 994                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 995
 996         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
 997
 998         /* Set all the strict priority first */
 999         for (i = 0; i < max_num_of_cos; i++) {
1000                 if (DCBX_INVALID_COS != sp_pri_to_cos[i]) {
1001                         if (DCBX_MAX_NUM_COS <= sp_pri_to_cos[i]) {
1002                                 DP(NETIF_MSG_LINK,
1003                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1004                                            "invalid cos entry\n");
1005                                 return -EINVAL;
1006                         }
1007
1008                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1009                             sp_pri_to_cos[i], pri_set);
1010
1011                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1012                             sp_pri_to_cos[i], pri_set);
1013                         pri_bitmask = 1 << sp_pri_to_cos[i];
1014                         /* COS is used remove it from bitmap.*/
1015                         if (0 == (pri_bitmask & cos_bit_to_set)) {
1016                                 DP(NETIF_MSG_LINK,
1017                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1018                                         "invalid There can't be two COS's with"
1019                                         " the same strict pri\n");
1020                                 return -EINVAL;
1021                         }
1022                         cos_bit_to_set &= ~pri_bitmask;
1023                         pri_set++;
1024                 }
1025         }
1026
1027         /* Set all the Non strict priority i= COS*/
1028         for (i = 0; i < max_num_of_cos; i++) {
1029                 pri_bitmask = 1 << i;
1030                 /* Check if COS was already used for SP */
1031                 if (pri_bitmask & cos_bit_to_set) {
1032                         /* COS wasn't used for SP */
1033                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1034                             i, pri_set);
1035
1036                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1037                             i, pri_set);
1038                         /* COS is used remove it from bitmap.*/
1039                         cos_bit_to_set &= ~pri_bitmask;
1040                         pri_set++;
1041                 }
1042         }
1043
1044         if (pri_set != max_num_of_cos) {
1045                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1046                                    "entries were set\n");
1047                 return -EINVAL;
1048         }
1049
1050         if (port) {
1051                 /* Only 6 usable clients*/
1052                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1053                        (u32)pri_cli_nig);
1054
1055                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1056         } else {
1057                 /* Only 9 usable clients*/
1058                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1059                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1060
1061                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1062                        pri_cli_nig_lsb);
1063                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1064                        pri_cli_nig_msb);
1065
1066                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1067         }
1068         return 0;
1069 }
1070
1071 /******************************************************************************
1072 * Description:
1073 *       Configure the COS to ETS according to BW and SP settings.
1074 ******************************************************************************/
1075 int bnx2x_ets_e3b0_config(const struct link_params *params,
1076                          const struct link_vars *vars,
1077                          const struct bnx2x_ets_params *ets_params)
1078 {
1079         struct bnx2x *bp = params->bp;
1080         int bnx2x_status = 0;
1081         const u8 port = params->port;
1082         u16 total_bw = 0;
1083         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1084         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1085         u8 cos_bw_bitmap = 0;
1086         u8 cos_sp_bitmap = 0;
1087         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1088         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1089                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1090         u8 cos_entry = 0;
1091
1092         if (!CHIP_IS_E3B0(bp)) {
1093                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_disabled the chip isn't E3B0"
1094                                    "\n");
1095                 return -EINVAL;
1096         }
1097
1098         if ((ets_params->num_of_cos > max_num_of_cos)) {
1099                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1100                                    "isn't supported\n");
1101                 return -EINVAL;
1102         }
1103
1104         /* Prepare sp strict priority parameters*/
1105         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1106
1107         /* Prepare BW parameters*/
1108         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1109                                                    &total_bw);
1110         if (0 != bnx2x_status) {
1111                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config get_total_bw failed "
1112                                    "\n");
1113                 return -EINVAL;
1114         }
1115
1116         /**
1117          *  Upper bound is set according to current link speed (min_w_val
1118          *  should be the same for upper bound and COS credit val).
1119          */
1120         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1121         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1122
1123
1124         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1125                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1126                         cos_bw_bitmap |= (1 << cos_entry);
1127                         /**
1128                          * The function also sets the BW in HW(not the mappin
1129                          * yet)
1130                          */
1131                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1132                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1133                                 total_bw,
1134                                 ets_params->cos[cos_entry].params.bw_params.bw,
1135                                  port);
1136                 } else if (bnx2x_cos_state_strict ==
1137                         ets_params->cos[cos_entry].state){
1138                         cos_sp_bitmap |= (1 << cos_entry);
1139
1140                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1141                                 params,
1142                                 sp_pri_to_cos,
1143                                 ets_params->cos[cos_entry].params.sp_params.pri,
1144                                 cos_entry);
1145
1146                 } else {
1147                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config cos state not"
1148                                            " valid\n");
1149                         return -EINVAL;
1150                 }
1151                 if (0 != bnx2x_status) {
1152                         DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_config set cos bw "
1153                                            "failed\n");
1154                         return bnx2x_status;
1155                 }
1156         }
1157
1158         /* Set SP register (which COS has higher priority) */
1159         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1160                                                          sp_pri_to_cos);
1161
1162         if (0 != bnx2x_status) {
1163                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config set_pri_cli_reg "
1164                                    "failed\n");
1165                 return bnx2x_status;
1166         }
1167
1168         /* Set client mapping of BW and strict */
1169         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1170                                               cos_sp_bitmap,
1171                                               cos_bw_bitmap);
1172
1173         if (0 != bnx2x_status) {
1174                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1175                 return bnx2x_status;
1176         }
1177         return 0;
1178 }
1179 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1180 {
1181         /* ETS disabled configuration */
1182         struct bnx2x *bp = params->bp;
1183         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1184         /*
1185          * defines which entries (clients) are subjected to WFQ arbitration
1186          * COS0 0x8
1187          * COS1 0x10
1188          */
1189         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1190         /*
1191          * mapping between the ARB_CREDIT_WEIGHT registers and actual
1192          * client numbers (WEIGHT_0 does not actually have to represent
1193          * client 0)
1194          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1195          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1196          */
1197         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1198
1199         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1200                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1201         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1202                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1203
1204         /* ETS mode enabled*/
1205         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1206
1207         /* Defines the number of consecutive slots for the strict priority */
1208         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1209         /*
1210          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1211          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1212          * entry, 4 - COS1 entry.
1213          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1214          * bit4   bit3    bit2     bit1    bit0
1215          * MCP and debug are strict
1216          */
1217         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1218
1219         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1220         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1221                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1222         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1223                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1224 }
1225
1226 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1227                         const u32 cos1_bw)
1228 {
1229         /* ETS disabled configuration*/
1230         struct bnx2x *bp = params->bp;
1231         const u32 total_bw = cos0_bw + cos1_bw;
1232         u32 cos0_credit_weight = 0;
1233         u32 cos1_credit_weight = 0;
1234
1235         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1236
1237         if ((0 == total_bw) ||
1238             (0 == cos0_bw) ||
1239             (0 == cos1_bw)) {
1240                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1241                 return;
1242         }
1243
1244         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1245                 total_bw;
1246         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1247                 total_bw;
1248
1249         bnx2x_ets_bw_limit_common(params);
1250
1251         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1252         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1253
1254         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1255         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1256 }
1257
1258 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1259 {
1260         /* ETS disabled configuration*/
1261         struct bnx2x *bp = params->bp;
1262         u32 val = 0;
1263
1264         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1265         /*
1266          * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1267          * as strict.  Bits 0,1,2 - debug and management entries,
1268          * 3 - COS0 entry, 4 - COS1 entry.
1269          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1270          *  bit4   bit3   bit2      bit1     bit0
1271          * MCP and debug are strict
1272          */
1273         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1274         /*
1275          * For strict priority entries defines the number of consecutive slots
1276          * for the highest priority.
1277          */
1278         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1279         /* ETS mode disable */
1280         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1281         /* Defines the number of consecutive slots for the strict priority */
1282         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1283
1284         /* Defines the number of consecutive slots for the strict priority */
1285         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1286
1287         /*
1288          * mapping between entry  priority to client number (0,1,2 -debug and
1289          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1290          * 3bits client num.
1291          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1292          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1293          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1294          */
1295         val = (0 == strict_cos) ? 0x2318 : 0x22E0;
1296         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1297
1298         return 0;
1299 }
1300 /******************************************************************/
1301 /*                      PFC section                               */
1302 /******************************************************************/
1303
1304 static void bnx2x_update_pfc_xmac(struct link_params *params,
1305                                   struct link_vars *vars,
1306                                   u8 is_lb)
1307 {
1308         struct bnx2x *bp = params->bp;
1309         u32 xmac_base;
1310         u32 pause_val, pfc0_val, pfc1_val;
1311
1312         /* XMAC base adrr */
1313         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1314
1315         /* Initialize pause and pfc registers */
1316         pause_val = 0x18000;
1317         pfc0_val = 0xFFFF8000;
1318         pfc1_val = 0x2;
1319
1320         /* No PFC support */
1321         if (!(params->feature_config_flags &
1322               FEATURE_CONFIG_PFC_ENABLED)) {
1323
1324                 /*
1325                  * RX flow control - Process pause frame in receive direction
1326                  */
1327                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1328                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1329
1330                 /*
1331                  * TX flow control - Send pause packet when buffer is full
1332                  */
1333                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1334                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1335         } else {/* PFC support */
1336                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1337                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1338                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1339                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN;
1340         }
1341
1342         /* Write pause and PFC registers */
1343         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1344         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1345         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1346
1347
1348         /* Set MAC address for source TX Pause/PFC frames */
1349         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1350                ((params->mac_addr[2] << 24) |
1351                 (params->mac_addr[3] << 16) |
1352                 (params->mac_addr[4] << 8) |
1353                 (params->mac_addr[5])));
1354         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1355                ((params->mac_addr[0] << 8) |
1356                 (params->mac_addr[1])));
1357
1358         udelay(30);
1359 }
1360
1361
1362 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1363                                     u32 pfc_frames_sent[2],
1364                                     u32 pfc_frames_received[2])
1365 {
1366         /* Read pfc statistic */
1367         struct bnx2x *bp = params->bp;
1368         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1369         u32 val_xon = 0;
1370         u32 val_xoff = 0;
1371
1372         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1373
1374         /* PFC received frames */
1375         val_xoff = REG_RD(bp, emac_base +
1376                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1377         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1378         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1379         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1380
1381         pfc_frames_received[0] = val_xon + val_xoff;
1382
1383         /* PFC received sent */
1384         val_xoff = REG_RD(bp, emac_base +
1385                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1386         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1387         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1388         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1389
1390         pfc_frames_sent[0] = val_xon + val_xoff;
1391 }
1392
1393 /* Read pfc statistic*/
1394 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1395                          u32 pfc_frames_sent[2],
1396                          u32 pfc_frames_received[2])
1397 {
1398         /* Read pfc statistic */
1399         struct bnx2x *bp = params->bp;
1400
1401         DP(NETIF_MSG_LINK, "pfc statistic\n");
1402
1403         if (!vars->link_up)
1404                 return;
1405
1406         if (MAC_TYPE_EMAC == vars->mac_type) {
1407                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1408                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1409                                         pfc_frames_received);
1410         }
1411 }
1412 /******************************************************************/
1413 /*                      MAC/PBF section                           */
1414 /******************************************************************/
1415 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1416 {
1417         u32 mode, emac_base;
1418         /**
1419          * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1420          * (a value of 49==0x31) and make sure that the AUTO poll is off
1421          */
1422
1423         if (CHIP_IS_E2(bp))
1424                 emac_base = GRCBASE_EMAC0;
1425         else
1426                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1427         mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1428         mode &= ~(EMAC_MDIO_MODE_AUTO_POLL |
1429                   EMAC_MDIO_MODE_CLOCK_CNT);
1430         if (USES_WARPCORE(bp))
1431                 mode |= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1432         else
1433                 mode |= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT);
1434
1435         mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1436         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, mode);
1437
1438         udelay(40);
1439 }
1440
1441 static void bnx2x_emac_init(struct link_params *params,
1442                             struct link_vars *vars)
1443 {
1444         /* reset and unreset the emac core */
1445         struct bnx2x *bp = params->bp;
1446         u8 port = params->port;
1447         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1448         u32 val;
1449         u16 timeout;
1450
1451         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1452                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1453         udelay(5);
1454         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1455                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1456
1457         /* init emac - use read-modify-write */
1458         /* self clear reset */
1459         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1460         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1461
1462         timeout = 200;
1463         do {
1464                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1465                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1466                 if (!timeout) {
1467                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1468                         return;
1469                 }
1470                 timeout--;
1471         } while (val & EMAC_MODE_RESET);
1472         bnx2x_set_mdio_clk(bp, params->chip_id, port);
1473         /* Set mac address */
1474         val = ((params->mac_addr[0] << 8) |
1475                 params->mac_addr[1]);
1476         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1477
1478         val = ((params->mac_addr[2] << 24) |
1479                (params->mac_addr[3] << 16) |
1480                (params->mac_addr[4] << 8) |
1481                 params->mac_addr[5]);
1482         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1483 }
1484
1485 static void bnx2x_set_xumac_nig(struct link_params *params,
1486                                 u16 tx_pause_en,
1487                                 u8 enable)
1488 {
1489         struct bnx2x *bp = params->bp;
1490
1491         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1492                enable);
1493         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1494                enable);
1495         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1496                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1497 }
1498
1499 static void bnx2x_umac_enable(struct link_params *params,
1500                             struct link_vars *vars, u8 lb)
1501 {
1502         u32 val;
1503         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1504         struct bnx2x *bp = params->bp;
1505         /* Reset UMAC */
1506         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1507                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1508         usleep_range(1000, 1000);
1509
1510         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1511                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1512
1513         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1514
1515         /**
1516          * This register determines on which events the MAC will assert
1517          * error on the i/f to the NIG along w/ EOP.
1518          */
1519
1520         /**
1521          * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1522          * params->port*0x14,      0xfffff.
1523          */
1524         /* This register opens the gate for the UMAC despite its name */
1525         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1526
1527         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1528                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1529                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1530                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1531         switch (vars->line_speed) {
1532         case SPEED_10:
1533                 val |= (0<<2);
1534                 break;
1535         case SPEED_100:
1536                 val |= (1<<2);
1537                 break;
1538         case SPEED_1000:
1539                 val |= (2<<2);
1540                 break;
1541         case SPEED_2500:
1542                 val |= (3<<2);
1543                 break;
1544         default:
1545                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1546                                vars->line_speed);
1547                 break;
1548         }
1549         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1550         udelay(50);
1551
1552         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1553         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1554                ((params->mac_addr[2] << 24) |
1555                 (params->mac_addr[3] << 16) |
1556                 (params->mac_addr[4] << 8) |
1557                 (params->mac_addr[5])));
1558         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1559                ((params->mac_addr[0] << 8) |
1560                 (params->mac_addr[1])));
1561
1562         /* Enable RX and TX */
1563         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1564         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1565                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1566         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1567         udelay(50);
1568
1569         /* Remove SW Reset */
1570         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1571
1572         /* Check loopback mode */
1573         if (lb)
1574                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1575         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1576
1577         /*
1578          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1579          * length used by the MAC receive logic to check frames.
1580          */
1581         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1582         bnx2x_set_xumac_nig(params,
1583                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1584         vars->mac_type = MAC_TYPE_UMAC;
1585
1586 }
1587
1588 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1589 {
1590         u32 port4mode_ovwr_val;
1591         /* Check 4-port override enabled */
1592         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1593         if (port4mode_ovwr_val & (1<<0)) {
1594                 /* Return 4-port mode override value */
1595                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1596         }
1597         /* Return 4-port mode from input pin */
1598         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1599 }
1600
1601 /* Define the XMAC mode */
1602 static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1603 {
1604         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1605
1606         /**
1607         * In 4-port mode, need to set the mode only once, so if XMAC is
1608         * already out of reset, it means the mode has already been set,
1609         * and it must not* reset the XMAC again, since it controls both
1610         * ports of the path
1611         **/
1612
1613         if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) &
1614              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1615                 DP(NETIF_MSG_LINK, "XMAC already out of reset"
1616                                    " in 4-port mode\n");
1617                 return;
1618         }
1619
1620         /* Hard reset */
1621         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1622                MISC_REGISTERS_RESET_REG_2_XMAC);
1623         usleep_range(1000, 1000);
1624
1625         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1626                MISC_REGISTERS_RESET_REG_2_XMAC);
1627         if (is_port4mode) {
1628                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1629
1630                 /*  Set the number of ports on the system side to up to 2 */
1631                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1632
1633                 /* Set the number of ports on the Warp Core to 10G */
1634                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1635         } else {
1636                 /*  Set the number of ports on the system side to 1 */
1637                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1638                 if (max_speed == SPEED_10000) {
1639                         DP(NETIF_MSG_LINK, "Init XMAC to 10G x 1"
1640                                            " port per path\n");
1641                         /* Set the number of ports on the Warp Core to 10G */
1642                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1643                 } else {
1644                         DP(NETIF_MSG_LINK, "Init XMAC to 20G x 2 ports"
1645                                            " per path\n");
1646                         /* Set the number of ports on the Warp Core to 20G */
1647                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1648                 }
1649         }
1650         /* Soft reset */
1651         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1652                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1653         usleep_range(1000, 1000);
1654
1655         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1656                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1657
1658 }
1659
1660 static void bnx2x_xmac_disable(struct link_params *params)
1661 {
1662         u8 port = params->port;
1663         struct bnx2x *bp = params->bp;
1664         u32 xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1665
1666         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1667             MISC_REGISTERS_RESET_REG_2_XMAC) {
1668                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1669                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1670                 usleep_range(1000, 1000);
1671                 bnx2x_set_xumac_nig(params, 0, 0);
1672                 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1673                        XMAC_CTRL_REG_SOFT_RESET);
1674         }
1675 }
1676
1677 static int bnx2x_xmac_enable(struct link_params *params,
1678                              struct link_vars *vars, u8 lb)
1679 {
1680         u32 val, xmac_base;
1681         struct bnx2x *bp = params->bp;
1682         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1683
1684         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1685
1686         bnx2x_xmac_init(bp, vars->line_speed);
1687
1688         /*
1689          * This register determines on which events the MAC will assert
1690          * error on the i/f to the NIG along w/ EOP.
1691          */
1692
1693         /*
1694          * This register tells the NIG whether to send traffic to UMAC
1695          * or XMAC
1696          */
1697         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1698
1699         /* Set Max packet size */
1700         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1701
1702         /* CRC append for Tx packets */
1703         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1704
1705         /* update PFC */
1706         bnx2x_update_pfc_xmac(params, vars, 0);
1707
1708         /* Enable TX and RX */
1709         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1710
1711         /* Check loopback mode */
1712         if (lb)
1713                 val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK;
1714         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1715         bnx2x_set_xumac_nig(params,
1716                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1717
1718         vars->mac_type = MAC_TYPE_XMAC;
1719
1720         return 0;
1721 }
1722 static int bnx2x_emac_enable(struct link_params *params,
1723                              struct link_vars *vars, u8 lb)
1724 {
1725         struct bnx2x *bp = params->bp;
1726         u8 port = params->port;
1727         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1728         u32 val;
1729
1730         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1731
1732         /* enable emac and not bmac */
1733         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1734
1735         /* ASIC */
1736         if (vars->phy_flags & PHY_XGXS_FLAG) {
1737                 u32 ser_lane = ((params->lane_config &
1738                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1739                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1740
1741                 DP(NETIF_MSG_LINK, "XGXS\n");
1742                 /* select the master lanes (out of 0-3) */
1743                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1744                 /* select XGXS */
1745                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1746
1747         } else { /* SerDes */
1748                 DP(NETIF_MSG_LINK, "SerDes\n");
1749                 /* select SerDes */
1750                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1751         }
1752
1753         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1754                       EMAC_RX_MODE_RESET);
1755         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1756                       EMAC_TX_MODE_RESET);
1757
1758         if (CHIP_REV_IS_SLOW(bp)) {
1759                 /* config GMII mode */
1760                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1761                 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
1762         } else { /* ASIC */
1763                 /* pause enable/disable */
1764                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1765                                EMAC_RX_MODE_FLOW_EN);
1766
1767                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1768                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1769                                 EMAC_TX_MODE_FLOW_EN));
1770                 if (!(params->feature_config_flags &
1771                       FEATURE_CONFIG_PFC_ENABLED)) {
1772                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1773                                 bnx2x_bits_en(bp, emac_base +
1774                                               EMAC_REG_EMAC_RX_MODE,
1775                                               EMAC_RX_MODE_FLOW_EN);
1776
1777                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1778                                 bnx2x_bits_en(bp, emac_base +
1779                                               EMAC_REG_EMAC_TX_MODE,
1780                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1781                                                EMAC_TX_MODE_FLOW_EN));
1782                 } else
1783                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1784                                       EMAC_TX_MODE_FLOW_EN);
1785         }
1786
1787         /* KEEP_VLAN_TAG, promiscuous */
1788         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1789         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1790
1791         /*
1792          * Setting this bit causes MAC control frames (except for pause
1793          * frames) to be passed on for processing. This setting has no
1794          * affect on the operation of the pause frames. This bit effects
1795          * all packets regardless of RX Parser packet sorting logic.
1796          * Turn the PFC off to make sure we are in Xon state before
1797          * enabling it.
1798          */
1799         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1800         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1801                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1802                 /* Enable PFC again */
1803                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1804                         EMAC_REG_RX_PFC_MODE_RX_EN |
1805                         EMAC_REG_RX_PFC_MODE_TX_EN |
1806                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1807
1808                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1809                         ((0x0101 <<
1810                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1811                          (0x00ff <<
1812                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1813                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1814         }
1815         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1816
1817         /* Set Loopback */
1818         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1819         if (lb)
1820                 val |= 0x810;
1821         else
1822                 val &= ~0x810;
1823         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1824
1825         /* enable emac */
1826         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1827
1828         /* enable emac for jumbo packets */
1829         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1830                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1831                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1832
1833         /* strip CRC */
1834         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1835
1836         /* disable the NIG in/out to the bmac */
1837         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1838         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1839         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1840
1841         /* enable the NIG in/out to the emac */
1842         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1843         val = 0;
1844         if ((params->feature_config_flags &
1845               FEATURE_CONFIG_PFC_ENABLED) ||
1846             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1847                 val = 1;
1848
1849         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1850         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1851
1852         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1853
1854         vars->mac_type = MAC_TYPE_EMAC;
1855         return 0;
1856 }
1857
1858 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1859                                    struct link_vars *vars)
1860 {
1861         u32 wb_data[2];
1862         struct bnx2x *bp = params->bp;
1863         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1864                 NIG_REG_INGRESS_BMAC0_MEM;
1865
1866         u32 val = 0x14;
1867         if ((!(params->feature_config_flags &
1868               FEATURE_CONFIG_PFC_ENABLED)) &&
1869                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1870                 /* Enable BigMAC to react on received Pause packets */
1871                 val |= (1<<5);
1872         wb_data[0] = val;
1873         wb_data[1] = 0;
1874         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1875
1876         /* tx control */
1877         val = 0xc0;
1878         if (!(params->feature_config_flags &
1879               FEATURE_CONFIG_PFC_ENABLED) &&
1880                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1881                 val |= 0x800000;
1882         wb_data[0] = val;
1883         wb_data[1] = 0;
1884         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1885 }
1886
1887 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1888                                    struct link_vars *vars,
1889                                    u8 is_lb)
1890 {
1891         /*
1892          * Set rx control: Strip CRC and enable BigMAC to relay
1893          * control packets to the system as well
1894          */
1895         u32 wb_data[2];
1896         struct bnx2x *bp = params->bp;
1897         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1898                 NIG_REG_INGRESS_BMAC0_MEM;
1899         u32 val = 0x14;
1900
1901         if ((!(params->feature_config_flags &
1902               FEATURE_CONFIG_PFC_ENABLED)) &&
1903                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1904                 /* Enable BigMAC to react on received Pause packets */
1905                 val |= (1<<5);
1906         wb_data[0] = val;
1907         wb_data[1] = 0;
1908         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1909         udelay(30);
1910
1911         /* Tx control */
1912         val = 0xc0;
1913         if (!(params->feature_config_flags &
1914                                 FEATURE_CONFIG_PFC_ENABLED) &&
1915             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1916                 val |= 0x800000;
1917         wb_data[0] = val;
1918         wb_data[1] = 0;
1919         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
1920
1921         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1922                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1923                 /* Enable PFC RX & TX & STATS and set 8 COS  */
1924                 wb_data[0] = 0x0;
1925                 wb_data[0] |= (1<<0);  /* RX */
1926                 wb_data[0] |= (1<<1);  /* TX */
1927                 wb_data[0] |= (1<<2);  /* Force initial Xon */
1928                 wb_data[0] |= (1<<3);  /* 8 cos */
1929                 wb_data[0] |= (1<<5);  /* STATS */
1930                 wb_data[1] = 0;
1931                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
1932                             wb_data, 2);
1933                 /* Clear the force Xon */
1934                 wb_data[0] &= ~(1<<2);
1935         } else {
1936                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
1937                 /* disable PFC RX & TX & STATS and set 8 COS */
1938                 wb_data[0] = 0x8;
1939                 wb_data[1] = 0;
1940         }
1941
1942         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
1943
1944         /*
1945          * Set Time (based unit is 512 bit time) between automatic
1946          * re-sending of PP packets amd enable automatic re-send of
1947          * Per-Priroity Packet as long as pp_gen is asserted and
1948          * pp_disable is low.
1949          */
1950         val = 0x8000;
1951         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1952                 val |= (1<<16); /* enable automatic re-send */
1953
1954         wb_data[0] = val;
1955         wb_data[1] = 0;
1956         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
1957                     wb_data, 2);
1958
1959         /* mac control */
1960         val = 0x3; /* Enable RX and TX */
1961         if (is_lb) {
1962                 val |= 0x4; /* Local loopback */
1963                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
1964         }
1965         /* When PFC enabled, Pass pause frames towards the NIG. */
1966         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
1967                 val |= ((1<<6)|(1<<5));
1968
1969         wb_data[0] = val;
1970         wb_data[1] = 0;
1971         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
1972 }
1973
1974
1975 /* PFC BRB internal port configuration params */
1976 struct bnx2x_pfc_brb_threshold_val {
1977         u32 pause_xoff;
1978         u32 pause_xon;
1979         u32 full_xoff;
1980         u32 full_xon;
1981 };
1982
1983 struct bnx2x_pfc_brb_e3b0_val {
1984         u32 full_lb_xoff_th;
1985         u32 full_lb_xon_threshold;
1986         u32 lb_guarantied;
1987         u32 mac_0_class_t_guarantied;
1988         u32 mac_0_class_t_guarantied_hyst;
1989         u32 mac_1_class_t_guarantied;
1990         u32 mac_1_class_t_guarantied_hyst;
1991 };
1992
1993 struct bnx2x_pfc_brb_th_val {
1994         struct bnx2x_pfc_brb_threshold_val pauseable_th;
1995         struct bnx2x_pfc_brb_threshold_val non_pauseable_th;
1996 };
1997 static int bnx2x_pfc_brb_get_config_params(
1998                                 struct link_params *params,
1999                                 struct bnx2x_pfc_brb_th_val *config_val)
2000 {
2001         struct bnx2x *bp = params->bp;
2002         DP(NETIF_MSG_LINK, "Setting PFC BRB configuration\n");
2003         if (CHIP_IS_E2(bp)) {
2004                 config_val->pauseable_th.pause_xoff =
2005                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2006                 config_val->pauseable_th.pause_xon =
2007                     PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE;
2008                 config_val->pauseable_th.full_xoff =
2009                     PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE;
2010                 config_val->pauseable_th.full_xon =
2011                     PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE;
2012                 /* non pause able*/
2013                 config_val->non_pauseable_th.pause_xoff =
2014                     PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2015                 config_val->non_pauseable_th.pause_xon =
2016                     PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2017                 config_val->non_pauseable_th.full_xoff =
2018                     PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2019                 config_val->non_pauseable_th.full_xon =
2020                     PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2021         } else if (CHIP_IS_E3A0(bp)) {
2022                 config_val->pauseable_th.pause_xoff =
2023                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2024                 config_val->pauseable_th.pause_xon =
2025                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE;
2026                 config_val->pauseable_th.full_xoff =
2027                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE;
2028                 config_val->pauseable_th.full_xon =
2029                     PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE;
2030                 /* non pause able*/
2031                 config_val->non_pauseable_th.pause_xoff =
2032                     PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2033                 config_val->non_pauseable_th.pause_xon =
2034                     PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2035                 config_val->non_pauseable_th.full_xoff =
2036                     PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2037                 config_val->non_pauseable_th.full_xon =
2038                     PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2039         } else if (CHIP_IS_E3B0(bp)) {
2040                 if (params->phy[INT_PHY].flags &
2041                     FLAGS_4_PORT_MODE) {
2042                         config_val->pauseable_th.pause_xoff =
2043                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2044                         config_val->pauseable_th.pause_xon =
2045                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2046                         config_val->pauseable_th.full_xoff =
2047                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2048                         config_val->pauseable_th.full_xon =
2049                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE;
2050                         /* non pause able*/
2051                         config_val->non_pauseable_th.pause_xoff =
2052                             PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2053                         config_val->non_pauseable_th.pause_xon =
2054                             PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2055                         config_val->non_pauseable_th.full_xoff =
2056                             PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2057                         config_val->non_pauseable_th.full_xon =
2058                             PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2059             } else {
2060                 config_val->pauseable_th.pause_xoff =
2061                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2062                 config_val->pauseable_th.pause_xon =
2063                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE;
2064                 config_val->pauseable_th.full_xoff =
2065                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE;
2066                 config_val->pauseable_th.full_xon =
2067                         PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE;
2068                 /* non pause able*/
2069                 config_val->non_pauseable_th.pause_xoff =
2070                     PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE;
2071                 config_val->non_pauseable_th.pause_xon =
2072                     PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE;
2073                 config_val->non_pauseable_th.full_xoff =
2074                     PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE;
2075                 config_val->non_pauseable_th.full_xon =
2076                     PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2077             }
2078         } else
2079             return -EINVAL;
2080
2081         return 0;
2082 }
2083
2084
2085 static void bnx2x_pfc_brb_get_e3b0_config_params(struct link_params *params,
2086                                                  struct bnx2x_pfc_brb_e3b0_val
2087                                                  *e3b0_val,
2088                                                  u32 cos0_pauseable,
2089                                                  u32 cos1_pauseable)
2090 {
2091         if (params->phy[INT_PHY].flags & FLAGS_4_PORT_MODE) {
2092                 e3b0_val->full_lb_xoff_th =
2093                     PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR;
2094                 e3b0_val->full_lb_xon_threshold =
2095                     PFC_E3B0_4P_BRB_FULL_LB_XON_THR;
2096                 e3b0_val->lb_guarantied =
2097                     PFC_E3B0_4P_LB_GUART;
2098                 e3b0_val->mac_0_class_t_guarantied =
2099                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART;
2100                 e3b0_val->mac_0_class_t_guarantied_hyst =
2101                     PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST;
2102                 e3b0_val->mac_1_class_t_guarantied =
2103                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART;
2104                 e3b0_val->mac_1_class_t_guarantied_hyst =
2105                     PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST;
2106         } else {
2107                 e3b0_val->full_lb_xoff_th =
2108                     PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR;
2109                 e3b0_val->full_lb_xon_threshold =
2110                     PFC_E3B0_2P_BRB_FULL_LB_XON_THR;
2111                 e3b0_val->mac_0_class_t_guarantied_hyst =
2112                     PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST;
2113                 e3b0_val->mac_1_class_t_guarantied =
2114                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART;
2115                 e3b0_val->mac_1_class_t_guarantied_hyst =
2116                     PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST;
2117
2118                 if (cos0_pauseable != cos1_pauseable) {
2119                         /* nonpauseable= Lossy + pauseable = Lossless*/
2120                         e3b0_val->lb_guarantied =
2121                             PFC_E3B0_2P_MIX_PAUSE_LB_GUART;
2122                         e3b0_val->mac_0_class_t_guarantied =
2123                             PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART;
2124                 } else if (cos0_pauseable) {
2125                         /* Lossless +Lossless*/
2126                         e3b0_val->lb_guarantied =
2127                             PFC_E3B0_2P_PAUSE_LB_GUART;
2128                         e3b0_val->mac_0_class_t_guarantied =
2129                             PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART;
2130                 } else {
2131                         /* Lossy +Lossy*/
2132                         e3b0_val->lb_guarantied =
2133                             PFC_E3B0_2P_NON_PAUSE_LB_GUART;
2134                         e3b0_val->mac_0_class_t_guarantied =
2135                             PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART;
2136                 }
2137         }
2138 }
2139 static int bnx2x_update_pfc_brb(struct link_params *params,
2140                                 struct link_vars *vars,
2141                                 struct bnx2x_nig_brb_pfc_port_params
2142                                 *pfc_params)
2143 {
2144         struct bnx2x *bp = params->bp;
2145         struct bnx2x_pfc_brb_th_val config_val = { {0} };
2146         struct bnx2x_pfc_brb_threshold_val *reg_th_config =
2147             &config_val.pauseable_th;
2148         struct bnx2x_pfc_brb_e3b0_val e3b0_val = {0};
2149         int set_pfc = params->feature_config_flags &
2150                 FEATURE_CONFIG_PFC_ENABLED;
2151         int bnx2x_status = 0;
2152         u8 port = params->port;
2153
2154         /* default - pause configuration */
2155         reg_th_config = &config_val.pauseable_th;
2156         bnx2x_status = bnx2x_pfc_brb_get_config_params(params, &config_val);
2157         if (0 != bnx2x_status)
2158                 return bnx2x_status;
2159
2160         if (set_pfc && pfc_params)
2161                 /* First COS */
2162                 if (!pfc_params->cos0_pauseable)
2163                         reg_th_config = &config_val.non_pauseable_th;
2164         /*
2165          * The number of free blocks below which the pause signal to class 0
2166          * of MAC #n is asserted. n=0,1
2167          */
2168         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2169                BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2170                reg_th_config->pause_xoff);
2171         /*
2172          * The number of free blocks above which the pause signal to class 0
2173          * of MAC #n is de-asserted. n=0,1
2174          */
2175         REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2176                BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2177         /*
2178          * The number of free blocks below which the full signal to class 0
2179          * of MAC #n is asserted. n=0,1
2180          */
2181         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2182                BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2183         /*
2184          * The number of free blocks above which the full signal to class 0
2185          * of MAC #n is de-asserted. n=0,1
2186          */
2187         REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
2188                BRB1_REG_FULL_0_XON_THRESHOLD_0 , reg_th_config->full_xon);
2189
2190         if (set_pfc && pfc_params) {
2191                 /* Second COS */
2192                 if (pfc_params->cos1_pauseable)
2193                         reg_th_config = &config_val.pauseable_th;
2194                 else
2195                         reg_th_config = &config_val.non_pauseable_th;
2196                 /*
2197                  * The number of free blocks below which the pause signal to
2198                  * class 1 of MAC #n is asserted. n=0,1
2199                 **/
2200                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2201                        BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2202                        reg_th_config->pause_xoff);
2203                 /*
2204                  * The number of free blocks above which the pause signal to
2205                  * class 1 of MAC #n is de-asserted. n=0,1
2206                  */
2207                 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2208                        BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2209                        reg_th_config->pause_xon);
2210                 /*
2211                  * The number of free blocks below which the full signal to
2212                  * class 1 of MAC #n is asserted. n=0,1
2213                  */
2214                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2215                        BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2216                        reg_th_config->full_xoff);
2217                 /*
2218                  * The number of free blocks above which the full signal to
2219                  * class 1 of MAC #n is de-asserted. n=0,1
2220                  */
2221                 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
2222                        BRB1_REG_FULL_1_XON_THRESHOLD_0,
2223                        reg_th_config->full_xon);
2224
2225
2226                 if (CHIP_IS_E3B0(bp)) {
2227                         /*Should be done by init tool */
2228                         /*
2229                         * BRB_empty_for_dup = BRB1_REG_BRB_EMPTY_THRESHOLD
2230                         * reset value
2231                         * 944
2232                         */
2233
2234                         /**
2235                          * The hysteresis on the guarantied buffer space for the Lb port
2236                          * before signaling XON.
2237                          **/
2238                         REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 80);
2239
2240                         bnx2x_pfc_brb_get_e3b0_config_params(
2241                             params,
2242                             &e3b0_val,
2243                             pfc_params->cos0_pauseable,
2244                             pfc_params->cos1_pauseable);
2245                         /**
2246                          * The number of free blocks below which the full signal to the
2247                          * LB port is asserted.
2248                         */
2249                         REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2250                                    e3b0_val.full_lb_xoff_th);
2251                         /**
2252                          * The number of free blocks above which the full signal to the
2253                          * LB port is de-asserted.
2254                         */
2255                         REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2256                                    e3b0_val.full_lb_xon_threshold);
2257                         /**
2258                         * The number of blocks guarantied for the MAC #n port. n=0,1
2259                         */
2260
2261                         /*The number of blocks guarantied for the LB port.*/
2262                         REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2263                                e3b0_val.lb_guarantied);
2264
2265                         /**
2266                          * The number of blocks guarantied for the MAC #n port.
2267                         */
2268                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2269                                    2 * e3b0_val.mac_0_class_t_guarantied);
2270                         REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2271                                    2 * e3b0_val.mac_1_class_t_guarantied);
2272                         /**
2273                          * The number of blocks guarantied for class #t in MAC0. t=0,1
2274                         */
2275                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2276                                e3b0_val.mac_0_class_t_guarantied);
2277                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2278                                e3b0_val.mac_0_class_t_guarantied);
2279                         /**
2280                          * The hysteresis on the guarantied buffer space for class in
2281                          * MAC0.  t=0,1
2282                         */
2283                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
2284                                e3b0_val.mac_0_class_t_guarantied_hyst);
2285                         REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2286                                e3b0_val.mac_0_class_t_guarantied_hyst);
2287
2288                         /**
2289                          * The number of blocks guarantied for class #t in MAC1.t=0,1
2290                         */
2291                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2292                                e3b0_val.mac_1_class_t_guarantied);
2293                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2294                                e3b0_val.mac_1_class_t_guarantied);
2295                         /**
2296                          * The hysteresis on the guarantied buffer space for class #t
2297                         * in MAC1.  t=0,1
2298                         */
2299                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
2300                                e3b0_val.mac_1_class_t_guarantied_hyst);
2301                         REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST,
2302                                e3b0_val.mac_1_class_t_guarantied_hyst);
2303
2304             }
2305
2306         }
2307
2308         return bnx2x_status;
2309 }
2310
2311 /******************************************************************************
2312 * Description:
2313 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2314 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2315 ******************************************************************************/
2316 int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2317                                               u8 cos_entry,
2318                                               u32 priority_mask, u8 port)
2319 {
2320         u32 nig_reg_rx_priority_mask_add = 0;
2321
2322         switch (cos_entry) {
2323         case 0:
2324              nig_reg_rx_priority_mask_add = (port) ?
2325                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2326                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2327              break;
2328         case 1:
2329             nig_reg_rx_priority_mask_add = (port) ?
2330                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2331                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2332             break;
2333         case 2:
2334             nig_reg_rx_priority_mask_add = (port) ?
2335                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2336                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2337             break;
2338         case 3:
2339             if (port)
2340                 return -EINVAL;
2341             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2342             break;
2343         case 4:
2344             if (port)
2345                 return -EINVAL;
2346             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2347             break;
2348         case 5:
2349             if (port)
2350                 return -EINVAL;
2351             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2352             break;
2353         }
2354
2355         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2356
2357         return 0;
2358 }
2359 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2360 {
2361         struct bnx2x *bp = params->bp;
2362
2363         REG_WR(bp, params->shmem_base +
2364                offsetof(struct shmem_region,
2365                         port_mb[params->port].link_status), link_status);
2366 }
2367
2368 static void bnx2x_update_pfc_nig(struct link_params *params,
2369                 struct link_vars *vars,
2370                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2371 {
2372         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2373         u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
2374         u32 pkt_priority_to_cos = 0;
2375         struct bnx2x *bp = params->bp;
2376         u8 port = params->port;
2377
2378         int set_pfc = params->feature_config_flags &
2379                 FEATURE_CONFIG_PFC_ENABLED;
2380         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2381
2382         /*
2383          * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2384          * MAC control frames (that are not pause packets)
2385          * will be forwarded to the XCM.
2386          */
2387         xcm_mask = REG_RD(bp,
2388                                 port ? NIG_REG_LLH1_XCM_MASK :
2389                                 NIG_REG_LLH0_XCM_MASK);
2390         /*
2391          * nig params will override non PFC params, since it's possible to
2392          * do transition from PFC to SAFC
2393          */
2394         if (set_pfc) {
2395                 pause_enable = 0;
2396                 llfc_out_en = 0;
2397                 llfc_enable = 0;
2398                 if (CHIP_IS_E3(bp))
2399                         ppp_enable = 0;
2400                 else
2401                 ppp_enable = 1;
2402                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2403                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2404                 xcm0_out_en = 0;
2405                 p0_hwpfc_enable = 1;
2406         } else  {
2407                 if (nig_params) {
2408                         llfc_out_en = nig_params->llfc_out_en;
2409                         llfc_enable = nig_params->llfc_enable;
2410                         pause_enable = nig_params->pause_enable;
2411                 } else  /*defaul non PFC mode - PAUSE */
2412                         pause_enable = 1;
2413
2414                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2415                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2416                 xcm0_out_en = 1;
2417         }
2418
2419         if (CHIP_IS_E3(bp))
2420                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2421                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2422         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2423                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2424         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2425                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2426         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2427                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2428
2429         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2430                NIG_REG_PPP_ENABLE_0, ppp_enable);
2431
2432         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2433                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2434
2435         REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2436
2437         /* output enable for RX_XCM # IF */
2438         REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
2439
2440         /* HW PFC TX enable */
2441         REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
2442
2443         if (nig_params) {
2444                 u8 i = 0;
2445                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2446
2447                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2448                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2449                 nig_params->rx_cos_priority_mask[i], port);
2450
2451                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2452                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2453                        nig_params->llfc_high_priority_classes);
2454
2455                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2456                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2457                        nig_params->llfc_low_priority_classes);
2458         }
2459         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2460                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2461                pkt_priority_to_cos);
2462 }
2463
2464 int bnx2x_update_pfc(struct link_params *params,
2465                       struct link_vars *vars,
2466                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2467 {
2468         /*
2469          * The PFC and pause are orthogonal to one another, meaning when
2470          * PFC is enabled, the pause are disabled, and when PFC is
2471          * disabled, pause are set according to the pause result.
2472          */
2473         u32 val;
2474         struct bnx2x *bp = params->bp;
2475         int bnx2x_status = 0;
2476         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2477
2478         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2479                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2480         else
2481                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2482
2483         bnx2x_update_mng(params, vars->link_status);
2484
2485         /* update NIG params */
2486         bnx2x_update_pfc_nig(params, vars, pfc_params);
2487
2488         /* update BRB params */
2489         bnx2x_status = bnx2x_update_pfc_brb(params, vars, pfc_params);
2490         if (0 != bnx2x_status)
2491                 return bnx2x_status;
2492
2493         if (!vars->link_up)
2494                 return bnx2x_status;
2495
2496         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2497         if (CHIP_IS_E3(bp))
2498                 bnx2x_update_pfc_xmac(params, vars, 0);
2499         else {
2500                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2501                 if ((val &
2502                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2503                     == 0) {
2504                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2505                         bnx2x_emac_enable(params, vars, 0);
2506                         return bnx2x_status;
2507                 }
2508
2509                 if (CHIP_IS_E2(bp))
2510                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2511                 else
2512                         bnx2x_update_pfc_bmac1(params, vars);
2513
2514                 val = 0;
2515                 if ((params->feature_config_flags &
2516                      FEATURE_CONFIG_PFC_ENABLED) ||
2517                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2518                         val = 1;
2519                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2520         }
2521         return bnx2x_status;
2522 }
2523
2524
2525 static int bnx2x_bmac1_enable(struct link_params *params,
2526                               struct link_vars *vars,
2527                               u8 is_lb)
2528 {
2529         struct bnx2x *bp = params->bp;
2530         u8 port = params->port;
2531         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2532                                NIG_REG_INGRESS_BMAC0_MEM;
2533         u32 wb_data[2];
2534         u32 val;
2535
2536         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2537
2538         /* XGXS control */
2539         wb_data[0] = 0x3c;
2540         wb_data[1] = 0;
2541         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2542                     wb_data, 2);
2543
2544         /* tx MAC SA */
2545         wb_data[0] = ((params->mac_addr[2] << 24) |
2546                        (params->mac_addr[3] << 16) |
2547                        (params->mac_addr[4] << 8) |
2548                         params->mac_addr[5]);
2549         wb_data[1] = ((params->mac_addr[0] << 8) |
2550                         params->mac_addr[1]);
2551         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2552
2553         /* mac control */
2554         val = 0x3;
2555         if (is_lb) {
2556                 val |= 0x4;
2557                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2558         }
2559         wb_data[0] = val;
2560         wb_data[1] = 0;
2561         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2562
2563         /* set rx mtu */
2564         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2565         wb_data[1] = 0;
2566         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2567
2568         bnx2x_update_pfc_bmac1(params, vars);
2569
2570         /* set tx mtu */
2571         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2572         wb_data[1] = 0;
2573         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2574
2575         /* set cnt max size */
2576         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2577         wb_data[1] = 0;
2578         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2579
2580         /* configure safc */
2581         wb_data[0] = 0x1000200;
2582         wb_data[1] = 0;
2583         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2584                     wb_data, 2);
2585
2586         if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2587                 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LSS_STATUS,
2588                             wb_data, 2);
2589                 if (wb_data[0] > 0)
2590                         return -ESRCH;
2591         }
2592         return 0;
2593 }
2594
2595 static int bnx2x_bmac2_enable(struct link_params *params,
2596                               struct link_vars *vars,
2597                               u8 is_lb)
2598 {
2599         struct bnx2x *bp = params->bp;
2600         u8 port = params->port;
2601         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2602                                NIG_REG_INGRESS_BMAC0_MEM;
2603         u32 wb_data[2];
2604
2605         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2606
2607         wb_data[0] = 0;
2608         wb_data[1] = 0;
2609         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2610         udelay(30);
2611
2612         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2613         wb_data[0] = 0x3c;
2614         wb_data[1] = 0;
2615         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2616                     wb_data, 2);
2617
2618         udelay(30);
2619
2620         /* tx MAC SA */
2621         wb_data[0] = ((params->mac_addr[2] << 24) |
2622                        (params->mac_addr[3] << 16) |
2623                        (params->mac_addr[4] << 8) |
2624                         params->mac_addr[5]);
2625         wb_data[1] = ((params->mac_addr[0] << 8) |
2626                         params->mac_addr[1]);
2627         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2628                     wb_data, 2);
2629
2630         udelay(30);
2631
2632         /* Configure SAFC */
2633         wb_data[0] = 0x1000200;
2634         wb_data[1] = 0;
2635         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2636                     wb_data, 2);
2637         udelay(30);
2638
2639         /* set rx mtu */
2640         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2641         wb_data[1] = 0;
2642         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2643         udelay(30);
2644
2645         /* set tx mtu */
2646         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2647         wb_data[1] = 0;
2648         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2649         udelay(30);
2650         /* set cnt max size */
2651         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2652         wb_data[1] = 0;
2653         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2654         udelay(30);
2655         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2656
2657         if (vars->phy_flags & PHY_TX_ERROR_CHECK_FLAG) {
2658                 REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LSS_STAT,
2659                             wb_data, 2);
2660                 if (wb_data[0] > 0) {
2661                         DP(NETIF_MSG_LINK, "Got bad LSS status 0x%x\n",
2662                                        wb_data[0]);
2663                         return -ESRCH;
2664                 }
2665         }
2666
2667         return 0;
2668 }
2669
2670 static int bnx2x_bmac_enable(struct link_params *params,
2671                              struct link_vars *vars,
2672                              u8 is_lb)
2673 {
2674         int rc = 0;
2675         u8 port = params->port;
2676         struct bnx2x *bp = params->bp;
2677         u32 val;
2678         /* reset and unreset the BigMac */
2679         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2680                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2681         msleep(1);
2682
2683         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2684                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2685
2686         /* enable access for bmac registers */
2687         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2688
2689         /* Enable BMAC according to BMAC type*/
2690         if (CHIP_IS_E2(bp))
2691                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2692         else
2693                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2694         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2695         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2696         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2697         val = 0;
2698         if ((params->feature_config_flags &
2699               FEATURE_CONFIG_PFC_ENABLED) ||
2700             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2701                 val = 1;
2702         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2703         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2704         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2705         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2706         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2707         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2708
2709         vars->mac_type = MAC_TYPE_BMAC;
2710         return rc;
2711 }
2712
2713 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
2714 {
2715         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2716                         NIG_REG_INGRESS_BMAC0_MEM;
2717         u32 wb_data[2];
2718         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2719
2720         /* Only if the bmac is out of reset */
2721         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2722                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2723             nig_bmac_enable) {
2724
2725                 if (CHIP_IS_E2(bp)) {
2726                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2727                         REG_RD_DMAE(bp, bmac_addr +
2728                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2729                                     wb_data, 2);
2730                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2731                         REG_WR_DMAE(bp, bmac_addr +
2732                                     BIGMAC2_REGISTER_BMAC_CONTROL,
2733                                     wb_data, 2);
2734                 } else {
2735                         /* Clear Rx Enable bit in BMAC_CONTROL register */
2736                         REG_RD_DMAE(bp, bmac_addr +
2737                                         BIGMAC_REGISTER_BMAC_CONTROL,
2738                                         wb_data, 2);
2739                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2740                         REG_WR_DMAE(bp, bmac_addr +
2741                                         BIGMAC_REGISTER_BMAC_CONTROL,
2742                                         wb_data, 2);
2743                 }
2744                 msleep(1);
2745         }
2746 }
2747
2748 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2749                             u32 line_speed)
2750 {
2751         struct bnx2x *bp = params->bp;
2752         u8 port = params->port;
2753         u32 init_crd, crd;
2754         u32 count = 1000;
2755
2756         /* disable port */
2757         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2758
2759         /* wait for init credit */
2760         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2761         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2762         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2763
2764         while ((init_crd != crd) && count) {
2765                 msleep(5);
2766
2767                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2768                 count--;
2769         }
2770         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2771         if (init_crd != crd) {
2772                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2773                           init_crd, crd);
2774                 return -EINVAL;
2775         }
2776
2777         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2778             line_speed == SPEED_10 ||
2779             line_speed == SPEED_100 ||
2780             line_speed == SPEED_1000 ||
2781             line_speed == SPEED_2500) {
2782                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2783                 /* update threshold */
2784                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2785                 /* update init credit */
2786                 init_crd = 778;         /* (800-18-4) */
2787
2788         } else {
2789                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2790                               ETH_OVREHEAD)/16;
2791                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2792                 /* update threshold */
2793                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2794                 /* update init credit */
2795                 switch (line_speed) {
2796                 case SPEED_10000:
2797                         init_crd = thresh + 553 - 22;
2798                         break;
2799                 default:
2800                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2801                                   line_speed);
2802                         return -EINVAL;
2803                 }
2804         }
2805         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2806         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2807                  line_speed, init_crd);
2808
2809         /* probe the credit changes */
2810         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2811         msleep(5);
2812         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2813
2814         /* enable port */
2815         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2816         return 0;
2817 }
2818
2819 /**
2820  * bnx2x_get_emac_base - retrive emac base address
2821  *
2822  * @bp:                 driver handle
2823  * @mdc_mdio_access:    access type
2824  * @port:               port id
2825  *
2826  * This function selects the MDC/MDIO access (through emac0 or
2827  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2828  * phy has a default access mode, which could also be overridden
2829  * by nvram configuration. This parameter, whether this is the
2830  * default phy configuration, or the nvram overrun
2831  * configuration, is passed here as mdc_mdio_access and selects
2832  * the emac_base for the CL45 read/writes operations
2833  */
2834 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2835                                u32 mdc_mdio_access, u8 port)
2836 {
2837         u32 emac_base = 0;
2838         switch (mdc_mdio_access) {
2839         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2840                 break;
2841         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2842                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2843                         emac_base = GRCBASE_EMAC1;
2844                 else
2845                         emac_base = GRCBASE_EMAC0;
2846                 break;
2847         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2848                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2849                         emac_base = GRCBASE_EMAC0;
2850                 else
2851                         emac_base = GRCBASE_EMAC1;
2852                 break;
2853         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2854                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2855                 break;
2856         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2857                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2858                 break;
2859         default:
2860                 break;
2861         }
2862         return emac_base;
2863
2864 }
2865
2866 /******************************************************************/
2867 /*                      CL22 access functions                     */
2868 /******************************************************************/
2869 static int bnx2x_cl22_write(struct bnx2x *bp,
2870                                        struct bnx2x_phy *phy,
2871                                        u16 reg, u16 val)
2872 {
2873         u32 tmp, mode;
2874         u8 i;
2875         int rc = 0;
2876         /* Switch to CL22 */
2877         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2878         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2879                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2880
2881         /* address */
2882         tmp = ((phy->addr << 21) | (reg << 16) | val |
2883                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2884                EMAC_MDIO_COMM_START_BUSY);
2885         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2886
2887         for (i = 0; i < 50; i++) {
2888                 udelay(10);
2889
2890                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2891                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2892                         udelay(5);
2893                         break;
2894                 }
2895         }
2896         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2897                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2898                 rc = -EFAULT;
2899         }
2900         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2901         return rc;
2902 }
2903
2904 static int bnx2x_cl22_read(struct bnx2x *bp,
2905                                       struct bnx2x_phy *phy,
2906                                       u16 reg, u16 *ret_val)
2907 {
2908         u32 val, mode;
2909         u16 i;
2910         int rc = 0;
2911
2912         /* Switch to CL22 */
2913         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2914         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2915                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2916
2917         /* address */
2918         val = ((phy->addr << 21) | (reg << 16) |
2919                EMAC_MDIO_COMM_COMMAND_READ_22 |
2920                EMAC_MDIO_COMM_START_BUSY);
2921         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2922
2923         for (i = 0; i < 50; i++) {
2924                 udelay(10);
2925
2926                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2927                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2928                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2929                         udelay(5);
2930                         break;
2931                 }
2932         }
2933         if (val & EMAC_MDIO_COMM_START_BUSY) {
2934                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2935
2936                 *ret_val = 0;
2937                 rc = -EFAULT;
2938         }
2939         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2940         return rc;
2941 }
2942
2943 /******************************************************************/
2944 /*                      CL45 access functions                     */
2945 /******************************************************************/
2946 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2947                            u8 devad, u16 reg, u16 *ret_val)
2948 {
2949         u32 val;
2950         u16 i;
2951         int rc = 0;
2952
2953         /* address */
2954         val = ((phy->addr << 21) | (devad << 16) | reg |
2955                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2956                EMAC_MDIO_COMM_START_BUSY);
2957         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2958
2959         for (i = 0; i < 50; i++) {
2960                 udelay(10);
2961
2962                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2963                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2964                         udelay(5);
2965                         break;
2966                 }
2967         }
2968         if (val & EMAC_MDIO_COMM_START_BUSY) {
2969                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2970                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2971                 *ret_val = 0;
2972                 rc = -EFAULT;
2973         } else {
2974                 /* data */
2975                 val = ((phy->addr << 21) | (devad << 16) |
2976                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2977                        EMAC_MDIO_COMM_START_BUSY);
2978                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2979
2980                 for (i = 0; i < 50; i++) {
2981                         udelay(10);
2982
2983                         val = REG_RD(bp, phy->mdio_ctrl +
2984                                      EMAC_REG_EMAC_MDIO_COMM);
2985                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2986                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2987                                 break;
2988                         }
2989                 }
2990                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2991                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2992                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2993                         *ret_val = 0;
2994                         rc = -EFAULT;
2995                 }
2996         }
2997         /* Work around for E3 A0 */
2998         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2999                 phy->flags ^= FLAGS_DUMMY_READ;
3000                 if (phy->flags & FLAGS_DUMMY_READ) {
3001                         u16 temp_val;
3002                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3003                 }
3004         }
3005
3006         return rc;
3007 }
3008
3009 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3010                             u8 devad, u16 reg, u16 val)
3011 {
3012         u32 tmp;
3013         u8 i;
3014         int rc = 0;
3015
3016         /* address */
3017
3018         tmp = ((phy->addr << 21) | (devad << 16) | reg |
3019                EMAC_MDIO_COMM_COMMAND_ADDRESS |
3020                EMAC_MDIO_COMM_START_BUSY);
3021         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3022
3023         for (i = 0; i < 50; i++) {
3024                 udelay(10);
3025
3026                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3027                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3028                         udelay(5);
3029                         break;
3030                 }
3031         }
3032         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3033                 DP(NETIF_MSG_LINK, "write phy register failed\n");
3034                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3035                 rc = -EFAULT;
3036
3037         } else {
3038                 /* data */
3039                 tmp = ((phy->addr << 21) | (devad << 16) | val |
3040                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3041                        EMAC_MDIO_COMM_START_BUSY);
3042                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3043
3044                 for (i = 0; i < 50; i++) {
3045                         udelay(10);
3046
3047                         tmp = REG_RD(bp, phy->mdio_ctrl +
3048                                      EMAC_REG_EMAC_MDIO_COMM);
3049                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3050                                 udelay(5);
3051                                 break;
3052                         }
3053                 }
3054                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3055                         DP(NETIF_MSG_LINK, "write phy register failed\n");
3056                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
3057                         rc = -EFAULT;
3058                 }
3059         }
3060         /* Work around for E3 A0 */
3061         if (phy->flags & FLAGS_MDC_MDIO_WA) {
3062                 phy->flags ^= FLAGS_DUMMY_READ;
3063                 if (phy->flags & FLAGS_DUMMY_READ) {
3064                         u16 temp_val;
3065                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
3066                 }
3067         }
3068
3069         return rc;
3070 }
3071
3072
3073 /******************************************************************/
3074 /*                      BSC access functions from E3              */
3075 /******************************************************************/
3076 static void bnx2x_bsc_module_sel(struct link_params *params)
3077 {
3078         int idx;
3079         u32 board_cfg, sfp_ctrl;
3080         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3081         struct bnx2x *bp = params->bp;
3082         u8 port = params->port;
3083         /* Read I2C output PINs */
3084         board_cfg = REG_RD(bp, params->shmem_base +
3085                            offsetof(struct shmem_region,
3086                                     dev_info.shared_hw_config.board));
3087         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3088         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3089                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3090
3091         /* Read I2C output value */
3092         sfp_ctrl = REG_RD(bp, params->shmem_base +
3093                           offsetof(struct shmem_region,
3094                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3095         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3096         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3097         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3098         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3099                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3100 }
3101
3102 static int bnx2x_bsc_read(struct link_params *params,
3103                           struct bnx2x_phy *phy,
3104                           u8 sl_devid,
3105                           u16 sl_addr,
3106                           u8 lc_addr,
3107                           u8 xfer_cnt,
3108                           u32 *data_array)
3109 {
3110         u32 val, i;
3111         int rc = 0;
3112         struct bnx2x *bp = params->bp;
3113
3114         if ((sl_devid != 0xa0) && (sl_devid != 0xa2)) {
3115                 DP(NETIF_MSG_LINK, "invalid sl_devid 0x%x\n", sl_devid);
3116                 return -EINVAL;
3117         }
3118
3119         if (xfer_cnt > 16) {
3120                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3121                                         xfer_cnt);
3122                 return -EINVAL;
3123         }
3124         bnx2x_bsc_module_sel(params);
3125
3126         xfer_cnt = 16 - lc_addr;
3127
3128         /* enable the engine */
3129         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3130         val |= MCPR_IMC_COMMAND_ENABLE;
3131         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3132
3133         /* program slave device ID */
3134         val = (sl_devid << 16) | sl_addr;
3135         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3136
3137         /* start xfer with 0 byte to update the address pointer ???*/
3138         val = (MCPR_IMC_COMMAND_ENABLE) |
3139               (MCPR_IMC_COMMAND_WRITE_OP <<
3140                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3141                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3142         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3143
3144         /* poll for completion */
3145         i = 0;
3146         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3147         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3148                 udelay(10);
3149                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3150                 if (i++ > 1000) {
3151                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3152                                                                 i);
3153                         rc = -EFAULT;
3154                         break;
3155                 }
3156         }
3157         if (rc == -EFAULT)
3158                 return rc;
3159
3160         /* start xfer with read op */
3161         val = (MCPR_IMC_COMMAND_ENABLE) |
3162                 (MCPR_IMC_COMMAND_READ_OP <<
3163                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3164                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3165                   (xfer_cnt);
3166         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3167
3168         /* poll for completion */
3169         i = 0;
3170         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3171         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3172                 udelay(10);
3173                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3174                 if (i++ > 1000) {
3175                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3176                         rc = -EFAULT;
3177                         break;
3178                 }
3179         }
3180         if (rc == -EFAULT)
3181                 return rc;
3182
3183         for (i = (lc_addr >> 2); i < 4; i++) {
3184                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3185 #ifdef __BIG_ENDIAN
3186                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3187                                 ((data_array[i] & 0x0000ff00) << 8) |
3188                                 ((data_array[i] & 0x00ff0000) >> 8) |
3189                                 ((data_array[i] & 0xff000000) >> 24);
3190 #endif
3191         }
3192         return rc;
3193 }
3194
3195 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3196                                      u8 devad, u16 reg, u16 or_val)
3197 {
3198         u16 val;
3199         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3200         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3201 }
3202
3203 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3204                    u8 devad, u16 reg, u16 *ret_val)
3205 {
3206         u8 phy_index;
3207         /*
3208          * Probe for the phy according to the given phy_addr, and execute
3209          * the read request on it
3210          */
3211         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3212                 if (params->phy[phy_index].addr == phy_addr) {
3213                         return bnx2x_cl45_read(params->bp,
3214                                                &params->phy[phy_index], devad,
3215                                                reg, ret_val);
3216                 }
3217         }
3218         return -EINVAL;
3219 }
3220
3221 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3222                     u8 devad, u16 reg, u16 val)
3223 {
3224         u8 phy_index;
3225         /*
3226          * Probe for the phy according to the given phy_addr, and execute
3227          * the write request on it
3228          */
3229         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3230                 if (params->phy[phy_index].addr == phy_addr) {
3231                         return bnx2x_cl45_write(params->bp,
3232                                                 &params->phy[phy_index], devad,
3233                                                 reg, val);
3234                 }
3235         }
3236         return -EINVAL;
3237 }
3238 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3239                                   struct link_params *params)
3240 {
3241         u8 lane = 0;
3242         struct bnx2x *bp = params->bp;
3243         u32 path_swap, path_swap_ovr;
3244         u8 path, port;
3245
3246         path = BP_PATH(bp);
3247         port = params->port;
3248
3249         if (bnx2x_is_4_port_mode(bp)) {
3250                 u32 port_swap, port_swap_ovr;
3251
3252                 /*figure out path swap value */
3253                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3254                 if (path_swap_ovr & 0x1)
3255                         path_swap = (path_swap_ovr & 0x2);
3256                 else
3257                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3258
3259                 if (path_swap)
3260                         path = path ^ 1;
3261
3262                 /*figure out port swap value */
3263                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3264                 if (port_swap_ovr & 0x1)
3265                         port_swap = (port_swap_ovr & 0x2);
3266                 else
3267                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3268
3269                 if (port_swap)
3270                         port = port ^ 1;
3271
3272                 lane = (port<<1) + path;
3273         } else { /* two port mode - no port swap */
3274
3275                 /*figure out path swap value */
3276                 path_swap_ovr =
3277                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3278                 if (path_swap_ovr & 0x1) {
3279                         path_swap = (path_swap_ovr & 0x2);
3280                 } else {
3281                         path_swap =
3282                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3283                 }
3284                 if (path_swap)
3285                         path = path ^ 1;
3286
3287                 lane = path << 1 ;
3288         }
3289         return lane;
3290 }
3291
3292 static void bnx2x_set_aer_mmd(struct link_params *params,
3293                               struct bnx2x_phy *phy)
3294 {
3295         u32 ser_lane;
3296         u16 offset, aer_val;
3297         struct bnx2x *bp = params->bp;
3298         ser_lane = ((params->lane_config &
3299                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3300                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3301
3302         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3303                 (phy->addr + ser_lane) : 0;
3304
3305         if (USES_WARPCORE(bp)) {
3306                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3307                 /*
3308                  * In Dual-lane mode, two lanes are joined together,
3309                  * so in order to configure them, the AER broadcast method is
3310                  * used here.
3311                  * 0x200 is the broadcast address for lanes 0,1
3312                  * 0x201 is the broadcast address for lanes 2,3
3313                  */
3314                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3315                         aer_val = (aer_val >> 1) | 0x200;
3316         } else if (CHIP_IS_E2(bp))
3317                 aer_val = 0x3800 + offset - 1;
3318         else
3319                 aer_val = 0x3800 + offset;
3320         DP(NETIF_MSG_LINK, "Set AER to 0x%x\n", aer_val);
3321         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3322                           MDIO_AER_BLOCK_AER_REG, aer_val);
3323
3324 }
3325
3326 /******************************************************************/
3327 /*                      Internal phy section                      */
3328 /******************************************************************/
3329
3330 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3331 {
3332         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3333
3334         /* Set Clause 22 */
3335         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3336         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3337         udelay(500);
3338         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3339         udelay(500);
3340          /* Set Clause 45 */
3341         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3342 }
3343
3344 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3345 {
3346         u32 val;
3347
3348         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3349
3350         val = SERDES_RESET_BITS << (port*16);
3351
3352         /* reset and unreset the SerDes/XGXS */
3353         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3354         udelay(500);
3355         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3356
3357         bnx2x_set_serdes_access(bp, port);
3358
3359         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3360                DEFAULT_PHY_DEV_ADDR);
3361 }
3362
3363 static void bnx2x_xgxs_deassert(struct link_params *params)
3364 {
3365         struct bnx2x *bp = params->bp;
3366         u8 port;
3367         u32 val;
3368         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3369         port = params->port;
3370
3371         val = XGXS_RESET_BITS << (port*16);
3372
3373         /* reset and unreset the SerDes/XGXS */
3374         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3375         udelay(500);
3376         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3377
3378         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 0);
3379         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3380                params->phy[INT_PHY].def_md_devad);
3381 }
3382
3383 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3384                                      struct link_params *params, u16 *ieee_fc)
3385 {
3386         struct bnx2x *bp = params->bp;
3387         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3388         /**
3389          * resolve pause mode and advertisement Please refer to Table
3390          * 28B-3 of the 802.3ab-1999 spec
3391          */
3392
3393         switch (phy->req_flow_ctrl) {
3394         case BNX2X_FLOW_CTRL_AUTO:
3395                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH)
3396                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3397                 else
3398                         *ieee_fc |=
3399                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3400                 break;
3401
3402         case BNX2X_FLOW_CTRL_TX:
3403                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3404                 break;
3405
3406         case BNX2X_FLOW_CTRL_RX:
3407         case BNX2X_FLOW_CTRL_BOTH:
3408                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3409                 break;
3410
3411         case BNX2X_FLOW_CTRL_NONE:
3412         default:
3413                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3414                 break;
3415         }
3416         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3417 }
3418
3419 static void set_phy_vars(struct link_params *params,
3420                          struct link_vars *vars)
3421 {
3422         struct bnx2x *bp = params->bp;
3423         u8 actual_phy_idx, phy_index, link_cfg_idx;
3424         u8 phy_config_swapped = params->multi_phy_config &
3425                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3426         for (phy_index = INT_PHY; phy_index < params->num_phys;
3427               phy_index++) {
3428                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3429                 actual_phy_idx = phy_index;
3430                 if (phy_config_swapped) {
3431                         if (phy_index == EXT_PHY1)
3432                                 actual_phy_idx = EXT_PHY2;
3433                         else if (phy_index == EXT_PHY2)
3434                                 actual_phy_idx = EXT_PHY1;
3435                 }
3436                 params->phy[actual_phy_idx].req_flow_ctrl =
3437                         params->req_flow_ctrl[link_cfg_idx];
3438
3439                 params->phy[actual_phy_idx].req_line_speed =
3440                         params->req_line_speed[link_cfg_idx];
3441
3442                 params->phy[actual_phy_idx].speed_cap_mask =
3443                         params->speed_cap_mask[link_cfg_idx];
3444
3445                 params->phy[actual_phy_idx].req_duplex =
3446                         params->req_duplex[link_cfg_idx];
3447
3448                 if (params->req_line_speed[link_cfg_idx] ==
3449                     SPEED_AUTO_NEG)
3450                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3451
3452                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3453                            " speed_cap_mask %x\n",
3454                            params->phy[actual_phy_idx].req_flow_ctrl,
3455                            params->phy[actual_phy_idx].req_line_speed,
3456                            params->phy[actual_phy_idx].speed_cap_mask);
3457         }
3458 }
3459
3460 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3461                                     struct bnx2x_phy *phy,
3462                                     struct link_vars *vars)
3463 {
3464         u16 val;
3465         struct bnx2x *bp = params->bp;
3466         /* read modify write pause advertizing */
3467         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3468
3469         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3470
3471         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3472         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3473         if ((vars->ieee_fc &
3474             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3475             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3476                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3477         }
3478         if ((vars->ieee_fc &
3479             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3480             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3481                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3482         }
3483         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3484         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3485 }
3486
3487 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3488 {                                               /*  LD      LP   */
3489         switch (pause_result) {                 /* ASYM P ASYM P */
3490         case 0xb:                               /*   1  0   1  1 */
3491                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3492                 break;
3493
3494         case 0xe:                               /*   1  1   1  0 */
3495                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3496                 break;
3497
3498         case 0x5:                               /*   0  1   0  1 */
3499         case 0x7:                               /*   0  1   1  1 */
3500         case 0xd:                               /*   1  1   0  1 */
3501         case 0xf:                               /*   1  1   1  1 */
3502                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3503                 break;
3504
3505         default:
3506                 break;
3507         }
3508         if (pause_result & (1<<0))
3509                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3510         if (pause_result & (1<<1))
3511                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3512 }
3513
3514 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3515                                    struct link_params *params,
3516                                    struct link_vars *vars)
3517 {
3518         struct bnx2x *bp = params->bp;
3519         u16 ld_pause;           /* local */
3520         u16 lp_pause;           /* link partner */
3521         u16 pause_result;
3522         u8 ret = 0;
3523         /* read twice */
3524
3525         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3526
3527         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
3528                 vars->flow_ctrl = phy->req_flow_ctrl;
3529         else if (phy->req_line_speed != SPEED_AUTO_NEG)
3530                 vars->flow_ctrl = params->req_fc_auto_adv;
3531         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3532                 ret = 1;
3533                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3534                         bnx2x_cl22_read(bp, phy,
3535                                         0x4, &ld_pause);
3536                         bnx2x_cl22_read(bp, phy,
3537                                         0x5, &lp_pause);
3538                 } else {
3539                         bnx2x_cl45_read(bp, phy,
3540                                         MDIO_AN_DEVAD,
3541                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3542                         bnx2x_cl45_read(bp, phy,
3543                                         MDIO_AN_DEVAD,
3544                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3545                 }
3546                 pause_result = (ld_pause &
3547                                 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3548                 pause_result |= (lp_pause &
3549                                  MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3550                 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n",
3551                    pause_result);
3552                 bnx2x_pause_resolve(vars, pause_result);
3553         }
3554         return ret;
3555 }
3556 /******************************************************************/
3557 /*                      Warpcore section                          */
3558 /******************************************************************/
3559 /* The init_internal_warpcore should mirror the xgxs,
3560  * i.e. reset the lane (if needed), set aer for the
3561  * init configuration, and set/clear SGMII flag. Internal
3562  * phy init is done purely in phy_init stage.
3563  */
3564 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3565                                         struct link_params *params,
3566                                         struct link_vars *vars) {
3567         u16 val16 = 0, lane, bam37 = 0;
3568         struct bnx2x *bp = params->bp;
3569         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3570         /* Check adding advertisement for 1G KX */
3571         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3572              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3573             (vars->line_speed == SPEED_1000)) {
3574                 u16 sd_digital;
3575                 val16 |= (1<<5);
3576
3577                 /* Enable CL37 1G Parallel Detect */
3578                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3579                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &sd_digital);
3580                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3581                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3582                                  (sd_digital | 0x1));
3583
3584                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3585         }
3586         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3587              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3588             (vars->line_speed ==  SPEED_10000)) {
3589                 /* Check adding advertisement for 10G KR */
3590                 val16 |= (1<<7);
3591                 /* Enable 10G Parallel Detect */
3592                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3593                                 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3594
3595                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3596         }
3597
3598         /* Set Transmit PMD settings */
3599         lane = bnx2x_get_warpcore_lane(phy, params);
3600         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3601                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3602                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3603                       (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3604                       (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3605         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3606                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3607                          0x03f0);
3608         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3609                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3610                          0x03f0);
3611         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3612                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3613                          0x383f);
3614
3615         /* Advertised speeds */
3616         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3617                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16);
3618
3619         /* Enable CL37 BAM */
3620         if (REG_RD(bp, params->shmem_base +
3621                    offsetof(struct shmem_region, dev_info.
3622                             port_hw_config[params->port].default_cfg)) &
3623             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3624                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3625                                 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, &bam37);
3626                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3627                         MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, bam37 | 1);
3628                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3629         }
3630
3631         /* Advertise pause */
3632         bnx2x_ext_phy_set_pause(params, phy, vars);
3633
3634         /* Enable Autoneg */
3635         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3636                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3637
3638         /* Over 1G - AN local device user page 1 */
3639         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3640                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3641
3642         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3643                         MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3644
3645         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3646                          MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3647 }
3648
3649 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3650                                       struct link_params *params,
3651                                       struct link_vars *vars)
3652 {
3653         struct bnx2x *bp = params->bp;
3654         u16 val;
3655
3656         /* Disable Autoneg */
3657         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3658                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7);
3659
3660         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3661                          MDIO_WC_REG_PAR_DET_10G_CTRL, 0);
3662
3663         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3664                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 0x3f00);
3665
3666         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3667                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0);
3668
3669         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3670                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3671
3672         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3673                         MDIO_WC_REG_DIGITAL3_UP1, 0x1);
3674
3675         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3676                          MDIO_WC_REG_DIGITAL5_MISC7, 0xa);
3677
3678         /* Disable CL36 PCS Tx */
3679         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3680                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, 0x0);
3681
3682         /* Double Wide Single Data Rate @ pll rate */
3683         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3684                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, 0xFFFF);
3685
3686         /* Leave cl72 training enable, needed for KR */
3687         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3688                 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150,
3689                 0x2);
3690
3691         /* Leave CL72 enabled */
3692         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3693                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3694                          &val);
3695         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3696                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3697                          val | 0x3800);
3698
3699         /* Set speed via PMA/PMD register */
3700         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3701                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3702
3703         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3704                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3705
3706         /*Enable encoded forced speed */
3707         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3708                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3709
3710         /* Turn TX scramble payload only the 64/66 scrambler */
3711         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3712                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3713
3714         /* Turn RX scramble payload only the 64/66 scrambler */
3715         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3716                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3717
3718         /* set and clear loopback to cause a reset to 64/66 decoder */
3719         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3720                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3721         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3722                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3723
3724 }
3725
3726 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3727                                        struct link_params *params,
3728                                        u8 is_xfi)
3729 {
3730         struct bnx2x *bp = params->bp;
3731         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3732         /* Hold rxSeqStart */
3733         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3734                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3735         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3736                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val | 0x8000));
3737
3738         /* Hold tx_fifo_reset */
3739         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3740                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3741         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3742                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, (val | 0x1));
3743
3744         /* Disable CL73 AN */
3745         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3746
3747         /* Disable 100FX Enable and Auto-Detect */
3748         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3749                         MDIO_WC_REG_FX100_CTRL1, &val);
3750         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3751                          MDIO_WC_REG_FX100_CTRL1, (val & 0xFFFA));
3752
3753         /* Disable 100FX Idle detect */
3754         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3755                         MDIO_WC_REG_FX100_CTRL3, &val);
3756         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3757                          MDIO_WC_REG_FX100_CTRL3, (val | 0x0080));
3758
3759         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3760         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3761                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3762         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3763                          MDIO_WC_REG_DIGITAL4_MISC3, (val & 0xFF7F));
3764
3765         /* Turn off auto-detect & fiber mode */
3766         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3767                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3768         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3769                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3770                          (val & 0xFFEE));
3771
3772         /* Set filter_force_link, disable_false_link and parallel_detect */
3773         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3774                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3775         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3776                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3777                          ((val | 0x0006) & 0xFFFE));
3778
3779         /* Set XFI / SFI */
3780         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3781                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3782
3783         misc1_val &= ~(0x1f);
3784
3785         if (is_xfi) {
3786                 misc1_val |= 0x5;
3787                 tap_val = ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3788                            (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3789                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3790                 tx_driver_val =
3791                       ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3792                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3793                        (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3794
3795         } else {
3796                 misc1_val |= 0x9;
3797                 tap_val = ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3798                            (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3799                            (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET));
3800                 tx_driver_val =
3801                       ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3802                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3803                        (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET));
3804         }
3805         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3806                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
3807
3808         /* Set Transmit PMD settings */
3809         lane = bnx2x_get_warpcore_lane(phy, params);
3810         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3811                          MDIO_WC_REG_TX_FIR_TAP,
3812                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
3813         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3814                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3815                          tx_driver_val);
3816
3817         /* Enable fiber mode, enable and invert sig_det */
3818         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3819                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &val);
3820         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3821                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, val | 0xd);
3822
3823         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
3824         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3825                         MDIO_WC_REG_DIGITAL4_MISC3, &val);
3826         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3827                          MDIO_WC_REG_DIGITAL4_MISC3, val | 0x8080);
3828
3829         /* 10G XFI Full Duplex */
3830         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3831                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
3832
3833         /* Release tx_fifo_reset */
3834         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3835                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, &val);
3836         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3837                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, val & 0xFFFE);
3838
3839         /* Release rxSeqStart */
3840         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3841                         MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, &val);
3842         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3843                          MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, (val & 0x7FFF));
3844 }
3845
3846 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x *bp,
3847                                        struct bnx2x_phy *phy)
3848 {
3849         DP(NETIF_MSG_LINK, "KR2 still not supported !!!\n");
3850 }
3851
3852 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
3853                                          struct bnx2x_phy *phy,
3854                                          u16 lane)
3855 {
3856         /* Rx0 anaRxControl1G */
3857         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3858                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
3859
3860         /* Rx2 anaRxControl1G */
3861         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3862                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
3863
3864         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3865                          MDIO_WC_REG_RX66_SCW0, 0xE070);
3866
3867         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3868                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
3869
3870         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3871                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
3872
3873         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3874                          MDIO_WC_REG_RX66_SCW3, 0x8090);
3875
3876         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3877                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
3878
3879         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3880                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
3881
3882         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3883                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
3884
3885         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3886                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
3887
3888         /* Serdes Digital Misc1 */
3889         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3890                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
3891
3892         /* Serdes Digital4 Misc3 */
3893         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3894                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
3895
3896         /* Set Transmit PMD settings */
3897         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3898                          MDIO_WC_REG_TX_FIR_TAP,
3899                         ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) |
3900                          (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) |
3901                          (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET) |
3902                          MDIO_WC_REG_TX_FIR_TAP_ENABLE));
3903         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3904                       MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3905                      ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) |
3906                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) |
3907                       (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)));
3908 }
3909
3910 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
3911                                            struct link_params *params,
3912                                            u8 fiber_mode)
3913 {
3914         struct bnx2x *bp = params->bp;
3915         u16 val16, digctrl_kx1, digctrl_kx2;
3916         u8 lane;
3917
3918         lane = bnx2x_get_warpcore_lane(phy, params);
3919
3920         /* Clear XFI clock comp in non-10G single lane mode. */
3921         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3922                         MDIO_WC_REG_RX66_CONTROL, &val16);
3923         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3924                          MDIO_WC_REG_RX66_CONTROL, val16 & ~(3<<13));
3925
3926         if (phy->req_line_speed == SPEED_AUTO_NEG) {
3927                 /* SGMII Autoneg */
3928                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3929                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3930                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3931                                  MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
3932                                  val16 | 0x1000);
3933                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
3934         } else {
3935                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3936                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3937                 val16 &= 0xcfbf;
3938                 switch (phy->req_line_speed) {
3939                 case SPEED_10:
3940                         break;
3941                 case SPEED_100:
3942                         val16 |= 0x2000;
3943                         break;
3944                 case SPEED_1000:
3945                         val16 |= 0x0040;
3946                         break;
3947                 default:
3948                         DP(NETIF_MSG_LINK, "Speed not supported: 0x%x"
3949                                            "\n", phy->req_line_speed);
3950                         return;
3951                 }
3952
3953                 if (phy->req_duplex == DUPLEX_FULL)
3954                         val16 |= 0x0100;
3955
3956                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3957                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
3958
3959                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
3960                                phy->req_line_speed);
3961                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3962                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
3963                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
3964         }
3965
3966         /* SGMII Slave mode and disable signal detect */
3967         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3968                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
3969         if (fiber_mode)
3970                 digctrl_kx1 = 1;
3971         else
3972                 digctrl_kx1 &= 0xff4a;
3973
3974         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3975                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3976                         digctrl_kx1);
3977
3978         /* Turn off parallel detect */
3979         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3980                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
3981         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3982                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3983                         (digctrl_kx2 & ~(1<<2)));
3984
3985         /* Re-enable parallel detect */
3986         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3987                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3988                         (digctrl_kx2 | (1<<2)));
3989
3990         /* Enable autodet */
3991         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3992                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3993                         (digctrl_kx1 | 0x10));
3994 }
3995
3996 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
3997                                       struct bnx2x_phy *phy,
3998                                       u8 reset)
3999 {
4000         u16 val;
4001         /* Take lane out of reset after configuration is finished */
4002         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4003                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4004         if (reset)
4005                 val |= 0xC000;
4006         else
4007                 val &= 0x3FFF;
4008         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4009                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4010         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4011                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4012 }
4013
4014
4015         /* Clear SFI/XFI link settings registers */
4016 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4017                                       struct link_params *params,
4018                                       u16 lane)
4019 {
4020         struct bnx2x *bp = params->bp;
4021         u16 val16;
4022
4023         /* Set XFI clock comp as default. */
4024         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4025                         MDIO_WC_REG_RX66_CONTROL, &val16);
4026         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4027                          MDIO_WC_REG_RX66_CONTROL, val16 | (3<<13));
4028
4029         bnx2x_warpcore_reset_lane(bp, phy, 1);
4030         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4031         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4032                          MDIO_WC_REG_FX100_CTRL1, 0x014a);
4033         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4034                          MDIO_WC_REG_FX100_CTRL3, 0x0800);
4035         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4036                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8008);
4037         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4038                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x0195);
4039         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4040                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x0007);
4041         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4042                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x0002);
4043         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4044                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000);
4045         lane = bnx2x_get_warpcore_lane(phy, params);
4046         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4047                          MDIO_WC_REG_TX_FIR_TAP, 0x0000);
4048         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4049                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4050         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4051                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4052         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4053                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140);
4054         bnx2x_warpcore_reset_lane(bp, phy, 0);
4055 }
4056
4057 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4058                                                 u32 chip_id,
4059                                                 u32 shmem_base, u8 port,
4060                                                 u8 *gpio_num, u8 *gpio_port)
4061 {
4062         u32 cfg_pin;
4063         *gpio_num = 0;
4064         *gpio_port = 0;
4065         if (CHIP_IS_E3(bp)) {
4066                 cfg_pin = (REG_RD(bp, shmem_base +
4067                                 offsetof(struct shmem_region,
4068                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4069                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4070                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4071
4072                 /*
4073                  * Should not happen. This function called upon interrupt
4074                  * triggered by GPIO ( since EPIO can only generate interrupts
4075                  * to MCP).
4076                  * So if this function was called and none of the GPIOs was set,
4077                  * it means the shit hit the fan.
4078                  */
4079                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4080                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4081                         DP(NETIF_MSG_LINK, "ERROR: Invalid cfg pin %x for "
4082                                            "module detect indication\n",
4083                                        cfg_pin);
4084                         return -EINVAL;
4085                 }
4086
4087                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4088                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4089         } else {
4090                 *gpio_num = MISC_REGISTERS_GPIO_3;
4091                 *gpio_port = port;
4092         }
4093         DP(NETIF_MSG_LINK, "MOD_ABS int GPIO%d_P%d\n", *gpio_num, *gpio_port);
4094         return 0;
4095 }
4096
4097 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4098                                        struct link_params *params)
4099 {
4100         struct bnx2x *bp = params->bp;
4101         u8 gpio_num, gpio_port;
4102         u32 gpio_val;
4103         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4104                                       params->shmem_base, params->port,
4105                                       &gpio_num, &gpio_port) != 0)
4106                 return 0;
4107         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4108
4109         /* Call the handling function in case module is detected */
4110         if (gpio_val == 0)
4111                 return 1;
4112         else
4113                 return 0;
4114 }
4115
4116 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4117                                        struct link_params *params,
4118                                        struct link_vars *vars)
4119 {
4120         struct bnx2x *bp = params->bp;
4121         u32 serdes_net_if;
4122         u8 fiber_mode;
4123         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4124         serdes_net_if = (REG_RD(bp, params->shmem_base +
4125                          offsetof(struct shmem_region, dev_info.
4126                                   port_hw_config[params->port].default_cfg)) &
4127                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4128         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4129                            "serdes_net_if = 0x%x\n",
4130                        vars->line_speed, serdes_net_if);
4131         bnx2x_set_aer_mmd(params, phy);
4132
4133         vars->phy_flags |= PHY_XGXS_FLAG;
4134         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4135             (phy->req_line_speed &&
4136              ((phy->req_line_speed == SPEED_100) ||
4137               (phy->req_line_speed == SPEED_10)))) {
4138                 vars->phy_flags |= PHY_SGMII_FLAG;
4139                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4140                 bnx2x_warpcore_clear_regs(phy, params, lane);
4141                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0);
4142         } else {
4143                 switch (serdes_net_if) {
4144                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4145                         /* Enable KR Auto Neg */
4146                         if (params->loopback_mode == LOOPBACK_NONE)
4147                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4148                         else {
4149                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4150                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4151                         }
4152                         break;
4153
4154                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4155                         bnx2x_warpcore_clear_regs(phy, params, lane);
4156                         if (vars->line_speed == SPEED_10000) {
4157                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4158                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4159                         } else {
4160                                 if (SINGLE_MEDIA_DIRECT(params)) {
4161                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4162                                         fiber_mode = 1;
4163                                 } else {
4164                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4165                                         fiber_mode = 0;
4166                                 }
4167                                 bnx2x_warpcore_set_sgmii_speed(phy,
4168                                                                 params,
4169                                                                 fiber_mode);
4170                         }
4171
4172                         break;
4173
4174                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4175
4176                         bnx2x_warpcore_clear_regs(phy, params, lane);
4177                         if (vars->line_speed == SPEED_10000) {
4178                                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4179                                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4180                         } else if (vars->line_speed == SPEED_1000) {
4181                                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4182                                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1);
4183                         }
4184                         /* Issue Module detection */
4185                         if (bnx2x_is_sfp_module_plugged(phy, params))
4186                                 bnx2x_sfp_module_detection(phy, params);
4187                         break;
4188
4189                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4190                         if (vars->line_speed != SPEED_20000) {
4191                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4192                                 return;
4193                         }
4194                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4195                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4196                         /* Issue Module detection */
4197
4198                         bnx2x_sfp_module_detection(phy, params);
4199                         break;
4200
4201                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4202                         if (vars->line_speed != SPEED_20000) {
4203                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4204                                 return;
4205                         }
4206                         DP(NETIF_MSG_LINK, "Setting 20G KR2\n");
4207                         bnx2x_warpcore_set_20G_KR2(bp, phy);
4208                         break;
4209
4210                 default:
4211                         DP(NETIF_MSG_LINK, "Unsupported Serdes Net Interface "
4212                                            "0x%x\n", serdes_net_if);
4213                         return;
4214                 }
4215         }
4216
4217         /* Take lane out of reset after configuration is finished */
4218         bnx2x_warpcore_reset_lane(bp, phy, 0);
4219         DP(NETIF_MSG_LINK, "Exit config init\n");
4220 }
4221
4222 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4223                                          struct bnx2x_phy *phy,
4224                                          u8 tx_en)
4225 {
4226         struct bnx2x *bp = params->bp;
4227         u32 cfg_pin;
4228         u8 port = params->port;
4229
4230         cfg_pin = REG_RD(bp, params->shmem_base +
4231                                 offsetof(struct shmem_region,
4232                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4233                                 PORT_HW_CFG_TX_LASER_MASK;
4234         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4235         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4236         /* For 20G, the expected pin to be used is 3 pins after the current */
4237
4238         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4239         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4240                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4241 }
4242
4243 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4244                                       struct link_params *params)
4245 {
4246         struct bnx2x *bp = params->bp;
4247         u16 val16;
4248         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4249         bnx2x_set_mdio_clk(bp, params->chip_id, params->port);
4250         bnx2x_set_aer_mmd(params, phy);
4251         /* Global register */
4252         bnx2x_warpcore_reset_lane(bp, phy, 1);
4253
4254         /* Clear loopback settings (if any) */
4255         /* 10G & 20G */
4256         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4257                         MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4258         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4259                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 &
4260                          0xBFFF);
4261
4262         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4263                         MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4264         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4265                         MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 & 0xfffe);
4266
4267         /* Update those 1-copy registers */
4268         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4269                           MDIO_AER_BLOCK_AER_REG, 0);
4270                 /* Enable 1G MDIO (1-copy) */
4271         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4272                         MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4273                         &val16);
4274         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4275                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4276                          val16 & ~0x10);
4277
4278         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4279                         MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4280         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4281                          MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4282                          val16 & 0xff00);
4283
4284 }
4285
4286 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4287                                         struct link_params *params)
4288 {
4289         struct bnx2x *bp = params->bp;
4290         u16 val16;
4291         u32 lane;
4292         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4293                        params->loopback_mode, phy->req_line_speed);
4294
4295         if (phy->req_line_speed < SPEED_10000) {
4296                 /* 10/100/1000 */
4297
4298                 /* Update those 1-copy registers */
4299                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4300                                   MDIO_AER_BLOCK_AER_REG, 0);
4301                 /* Enable 1G MDIO (1-copy) */
4302                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4303                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4304                                 &val16);
4305                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4306                                 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4307                                 val16 | 0x10);
4308                 /* Set 1G loopback based on lane (1-copy) */
4309                 lane = bnx2x_get_warpcore_lane(phy, params);
4310                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4311                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4312                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4313                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4314                                 val16 | (1<<lane));
4315
4316                 /* Switch back to 4-copy registers */
4317                 bnx2x_set_aer_mmd(params, phy);
4318                 /* Global loopback, not recommended. */
4319                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4320                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4321                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4322                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4323                                 0x4000);
4324         } else {
4325                 /* 10G & 20G */
4326                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4327                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4328                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4329                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16 |
4330                                  0x4000);
4331
4332                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4333                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, &val16);
4334                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4335                                 MDIO_WC_REG_IEEE0BLK_MIICNTL, val16 | 0x1);
4336         }
4337 }
4338
4339
4340 void bnx2x_link_status_update(struct link_params *params,
4341                               struct link_vars *vars)
4342 {
4343         struct bnx2x *bp = params->bp;
4344         u8 link_10g_plus;
4345         u8 port = params->port;
4346         u32 sync_offset, media_types;
4347         /* Update PHY configuration */
4348         set_phy_vars(params, vars);
4349
4350         vars->link_status = REG_RD(bp, params->shmem_base +
4351                                    offsetof(struct shmem_region,
4352                                             port_mb[port].link_status));
4353
4354         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4355         vars->phy_flags = PHY_XGXS_FLAG;
4356         if (vars->link_up) {
4357                 DP(NETIF_MSG_LINK, "phy link up\n");
4358
4359                 vars->phy_link_up = 1;
4360                 vars->duplex = DUPLEX_FULL;
4361                 switch (vars->link_status &
4362                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4363                         case LINK_10THD:
4364                                 vars->duplex = DUPLEX_HALF;
4365                                 /* fall thru */
4366                         case LINK_10TFD:
4367                                 vars->line_speed = SPEED_10;
4368                                 break;
4369
4370                         case LINK_100TXHD:
4371                                 vars->duplex = DUPLEX_HALF;
4372                                 /* fall thru */
4373                         case LINK_100T4:
4374                         case LINK_100TXFD:
4375                                 vars->line_speed = SPEED_100;
4376                                 break;
4377
4378                         case LINK_1000THD:
4379                                 vars->duplex = DUPLEX_HALF;
4380                                 /* fall thru */
4381                         case LINK_1000TFD:
4382                                 vars->line_speed = SPEED_1000;
4383                                 break;
4384
4385                         case LINK_2500THD:
4386                                 vars->duplex = DUPLEX_HALF;
4387                                 /* fall thru */
4388                         case LINK_2500TFD:
4389                                 vars->line_speed = SPEED_2500;
4390                                 break;
4391
4392                         case LINK_10GTFD:
4393                                 vars->line_speed = SPEED_10000;
4394                                 break;
4395                         case LINK_20GTFD:
4396                                 vars->line_speed = SPEED_20000;
4397                                 break;
4398                         default:
4399                                 break;
4400                 }
4401                 vars->flow_ctrl = 0;
4402                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4403                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4404
4405                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4406                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4407
4408                 if (!vars->flow_ctrl)
4409                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4410
4411                 if (vars->line_speed &&
4412                     ((vars->line_speed == SPEED_10) ||
4413                      (vars->line_speed == SPEED_100))) {
4414                         vars->phy_flags |= PHY_SGMII_FLAG;
4415                 } else {
4416                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4417                 }
4418                 if (vars->line_speed &&
4419                     USES_WARPCORE(bp) &&
4420                     (vars->line_speed == SPEED_1000))
4421                         vars->phy_flags |= PHY_SGMII_FLAG;
4422                 /* anything 10 and over uses the bmac */
4423                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4424
4425                 if (link_10g_plus) {
4426                         if (USES_WARPCORE(bp))
4427                                 vars->mac_type = MAC_TYPE_XMAC;
4428                         else
4429                                 vars->mac_type = MAC_TYPE_BMAC;
4430                 } else {
4431                         if (USES_WARPCORE(bp))
4432                                 vars->mac_type = MAC_TYPE_UMAC;
4433                         else
4434                                 vars->mac_type = MAC_TYPE_EMAC;
4435                 }
4436         } else { /* link down */
4437                 DP(NETIF_MSG_LINK, "phy link down\n");
4438
4439                 vars->phy_link_up = 0;
4440
4441                 vars->line_speed = 0;
4442                 vars->duplex = DUPLEX_FULL;
4443                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4444
4445                 /* indicate no mac active */
4446                 vars->mac_type = MAC_TYPE_NONE;
4447         }
4448
4449         /* Sync media type */
4450         sync_offset = params->shmem_base +
4451                         offsetof(struct shmem_region,
4452                                  dev_info.port_hw_config[port].media_type);
4453         media_types = REG_RD(bp, sync_offset);
4454
4455         params->phy[INT_PHY].media_type =
4456                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4457                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4458         params->phy[EXT_PHY1].media_type =
4459                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4460                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4461         params->phy[EXT_PHY2].media_type =
4462                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4463                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4464         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4465
4466         /* Sync AEU offset */
4467         sync_offset = params->shmem_base +
4468                         offsetof(struct shmem_region,
4469                                  dev_info.port_hw_config[port].aeu_int_mask);
4470
4471         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4472
4473         /* Sync PFC status */
4474         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4475                 params->feature_config_flags |=
4476                                         FEATURE_CONFIG_PFC_ENABLED;
4477         else
4478                 params->feature_config_flags &=
4479                                         ~FEATURE_CONFIG_PFC_ENABLED;
4480
4481         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4482                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4483         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4484                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4485 }
4486
4487
4488 static void bnx2x_set_master_ln(struct link_params *params,
4489                                 struct bnx2x_phy *phy)
4490 {
4491         struct bnx2x *bp = params->bp;
4492         u16 new_master_ln, ser_lane;
4493         ser_lane = ((params->lane_config &
4494                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4495                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4496
4497         /* set the master_ln for AN */
4498         CL22_RD_OVER_CL45(bp, phy,
4499                           MDIO_REG_BANK_XGXS_BLOCK2,
4500                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4501                           &new_master_ln);
4502
4503         CL22_WR_OVER_CL45(bp, phy,
4504                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4505                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4506                           (new_master_ln | ser_lane));
4507 }
4508
4509 static int bnx2x_reset_unicore(struct link_params *params,
4510                                struct bnx2x_phy *phy,
4511                                u8 set_serdes)
4512 {
4513         struct bnx2x *bp = params->bp;
4514         u16 mii_control;
4515         u16 i;
4516         CL22_RD_OVER_CL45(bp, phy,
4517                           MDIO_REG_BANK_COMBO_IEEE0,
4518                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4519
4520         /* reset the unicore */
4521         CL22_WR_OVER_CL45(bp, phy,
4522                           MDIO_REG_BANK_COMBO_IEEE0,
4523                           MDIO_COMBO_IEEE0_MII_CONTROL,
4524                           (mii_control |
4525                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4526         if (set_serdes)
4527                 bnx2x_set_serdes_access(bp, params->port);
4528
4529         /* wait for the reset to self clear */
4530         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4531                 udelay(5);
4532
4533                 /* the reset erased the previous bank value */
4534                 CL22_RD_OVER_CL45(bp, phy,
4535                                   MDIO_REG_BANK_COMBO_IEEE0,
4536                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4537                                   &mii_control);
4538
4539                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4540                         udelay(5);
4541                         return 0;
4542                 }
4543         }
4544
4545         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4546                               " Port %d\n",
4547                          params->port);
4548         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4549         return -EINVAL;
4550
4551 }
4552
4553 static void bnx2x_set_swap_lanes(struct link_params *params,
4554                                  struct bnx2x_phy *phy)
4555 {
4556         struct bnx2x *bp = params->bp;
4557         /*
4558          *  Each two bits represents a lane number:
4559          *  No swap is 0123 => 0x1b no need to enable the swap
4560          */
4561         u16 ser_lane, rx_lane_swap, tx_lane_swap;
4562
4563         ser_lane = ((params->lane_config &
4564                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4565                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4566         rx_lane_swap = ((params->lane_config &
4567                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4568                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4569         tx_lane_swap = ((params->lane_config &
4570                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4571                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4572
4573         if (rx_lane_swap != 0x1b) {
4574                 CL22_WR_OVER_CL45(bp, phy,
4575                                   MDIO_REG_BANK_XGXS_BLOCK2,
4576                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4577                                   (rx_lane_swap |
4578                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4579                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4580         } else {
4581                 CL22_WR_OVER_CL45(bp, phy,
4582                                   MDIO_REG_BANK_XGXS_BLOCK2,
4583                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4584         }
4585
4586         if (tx_lane_swap != 0x1b) {
4587                 CL22_WR_OVER_CL45(bp, phy,
4588                                   MDIO_REG_BANK_XGXS_BLOCK2,
4589                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4590                                   (tx_lane_swap |
4591                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4592         } else {
4593                 CL22_WR_OVER_CL45(bp, phy,
4594                                   MDIO_REG_BANK_XGXS_BLOCK2,
4595                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4596         }
4597 }
4598
4599 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4600                                          struct link_params *params)
4601 {
4602         struct bnx2x *bp = params->bp;
4603         u16 control2;
4604         CL22_RD_OVER_CL45(bp, phy,
4605                           MDIO_REG_BANK_SERDES_DIGITAL,
4606                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4607                           &control2);
4608         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4609                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4610         else
4611                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4612         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4613                 phy->speed_cap_mask, control2);
4614         CL22_WR_OVER_CL45(bp, phy,
4615                           MDIO_REG_BANK_SERDES_DIGITAL,
4616                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4617                           control2);
4618
4619         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4620              (phy->speed_cap_mask &
4621                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4622                 DP(NETIF_MSG_LINK, "XGXS\n");
4623
4624                 CL22_WR_OVER_CL45(bp, phy,
4625                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4626                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4627                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4628
4629                 CL22_RD_OVER_CL45(bp, phy,
4630                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4631                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4632                                   &control2);
4633
4634
4635                 control2 |=
4636                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4637
4638                 CL22_WR_OVER_CL45(bp, phy,
4639                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4640                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4641                                   control2);
4642
4643                 /* Disable parallel detection of HiG */
4644                 CL22_WR_OVER_CL45(bp, phy,
4645                                   MDIO_REG_BANK_XGXS_BLOCK2,
4646                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4647                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
4648                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
4649         }
4650 }
4651
4652 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
4653                               struct link_params *params,
4654                               struct link_vars *vars,
4655                               u8 enable_cl73)
4656 {
4657         struct bnx2x *bp = params->bp;
4658         u16 reg_val;
4659
4660         /* CL37 Autoneg */
4661         CL22_RD_OVER_CL45(bp, phy,
4662                           MDIO_REG_BANK_COMBO_IEEE0,
4663                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4664
4665         /* CL37 Autoneg Enabled */
4666         if (vars->line_speed == SPEED_AUTO_NEG)
4667                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
4668         else /* CL37 Autoneg Disabled */
4669                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4670                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
4671
4672         CL22_WR_OVER_CL45(bp, phy,
4673                           MDIO_REG_BANK_COMBO_IEEE0,
4674                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4675
4676         /* Enable/Disable Autodetection */
4677
4678         CL22_RD_OVER_CL45(bp, phy,
4679                           MDIO_REG_BANK_SERDES_DIGITAL,
4680                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
4681         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
4682                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
4683         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
4684         if (vars->line_speed == SPEED_AUTO_NEG)
4685                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4686         else
4687                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
4688
4689         CL22_WR_OVER_CL45(bp, phy,
4690                           MDIO_REG_BANK_SERDES_DIGITAL,
4691                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
4692
4693         /* Enable TetonII and BAM autoneg */
4694         CL22_RD_OVER_CL45(bp, phy,
4695                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4696                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4697                           &reg_val);
4698         if (vars->line_speed == SPEED_AUTO_NEG) {
4699                 /* Enable BAM aneg Mode and TetonII aneg Mode */
4700                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4701                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4702         } else {
4703                 /* TetonII and BAM Autoneg Disabled */
4704                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
4705                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
4706         }
4707         CL22_WR_OVER_CL45(bp, phy,
4708                           MDIO_REG_BANK_BAM_NEXT_PAGE,
4709                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
4710                           reg_val);
4711
4712         if (enable_cl73) {
4713                 /* Enable Cl73 FSM status bits */
4714                 CL22_WR_OVER_CL45(bp, phy,
4715                                   MDIO_REG_BANK_CL73_USERB0,
4716                                   MDIO_CL73_USERB0_CL73_UCTRL,
4717                                   0xe);
4718
4719                 /* Enable BAM Station Manager*/
4720                 CL22_WR_OVER_CL45(bp, phy,
4721                         MDIO_REG_BANK_CL73_USERB0,
4722                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
4723                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
4724                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
4725                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
4726
4727                 /* Advertise CL73 link speeds */
4728                 CL22_RD_OVER_CL45(bp, phy,
4729                                   MDIO_REG_BANK_CL73_IEEEB1,
4730                                   MDIO_CL73_IEEEB1_AN_ADV2,
4731                                   &reg_val);
4732                 if (phy->speed_cap_mask &
4733                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4734                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
4735                 if (phy->speed_cap_mask &
4736                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4737                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
4738
4739                 CL22_WR_OVER_CL45(bp, phy,
4740                                   MDIO_REG_BANK_CL73_IEEEB1,
4741                                   MDIO_CL73_IEEEB1_AN_ADV2,
4742                                   reg_val);
4743
4744                 /* CL73 Autoneg Enabled */
4745                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
4746
4747         } else /* CL73 Autoneg Disabled */
4748                 reg_val = 0;
4749
4750         CL22_WR_OVER_CL45(bp, phy,
4751                           MDIO_REG_BANK_CL73_IEEEB0,
4752                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
4753 }
4754
4755 /* program SerDes, forced speed */
4756 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
4757                                  struct link_params *params,
4758                                  struct link_vars *vars)
4759 {
4760         struct bnx2x *bp = params->bp;
4761         u16 reg_val;
4762
4763         /* program duplex, disable autoneg and sgmii*/
4764         CL22_RD_OVER_CL45(bp, phy,
4765                           MDIO_REG_BANK_COMBO_IEEE0,
4766                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
4767         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
4768                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4769                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
4770         if (phy->req_duplex == DUPLEX_FULL)
4771                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4772         CL22_WR_OVER_CL45(bp, phy,
4773                           MDIO_REG_BANK_COMBO_IEEE0,
4774                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
4775
4776         /*
4777          * program speed
4778          *  - needed only if the speed is greater than 1G (2.5G or 10G)
4779          */
4780         CL22_RD_OVER_CL45(bp, phy,
4781                           MDIO_REG_BANK_SERDES_DIGITAL,
4782                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
4783         /* clearing the speed value before setting the right speed */
4784         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
4785
4786         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
4787                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4788
4789         if (!((vars->line_speed == SPEED_1000) ||
4790               (vars->line_speed == SPEED_100) ||
4791               (vars->line_speed == SPEED_10))) {
4792
4793                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
4794                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
4795                 if (vars->line_speed == SPEED_10000)
4796                         reg_val |=
4797                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
4798         }
4799
4800         CL22_WR_OVER_CL45(bp, phy,
4801                           MDIO_REG_BANK_SERDES_DIGITAL,
4802                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
4803
4804 }
4805
4806 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
4807                                               struct link_params *params)
4808 {
4809         struct bnx2x *bp = params->bp;
4810         u16 val = 0;
4811
4812         /* configure the 48 bits for BAM AN */
4813
4814         /* set extended capabilities */
4815         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
4816                 val |= MDIO_OVER_1G_UP1_2_5G;
4817         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
4818                 val |= MDIO_OVER_1G_UP1_10G;
4819         CL22_WR_OVER_CL45(bp, phy,
4820                           MDIO_REG_BANK_OVER_1G,
4821                           MDIO_OVER_1G_UP1, val);
4822
4823         CL22_WR_OVER_CL45(bp, phy,
4824                           MDIO_REG_BANK_OVER_1G,
4825                           MDIO_OVER_1G_UP3, 0x400);
4826 }
4827
4828 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
4829                                               struct link_params *params,
4830                                               u16 ieee_fc)
4831 {
4832         struct bnx2x *bp = params->bp;
4833         u16 val;
4834         /* for AN, we are always publishing full duplex */
4835
4836         CL22_WR_OVER_CL45(bp, phy,
4837                           MDIO_REG_BANK_COMBO_IEEE0,
4838                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
4839         CL22_RD_OVER_CL45(bp, phy,
4840                           MDIO_REG_BANK_CL73_IEEEB1,
4841                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
4842         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
4843         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
4844         CL22_WR_OVER_CL45(bp, phy,
4845                           MDIO_REG_BANK_CL73_IEEEB1,
4846                           MDIO_CL73_IEEEB1_AN_ADV1, val);
4847 }
4848
4849 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
4850                                   struct link_params *params,
4851                                   u8 enable_cl73)
4852 {
4853         struct bnx2x *bp = params->bp;
4854         u16 mii_control;
4855
4856         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
4857         /* Enable and restart BAM/CL37 aneg */
4858
4859         if (enable_cl73) {
4860                 CL22_RD_OVER_CL45(bp, phy,
4861                                   MDIO_REG_BANK_CL73_IEEEB0,
4862                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4863                                   &mii_control);
4864
4865                 CL22_WR_OVER_CL45(bp, phy,
4866                                   MDIO_REG_BANK_CL73_IEEEB0,
4867                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
4868                                   (mii_control |
4869                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
4870                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
4871         } else {
4872
4873                 CL22_RD_OVER_CL45(bp, phy,
4874                                   MDIO_REG_BANK_COMBO_IEEE0,
4875                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4876                                   &mii_control);
4877                 DP(NETIF_MSG_LINK,
4878                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
4879                          mii_control);
4880                 CL22_WR_OVER_CL45(bp, phy,
4881                                   MDIO_REG_BANK_COMBO_IEEE0,
4882                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4883                                   (mii_control |
4884                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4885                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
4886         }
4887 }
4888
4889 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
4890                                            struct link_params *params,
4891                                            struct link_vars *vars)
4892 {
4893         struct bnx2x *bp = params->bp;
4894         u16 control1;
4895
4896         /* in SGMII mode, the unicore is always slave */
4897
4898         CL22_RD_OVER_CL45(bp, phy,
4899                           MDIO_REG_BANK_SERDES_DIGITAL,
4900                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4901                           &control1);
4902         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
4903         /* set sgmii mode (and not fiber) */
4904         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
4905                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
4906                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
4907         CL22_WR_OVER_CL45(bp, phy,
4908                           MDIO_REG_BANK_SERDES_DIGITAL,
4909                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
4910                           control1);
4911
4912         /* if forced speed */
4913         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
4914                 /* set speed, disable autoneg */
4915                 u16 mii_control;
4916
4917                 CL22_RD_OVER_CL45(bp, phy,
4918                                   MDIO_REG_BANK_COMBO_IEEE0,
4919                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4920                                   &mii_control);
4921                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
4922                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
4923                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
4924
4925                 switch (vars->line_speed) {
4926                 case SPEED_100:
4927                         mii_control |=
4928                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
4929                         break;
4930                 case SPEED_1000:
4931                         mii_control |=
4932                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
4933                         break;
4934                 case SPEED_10:
4935                         /* there is nothing to set for 10M */
4936                         break;
4937                 default:
4938                         /* invalid speed for SGMII */
4939                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
4940                                   vars->line_speed);
4941                         break;
4942                 }
4943
4944                 /* setting the full duplex */
4945                 if (phy->req_duplex == DUPLEX_FULL)
4946                         mii_control |=
4947                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
4948                 CL22_WR_OVER_CL45(bp, phy,
4949                                   MDIO_REG_BANK_COMBO_IEEE0,
4950                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4951                                   mii_control);
4952
4953         } else { /* AN mode */
4954                 /* enable and restart AN */
4955                 bnx2x_restart_autoneg(phy, params, 0);
4956         }
4957 }
4958
4959
4960 /*
4961  * link management
4962  */
4963
4964 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
4965                                              struct link_params *params)
4966 {
4967         struct bnx2x *bp = params->bp;
4968         u16 pd_10g, status2_1000x;
4969         if (phy->req_line_speed != SPEED_AUTO_NEG)
4970                 return 0;
4971         CL22_RD_OVER_CL45(bp, phy,
4972                           MDIO_REG_BANK_SERDES_DIGITAL,
4973                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4974                           &status2_1000x);
4975         CL22_RD_OVER_CL45(bp, phy,
4976                           MDIO_REG_BANK_SERDES_DIGITAL,
4977                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
4978                           &status2_1000x);
4979         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
4980                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
4981                          params->port);
4982                 return 1;
4983         }
4984
4985         CL22_RD_OVER_CL45(bp, phy,
4986                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
4987                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
4988                           &pd_10g);
4989
4990         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
4991                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
4992                          params->port);
4993                 return 1;
4994         }
4995         return 0;
4996 }
4997
4998 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
4999                                     struct link_params *params,
5000                                     struct link_vars *vars,
5001                                     u32 gp_status)
5002 {
5003         struct bnx2x *bp = params->bp;
5004         u16 ld_pause;   /* local driver */
5005         u16 lp_pause;   /* link partner */
5006         u16 pause_result;
5007
5008         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5009
5010         /* resolve from gp_status in case of AN complete and not sgmii */
5011         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO)
5012                 vars->flow_ctrl = phy->req_flow_ctrl;
5013         else if (phy->req_line_speed != SPEED_AUTO_NEG)
5014                 vars->flow_ctrl = params->req_fc_auto_adv;
5015         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5016                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5017                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5018                         vars->flow_ctrl = params->req_fc_auto_adv;
5019                         return;
5020                 }
5021                 if ((gp_status &
5022                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5023                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5024                     (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5025                      MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5026
5027                         CL22_RD_OVER_CL45(bp, phy,
5028                                           MDIO_REG_BANK_CL73_IEEEB1,
5029                                           MDIO_CL73_IEEEB1_AN_ADV1,
5030                                           &ld_pause);
5031                         CL22_RD_OVER_CL45(bp, phy,
5032                                           MDIO_REG_BANK_CL73_IEEEB1,
5033                                           MDIO_CL73_IEEEB1_AN_LP_ADV1,
5034                                           &lp_pause);
5035                         pause_result = (ld_pause &
5036                                         MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK)
5037                                         >> 8;
5038                         pause_result |= (lp_pause &
5039                                         MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK)
5040                                         >> 10;
5041                         DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n",
5042                                  pause_result);
5043                 } else {
5044                         CL22_RD_OVER_CL45(bp, phy,
5045                                           MDIO_REG_BANK_COMBO_IEEE0,
5046                                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5047                                           &ld_pause);
5048                         CL22_RD_OVER_CL45(bp, phy,
5049                                 MDIO_REG_BANK_COMBO_IEEE0,
5050                                 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5051                                 &lp_pause);
5052                         pause_result = (ld_pause &
5053                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5054                         pause_result |= (lp_pause &
5055                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5056                         DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n",
5057                                  pause_result);
5058                 }
5059                 bnx2x_pause_resolve(vars, pause_result);
5060         }
5061         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5062 }
5063
5064 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5065                                          struct link_params *params)
5066 {
5067         struct bnx2x *bp = params->bp;
5068         u16 rx_status, ustat_val, cl37_fsm_received;
5069         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5070         /* Step 1: Make sure signal is detected */
5071         CL22_RD_OVER_CL45(bp, phy,
5072                           MDIO_REG_BANK_RX0,
5073                           MDIO_RX0_RX_STATUS,
5074                           &rx_status);
5075         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5076             (MDIO_RX0_RX_STATUS_SIGDET)) {
5077                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5078                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5079                 CL22_WR_OVER_CL45(bp, phy,
5080                                   MDIO_REG_BANK_CL73_IEEEB0,
5081                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5082                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5083                 return;
5084         }
5085         /* Step 2: Check CL73 state machine */
5086         CL22_RD_OVER_CL45(bp, phy,
5087                           MDIO_REG_BANK_CL73_USERB0,
5088                           MDIO_CL73_USERB0_CL73_USTAT1,
5089                           &ustat_val);
5090         if ((ustat_val &
5091              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5092               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5093             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5094               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5095                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5096                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5097                 return;
5098         }
5099         /*
5100          * Step 3: Check CL37 Message Pages received to indicate LP
5101          * supports only CL37
5102          */
5103         CL22_RD_OVER_CL45(bp, phy,
5104                           MDIO_REG_BANK_REMOTE_PHY,
5105                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5106                           &cl37_fsm_received);
5107         if ((cl37_fsm_received &
5108              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5109              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5110             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5111               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5112                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5113                              "misc_rx_status(0x8330) = 0x%x\n",
5114                          cl37_fsm_received);
5115                 return;
5116         }
5117         /*
5118          * The combined cl37/cl73 fsm state information indicating that
5119          * we are connected to a device which does not support cl73, but
5120          * does support cl37 BAM. In this case we disable cl73 and
5121          * restart cl37 auto-neg
5122          */
5123
5124         /* Disable CL73 */
5125         CL22_WR_OVER_CL45(bp, phy,
5126                           MDIO_REG_BANK_CL73_IEEEB0,
5127                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5128                           0);
5129         /* Restart CL37 autoneg */
5130         bnx2x_restart_autoneg(phy, params, 0);
5131         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5132 }
5133
5134 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5135                                   struct link_params *params,
5136                                   struct link_vars *vars,
5137                                   u32 gp_status)
5138 {
5139         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5140                 vars->link_status |=
5141                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5142
5143         if (bnx2x_direct_parallel_detect_used(phy, params))
5144                 vars->link_status |=
5145                         LINK_STATUS_PARALLEL_DETECTION_USED;
5146 }
5147 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5148                                      struct link_params *params,
5149                                       struct link_vars *vars,
5150                                       u16 is_link_up,
5151                                       u16 speed_mask,
5152                                       u16 is_duplex)
5153 {
5154         struct bnx2x *bp = params->bp;
5155         if (phy->req_line_speed == SPEED_AUTO_NEG)
5156                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5157         if (is_link_up) {
5158                 DP(NETIF_MSG_LINK, "phy link up\n");
5159
5160                 vars->phy_link_up = 1;
5161                 vars->link_status |= LINK_STATUS_LINK_UP;
5162
5163                 switch (speed_mask) {
5164                 case GP_STATUS_10M:
5165                         vars->line_speed = SPEED_10;
5166                         if (vars->duplex == DUPLEX_FULL)
5167                                 vars->link_status |= LINK_10TFD;
5168                         else
5169                                 vars->link_status |= LINK_10THD;
5170                         break;
5171
5172                 case GP_STATUS_100M:
5173                         vars->line_speed = SPEED_100;
5174                         if (vars->duplex == DUPLEX_FULL)
5175                                 vars->link_status |= LINK_100TXFD;
5176                         else
5177                                 vars->link_status |= LINK_100TXHD;
5178                         break;
5179
5180                 case GP_STATUS_1G:
5181                 case GP_STATUS_1G_KX:
5182                         vars->line_speed = SPEED_1000;
5183                         if (vars->duplex == DUPLEX_FULL)
5184                                 vars->link_status |= LINK_1000TFD;
5185                         else
5186                                 vars->link_status |= LINK_1000THD;
5187                         break;
5188
5189                 case GP_STATUS_2_5G:
5190                         vars->line_speed = SPEED_2500;
5191                         if (vars->duplex == DUPLEX_FULL)
5192                                 vars->link_status |= LINK_2500TFD;
5193                         else
5194                                 vars->link_status |= LINK_2500THD;
5195                         break;
5196
5197                 case GP_STATUS_5G:
5198                 case GP_STATUS_6G:
5199                         DP(NETIF_MSG_LINK,
5200                                  "link speed unsupported  gp_status 0x%x\n",
5201                                   speed_mask);
5202                         return -EINVAL;
5203
5204                 case GP_STATUS_10G_KX4:
5205                 case GP_STATUS_10G_HIG:
5206                 case GP_STATUS_10G_CX4:
5207                 case GP_STATUS_10G_KR:
5208                 case GP_STATUS_10G_SFI:
5209                 case GP_STATUS_10G_XFI:
5210                         vars->line_speed = SPEED_10000;
5211                         vars->link_status |= LINK_10GTFD;
5212                         break;
5213                 case GP_STATUS_20G_DXGXS:
5214                         vars->line_speed = SPEED_20000;
5215                         vars->link_status |= LINK_20GTFD;
5216                         break;
5217                 default:
5218                         DP(NETIF_MSG_LINK,
5219                                   "link speed unsupported gp_status 0x%x\n",
5220                                   speed_mask);
5221                         return -EINVAL;
5222                 }
5223         } else { /* link_down */
5224                 DP(NETIF_MSG_LINK, "phy link down\n");
5225
5226                 vars->phy_link_up = 0;
5227
5228                 vars->duplex = DUPLEX_FULL;
5229                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5230                 vars->mac_type = MAC_TYPE_NONE;
5231         }
5232         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5233                     vars->phy_link_up, vars->line_speed);
5234         return 0;
5235 }
5236
5237 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5238                                       struct link_params *params,
5239                                       struct link_vars *vars)
5240 {
5241
5242         struct bnx2x *bp = params->bp;
5243
5244         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5245         int rc = 0;
5246
5247         /* Read gp_status */
5248         CL22_RD_OVER_CL45(bp, phy,
5249                           MDIO_REG_BANK_GP_STATUS,
5250                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5251                           &gp_status);
5252         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5253                 duplex = DUPLEX_FULL;
5254         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5255                 link_up = 1;
5256         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5257         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5258                        gp_status, link_up, speed_mask);
5259         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5260                                          duplex);
5261         if (rc == -EINVAL)
5262                 return rc;
5263
5264         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5265                 if (SINGLE_MEDIA_DIRECT(params)) {
5266                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5267                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5268                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5269                                                       gp_status);
5270                 }
5271         } else { /* link_down */
5272                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5273                     SINGLE_MEDIA_DIRECT(params)) {
5274                         /* Check signal is detected */
5275                         bnx2x_check_fallback_to_cl37(phy, params);
5276                 }
5277         }
5278
5279         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5280                    vars->duplex, vars->flow_ctrl, vars->link_status);
5281         return rc;
5282 }
5283
5284 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5285                                      struct link_params *params,
5286                                      struct link_vars *vars)
5287 {
5288
5289         struct bnx2x *bp = params->bp;
5290
5291         u8 lane;
5292         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5293         int rc = 0;
5294         lane = bnx2x_get_warpcore_lane(phy, params);
5295         /* Read gp_status */
5296         if (phy->req_line_speed > SPEED_10000) {
5297                 u16 temp_link_up;
5298                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5299                                 1, &temp_link_up);
5300                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5301                                 1, &link_up);
5302                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5303                                temp_link_up, link_up);
5304                 link_up &= (1<<2);
5305                 if (link_up)
5306                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5307         } else {
5308                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5309                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &gp_status1);
5310                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5311                 /* Check for either KR or generic link up. */
5312                 gp_status1 = ((gp_status1 >> 8) & 0xf) |
5313                         ((gp_status1 >> 12) & 0xf);
5314                 link_up = gp_status1 & (1 << lane);
5315                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5316                         u16 pd, gp_status4;
5317                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5318                                 /* Check Autoneg complete */
5319                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5320                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5321                                                 &gp_status4);
5322                                 if (gp_status4 & ((1<<12)<<lane))
5323                                         vars->link_status |=
5324                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5325
5326                                 /* Check parallel detect used */
5327                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5328                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5329                                                 &pd);
5330                                 if (pd & (1<<15))
5331                                         vars->link_status |=
5332                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5333                         }
5334                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5335                 }
5336         }
5337
5338         if (lane < 2) {
5339                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5340                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5341         } else {
5342                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5343                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5344         }
5345         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5346
5347         if ((lane & 1) == 0)
5348                 gp_speed <<= 8;
5349         gp_speed &= 0x3f00;
5350
5351
5352         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5353                                          duplex);
5354
5355         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5356                    vars->duplex, vars->flow_ctrl, vars->link_status);
5357         return rc;
5358 }
5359 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5360 {
5361         struct bnx2x *bp = params->bp;
5362         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5363         u16 lp_up2;
5364         u16 tx_driver;
5365         u16 bank;
5366
5367         /* read precomp */
5368         CL22_RD_OVER_CL45(bp, phy,
5369                           MDIO_REG_BANK_OVER_1G,
5370                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5371
5372         /* bits [10:7] at lp_up2, positioned at [15:12] */
5373         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5374                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5375                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5376
5377         if (lp_up2 == 0)
5378                 return;
5379
5380         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5381               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5382                 CL22_RD_OVER_CL45(bp, phy,
5383                                   bank,
5384                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5385
5386                 /* replace tx_driver bits [15:12] */
5387                 if (lp_up2 !=
5388                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5389                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5390                         tx_driver |= lp_up2;
5391                         CL22_WR_OVER_CL45(bp, phy,
5392                                           bank,
5393                                           MDIO_TX0_TX_DRIVER, tx_driver);
5394                 }
5395         }
5396 }
5397
5398 static int bnx2x_emac_program(struct link_params *params,
5399                               struct link_vars *vars)
5400 {
5401         struct bnx2x *bp = params->bp;
5402         u8 port = params->port;
5403         u16 mode = 0;
5404
5405         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5406         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5407                        EMAC_REG_EMAC_MODE,
5408                        (EMAC_MODE_25G_MODE |
5409                         EMAC_MODE_PORT_MII_10M |
5410                         EMAC_MODE_HALF_DUPLEX));
5411         switch (vars->line_speed) {
5412         case SPEED_10:
5413                 mode |= EMAC_MODE_PORT_MII_10M;
5414                 break;
5415
5416         case SPEED_100:
5417                 mode |= EMAC_MODE_PORT_MII;
5418                 break;
5419
5420         case SPEED_1000:
5421                 mode |= EMAC_MODE_PORT_GMII;
5422                 break;
5423
5424         case SPEED_2500:
5425                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5426                 break;
5427
5428         default:
5429                 /* 10G not valid for EMAC */
5430                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5431                            vars->line_speed);
5432                 return -EINVAL;
5433         }
5434
5435         if (vars->duplex == DUPLEX_HALF)
5436                 mode |= EMAC_MODE_HALF_DUPLEX;
5437         bnx2x_bits_en(bp,
5438                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5439                       mode);
5440
5441         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5442         return 0;
5443 }
5444
5445 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5446                                   struct link_params *params)
5447 {
5448
5449         u16 bank, i = 0;
5450         struct bnx2x *bp = params->bp;
5451
5452         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5453               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5454                         CL22_WR_OVER_CL45(bp, phy,
5455                                           bank,
5456                                           MDIO_RX0_RX_EQ_BOOST,
5457                                           phy->rx_preemphasis[i]);
5458         }
5459
5460         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5461                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5462                         CL22_WR_OVER_CL45(bp, phy,
5463                                           bank,
5464                                           MDIO_TX0_TX_DRIVER,
5465                                           phy->tx_preemphasis[i]);
5466         }
5467 }
5468
5469 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5470                                    struct link_params *params,
5471                                    struct link_vars *vars)
5472 {
5473         struct bnx2x *bp = params->bp;
5474         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5475                           (params->loopback_mode == LOOPBACK_XGXS));
5476         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5477                 if (SINGLE_MEDIA_DIRECT(params) &&
5478                     (params->feature_config_flags &
5479                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5480                         bnx2x_set_preemphasis(phy, params);
5481
5482                 /* forced speed requested? */
5483                 if (vars->line_speed != SPEED_AUTO_NEG ||
5484                     (SINGLE_MEDIA_DIRECT(params) &&
5485                      params->loopback_mode == LOOPBACK_EXT)) {
5486                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5487
5488                         /* disable autoneg */
5489                         bnx2x_set_autoneg(phy, params, vars, 0);
5490
5491                         /* program speed and duplex */
5492                         bnx2x_program_serdes(phy, params, vars);
5493
5494                 } else { /* AN_mode */
5495                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5496
5497                         /* AN enabled */
5498                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5499
5500                         /* program duplex & pause advertisement (for aneg) */
5501                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5502                                                           vars->ieee_fc);
5503
5504                         /* enable autoneg */
5505                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5506
5507                         /* enable and restart AN */
5508                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5509                 }
5510
5511         } else { /* SGMII mode */
5512                 DP(NETIF_MSG_LINK, "SGMII\n");
5513
5514                 bnx2x_initialize_sgmii_process(phy, params, vars);
5515         }
5516 }
5517
5518 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5519                           struct link_params *params,
5520                           struct link_vars *vars)
5521 {
5522         int rc;
5523         vars->phy_flags |= PHY_XGXS_FLAG;
5524         if ((phy->req_line_speed &&
5525              ((phy->req_line_speed == SPEED_100) ||
5526               (phy->req_line_speed == SPEED_10))) ||
5527             (!phy->req_line_speed &&
5528              (phy->speed_cap_mask >=
5529               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5530              (phy->speed_cap_mask <
5531               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5532             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5533                 vars->phy_flags |= PHY_SGMII_FLAG;
5534         else
5535                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5536
5537         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5538         bnx2x_set_aer_mmd(params, phy);
5539         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5540                 bnx2x_set_master_ln(params, phy);
5541
5542         rc = bnx2x_reset_unicore(params, phy, 0);
5543         /* reset the SerDes and wait for reset bit return low */
5544         if (rc != 0)
5545                 return rc;
5546
5547         bnx2x_set_aer_mmd(params, phy);
5548         /* setting the masterLn_def again after the reset */
5549         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5550                 bnx2x_set_master_ln(params, phy);
5551                 bnx2x_set_swap_lanes(params, phy);
5552         }
5553
5554         return rc;
5555 }
5556
5557 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5558                                      struct bnx2x_phy *phy,
5559                                      struct link_params *params)
5560 {
5561         u16 cnt, ctrl;
5562         /* Wait for soft reset to get cleared up to 1 sec */
5563         for (cnt = 0; cnt < 1000; cnt++) {
5564                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5565                         bnx2x_cl22_read(bp, phy,
5566                                 MDIO_PMA_REG_CTRL, &ctrl);
5567                 else
5568                         bnx2x_cl45_read(bp, phy,
5569                                 MDIO_PMA_DEVAD,
5570                                 MDIO_PMA_REG_CTRL, &ctrl);
5571                 if (!(ctrl & (1<<15)))
5572                         break;
5573                 msleep(1);
5574         }
5575
5576         if (cnt == 1000)
5577                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
5578                                       " Port %d\n",
5579                          params->port);
5580         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
5581         return cnt;
5582 }
5583
5584 static void bnx2x_link_int_enable(struct link_params *params)
5585 {
5586         u8 port = params->port;
5587         u32 mask;
5588         struct bnx2x *bp = params->bp;
5589
5590         /* Setting the status to report on link up for either XGXS or SerDes */
5591         if (CHIP_IS_E3(bp)) {
5592                 mask = NIG_MASK_XGXS0_LINK_STATUS;
5593                 if (!(SINGLE_MEDIA_DIRECT(params)))
5594                         mask |= NIG_MASK_MI_INT;
5595         } else if (params->switch_cfg == SWITCH_CFG_10G) {
5596                 mask = (NIG_MASK_XGXS0_LINK10G |
5597                         NIG_MASK_XGXS0_LINK_STATUS);
5598                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
5599                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5600                         params->phy[INT_PHY].type !=
5601                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
5602                         mask |= NIG_MASK_MI_INT;
5603                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5604                 }
5605
5606         } else { /* SerDes */
5607                 mask = NIG_MASK_SERDES0_LINK_STATUS;
5608                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
5609                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
5610                         params->phy[INT_PHY].type !=
5611                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
5612                         mask |= NIG_MASK_MI_INT;
5613                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
5614                 }
5615         }
5616         bnx2x_bits_en(bp,
5617                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
5618                       mask);
5619
5620         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
5621                  (params->switch_cfg == SWITCH_CFG_10G),
5622                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
5623         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5624                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
5625                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
5626                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
5627         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
5628            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
5629            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
5630 }
5631
5632 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5633                                      u8 exp_mi_int)
5634 {
5635         u32 latch_status = 0;
5636
5637         /*
5638          * Disable the MI INT ( external phy int ) by writing 1 to the
5639          * status register. Link down indication is high-active-signal,
5640          * so in this case we need to write the status to clear the XOR
5641          */
5642         /* Read Latched signals */
5643         latch_status = REG_RD(bp,
5644                                     NIG_REG_LATCH_STATUS_0 + port*8);
5645         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
5646         /* Handle only those with latched-signal=up.*/
5647         if (exp_mi_int)
5648                 bnx2x_bits_en(bp,
5649                               NIG_REG_STATUS_INTERRUPT_PORT0
5650                               + port*4,
5651                               NIG_STATUS_EMAC0_MI_INT);
5652         else
5653                 bnx2x_bits_dis(bp,
5654                                NIG_REG_STATUS_INTERRUPT_PORT0
5655                                + port*4,
5656                                NIG_STATUS_EMAC0_MI_INT);
5657
5658         if (latch_status & 1) {
5659
5660                 /* For all latched-signal=up : Re-Arm Latch signals */
5661                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
5662                        (latch_status & 0xfffe) | (latch_status & 1));
5663         }
5664         /* For all latched-signal=up,Write original_signal to status */
5665 }
5666
5667 static void bnx2x_link_int_ack(struct link_params *params,
5668                                struct link_vars *vars, u8 is_10g_plus)
5669 {
5670         struct bnx2x *bp = params->bp;
5671         u8 port = params->port;
5672         u32 mask;
5673         /*
5674          * First reset all status we assume only one line will be
5675          * change at a time
5676          */
5677         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5678                        (NIG_STATUS_XGXS0_LINK10G |
5679                         NIG_STATUS_XGXS0_LINK_STATUS |
5680                         NIG_STATUS_SERDES0_LINK_STATUS));
5681         if (vars->phy_link_up) {
5682                 if (USES_WARPCORE(bp))
5683                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
5684                 else {
5685                         if (is_10g_plus)
5686                                 mask = NIG_STATUS_XGXS0_LINK10G;
5687                         else if (params->switch_cfg == SWITCH_CFG_10G) {
5688                                 /*
5689                                  * Disable the link interrupt by writing 1 to
5690                                  * the relevant lane in the status register
5691                                  */
5692                                 u32 ser_lane =
5693                                         ((params->lane_config &
5694                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5695                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5696                                 mask = ((1 << ser_lane) <<
5697                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
5698                         } else
5699                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
5700                 }
5701                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
5702                                mask);
5703                 bnx2x_bits_en(bp,
5704                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
5705                               mask);
5706         }
5707 }
5708
5709 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
5710 {
5711         u8 *str_ptr = str;
5712         u32 mask = 0xf0000000;
5713         u8 shift = 8*4;
5714         u8 digit;
5715         u8 remove_leading_zeros = 1;
5716         if (*len < 10) {
5717                 /* Need more than 10chars for this format */
5718                 *str_ptr = '\0';
5719                 (*len)--;
5720                 return -EINVAL;
5721         }
5722         while (shift > 0) {
5723
5724                 shift -= 4;
5725                 digit = ((num & mask) >> shift);
5726                 if (digit == 0 && remove_leading_zeros) {
5727                         mask = mask >> 4;
5728                         continue;
5729                 } else if (digit < 0xa)
5730                         *str_ptr = digit + '0';
5731                 else
5732                         *str_ptr = digit - 0xa + 'a';
5733                 remove_leading_zeros = 0;
5734                 str_ptr++;
5735                 (*len)--;
5736                 mask = mask >> 4;
5737                 if (shift == 4*4) {
5738                         *str_ptr = '.';
5739                         str_ptr++;
5740                         (*len)--;
5741                         remove_leading_zeros = 1;
5742                 }
5743         }
5744         return 0;
5745 }
5746
5747
5748 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
5749 {
5750         str[0] = '\0';
5751         (*len)--;
5752         return 0;
5753 }
5754
5755 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
5756                                  u8 *version, u16 len)
5757 {
5758         struct bnx2x *bp;
5759         u32 spirom_ver = 0;
5760         int status = 0;
5761         u8 *ver_p = version;
5762         u16 remain_len = len;
5763         if (version == NULL || params == NULL)
5764                 return -EINVAL;
5765         bp = params->bp;
5766
5767         /* Extract first external phy*/
5768         version[0] = '\0';
5769         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
5770
5771         if (params->phy[EXT_PHY1].format_fw_ver) {
5772                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
5773                                                               ver_p,
5774                                                               &remain_len);
5775                 ver_p += (len - remain_len);
5776         }
5777         if ((params->num_phys == MAX_PHYS) &&
5778             (params->phy[EXT_PHY2].ver_addr != 0)) {
5779                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
5780                 if (params->phy[EXT_PHY2].format_fw_ver) {
5781                         *ver_p = '/';
5782                         ver_p++;
5783                         remain_len--;
5784                         status |= params->phy[EXT_PHY2].format_fw_ver(
5785                                 spirom_ver,
5786                                 ver_p,
5787                                 &remain_len);
5788                         ver_p = version + (len - remain_len);
5789                 }
5790         }
5791         *ver_p = '\0';
5792         return status;
5793 }
5794
5795 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
5796                                     struct link_params *params)
5797 {
5798         u8 port = params->port;
5799         struct bnx2x *bp = params->bp;
5800
5801         if (phy->req_line_speed != SPEED_1000) {
5802                 u32 md_devad = 0;
5803
5804                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
5805
5806                 if (!CHIP_IS_E3(bp)) {
5807                         /* change the uni_phy_addr in the nig */
5808                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
5809                                                port*0x18));
5810
5811                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5812                                0x5);
5813                 }
5814
5815                 bnx2x_cl45_write(bp, phy,
5816                                  5,
5817                                  (MDIO_REG_BANK_AER_BLOCK +
5818                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
5819                                  0x2800);
5820
5821                 bnx2x_cl45_write(bp, phy,
5822                                  5,
5823                                  (MDIO_REG_BANK_CL73_IEEEB0 +
5824                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
5825                                  0x6041);
5826                 msleep(200);
5827                 /* set aer mmd back */
5828                 bnx2x_set_aer_mmd(params, phy);
5829
5830                 if (!CHIP_IS_E3(bp)) {
5831                         /* and md_devad */
5832                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
5833                                md_devad);
5834                 }
5835         } else {
5836                 u16 mii_ctrl;
5837                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
5838                 bnx2x_cl45_read(bp, phy, 5,
5839                                 (MDIO_REG_BANK_COMBO_IEEE0 +
5840                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5841                                 &mii_ctrl);
5842                 bnx2x_cl45_write(bp, phy, 5,
5843                                  (MDIO_REG_BANK_COMBO_IEEE0 +
5844                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
5845                                  mii_ctrl |
5846                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
5847         }
5848 }
5849
5850 int bnx2x_set_led(struct link_params *params,
5851                   struct link_vars *vars, u8 mode, u32 speed)
5852 {
5853         u8 port = params->port;
5854         u16 hw_led_mode = params->hw_led_mode;
5855         int rc = 0;
5856         u8 phy_idx;
5857         u32 tmp;
5858         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
5859         struct bnx2x *bp = params->bp;
5860         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
5861         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
5862                  speed, hw_led_mode);
5863         /* In case */
5864         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
5865                 if (params->phy[phy_idx].set_link_led) {
5866                         params->phy[phy_idx].set_link_led(
5867                                 &params->phy[phy_idx], params, mode);
5868                 }
5869         }
5870
5871         switch (mode) {
5872         case LED_MODE_FRONT_PANEL_OFF:
5873         case LED_MODE_OFF:
5874                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
5875                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5876                        SHARED_HW_CFG_LED_MAC1);
5877
5878                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5879                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE));
5880                 break;
5881
5882         case LED_MODE_OPER:
5883                 /*
5884                  * For all other phys, OPER mode is same as ON, so in case
5885                  * link is down, do nothing
5886                  */
5887                 if (!vars->link_up)
5888                         break;
5889         case LED_MODE_ON:
5890                 if (((params->phy[EXT_PHY1].type ==
5891                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
5892                          (params->phy[EXT_PHY1].type ==
5893                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
5894                     CHIP_IS_E2(bp) && params->num_phys == 2) {
5895                         /*
5896                          * This is a work-around for E2+8727 Configurations
5897                          */
5898                         if (mode == LED_MODE_ON ||
5899                                 speed == SPEED_10000){
5900                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5901                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5902
5903                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5904                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
5905                                         (tmp | EMAC_LED_OVERRIDE));
5906                                 return rc;
5907                         }
5908                 } else if (SINGLE_MEDIA_DIRECT(params) &&
5909                            (CHIP_IS_E1x(bp) ||
5910                             CHIP_IS_E2(bp))) {
5911                         /*
5912                          * This is a work-around for HW issue found when link
5913                          * is up in CL73
5914                          */
5915                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
5916                         REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
5917                 } else {
5918                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
5919                 }
5920
5921                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5922                 /* Set blinking rate to ~15.9Hz */
5923                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
5924                        LED_BLINK_RATE_VAL);
5925                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5926                        port*4, 1);
5927                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5928                 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE)));
5929
5930                 if (CHIP_IS_E1(bp) &&
5931                     ((speed == SPEED_2500) ||
5932                      (speed == SPEED_1000) ||
5933                      (speed == SPEED_100) ||
5934                      (speed == SPEED_10))) {
5935                         /*
5936                          * On Everest 1 Ax chip versions for speeds less than
5937                          * 10G LED scheme is different
5938                          */
5939                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
5940                                + port*4, 1);
5941                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
5942                                port*4, 0);
5943                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
5944                                port*4, 1);
5945                 }
5946                 break;
5947
5948         default:
5949                 rc = -EINVAL;
5950                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
5951                          mode);
5952                 break;
5953         }
5954         return rc;
5955
5956 }
5957
5958 /*
5959  * This function comes to reflect the actual link state read DIRECTLY from the
5960  * HW
5961  */
5962 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
5963                     u8 is_serdes)
5964 {
5965         struct bnx2x *bp = params->bp;
5966         u16 gp_status = 0, phy_index = 0;
5967         u8 ext_phy_link_up = 0, serdes_phy_type;
5968         struct link_vars temp_vars;
5969         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
5970
5971         if (CHIP_IS_E3(bp)) {
5972                 u16 link_up;
5973                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
5974                     > SPEED_10000) {
5975                         /* Check 20G link */
5976                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5977                                         1, &link_up);
5978                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5979                                         1, &link_up);
5980                         link_up &= (1<<2);
5981                 } else {
5982                         /* Check 10G link and below*/
5983                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
5984                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
5985                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
5986                                         &gp_status);
5987                         gp_status = ((gp_status >> 8) & 0xf) |
5988                                 ((gp_status >> 12) & 0xf);
5989                         link_up = gp_status & (1 << lane);
5990                 }
5991                 if (!link_up)
5992                         return -ESRCH;
5993         } else {
5994                 CL22_RD_OVER_CL45(bp, int_phy,
5995                           MDIO_REG_BANK_GP_STATUS,
5996                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5997                           &gp_status);
5998         /* link is up only if both local phy and external phy are up */
5999         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6000                 return -ESRCH;
6001         }
6002         /* In XGXS loopback mode, do not check external PHY */
6003         if (params->loopback_mode == LOOPBACK_XGXS)
6004                 return 0;
6005
6006         switch (params->num_phys) {
6007         case 1:
6008                 /* No external PHY */
6009                 return 0;
6010         case 2:
6011                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6012                         &params->phy[EXT_PHY1],
6013                         params, &temp_vars);
6014                 break;
6015         case 3: /* Dual Media */
6016                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6017                       phy_index++) {
6018                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6019                                             ETH_PHY_SFP_FIBER) ||
6020                                            (params->phy[phy_index].media_type ==
6021                                             ETH_PHY_XFP_FIBER) ||
6022                                            (params->phy[phy_index].media_type ==
6023                                             ETH_PHY_DA_TWINAX));
6024
6025                         if (is_serdes != serdes_phy_type)
6026                                 continue;
6027                         if (params->phy[phy_index].read_status) {
6028                                 ext_phy_link_up |=
6029                                         params->phy[phy_index].read_status(
6030                                                 &params->phy[phy_index],
6031                                                 params, &temp_vars);
6032                         }
6033                 }
6034                 break;
6035         }
6036         if (ext_phy_link_up)
6037                 return 0;
6038         return -ESRCH;
6039 }
6040
6041 static int bnx2x_link_initialize(struct link_params *params,
6042                                  struct link_vars *vars)
6043 {
6044         int rc = 0;
6045         u8 phy_index, non_ext_phy;
6046         struct bnx2x *bp = params->bp;
6047         /*
6048          * In case of external phy existence, the line speed would be the
6049          * line speed linked up by the external phy. In case it is direct
6050          * only, then the line_speed during initialization will be
6051          * equal to the req_line_speed
6052          */
6053         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6054
6055         /*
6056          * Initialize the internal phy in case this is a direct board
6057          * (no external phys), or this board has external phy which requires
6058          * to first.
6059          */
6060         if (!USES_WARPCORE(bp))
6061                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6062         /* init ext phy and enable link state int */
6063         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6064                        (params->loopback_mode == LOOPBACK_XGXS));
6065
6066         if (non_ext_phy ||
6067             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6068             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6069                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6070                 if (vars->line_speed == SPEED_AUTO_NEG &&
6071                     (CHIP_IS_E1x(bp) ||
6072                      CHIP_IS_E2(bp)))
6073                         bnx2x_set_parallel_detection(phy, params);
6074                         if (params->phy[INT_PHY].config_init)
6075                                 params->phy[INT_PHY].config_init(phy,
6076                                                                  params,
6077                                                                  vars);
6078         }
6079
6080         /* Init external phy*/
6081         if (non_ext_phy) {
6082                 if (params->phy[INT_PHY].supported &
6083                     SUPPORTED_FIBRE)
6084                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6085         } else {
6086                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6087                       phy_index++) {
6088                         /*
6089                          * No need to initialize second phy in case of first
6090                          * phy only selection. In case of second phy, we do
6091                          * need to initialize the first phy, since they are
6092                          * connected.
6093                          */
6094                         if (params->phy[phy_index].supported &
6095                             SUPPORTED_FIBRE)
6096                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6097
6098                         if (phy_index == EXT_PHY2 &&
6099                             (bnx2x_phy_selection(params) ==
6100                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6101                                 DP(NETIF_MSG_LINK, "Not initializing"
6102                                                 " second phy\n");
6103                                 continue;
6104                         }
6105                         params->phy[phy_index].config_init(
6106                                 &params->phy[phy_index],
6107                                 params, vars);
6108                 }
6109         }
6110         /* Reset the interrupt indication after phy was initialized */
6111         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6112                        params->port*4,
6113                        (NIG_STATUS_XGXS0_LINK10G |
6114                         NIG_STATUS_XGXS0_LINK_STATUS |
6115                         NIG_STATUS_SERDES0_LINK_STATUS |
6116                         NIG_MASK_MI_INT));
6117         bnx2x_update_mng(params, vars->link_status);
6118         return rc;
6119 }
6120
6121 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6122                                  struct link_params *params)
6123 {
6124         /* reset the SerDes/XGXS */
6125         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6126                (0x1ff << (params->port*16)));
6127 }
6128
6129 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6130                                         struct link_params *params)
6131 {
6132         struct bnx2x *bp = params->bp;
6133         u8 gpio_port;
6134         /* HW reset */
6135         if (CHIP_IS_E2(bp))
6136                 gpio_port = BP_PATH(bp);
6137         else
6138                 gpio_port = params->port;
6139         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6140                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6141                        gpio_port);
6142         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6143                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6144                        gpio_port);
6145         DP(NETIF_MSG_LINK, "reset external PHY\n");
6146 }
6147
6148 static int bnx2x_update_link_down(struct link_params *params,
6149                                   struct link_vars *vars)
6150 {
6151         struct bnx2x *bp = params->bp;
6152         u8 port = params->port;
6153
6154         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6155         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6156         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6157         /* indicate no mac active */
6158         vars->mac_type = MAC_TYPE_NONE;
6159
6160         /* update shared memory */
6161         vars->link_status &= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK |
6162                                LINK_STATUS_LINK_UP |
6163                                LINK_STATUS_AUTO_NEGOTIATE_COMPLETE |
6164                                LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK |
6165                                LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK |
6166                                LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK);
6167         vars->line_speed = 0;
6168         bnx2x_update_mng(params, vars->link_status);
6169
6170         /* activate nig drain */
6171         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6172
6173         /* disable emac */
6174         if (!CHIP_IS_E3(bp))
6175                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6176
6177         msleep(10);
6178         /* reset BigMac/Xmac */
6179         if (CHIP_IS_E1x(bp) ||
6180             CHIP_IS_E2(bp)) {
6181                 bnx2x_bmac_rx_disable(bp, params->port);
6182                 REG_WR(bp, GRCBASE_MISC +
6183                        MISC_REGISTERS_RESET_REG_2_CLEAR,
6184                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6185         }
6186         if (CHIP_IS_E3(bp))
6187                 bnx2x_xmac_disable(params);
6188
6189         return 0;
6190 }
6191
6192 static int bnx2x_update_link_up(struct link_params *params,
6193                                 struct link_vars *vars,
6194                                 u8 link_10g)
6195 {
6196         struct bnx2x *bp = params->bp;
6197         u8 port = params->port;
6198         int rc = 0;
6199
6200         vars->link_status |= LINK_STATUS_LINK_UP;
6201         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6202
6203         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6204                 vars->link_status |=
6205                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6206
6207         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6208                 vars->link_status |=
6209                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6210         if (USES_WARPCORE(bp)) {
6211                 if (link_10g) {
6212                         if (bnx2x_xmac_enable(params, vars, 0) ==
6213                             -ESRCH) {
6214                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6215                                 vars->link_up = 0;
6216                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6217                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6218                         }
6219                 } else
6220                         bnx2x_umac_enable(params, vars, 0);
6221                 bnx2x_set_led(params, vars,
6222                               LED_MODE_OPER, vars->line_speed);
6223         }
6224         if ((CHIP_IS_E1x(bp) ||
6225              CHIP_IS_E2(bp))) {
6226                 if (link_10g) {
6227                         if (bnx2x_bmac_enable(params, vars, 0) ==
6228                             -ESRCH) {
6229                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6230                                 vars->link_up = 0;
6231                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6232                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6233                         }
6234
6235                         bnx2x_set_led(params, vars,
6236                                       LED_MODE_OPER, SPEED_10000);
6237                 } else {
6238                         rc = bnx2x_emac_program(params, vars);
6239                         bnx2x_emac_enable(params, vars, 0);
6240
6241                         /* AN complete? */
6242                         if ((vars->link_status &
6243                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6244                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6245                             SINGLE_MEDIA_DIRECT(params))
6246                                 bnx2x_set_gmii_tx_driver(params);
6247                 }
6248         }
6249
6250         /* PBF - link up */
6251         if (CHIP_IS_E1x(bp))
6252                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6253                                        vars->line_speed);
6254
6255         /* disable drain */
6256         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6257
6258         /* update shared memory */
6259         bnx2x_update_mng(params, vars->link_status);
6260         msleep(20);
6261         return rc;
6262 }
6263 /*
6264  * The bnx2x_link_update function should be called upon link
6265  * interrupt.
6266  * Link is considered up as follows:
6267  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6268  *   to be up
6269  * - SINGLE_MEDIA - The link between the 577xx and the external
6270  *   phy (XGXS) need to up as well as the external link of the
6271  *   phy (PHY_EXT1)
6272  * - DUAL_MEDIA - The link between the 577xx and the first
6273  *   external phy needs to be up, and at least one of the 2
6274  *   external phy link must be up.
6275  */
6276 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6277 {
6278         struct bnx2x *bp = params->bp;
6279         struct link_vars phy_vars[MAX_PHYS];
6280         u8 port = params->port;
6281         u8 link_10g_plus, phy_index;
6282         u8 ext_phy_link_up = 0, cur_link_up;
6283         int rc = 0;
6284         u8 is_mi_int = 0;
6285         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6286         u8 active_external_phy = INT_PHY;
6287         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6288         for (phy_index = INT_PHY; phy_index < params->num_phys;
6289               phy_index++) {
6290                 phy_vars[phy_index].flow_ctrl = 0;
6291                 phy_vars[phy_index].link_status = 0;
6292                 phy_vars[phy_index].line_speed = 0;
6293                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6294                 phy_vars[phy_index].phy_link_up = 0;
6295                 phy_vars[phy_index].link_up = 0;
6296                 phy_vars[phy_index].fault_detected = 0;
6297         }
6298
6299         if (USES_WARPCORE(bp))
6300                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6301
6302         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6303                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6304                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6305
6306         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6307                                 port*0x18) > 0);
6308         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6309                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6310                  is_mi_int,
6311                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6312
6313         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6314           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6315           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6316
6317         /* disable emac */
6318         if (!CHIP_IS_E3(bp))
6319                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6320
6321         /*
6322          * Step 1:
6323          * Check external link change only for external phys, and apply
6324          * priority selection between them in case the link on both phys
6325          * is up. Note that instead of the common vars, a temporary
6326          * vars argument is used since each phy may have different link/
6327          * speed/duplex result
6328          */
6329         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6330               phy_index++) {
6331                 struct bnx2x_phy *phy = &params->phy[phy_index];
6332                 if (!phy->read_status)
6333                         continue;
6334                 /* Read link status and params of this ext phy */
6335                 cur_link_up = phy->read_status(phy, params,
6336                                                &phy_vars[phy_index]);
6337                 if (cur_link_up) {
6338                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6339                                    phy_index);
6340                 } else {
6341                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6342                                    phy_index);
6343                         continue;
6344                 }
6345
6346                 if (!ext_phy_link_up) {
6347                         ext_phy_link_up = 1;
6348                         active_external_phy = phy_index;
6349                 } else {
6350                         switch (bnx2x_phy_selection(params)) {
6351                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6352                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6353                         /*
6354                          * In this option, the first PHY makes sure to pass the
6355                          * traffic through itself only.
6356                          * Its not clear how to reset the link on the second phy
6357                          */
6358                                 active_external_phy = EXT_PHY1;
6359                                 break;
6360                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6361                         /*
6362                          * In this option, the first PHY makes sure to pass the
6363                          * traffic through the second PHY.
6364                          */
6365                                 active_external_phy = EXT_PHY2;
6366                                 break;
6367                         default:
6368                         /*
6369                          * Link indication on both PHYs with the following cases
6370                          * is invalid:
6371                          * - FIRST_PHY means that second phy wasn't initialized,
6372                          * hence its link is expected to be down
6373                          * - SECOND_PHY means that first phy should not be able
6374                          * to link up by itself (using configuration)
6375                          * - DEFAULT should be overriden during initialiazation
6376                          */
6377                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6378                                            "mpc=0x%x. DISABLING LINK !!!\n",
6379                                            params->multi_phy_config);
6380                                 ext_phy_link_up = 0;
6381                                 break;
6382                         }
6383                 }
6384         }
6385         prev_line_speed = vars->line_speed;
6386         /*
6387          * Step 2:
6388          * Read the status of the internal phy. In case of
6389          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6390          * otherwise this is the link between the 577xx and the first
6391          * external phy
6392          */
6393         if (params->phy[INT_PHY].read_status)
6394                 params->phy[INT_PHY].read_status(
6395                         &params->phy[INT_PHY],
6396                         params, vars);
6397         /*
6398          * The INT_PHY flow control reside in the vars. This include the
6399          * case where the speed or flow control are not set to AUTO.
6400          * Otherwise, the active external phy flow control result is set
6401          * to the vars. The ext_phy_line_speed is needed to check if the
6402          * speed is different between the internal phy and external phy.
6403          * This case may be result of intermediate link speed change.
6404          */
6405         if (active_external_phy > INT_PHY) {
6406                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6407                 /*
6408                  * Link speed is taken from the XGXS. AN and FC result from
6409                  * the external phy.
6410                  */
6411                 vars->link_status |= phy_vars[active_external_phy].link_status;
6412
6413                 /*
6414                  * if active_external_phy is first PHY and link is up - disable
6415                  * disable TX on second external PHY
6416                  */
6417                 if (active_external_phy == EXT_PHY1) {
6418                         if (params->phy[EXT_PHY2].phy_specific_func) {
6419                                 DP(NETIF_MSG_LINK, "Disabling TX on"
6420                                                    " EXT_PHY2\n");
6421                                 params->phy[EXT_PHY2].phy_specific_func(
6422                                         &params->phy[EXT_PHY2],
6423                                         params, DISABLE_TX);
6424                         }
6425                 }
6426
6427                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6428                 vars->duplex = phy_vars[active_external_phy].duplex;
6429                 if (params->phy[active_external_phy].supported &
6430                     SUPPORTED_FIBRE)
6431                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6432                 else
6433                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6434                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6435                            active_external_phy);
6436         }
6437
6438         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6439               phy_index++) {
6440                 if (params->phy[phy_index].flags &
6441                     FLAGS_REARM_LATCH_SIGNAL) {
6442                         bnx2x_rearm_latch_signal(bp, port,
6443                                                  phy_index ==
6444                                                  active_external_phy);
6445                         break;
6446                 }
6447         }
6448         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6449                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6450                    vars->link_status, ext_phy_line_speed);
6451         /*
6452          * Upon link speed change set the NIG into drain mode. Comes to
6453          * deals with possible FIFO glitch due to clk change when speed
6454          * is decreased without link down indicator
6455          */
6456
6457         if (vars->phy_link_up) {
6458                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6459                     (ext_phy_line_speed != vars->line_speed)) {
6460                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6461                                    " different than the external"
6462                                    " link speed %d\n", vars->line_speed,
6463                                    ext_phy_line_speed);
6464                         vars->phy_link_up = 0;
6465                 } else if (prev_line_speed != vars->line_speed) {
6466                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6467                                0);
6468                         msleep(1);
6469                 }
6470         }
6471
6472         /* anything 10 and over uses the bmac */
6473         link_10g_plus = (vars->line_speed >= SPEED_10000);
6474
6475         bnx2x_link_int_ack(params, vars, link_10g_plus);
6476
6477         /*
6478          * In case external phy link is up, and internal link is down
6479          * (not initialized yet probably after link initialization, it
6480          * needs to be initialized.
6481          * Note that after link down-up as result of cable plug, the xgxs
6482          * link would probably become up again without the need
6483          * initialize it
6484          */
6485         if (!(SINGLE_MEDIA_DIRECT(params))) {
6486                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6487                            " init_preceding = %d\n", ext_phy_link_up,
6488                            vars->phy_link_up,
6489                            params->phy[EXT_PHY1].flags &
6490                            FLAGS_INIT_XGXS_FIRST);
6491                 if (!(params->phy[EXT_PHY1].flags &
6492                       FLAGS_INIT_XGXS_FIRST)
6493                     && ext_phy_link_up && !vars->phy_link_up) {
6494                         vars->line_speed = ext_phy_line_speed;
6495                         if (vars->line_speed < SPEED_1000)
6496                                 vars->phy_flags |= PHY_SGMII_FLAG;
6497                         else
6498                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6499
6500                         if (params->phy[INT_PHY].config_init)
6501                                 params->phy[INT_PHY].config_init(
6502                                         &params->phy[INT_PHY], params,
6503                                                 vars);
6504                 }
6505         }
6506         /*
6507          * Link is up only if both local phy and external phy (in case of
6508          * non-direct board) are up and no fault detected on active PHY.
6509          */
6510         vars->link_up = (vars->phy_link_up &&
6511                          (ext_phy_link_up ||
6512                           SINGLE_MEDIA_DIRECT(params)) &&
6513                          (phy_vars[active_external_phy].fault_detected == 0));
6514
6515         if (vars->link_up)
6516                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6517         else
6518                 rc = bnx2x_update_link_down(params, vars);
6519
6520         return rc;
6521 }
6522
6523
6524 /*****************************************************************************/
6525 /*                          External Phy section                             */
6526 /*****************************************************************************/
6527 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
6528 {
6529         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6530                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6531         msleep(1);
6532         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6533                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
6534 }
6535
6536 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
6537                                       u32 spirom_ver, u32 ver_addr)
6538 {
6539         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
6540                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
6541
6542         if (ver_addr)
6543                 REG_WR(bp, ver_addr, spirom_ver);
6544 }
6545
6546 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
6547                                       struct bnx2x_phy *phy,
6548                                       u8 port)
6549 {
6550         u16 fw_ver1, fw_ver2;
6551
6552         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6553                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6554         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
6555                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
6556         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
6557                                   phy->ver_addr);
6558 }
6559
6560 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
6561                                        struct bnx2x_phy *phy,
6562                                        struct link_vars *vars)
6563 {
6564         u16 val;
6565         bnx2x_cl45_read(bp, phy,
6566                         MDIO_AN_DEVAD,
6567                         MDIO_AN_REG_STATUS, &val);
6568         bnx2x_cl45_read(bp, phy,
6569                         MDIO_AN_DEVAD,
6570                         MDIO_AN_REG_STATUS, &val);
6571         if (val & (1<<5))
6572                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6573         if ((val & (1<<0)) == 0)
6574                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
6575 }
6576
6577 /******************************************************************/
6578 /*              common BCM8073/BCM8727 PHY SECTION                */
6579 /******************************************************************/
6580 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
6581                                   struct link_params *params,
6582                                   struct link_vars *vars)
6583 {
6584         struct bnx2x *bp = params->bp;
6585         if (phy->req_line_speed == SPEED_10 ||
6586             phy->req_line_speed == SPEED_100) {
6587                 vars->flow_ctrl = phy->req_flow_ctrl;
6588                 return;
6589         }
6590
6591         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
6592             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
6593                 u16 pause_result;
6594                 u16 ld_pause;           /* local */
6595                 u16 lp_pause;           /* link partner */
6596                 bnx2x_cl45_read(bp, phy,
6597                                 MDIO_AN_DEVAD,
6598                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
6599
6600                 bnx2x_cl45_read(bp, phy,
6601                                 MDIO_AN_DEVAD,
6602                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
6603                 pause_result = (ld_pause &
6604                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
6605                 pause_result |= (lp_pause &
6606                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
6607
6608                 bnx2x_pause_resolve(vars, pause_result);
6609                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
6610                            pause_result);
6611         }
6612 }
6613 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
6614                                              struct bnx2x_phy *phy,
6615                                              u8 port)
6616 {
6617         u32 count = 0;
6618         u16 fw_ver1, fw_msgout;
6619         int rc = 0;
6620
6621         /* Boot port from external ROM  */
6622         /* EDC grst */
6623         bnx2x_cl45_write(bp, phy,
6624                          MDIO_PMA_DEVAD,
6625                          MDIO_PMA_REG_GEN_CTRL,
6626                          0x0001);
6627
6628         /* ucode reboot and rst */
6629         bnx2x_cl45_write(bp, phy,
6630                          MDIO_PMA_DEVAD,
6631                          MDIO_PMA_REG_GEN_CTRL,
6632                          0x008c);
6633
6634         bnx2x_cl45_write(bp, phy,
6635                          MDIO_PMA_DEVAD,
6636                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
6637
6638         /* Reset internal microprocessor */
6639         bnx2x_cl45_write(bp, phy,
6640                          MDIO_PMA_DEVAD,
6641                          MDIO_PMA_REG_GEN_CTRL,
6642                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
6643
6644         /* Release srst bit */
6645         bnx2x_cl45_write(bp, phy,
6646                          MDIO_PMA_DEVAD,
6647                          MDIO_PMA_REG_GEN_CTRL,
6648                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
6649
6650         /* Delay 100ms per the PHY specifications */
6651         msleep(100);
6652
6653         /* 8073 sometimes taking longer to download */
6654         do {
6655                 count++;
6656                 if (count > 300) {
6657                         DP(NETIF_MSG_LINK,
6658                                  "bnx2x_8073_8727_external_rom_boot port %x:"
6659                                  "Download failed. fw version = 0x%x\n",
6660                                  port, fw_ver1);
6661                         rc = -EINVAL;
6662                         break;
6663                 }
6664
6665                 bnx2x_cl45_read(bp, phy,
6666                                 MDIO_PMA_DEVAD,
6667                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
6668                 bnx2x_cl45_read(bp, phy,
6669                                 MDIO_PMA_DEVAD,
6670                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
6671
6672                 msleep(1);
6673         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
6674                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
6675                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
6676
6677         /* Clear ser_boot_ctl bit */
6678         bnx2x_cl45_write(bp, phy,
6679                          MDIO_PMA_DEVAD,
6680                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
6681         bnx2x_save_bcm_spirom_ver(bp, phy, port);
6682
6683         DP(NETIF_MSG_LINK,
6684                  "bnx2x_8073_8727_external_rom_boot port %x:"
6685                  "Download complete. fw version = 0x%x\n",
6686                  port, fw_ver1);
6687
6688         return rc;
6689 }
6690
6691 /******************************************************************/
6692 /*                      BCM8073 PHY SECTION                       */
6693 /******************************************************************/
6694 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
6695 {
6696         /* This is only required for 8073A1, version 102 only */
6697         u16 val;
6698
6699         /* Read 8073 HW revision*/
6700         bnx2x_cl45_read(bp, phy,
6701                         MDIO_PMA_DEVAD,
6702                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6703
6704         if (val != 1) {
6705                 /* No need to workaround in 8073 A1 */
6706                 return 0;
6707         }
6708
6709         bnx2x_cl45_read(bp, phy,
6710                         MDIO_PMA_DEVAD,
6711                         MDIO_PMA_REG_ROM_VER2, &val);
6712
6713         /* SNR should be applied only for version 0x102 */
6714         if (val != 0x102)
6715                 return 0;
6716
6717         return 1;
6718 }
6719
6720 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
6721 {
6722         u16 val, cnt, cnt1 ;
6723
6724         bnx2x_cl45_read(bp, phy,
6725                         MDIO_PMA_DEVAD,
6726                         MDIO_PMA_REG_8073_CHIP_REV, &val);
6727
6728         if (val > 0) {
6729                 /* No need to workaround in 8073 A1 */
6730                 return 0;
6731         }
6732         /* XAUI workaround in 8073 A0: */
6733
6734         /*
6735          * After loading the boot ROM and restarting Autoneg, poll
6736          * Dev1, Reg $C820:
6737          */
6738
6739         for (cnt = 0; cnt < 1000; cnt++) {
6740                 bnx2x_cl45_read(bp, phy,
6741                                 MDIO_PMA_DEVAD,
6742                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
6743                                 &val);
6744                   /*
6745                    * If bit [14] = 0 or bit [13] = 0, continue on with
6746                    * system initialization (XAUI work-around not required, as
6747                    * these bits indicate 2.5G or 1G link up).
6748                    */
6749                 if (!(val & (1<<14)) || !(val & (1<<13))) {
6750                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
6751                         return 0;
6752                 } else if (!(val & (1<<15))) {
6753                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
6754                         /*
6755                          * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
6756                          * MSB (bit15) goes to 1 (indicating that the XAUI
6757                          * workaround has completed), then continue on with
6758                          * system initialization.
6759                          */
6760                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
6761                                 bnx2x_cl45_read(bp, phy,
6762                                         MDIO_PMA_DEVAD,
6763                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
6764                                 if (val & (1<<15)) {
6765                                         DP(NETIF_MSG_LINK,
6766                                           "XAUI workaround has completed\n");
6767                                         return 0;
6768                                  }
6769                                  msleep(3);
6770                         }
6771                         break;
6772                 }
6773                 msleep(3);
6774         }
6775         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
6776         return -EINVAL;
6777 }
6778
6779 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
6780 {
6781         /* Force KR or KX */
6782         bnx2x_cl45_write(bp, phy,
6783                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
6784         bnx2x_cl45_write(bp, phy,
6785                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
6786         bnx2x_cl45_write(bp, phy,
6787                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
6788         bnx2x_cl45_write(bp, phy,
6789                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
6790 }
6791
6792 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
6793                                       struct bnx2x_phy *phy,
6794                                       struct link_vars *vars)
6795 {
6796         u16 cl37_val;
6797         struct bnx2x *bp = params->bp;
6798         bnx2x_cl45_read(bp, phy,
6799                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
6800
6801         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6802         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
6803         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6804         if ((vars->ieee_fc &
6805             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
6806             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
6807                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
6808         }
6809         if ((vars->ieee_fc &
6810             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
6811             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
6812                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
6813         }
6814         if ((vars->ieee_fc &
6815             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
6816             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
6817                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
6818         }
6819         DP(NETIF_MSG_LINK,
6820                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
6821
6822         bnx2x_cl45_write(bp, phy,
6823                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
6824         msleep(500);
6825 }
6826
6827 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
6828                                   struct link_params *params,
6829                                   struct link_vars *vars)
6830 {
6831         struct bnx2x *bp = params->bp;
6832         u16 val = 0, tmp1;
6833         u8 gpio_port;
6834         DP(NETIF_MSG_LINK, "Init 8073\n");
6835
6836         if (CHIP_IS_E2(bp))
6837                 gpio_port = BP_PATH(bp);
6838         else
6839                 gpio_port = params->port;
6840         /* Restore normal power mode*/
6841         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6842                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6843
6844         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6845                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
6846
6847         /* enable LASI */
6848         bnx2x_cl45_write(bp, phy,
6849                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
6850         bnx2x_cl45_write(bp, phy,
6851                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
6852
6853         bnx2x_8073_set_pause_cl37(params, phy, vars);
6854
6855         bnx2x_cl45_read(bp, phy,
6856                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
6857
6858         bnx2x_cl45_read(bp, phy,
6859                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
6860
6861         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
6862
6863         /* Swap polarity if required - Must be done only in non-1G mode */
6864         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
6865                 /* Configure the 8073 to swap _P and _N of the KR lines */
6866                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
6867                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
6868                 bnx2x_cl45_read(bp, phy,
6869                                 MDIO_PMA_DEVAD,
6870                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
6871                 bnx2x_cl45_write(bp, phy,
6872                                  MDIO_PMA_DEVAD,
6873                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
6874                                  (val | (3<<9)));
6875         }
6876
6877
6878         /* Enable CL37 BAM */
6879         if (REG_RD(bp, params->shmem_base +
6880                          offsetof(struct shmem_region, dev_info.
6881                                   port_hw_config[params->port].default_cfg)) &
6882             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
6883
6884                 bnx2x_cl45_read(bp, phy,
6885                                 MDIO_AN_DEVAD,
6886                                 MDIO_AN_REG_8073_BAM, &val);
6887                 bnx2x_cl45_write(bp, phy,
6888                                  MDIO_AN_DEVAD,
6889                                  MDIO_AN_REG_8073_BAM, val | 1);
6890                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
6891         }
6892         if (params->loopback_mode == LOOPBACK_EXT) {
6893                 bnx2x_807x_force_10G(bp, phy);
6894                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
6895                 return 0;
6896         } else {
6897                 bnx2x_cl45_write(bp, phy,
6898                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
6899         }
6900         if (phy->req_line_speed != SPEED_AUTO_NEG) {
6901                 if (phy->req_line_speed == SPEED_10000) {
6902                         val = (1<<7);
6903                 } else if (phy->req_line_speed ==  SPEED_2500) {
6904                         val = (1<<5);
6905                         /*
6906                          * Note that 2.5G works only when used with 1G
6907                          * advertisement
6908                          */
6909                 } else
6910                         val = (1<<5);
6911         } else {
6912                 val = 0;
6913                 if (phy->speed_cap_mask &
6914                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6915                         val |= (1<<7);
6916
6917                 /* Note that 2.5G works only when used with 1G advertisement */
6918                 if (phy->speed_cap_mask &
6919                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
6920                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
6921                         val |= (1<<5);
6922                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
6923         }
6924
6925         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
6926         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
6927
6928         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
6929              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
6930             (phy->req_line_speed == SPEED_2500)) {
6931                 u16 phy_ver;
6932                 /* Allow 2.5G for A1 and above */
6933                 bnx2x_cl45_read(bp, phy,
6934                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
6935                                 &phy_ver);
6936                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
6937                 if (phy_ver > 0)
6938                         tmp1 |= 1;
6939                 else
6940                         tmp1 &= 0xfffe;
6941         } else {
6942                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
6943                 tmp1 &= 0xfffe;
6944         }
6945
6946         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
6947         /* Add support for CL37 (passive mode) II */
6948
6949         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
6950         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
6951                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
6952                                   0x20 : 0x40)));
6953
6954         /* Add support for CL37 (passive mode) III */
6955         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
6956
6957         /*
6958          * The SNR will improve about 2db by changing BW and FEE main
6959          * tap. Rest commands are executed after link is up
6960          * Change FFE main cursor to 5 in EDC register
6961          */
6962         if (bnx2x_8073_is_snr_needed(bp, phy))
6963                 bnx2x_cl45_write(bp, phy,
6964                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
6965                                  0xFB0C);
6966
6967         /* Enable FEC (Forware Error Correction) Request in the AN */
6968         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
6969         tmp1 |= (1<<15);
6970         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
6971
6972         bnx2x_ext_phy_set_pause(params, phy, vars);
6973
6974         /* Restart autoneg */
6975         msleep(500);
6976         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
6977         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
6978                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
6979         return 0;
6980 }
6981
6982 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
6983                                  struct link_params *params,
6984                                  struct link_vars *vars)
6985 {
6986         struct bnx2x *bp = params->bp;
6987         u8 link_up = 0;
6988         u16 val1, val2;
6989         u16 link_status = 0;
6990         u16 an1000_status = 0;
6991
6992         bnx2x_cl45_read(bp, phy,
6993                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
6994
6995         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
6996
6997         /* clear the interrupt LASI status register */
6998         bnx2x_cl45_read(bp, phy,
6999                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7000         bnx2x_cl45_read(bp, phy,
7001                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7002         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7003         /* Clear MSG-OUT */
7004         bnx2x_cl45_read(bp, phy,
7005                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7006
7007         /* Check the LASI */
7008         bnx2x_cl45_read(bp, phy,
7009                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7010
7011         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7012
7013         /* Check the link status */
7014         bnx2x_cl45_read(bp, phy,
7015                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7016         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7017
7018         bnx2x_cl45_read(bp, phy,
7019                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7020         bnx2x_cl45_read(bp, phy,
7021                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7022         link_up = ((val1 & 4) == 4);
7023         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7024
7025         if (link_up &&
7026              ((phy->req_line_speed != SPEED_10000))) {
7027                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7028                         return 0;
7029         }
7030         bnx2x_cl45_read(bp, phy,
7031                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7032         bnx2x_cl45_read(bp, phy,
7033                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7034
7035         /* Check the link status on 1.1.2 */
7036         bnx2x_cl45_read(bp, phy,
7037                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7038         bnx2x_cl45_read(bp, phy,
7039                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7040         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7041                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7042
7043         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7044         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7045                 /*
7046                  * The SNR will improve about 2dbby changing the BW and FEE main
7047                  * tap. The 1st write to change FFE main tap is set before
7048                  * restart AN. Change PLL Bandwidth in EDC register
7049                  */
7050                 bnx2x_cl45_write(bp, phy,
7051                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7052                                  0x26BC);
7053
7054                 /* Change CDR Bandwidth in EDC register */
7055                 bnx2x_cl45_write(bp, phy,
7056                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7057                                  0x0333);
7058         }
7059         bnx2x_cl45_read(bp, phy,
7060                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7061                         &link_status);
7062
7063         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7064         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7065                 link_up = 1;
7066                 vars->line_speed = SPEED_10000;
7067                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7068                            params->port);
7069         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7070                 link_up = 1;
7071                 vars->line_speed = SPEED_2500;
7072                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7073                            params->port);
7074         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7075                 link_up = 1;
7076                 vars->line_speed = SPEED_1000;
7077                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7078                            params->port);
7079         } else {
7080                 link_up = 0;
7081                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7082                            params->port);
7083         }
7084
7085         if (link_up) {
7086                 /* Swap polarity if required */
7087                 if (params->lane_config &
7088                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7089                         /* Configure the 8073 to swap P and N of the KR lines */
7090                         bnx2x_cl45_read(bp, phy,
7091                                         MDIO_XS_DEVAD,
7092                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7093                         /*
7094                          * Set bit 3 to invert Rx in 1G mode and clear this bit
7095                          * when it`s in 10G mode.
7096                          */
7097                         if (vars->line_speed == SPEED_1000) {
7098                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7099                                               "the 8073\n");
7100                                 val1 |= (1<<3);
7101                         } else
7102                                 val1 &= ~(1<<3);
7103
7104                         bnx2x_cl45_write(bp, phy,
7105                                          MDIO_XS_DEVAD,
7106                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7107                                          val1);
7108                 }
7109                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7110                 bnx2x_8073_resolve_fc(phy, params, vars);
7111                 vars->duplex = DUPLEX_FULL;
7112         }
7113         return link_up;
7114 }
7115
7116 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7117                                   struct link_params *params)
7118 {
7119         struct bnx2x *bp = params->bp;
7120         u8 gpio_port;
7121         if (CHIP_IS_E2(bp))
7122                 gpio_port = BP_PATH(bp);
7123         else
7124                 gpio_port = params->port;
7125         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7126            gpio_port);
7127         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7128                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7129                        gpio_port);
7130 }
7131
7132 /******************************************************************/
7133 /*                      BCM8705 PHY SECTION                       */
7134 /******************************************************************/
7135 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7136                                   struct link_params *params,
7137                                   struct link_vars *vars)
7138 {
7139         struct bnx2x *bp = params->bp;
7140         DP(NETIF_MSG_LINK, "init 8705\n");
7141         /* Restore normal power mode*/
7142         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7143                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7144         /* HW reset */
7145         bnx2x_ext_phy_hw_reset(bp, params->port);
7146         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7147         bnx2x_wait_reset_complete(bp, phy, params);
7148
7149         bnx2x_cl45_write(bp, phy,
7150                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7151         bnx2x_cl45_write(bp, phy,
7152                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7153         bnx2x_cl45_write(bp, phy,
7154                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7155         bnx2x_cl45_write(bp, phy,
7156                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7157         /* BCM8705 doesn't have microcode, hence the 0 */
7158         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7159         return 0;
7160 }
7161
7162 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7163                                  struct link_params *params,
7164                                  struct link_vars *vars)
7165 {
7166         u8 link_up = 0;
7167         u16 val1, rx_sd;
7168         struct bnx2x *bp = params->bp;
7169         DP(NETIF_MSG_LINK, "read status 8705\n");
7170         bnx2x_cl45_read(bp, phy,
7171                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7172         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7173
7174         bnx2x_cl45_read(bp, phy,
7175                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7176         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7177
7178         bnx2x_cl45_read(bp, phy,
7179                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7180
7181         bnx2x_cl45_read(bp, phy,
7182                       MDIO_PMA_DEVAD, 0xc809, &val1);
7183         bnx2x_cl45_read(bp, phy,
7184                       MDIO_PMA_DEVAD, 0xc809, &val1);
7185
7186         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7187         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7188         if (link_up) {
7189                 vars->line_speed = SPEED_10000;
7190                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7191         }
7192         return link_up;
7193 }
7194
7195 /******************************************************************/
7196 /*                      SFP+ module Section                       */
7197 /******************************************************************/
7198 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7199                                            struct bnx2x_phy *phy,
7200                                            u8 pmd_dis)
7201 {
7202         struct bnx2x *bp = params->bp;
7203         /*
7204          * Disable transmitter only for bootcodes which can enable it afterwards
7205          * (for D3 link)
7206          */
7207         if (pmd_dis) {
7208                 if (params->feature_config_flags &
7209                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7210                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7211                 else {
7212                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7213                         return;
7214                 }
7215         } else
7216                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7217         bnx2x_cl45_write(bp, phy,
7218                          MDIO_PMA_DEVAD,
7219                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7220 }
7221
7222 static u8 bnx2x_get_gpio_port(struct link_params *params)
7223 {
7224         u8 gpio_port;
7225         u32 swap_val, swap_override;
7226         struct bnx2x *bp = params->bp;
7227         if (CHIP_IS_E2(bp))
7228                 gpio_port = BP_PATH(bp);
7229         else
7230                 gpio_port = params->port;
7231         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7232         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7233         return gpio_port ^ (swap_val && swap_override);
7234 }
7235
7236 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7237                                            struct bnx2x_phy *phy,
7238                                            u8 tx_en)
7239 {
7240         u16 val;
7241         u8 port = params->port;
7242         struct bnx2x *bp = params->bp;
7243         u32 tx_en_mode;
7244
7245         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7246         tx_en_mode = REG_RD(bp, params->shmem_base +
7247                             offsetof(struct shmem_region,
7248                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7249                 PORT_HW_CFG_TX_LASER_MASK;
7250         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7251                            "mode = %x\n", tx_en, port, tx_en_mode);
7252         switch (tx_en_mode) {
7253         case PORT_HW_CFG_TX_LASER_MDIO:
7254
7255                 bnx2x_cl45_read(bp, phy,
7256                                 MDIO_PMA_DEVAD,
7257                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7258                                 &val);
7259
7260                 if (tx_en)
7261                         val &= ~(1<<15);
7262                 else
7263                         val |= (1<<15);
7264
7265                 bnx2x_cl45_write(bp, phy,
7266                                  MDIO_PMA_DEVAD,
7267                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7268                                  val);
7269         break;
7270         case PORT_HW_CFG_TX_LASER_GPIO0:
7271         case PORT_HW_CFG_TX_LASER_GPIO1:
7272         case PORT_HW_CFG_TX_LASER_GPIO2:
7273         case PORT_HW_CFG_TX_LASER_GPIO3:
7274         {
7275                 u16 gpio_pin;
7276                 u8 gpio_port, gpio_mode;
7277                 if (tx_en)
7278                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7279                 else
7280                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7281
7282                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7283                 gpio_port = bnx2x_get_gpio_port(params);
7284                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7285                 break;
7286         }
7287         default:
7288                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7289                 break;
7290         }
7291 }
7292
7293 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7294                                       struct bnx2x_phy *phy,
7295                                       u8 tx_en)
7296 {
7297         struct bnx2x *bp = params->bp;
7298         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7299         if (CHIP_IS_E3(bp))
7300                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7301         else
7302                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7303 }
7304
7305 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7306                                              struct link_params *params,
7307                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7308 {
7309         struct bnx2x *bp = params->bp;
7310         u16 val = 0;
7311         u16 i;
7312         if (byte_cnt > 16) {
7313                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7314                             " is limited to 0xf\n");
7315                 return -EINVAL;
7316         }
7317         /* Set the read command byte count */
7318         bnx2x_cl45_write(bp, phy,
7319                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7320                          (byte_cnt | 0xa000));
7321
7322         /* Set the read command address */
7323         bnx2x_cl45_write(bp, phy,
7324                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7325                          addr);
7326
7327         /* Activate read command */
7328         bnx2x_cl45_write(bp, phy,
7329                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7330                          0x2c0f);
7331
7332         /* Wait up to 500us for command complete status */
7333         for (i = 0; i < 100; i++) {
7334                 bnx2x_cl45_read(bp, phy,
7335                                 MDIO_PMA_DEVAD,
7336                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7337                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7338                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7339                         break;
7340                 udelay(5);
7341         }
7342
7343         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7344                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7345                 DP(NETIF_MSG_LINK,
7346                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7347                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7348                 return -EINVAL;
7349         }
7350
7351         /* Read the buffer */
7352         for (i = 0; i < byte_cnt; i++) {
7353                 bnx2x_cl45_read(bp, phy,
7354                                 MDIO_PMA_DEVAD,
7355                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7356                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7357         }
7358
7359         for (i = 0; i < 100; i++) {
7360                 bnx2x_cl45_read(bp, phy,
7361                                 MDIO_PMA_DEVAD,
7362                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7363                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7364                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7365                         return 0;
7366                 msleep(1);
7367         }
7368         return -EINVAL;
7369 }
7370
7371 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7372                                                  struct link_params *params,
7373                                                  u16 addr, u8 byte_cnt,
7374                                                  u8 *o_buf)
7375 {
7376         int rc = 0;
7377         u8 i, j = 0, cnt = 0;
7378         u32 data_array[4];
7379         u16 addr32;
7380         struct bnx2x *bp = params->bp;
7381         /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7382                                         " addr %d, cnt %d\n",
7383                                         addr, byte_cnt);*/
7384         if (byte_cnt > 16) {
7385                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7386                             " is limited to 16 bytes\n");
7387                 return -EINVAL;
7388         }
7389
7390         /* 4 byte aligned address */
7391         addr32 = addr & (~0x3);
7392         do {
7393                 rc = bnx2x_bsc_read(params, phy, 0xa0, addr32, 0, byte_cnt,
7394                                     data_array);
7395         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7396
7397         if (rc == 0) {
7398                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7399                         o_buf[j] = *((u8 *)data_array + i);
7400                         j++;
7401                 }
7402         }
7403
7404         return rc;
7405 }
7406
7407 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7408                                              struct link_params *params,
7409                                              u16 addr, u8 byte_cnt, u8 *o_buf)
7410 {
7411         struct bnx2x *bp = params->bp;
7412         u16 val, i;
7413
7414         if (byte_cnt > 16) {
7415                 DP(NETIF_MSG_LINK, "Reading from eeprom is"
7416                             " is limited to 0xf\n");
7417                 return -EINVAL;
7418         }
7419
7420         /* Need to read from 1.8000 to clear it */
7421         bnx2x_cl45_read(bp, phy,
7422                         MDIO_PMA_DEVAD,
7423                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7424                         &val);
7425
7426         /* Set the read command byte count */
7427         bnx2x_cl45_write(bp, phy,
7428                          MDIO_PMA_DEVAD,
7429                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7430                          ((byte_cnt < 2) ? 2 : byte_cnt));
7431
7432         /* Set the read command address */
7433         bnx2x_cl45_write(bp, phy,
7434                          MDIO_PMA_DEVAD,
7435                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7436                          addr);
7437         /* Set the destination address */
7438         bnx2x_cl45_write(bp, phy,
7439                          MDIO_PMA_DEVAD,
7440                          0x8004,
7441                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7442
7443         /* Activate read command */
7444         bnx2x_cl45_write(bp, phy,
7445                          MDIO_PMA_DEVAD,
7446                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7447                          0x8002);
7448         /*
7449          * Wait appropriate time for two-wire command to finish before
7450          * polling the status register
7451          */
7452         msleep(1);
7453
7454         /* Wait up to 500us for command complete status */
7455         for (i = 0; i < 100; i++) {
7456                 bnx2x_cl45_read(bp, phy,
7457                                 MDIO_PMA_DEVAD,
7458                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7459                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7460                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7461                         break;
7462                 udelay(5);
7463         }
7464
7465         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7466                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7467                 DP(NETIF_MSG_LINK,
7468                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7469                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7470                 return -EFAULT;
7471         }
7472
7473         /* Read the buffer */
7474         for (i = 0; i < byte_cnt; i++) {
7475                 bnx2x_cl45_read(bp, phy,
7476                                 MDIO_PMA_DEVAD,
7477                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
7478                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
7479         }
7480
7481         for (i = 0; i < 100; i++) {
7482                 bnx2x_cl45_read(bp, phy,
7483                                 MDIO_PMA_DEVAD,
7484                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7485                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7486                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7487                         return 0;
7488                 msleep(1);
7489         }
7490
7491         return -EINVAL;
7492 }
7493
7494 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7495                                  struct link_params *params, u16 addr,
7496                                  u8 byte_cnt, u8 *o_buf)
7497 {
7498         int rc = -EINVAL;
7499         switch (phy->type) {
7500         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
7501                 rc = bnx2x_8726_read_sfp_module_eeprom(phy, params, addr,
7502                                                        byte_cnt, o_buf);
7503         break;
7504         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7505         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7506                 rc = bnx2x_8727_read_sfp_module_eeprom(phy, params, addr,
7507                                                        byte_cnt, o_buf);
7508         break;
7509         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7510                 rc = bnx2x_warpcore_read_sfp_module_eeprom(phy, params, addr,
7511                                                            byte_cnt, o_buf);
7512         break;
7513         }
7514         return rc;
7515 }
7516
7517 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7518                               struct link_params *params,
7519                               u16 *edc_mode)
7520 {
7521         struct bnx2x *bp = params->bp;
7522         u32 sync_offset = 0, phy_idx, media_types;
7523         u8 val, check_limiting_mode = 0;
7524         *edc_mode = EDC_MODE_LIMITING;
7525
7526         phy->media_type = ETH_PHY_UNSPECIFIED;
7527         /* First check for copper cable */
7528         if (bnx2x_read_sfp_module_eeprom(phy,
7529                                          params,
7530                                          SFP_EEPROM_CON_TYPE_ADDR,
7531                                          1,
7532                                          &val) != 0) {
7533                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
7534                 return -EINVAL;
7535         }
7536
7537         switch (val) {
7538         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
7539         {
7540                 u8 copper_module_type;
7541                 phy->media_type = ETH_PHY_DA_TWINAX;
7542                 /*
7543                  * Check if its active cable (includes SFP+ module)
7544                  * of passive cable
7545                  */
7546                 if (bnx2x_read_sfp_module_eeprom(phy,
7547                                                params,
7548                                                SFP_EEPROM_FC_TX_TECH_ADDR,
7549                                                1,
7550                                                &copper_module_type) != 0) {
7551                         DP(NETIF_MSG_LINK,
7552                                 "Failed to read copper-cable-type"
7553                                 " from SFP+ EEPROM\n");
7554                         return -EINVAL;
7555                 }
7556
7557                 if (copper_module_type &
7558                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
7559                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
7560                         check_limiting_mode = 1;
7561                 } else if (copper_module_type &
7562                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
7563                                 DP(NETIF_MSG_LINK, "Passive Copper"
7564                                             " cable detected\n");
7565                                 *edc_mode =
7566                                       EDC_MODE_PASSIVE_DAC;
7567                 } else {
7568                         DP(NETIF_MSG_LINK, "Unknown copper-cable-"
7569                                      "type 0x%x !!!\n", copper_module_type);
7570                         return -EINVAL;
7571                 }
7572                 break;
7573         }
7574         case SFP_EEPROM_CON_TYPE_VAL_LC:
7575                 phy->media_type = ETH_PHY_SFP_FIBER;
7576                 DP(NETIF_MSG_LINK, "Optic module detected\n");
7577                 check_limiting_mode = 1;
7578                 break;
7579         default:
7580                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
7581                          val);
7582                 return -EINVAL;
7583         }
7584         sync_offset = params->shmem_base +
7585                 offsetof(struct shmem_region,
7586                          dev_info.port_hw_config[params->port].media_type);
7587         media_types = REG_RD(bp, sync_offset);
7588         /* Update media type for non-PMF sync */
7589         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
7590                 if (&(params->phy[phy_idx]) == phy) {
7591                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
7592                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7593                         media_types |= ((phy->media_type &
7594                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
7595                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
7596                         break;
7597                 }
7598         }
7599         REG_WR(bp, sync_offset, media_types);
7600         if (check_limiting_mode) {
7601                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
7602                 if (bnx2x_read_sfp_module_eeprom(phy,
7603                                                  params,
7604                                                  SFP_EEPROM_OPTIONS_ADDR,
7605                                                  SFP_EEPROM_OPTIONS_SIZE,
7606                                                  options) != 0) {
7607                         DP(NETIF_MSG_LINK, "Failed to read Option"
7608                                 " field from module EEPROM\n");
7609                         return -EINVAL;
7610                 }
7611                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
7612                         *edc_mode = EDC_MODE_LINEAR;
7613                 else
7614                         *edc_mode = EDC_MODE_LIMITING;
7615         }
7616         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7617         return 0;
7618 }
7619 /*
7620  * This function read the relevant field from the module (SFP+), and verify it
7621  * is compliant with this board
7622  */
7623 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
7624                                    struct link_params *params)
7625 {
7626         struct bnx2x *bp = params->bp;
7627         u32 val, cmd;
7628         u32 fw_resp, fw_cmd_param;
7629         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
7630         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
7631         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
7632         val = REG_RD(bp, params->shmem_base +
7633                          offsetof(struct shmem_region, dev_info.
7634                                   port_feature_config[params->port].config));
7635         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
7636             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
7637                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
7638                 return 0;
7639         }
7640
7641         if (params->feature_config_flags &
7642             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
7643                 /* Use specific phy request */
7644                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
7645         } else if (params->feature_config_flags &
7646                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
7647                 /* Use first phy request only in case of non-dual media*/
7648                 if (DUAL_MEDIA(params)) {
7649                         DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7650                            "verification\n");
7651                         return -EINVAL;
7652                 }
7653                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
7654         } else {
7655                 /* No support in OPT MDL detection */
7656                 DP(NETIF_MSG_LINK, "FW does not support OPT MDL "
7657                           "verification\n");
7658                 return -EINVAL;
7659         }
7660
7661         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
7662         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
7663         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
7664                 DP(NETIF_MSG_LINK, "Approved module\n");
7665                 return 0;
7666         }
7667
7668         /* format the warning message */
7669         if (bnx2x_read_sfp_module_eeprom(phy,
7670                                          params,
7671                                          SFP_EEPROM_VENDOR_NAME_ADDR,
7672                                          SFP_EEPROM_VENDOR_NAME_SIZE,
7673                                          (u8 *)vendor_name))
7674                 vendor_name[0] = '\0';
7675         else
7676                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
7677         if (bnx2x_read_sfp_module_eeprom(phy,
7678                                          params,
7679                                          SFP_EEPROM_PART_NO_ADDR,
7680                                          SFP_EEPROM_PART_NO_SIZE,
7681                                          (u8 *)vendor_pn))
7682                 vendor_pn[0] = '\0';
7683         else
7684                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
7685
7686         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
7687                               " Port %d from %s part number %s\n",
7688                          params->port, vendor_name, vendor_pn);
7689         phy->flags |= FLAGS_SFP_NOT_APPROVED;
7690         return -EINVAL;
7691 }
7692
7693 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
7694                                                  struct link_params *params)
7695
7696 {
7697         u8 val;
7698         struct bnx2x *bp = params->bp;
7699         u16 timeout;
7700         /*
7701          * Initialization time after hot-plug may take up to 300ms for
7702          * some phys type ( e.g. JDSU )
7703          */
7704
7705         for (timeout = 0; timeout < 60; timeout++) {
7706                 if (bnx2x_read_sfp_module_eeprom(phy, params, 1, 1, &val)
7707                     == 0) {
7708                         DP(NETIF_MSG_LINK, "SFP+ module initialization "
7709                                      "took %d ms\n", timeout * 5);
7710                         return 0;
7711                 }
7712                 msleep(5);
7713         }
7714         return -EINVAL;
7715 }
7716
7717 static void bnx2x_8727_power_module(struct bnx2x *bp,
7718                                     struct bnx2x_phy *phy,
7719                                     u8 is_power_up) {
7720         /* Make sure GPIOs are not using for LED mode */
7721         u16 val;
7722         /*
7723          * In the GPIO register, bit 4 is use to determine if the GPIOs are
7724          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
7725          * output
7726          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
7727          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
7728          * where the 1st bit is the over-current(only input), and 2nd bit is
7729          * for power( only output )
7730          *
7731          * In case of NOC feature is disabled and power is up, set GPIO control
7732          *  as input to enable listening of over-current indication
7733          */
7734         if (phy->flags & FLAGS_NOC)
7735                 return;
7736         if (is_power_up)
7737                 val = (1<<4);
7738         else
7739                 /*
7740                  * Set GPIO control to OUTPUT, and set the power bit
7741                  * to according to the is_power_up
7742                  */
7743                 val = (1<<1);
7744
7745         bnx2x_cl45_write(bp, phy,
7746                          MDIO_PMA_DEVAD,
7747                          MDIO_PMA_REG_8727_GPIO_CTRL,
7748                          val);
7749 }
7750
7751 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
7752                                         struct bnx2x_phy *phy,
7753                                         u16 edc_mode)
7754 {
7755         u16 cur_limiting_mode;
7756
7757         bnx2x_cl45_read(bp, phy,
7758                         MDIO_PMA_DEVAD,
7759                         MDIO_PMA_REG_ROM_VER2,
7760                         &cur_limiting_mode);
7761         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
7762                  cur_limiting_mode);
7763
7764         if (edc_mode == EDC_MODE_LIMITING) {
7765                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
7766                 bnx2x_cl45_write(bp, phy,
7767                                  MDIO_PMA_DEVAD,
7768                                  MDIO_PMA_REG_ROM_VER2,
7769                                  EDC_MODE_LIMITING);
7770         } else { /* LRM mode ( default )*/
7771
7772                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
7773
7774                 /*
7775                  * Changing to LRM mode takes quite few seconds. So do it only
7776                  * if current mode is limiting (default is LRM)
7777                  */
7778                 if (cur_limiting_mode != EDC_MODE_LIMITING)
7779                         return 0;
7780
7781                 bnx2x_cl45_write(bp, phy,
7782                                  MDIO_PMA_DEVAD,
7783                                  MDIO_PMA_REG_LRM_MODE,
7784                                  0);
7785                 bnx2x_cl45_write(bp, phy,
7786                                  MDIO_PMA_DEVAD,
7787                                  MDIO_PMA_REG_ROM_VER2,
7788                                  0x128);
7789                 bnx2x_cl45_write(bp, phy,
7790                                  MDIO_PMA_DEVAD,
7791                                  MDIO_PMA_REG_MISC_CTRL0,
7792                                  0x4008);
7793                 bnx2x_cl45_write(bp, phy,
7794                                  MDIO_PMA_DEVAD,
7795                                  MDIO_PMA_REG_LRM_MODE,
7796                                  0xaaaa);
7797         }
7798         return 0;
7799 }
7800
7801 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
7802                                         struct bnx2x_phy *phy,
7803                                         u16 edc_mode)
7804 {
7805         u16 phy_identifier;
7806         u16 rom_ver2_val;
7807         bnx2x_cl45_read(bp, phy,
7808                         MDIO_PMA_DEVAD,
7809                         MDIO_PMA_REG_PHY_IDENTIFIER,
7810                         &phy_identifier);
7811
7812         bnx2x_cl45_write(bp, phy,
7813                          MDIO_PMA_DEVAD,
7814                          MDIO_PMA_REG_PHY_IDENTIFIER,
7815                          (phy_identifier & ~(1<<9)));
7816
7817         bnx2x_cl45_read(bp, phy,
7818                         MDIO_PMA_DEVAD,
7819                         MDIO_PMA_REG_ROM_VER2,
7820                         &rom_ver2_val);
7821         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
7822         bnx2x_cl45_write(bp, phy,
7823                          MDIO_PMA_DEVAD,
7824                          MDIO_PMA_REG_ROM_VER2,
7825                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
7826
7827         bnx2x_cl45_write(bp, phy,
7828                          MDIO_PMA_DEVAD,
7829                          MDIO_PMA_REG_PHY_IDENTIFIER,
7830                          (phy_identifier | (1<<9)));
7831
7832         return 0;
7833 }
7834
7835 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
7836                                      struct link_params *params,
7837                                      u32 action)
7838 {
7839         struct bnx2x *bp = params->bp;
7840
7841         switch (action) {
7842         case DISABLE_TX:
7843                 bnx2x_sfp_set_transmitter(params, phy, 0);
7844                 break;
7845         case ENABLE_TX:
7846                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
7847                         bnx2x_sfp_set_transmitter(params, phy, 1);
7848                 break;
7849         default:
7850                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
7851                    action);
7852                 return;
7853         }
7854 }
7855
7856 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
7857                                            u8 gpio_mode)
7858 {
7859         struct bnx2x *bp = params->bp;
7860
7861         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
7862                             offsetof(struct shmem_region,
7863                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
7864                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
7865         switch (fault_led_gpio) {
7866         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
7867                 return;
7868         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
7869         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
7870         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
7871         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
7872         {
7873                 u8 gpio_port = bnx2x_get_gpio_port(params);
7874                 u16 gpio_pin = fault_led_gpio -
7875                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
7876                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
7877                                    "pin %x port %x mode %x\n",
7878                                gpio_pin, gpio_port, gpio_mode);
7879                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7880         }
7881         break;
7882         default:
7883                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
7884                                fault_led_gpio);
7885         }
7886 }
7887
7888 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
7889                                           u8 gpio_mode)
7890 {
7891         u32 pin_cfg;
7892         u8 port = params->port;
7893         struct bnx2x *bp = params->bp;
7894         pin_cfg = (REG_RD(bp, params->shmem_base +
7895                          offsetof(struct shmem_region,
7896                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
7897                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
7898                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
7899         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
7900                        gpio_mode, pin_cfg);
7901         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
7902 }
7903
7904 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
7905                                            u8 gpio_mode)
7906 {
7907         struct bnx2x *bp = params->bp;
7908         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
7909         if (CHIP_IS_E3(bp)) {
7910                 /*
7911                  * Low ==> if SFP+ module is supported otherwise
7912                  * High ==> if SFP+ module is not on the approved vendor list
7913                  */
7914                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
7915         } else
7916                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
7917 }
7918
7919 static void bnx2x_warpcore_power_module(struct link_params *params,
7920                                         struct bnx2x_phy *phy,
7921                                         u8 power)
7922 {
7923         u32 pin_cfg;
7924         struct bnx2x *bp = params->bp;
7925
7926         pin_cfg = (REG_RD(bp, params->shmem_base +
7927                           offsetof(struct shmem_region,
7928                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7929                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7930                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7931
7932         if (pin_cfg == PIN_CFG_NA)
7933                 return;
7934         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7935                        power, pin_cfg);
7936         /*
7937          * Low ==> corresponding SFP+ module is powered
7938          * high ==> the SFP+ module is powered down
7939          */
7940         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7941 }
7942
7943 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
7944                                     struct link_params *params)
7945 {
7946         bnx2x_warpcore_power_module(params, phy, 0);
7947 }
7948
7949 static void bnx2x_power_sfp_module(struct link_params *params,
7950                                    struct bnx2x_phy *phy,
7951                                    u8 power)
7952 {
7953         struct bnx2x *bp = params->bp;
7954         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
7955
7956         switch (phy->type) {
7957         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
7958         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
7959                 bnx2x_8727_power_module(params->bp, phy, power);
7960                 break;
7961         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
7962                 bnx2x_warpcore_power_module(params, phy, power);
7963                 break;
7964         default:
7965                 break;
7966         }
7967 }
7968 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
7969                                              struct bnx2x_phy *phy,
7970                                              u16 edc_mode)
7971 {
7972         u16 val = 0;
7973         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7974         struct bnx2x *bp = params->bp;
7975
7976         u8 lane = bnx2x_get_warpcore_lane(phy, params);
7977         /* This is a global register which controls all lanes */
7978         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7979                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
7980         val &= ~(0xf << (lane << 2));
7981
7982         switch (edc_mode) {
7983         case EDC_MODE_LINEAR:
7984         case EDC_MODE_LIMITING:
7985                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
7986                 break;
7987         case EDC_MODE_PASSIVE_DAC:
7988                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
7989                 break;
7990         default:
7991                 break;
7992         }
7993
7994         val |= (mode << (lane << 2));
7995         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
7996                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
7997         /* A must read */
7998         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
7999                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8000
8001
8002 }
8003
8004 static void bnx2x_set_limiting_mode(struct link_params *params,
8005                                     struct bnx2x_phy *phy,
8006                                     u16 edc_mode)
8007 {
8008         switch (phy->type) {
8009         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8010                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8011                 break;
8012         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8013         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8014                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8015                 break;
8016         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8017                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8018                 break;
8019         }
8020 }
8021
8022 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8023                                struct link_params *params)
8024 {
8025         struct bnx2x *bp = params->bp;
8026         u16 edc_mode;
8027         int rc = 0;
8028
8029         u32 val = REG_RD(bp, params->shmem_base +
8030                              offsetof(struct shmem_region, dev_info.
8031                                      port_feature_config[params->port].config));
8032
8033         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8034                  params->port);
8035         /* Power up module */
8036         bnx2x_power_sfp_module(params, phy, 1);
8037         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8038                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8039                 return -EINVAL;
8040         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8041                 /* check SFP+ module compatibility */
8042                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8043                 rc = -EINVAL;
8044                 /* Turn on fault module-detected led */
8045                 bnx2x_set_sfp_module_fault_led(params,
8046                                                MISC_REGISTERS_GPIO_HIGH);
8047
8048                 /* Check if need to power down the SFP+ module */
8049                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8050                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8051                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8052                         bnx2x_power_sfp_module(params, phy, 0);
8053                         return rc;
8054                 }
8055         } else {
8056                 /* Turn off fault module-detected led */
8057                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8058         }
8059
8060         /*
8061          * Check and set limiting mode / LRM mode on 8726. On 8727 it
8062          * is done automatically
8063          */
8064         bnx2x_set_limiting_mode(params, phy, edc_mode);
8065
8066         /*
8067          * Enable transmit for this module if the module is approved, or
8068          * if unapproved modules should also enable the Tx laser
8069          */
8070         if (rc == 0 ||
8071             (val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8072             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8073                 bnx2x_sfp_set_transmitter(params, phy, 1);
8074         else
8075                 bnx2x_sfp_set_transmitter(params, phy, 0);
8076
8077         return rc;
8078 }
8079
8080 void bnx2x_handle_module_detect_int(struct link_params *params)
8081 {
8082         struct bnx2x *bp = params->bp;
8083         struct bnx2x_phy *phy;
8084         u32 gpio_val;
8085         u8 gpio_num, gpio_port;
8086         if (CHIP_IS_E3(bp))
8087                 phy = &params->phy[INT_PHY];
8088         else
8089                 phy = &params->phy[EXT_PHY1];
8090
8091         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8092                                       params->port, &gpio_num, &gpio_port) ==
8093             -EINVAL) {
8094                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8095                 return;
8096         }
8097
8098         /* Set valid module led off */
8099         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8100
8101         /* Get current gpio val reflecting module plugged in / out*/
8102         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8103
8104         /* Call the handling function in case module is detected */
8105         if (gpio_val == 0) {
8106                 bnx2x_power_sfp_module(params, phy, 1);
8107                 bnx2x_set_gpio_int(bp, gpio_num,
8108                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8109                                    gpio_port);
8110                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8111                         bnx2x_sfp_module_detection(phy, params);
8112                 else
8113                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8114         } else {
8115                 u32 val = REG_RD(bp, params->shmem_base +
8116                                  offsetof(struct shmem_region, dev_info.
8117                                           port_feature_config[params->port].
8118                                           config));
8119
8120                 bnx2x_set_gpio_int(bp, gpio_num,
8121                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8122                                    gpio_port);
8123                 /*
8124                  * Module was plugged out.
8125                  * Disable transmit for this module
8126                  */
8127                 phy->media_type = ETH_PHY_NOT_PRESENT;
8128                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8129                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8130                         bnx2x_sfp_set_transmitter(params, phy, 0);
8131         }
8132 }
8133
8134 /******************************************************************/
8135 /*              Used by 8706 and 8727                             */
8136 /******************************************************************/
8137 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8138                                  struct bnx2x_phy *phy,
8139                                  u16 alarm_status_offset,
8140                                  u16 alarm_ctrl_offset)
8141 {
8142         u16 alarm_status, val;
8143         bnx2x_cl45_read(bp, phy,
8144                         MDIO_PMA_DEVAD, alarm_status_offset,
8145                         &alarm_status);
8146         bnx2x_cl45_read(bp, phy,
8147                         MDIO_PMA_DEVAD, alarm_status_offset,
8148                         &alarm_status);
8149         /* Mask or enable the fault event. */
8150         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8151         if (alarm_status & (1<<0))
8152                 val &= ~(1<<0);
8153         else
8154                 val |= (1<<0);
8155         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8156 }
8157 /******************************************************************/
8158 /*              common BCM8706/BCM8726 PHY SECTION                */
8159 /******************************************************************/
8160 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8161                                       struct link_params *params,
8162                                       struct link_vars *vars)
8163 {
8164         u8 link_up = 0;
8165         u16 val1, val2, rx_sd, pcs_status;
8166         struct bnx2x *bp = params->bp;
8167         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8168         /* Clear RX Alarm*/
8169         bnx2x_cl45_read(bp, phy,
8170                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8171
8172         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8173                              MDIO_PMA_LASI_TXCTRL);
8174
8175         /* clear LASI indication*/
8176         bnx2x_cl45_read(bp, phy,
8177                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8178         bnx2x_cl45_read(bp, phy,
8179                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8180         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8181
8182         bnx2x_cl45_read(bp, phy,
8183                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8184         bnx2x_cl45_read(bp, phy,
8185                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8186         bnx2x_cl45_read(bp, phy,
8187                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8188         bnx2x_cl45_read(bp, phy,
8189                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8190
8191         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8192                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8193         /*
8194          * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8195          * are set, or if the autoneg bit 1 is set
8196          */
8197         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8198         if (link_up) {
8199                 if (val2 & (1<<1))
8200                         vars->line_speed = SPEED_1000;
8201                 else
8202                         vars->line_speed = SPEED_10000;
8203                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8204                 vars->duplex = DUPLEX_FULL;
8205         }
8206
8207         /* Capture 10G link fault. Read twice to clear stale value. */
8208         if (vars->line_speed == SPEED_10000) {
8209                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8210                             MDIO_PMA_LASI_TXSTAT, &val1);
8211                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8212                             MDIO_PMA_LASI_TXSTAT, &val1);
8213                 if (val1 & (1<<0))
8214                         vars->fault_detected = 1;
8215         }
8216
8217         return link_up;
8218 }
8219
8220 /******************************************************************/
8221 /*                      BCM8706 PHY SECTION                       */
8222 /******************************************************************/
8223 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8224                                  struct link_params *params,
8225                                  struct link_vars *vars)
8226 {
8227         u32 tx_en_mode;
8228         u16 cnt, val, tmp1;
8229         struct bnx2x *bp = params->bp;
8230
8231         /* SPF+ PHY: Set flag to check for Tx error */
8232         vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8233
8234         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8235                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8236         /* HW reset */
8237         bnx2x_ext_phy_hw_reset(bp, params->port);
8238         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8239         bnx2x_wait_reset_complete(bp, phy, params);
8240
8241         /* Wait until fw is loaded */
8242         for (cnt = 0; cnt < 100; cnt++) {
8243                 bnx2x_cl45_read(bp, phy,
8244                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8245                 if (val)
8246                         break;
8247                 msleep(10);
8248         }
8249         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8250         if ((params->feature_config_flags &
8251              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8252                 u8 i;
8253                 u16 reg;
8254                 for (i = 0; i < 4; i++) {
8255                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8256                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8257                                    MDIO_XS_8706_REG_BANK_RX0);
8258                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8259                         /* Clear first 3 bits of the control */
8260                         val &= ~0x7;
8261                         /* Set control bits according to configuration */
8262                         val |= (phy->rx_preemphasis[i] & 0x7);
8263                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8264                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8265                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8266                 }
8267         }
8268         /* Force speed */
8269         if (phy->req_line_speed == SPEED_10000) {
8270                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8271
8272                 bnx2x_cl45_write(bp, phy,
8273                                  MDIO_PMA_DEVAD,
8274                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8275                 bnx2x_cl45_write(bp, phy,
8276                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8277                                  0);
8278                 /* Arm LASI for link and Tx fault. */
8279                 bnx2x_cl45_write(bp, phy,
8280                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8281         } else {
8282                 /* Force 1Gbps using autoneg with 1G advertisement */
8283
8284                 /* Allow CL37 through CL73 */
8285                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8286                 bnx2x_cl45_write(bp, phy,
8287                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8288
8289                 /* Enable Full-Duplex advertisement on CL37 */
8290                 bnx2x_cl45_write(bp, phy,
8291                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8292                 /* Enable CL37 AN */
8293                 bnx2x_cl45_write(bp, phy,
8294                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8295                 /* 1G support */
8296                 bnx2x_cl45_write(bp, phy,
8297                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8298
8299                 /* Enable clause 73 AN */
8300                 bnx2x_cl45_write(bp, phy,
8301                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8302                 bnx2x_cl45_write(bp, phy,
8303                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8304                                  0x0400);
8305                 bnx2x_cl45_write(bp, phy,
8306                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8307                                  0x0004);
8308         }
8309         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8310
8311         /*
8312          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8313          * power mode, if TX Laser is disabled
8314          */
8315
8316         tx_en_mode = REG_RD(bp, params->shmem_base +
8317                             offsetof(struct shmem_region,
8318                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8319                         & PORT_HW_CFG_TX_LASER_MASK;
8320
8321         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8322                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8323                 bnx2x_cl45_read(bp, phy,
8324                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8325                 tmp1 |= 0x1;
8326                 bnx2x_cl45_write(bp, phy,
8327                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8328         }
8329
8330         return 0;
8331 }
8332
8333 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8334                                   struct link_params *params,
8335                                   struct link_vars *vars)
8336 {
8337         return bnx2x_8706_8726_read_status(phy, params, vars);
8338 }
8339
8340 /******************************************************************/
8341 /*                      BCM8726 PHY SECTION                       */
8342 /******************************************************************/
8343 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8344                                        struct link_params *params)
8345 {
8346         struct bnx2x *bp = params->bp;
8347         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8348         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8349 }
8350
8351 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8352                                          struct link_params *params)
8353 {
8354         struct bnx2x *bp = params->bp;
8355         /* Need to wait 100ms after reset */
8356         msleep(100);
8357
8358         /* Micro controller re-boot */
8359         bnx2x_cl45_write(bp, phy,
8360                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8361
8362         /* Set soft reset */
8363         bnx2x_cl45_write(bp, phy,
8364                          MDIO_PMA_DEVAD,
8365                          MDIO_PMA_REG_GEN_CTRL,
8366                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8367
8368         bnx2x_cl45_write(bp, phy,
8369                          MDIO_PMA_DEVAD,
8370                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8371
8372         bnx2x_cl45_write(bp, phy,
8373                          MDIO_PMA_DEVAD,
8374                          MDIO_PMA_REG_GEN_CTRL,
8375                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8376
8377         /* wait for 150ms for microcode load */
8378         msleep(150);
8379
8380         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8381         bnx2x_cl45_write(bp, phy,
8382                          MDIO_PMA_DEVAD,
8383                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8384
8385         msleep(200);
8386         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8387 }
8388
8389 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
8390                                  struct link_params *params,
8391                                  struct link_vars *vars)
8392 {
8393         struct bnx2x *bp = params->bp;
8394         u16 val1;
8395         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
8396         if (link_up) {
8397                 bnx2x_cl45_read(bp, phy,
8398                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
8399                                 &val1);
8400                 if (val1 & (1<<15)) {
8401                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
8402                         link_up = 0;
8403                         vars->line_speed = 0;
8404                 }
8405         }
8406         return link_up;
8407 }
8408
8409
8410 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8411                                   struct link_params *params,
8412                                   struct link_vars *vars)
8413 {
8414         struct bnx2x *bp = params->bp;
8415         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
8416
8417         /* SPF+ PHY: Set flag to check for Tx error */
8418         vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8419
8420         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
8421         bnx2x_wait_reset_complete(bp, phy, params);
8422
8423         bnx2x_8726_external_rom_boot(phy, params);
8424
8425         /*
8426          * Need to call module detected on initialization since the module
8427          * detection triggered by actual module insertion might occur before
8428          * driver is loaded, and when driver is loaded, it reset all
8429          * registers, including the transmitter
8430          */
8431         bnx2x_sfp_module_detection(phy, params);
8432
8433         if (phy->req_line_speed == SPEED_1000) {
8434                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8435                 bnx2x_cl45_write(bp, phy,
8436                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8437                 bnx2x_cl45_write(bp, phy,
8438                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8439                 bnx2x_cl45_write(bp, phy,
8440                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
8441                 bnx2x_cl45_write(bp, phy,
8442                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8443                                  0x400);
8444         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8445                    (phy->speed_cap_mask &
8446                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
8447                    ((phy->speed_cap_mask &
8448                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8449                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8450                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8451                 /* Set Flow control */
8452                 bnx2x_ext_phy_set_pause(params, phy, vars);
8453                 bnx2x_cl45_write(bp, phy,
8454                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
8455                 bnx2x_cl45_write(bp, phy,
8456                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8457                 bnx2x_cl45_write(bp, phy,
8458                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
8459                 bnx2x_cl45_write(bp, phy,
8460                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8461                 bnx2x_cl45_write(bp, phy,
8462                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8463                 /*
8464                  * Enable RX-ALARM control to receive interrupt for 1G speed
8465                  * change
8466                  */
8467                 bnx2x_cl45_write(bp, phy,
8468                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
8469                 bnx2x_cl45_write(bp, phy,
8470                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8471                                  0x400);
8472
8473         } else { /* Default 10G. Set only LASI control */
8474                 bnx2x_cl45_write(bp, phy,
8475                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
8476         }
8477
8478         /* Set TX PreEmphasis if needed */
8479         if ((params->feature_config_flags &
8480              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8481                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x,"
8482                          "TX_CTRL2 0x%x\n",
8483                          phy->tx_preemphasis[0],
8484                          phy->tx_preemphasis[1]);
8485                 bnx2x_cl45_write(bp, phy,
8486                                  MDIO_PMA_DEVAD,
8487                                  MDIO_PMA_REG_8726_TX_CTRL1,
8488                                  phy->tx_preemphasis[0]);
8489
8490                 bnx2x_cl45_write(bp, phy,
8491                                  MDIO_PMA_DEVAD,
8492                                  MDIO_PMA_REG_8726_TX_CTRL2,
8493                                  phy->tx_preemphasis[1]);
8494         }
8495
8496         return 0;
8497
8498 }
8499
8500 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
8501                                   struct link_params *params)
8502 {
8503         struct bnx2x *bp = params->bp;
8504         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
8505         /* Set serial boot control for external load */
8506         bnx2x_cl45_write(bp, phy,
8507                          MDIO_PMA_DEVAD,
8508                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
8509 }
8510
8511 /******************************************************************/
8512 /*                      BCM8727 PHY SECTION                       */
8513 /******************************************************************/
8514
8515 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
8516                                     struct link_params *params, u8 mode)
8517 {
8518         struct bnx2x *bp = params->bp;
8519         u16 led_mode_bitmask = 0;
8520         u16 gpio_pins_bitmask = 0;
8521         u16 val;
8522         /* Only NOC flavor requires to set the LED specifically */
8523         if (!(phy->flags & FLAGS_NOC))
8524                 return;
8525         switch (mode) {
8526         case LED_MODE_FRONT_PANEL_OFF:
8527         case LED_MODE_OFF:
8528                 led_mode_bitmask = 0;
8529                 gpio_pins_bitmask = 0x03;
8530                 break;
8531         case LED_MODE_ON:
8532                 led_mode_bitmask = 0;
8533                 gpio_pins_bitmask = 0x02;
8534                 break;
8535         case LED_MODE_OPER:
8536                 led_mode_bitmask = 0x60;
8537                 gpio_pins_bitmask = 0x11;
8538                 break;
8539         }
8540         bnx2x_cl45_read(bp, phy,
8541                         MDIO_PMA_DEVAD,
8542                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8543                         &val);
8544         val &= 0xff8f;
8545         val |= led_mode_bitmask;
8546         bnx2x_cl45_write(bp, phy,
8547                          MDIO_PMA_DEVAD,
8548                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8549                          val);
8550         bnx2x_cl45_read(bp, phy,
8551                         MDIO_PMA_DEVAD,
8552                         MDIO_PMA_REG_8727_GPIO_CTRL,
8553                         &val);
8554         val &= 0xffe0;
8555         val |= gpio_pins_bitmask;
8556         bnx2x_cl45_write(bp, phy,
8557                          MDIO_PMA_DEVAD,
8558                          MDIO_PMA_REG_8727_GPIO_CTRL,
8559                          val);
8560 }
8561 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8562                                 struct link_params *params) {
8563         u32 swap_val, swap_override;
8564         u8 port;
8565         /*
8566          * The PHY reset is controlled by GPIO 1. Fake the port number
8567          * to cancel the swap done in set_gpio()
8568          */
8569         struct bnx2x *bp = params->bp;
8570         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8571         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8572         port = (swap_val && swap_override) ^ 1;
8573         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
8574                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
8575 }
8576
8577 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8578                                   struct link_params *params,
8579                                   struct link_vars *vars)
8580 {
8581         u32 tx_en_mode;
8582         u16 tmp1, val, mod_abs, tmp2;
8583         u16 rx_alarm_ctrl_val;
8584         u16 lasi_ctrl_val;
8585         struct bnx2x *bp = params->bp;
8586         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
8587
8588         /* SPF+ PHY: Set flag to check for Tx error */
8589         vars->phy_flags = PHY_TX_ERROR_CHECK_FLAG;
8590
8591         bnx2x_wait_reset_complete(bp, phy, params);
8592         rx_alarm_ctrl_val = (1<<2) | (1<<5) ;
8593         /* Should be 0x6 to enable XS on Tx side. */
8594         lasi_ctrl_val = 0x0006;
8595
8596         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
8597         /* enable LASI */
8598         bnx2x_cl45_write(bp, phy,
8599                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8600                          rx_alarm_ctrl_val);
8601         bnx2x_cl45_write(bp, phy,
8602                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8603                          0);
8604         bnx2x_cl45_write(bp, phy,
8605                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8606
8607         /*
8608          * Initially configure MOD_ABS to interrupt when module is
8609          * presence( bit 8)
8610          */
8611         bnx2x_cl45_read(bp, phy,
8612                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8613         /*
8614          * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8615          * When the EDC is off it locks onto a reference clock and avoids
8616          * becoming 'lost'
8617          */
8618         mod_abs &= ~(1<<8);
8619         if (!(phy->flags & FLAGS_NOC))
8620                 mod_abs &= ~(1<<9);
8621         bnx2x_cl45_write(bp, phy,
8622                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8623
8624
8625         /* Enable/Disable PHY transmitter output */
8626         bnx2x_set_disable_pmd_transmit(params, phy, 0);
8627
8628         /* Make MOD_ABS give interrupt on change */
8629         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8630                         &val);
8631         val |= (1<<12);
8632         if (phy->flags & FLAGS_NOC)
8633                 val |= (3<<5);
8634
8635         /*
8636          * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8637          * status which reflect SFP+ module over-current
8638          */
8639         if (!(phy->flags & FLAGS_NOC))
8640                 val &= 0xff8f; /* Reset bits 4-6 */
8641         bnx2x_cl45_write(bp, phy,
8642                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, val);
8643
8644         bnx2x_8727_power_module(bp, phy, 1);
8645
8646         bnx2x_cl45_read(bp, phy,
8647                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8648
8649         bnx2x_cl45_read(bp, phy,
8650                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8651
8652         /* Set option 1G speed */
8653         if (phy->req_line_speed == SPEED_1000) {
8654                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
8655                 bnx2x_cl45_write(bp, phy,
8656                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
8657                 bnx2x_cl45_write(bp, phy,
8658                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
8659                 bnx2x_cl45_read(bp, phy,
8660                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
8661                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
8662                 /*
8663                  * Power down the XAUI until link is up in case of dual-media
8664                  * and 1G
8665                  */
8666                 if (DUAL_MEDIA(params)) {
8667                         bnx2x_cl45_read(bp, phy,
8668                                         MDIO_PMA_DEVAD,
8669                                         MDIO_PMA_REG_8727_PCS_GP, &val);
8670                         val |= (3<<10);
8671                         bnx2x_cl45_write(bp, phy,
8672                                          MDIO_PMA_DEVAD,
8673                                          MDIO_PMA_REG_8727_PCS_GP, val);
8674                 }
8675         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
8676                    ((phy->speed_cap_mask &
8677                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
8678                    ((phy->speed_cap_mask &
8679                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
8680                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
8681
8682                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
8683                 bnx2x_cl45_write(bp, phy,
8684                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
8685                 bnx2x_cl45_write(bp, phy,
8686                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
8687         } else {
8688                 /*
8689                  * Since the 8727 has only single reset pin, need to set the 10G
8690                  * registers although it is default
8691                  */
8692                 bnx2x_cl45_write(bp, phy,
8693                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
8694                                  0x0020);
8695                 bnx2x_cl45_write(bp, phy,
8696                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
8697                 bnx2x_cl45_write(bp, phy,
8698                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8699                 bnx2x_cl45_write(bp, phy,
8700                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
8701                                  0x0008);
8702         }
8703
8704         /*
8705          * Set 2-wire transfer rate of SFP+ module EEPROM
8706          * to 100Khz since some DACs(direct attached cables) do
8707          * not work at 400Khz.
8708          */
8709         bnx2x_cl45_write(bp, phy,
8710                          MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8711                          0xa001);
8712
8713         /* Set TX PreEmphasis if needed */
8714         if ((params->feature_config_flags &
8715              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8716                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8717                            phy->tx_preemphasis[0],
8718                            phy->tx_preemphasis[1]);
8719                 bnx2x_cl45_write(bp, phy,
8720                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
8721                                  phy->tx_preemphasis[0]);
8722
8723                 bnx2x_cl45_write(bp, phy,
8724                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
8725                                  phy->tx_preemphasis[1]);
8726         }
8727
8728         /*
8729          * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8730          * power mode, if TX Laser is disabled
8731          */
8732         tx_en_mode = REG_RD(bp, params->shmem_base +
8733                             offsetof(struct shmem_region,
8734                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8735                         & PORT_HW_CFG_TX_LASER_MASK;
8736
8737         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8738
8739                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8740                 bnx2x_cl45_read(bp, phy,
8741                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
8742                 tmp2 |= 0x1000;
8743                 tmp2 &= 0xFFEF;
8744                 bnx2x_cl45_write(bp, phy,
8745                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
8746         }
8747
8748         return 0;
8749 }
8750
8751 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
8752                                       struct link_params *params)
8753 {
8754         struct bnx2x *bp = params->bp;
8755         u16 mod_abs, rx_alarm_status;
8756         u32 val = REG_RD(bp, params->shmem_base +
8757                              offsetof(struct shmem_region, dev_info.
8758                                       port_feature_config[params->port].
8759                                       config));
8760         bnx2x_cl45_read(bp, phy,
8761                         MDIO_PMA_DEVAD,
8762                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8763         if (mod_abs & (1<<8)) {
8764
8765                 /* Module is absent */
8766                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8767                             "show module is absent\n");
8768                 phy->media_type = ETH_PHY_NOT_PRESENT;
8769                 /*
8770                  * 1. Set mod_abs to detect next module
8771                  *    presence event
8772                  * 2. Set EDC off by setting OPTXLOS signal input to low
8773                  *    (bit 9).
8774                  *    When the EDC is off it locks onto a reference clock and
8775                  *    avoids becoming 'lost'.
8776                  */
8777                 mod_abs &= ~(1<<8);
8778                 if (!(phy->flags & FLAGS_NOC))
8779                         mod_abs &= ~(1<<9);
8780                 bnx2x_cl45_write(bp, phy,
8781                                  MDIO_PMA_DEVAD,
8782                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8783
8784                 /*
8785                  * Clear RX alarm since it stays up as long as
8786                  * the mod_abs wasn't changed
8787                  */
8788                 bnx2x_cl45_read(bp, phy,
8789                                 MDIO_PMA_DEVAD,
8790                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8791
8792         } else {
8793                 /* Module is present */
8794                 DP(NETIF_MSG_LINK, "MOD_ABS indication "
8795                             "show module is present\n");
8796                 /*
8797                  * First disable transmitter, and if the module is ok, the
8798                  * module_detection will enable it
8799                  * 1. Set mod_abs to detect next module absent event ( bit 8)
8800                  * 2. Restore the default polarity of the OPRXLOS signal and
8801                  * this signal will then correctly indicate the presence or
8802                  * absence of the Rx signal. (bit 9)
8803                  */
8804                 mod_abs |= (1<<8);
8805                 if (!(phy->flags & FLAGS_NOC))
8806                         mod_abs |= (1<<9);
8807                 bnx2x_cl45_write(bp, phy,
8808                                  MDIO_PMA_DEVAD,
8809                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
8810
8811                 /*
8812                  * Clear RX alarm since it stays up as long as the mod_abs
8813                  * wasn't changed. This is need to be done before calling the
8814                  * module detection, otherwise it will clear* the link update
8815                  * alarm
8816                  */
8817                 bnx2x_cl45_read(bp, phy,
8818                                 MDIO_PMA_DEVAD,
8819                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8820
8821
8822                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8823                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
8824                         bnx2x_sfp_set_transmitter(params, phy, 0);
8825
8826                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
8827                         bnx2x_sfp_module_detection(phy, params);
8828                 else
8829                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8830         }
8831
8832         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
8833                    rx_alarm_status);
8834         /* No need to check link status in case of module plugged in/out */
8835 }
8836
8837 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
8838                                  struct link_params *params,
8839                                  struct link_vars *vars)
8840
8841 {
8842         struct bnx2x *bp = params->bp;
8843         u8 link_up = 0, oc_port = params->port;
8844         u16 link_status = 0;
8845         u16 rx_alarm_status, lasi_ctrl, val1;
8846
8847         /* If PHY is not initialized, do not check link status */
8848         bnx2x_cl45_read(bp, phy,
8849                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8850                         &lasi_ctrl);
8851         if (!lasi_ctrl)
8852                 return 0;
8853
8854         /* Check the LASI on Rx */
8855         bnx2x_cl45_read(bp, phy,
8856                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
8857                         &rx_alarm_status);
8858         vars->line_speed = 0;
8859         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
8860
8861         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8862                              MDIO_PMA_LASI_TXCTRL);
8863
8864         bnx2x_cl45_read(bp, phy,
8865                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8866
8867         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
8868
8869         /* Clear MSG-OUT */
8870         bnx2x_cl45_read(bp, phy,
8871                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8872
8873         /*
8874          * If a module is present and there is need to check
8875          * for over current
8876          */
8877         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
8878                 /* Check over-current using 8727 GPIO0 input*/
8879                 bnx2x_cl45_read(bp, phy,
8880                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
8881                                 &val1);
8882
8883                 if ((val1 & (1<<8)) == 0) {
8884                         if (!CHIP_IS_E1x(bp))
8885                                 oc_port = BP_PATH(bp) + (params->port << 1);
8886                         DP(NETIF_MSG_LINK, "8727 Power fault has been detected"
8887                                        " on port %d\n", oc_port);
8888                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
8889                                             " been detected and the power to "
8890                                             "that SFP+ module has been removed"
8891                                             " to prevent failure of the card."
8892                                             " Please remove the SFP+ module and"
8893                                             " restart the system to clear this"
8894                                             " error.\n",
8895                          oc_port);
8896                         /* Disable all RX_ALARMs except for mod_abs */
8897                         bnx2x_cl45_write(bp, phy,
8898                                          MDIO_PMA_DEVAD,
8899                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
8900
8901                         bnx2x_cl45_read(bp, phy,
8902                                         MDIO_PMA_DEVAD,
8903                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8904                         /* Wait for module_absent_event */
8905                         val1 |= (1<<8);
8906                         bnx2x_cl45_write(bp, phy,
8907                                          MDIO_PMA_DEVAD,
8908                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
8909                         /* Clear RX alarm */
8910                         bnx2x_cl45_read(bp, phy,
8911                                 MDIO_PMA_DEVAD,
8912                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
8913                         return 0;
8914                 }
8915         } /* Over current check */
8916
8917         /* When module absent bit is set, check module */
8918         if (rx_alarm_status & (1<<5)) {
8919                 bnx2x_8727_handle_mod_abs(phy, params);
8920                 /* Enable all mod_abs and link detection bits */
8921                 bnx2x_cl45_write(bp, phy,
8922                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8923                                  ((1<<5) | (1<<2)));
8924         }
8925         DP(NETIF_MSG_LINK, "Enabling 8727 TX laser if SFP is approved\n");
8926         bnx2x_8727_specific_func(phy, params, ENABLE_TX);
8927         /* If transmitter is disabled, ignore false link up indication */
8928         bnx2x_cl45_read(bp, phy,
8929                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
8930         if (val1 & (1<<15)) {
8931                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
8932                 return 0;
8933         }
8934
8935         bnx2x_cl45_read(bp, phy,
8936                         MDIO_PMA_DEVAD,
8937                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
8938
8939         /*
8940          * Bits 0..2 --> speed detected,
8941          * Bits 13..15--> link is down
8942          */
8943         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8944                 link_up = 1;
8945                 vars->line_speed = SPEED_10000;
8946                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
8947                            params->port);
8948         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8949                 link_up = 1;
8950                 vars->line_speed = SPEED_1000;
8951                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
8952                            params->port);
8953         } else {
8954                 link_up = 0;
8955                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
8956                            params->port);
8957         }
8958
8959         /* Capture 10G link fault. */
8960         if (vars->line_speed == SPEED_10000) {
8961                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8962                             MDIO_PMA_LASI_TXSTAT, &val1);
8963
8964                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8965                             MDIO_PMA_LASI_TXSTAT, &val1);
8966
8967                 if (val1 & (1<<0)) {
8968                         vars->fault_detected = 1;
8969                 }
8970         }
8971
8972         if (link_up) {
8973                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8974                 vars->duplex = DUPLEX_FULL;
8975                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
8976         }
8977
8978         if ((DUAL_MEDIA(params)) &&
8979             (phy->req_line_speed == SPEED_1000)) {
8980                 bnx2x_cl45_read(bp, phy,
8981                                 MDIO_PMA_DEVAD,
8982                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
8983                 /*
8984                  * In case of dual-media board and 1G, power up the XAUI side,
8985                  * otherwise power it down. For 10G it is done automatically
8986                  */
8987                 if (link_up)
8988                         val1 &= ~(3<<10);
8989                 else
8990                         val1 |= (3<<10);
8991                 bnx2x_cl45_write(bp, phy,
8992                                  MDIO_PMA_DEVAD,
8993                                  MDIO_PMA_REG_8727_PCS_GP, val1);
8994         }
8995         return link_up;
8996 }
8997
8998 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
8999                                   struct link_params *params)
9000 {
9001         struct bnx2x *bp = params->bp;
9002
9003         /* Enable/Disable PHY transmitter output */
9004         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9005
9006         /* Disable Transmitter */
9007         bnx2x_sfp_set_transmitter(params, phy, 0);
9008         /* Clear LASI */
9009         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9010
9011 }
9012
9013 /******************************************************************/
9014 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9015 /******************************************************************/
9016 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9017                                            struct link_params *params)
9018 {
9019         u16 val, fw_ver1, fw_ver2, cnt;
9020         u8 port;
9021         struct bnx2x *bp = params->bp;
9022
9023         port = params->port;
9024
9025         /* For the 32 bits registers in 848xx, access via MDIO2ARM interface.*/
9026         /* (1) set register 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9027         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0014);
9028         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9029         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81B, 0x0000);
9030         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81C, 0x0300);
9031         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x0009);
9032
9033         for (cnt = 0; cnt < 100; cnt++) {
9034                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9035                 if (val & 1)
9036                         break;
9037                 udelay(5);
9038         }
9039         if (cnt == 100) {
9040                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(1)\n");
9041                 bnx2x_save_spirom_version(bp, port, 0,
9042                                           phy->ver_addr);
9043                 return;
9044         }
9045
9046
9047         /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9048         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9049         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9050         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9051         for (cnt = 0; cnt < 100; cnt++) {
9052                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9053                 if (val & 1)
9054                         break;
9055                 udelay(5);
9056         }
9057         if (cnt == 100) {
9058                 DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw version(2)\n");
9059                 bnx2x_save_spirom_version(bp, port, 0,
9060                                           phy->ver_addr);
9061                 return;
9062         }
9063
9064         /* lower 16 bits of the register SPI_FW_STATUS */
9065         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9066         /* upper 16 bits of register SPI_FW_STATUS */
9067         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9068
9069         bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9070                                   phy->ver_addr);
9071 }
9072
9073 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9074                                 struct bnx2x_phy *phy)
9075 {
9076         u16 val;
9077
9078         /* PHYC_CTL_LED_CTL */
9079         bnx2x_cl45_read(bp, phy,
9080                         MDIO_PMA_DEVAD,
9081                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9082         val &= 0xFE00;
9083         val |= 0x0092;
9084
9085         bnx2x_cl45_write(bp, phy,
9086                          MDIO_PMA_DEVAD,
9087                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9088
9089         bnx2x_cl45_write(bp, phy,
9090                          MDIO_PMA_DEVAD,
9091                          MDIO_PMA_REG_8481_LED1_MASK,
9092                          0x80);
9093
9094         bnx2x_cl45_write(bp, phy,
9095                          MDIO_PMA_DEVAD,
9096                          MDIO_PMA_REG_8481_LED2_MASK,
9097                          0x18);
9098
9099         /* Select activity source by Tx and Rx, as suggested by PHY AE */
9100         bnx2x_cl45_write(bp, phy,
9101                          MDIO_PMA_DEVAD,
9102                          MDIO_PMA_REG_8481_LED3_MASK,
9103                          0x0006);
9104
9105         /* Select the closest activity blink rate to that in 10/100/1000 */
9106         bnx2x_cl45_write(bp, phy,
9107                         MDIO_PMA_DEVAD,
9108                         MDIO_PMA_REG_8481_LED3_BLINK,
9109                         0);
9110
9111         bnx2x_cl45_read(bp, phy,
9112                         MDIO_PMA_DEVAD,
9113                         MDIO_PMA_REG_84823_CTL_LED_CTL_1, &val);
9114         val |= MDIO_PMA_REG_84823_LED3_STRETCH_EN; /* stretch_en for LED3*/
9115
9116         bnx2x_cl45_write(bp, phy,
9117                          MDIO_PMA_DEVAD,
9118                          MDIO_PMA_REG_84823_CTL_LED_CTL_1, val);
9119
9120         /* 'Interrupt Mask' */
9121         bnx2x_cl45_write(bp, phy,
9122                          MDIO_AN_DEVAD,
9123                          0xFFFB, 0xFFFD);
9124 }
9125
9126 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9127                                        struct link_params *params,
9128                                        struct link_vars *vars)
9129 {
9130         struct bnx2x *bp = params->bp;
9131         u16 autoneg_val, an_1000_val, an_10_100_val;
9132         u16 tmp_req_line_speed;
9133
9134         tmp_req_line_speed = phy->req_line_speed;
9135         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9136                 if (phy->req_line_speed == SPEED_10000)
9137                         phy->req_line_speed = SPEED_AUTO_NEG;
9138
9139         /*
9140          * This phy uses the NIG latch mechanism since link indication
9141          * arrives through its LED4 and not via its LASI signal, so we
9142          * get steady signal instead of clear on read
9143          */
9144         bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9145                       1 << NIG_LATCH_BC_ENABLE_MI_INT);
9146
9147         bnx2x_cl45_write(bp, phy,
9148                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9149
9150         bnx2x_848xx_set_led(bp, phy);
9151
9152         /* set 1000 speed advertisement */
9153         bnx2x_cl45_read(bp, phy,
9154                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9155                         &an_1000_val);
9156
9157         bnx2x_ext_phy_set_pause(params, phy, vars);
9158         bnx2x_cl45_read(bp, phy,
9159                         MDIO_AN_DEVAD,
9160                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9161                         &an_10_100_val);
9162         bnx2x_cl45_read(bp, phy,
9163                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9164                         &autoneg_val);
9165         /* Disable forced speed */
9166         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9167         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9168
9169         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9170              (phy->speed_cap_mask &
9171              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9172             (phy->req_line_speed == SPEED_1000)) {
9173                 an_1000_val |= (1<<8);
9174                 autoneg_val |= (1<<9 | 1<<12);
9175                 if (phy->req_duplex == DUPLEX_FULL)
9176                         an_1000_val |= (1<<9);
9177                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9178         } else
9179                 an_1000_val &= ~((1<<8) | (1<<9));
9180
9181         bnx2x_cl45_write(bp, phy,
9182                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9183                          an_1000_val);
9184
9185         /* set 100 speed advertisement */
9186         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9187              (phy->speed_cap_mask &
9188               (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
9189                PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) &&
9190              (phy->supported &
9191               (SUPPORTED_100baseT_Half |
9192                SUPPORTED_100baseT_Full)))) {
9193                 an_10_100_val |= (1<<7);
9194                 /* Enable autoneg and restart autoneg for legacy speeds */
9195                 autoneg_val |= (1<<9 | 1<<12);
9196
9197                 if (phy->req_duplex == DUPLEX_FULL)
9198                         an_10_100_val |= (1<<8);
9199                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
9200         }
9201         /* set 10 speed advertisement */
9202         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9203              (phy->speed_cap_mask &
9204               (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
9205                PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) &&
9206              (phy->supported &
9207               (SUPPORTED_10baseT_Half |
9208                SUPPORTED_10baseT_Full)))) {
9209                 an_10_100_val |= (1<<5);
9210                 autoneg_val |= (1<<9 | 1<<12);
9211                 if (phy->req_duplex == DUPLEX_FULL)
9212                         an_10_100_val |= (1<<6);
9213                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
9214         }
9215
9216         /* Only 10/100 are allowed to work in FORCE mode */
9217         if ((phy->req_line_speed == SPEED_100) &&
9218             (phy->supported &
9219              (SUPPORTED_100baseT_Half |
9220               SUPPORTED_100baseT_Full))) {
9221                 autoneg_val |= (1<<13);
9222                 /* Enabled AUTO-MDIX when autoneg is disabled */
9223                 bnx2x_cl45_write(bp, phy,
9224                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9225                                  (1<<15 | 1<<9 | 7<<0));
9226                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9227         }
9228         if ((phy->req_line_speed == SPEED_10) &&
9229             (phy->supported &
9230              (SUPPORTED_10baseT_Half |
9231               SUPPORTED_10baseT_Full))) {
9232                 /* Enabled AUTO-MDIX when autoneg is disabled */
9233                 bnx2x_cl45_write(bp, phy,
9234                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9235                                  (1<<15 | 1<<9 | 7<<0));
9236                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9237         }
9238
9239         bnx2x_cl45_write(bp, phy,
9240                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9241                          an_10_100_val);
9242
9243         if (phy->req_duplex == DUPLEX_FULL)
9244                 autoneg_val |= (1<<8);
9245
9246         bnx2x_cl45_write(bp, phy,
9247                          MDIO_AN_DEVAD,
9248                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9249
9250         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9251             (phy->speed_cap_mask &
9252              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9253                 (phy->req_line_speed == SPEED_10000)) {
9254                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9255                         /* Restart autoneg for 10G*/
9256
9257                         bnx2x_cl45_write(bp, phy,
9258                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9259                                  0x3200);
9260         } else if (phy->req_line_speed != SPEED_10 &&
9261                    phy->req_line_speed != SPEED_100) {
9262                 bnx2x_cl45_write(bp, phy,
9263                                  MDIO_AN_DEVAD,
9264                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9265                                  1);
9266         }
9267         /* Save spirom version */
9268         bnx2x_save_848xx_spirom_version(phy, params);
9269
9270         phy->req_line_speed = tmp_req_line_speed;
9271
9272         return 0;
9273 }
9274
9275 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9276                                   struct link_params *params,
9277                                   struct link_vars *vars)
9278 {
9279         struct bnx2x *bp = params->bp;
9280         /* Restore normal power mode*/
9281         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9282                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9283
9284         /* HW reset */
9285         bnx2x_ext_phy_hw_reset(bp, params->port);
9286         bnx2x_wait_reset_complete(bp, phy, params);
9287
9288         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9289         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9290 }
9291
9292
9293 #define PHY84833_HDSHK_WAIT 300
9294 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9295                                    struct link_params *params,
9296                                    struct link_vars *vars)
9297 {
9298         u32 idx;
9299         u32 pair_swap;
9300         u16 val;
9301         u16 data;
9302         struct bnx2x *bp = params->bp;
9303         /* Do pair swap */
9304
9305         /* Check for configuration. */
9306         pair_swap = REG_RD(bp, params->shmem_base +
9307                            offsetof(struct shmem_region,
9308                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9309                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9310
9311         if (pair_swap == 0)
9312                 return 0;
9313
9314         data = (u16)pair_swap;
9315
9316         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9317         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9318                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9319                         PHY84833_CMD_OPEN_OVERRIDE);
9320         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9321                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9322                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9323                 if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9324                         break;
9325                 msleep(1);
9326         }
9327         if (idx >= PHY84833_HDSHK_WAIT) {
9328                 DP(NETIF_MSG_LINK, "Pairswap: FW not ready.\n");
9329                 return -EINVAL;
9330         }
9331
9332         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9333                         MDIO_84833_TOP_CFG_SCRATCH_REG4,
9334                         data);
9335         /* Issue pair swap command */
9336         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9337                         MDIO_84833_TOP_CFG_SCRATCH_REG0,
9338                         PHY84833_DIAG_CMD_PAIR_SWAP_CHANGE);
9339         for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9340                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9341                                 MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9342                 if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9343                         (val == PHY84833_CMD_COMPLETE_ERROR))
9344                         break;
9345                 msleep(1);
9346         }
9347         if ((idx >= PHY84833_HDSHK_WAIT) ||
9348                 (val == PHY84833_CMD_COMPLETE_ERROR)) {
9349                 DP(NETIF_MSG_LINK, "Pairswap: override failed.\n");
9350                 return -EINVAL;
9351         }
9352         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9353                         MDIO_84833_TOP_CFG_SCRATCH_REG2,
9354                         PHY84833_CMD_CLEAR_COMPLETE);
9355         DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data);
9356         return 0;
9357 }
9358
9359
9360 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9361                                       u32 shmem_base_path[],
9362                                       u32 chip_id)
9363 {
9364         u32 reset_pin[2];
9365         u32 idx;
9366         u8 reset_gpios;
9367         if (CHIP_IS_E3(bp)) {
9368                 /* Assume that these will be GPIOs, not EPIOs. */
9369                 for (idx = 0; idx < 2; idx++) {
9370                         /* Map config param to register bit. */
9371                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9372                                 offsetof(struct shmem_region,
9373                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9374                         reset_pin[idx] = (reset_pin[idx] &
9375                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9376                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9377                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9378                         reset_pin[idx] = (1 << reset_pin[idx]);
9379                 }
9380                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9381         } else {
9382                 /* E2, look from diff place of shmem. */
9383                 for (idx = 0; idx < 2; idx++) {
9384                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9385                                 offsetof(struct shmem_region,
9386                                 dev_info.port_hw_config[0].default_cfg));
9387                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
9388                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
9389                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
9390                         reset_pin[idx] = (1 << reset_pin[idx]);
9391                 }
9392                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9393         }
9394
9395         return reset_gpios;
9396 }
9397
9398 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
9399                                 struct link_params *params)
9400 {
9401         struct bnx2x *bp = params->bp;
9402         u8 reset_gpios;
9403         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
9404                                 offsetof(struct shmem2_region,
9405                                 other_shmem_base_addr));
9406
9407         u32 shmem_base_path[2];
9408         shmem_base_path[0] = params->shmem_base;
9409         shmem_base_path[1] = other_shmem_base_addr;
9410
9411         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
9412                                                   params->chip_id);
9413
9414         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9415         udelay(10);
9416         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
9417                 reset_gpios);
9418
9419         return 0;
9420 }
9421
9422 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
9423                                                 u32 shmem_base_path[],
9424                                                 u32 chip_id)
9425 {
9426         u8 reset_gpios;
9427
9428         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
9429
9430         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
9431         udelay(10);
9432         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
9433         msleep(800);
9434         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
9435                 reset_gpios);
9436
9437         return 0;
9438 }
9439
9440 #define PHY84833_CONSTANT_LATENCY 1193
9441 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9442                                    struct link_params *params,
9443                                    struct link_vars *vars)
9444 {
9445         struct bnx2x *bp = params->bp;
9446         u8 port, initialize = 1;
9447         u16 val;
9448         u16 temp;
9449         u32 actual_phy_selection, cms_enable, idx;
9450         int rc = 0;
9451
9452         msleep(1);
9453
9454         if (!(CHIP_IS_E1(bp)))
9455                 port = BP_PATH(bp);
9456         else
9457                 port = params->port;
9458
9459         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9460                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9461                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
9462                                port);
9463         } else {
9464                 /* MDIO reset */
9465                 bnx2x_cl45_write(bp, phy,
9466                                 MDIO_PMA_DEVAD,
9467                                 MDIO_PMA_REG_CTRL, 0x8000);
9468                 /* Bring PHY out of super isolate mode */
9469                 bnx2x_cl45_read(bp, phy,
9470                                 MDIO_CTL_DEVAD,
9471                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val);
9472                 val &= ~MDIO_84833_SUPER_ISOLATE;
9473                 bnx2x_cl45_write(bp, phy,
9474                                 MDIO_CTL_DEVAD,
9475                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val);
9476         }
9477
9478         bnx2x_wait_reset_complete(bp, phy, params);
9479
9480         /* Wait for GPHY to come out of reset */
9481         msleep(50);
9482
9483         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9484                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
9485
9486         /*
9487          * BCM84823 requires that XGXS links up first @ 10G for normal behavior
9488          */
9489         temp = vars->line_speed;
9490         vars->line_speed = SPEED_10000;
9491         bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
9492         bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
9493         vars->line_speed = temp;
9494
9495         /* Set dual-media configuration according to configuration */
9496
9497         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9498                         MDIO_CTL_REG_84823_MEDIA, &val);
9499         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9500                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
9501                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
9502                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
9503                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
9504
9505         if (CHIP_IS_E3(bp)) {
9506                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
9507                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
9508         } else {
9509                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
9510                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
9511         }
9512
9513         actual_phy_selection = bnx2x_phy_selection(params);
9514
9515         switch (actual_phy_selection) {
9516         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
9517                 /* Do nothing. Essentially this is like the priority copper */
9518                 break;
9519         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
9520                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
9521                 break;
9522         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
9523                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
9524                 break;
9525         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
9526                 /* Do nothing here. The first PHY won't be initialized at all */
9527                 break;
9528         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
9529                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
9530                 initialize = 0;
9531                 break;
9532         }
9533         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
9534                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
9535
9536         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9537                          MDIO_CTL_REG_84823_MEDIA, val);
9538         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
9539                    params->multi_phy_config, val);
9540
9541         /* AutogrEEEn */
9542         if (params->feature_config_flags &
9543                 FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
9544                 /* Ensure that f/w is ready */
9545                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9546                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9547                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9548                         if (val == PHY84833_CMD_OPEN_FOR_CMDS)
9549                                 break;
9550                         usleep_range(1000, 1000);
9551                 }
9552                 if (idx >= PHY84833_HDSHK_WAIT) {
9553                         DP(NETIF_MSG_LINK, "AutogrEEEn: FW not ready.\n");
9554                         return -EINVAL;
9555                 }
9556
9557                 /* Select EEE mode */
9558                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9559                                 MDIO_84833_TOP_CFG_SCRATCH_REG3,
9560                                 0x2);
9561
9562                 /* Set Idle and Latency */
9563                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9564                                 MDIO_84833_TOP_CFG_SCRATCH_REG4,
9565                                 PHY84833_CONSTANT_LATENCY + 1);
9566
9567                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9568                                 MDIO_84833_TOP_CFG_DATA3_REG,
9569                                 PHY84833_CONSTANT_LATENCY + 1);
9570
9571                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9572                                 MDIO_84833_TOP_CFG_DATA4_REG,
9573                                 PHY84833_CONSTANT_LATENCY);
9574
9575                 /* Send EEE instruction to command register */
9576                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9577                                 MDIO_84833_TOP_CFG_SCRATCH_REG0,
9578                                 PHY84833_DIAG_CMD_SET_EEE_MODE);
9579
9580                 /* Ensure that the command has completed */
9581                 for (idx = 0; idx < PHY84833_HDSHK_WAIT; idx++) {
9582                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9583                                         MDIO_84833_TOP_CFG_SCRATCH_REG2, &val);
9584                         if ((val == PHY84833_CMD_COMPLETE_PASS) ||
9585                                 (val == PHY84833_CMD_COMPLETE_ERROR))
9586                                 break;
9587                         usleep_range(1000, 1000);
9588                 }
9589                 if ((idx >= PHY84833_HDSHK_WAIT) ||
9590                         (val == PHY84833_CMD_COMPLETE_ERROR)) {
9591                         DP(NETIF_MSG_LINK, "AutogrEEEn: command failed.\n");
9592                         return -EINVAL;
9593                 }
9594
9595                 /* Reset command handler */
9596                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9597                             MDIO_84833_TOP_CFG_SCRATCH_REG2,
9598                             PHY84833_CMD_CLEAR_COMPLETE);
9599         }
9600
9601         if (initialize)
9602                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
9603         else
9604                 bnx2x_save_848xx_spirom_version(phy, params);
9605         /* 84833 PHY has a better feature and doesn't need to support this. */
9606         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9607                 cms_enable = REG_RD(bp, params->shmem_base +
9608                         offsetof(struct shmem_region,
9609                         dev_info.port_hw_config[params->port].default_cfg)) &
9610                         PORT_HW_CFG_ENABLE_CMS_MASK;
9611
9612                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9613                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
9614                 if (cms_enable)
9615                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
9616                 else
9617                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
9618                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9619                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
9620         }
9621
9622         return rc;
9623 }
9624
9625 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
9626                                   struct link_params *params,
9627                                   struct link_vars *vars)
9628 {
9629         struct bnx2x *bp = params->bp;
9630         u16 val, val1, val2;
9631         u8 link_up = 0;
9632
9633
9634         /* Check 10G-BaseT link status */
9635         /* Check PMD signal ok */
9636         bnx2x_cl45_read(bp, phy,
9637                         MDIO_AN_DEVAD, 0xFFFA, &val1);
9638         bnx2x_cl45_read(bp, phy,
9639                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
9640                         &val2);
9641         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
9642
9643         /* Check link 10G */
9644         if (val2 & (1<<11)) {
9645                 vars->line_speed = SPEED_10000;
9646                 vars->duplex = DUPLEX_FULL;
9647                 link_up = 1;
9648                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
9649         } else { /* Check Legacy speed link */
9650                 u16 legacy_status, legacy_speed;
9651
9652                 /* Enable expansion register 0x42 (Operation mode status) */
9653                 bnx2x_cl45_write(bp, phy,
9654                                  MDIO_AN_DEVAD,
9655                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
9656
9657                 /* Get legacy speed operation status */
9658                 bnx2x_cl45_read(bp, phy,
9659                                 MDIO_AN_DEVAD,
9660                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
9661                                 &legacy_status);
9662
9663                 DP(NETIF_MSG_LINK, "Legacy speed status"
9664                              " = 0x%x\n", legacy_status);
9665                 link_up = ((legacy_status & (1<<11)) == (1<<11));
9666                 if (link_up) {
9667                         legacy_speed = (legacy_status & (3<<9));
9668                         if (legacy_speed == (0<<9))
9669                                 vars->line_speed = SPEED_10;
9670                         else if (legacy_speed == (1<<9))
9671                                 vars->line_speed = SPEED_100;
9672                         else if (legacy_speed == (2<<9))
9673                                 vars->line_speed = SPEED_1000;
9674                         else /* Should not happen */
9675                                 vars->line_speed = 0;
9676
9677                         if (legacy_status & (1<<8))
9678                                 vars->duplex = DUPLEX_FULL;
9679                         else
9680                                 vars->duplex = DUPLEX_HALF;
9681
9682                         DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
9683                                    " is_duplex_full= %d\n", vars->line_speed,
9684                                    (vars->duplex == DUPLEX_FULL));
9685                         /* Check legacy speed AN resolution */
9686                         bnx2x_cl45_read(bp, phy,
9687                                         MDIO_AN_DEVAD,
9688                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
9689                                         &val);
9690                         if (val & (1<<5))
9691                                 vars->link_status |=
9692                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
9693                         bnx2x_cl45_read(bp, phy,
9694                                         MDIO_AN_DEVAD,
9695                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
9696                                         &val);
9697                         if ((val & (1<<0)) == 0)
9698                                 vars->link_status |=
9699                                         LINK_STATUS_PARALLEL_DETECTION_USED;
9700                 }
9701         }
9702         if (link_up) {
9703                 DP(NETIF_MSG_LINK, "BCM84823: link speed is %d\n",
9704                            vars->line_speed);
9705                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9706         }
9707
9708         return link_up;
9709 }
9710
9711
9712 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
9713 {
9714         int status = 0;
9715         u32 spirom_ver;
9716         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
9717         status = bnx2x_format_ver(spirom_ver, str, len);
9718         return status;
9719 }
9720
9721 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
9722                                 struct link_params *params)
9723 {
9724         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9725                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
9726         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
9727                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
9728 }
9729
9730 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
9731                                         struct link_params *params)
9732 {
9733         bnx2x_cl45_write(params->bp, phy,
9734                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
9735         bnx2x_cl45_write(params->bp, phy,
9736                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
9737 }
9738
9739 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
9740                                    struct link_params *params)
9741 {
9742         struct bnx2x *bp = params->bp;
9743         u8 port;
9744         u16 val16;
9745
9746         if (!(CHIP_IS_E1(bp)))
9747                 port = BP_PATH(bp);
9748         else
9749                 port = params->port;
9750
9751         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
9752                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
9753                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
9754                                port);
9755         } else {
9756                 bnx2x_cl45_read(bp, phy,
9757                                 MDIO_CTL_DEVAD,
9758                                 0x400f, &val16);
9759                 /* Put to low power mode on newer FW */
9760                 if ((val16 & 0x303f) > 0x1009)
9761                         bnx2x_cl45_write(bp, phy,
9762                                         MDIO_PMA_DEVAD,
9763                                         MDIO_PMA_REG_CTRL, 0x800);
9764         }
9765 }
9766
9767 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
9768                                      struct link_params *params, u8 mode)
9769 {
9770         struct bnx2x *bp = params->bp;
9771         u16 val;
9772         u8 port;
9773
9774         if (!(CHIP_IS_E1(bp)))
9775                 port = BP_PATH(bp);
9776         else
9777                 port = params->port;
9778
9779         switch (mode) {
9780         case LED_MODE_OFF:
9781
9782                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
9783
9784                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9785                     SHARED_HW_CFG_LED_EXTPHY1) {
9786
9787                         /* Set LED masks */
9788                         bnx2x_cl45_write(bp, phy,
9789                                         MDIO_PMA_DEVAD,
9790                                         MDIO_PMA_REG_8481_LED1_MASK,
9791                                         0x0);
9792
9793                         bnx2x_cl45_write(bp, phy,
9794                                         MDIO_PMA_DEVAD,
9795                                         MDIO_PMA_REG_8481_LED2_MASK,
9796                                         0x0);
9797
9798                         bnx2x_cl45_write(bp, phy,
9799                                         MDIO_PMA_DEVAD,
9800                                         MDIO_PMA_REG_8481_LED3_MASK,
9801                                         0x0);
9802
9803                         bnx2x_cl45_write(bp, phy,
9804                                         MDIO_PMA_DEVAD,
9805                                         MDIO_PMA_REG_8481_LED5_MASK,
9806                                         0x0);
9807
9808                 } else {
9809                         bnx2x_cl45_write(bp, phy,
9810                                          MDIO_PMA_DEVAD,
9811                                          MDIO_PMA_REG_8481_LED1_MASK,
9812                                          0x0);
9813                 }
9814                 break;
9815         case LED_MODE_FRONT_PANEL_OFF:
9816
9817                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
9818                    port);
9819
9820                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9821                     SHARED_HW_CFG_LED_EXTPHY1) {
9822
9823                         /* Set LED masks */
9824                         bnx2x_cl45_write(bp, phy,
9825                                          MDIO_PMA_DEVAD,
9826                                          MDIO_PMA_REG_8481_LED1_MASK,
9827                                          0x0);
9828
9829                         bnx2x_cl45_write(bp, phy,
9830                                          MDIO_PMA_DEVAD,
9831                                          MDIO_PMA_REG_8481_LED2_MASK,
9832                                          0x0);
9833
9834                         bnx2x_cl45_write(bp, phy,
9835                                          MDIO_PMA_DEVAD,
9836                                          MDIO_PMA_REG_8481_LED3_MASK,
9837                                          0x0);
9838
9839                         bnx2x_cl45_write(bp, phy,
9840                                          MDIO_PMA_DEVAD,
9841                                          MDIO_PMA_REG_8481_LED5_MASK,
9842                                          0x20);
9843
9844                 } else {
9845                         bnx2x_cl45_write(bp, phy,
9846                                          MDIO_PMA_DEVAD,
9847                                          MDIO_PMA_REG_8481_LED1_MASK,
9848                                          0x0);
9849                 }
9850                 break;
9851         case LED_MODE_ON:
9852
9853                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
9854
9855                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9856                     SHARED_HW_CFG_LED_EXTPHY1) {
9857                         /* Set control reg */
9858                         bnx2x_cl45_read(bp, phy,
9859                                         MDIO_PMA_DEVAD,
9860                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9861                                         &val);
9862                         val &= 0x8000;
9863                         val |= 0x2492;
9864
9865                         bnx2x_cl45_write(bp, phy,
9866                                          MDIO_PMA_DEVAD,
9867                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9868                                          val);
9869
9870                         /* Set LED masks */
9871                         bnx2x_cl45_write(bp, phy,
9872                                          MDIO_PMA_DEVAD,
9873                                          MDIO_PMA_REG_8481_LED1_MASK,
9874                                          0x0);
9875
9876                         bnx2x_cl45_write(bp, phy,
9877                                          MDIO_PMA_DEVAD,
9878                                          MDIO_PMA_REG_8481_LED2_MASK,
9879                                          0x20);
9880
9881                         bnx2x_cl45_write(bp, phy,
9882                                          MDIO_PMA_DEVAD,
9883                                          MDIO_PMA_REG_8481_LED3_MASK,
9884                                          0x20);
9885
9886                         bnx2x_cl45_write(bp, phy,
9887                                          MDIO_PMA_DEVAD,
9888                                          MDIO_PMA_REG_8481_LED5_MASK,
9889                                          0x0);
9890                 } else {
9891                         bnx2x_cl45_write(bp, phy,
9892                                          MDIO_PMA_DEVAD,
9893                                          MDIO_PMA_REG_8481_LED1_MASK,
9894                                          0x20);
9895                 }
9896                 break;
9897
9898         case LED_MODE_OPER:
9899
9900                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
9901
9902                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
9903                     SHARED_HW_CFG_LED_EXTPHY1) {
9904
9905                         /* Set control reg */
9906                         bnx2x_cl45_read(bp, phy,
9907                                         MDIO_PMA_DEVAD,
9908                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9909                                         &val);
9910
9911                         if (!((val &
9912                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
9913                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
9914                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
9915                                 bnx2x_cl45_write(bp, phy,
9916                                                  MDIO_PMA_DEVAD,
9917                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
9918                                                  0xa492);
9919                         }
9920
9921                         /* Set LED masks */
9922                         bnx2x_cl45_write(bp, phy,
9923                                          MDIO_PMA_DEVAD,
9924                                          MDIO_PMA_REG_8481_LED1_MASK,
9925                                          0x10);
9926
9927                         bnx2x_cl45_write(bp, phy,
9928                                          MDIO_PMA_DEVAD,
9929                                          MDIO_PMA_REG_8481_LED2_MASK,
9930                                          0x80);
9931
9932                         bnx2x_cl45_write(bp, phy,
9933                                          MDIO_PMA_DEVAD,
9934                                          MDIO_PMA_REG_8481_LED3_MASK,
9935                                          0x98);
9936
9937                         bnx2x_cl45_write(bp, phy,
9938                                          MDIO_PMA_DEVAD,
9939                                          MDIO_PMA_REG_8481_LED5_MASK,
9940                                          0x40);
9941
9942                 } else {
9943                         bnx2x_cl45_write(bp, phy,
9944                                          MDIO_PMA_DEVAD,
9945                                          MDIO_PMA_REG_8481_LED1_MASK,
9946                                          0x80);
9947
9948                         /* Tell LED3 to blink on source */
9949                         bnx2x_cl45_read(bp, phy,
9950                                         MDIO_PMA_DEVAD,
9951                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
9952                                         &val);
9953                         val &= ~(7<<6);
9954                         val |= (1<<6); /* A83B[8:6]= 1 */
9955                         bnx2x_cl45_write(bp, phy,
9956                                          MDIO_PMA_DEVAD,
9957                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
9958                                          val);
9959                 }
9960                 break;
9961         }
9962
9963         /*
9964          * This is a workaround for E3+84833 until autoneg
9965          * restart is fixed in f/w
9966          */
9967         if (CHIP_IS_E3(bp)) {
9968                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
9969                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
9970         }
9971 }
9972
9973 /******************************************************************/
9974 /*                      54618SE PHY SECTION                       */
9975 /******************************************************************/
9976 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
9977                                                struct link_params *params,
9978                                                struct link_vars *vars)
9979 {
9980         struct bnx2x *bp = params->bp;
9981         u8 port;
9982         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
9983         u32 cfg_pin;
9984
9985         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
9986         usleep_range(1000, 1000);
9987
9988         /* This works with E3 only, no need to check the chip
9989            before determining the port. */
9990         port = params->port;
9991
9992         cfg_pin = (REG_RD(bp, params->shmem_base +
9993                         offsetof(struct shmem_region,
9994                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
9995                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9996                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9997
9998         /* Drive pin high to bring the GPHY out of reset. */
9999         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10000
10001         /* wait for GPHY to reset */
10002         msleep(50);
10003
10004         /* reset phy */
10005         bnx2x_cl22_write(bp, phy,
10006                          MDIO_PMA_REG_CTRL, 0x8000);
10007         bnx2x_wait_reset_complete(bp, phy, params);
10008
10009         /*wait for GPHY to reset */
10010         msleep(50);
10011
10012         /* Configure LED4: set to INTR (0x6). */
10013         /* Accessing shadow register 0xe. */
10014         bnx2x_cl22_write(bp, phy,
10015                         MDIO_REG_GPHY_SHADOW,
10016                         MDIO_REG_GPHY_SHADOW_LED_SEL2);
10017         bnx2x_cl22_read(bp, phy,
10018                         MDIO_REG_GPHY_SHADOW,
10019                         &temp);
10020         temp &= ~(0xf << 4);
10021         temp |= (0x6 << 4);
10022         bnx2x_cl22_write(bp, phy,
10023                         MDIO_REG_GPHY_SHADOW,
10024                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10025         /* Configure INTR based on link status change. */
10026         bnx2x_cl22_write(bp, phy,
10027                         MDIO_REG_INTR_MASK,
10028                         ~MDIO_REG_INTR_MASK_LINK_STATUS);
10029
10030         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10031         bnx2x_cl22_write(bp, phy,
10032                         MDIO_REG_GPHY_SHADOW,
10033                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10034         bnx2x_cl22_read(bp, phy,
10035                         MDIO_REG_GPHY_SHADOW,
10036                         &temp);
10037         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10038         bnx2x_cl22_write(bp, phy,
10039                         MDIO_REG_GPHY_SHADOW,
10040                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10041
10042         /* Set up fc */
10043         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10044         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10045         fc_val = 0;
10046         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10047                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10048                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10049
10050         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10051                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10052                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10053
10054         /* read all advertisement */
10055         bnx2x_cl22_read(bp, phy,
10056                         0x09,
10057                         &an_1000_val);
10058
10059         bnx2x_cl22_read(bp, phy,
10060                         0x04,
10061                         &an_10_100_val);
10062
10063         bnx2x_cl22_read(bp, phy,
10064                         MDIO_PMA_REG_CTRL,
10065                         &autoneg_val);
10066
10067         /* Disable forced speed */
10068         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10069         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10070                            (1<<11));
10071
10072         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10073                         (phy->speed_cap_mask &
10074                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10075                         (phy->req_line_speed == SPEED_1000)) {
10076                 an_1000_val |= (1<<8);
10077                 autoneg_val |= (1<<9 | 1<<12);
10078                 if (phy->req_duplex == DUPLEX_FULL)
10079                         an_1000_val |= (1<<9);
10080                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10081         } else
10082                 an_1000_val &= ~((1<<8) | (1<<9));
10083
10084         bnx2x_cl22_write(bp, phy,
10085                         0x09,
10086                         an_1000_val);
10087         bnx2x_cl22_read(bp, phy,
10088                         0x09,
10089                         &an_1000_val);
10090
10091         /* set 100 speed advertisement */
10092         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10093                         (phy->speed_cap_mask &
10094                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10095                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10096                 an_10_100_val |= (1<<7);
10097                 /* Enable autoneg and restart autoneg for legacy speeds */
10098                 autoneg_val |= (1<<9 | 1<<12);
10099
10100                 if (phy->req_duplex == DUPLEX_FULL)
10101                         an_10_100_val |= (1<<8);
10102                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10103         }
10104
10105         /* set 10 speed advertisement */
10106         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10107                         (phy->speed_cap_mask &
10108                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10109                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10110                 an_10_100_val |= (1<<5);
10111                 autoneg_val |= (1<<9 | 1<<12);
10112                 if (phy->req_duplex == DUPLEX_FULL)
10113                         an_10_100_val |= (1<<6);
10114                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10115         }
10116
10117         /* Only 10/100 are allowed to work in FORCE mode */
10118         if (phy->req_line_speed == SPEED_100) {
10119                 autoneg_val |= (1<<13);
10120                 /* Enabled AUTO-MDIX when autoneg is disabled */
10121                 bnx2x_cl22_write(bp, phy,
10122                                 0x18,
10123                                 (1<<15 | 1<<9 | 7<<0));
10124                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10125         }
10126         if (phy->req_line_speed == SPEED_10) {
10127                 /* Enabled AUTO-MDIX when autoneg is disabled */
10128                 bnx2x_cl22_write(bp, phy,
10129                                 0x18,
10130                                 (1<<15 | 1<<9 | 7<<0));
10131                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10132         }
10133
10134         /* Check if we should turn on Auto-GrEEEn */
10135         bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &temp);
10136         if (temp == MDIO_REG_GPHY_ID_54618SE) {
10137                 if (params->feature_config_flags &
10138                     FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10139                         temp = 6;
10140                         DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10141                 } else {
10142                         temp = 0;
10143                         DP(NETIF_MSG_LINK, "Disabling Auto-GrEEEn\n");
10144                 }
10145                 bnx2x_cl22_write(bp, phy,
10146                                  MDIO_REG_GPHY_CL45_ADDR_REG, MDIO_AN_DEVAD);
10147                 bnx2x_cl22_write(bp, phy,
10148                                  MDIO_REG_GPHY_CL45_DATA_REG,
10149                                  MDIO_REG_GPHY_EEE_ADV);
10150                 bnx2x_cl22_write(bp, phy,
10151                                  MDIO_REG_GPHY_CL45_ADDR_REG,
10152                                  (0x1 << 14) | MDIO_AN_DEVAD);
10153                 bnx2x_cl22_write(bp, phy,
10154                                  MDIO_REG_GPHY_CL45_DATA_REG,
10155                                  temp);
10156         }
10157
10158         bnx2x_cl22_write(bp, phy,
10159                         0x04,
10160                         an_10_100_val | fc_val);
10161
10162         if (phy->req_duplex == DUPLEX_FULL)
10163                 autoneg_val |= (1<<8);
10164
10165         bnx2x_cl22_write(bp, phy,
10166                         MDIO_PMA_REG_CTRL, autoneg_val);
10167
10168         return 0;
10169 }
10170
10171 static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10172                                        struct link_params *params, u8 mode)
10173 {
10174         struct bnx2x *bp = params->bp;
10175         DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10176         switch (mode) {
10177         case LED_MODE_FRONT_PANEL_OFF:
10178         case LED_MODE_OFF:
10179         case LED_MODE_OPER:
10180         case LED_MODE_ON:
10181         default:
10182                 break;
10183         }
10184         return;
10185 }
10186
10187 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10188                                      struct link_params *params)
10189 {
10190         struct bnx2x *bp = params->bp;
10191         u32 cfg_pin;
10192         u8 port;
10193
10194         /* This works with E3 only, no need to check the chip
10195            before determining the port. */
10196         port = params->port;
10197         cfg_pin = (REG_RD(bp, params->shmem_base +
10198                         offsetof(struct shmem_region,
10199                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10200                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10201                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10202
10203         /* Drive pin low to put GPHY in reset. */
10204         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10205 }
10206
10207 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10208                                     struct link_params *params,
10209                                     struct link_vars *vars)
10210 {
10211         struct bnx2x *bp = params->bp;
10212         u16 val;
10213         u8 link_up = 0;
10214         u16 legacy_status, legacy_speed;
10215
10216         /* Get speed operation status */
10217         bnx2x_cl22_read(bp, phy,
10218                         0x19,
10219                         &legacy_status);
10220         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
10221
10222         /* Read status to clear the PHY interrupt. */
10223         bnx2x_cl22_read(bp, phy,
10224                         MDIO_REG_INTR_STATUS,
10225                         &val);
10226
10227         link_up = ((legacy_status & (1<<2)) == (1<<2));
10228
10229         if (link_up) {
10230                 legacy_speed = (legacy_status & (7<<8));
10231                 if (legacy_speed == (7<<8)) {
10232                         vars->line_speed = SPEED_1000;
10233                         vars->duplex = DUPLEX_FULL;
10234                 } else if (legacy_speed == (6<<8)) {
10235                         vars->line_speed = SPEED_1000;
10236                         vars->duplex = DUPLEX_HALF;
10237                 } else if (legacy_speed == (5<<8)) {
10238                         vars->line_speed = SPEED_100;
10239                         vars->duplex = DUPLEX_FULL;
10240                 }
10241                 /* Omitting 100Base-T4 for now */
10242                 else if (legacy_speed == (3<<8)) {
10243                         vars->line_speed = SPEED_100;
10244                         vars->duplex = DUPLEX_HALF;
10245                 } else if (legacy_speed == (2<<8)) {
10246                         vars->line_speed = SPEED_10;
10247                         vars->duplex = DUPLEX_FULL;
10248                 } else if (legacy_speed == (1<<8)) {
10249                         vars->line_speed = SPEED_10;
10250                         vars->duplex = DUPLEX_HALF;
10251                 } else /* Should not happen */
10252                         vars->line_speed = 0;
10253
10254                 DP(NETIF_MSG_LINK, "Link is up in %dMbps,"
10255                            " is_duplex_full= %d\n", vars->line_speed,
10256                            (vars->duplex == DUPLEX_FULL));
10257
10258                 /* Check legacy speed AN resolution */
10259                 bnx2x_cl22_read(bp, phy,
10260                                 0x01,
10261                                 &val);
10262                 if (val & (1<<5))
10263                         vars->link_status |=
10264                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10265                 bnx2x_cl22_read(bp, phy,
10266                                 0x06,
10267                                 &val);
10268                 if ((val & (1<<0)) == 0)
10269                         vars->link_status |=
10270                                 LINK_STATUS_PARALLEL_DETECTION_USED;
10271
10272                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
10273                            vars->line_speed);
10274
10275                 /* Report whether EEE is resolved. */
10276                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_PHYID_LSB, &val);
10277                 if (val == MDIO_REG_GPHY_ID_54618SE) {
10278                         if (vars->link_status &
10279                             LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
10280                                 val = 0;
10281                         else {
10282                                 bnx2x_cl22_write(bp, phy,
10283                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10284                                         MDIO_AN_DEVAD);
10285                                 bnx2x_cl22_write(bp, phy,
10286                                         MDIO_REG_GPHY_CL45_DATA_REG,
10287                                         MDIO_REG_GPHY_EEE_RESOLVED);
10288                                 bnx2x_cl22_write(bp, phy,
10289                                         MDIO_REG_GPHY_CL45_ADDR_REG,
10290                                         (0x1 << 14) | MDIO_AN_DEVAD);
10291                                 bnx2x_cl22_read(bp, phy,
10292                                         MDIO_REG_GPHY_CL45_DATA_REG,
10293                                         &val);
10294                         }
10295                         DP(NETIF_MSG_LINK, "EEE resolution: 0x%x\n", val);
10296                 }
10297
10298                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10299         }
10300         return link_up;
10301 }
10302
10303 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10304                                           struct link_params *params)
10305 {
10306         struct bnx2x *bp = params->bp;
10307         u16 val;
10308         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10309
10310         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
10311
10312         /* Enable master/slave manual mmode and set to master */
10313         /* mii write 9 [bits set 11 12] */
10314         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
10315
10316         /* forced 1G and disable autoneg */
10317         /* set val [mii read 0] */
10318         /* set val [expr $val & [bits clear 6 12 13]] */
10319         /* set val [expr $val | [bits set 6 8]] */
10320         /* mii write 0 $val */
10321         bnx2x_cl22_read(bp, phy, 0x00, &val);
10322         val &= ~((1<<6) | (1<<12) | (1<<13));
10323         val |= (1<<6) | (1<<8);
10324         bnx2x_cl22_write(bp, phy, 0x00, val);
10325
10326         /* Set external loopback and Tx using 6dB coding */
10327         /* mii write 0x18 7 */
10328         /* set val [mii read 0x18] */
10329         /* mii write 0x18 [expr $val | [bits set 10 15]] */
10330         bnx2x_cl22_write(bp, phy, 0x18, 7);
10331         bnx2x_cl22_read(bp, phy, 0x18, &val);
10332         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
10333
10334         /* This register opens the gate for the UMAC despite its name */
10335         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10336
10337         /*
10338          * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10339          * length used by the MAC receive logic to check frames.
10340          */
10341         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
10342 }
10343
10344 /******************************************************************/
10345 /*                      SFX7101 PHY SECTION                       */
10346 /******************************************************************/
10347 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
10348                                        struct link_params *params)
10349 {
10350         struct bnx2x *bp = params->bp;
10351         /* SFX7101_XGXS_TEST1 */
10352         bnx2x_cl45_write(bp, phy,
10353                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
10354 }
10355
10356 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
10357                                   struct link_params *params,
10358                                   struct link_vars *vars)
10359 {
10360         u16 fw_ver1, fw_ver2, val;
10361         struct bnx2x *bp = params->bp;
10362         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
10363
10364         /* Restore normal power mode*/
10365         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10366                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10367         /* HW reset */
10368         bnx2x_ext_phy_hw_reset(bp, params->port);
10369         bnx2x_wait_reset_complete(bp, phy, params);
10370
10371         bnx2x_cl45_write(bp, phy,
10372                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
10373         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
10374         bnx2x_cl45_write(bp, phy,
10375                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
10376
10377         bnx2x_ext_phy_set_pause(params, phy, vars);
10378         /* Restart autoneg */
10379         bnx2x_cl45_read(bp, phy,
10380                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
10381         val |= 0x200;
10382         bnx2x_cl45_write(bp, phy,
10383                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
10384
10385         /* Save spirom version */
10386         bnx2x_cl45_read(bp, phy,
10387                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
10388
10389         bnx2x_cl45_read(bp, phy,
10390                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
10391         bnx2x_save_spirom_version(bp, params->port,
10392                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
10393         return 0;
10394 }
10395
10396 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
10397                                  struct link_params *params,
10398                                  struct link_vars *vars)
10399 {
10400         struct bnx2x *bp = params->bp;
10401         u8 link_up;
10402         u16 val1, val2;
10403         bnx2x_cl45_read(bp, phy,
10404                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
10405         bnx2x_cl45_read(bp, phy,
10406                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10407         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
10408                    val2, val1);
10409         bnx2x_cl45_read(bp, phy,
10410                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
10411         bnx2x_cl45_read(bp, phy,
10412                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
10413         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
10414                    val2, val1);
10415         link_up = ((val1 & 4) == 4);
10416         /* if link is up print the AN outcome of the SFX7101 PHY */
10417         if (link_up) {
10418                 bnx2x_cl45_read(bp, phy,
10419                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
10420                                 &val2);
10421                 vars->line_speed = SPEED_10000;
10422                 vars->duplex = DUPLEX_FULL;
10423                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
10424                            val2, (val2 & (1<<14)));
10425                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10426                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10427         }
10428         return link_up;
10429 }
10430
10431 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
10432 {
10433         if (*len < 5)
10434                 return -EINVAL;
10435         str[0] = (spirom_ver & 0xFF);
10436         str[1] = (spirom_ver & 0xFF00) >> 8;
10437         str[2] = (spirom_ver & 0xFF0000) >> 16;
10438         str[3] = (spirom_ver & 0xFF000000) >> 24;
10439         str[4] = '\0';
10440         *len -= 5;
10441         return 0;
10442 }
10443
10444 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
10445 {
10446         u16 val, cnt;
10447
10448         bnx2x_cl45_read(bp, phy,
10449                         MDIO_PMA_DEVAD,
10450                         MDIO_PMA_REG_7101_RESET, &val);
10451
10452         for (cnt = 0; cnt < 10; cnt++) {
10453                 msleep(50);
10454                 /* Writes a self-clearing reset */
10455                 bnx2x_cl45_write(bp, phy,
10456                                  MDIO_PMA_DEVAD,
10457                                  MDIO_PMA_REG_7101_RESET,
10458                                  (val | (1<<15)));
10459                 /* Wait for clear */
10460                 bnx2x_cl45_read(bp, phy,
10461                                 MDIO_PMA_DEVAD,
10462                                 MDIO_PMA_REG_7101_RESET, &val);
10463
10464                 if ((val & (1<<15)) == 0)
10465                         break;
10466         }
10467 }
10468
10469 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
10470                                 struct link_params *params) {
10471         /* Low power mode is controlled by GPIO 2 */
10472         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
10473                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10474         /* The PHY reset is controlled by GPIO 1 */
10475         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10476                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
10477 }
10478
10479 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
10480                                     struct link_params *params, u8 mode)
10481 {
10482         u16 val = 0;
10483         struct bnx2x *bp = params->bp;
10484         switch (mode) {
10485         case LED_MODE_FRONT_PANEL_OFF:
10486         case LED_MODE_OFF:
10487                 val = 2;
10488                 break;
10489         case LED_MODE_ON:
10490                 val = 1;
10491                 break;
10492         case LED_MODE_OPER:
10493                 val = 0;
10494                 break;
10495         }
10496         bnx2x_cl45_write(bp, phy,
10497                          MDIO_PMA_DEVAD,
10498                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
10499                          val);
10500 }
10501
10502 /******************************************************************/
10503 /*                      STATIC PHY DECLARATION                    */
10504 /******************************************************************/
10505
10506 static struct bnx2x_phy phy_null = {
10507         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
10508         .addr           = 0,
10509         .def_md_devad   = 0,
10510         .flags          = FLAGS_INIT_XGXS_FIRST,
10511         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10512         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10513         .mdio_ctrl      = 0,
10514         .supported      = 0,
10515         .media_type     = ETH_PHY_NOT_PRESENT,
10516         .ver_addr       = 0,
10517         .req_flow_ctrl  = 0,
10518         .req_line_speed = 0,
10519         .speed_cap_mask = 0,
10520         .req_duplex     = 0,
10521         .rsrv           = 0,
10522         .config_init    = (config_init_t)NULL,
10523         .read_status    = (read_status_t)NULL,
10524         .link_reset     = (link_reset_t)NULL,
10525         .config_loopback = (config_loopback_t)NULL,
10526         .format_fw_ver  = (format_fw_ver_t)NULL,
10527         .hw_reset       = (hw_reset_t)NULL,
10528         .set_link_led   = (set_link_led_t)NULL,
10529         .phy_specific_func = (phy_specific_func_t)NULL
10530 };
10531
10532 static struct bnx2x_phy phy_serdes = {
10533         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
10534         .addr           = 0xff,
10535         .def_md_devad   = 0,
10536         .flags          = 0,
10537         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10538         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10539         .mdio_ctrl      = 0,
10540         .supported      = (SUPPORTED_10baseT_Half |
10541                            SUPPORTED_10baseT_Full |
10542                            SUPPORTED_100baseT_Half |
10543                            SUPPORTED_100baseT_Full |
10544                            SUPPORTED_1000baseT_Full |
10545                            SUPPORTED_2500baseX_Full |
10546                            SUPPORTED_TP |
10547                            SUPPORTED_Autoneg |
10548                            SUPPORTED_Pause |
10549                            SUPPORTED_Asym_Pause),
10550         .media_type     = ETH_PHY_BASE_T,
10551         .ver_addr       = 0,
10552         .req_flow_ctrl  = 0,
10553         .req_line_speed = 0,
10554         .speed_cap_mask = 0,
10555         .req_duplex     = 0,
10556         .rsrv           = 0,
10557         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10558         .read_status    = (read_status_t)bnx2x_link_settings_status,
10559         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10560         .config_loopback = (config_loopback_t)NULL,
10561         .format_fw_ver  = (format_fw_ver_t)NULL,
10562         .hw_reset       = (hw_reset_t)NULL,
10563         .set_link_led   = (set_link_led_t)NULL,
10564         .phy_specific_func = (phy_specific_func_t)NULL
10565 };
10566
10567 static struct bnx2x_phy phy_xgxs = {
10568         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10569         .addr           = 0xff,
10570         .def_md_devad   = 0,
10571         .flags          = 0,
10572         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10573         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10574         .mdio_ctrl      = 0,
10575         .supported      = (SUPPORTED_10baseT_Half |
10576                            SUPPORTED_10baseT_Full |
10577                            SUPPORTED_100baseT_Half |
10578                            SUPPORTED_100baseT_Full |
10579                            SUPPORTED_1000baseT_Full |
10580                            SUPPORTED_2500baseX_Full |
10581                            SUPPORTED_10000baseT_Full |
10582                            SUPPORTED_FIBRE |
10583                            SUPPORTED_Autoneg |
10584                            SUPPORTED_Pause |
10585                            SUPPORTED_Asym_Pause),
10586         .media_type     = ETH_PHY_CX4,
10587         .ver_addr       = 0,
10588         .req_flow_ctrl  = 0,
10589         .req_line_speed = 0,
10590         .speed_cap_mask = 0,
10591         .req_duplex     = 0,
10592         .rsrv           = 0,
10593         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
10594         .read_status    = (read_status_t)bnx2x_link_settings_status,
10595         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
10596         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
10597         .format_fw_ver  = (format_fw_ver_t)NULL,
10598         .hw_reset       = (hw_reset_t)NULL,
10599         .set_link_led   = (set_link_led_t)NULL,
10600         .phy_specific_func = (phy_specific_func_t)NULL
10601 };
10602 static struct bnx2x_phy phy_warpcore = {
10603         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
10604         .addr           = 0xff,
10605         .def_md_devad   = 0,
10606         .flags          = FLAGS_HW_LOCK_REQUIRED,
10607         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10608         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10609         .mdio_ctrl      = 0,
10610         .supported      = (SUPPORTED_10baseT_Half |
10611                              SUPPORTED_10baseT_Full |
10612                              SUPPORTED_100baseT_Half |
10613                              SUPPORTED_100baseT_Full |
10614                              SUPPORTED_1000baseT_Full |
10615                              SUPPORTED_10000baseT_Full |
10616                              SUPPORTED_20000baseKR2_Full |
10617                              SUPPORTED_20000baseMLD2_Full |
10618                              SUPPORTED_FIBRE |
10619                              SUPPORTED_Autoneg |
10620                              SUPPORTED_Pause |
10621                              SUPPORTED_Asym_Pause),
10622         .media_type     = ETH_PHY_UNSPECIFIED,
10623         .ver_addr       = 0,
10624         .req_flow_ctrl  = 0,
10625         .req_line_speed = 0,
10626         .speed_cap_mask = 0,
10627         /* req_duplex = */0,
10628         /* rsrv = */0,
10629         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
10630         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
10631         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
10632         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
10633         .format_fw_ver  = (format_fw_ver_t)NULL,
10634         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
10635         .set_link_led   = (set_link_led_t)NULL,
10636         .phy_specific_func = (phy_specific_func_t)NULL
10637 };
10638
10639
10640 static struct bnx2x_phy phy_7101 = {
10641         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
10642         .addr           = 0xff,
10643         .def_md_devad   = 0,
10644         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10645         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10646         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10647         .mdio_ctrl      = 0,
10648         .supported      = (SUPPORTED_10000baseT_Full |
10649                            SUPPORTED_TP |
10650                            SUPPORTED_Autoneg |
10651                            SUPPORTED_Pause |
10652                            SUPPORTED_Asym_Pause),
10653         .media_type     = ETH_PHY_BASE_T,
10654         .ver_addr       = 0,
10655         .req_flow_ctrl  = 0,
10656         .req_line_speed = 0,
10657         .speed_cap_mask = 0,
10658         .req_duplex     = 0,
10659         .rsrv           = 0,
10660         .config_init    = (config_init_t)bnx2x_7101_config_init,
10661         .read_status    = (read_status_t)bnx2x_7101_read_status,
10662         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10663         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
10664         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
10665         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
10666         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
10667         .phy_specific_func = (phy_specific_func_t)NULL
10668 };
10669 static struct bnx2x_phy phy_8073 = {
10670         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
10671         .addr           = 0xff,
10672         .def_md_devad   = 0,
10673         .flags          = FLAGS_HW_LOCK_REQUIRED,
10674         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10675         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10676         .mdio_ctrl      = 0,
10677         .supported      = (SUPPORTED_10000baseT_Full |
10678                            SUPPORTED_2500baseX_Full |
10679                            SUPPORTED_1000baseT_Full |
10680                            SUPPORTED_FIBRE |
10681                            SUPPORTED_Autoneg |
10682                            SUPPORTED_Pause |
10683                            SUPPORTED_Asym_Pause),
10684         .media_type     = ETH_PHY_KR,
10685         .ver_addr       = 0,
10686         .req_flow_ctrl  = 0,
10687         .req_line_speed = 0,
10688         .speed_cap_mask = 0,
10689         .req_duplex     = 0,
10690         .rsrv           = 0,
10691         .config_init    = (config_init_t)bnx2x_8073_config_init,
10692         .read_status    = (read_status_t)bnx2x_8073_read_status,
10693         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
10694         .config_loopback = (config_loopback_t)NULL,
10695         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10696         .hw_reset       = (hw_reset_t)NULL,
10697         .set_link_led   = (set_link_led_t)NULL,
10698         .phy_specific_func = (phy_specific_func_t)NULL
10699 };
10700 static struct bnx2x_phy phy_8705 = {
10701         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
10702         .addr           = 0xff,
10703         .def_md_devad   = 0,
10704         .flags          = FLAGS_INIT_XGXS_FIRST,
10705         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10706         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10707         .mdio_ctrl      = 0,
10708         .supported      = (SUPPORTED_10000baseT_Full |
10709                            SUPPORTED_FIBRE |
10710                            SUPPORTED_Pause |
10711                            SUPPORTED_Asym_Pause),
10712         .media_type     = ETH_PHY_XFP_FIBER,
10713         .ver_addr       = 0,
10714         .req_flow_ctrl  = 0,
10715         .req_line_speed = 0,
10716         .speed_cap_mask = 0,
10717         .req_duplex     = 0,
10718         .rsrv           = 0,
10719         .config_init    = (config_init_t)bnx2x_8705_config_init,
10720         .read_status    = (read_status_t)bnx2x_8705_read_status,
10721         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10722         .config_loopback = (config_loopback_t)NULL,
10723         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
10724         .hw_reset       = (hw_reset_t)NULL,
10725         .set_link_led   = (set_link_led_t)NULL,
10726         .phy_specific_func = (phy_specific_func_t)NULL
10727 };
10728 static struct bnx2x_phy phy_8706 = {
10729         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
10730         .addr           = 0xff,
10731         .def_md_devad   = 0,
10732         .flags          = FLAGS_INIT_XGXS_FIRST,
10733         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10734         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10735         .mdio_ctrl      = 0,
10736         .supported      = (SUPPORTED_10000baseT_Full |
10737                            SUPPORTED_1000baseT_Full |
10738                            SUPPORTED_FIBRE |
10739                            SUPPORTED_Pause |
10740                            SUPPORTED_Asym_Pause),
10741         .media_type     = ETH_PHY_SFP_FIBER,
10742         .ver_addr       = 0,
10743         .req_flow_ctrl  = 0,
10744         .req_line_speed = 0,
10745         .speed_cap_mask = 0,
10746         .req_duplex     = 0,
10747         .rsrv           = 0,
10748         .config_init    = (config_init_t)bnx2x_8706_config_init,
10749         .read_status    = (read_status_t)bnx2x_8706_read_status,
10750         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
10751         .config_loopback = (config_loopback_t)NULL,
10752         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10753         .hw_reset       = (hw_reset_t)NULL,
10754         .set_link_led   = (set_link_led_t)NULL,
10755         .phy_specific_func = (phy_specific_func_t)NULL
10756 };
10757
10758 static struct bnx2x_phy phy_8726 = {
10759         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
10760         .addr           = 0xff,
10761         .def_md_devad   = 0,
10762         .flags          = (FLAGS_HW_LOCK_REQUIRED |
10763                            FLAGS_INIT_XGXS_FIRST),
10764         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10765         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10766         .mdio_ctrl      = 0,
10767         .supported      = (SUPPORTED_10000baseT_Full |
10768                            SUPPORTED_1000baseT_Full |
10769                            SUPPORTED_Autoneg |
10770                            SUPPORTED_FIBRE |
10771                            SUPPORTED_Pause |
10772                            SUPPORTED_Asym_Pause),
10773         .media_type     = ETH_PHY_NOT_PRESENT,
10774         .ver_addr       = 0,
10775         .req_flow_ctrl  = 0,
10776         .req_line_speed = 0,
10777         .speed_cap_mask = 0,
10778         .req_duplex     = 0,
10779         .rsrv           = 0,
10780         .config_init    = (config_init_t)bnx2x_8726_config_init,
10781         .read_status    = (read_status_t)bnx2x_8726_read_status,
10782         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
10783         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
10784         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10785         .hw_reset       = (hw_reset_t)NULL,
10786         .set_link_led   = (set_link_led_t)NULL,
10787         .phy_specific_func = (phy_specific_func_t)NULL
10788 };
10789
10790 static struct bnx2x_phy phy_8727 = {
10791         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
10792         .addr           = 0xff,
10793         .def_md_devad   = 0,
10794         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
10795         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10796         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10797         .mdio_ctrl      = 0,
10798         .supported      = (SUPPORTED_10000baseT_Full |
10799                            SUPPORTED_1000baseT_Full |
10800                            SUPPORTED_FIBRE |
10801                            SUPPORTED_Pause |
10802                            SUPPORTED_Asym_Pause),
10803         .media_type     = ETH_PHY_NOT_PRESENT,
10804         .ver_addr       = 0,
10805         .req_flow_ctrl  = 0,
10806         .req_line_speed = 0,
10807         .speed_cap_mask = 0,
10808         .req_duplex     = 0,
10809         .rsrv           = 0,
10810         .config_init    = (config_init_t)bnx2x_8727_config_init,
10811         .read_status    = (read_status_t)bnx2x_8727_read_status,
10812         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
10813         .config_loopback = (config_loopback_t)NULL,
10814         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
10815         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
10816         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
10817         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
10818 };
10819 static struct bnx2x_phy phy_8481 = {
10820         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
10821         .addr           = 0xff,
10822         .def_md_devad   = 0,
10823         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10824                           FLAGS_REARM_LATCH_SIGNAL,
10825         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10826         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10827         .mdio_ctrl      = 0,
10828         .supported      = (SUPPORTED_10baseT_Half |
10829                            SUPPORTED_10baseT_Full |
10830                            SUPPORTED_100baseT_Half |
10831                            SUPPORTED_100baseT_Full |
10832                            SUPPORTED_1000baseT_Full |
10833                            SUPPORTED_10000baseT_Full |
10834                            SUPPORTED_TP |
10835                            SUPPORTED_Autoneg |
10836                            SUPPORTED_Pause |
10837                            SUPPORTED_Asym_Pause),
10838         .media_type     = ETH_PHY_BASE_T,
10839         .ver_addr       = 0,
10840         .req_flow_ctrl  = 0,
10841         .req_line_speed = 0,
10842         .speed_cap_mask = 0,
10843         .req_duplex     = 0,
10844         .rsrv           = 0,
10845         .config_init    = (config_init_t)bnx2x_8481_config_init,
10846         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10847         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
10848         .config_loopback = (config_loopback_t)NULL,
10849         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10850         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
10851         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10852         .phy_specific_func = (phy_specific_func_t)NULL
10853 };
10854
10855 static struct bnx2x_phy phy_84823 = {
10856         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
10857         .addr           = 0xff,
10858         .def_md_devad   = 0,
10859         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10860                           FLAGS_REARM_LATCH_SIGNAL,
10861         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10862         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10863         .mdio_ctrl      = 0,
10864         .supported      = (SUPPORTED_10baseT_Half |
10865                            SUPPORTED_10baseT_Full |
10866                            SUPPORTED_100baseT_Half |
10867                            SUPPORTED_100baseT_Full |
10868                            SUPPORTED_1000baseT_Full |
10869                            SUPPORTED_10000baseT_Full |
10870                            SUPPORTED_TP |
10871                            SUPPORTED_Autoneg |
10872                            SUPPORTED_Pause |
10873                            SUPPORTED_Asym_Pause),
10874         .media_type     = ETH_PHY_BASE_T,
10875         .ver_addr       = 0,
10876         .req_flow_ctrl  = 0,
10877         .req_line_speed = 0,
10878         .speed_cap_mask = 0,
10879         .req_duplex     = 0,
10880         .rsrv           = 0,
10881         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10882         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10883         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10884         .config_loopback = (config_loopback_t)NULL,
10885         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10886         .hw_reset       = (hw_reset_t)NULL,
10887         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10888         .phy_specific_func = (phy_specific_func_t)NULL
10889 };
10890
10891 static struct bnx2x_phy phy_84833 = {
10892         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
10893         .addr           = 0xff,
10894         .def_md_devad   = 0,
10895         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
10896                             FLAGS_REARM_LATCH_SIGNAL,
10897         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10898         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10899         .mdio_ctrl      = 0,
10900         .supported      = (SUPPORTED_100baseT_Half |
10901                            SUPPORTED_100baseT_Full |
10902                            SUPPORTED_1000baseT_Full |
10903                            SUPPORTED_10000baseT_Full |
10904                            SUPPORTED_TP |
10905                            SUPPORTED_Autoneg |
10906                            SUPPORTED_Pause |
10907                            SUPPORTED_Asym_Pause),
10908         .media_type     = ETH_PHY_BASE_T,
10909         .ver_addr       = 0,
10910         .req_flow_ctrl  = 0,
10911         .req_line_speed = 0,
10912         .speed_cap_mask = 0,
10913         .req_duplex     = 0,
10914         .rsrv           = 0,
10915         .config_init    = (config_init_t)bnx2x_848x3_config_init,
10916         .read_status    = (read_status_t)bnx2x_848xx_read_status,
10917         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
10918         .config_loopback = (config_loopback_t)NULL,
10919         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
10920         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
10921         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
10922         .phy_specific_func = (phy_specific_func_t)NULL
10923 };
10924
10925 static struct bnx2x_phy phy_54618se = {
10926         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
10927         .addr           = 0xff,
10928         .def_md_devad   = 0,
10929         .flags          = FLAGS_INIT_XGXS_FIRST,
10930         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10931         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
10932         .mdio_ctrl      = 0,
10933         .supported      = (SUPPORTED_10baseT_Half |
10934                            SUPPORTED_10baseT_Full |
10935                            SUPPORTED_100baseT_Half |
10936                            SUPPORTED_100baseT_Full |
10937                            SUPPORTED_1000baseT_Full |
10938                            SUPPORTED_TP |
10939                            SUPPORTED_Autoneg |
10940                            SUPPORTED_Pause |
10941                            SUPPORTED_Asym_Pause),
10942         .media_type     = ETH_PHY_BASE_T,
10943         .ver_addr       = 0,
10944         .req_flow_ctrl  = 0,
10945         .req_line_speed = 0,
10946         .speed_cap_mask = 0,
10947         /* req_duplex = */0,
10948         /* rsrv = */0,
10949         .config_init    = (config_init_t)bnx2x_54618se_config_init,
10950         .read_status    = (read_status_t)bnx2x_54618se_read_status,
10951         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
10952         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
10953         .format_fw_ver  = (format_fw_ver_t)NULL,
10954         .hw_reset       = (hw_reset_t)NULL,
10955         .set_link_led   = (set_link_led_t)bnx2x_54618se_set_link_led,
10956         .phy_specific_func = (phy_specific_func_t)NULL
10957 };
10958 /*****************************************************************/
10959 /*                                                               */
10960 /* Populate the phy according. Main function: bnx2x_populate_phy   */
10961 /*                                                               */
10962 /*****************************************************************/
10963
10964 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
10965                                      struct bnx2x_phy *phy, u8 port,
10966                                      u8 phy_index)
10967 {
10968         /* Get the 4 lanes xgxs config rx and tx */
10969         u32 rx = 0, tx = 0, i;
10970         for (i = 0; i < 2; i++) {
10971                 /*
10972                  * INT_PHY and EXT_PHY1 share the same value location in the
10973                  * shmem. When num_phys is greater than 1, than this value
10974                  * applies only to EXT_PHY1
10975                  */
10976                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
10977                         rx = REG_RD(bp, shmem_base +
10978                                     offsetof(struct shmem_region,
10979                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
10980
10981                         tx = REG_RD(bp, shmem_base +
10982                                     offsetof(struct shmem_region,
10983                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
10984                 } else {
10985                         rx = REG_RD(bp, shmem_base +
10986                                     offsetof(struct shmem_region,
10987                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10988
10989                         tx = REG_RD(bp, shmem_base +
10990                                     offsetof(struct shmem_region,
10991                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
10992                 }
10993
10994                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
10995                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
10996
10997                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
10998                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
10999         }
11000 }
11001
11002 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11003                                     u8 phy_index, u8 port)
11004 {
11005         u32 ext_phy_config = 0;
11006         switch (phy_index) {
11007         case EXT_PHY1:
11008                 ext_phy_config = REG_RD(bp, shmem_base +
11009                                               offsetof(struct shmem_region,
11010                         dev_info.port_hw_config[port].external_phy_config));
11011                 break;
11012         case EXT_PHY2:
11013                 ext_phy_config = REG_RD(bp, shmem_base +
11014                                               offsetof(struct shmem_region,
11015                         dev_info.port_hw_config[port].external_phy_config2));
11016                 break;
11017         default:
11018                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11019                 return -EINVAL;
11020         }
11021
11022         return ext_phy_config;
11023 }
11024 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11025                                   struct bnx2x_phy *phy)
11026 {
11027         u32 phy_addr;
11028         u32 chip_id;
11029         u32 switch_cfg = (REG_RD(bp, shmem_base +
11030                                        offsetof(struct shmem_region,
11031                         dev_info.port_feature_config[port].link_config)) &
11032                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11033         chip_id = REG_RD(bp, MISC_REG_CHIP_NUM) << 16;
11034         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11035         if (USES_WARPCORE(bp)) {
11036                 u32 serdes_net_if;
11037                 phy_addr = REG_RD(bp,
11038                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11039                 *phy = phy_warpcore;
11040                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11041                         phy->flags |= FLAGS_4_PORT_MODE;
11042                 else
11043                         phy->flags &= ~FLAGS_4_PORT_MODE;
11044                         /* Check Dual mode */
11045                 serdes_net_if = (REG_RD(bp, shmem_base +
11046                                         offsetof(struct shmem_region, dev_info.
11047                                         port_hw_config[port].default_cfg)) &
11048                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11049                 /*
11050                  * Set the appropriate supported and flags indications per
11051                  * interface type of the chip
11052                  */
11053                 switch (serdes_net_if) {
11054                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11055                         phy->supported &= (SUPPORTED_10baseT_Half |
11056                                            SUPPORTED_10baseT_Full |
11057                                            SUPPORTED_100baseT_Half |
11058                                            SUPPORTED_100baseT_Full |
11059                                            SUPPORTED_1000baseT_Full |
11060                                            SUPPORTED_FIBRE |
11061                                            SUPPORTED_Autoneg |
11062                                            SUPPORTED_Pause |
11063                                            SUPPORTED_Asym_Pause);
11064                         phy->media_type = ETH_PHY_BASE_T;
11065                         break;
11066                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11067                         phy->media_type = ETH_PHY_XFP_FIBER;
11068                         break;
11069                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11070                         phy->supported &= (SUPPORTED_1000baseT_Full |
11071                                            SUPPORTED_10000baseT_Full |
11072                                            SUPPORTED_FIBRE |
11073                                            SUPPORTED_Pause |
11074                                            SUPPORTED_Asym_Pause);
11075                         phy->media_type = ETH_PHY_SFP_FIBER;
11076                         break;
11077                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11078                         phy->media_type = ETH_PHY_KR;
11079                         phy->supported &= (SUPPORTED_1000baseT_Full |
11080                                            SUPPORTED_10000baseT_Full |
11081                                            SUPPORTED_FIBRE |
11082                                            SUPPORTED_Autoneg |
11083                                            SUPPORTED_Pause |
11084                                            SUPPORTED_Asym_Pause);
11085                         break;
11086                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11087                         phy->media_type = ETH_PHY_KR;
11088                         phy->flags |= FLAGS_WC_DUAL_MODE;
11089                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11090                                            SUPPORTED_FIBRE |
11091                                            SUPPORTED_Pause |
11092                                            SUPPORTED_Asym_Pause);
11093                         break;
11094                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11095                         phy->media_type = ETH_PHY_KR;
11096                         phy->flags |= FLAGS_WC_DUAL_MODE;
11097                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11098                                            SUPPORTED_FIBRE |
11099                                            SUPPORTED_Pause |
11100                                            SUPPORTED_Asym_Pause);
11101                         break;
11102                 default:
11103                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11104                                        serdes_net_if);
11105                         break;
11106                 }
11107
11108                 /*
11109                  * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11110                  * was not set as expected. For B0, ECO will be enabled so there
11111                  * won't be an issue there
11112                  */
11113                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11114                         phy->flags |= FLAGS_MDC_MDIO_WA;
11115         } else {
11116                 switch (switch_cfg) {
11117                 case SWITCH_CFG_1G:
11118                         phy_addr = REG_RD(bp,
11119                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11120                                           port * 0x10);
11121                         *phy = phy_serdes;
11122                         break;
11123                 case SWITCH_CFG_10G:
11124                         phy_addr = REG_RD(bp,
11125                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11126                                           port * 0x18);
11127                         *phy = phy_xgxs;
11128                         break;
11129                 default:
11130                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11131                         return -EINVAL;
11132                 }
11133         }
11134         phy->addr = (u8)phy_addr;
11135         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11136                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11137                                             port);
11138         if (CHIP_IS_E2(bp))
11139                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11140         else
11141                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11142
11143         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11144                    port, phy->addr, phy->mdio_ctrl);
11145
11146         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
11147         return 0;
11148 }
11149
11150 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11151                                   u8 phy_index,
11152                                   u32 shmem_base,
11153                                   u32 shmem2_base,
11154                                   u8 port,
11155                                   struct bnx2x_phy *phy)
11156 {
11157         u32 ext_phy_config, phy_type, config2;
11158         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
11159         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
11160                                                   phy_index, port);
11161         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11162         /* Select the phy type */
11163         switch (phy_type) {
11164         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
11165                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
11166                 *phy = phy_8073;
11167                 break;
11168         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
11169                 *phy = phy_8705;
11170                 break;
11171         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
11172                 *phy = phy_8706;
11173                 break;
11174         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
11175                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11176                 *phy = phy_8726;
11177                 break;
11178         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
11179                 /* BCM8727_NOC => BCM8727 no over current */
11180                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11181                 *phy = phy_8727;
11182                 phy->flags |= FLAGS_NOC;
11183                 break;
11184         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
11185         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
11186                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
11187                 *phy = phy_8727;
11188                 break;
11189         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
11190                 *phy = phy_8481;
11191                 break;
11192         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
11193                 *phy = phy_84823;
11194                 break;
11195         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
11196                 *phy = phy_84833;
11197                 break;
11198         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
11199                 *phy = phy_54618se;
11200                 break;
11201         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
11202                 *phy = phy_7101;
11203                 break;
11204         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
11205                 *phy = phy_null;
11206                 return -EINVAL;
11207         default:
11208                 *phy = phy_null;
11209                 return 0;
11210         }
11211
11212         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11213         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11214
11215         /*
11216          * The shmem address of the phy version is located on different
11217          * structures. In case this structure is too old, do not set
11218          * the address
11219          */
11220         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
11221                                         dev_info.shared_hw_config.config2));
11222         if (phy_index == EXT_PHY1) {
11223                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
11224                                 port_mb[port].ext_phy_fw_version);
11225
11226                 /* Check specific mdc mdio settings */
11227                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
11228                         mdc_mdio_access = config2 &
11229                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
11230         } else {
11231                 u32 size = REG_RD(bp, shmem2_base);
11232
11233                 if (size >
11234                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
11235                         phy->ver_addr = shmem2_base +
11236                             offsetof(struct shmem2_region,
11237                                      ext_phy_fw_version2[port]);
11238                 }
11239                 /* Check specific mdc mdio settings */
11240                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
11241                         mdc_mdio_access = (config2 &
11242                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
11243                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
11244                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
11245         }
11246         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
11247
11248         /*
11249          * In case mdc/mdio_access of the external phy is different than the
11250          * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11251          * to prevent one port interfere with another port's CL45 operations.
11252          */
11253         if (mdc_mdio_access != SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH)
11254                 phy->flags |= FLAGS_HW_LOCK_REQUIRED;
11255         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
11256                    phy_type, port, phy_index);
11257         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
11258                    phy->addr, phy->mdio_ctrl);
11259         return 0;
11260 }
11261
11262 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
11263                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
11264 {
11265         int status = 0;
11266         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
11267         if (phy_index == INT_PHY)
11268                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
11269         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
11270                                         port, phy);
11271         return status;
11272 }
11273
11274 static void bnx2x_phy_def_cfg(struct link_params *params,
11275                               struct bnx2x_phy *phy,
11276                               u8 phy_index)
11277 {
11278         struct bnx2x *bp = params->bp;
11279         u32 link_config;
11280         /* Populate the default phy configuration for MF mode */
11281         if (phy_index == EXT_PHY2) {
11282                 link_config = REG_RD(bp, params->shmem_base +
11283                                      offsetof(struct shmem_region, dev_info.
11284                         port_feature_config[params->port].link_config2));
11285                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11286                                              offsetof(struct shmem_region,
11287                                                       dev_info.
11288                         port_hw_config[params->port].speed_capability_mask2));
11289         } else {
11290                 link_config = REG_RD(bp, params->shmem_base +
11291                                      offsetof(struct shmem_region, dev_info.
11292                                 port_feature_config[params->port].link_config));
11293                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
11294                                              offsetof(struct shmem_region,
11295                                                       dev_info.
11296                         port_hw_config[params->port].speed_capability_mask));
11297         }
11298         DP(NETIF_MSG_LINK, "Default config phy idx %x cfg 0x%x speed_cap_mask"
11299                        " 0x%x\n", phy_index, link_config, phy->speed_cap_mask);
11300
11301         phy->req_duplex = DUPLEX_FULL;
11302         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
11303         case PORT_FEATURE_LINK_SPEED_10M_HALF:
11304                 phy->req_duplex = DUPLEX_HALF;
11305         case PORT_FEATURE_LINK_SPEED_10M_FULL:
11306                 phy->req_line_speed = SPEED_10;
11307                 break;
11308         case PORT_FEATURE_LINK_SPEED_100M_HALF:
11309                 phy->req_duplex = DUPLEX_HALF;
11310         case PORT_FEATURE_LINK_SPEED_100M_FULL:
11311                 phy->req_line_speed = SPEED_100;
11312                 break;
11313         case PORT_FEATURE_LINK_SPEED_1G:
11314                 phy->req_line_speed = SPEED_1000;
11315                 break;
11316         case PORT_FEATURE_LINK_SPEED_2_5G:
11317                 phy->req_line_speed = SPEED_2500;
11318                 break;
11319         case PORT_FEATURE_LINK_SPEED_10G_CX4:
11320                 phy->req_line_speed = SPEED_10000;
11321                 break;
11322         default:
11323                 phy->req_line_speed = SPEED_AUTO_NEG;
11324                 break;
11325         }
11326
11327         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
11328         case PORT_FEATURE_FLOW_CONTROL_AUTO:
11329                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
11330                 break;
11331         case PORT_FEATURE_FLOW_CONTROL_TX:
11332                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
11333                 break;
11334         case PORT_FEATURE_FLOW_CONTROL_RX:
11335                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
11336                 break;
11337         case PORT_FEATURE_FLOW_CONTROL_BOTH:
11338                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
11339                 break;
11340         default:
11341                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11342                 break;
11343         }
11344 }
11345
11346 u32 bnx2x_phy_selection(struct link_params *params)
11347 {
11348         u32 phy_config_swapped, prio_cfg;
11349         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
11350
11351         phy_config_swapped = params->multi_phy_config &
11352                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11353
11354         prio_cfg = params->multi_phy_config &
11355                         PORT_HW_CFG_PHY_SELECTION_MASK;
11356
11357         if (phy_config_swapped) {
11358                 switch (prio_cfg) {
11359                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11360                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
11361                      break;
11362                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11363                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
11364                      break;
11365                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11366                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
11367                      break;
11368                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11369                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
11370                      break;
11371                 }
11372         } else
11373                 return_cfg = prio_cfg;
11374
11375         return return_cfg;
11376 }
11377
11378
11379 int bnx2x_phy_probe(struct link_params *params)
11380 {
11381         u8 phy_index, actual_phy_idx, link_cfg_idx;
11382         u32 phy_config_swapped, sync_offset, media_types;
11383         struct bnx2x *bp = params->bp;
11384         struct bnx2x_phy *phy;
11385         params->num_phys = 0;
11386         DP(NETIF_MSG_LINK, "Begin phy probe\n");
11387         phy_config_swapped = params->multi_phy_config &
11388                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
11389
11390         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
11391               phy_index++) {
11392                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
11393                 actual_phy_idx = phy_index;
11394                 if (phy_config_swapped) {
11395                         if (phy_index == EXT_PHY1)
11396                                 actual_phy_idx = EXT_PHY2;
11397                         else if (phy_index == EXT_PHY2)
11398                                 actual_phy_idx = EXT_PHY1;
11399                 }
11400                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
11401                                " actual_phy_idx %x\n", phy_config_swapped,
11402                            phy_index, actual_phy_idx);
11403                 phy = &params->phy[actual_phy_idx];
11404                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
11405                                        params->shmem2_base, params->port,
11406                                        phy) != 0) {
11407                         params->num_phys = 0;
11408                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
11409                                    phy_index);
11410                         for (phy_index = INT_PHY;
11411                               phy_index < MAX_PHYS;
11412                               phy_index++)
11413                                 *phy = phy_null;
11414                         return -EINVAL;
11415                 }
11416                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
11417                         break;
11418
11419                 sync_offset = params->shmem_base +
11420                         offsetof(struct shmem_region,
11421                         dev_info.port_hw_config[params->port].media_type);
11422                 media_types = REG_RD(bp, sync_offset);
11423
11424                 /*
11425                  * Update media type for non-PMF sync only for the first time
11426                  * In case the media type changes afterwards, it will be updated
11427                  * using the update_status function
11428                  */
11429                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
11430                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11431                                      actual_phy_idx))) == 0) {
11432                         media_types |= ((phy->media_type &
11433                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
11434                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
11435                                  actual_phy_idx));
11436                 }
11437                 REG_WR(bp, sync_offset, media_types);
11438
11439                 bnx2x_phy_def_cfg(params, phy, phy_index);
11440                 params->num_phys++;
11441         }
11442
11443         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
11444         return 0;
11445 }
11446
11447 void bnx2x_init_bmac_loopback(struct link_params *params,
11448                               struct link_vars *vars)
11449 {
11450         struct bnx2x *bp = params->bp;
11451                 vars->link_up = 1;
11452                 vars->line_speed = SPEED_10000;
11453                 vars->duplex = DUPLEX_FULL;
11454                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11455                 vars->mac_type = MAC_TYPE_BMAC;
11456
11457                 vars->phy_flags = PHY_XGXS_FLAG;
11458
11459                 bnx2x_xgxs_deassert(params);
11460
11461                 /* set bmac loopback */
11462                 bnx2x_bmac_enable(params, vars, 1);
11463
11464                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11465 }
11466
11467 void bnx2x_init_emac_loopback(struct link_params *params,
11468                               struct link_vars *vars)
11469 {
11470         struct bnx2x *bp = params->bp;
11471                 vars->link_up = 1;
11472                 vars->line_speed = SPEED_1000;
11473                 vars->duplex = DUPLEX_FULL;
11474                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11475                 vars->mac_type = MAC_TYPE_EMAC;
11476
11477                 vars->phy_flags = PHY_XGXS_FLAG;
11478
11479                 bnx2x_xgxs_deassert(params);
11480                 /* set bmac loopback */
11481                 bnx2x_emac_enable(params, vars, 1);
11482                 bnx2x_emac_program(params, vars);
11483                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11484 }
11485
11486 void bnx2x_init_xmac_loopback(struct link_params *params,
11487                               struct link_vars *vars)
11488 {
11489         struct bnx2x *bp = params->bp;
11490         vars->link_up = 1;
11491         if (!params->req_line_speed[0])
11492                 vars->line_speed = SPEED_10000;
11493         else
11494                 vars->line_speed = params->req_line_speed[0];
11495         vars->duplex = DUPLEX_FULL;
11496         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11497         vars->mac_type = MAC_TYPE_XMAC;
11498         vars->phy_flags = PHY_XGXS_FLAG;
11499         /*
11500          * Set WC to loopback mode since link is required to provide clock
11501          * to the XMAC in 20G mode
11502          */
11503         if (vars->line_speed == SPEED_20000) {
11504                 bnx2x_set_aer_mmd(params, &params->phy[0]);
11505                 bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
11506                 params->phy[INT_PHY].config_loopback(
11507                         &params->phy[INT_PHY],
11508                         params);
11509         }
11510         bnx2x_xmac_enable(params, vars, 1);
11511         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11512 }
11513
11514 void bnx2x_init_umac_loopback(struct link_params *params,
11515                               struct link_vars *vars)
11516 {
11517         struct bnx2x *bp = params->bp;
11518         vars->link_up = 1;
11519         vars->line_speed = SPEED_1000;
11520         vars->duplex = DUPLEX_FULL;
11521         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11522         vars->mac_type = MAC_TYPE_UMAC;
11523         vars->phy_flags = PHY_XGXS_FLAG;
11524         bnx2x_umac_enable(params, vars, 1);
11525
11526         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11527 }
11528
11529 void bnx2x_init_xgxs_loopback(struct link_params *params,
11530                               struct link_vars *vars)
11531 {
11532         struct bnx2x *bp = params->bp;
11533                 vars->link_up = 1;
11534                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11535                 vars->duplex = DUPLEX_FULL;
11536         if (params->req_line_speed[0] == SPEED_1000)
11537                         vars->line_speed = SPEED_1000;
11538         else
11539                         vars->line_speed = SPEED_10000;
11540
11541         if (!USES_WARPCORE(bp))
11542                 bnx2x_xgxs_deassert(params);
11543         bnx2x_link_initialize(params, vars);
11544
11545         if (params->req_line_speed[0] == SPEED_1000) {
11546                 if (USES_WARPCORE(bp))
11547                         bnx2x_umac_enable(params, vars, 0);
11548                 else {
11549                         bnx2x_emac_program(params, vars);
11550                         bnx2x_emac_enable(params, vars, 0);
11551                 }
11552         } else {
11553                 if (USES_WARPCORE(bp))
11554                         bnx2x_xmac_enable(params, vars, 0);
11555                 else
11556                         bnx2x_bmac_enable(params, vars, 0);
11557         }
11558
11559                 if (params->loopback_mode == LOOPBACK_XGXS) {
11560                         /* set 10G XGXS loopback */
11561                         params->phy[INT_PHY].config_loopback(
11562                                 &params->phy[INT_PHY],
11563                                 params);
11564
11565                 } else {
11566                         /* set external phy loopback */
11567                         u8 phy_index;
11568                         for (phy_index = EXT_PHY1;
11569                               phy_index < params->num_phys; phy_index++) {
11570                                 if (params->phy[phy_index].config_loopback)
11571                                         params->phy[phy_index].config_loopback(
11572                                                 &params->phy[phy_index],
11573                                                 params);
11574                         }
11575                 }
11576                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
11577
11578         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
11579 }
11580
11581 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
11582 {
11583         struct bnx2x *bp = params->bp;
11584         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
11585         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
11586                    params->req_line_speed[0], params->req_flow_ctrl[0]);
11587         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
11588                    params->req_line_speed[1], params->req_flow_ctrl[1]);
11589         vars->link_status = 0;
11590         vars->phy_link_up = 0;
11591         vars->link_up = 0;
11592         vars->line_speed = 0;
11593         vars->duplex = DUPLEX_FULL;
11594         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11595         vars->mac_type = MAC_TYPE_NONE;
11596         vars->phy_flags = 0;
11597
11598         /* disable attentions */
11599         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
11600                        (NIG_MASK_XGXS0_LINK_STATUS |
11601                         NIG_MASK_XGXS0_LINK10G |
11602                         NIG_MASK_SERDES0_LINK_STATUS |
11603                         NIG_MASK_MI_INT));
11604
11605         bnx2x_emac_init(params, vars);
11606
11607         if (params->num_phys == 0) {
11608                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
11609                 return -EINVAL;
11610         }
11611         set_phy_vars(params, vars);
11612
11613         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
11614         switch (params->loopback_mode) {
11615         case LOOPBACK_BMAC:
11616                 bnx2x_init_bmac_loopback(params, vars);
11617                 break;
11618         case LOOPBACK_EMAC:
11619                 bnx2x_init_emac_loopback(params, vars);
11620                 break;
11621         case LOOPBACK_XMAC:
11622                 bnx2x_init_xmac_loopback(params, vars);
11623                 break;
11624         case LOOPBACK_UMAC:
11625                 bnx2x_init_umac_loopback(params, vars);
11626                 break;
11627         case LOOPBACK_XGXS:
11628         case LOOPBACK_EXT_PHY:
11629                 bnx2x_init_xgxs_loopback(params, vars);
11630                 break;
11631         default:
11632                 if (!CHIP_IS_E3(bp)) {
11633                         if (params->switch_cfg == SWITCH_CFG_10G)
11634                                 bnx2x_xgxs_deassert(params);
11635                         else
11636                                 bnx2x_serdes_deassert(bp, params->port);
11637                 }
11638                 bnx2x_link_initialize(params, vars);
11639                 msleep(30);
11640                 bnx2x_link_int_enable(params);
11641                 break;
11642         }
11643         return 0;
11644 }
11645
11646 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11647                      u8 reset_ext_phy)
11648 {
11649         struct bnx2x *bp = params->bp;
11650         u8 phy_index, port = params->port, clear_latch_ind = 0;
11651         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
11652         /* disable attentions */
11653         vars->link_status = 0;
11654         bnx2x_update_mng(params, vars->link_status);
11655         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
11656                        (NIG_MASK_XGXS0_LINK_STATUS |
11657                         NIG_MASK_XGXS0_LINK10G |
11658                         NIG_MASK_SERDES0_LINK_STATUS |
11659                         NIG_MASK_MI_INT));
11660
11661         /* activate nig drain */
11662         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
11663
11664         /* disable nig egress interface */
11665         if (!CHIP_IS_E3(bp)) {
11666                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
11667                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
11668         }
11669
11670         /* Stop BigMac rx */
11671         if (!CHIP_IS_E3(bp))
11672                 bnx2x_bmac_rx_disable(bp, port);
11673         else
11674                 bnx2x_xmac_disable(params);
11675         /* disable emac */
11676         if (!CHIP_IS_E3(bp))
11677                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
11678
11679         msleep(10);
11680         /* The PHY reset is controlled by GPIO 1
11681          * Hold it as vars low
11682          */
11683          /* clear link led */
11684         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
11685
11686         if (reset_ext_phy) {
11687                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
11688                       phy_index++) {
11689                         if (params->phy[phy_index].link_reset)
11690                                 params->phy[phy_index].link_reset(
11691                                         &params->phy[phy_index],
11692                                         params);
11693                         if (params->phy[phy_index].flags &
11694                             FLAGS_REARM_LATCH_SIGNAL)
11695                                 clear_latch_ind = 1;
11696                 }
11697         }
11698
11699         if (clear_latch_ind) {
11700                 /* Clear latching indication */
11701                 bnx2x_rearm_latch_signal(bp, port, 0);
11702                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
11703                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
11704         }
11705         if (params->phy[INT_PHY].link_reset)
11706                 params->phy[INT_PHY].link_reset(
11707                         &params->phy[INT_PHY], params);
11708         /* reset BigMac */
11709         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11710                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11711
11712         /* disable nig ingress interface */
11713         if (!CHIP_IS_E3(bp)) {
11714                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11715                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11716         }
11717         vars->link_up = 0;
11718         vars->phy_flags = 0;
11719         return 0;
11720 }
11721
11722 /****************************************************************************/
11723 /*                              Common function                             */
11724 /****************************************************************************/
11725 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
11726                                       u32 shmem_base_path[],
11727                                       u32 shmem2_base_path[], u8 phy_index,
11728                                       u32 chip_id)
11729 {
11730         struct bnx2x_phy phy[PORT_MAX];
11731         struct bnx2x_phy *phy_blk[PORT_MAX];
11732         u16 val;
11733         s8 port = 0;
11734         s8 port_of_path = 0;
11735         u32 swap_val, swap_override;
11736         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
11737         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
11738         port ^= (swap_val && swap_override);
11739         bnx2x_ext_phy_hw_reset(bp, port);
11740         /* PART1 - Reset both phys */
11741         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11742                 u32 shmem_base, shmem2_base;
11743                 /* In E2, same phy is using for port0 of the two paths */
11744                 if (CHIP_IS_E1x(bp)) {
11745                         shmem_base = shmem_base_path[0];
11746                         shmem2_base = shmem2_base_path[0];
11747                         port_of_path = port;
11748                 } else {
11749                         shmem_base = shmem_base_path[port];
11750                         shmem2_base = shmem2_base_path[port];
11751                         port_of_path = 0;
11752                 }
11753
11754                 /* Extract the ext phy address for the port */
11755                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11756                                        port_of_path, &phy[port]) !=
11757                     0) {
11758                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
11759                         return -EINVAL;
11760                 }
11761                 /* disable attentions */
11762                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
11763                                port_of_path*4,
11764                                (NIG_MASK_XGXS0_LINK_STATUS |
11765                                 NIG_MASK_XGXS0_LINK10G |
11766                                 NIG_MASK_SERDES0_LINK_STATUS |
11767                                 NIG_MASK_MI_INT));
11768
11769                 /* Need to take the phy out of low power mode in order
11770                         to write to access its registers */
11771                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11772                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11773                                port);
11774
11775                 /* Reset the phy */
11776                 bnx2x_cl45_write(bp, &phy[port],
11777                                  MDIO_PMA_DEVAD,
11778                                  MDIO_PMA_REG_CTRL,
11779                                  1<<15);
11780         }
11781
11782         /* Add delay of 150ms after reset */
11783         msleep(150);
11784
11785         if (phy[PORT_0].addr & 0x1) {
11786                 phy_blk[PORT_0] = &(phy[PORT_1]);
11787                 phy_blk[PORT_1] = &(phy[PORT_0]);
11788         } else {
11789                 phy_blk[PORT_0] = &(phy[PORT_0]);
11790                 phy_blk[PORT_1] = &(phy[PORT_1]);
11791         }
11792
11793         /* PART2 - Download firmware to both phys */
11794         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11795                 if (CHIP_IS_E1x(bp))
11796                         port_of_path = port;
11797                 else
11798                         port_of_path = 0;
11799
11800                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
11801                            phy_blk[port]->addr);
11802                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
11803                                                       port_of_path))
11804                         return -EINVAL;
11805
11806                 /* Only set bit 10 = 1 (Tx power down) */
11807                 bnx2x_cl45_read(bp, phy_blk[port],
11808                                 MDIO_PMA_DEVAD,
11809                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11810
11811                 /* Phase1 of TX_POWER_DOWN reset */
11812                 bnx2x_cl45_write(bp, phy_blk[port],
11813                                  MDIO_PMA_DEVAD,
11814                                  MDIO_PMA_REG_TX_POWER_DOWN,
11815                                  (val | 1<<10));
11816         }
11817
11818         /*
11819          * Toggle Transmitter: Power down and then up with 600ms delay
11820          * between
11821          */
11822         msleep(600);
11823
11824         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
11825         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11826                 /* Phase2 of POWER_DOWN_RESET */
11827                 /* Release bit 10 (Release Tx power down) */
11828                 bnx2x_cl45_read(bp, phy_blk[port],
11829                                 MDIO_PMA_DEVAD,
11830                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
11831
11832                 bnx2x_cl45_write(bp, phy_blk[port],
11833                                 MDIO_PMA_DEVAD,
11834                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
11835                 msleep(15);
11836
11837                 /* Read modify write the SPI-ROM version select register */
11838                 bnx2x_cl45_read(bp, phy_blk[port],
11839                                 MDIO_PMA_DEVAD,
11840                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
11841                 bnx2x_cl45_write(bp, phy_blk[port],
11842                                  MDIO_PMA_DEVAD,
11843                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
11844
11845                 /* set GPIO2 back to LOW */
11846                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11847                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
11848         }
11849         return 0;
11850 }
11851 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
11852                                       u32 shmem_base_path[],
11853                                       u32 shmem2_base_path[], u8 phy_index,
11854                                       u32 chip_id)
11855 {
11856         u32 val;
11857         s8 port;
11858         struct bnx2x_phy phy;
11859         /* Use port1 because of the static port-swap */
11860         /* Enable the module detection interrupt */
11861         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
11862         val |= ((1<<MISC_REGISTERS_GPIO_3)|
11863                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
11864         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
11865
11866         bnx2x_ext_phy_hw_reset(bp, 0);
11867         msleep(5);
11868         for (port = 0; port < PORT_MAX; port++) {
11869                 u32 shmem_base, shmem2_base;
11870
11871                 /* In E2, same phy is using for port0 of the two paths */
11872                 if (CHIP_IS_E1x(bp)) {
11873                         shmem_base = shmem_base_path[0];
11874                         shmem2_base = shmem2_base_path[0];
11875                 } else {
11876                         shmem_base = shmem_base_path[port];
11877                         shmem2_base = shmem2_base_path[port];
11878                 }
11879                 /* Extract the ext phy address for the port */
11880                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11881                                        port, &phy) !=
11882                     0) {
11883                         DP(NETIF_MSG_LINK, "populate phy failed\n");
11884                         return -EINVAL;
11885                 }
11886
11887                 /* Reset phy*/
11888                 bnx2x_cl45_write(bp, &phy,
11889                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
11890
11891
11892                 /* Set fault module detected LED on */
11893                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
11894                                MISC_REGISTERS_GPIO_HIGH,
11895                                port);
11896         }
11897
11898         return 0;
11899 }
11900 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
11901                                          u8 *io_gpio, u8 *io_port)
11902 {
11903
11904         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
11905                                           offsetof(struct shmem_region,
11906                                 dev_info.port_hw_config[PORT_0].default_cfg));
11907         switch (phy_gpio_reset) {
11908         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
11909                 *io_gpio = 0;
11910                 *io_port = 0;
11911                 break;
11912         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
11913                 *io_gpio = 1;
11914                 *io_port = 0;
11915                 break;
11916         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
11917                 *io_gpio = 2;
11918                 *io_port = 0;
11919                 break;
11920         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
11921                 *io_gpio = 3;
11922                 *io_port = 0;
11923                 break;
11924         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
11925                 *io_gpio = 0;
11926                 *io_port = 1;
11927                 break;
11928         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
11929                 *io_gpio = 1;
11930                 *io_port = 1;
11931                 break;
11932         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
11933                 *io_gpio = 2;
11934                 *io_port = 1;
11935                 break;
11936         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
11937                 *io_gpio = 3;
11938                 *io_port = 1;
11939                 break;
11940         default:
11941                 /* Don't override the io_gpio and io_port */
11942                 break;
11943         }
11944 }
11945
11946 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
11947                                       u32 shmem_base_path[],
11948                                       u32 shmem2_base_path[], u8 phy_index,
11949                                       u32 chip_id)
11950 {
11951         s8 port, reset_gpio;
11952         u32 swap_val, swap_override;
11953         struct bnx2x_phy phy[PORT_MAX];
11954         struct bnx2x_phy *phy_blk[PORT_MAX];
11955         s8 port_of_path;
11956         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
11957         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
11958
11959         reset_gpio = MISC_REGISTERS_GPIO_1;
11960         port = 1;
11961
11962         /*
11963          * Retrieve the reset gpio/port which control the reset.
11964          * Default is GPIO1, PORT1
11965          */
11966         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
11967                                      (u8 *)&reset_gpio, (u8 *)&port);
11968
11969         /* Calculate the port based on port swap */
11970         port ^= (swap_val && swap_override);
11971
11972         /* Initiate PHY reset*/
11973         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
11974                        port);
11975         msleep(1);
11976         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11977                        port);
11978
11979         msleep(5);
11980
11981         /* PART1 - Reset both phys */
11982         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
11983                 u32 shmem_base, shmem2_base;
11984
11985                 /* In E2, same phy is using for port0 of the two paths */
11986                 if (CHIP_IS_E1x(bp)) {
11987                         shmem_base = shmem_base_path[0];
11988                         shmem2_base = shmem2_base_path[0];
11989                         port_of_path = port;
11990                 } else {
11991                         shmem_base = shmem_base_path[port];
11992                         shmem2_base = shmem2_base_path[port];
11993                         port_of_path = 0;
11994                 }
11995
11996                 /* Extract the ext phy address for the port */
11997                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
11998                                        port_of_path, &phy[port]) !=
11999                                        0) {
12000                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12001                         return -EINVAL;
12002                 }
12003                 /* disable attentions */
12004                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12005                                port_of_path*4,
12006                                (NIG_MASK_XGXS0_LINK_STATUS |
12007                                 NIG_MASK_XGXS0_LINK10G |
12008                                 NIG_MASK_SERDES0_LINK_STATUS |
12009                                 NIG_MASK_MI_INT));
12010
12011
12012                 /* Reset the phy */
12013                 bnx2x_cl45_write(bp, &phy[port],
12014                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
12015         }
12016
12017         /* Add delay of 150ms after reset */
12018         msleep(150);
12019         if (phy[PORT_0].addr & 0x1) {
12020                 phy_blk[PORT_0] = &(phy[PORT_1]);
12021                 phy_blk[PORT_1] = &(phy[PORT_0]);
12022         } else {
12023                 phy_blk[PORT_0] = &(phy[PORT_0]);
12024                 phy_blk[PORT_1] = &(phy[PORT_1]);
12025         }
12026         /* PART2 - Download firmware to both phys */
12027         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12028                 if (CHIP_IS_E1x(bp))
12029                         port_of_path = port;
12030                 else
12031                         port_of_path = 0;
12032                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12033                            phy_blk[port]->addr);
12034                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12035                                                       port_of_path))
12036                         return -EINVAL;
12037                 /* Disable PHY transmitter output */
12038                 bnx2x_cl45_write(bp, phy_blk[port],
12039                                  MDIO_PMA_DEVAD,
12040                                  MDIO_PMA_REG_TX_DISABLE, 1);
12041
12042         }
12043         return 0;
12044 }
12045
12046 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12047                                      u32 shmem2_base_path[], u8 phy_index,
12048                                      u32 ext_phy_type, u32 chip_id)
12049 {
12050         int rc = 0;
12051
12052         switch (ext_phy_type) {
12053         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12054                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
12055                                                 shmem2_base_path,
12056                                                 phy_index, chip_id);
12057                 break;
12058         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12059         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12060         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12061                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
12062                                                 shmem2_base_path,
12063                                                 phy_index, chip_id);
12064                 break;
12065
12066         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12067                 /*
12068                  * GPIO1 affects both ports, so there's need to pull
12069                  * it for single port alone
12070                  */
12071                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
12072                                                 shmem2_base_path,
12073                                                 phy_index, chip_id);
12074                 break;
12075         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12076                 /*
12077                  * GPIO3's are linked, and so both need to be toggled
12078                  * to obtain required 2us pulse.
12079                  */
12080                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, chip_id);
12081                 break;
12082         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12083                 rc = -EINVAL;
12084                 break;
12085         default:
12086                 DP(NETIF_MSG_LINK,
12087                            "ext_phy 0x%x common init not required\n",
12088                            ext_phy_type);
12089                 break;
12090         }
12091
12092         if (rc != 0)
12093                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
12094                                       " Port %d\n",
12095                          0);
12096         return rc;
12097 }
12098
12099 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
12100                           u32 shmem2_base_path[], u32 chip_id)
12101 {
12102         int rc = 0;
12103         u32 phy_ver, val;
12104         u8 phy_index = 0;
12105         u32 ext_phy_type, ext_phy_config;
12106         bnx2x_set_mdio_clk(bp, chip_id, PORT_0);
12107         bnx2x_set_mdio_clk(bp, chip_id, PORT_1);
12108         DP(NETIF_MSG_LINK, "Begin common phy init\n");
12109         if (CHIP_IS_E3(bp)) {
12110                 /* Enable EPIO */
12111                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
12112                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
12113         }
12114         /* Check if common init was already done */
12115         phy_ver = REG_RD(bp, shmem_base_path[0] +
12116                          offsetof(struct shmem_region,
12117                                   port_mb[PORT_0].ext_phy_fw_version));
12118         if (phy_ver) {
12119                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
12120                                phy_ver);
12121                 return 0;
12122         }
12123
12124         /* Read the ext_phy_type for arbitrary port(0) */
12125         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12126               phy_index++) {
12127                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
12128                                                           shmem_base_path[0],
12129                                                           phy_index, 0);
12130                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12131                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
12132                                                 shmem2_base_path,
12133                                                 phy_index, ext_phy_type,
12134                                                 chip_id);
12135         }
12136         return rc;
12137 }
12138
12139 static void bnx2x_check_over_curr(struct link_params *params,
12140                                   struct link_vars *vars)
12141 {
12142         struct bnx2x *bp = params->bp;
12143         u32 cfg_pin;
12144         u8 port = params->port;
12145         u32 pin_val;
12146
12147         cfg_pin = (REG_RD(bp, params->shmem_base +
12148                           offsetof(struct shmem_region,
12149                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
12150                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
12151                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
12152
12153         /* Ignore check if no external input PIN available */
12154         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
12155                 return;
12156
12157         if (!pin_val) {
12158                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
12159                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
12160                                             " been detected and the power to "
12161                                             "that SFP+ module has been removed"
12162                                             " to prevent failure of the card."
12163                                             " Please remove the SFP+ module and"
12164                                             " restart the system to clear this"
12165                                             " error.\n",
12166                          params->port);
12167                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
12168                 }
12169         } else
12170                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
12171 }
12172
12173 static void bnx2x_analyze_link_error(struct link_params *params,
12174                                      struct link_vars *vars, u32 lss_status)
12175 {
12176         struct bnx2x *bp = params->bp;
12177         /* Compare new value with previous value */
12178         u8 led_mode;
12179         u32 half_open_conn = (vars->phy_flags & PHY_HALF_OPEN_CONN_FLAG) > 0;
12180
12181         /*DP(NETIF_MSG_LINK, "CHECK LINK: %x half_open:%x-> lss:%x\n",
12182                        vars->link_up,
12183                        half_open_conn, lss_status);*/
12184
12185         if ((lss_status ^ half_open_conn) == 0)
12186                 return;
12187
12188         /* If values differ */
12189         DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12190                        half_open_conn, lss_status);
12191
12192         /*
12193          * a. Update shmem->link_status accordingly
12194          * b. Update link_vars->link_up
12195          */
12196         if (lss_status) {
12197                 vars->link_status &= ~LINK_STATUS_LINK_UP;
12198                 vars->link_up = 0;
12199                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
12200                 /*
12201                  * Set LED mode to off since the PHY doesn't know about these
12202                  * errors
12203                  */
12204                 led_mode = LED_MODE_OFF;
12205         } else {
12206                 vars->link_status |= LINK_STATUS_LINK_UP;
12207                 vars->link_up = 1;
12208                 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
12209                 led_mode = LED_MODE_OPER;
12210         }
12211         /* Update the LED according to the link state */
12212         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
12213
12214         /* Update link status in the shared memory */
12215         bnx2x_update_mng(params, vars->link_status);
12216
12217         /* C. Trigger General Attention */
12218         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
12219         bnx2x_notify_link_changed(bp);
12220 }
12221
12222 static void bnx2x_check_half_open_conn(struct link_params *params,
12223                                        struct link_vars *vars)
12224 {
12225         struct bnx2x *bp = params->bp;
12226         u32 lss_status = 0;
12227         u32 mac_base;
12228         /* In case link status is physically up @ 10G do */
12229         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
12230                 return;
12231
12232         if (!CHIP_IS_E3(bp) &&
12233             (REG_RD(bp, MISC_REG_RESET_REG_2) &
12234                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))) {
12235                 /* Check E1X / E2 BMAC */
12236                 u32 lss_status_reg;
12237                 u32 wb_data[2];
12238                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
12239                         NIG_REG_INGRESS_BMAC0_MEM;
12240                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
12241                 if (CHIP_IS_E2(bp))
12242                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
12243                 else
12244                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
12245
12246                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
12247                 lss_status = (wb_data[0] > 0);
12248
12249                 bnx2x_analyze_link_error(params, vars, lss_status);
12250         }
12251 }
12252
12253 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12254 {
12255         struct bnx2x *bp = params->bp;
12256         if (!params) {
12257                 DP(NETIF_MSG_LINK, "Ininitliazed params !\n");
12258                 return;
12259         }
12260         /* DP(NETIF_MSG_LINK, "Periodic called vars->phy_flags 0x%x speed 0x%x
12261          RESET_REG_2 0x%x\n", vars->phy_flags, vars->line_speed,
12262           REG_RD(bp, MISC_REG_RESET_REG_2)); */
12263         bnx2x_check_half_open_conn(params, vars);
12264         if (CHIP_IS_E3(bp))
12265                 bnx2x_check_over_curr(params, vars);
12266 }
12267
12268 u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
12269 {
12270         u8 phy_index;
12271         struct bnx2x_phy phy;
12272         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12273               phy_index++) {
12274                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12275                                        0, &phy) != 0) {
12276                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12277                         return 0;
12278                 }
12279
12280                 if (phy.flags & FLAGS_HW_LOCK_REQUIRED)
12281                         return 1;
12282         }
12283         return 0;
12284 }
12285
12286 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
12287                              u32 shmem_base,
12288                              u32 shmem2_base,
12289                              u8 port)
12290 {
12291         u8 phy_index, fan_failure_det_req = 0;
12292         struct bnx2x_phy phy;
12293         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12294               phy_index++) {
12295                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12296                                        port, &phy)
12297                     != 0) {
12298                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12299                         return 0;
12300                 }
12301                 fan_failure_det_req |= (phy.flags &
12302                                         FLAGS_FAN_FAILURE_DET_REQ);
12303         }
12304         return fan_failure_det_req;
12305 }
12306
12307 void bnx2x_hw_reset_phy(struct link_params *params)
12308 {
12309         u8 phy_index;
12310         struct bnx2x *bp = params->bp;
12311         bnx2x_update_mng(params, 0);
12312         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12313                        (NIG_MASK_XGXS0_LINK_STATUS |
12314                         NIG_MASK_XGXS0_LINK10G |
12315                         NIG_MASK_SERDES0_LINK_STATUS |
12316                         NIG_MASK_MI_INT));
12317
12318         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12319               phy_index++) {
12320                 if (params->phy[phy_index].hw_reset) {
12321                         params->phy[phy_index].hw_reset(
12322                                 &params->phy[phy_index],
12323                                 params);
12324                         params->phy[phy_index] = phy_null;
12325                 }
12326         }
12327 }
12328
12329 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
12330                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
12331                             u8 port)
12332 {
12333         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
12334         u32 val;
12335         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
12336         if (CHIP_IS_E3(bp)) {
12337                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
12338                                               shmem_base,
12339                                               port,
12340                                               &gpio_num,
12341                                               &gpio_port) != 0)
12342                         return;
12343         } else {
12344                 struct bnx2x_phy phy;
12345                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
12346                       phy_index++) {
12347                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
12348                                                shmem2_base, port, &phy)
12349                             != 0) {
12350                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
12351                                 return;
12352                         }
12353                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
12354                                 gpio_num = MISC_REGISTERS_GPIO_3;
12355                                 gpio_port = port;
12356                                 break;
12357                         }
12358                 }
12359         }
12360
12361         if (gpio_num == 0xff)
12362                 return;
12363
12364         /* Set GPIO3 to trigger SFP+ module insertion/removal */
12365         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
12366
12367         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
12368         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
12369         gpio_port ^= (swap_val && swap_override);
12370
12371         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
12372                 (gpio_num + (gpio_port << 2));
12373
12374         sync_offset = shmem_base +
12375                 offsetof(struct shmem_region,
12376                          dev_info.port_hw_config[port].aeu_int_mask);
12377         REG_WR(bp, sync_offset, vars->aeu_int_mask);
12378
12379         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
12380                        gpio_num, gpio_port, vars->aeu_int_mask);
12381
12382         if (port == 0)
12383                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12384         else
12385                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
12386
12387         /* Open appropriate AEU for interrupts */
12388         aeu_mask = REG_RD(bp, offset);
12389         aeu_mask |= vars->aeu_int_mask;
12390         REG_WR(bp, offset, aeu_mask);
12391
12392         /* Enable the GPIO to trigger interrupt */
12393         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12394         val |= 1 << (gpio_num + (gpio_port << 2));
12395         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12396 }