1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
12 #include "bnx2x_fw_defs.h"
14 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
20 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
22 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
23 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
28 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
29 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
30 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
40 /****************************************************************************
41 * Shared HW configuration *
42 ****************************************************************************/
43 struct shared_hw_cfg { /* NVRAM Offset */
44 /* Up to 16 bytes of NULL-terminated string */
45 u8 part_num[16]; /* 0x104 */
47 u32 config; /* 0x114 */
48 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
49 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
50 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
51 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
52 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
54 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
56 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
58 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
59 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
60 /* Whatever MFW found in NVM
61 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
62 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
63 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
64 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
65 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
66 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
67 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
68 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
69 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
70 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
71 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
72 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
73 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
74 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
76 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
77 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
78 #define SHARED_HW_CFG_LED_MAC1 0x00000000
79 #define SHARED_HW_CFG_LED_PHY1 0x00010000
80 #define SHARED_HW_CFG_LED_PHY2 0x00020000
81 #define SHARED_HW_CFG_LED_PHY3 0x00030000
82 #define SHARED_HW_CFG_LED_MAC2 0x00040000
83 #define SHARED_HW_CFG_LED_PHY4 0x00050000
84 #define SHARED_HW_CFG_LED_PHY5 0x00060000
85 #define SHARED_HW_CFG_LED_PHY6 0x00070000
86 #define SHARED_HW_CFG_LED_MAC3 0x00080000
87 #define SHARED_HW_CFG_LED_PHY7 0x00090000
88 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
89 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
90 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
91 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
92 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
95 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
96 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
97 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
98 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
99 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
100 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
101 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
102 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
104 u32 config2; /* 0x118 */
105 /* one time auto detect grace period (in sec) */
106 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
107 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
109 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
111 /* The default value for the core clock is 250MHz and it is
112 achieved by setting the clock change to 4 */
113 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
114 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
116 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
117 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
119 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
121 /* The fan failure mechanism is usually related to the PHY type
122 since the power consumption of the board is determined by the PHY.
123 Currently, fan is required for most designs with SFX7101, BCM8727
124 and BCM8481. If a fan is not required for a board which uses one
125 of those PHYs, this field should be set to "Disabled". If a fan is
126 required for a different PHY type, this option should be set to
128 The fan failure indication is expected on
130 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
131 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
132 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
133 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
134 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
136 /* Set the MDC/MDIO access for the first external phy */
137 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
138 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
139 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
140 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
141 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
142 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
143 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
145 /* Set the MDC/MDIO access for the second external phy */
146 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
147 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
148 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
149 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
150 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
151 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
152 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
153 u32 power_dissipated; /* 0x11c */
154 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
155 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
157 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
158 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
159 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
160 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
161 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
162 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
164 u32 ump_nc_si_config; /* 0x120 */
165 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
166 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
167 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
168 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
169 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
170 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
172 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
173 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
175 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
176 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
177 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
178 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
180 u32 board; /* 0x124 */
181 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
182 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
184 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
185 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
187 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
188 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
190 u32 reserved; /* 0x128 */
195 /****************************************************************************
196 * Port HW configuration *
197 ****************************************************************************/
198 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
201 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
202 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
205 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
206 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
208 u32 power_dissipated;
209 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
210 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
211 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
212 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
213 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
214 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
215 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
216 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
219 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
220 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
221 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
222 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
223 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
224 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
225 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
226 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
229 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
230 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
233 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
236 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
240 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
241 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
243 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
244 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
247 u32 Reserved0[3]; /* 0x158 */
248 /* Controls the TX laser of the SFP+ module */
249 u32 sfp_ctrl; /* 0x164 */
250 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
251 #define PORT_HW_CFG_TX_LASER_SHIFT 0
252 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
253 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
254 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
255 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
256 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
258 /* Controls the fault module LED of the SFP+ */
259 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
260 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
261 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
262 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
263 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
264 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
265 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
267 u32 Reserved01[10]; /* 0x158 */
269 u32 aeu_int_mask; /* 0x190 */
271 u32 media_type; /* 0x194 */
272 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
273 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
275 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
276 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
278 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
279 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
280 /* for external PHY, or forced mode or during AN */
281 u16 xgxs_config_rx[4]; /* 0x198 */
283 u16 xgxs_config_tx[4]; /* 0x1A0 */
285 u32 Reserved1[56]; /* 0x1A8 */
286 u32 default_cfg; /* 0x288 */
287 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
288 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
289 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
290 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
291 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
292 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
294 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
295 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
296 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
297 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
298 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
299 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
301 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
302 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
303 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
304 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
305 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
306 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
308 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
309 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
310 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
311 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
312 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
313 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
316 * When KR link is required to be set to force which is not
317 * KR-compliant, this parameter determine what is the trigger for it.
318 * When GPIO is selected, low input will force the speed. Currently
319 * default speed is 1G. In the future, it may be widen to select the
320 * forced speed in with another parameter. Note when force-1G is
321 * enabled, it override option 56: Link Speed option.
323 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
324 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
325 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
326 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
327 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
328 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
329 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
330 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
331 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
332 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
333 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
334 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
335 /* Enable to determine with which GPIO to reset the external phy */
336 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
337 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
338 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
339 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
340 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
341 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
342 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
343 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
344 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
345 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
346 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
347 /* Enable BAM on KR */
348 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
349 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
350 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
351 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
353 /* Enable Common Mode Sense */
354 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
355 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
356 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
357 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
359 u32 speed_capability_mask2; /* 0x28C */
360 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
361 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
362 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
363 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
364 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
365 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
366 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
367 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
368 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
369 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12G 0x00000080
370 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_12_DOT_5G 0x00000100
371 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_13G 0x00000200
372 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_15G 0x00000400
373 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_16G 0x00000800
375 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
376 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
377 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
378 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
379 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
380 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
381 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
382 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
383 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
384 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12G 0x00800000
385 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_12_DOT_5G 0x01000000
386 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_13G 0x02000000
387 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_15G 0x04000000
388 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_16G 0x08000000
390 /* In the case where two media types (e.g. copper and fiber) are
391 present and electrically active at the same time, PHY Selection
392 will determine which of the two PHYs will be designated as the
393 Active PHY and used for a connection to the network. */
394 u32 multi_phy_config; /* 0x290 */
395 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
396 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
397 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
398 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
399 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
400 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
401 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
403 /* When enabled, all second phy nvram parameters will be swapped
404 with the first phy parameters */
405 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
406 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
407 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
408 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
411 /* Address of the second external phy */
412 u32 external_phy_config2; /* 0x294 */
413 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
414 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
416 /* The second XGXS external PHY type */
417 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
418 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
419 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
420 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
421 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
422 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
423 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
424 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
425 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
426 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
427 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
428 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
429 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
430 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
431 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
432 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
433 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
434 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
435 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
437 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
438 8706, 8726 and 8727) not all 4 values are needed. */
439 u16 xgxs_config2_rx[4]; /* 0x296 */
440 u16 xgxs_config2_tx[4]; /* 0x2A0 */
443 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
444 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
446 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
447 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
448 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
449 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
450 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
451 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
453 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
455 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
457 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
459 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
460 /* Indicate whether to swap the external phy polarity */
461 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
462 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
463 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
465 u32 external_phy_config;
466 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
467 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
468 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
469 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
470 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
472 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
473 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
475 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
476 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
477 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
478 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
479 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
480 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
481 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
482 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
483 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
484 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
485 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
486 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
487 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
488 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
489 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
490 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
491 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
492 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
494 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
495 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
497 u32 speed_capability_mask;
498 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
499 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
500 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
501 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
502 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
503 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
504 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
505 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
506 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
507 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
508 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
509 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
510 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
511 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
512 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
514 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
515 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
516 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
517 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
518 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
519 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
520 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
521 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
522 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
523 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
524 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
525 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
526 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
527 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
528 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
535 /****************************************************************************
536 * Shared Feature configuration *
537 ****************************************************************************/
538 struct shared_feat_cfg { /* NVRAM Offset */
540 u32 config; /* 0x450 */
541 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
543 /* Use the values from options 47 and 48 instead of the HW default
545 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
546 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002
548 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
549 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
550 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
551 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
552 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
553 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
558 /****************************************************************************
559 * Port Feature configuration *
560 ****************************************************************************/
561 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
564 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
565 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
566 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
567 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
568 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
569 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
570 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
571 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
572 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
573 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
574 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
575 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
576 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
577 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
578 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
579 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
580 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
581 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
582 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
583 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
584 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
585 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
586 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
587 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
588 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
589 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
590 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
591 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
592 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
593 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
594 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
595 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
596 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
597 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
598 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
599 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
600 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000
601 #define PORT_FEATURE_EN_SIZE_SHIFT 24
602 #define PORT_FEATURE_WOL_ENABLED 0x01000000
603 #define PORT_FEATURE_MBA_ENABLED 0x02000000
604 #define PORT_FEATURE_MFW_ENABLED 0x04000000
606 /* Reserved bits: 28-29 */
607 /* Check the optic vendor via i2c against a list of approved modules
608 in a separate nvram image */
609 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
610 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
611 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000
612 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000
613 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
614 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
618 /* Default is used when driver sets to "auto" mode */
619 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
620 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
621 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
622 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
623 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
624 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
625 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
626 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
627 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
630 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
631 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
632 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
633 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
634 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
635 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
636 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
637 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
638 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
639 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
640 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
641 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
642 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
643 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
644 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
645 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
646 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
647 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
648 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
649 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
650 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
651 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
652 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
653 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
654 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
655 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
656 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
657 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
658 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
659 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
660 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
661 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
662 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
663 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
664 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
665 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
666 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
667 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
668 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
669 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
670 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
671 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
672 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
673 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
674 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
675 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
676 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
677 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
678 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
679 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
680 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
681 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
682 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
683 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
686 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
687 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
690 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
691 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
692 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
695 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
696 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
697 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
698 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
699 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
703 #define PORT_FEATURE_SMBUS_EN 0x00000001
704 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
705 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
709 u32 link_config; /* Used as HW defaults for the driver */
710 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
711 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
712 /* (forced) low speed switch (< 10G) */
713 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
714 /* (forced) high speed switch (>= 10G) */
715 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
716 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
717 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
719 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
720 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
721 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
722 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
723 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
724 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
725 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
726 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
727 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
728 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
729 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
730 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
731 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
732 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
733 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
734 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
735 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
737 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
738 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
739 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
740 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
741 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
742 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
743 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
745 /* The default for MCP link configuration,
746 uses the same defines as link_config */
747 u32 mfw_wol_link_cfg;
748 /* The default for the driver of the second external phy,
749 uses the same defines as link_config */
750 u32 link_config2; /* 0x47C */
752 /* The default for MCP of the second external phy,
753 uses the same defines as link_config */
754 u32 mfw_wol_link_cfg2; /* 0x480 */
756 u32 Reserved2[17]; /* 0x484 */
761 /****************************************************************************
762 * Device Information *
763 ****************************************************************************/
764 struct shm_dev_info { /* size */
766 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
768 struct shared_hw_cfg shared_hw_config; /* 40 */
770 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
772 struct shared_feat_cfg shared_feature_config; /* 4 */
774 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
787 #define E1_FUNC_MAX 2
788 #define E1H_FUNC_MAX 8
789 #define E2_FUNC_MAX 4 /* per path */
799 /* This value (in milliseconds) determines the frequency of the driver
800 * issuing the PULSE message code. The firmware monitors this periodic
801 * pulse to determine when to switch to an OS-absent mode. */
802 #define DRV_PULSE_PERIOD_MS 250
804 /* This value (in milliseconds) determines how long the driver should
805 * wait for an acknowledgement from the firmware before timing out. Once
806 * the firmware has timed out, the driver will assume there is no firmware
807 * running and there won't be any firmware-driver synchronization during a
809 #define FW_ACK_TIME_OUT_MS 5000
811 #define FW_ACK_POLL_TIME_MS 1
813 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
815 /* LED Blink rate that will achieve ~15.9Hz */
816 #define LED_BLINK_RATE_VAL 480
818 /****************************************************************************
819 * Driver <-> FW Mailbox *
820 ****************************************************************************/
824 /* Driver should update this field on any link change event */
826 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
827 #define LINK_STATUS_LINK_UP 0x00000001
828 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
829 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
830 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
831 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
832 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
833 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
834 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
835 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
836 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
837 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
838 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
839 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
840 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
841 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
842 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
843 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
844 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
845 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
846 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
847 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
848 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
849 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
850 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
851 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
852 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
854 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
855 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
857 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
858 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
859 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
861 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
862 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
863 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
864 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
865 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
866 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
867 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
869 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
870 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
872 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
873 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
875 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
876 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
877 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
878 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
879 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
881 #define LINK_STATUS_SERDES_LINK 0x00100000
883 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
884 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
885 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
886 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
887 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
888 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
889 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
890 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
896 /* MCP firmware does not use this field */
897 u32 ext_phy_fw_version;
905 #define DRV_MSG_CODE_MASK 0xffff0000
906 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
907 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
908 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
909 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
910 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
911 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
912 #define DRV_MSG_CODE_DCC_OK 0x30000000
913 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
914 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
915 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
916 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
917 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
918 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
919 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
920 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
922 * The optic module verification commands require bootcode
925 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
926 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
928 * The specific optic module verification command requires bootcode
931 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
932 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
934 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
935 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
936 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
937 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
938 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
939 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
940 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
941 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
942 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
944 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
949 #define FW_MSG_CODE_MASK 0xffff0000
950 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
951 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
952 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
953 /* Load common chip is supported from bc 6.0.0 */
954 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
955 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
956 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
957 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
958 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
959 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
960 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
961 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
962 #define FW_MSG_CODE_DCC_DONE 0x30100000
963 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
964 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
965 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
966 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
967 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
968 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
969 #define FW_MSG_CODE_NO_KEY 0x80f00000
970 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
971 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
972 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
973 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
974 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
975 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
976 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
977 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
978 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
980 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
981 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
982 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
983 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
985 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
990 #define DRV_PULSE_SEQ_MASK 0x00007fff
991 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
992 /* The system time is in the format of
993 * (year-2001)*12*32 + month*32 + day. */
994 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
995 /* Indicate to the firmware not to go into the
996 * OS-absent when it is not getting driver pulse.
997 * This is used for debugging as well for PXE(MBA). */
1000 #define MCP_PULSE_SEQ_MASK 0x00007fff
1001 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1002 /* Indicates to the driver not to assert due to lack
1003 * of MCP response */
1004 #define MCP_EVENT_MASK 0xffff0000
1005 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1007 u32 iscsi_boot_signature;
1008 u32 iscsi_boot_block_offset;
1011 #define DRV_STATUS_PMF 0x00000001
1012 #define DRV_STATUS_SET_MF_BW 0x00000004
1014 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1015 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1016 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1017 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1018 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1019 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1020 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1021 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1022 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1025 #define VIRT_MAC_SIGN_MASK 0xffff0000
1026 #define VIRT_MAC_SIGNATURE 0x564d0000
1032 /****************************************************************************
1033 * Management firmware state *
1034 ****************************************************************************/
1035 /* Allocate 440 bytes for management firmware */
1036 #define MGMTFW_STATE_WORD_SIZE 110
1038 struct mgmtfw_state {
1039 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1043 /****************************************************************************
1044 * Multi-Function configuration *
1045 ****************************************************************************/
1046 struct shared_mf_cfg {
1049 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1051 #define SHARED_MF_CLP_EXIT 0x00000001
1053 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1057 struct port_mf_cfg {
1059 u32 dynamic_cfg; /* device control channel */
1060 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1061 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1062 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1068 struct func_mf_cfg {
1072 /* function 0 of each port cannot be hidden */
1073 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1075 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
1076 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1077 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1078 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1079 #define FUNC_MF_CFG_PROTOCOL_DEFAULT\
1080 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1082 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1085 /* 0 - low priority, 3 - high priority */
1086 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1087 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1088 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1091 /* value range - 0..100, increments in 100Mbps */
1092 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1093 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1094 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1095 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1096 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1097 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1099 u32 mac_upper; /* MAC */
1100 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1101 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1102 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1104 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1106 u32 e1hov_tag; /* VNI */
1107 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1108 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1109 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1115 /* This structure is not applicable and should not be accessed on 57711 */
1116 struct func_ext_cfg {
1118 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1119 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1120 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1121 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1122 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1123 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1125 u32 iscsi_mac_addr_upper;
1126 u32 iscsi_mac_addr_lower;
1128 u32 fcoe_mac_addr_upper;
1129 u32 fcoe_mac_addr_lower;
1131 u32 fcoe_wwn_port_name_upper;
1132 u32 fcoe_wwn_port_name_lower;
1134 u32 fcoe_wwn_node_name_upper;
1135 u32 fcoe_wwn_node_name_lower;
1138 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1139 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1140 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1141 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1142 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1147 struct shared_mf_cfg shared_mf_config;
1148 struct port_mf_cfg port_mf_config[PORT_MAX];
1149 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
1151 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX];
1155 /****************************************************************************
1156 * Shared Memory Region *
1157 ****************************************************************************/
1158 struct shmem_region { /* SharedMem Offset (size) */
1160 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1161 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1162 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1164 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1165 #define SHR_MEM_VALIDITY_MB 0x00200000
1166 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1167 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1168 /* One licensing bit should be set */
1169 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1170 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1171 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1172 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1174 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1175 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1176 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1177 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1178 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1179 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1181 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1183 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1185 /* FW information (for internal FW use) */
1186 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1187 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1189 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1190 struct drv_func_mb func_mb[]; /* 0x684
1191 (44*2/4/8=0x58/0xb0/0x160) */
1193 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1204 struct fw_flr_ack ack;
1207 /**** SUPPORT FOR SHMEM ARRRAYS ***
1208 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1209 * define arrays with storage types smaller then unsigned dwords.
1210 * The macros below add generic support for SHMEM arrays with numeric elements
1211 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1212 * array with individual bit-filed elements accessed using shifts and masks.
1216 /* eb is the bitwidth of a single element */
1217 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1218 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1220 /* the bit-position macro allows the used to flip the order of the arrays
1221 * elements on a per byte or word boundary.
1223 * example: an array with 8 entries each 4 bit wide. This array will fit into
1224 * a single dword. The diagrmas below show the array order of the nibbles.
1226 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1229 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1232 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1235 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1238 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1241 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1244 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1245 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1246 (((i)%((fb)/(eb))) * (eb)))
1248 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1249 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1250 SHMEM_ARRAY_MASK(eb))
1252 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1254 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1255 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1256 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1257 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1261 /****START OF DCBX STRUCTURES DECLARATIONS****/
1262 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1263 #define DCBX_PRI_PG_BITWIDTH 4
1264 #define DCBX_PRI_PG_FBITS 8
1265 #define DCBX_PRI_PG_GET(a, i) \
1266 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1267 #define DCBX_PRI_PG_SET(a, i, val) \
1268 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1269 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1270 #define DCBX_BW_PG_BITWIDTH 8
1271 #define DCBX_PG_BW_GET(a, i) \
1272 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1273 #define DCBX_PG_BW_SET(a, i, val) \
1274 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1275 #define DCBX_STRICT_PRI_PG 15
1276 #define DCBX_MAX_APP_PROTOCOL 16
1277 #define FCOE_APP_IDX 0
1278 #define ISCSI_APP_IDX 1
1279 #define PREDEFINED_APP_IDX_MAX 2
1281 struct dcbx_ets_feature {
1287 struct dcbx_pfc_feature {
1290 #define DCBX_PFC_PRI_0 0x01
1291 #define DCBX_PFC_PRI_1 0x02
1292 #define DCBX_PFC_PRI_2 0x04
1293 #define DCBX_PFC_PRI_3 0x08
1294 #define DCBX_PFC_PRI_4 0x10
1295 #define DCBX_PFC_PRI_5 0x20
1296 #define DCBX_PFC_PRI_6 0x40
1297 #define DCBX_PFC_PRI_7 0x80
1301 #elif defined(__LITTLE_ENDIAN)
1306 #define DCBX_PFC_PRI_0 0x01
1307 #define DCBX_PFC_PRI_1 0x02
1308 #define DCBX_PFC_PRI_2 0x04
1309 #define DCBX_PFC_PRI_3 0x08
1310 #define DCBX_PFC_PRI_4 0x10
1311 #define DCBX_PFC_PRI_5 0x20
1312 #define DCBX_PFC_PRI_6 0x40
1313 #define DCBX_PFC_PRI_7 0x80
1317 struct dcbx_app_priority_entry {
1322 #define DCBX_APP_ENTRY_VALID 0x01
1323 #define DCBX_APP_ENTRY_SF_MASK 0x30
1324 #define DCBX_APP_ENTRY_SF_SHIFT 4
1325 #define DCBX_APP_SF_ETH_TYPE 0x10
1326 #define DCBX_APP_SF_PORT 0x20
1327 #elif defined(__LITTLE_ENDIAN)
1329 #define DCBX_APP_ENTRY_VALID 0x01
1330 #define DCBX_APP_ENTRY_SF_MASK 0x30
1331 #define DCBX_APP_ENTRY_SF_SHIFT 4
1332 #define DCBX_APP_SF_ETH_TYPE 0x10
1333 #define DCBX_APP_SF_PORT 0x20
1339 struct dcbx_app_priority_feature {
1345 #elif defined(__LITTLE_ENDIAN)
1351 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1354 struct dcbx_features {
1355 struct dcbx_ets_feature ets;
1356 struct dcbx_pfc_feature pfc;
1357 struct dcbx_app_priority_feature app;
1360 struct lldp_params {
1362 u8 msg_fast_tx_interval;
1366 #define LLDP_TX_ONLY 0x01
1367 #define LLDP_RX_ONLY 0x02
1368 #define LLDP_TX_RX 0x03
1369 #define LLDP_DISABLED 0x04
1374 #elif defined(__LITTLE_ENDIAN)
1376 #define LLDP_TX_ONLY 0x01
1377 #define LLDP_RX_ONLY 0x02
1378 #define LLDP_TX_RX 0x03
1379 #define LLDP_DISABLED 0x04
1382 u8 msg_fast_tx_interval;
1388 #define REM_CHASSIS_ID_STAT_LEN 4
1389 #define REM_PORT_ID_STAT_LEN 4
1390 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1391 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1394 struct lldp_dcbx_stat {
1395 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1396 #define LOCAL_PORT_ID_STAT_LEN 2
1397 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1398 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1399 u32 num_tx_dcbx_pkts;
1400 u32 num_rx_dcbx_pkts;
1403 struct lldp_admin_mib {
1405 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1406 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1407 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1408 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1409 #define DCBX_ETS_RECO_VALID 0x00000010
1410 #define DCBX_ETS_WILLING 0x00000020
1411 #define DCBX_PFC_WILLING 0x00000040
1412 #define DCBX_APP_WILLING 0x00000080
1413 #define DCBX_VERSION_CEE 0x00000100
1414 #define DCBX_VERSION_IEEE 0x00000200
1415 #define DCBX_DCBX_ENABLED 0x00000400
1416 #define DCBX_CEE_VERSION_MASK 0x0000f000
1417 #define DCBX_CEE_VERSION_SHIFT 12
1418 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1419 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1420 struct dcbx_features features;
1423 struct lldp_remote_mib {
1426 #define DCBX_ETS_TLV_RX 0x00000001
1427 #define DCBX_PFC_TLV_RX 0x00000002
1428 #define DCBX_APP_TLV_RX 0x00000004
1429 #define DCBX_ETS_RX_ERROR 0x00000010
1430 #define DCBX_PFC_RX_ERROR 0x00000020
1431 #define DCBX_APP_RX_ERROR 0x00000040
1432 #define DCBX_ETS_REM_WILLING 0x00000100
1433 #define DCBX_PFC_REM_WILLING 0x00000200
1434 #define DCBX_APP_REM_WILLING 0x00000400
1435 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1436 struct dcbx_features features;
1440 struct lldp_local_mib {
1443 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1444 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1445 #define DCBX_LOCAL_APP_ERROR 0x00000004
1446 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1447 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1448 struct dcbx_features features;
1451 /***END OF DCBX STRUCTURES DECLARATIONS***/
1453 struct shmem2_region {
1458 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1459 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1460 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1461 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1462 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1463 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1464 #define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
1465 u32 ext_phy_fw_version2[PORT_MAX];
1467 * For backwards compatibility, if the mf_cfg_addr does not exist
1468 * (the size filed is smaller than 0xc) the mf_cfg resides at the
1469 * end of struct shmem_region
1472 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1474 struct fw_flr_mb flr_mb;
1475 u32 dcbx_lldp_params_offset;
1476 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
1477 u32 dcbx_neg_res_offset;
1478 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
1479 u32 dcbx_remote_mib_offset;
1480 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
1482 * The other shmemX_base_addr holds the other path's shmem address
1483 * required for example in case of common phy init, or for path1 to know
1484 * the address of mcp debug trace which is located in offset from shmem
1487 u32 other_shmem_base_addr;
1488 u32 other_shmem2_base_addr;
1489 u32 reserved1[E2_VF_MAX / 32];
1490 u32 reserved2[E2_FUNC_MAX][E2_VF_MAX / 32];
1491 u32 dcbx_lldp_dcbx_stat_offset;
1492 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
1497 u32 rx_stat_ifhcinoctets;
1498 u32 rx_stat_ifhcinbadoctets;
1499 u32 rx_stat_etherstatsfragments;
1500 u32 rx_stat_ifhcinucastpkts;
1501 u32 rx_stat_ifhcinmulticastpkts;
1502 u32 rx_stat_ifhcinbroadcastpkts;
1503 u32 rx_stat_dot3statsfcserrors;
1504 u32 rx_stat_dot3statsalignmenterrors;
1505 u32 rx_stat_dot3statscarriersenseerrors;
1506 u32 rx_stat_xonpauseframesreceived;
1507 u32 rx_stat_xoffpauseframesreceived;
1508 u32 rx_stat_maccontrolframesreceived;
1509 u32 rx_stat_xoffstateentered;
1510 u32 rx_stat_dot3statsframestoolong;
1511 u32 rx_stat_etherstatsjabbers;
1512 u32 rx_stat_etherstatsundersizepkts;
1513 u32 rx_stat_etherstatspkts64octets;
1514 u32 rx_stat_etherstatspkts65octetsto127octets;
1515 u32 rx_stat_etherstatspkts128octetsto255octets;
1516 u32 rx_stat_etherstatspkts256octetsto511octets;
1517 u32 rx_stat_etherstatspkts512octetsto1023octets;
1518 u32 rx_stat_etherstatspkts1024octetsto1522octets;
1519 u32 rx_stat_etherstatspktsover1522octets;
1521 u32 rx_stat_falsecarriererrors;
1523 u32 tx_stat_ifhcoutoctets;
1524 u32 tx_stat_ifhcoutbadoctets;
1525 u32 tx_stat_etherstatscollisions;
1526 u32 tx_stat_outxonsent;
1527 u32 tx_stat_outxoffsent;
1528 u32 tx_stat_flowcontroldone;
1529 u32 tx_stat_dot3statssinglecollisionframes;
1530 u32 tx_stat_dot3statsmultiplecollisionframes;
1531 u32 tx_stat_dot3statsdeferredtransmissions;
1532 u32 tx_stat_dot3statsexcessivecollisions;
1533 u32 tx_stat_dot3statslatecollisions;
1534 u32 tx_stat_ifhcoutucastpkts;
1535 u32 tx_stat_ifhcoutmulticastpkts;
1536 u32 tx_stat_ifhcoutbroadcastpkts;
1537 u32 tx_stat_etherstatspkts64octets;
1538 u32 tx_stat_etherstatspkts65octetsto127octets;
1539 u32 tx_stat_etherstatspkts128octetsto255octets;
1540 u32 tx_stat_etherstatspkts256octetsto511octets;
1541 u32 tx_stat_etherstatspkts512octetsto1023octets;
1542 u32 tx_stat_etherstatspkts1024octetsto1522octets;
1543 u32 tx_stat_etherstatspktsover1522octets;
1544 u32 tx_stat_dot3statsinternalmactransmiterrors;
1548 struct bmac1_stats {
1549 u32 tx_stat_gtpkt_lo;
1550 u32 tx_stat_gtpkt_hi;
1551 u32 tx_stat_gtxpf_lo;
1552 u32 tx_stat_gtxpf_hi;
1553 u32 tx_stat_gtfcs_lo;
1554 u32 tx_stat_gtfcs_hi;
1555 u32 tx_stat_gtmca_lo;
1556 u32 tx_stat_gtmca_hi;
1557 u32 tx_stat_gtbca_lo;
1558 u32 tx_stat_gtbca_hi;
1559 u32 tx_stat_gtfrg_lo;
1560 u32 tx_stat_gtfrg_hi;
1561 u32 tx_stat_gtovr_lo;
1562 u32 tx_stat_gtovr_hi;
1563 u32 tx_stat_gt64_lo;
1564 u32 tx_stat_gt64_hi;
1565 u32 tx_stat_gt127_lo;
1566 u32 tx_stat_gt127_hi;
1567 u32 tx_stat_gt255_lo;
1568 u32 tx_stat_gt255_hi;
1569 u32 tx_stat_gt511_lo;
1570 u32 tx_stat_gt511_hi;
1571 u32 tx_stat_gt1023_lo;
1572 u32 tx_stat_gt1023_hi;
1573 u32 tx_stat_gt1518_lo;
1574 u32 tx_stat_gt1518_hi;
1575 u32 tx_stat_gt2047_lo;
1576 u32 tx_stat_gt2047_hi;
1577 u32 tx_stat_gt4095_lo;
1578 u32 tx_stat_gt4095_hi;
1579 u32 tx_stat_gt9216_lo;
1580 u32 tx_stat_gt9216_hi;
1581 u32 tx_stat_gt16383_lo;
1582 u32 tx_stat_gt16383_hi;
1583 u32 tx_stat_gtmax_lo;
1584 u32 tx_stat_gtmax_hi;
1585 u32 tx_stat_gtufl_lo;
1586 u32 tx_stat_gtufl_hi;
1587 u32 tx_stat_gterr_lo;
1588 u32 tx_stat_gterr_hi;
1589 u32 tx_stat_gtbyt_lo;
1590 u32 tx_stat_gtbyt_hi;
1592 u32 rx_stat_gr64_lo;
1593 u32 rx_stat_gr64_hi;
1594 u32 rx_stat_gr127_lo;
1595 u32 rx_stat_gr127_hi;
1596 u32 rx_stat_gr255_lo;
1597 u32 rx_stat_gr255_hi;
1598 u32 rx_stat_gr511_lo;
1599 u32 rx_stat_gr511_hi;
1600 u32 rx_stat_gr1023_lo;
1601 u32 rx_stat_gr1023_hi;
1602 u32 rx_stat_gr1518_lo;
1603 u32 rx_stat_gr1518_hi;
1604 u32 rx_stat_gr2047_lo;
1605 u32 rx_stat_gr2047_hi;
1606 u32 rx_stat_gr4095_lo;
1607 u32 rx_stat_gr4095_hi;
1608 u32 rx_stat_gr9216_lo;
1609 u32 rx_stat_gr9216_hi;
1610 u32 rx_stat_gr16383_lo;
1611 u32 rx_stat_gr16383_hi;
1612 u32 rx_stat_grmax_lo;
1613 u32 rx_stat_grmax_hi;
1614 u32 rx_stat_grpkt_lo;
1615 u32 rx_stat_grpkt_hi;
1616 u32 rx_stat_grfcs_lo;
1617 u32 rx_stat_grfcs_hi;
1618 u32 rx_stat_grmca_lo;
1619 u32 rx_stat_grmca_hi;
1620 u32 rx_stat_grbca_lo;
1621 u32 rx_stat_grbca_hi;
1622 u32 rx_stat_grxcf_lo;
1623 u32 rx_stat_grxcf_hi;
1624 u32 rx_stat_grxpf_lo;
1625 u32 rx_stat_grxpf_hi;
1626 u32 rx_stat_grxuo_lo;
1627 u32 rx_stat_grxuo_hi;
1628 u32 rx_stat_grjbr_lo;
1629 u32 rx_stat_grjbr_hi;
1630 u32 rx_stat_grovr_lo;
1631 u32 rx_stat_grovr_hi;
1632 u32 rx_stat_grflr_lo;
1633 u32 rx_stat_grflr_hi;
1634 u32 rx_stat_grmeg_lo;
1635 u32 rx_stat_grmeg_hi;
1636 u32 rx_stat_grmeb_lo;
1637 u32 rx_stat_grmeb_hi;
1638 u32 rx_stat_grbyt_lo;
1639 u32 rx_stat_grbyt_hi;
1640 u32 rx_stat_grund_lo;
1641 u32 rx_stat_grund_hi;
1642 u32 rx_stat_grfrg_lo;
1643 u32 rx_stat_grfrg_hi;
1644 u32 rx_stat_grerb_lo;
1645 u32 rx_stat_grerb_hi;
1646 u32 rx_stat_grfre_lo;
1647 u32 rx_stat_grfre_hi;
1648 u32 rx_stat_gripj_lo;
1649 u32 rx_stat_gripj_hi;
1652 struct bmac2_stats {
1653 u32 tx_stat_gtpk_lo; /* gtpok */
1654 u32 tx_stat_gtpk_hi; /* gtpok */
1655 u32 tx_stat_gtxpf_lo; /* gtpf */
1656 u32 tx_stat_gtxpf_hi; /* gtpf */
1657 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
1658 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
1659 u32 tx_stat_gtfcs_lo;
1660 u32 tx_stat_gtfcs_hi;
1661 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
1662 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
1663 u32 tx_stat_gtmca_lo;
1664 u32 tx_stat_gtmca_hi;
1665 u32 tx_stat_gtbca_lo;
1666 u32 tx_stat_gtbca_hi;
1667 u32 tx_stat_gtovr_lo;
1668 u32 tx_stat_gtovr_hi;
1669 u32 tx_stat_gtfrg_lo;
1670 u32 tx_stat_gtfrg_hi;
1671 u32 tx_stat_gtpkt1_lo; /* gtpkt */
1672 u32 tx_stat_gtpkt1_hi; /* gtpkt */
1673 u32 tx_stat_gt64_lo;
1674 u32 tx_stat_gt64_hi;
1675 u32 tx_stat_gt127_lo;
1676 u32 tx_stat_gt127_hi;
1677 u32 tx_stat_gt255_lo;
1678 u32 tx_stat_gt255_hi;
1679 u32 tx_stat_gt511_lo;
1680 u32 tx_stat_gt511_hi;
1681 u32 tx_stat_gt1023_lo;
1682 u32 tx_stat_gt1023_hi;
1683 u32 tx_stat_gt1518_lo;
1684 u32 tx_stat_gt1518_hi;
1685 u32 tx_stat_gt2047_lo;
1686 u32 tx_stat_gt2047_hi;
1687 u32 tx_stat_gt4095_lo;
1688 u32 tx_stat_gt4095_hi;
1689 u32 tx_stat_gt9216_lo;
1690 u32 tx_stat_gt9216_hi;
1691 u32 tx_stat_gt16383_lo;
1692 u32 tx_stat_gt16383_hi;
1693 u32 tx_stat_gtmax_lo;
1694 u32 tx_stat_gtmax_hi;
1695 u32 tx_stat_gtufl_lo;
1696 u32 tx_stat_gtufl_hi;
1697 u32 tx_stat_gterr_lo;
1698 u32 tx_stat_gterr_hi;
1699 u32 tx_stat_gtbyt_lo;
1700 u32 tx_stat_gtbyt_hi;
1702 u32 rx_stat_gr64_lo;
1703 u32 rx_stat_gr64_hi;
1704 u32 rx_stat_gr127_lo;
1705 u32 rx_stat_gr127_hi;
1706 u32 rx_stat_gr255_lo;
1707 u32 rx_stat_gr255_hi;
1708 u32 rx_stat_gr511_lo;
1709 u32 rx_stat_gr511_hi;
1710 u32 rx_stat_gr1023_lo;
1711 u32 rx_stat_gr1023_hi;
1712 u32 rx_stat_gr1518_lo;
1713 u32 rx_stat_gr1518_hi;
1714 u32 rx_stat_gr2047_lo;
1715 u32 rx_stat_gr2047_hi;
1716 u32 rx_stat_gr4095_lo;
1717 u32 rx_stat_gr4095_hi;
1718 u32 rx_stat_gr9216_lo;
1719 u32 rx_stat_gr9216_hi;
1720 u32 rx_stat_gr16383_lo;
1721 u32 rx_stat_gr16383_hi;
1722 u32 rx_stat_grmax_lo;
1723 u32 rx_stat_grmax_hi;
1724 u32 rx_stat_grpkt_lo;
1725 u32 rx_stat_grpkt_hi;
1726 u32 rx_stat_grfcs_lo;
1727 u32 rx_stat_grfcs_hi;
1728 u32 rx_stat_gruca_lo;
1729 u32 rx_stat_gruca_hi;
1730 u32 rx_stat_grmca_lo;
1731 u32 rx_stat_grmca_hi;
1732 u32 rx_stat_grbca_lo;
1733 u32 rx_stat_grbca_hi;
1734 u32 rx_stat_grxpf_lo; /* grpf */
1735 u32 rx_stat_grxpf_hi; /* grpf */
1736 u32 rx_stat_grpp_lo;
1737 u32 rx_stat_grpp_hi;
1738 u32 rx_stat_grxuo_lo; /* gruo */
1739 u32 rx_stat_grxuo_hi; /* gruo */
1740 u32 rx_stat_grjbr_lo;
1741 u32 rx_stat_grjbr_hi;
1742 u32 rx_stat_grovr_lo;
1743 u32 rx_stat_grovr_hi;
1744 u32 rx_stat_grxcf_lo; /* grcf */
1745 u32 rx_stat_grxcf_hi; /* grcf */
1746 u32 rx_stat_grflr_lo;
1747 u32 rx_stat_grflr_hi;
1748 u32 rx_stat_grpok_lo;
1749 u32 rx_stat_grpok_hi;
1750 u32 rx_stat_grmeg_lo;
1751 u32 rx_stat_grmeg_hi;
1752 u32 rx_stat_grmeb_lo;
1753 u32 rx_stat_grmeb_hi;
1754 u32 rx_stat_grbyt_lo;
1755 u32 rx_stat_grbyt_hi;
1756 u32 rx_stat_grund_lo;
1757 u32 rx_stat_grund_hi;
1758 u32 rx_stat_grfrg_lo;
1759 u32 rx_stat_grfrg_hi;
1760 u32 rx_stat_grerb_lo; /* grerrbyt */
1761 u32 rx_stat_grerb_hi; /* grerrbyt */
1762 u32 rx_stat_grfre_lo; /* grfrerr */
1763 u32 rx_stat_grfre_hi; /* grfrerr */
1764 u32 rx_stat_gripj_lo;
1765 u32 rx_stat_gripj_hi;
1769 struct emac_stats emac_stats;
1770 struct bmac1_stats bmac1_stats;
1771 struct bmac2_stats bmac2_stats;
1777 u32 rx_stat_ifhcinbadoctets_hi;
1778 u32 rx_stat_ifhcinbadoctets_lo;
1780 /* out_bad_octets */
1781 u32 tx_stat_ifhcoutbadoctets_hi;
1782 u32 tx_stat_ifhcoutbadoctets_lo;
1784 /* crc_receive_errors */
1785 u32 rx_stat_dot3statsfcserrors_hi;
1786 u32 rx_stat_dot3statsfcserrors_lo;
1787 /* alignment_errors */
1788 u32 rx_stat_dot3statsalignmenterrors_hi;
1789 u32 rx_stat_dot3statsalignmenterrors_lo;
1790 /* carrier_sense_errors */
1791 u32 rx_stat_dot3statscarriersenseerrors_hi;
1792 u32 rx_stat_dot3statscarriersenseerrors_lo;
1793 /* false_carrier_detections */
1794 u32 rx_stat_falsecarriererrors_hi;
1795 u32 rx_stat_falsecarriererrors_lo;
1797 /* runt_packets_received */
1798 u32 rx_stat_etherstatsundersizepkts_hi;
1799 u32 rx_stat_etherstatsundersizepkts_lo;
1800 /* jabber_packets_received */
1801 u32 rx_stat_dot3statsframestoolong_hi;
1802 u32 rx_stat_dot3statsframestoolong_lo;
1804 /* error_runt_packets_received */
1805 u32 rx_stat_etherstatsfragments_hi;
1806 u32 rx_stat_etherstatsfragments_lo;
1807 /* error_jabber_packets_received */
1808 u32 rx_stat_etherstatsjabbers_hi;
1809 u32 rx_stat_etherstatsjabbers_lo;
1811 /* control_frames_received */
1812 u32 rx_stat_maccontrolframesreceived_hi;
1813 u32 rx_stat_maccontrolframesreceived_lo;
1814 u32 rx_stat_bmac_xpf_hi;
1815 u32 rx_stat_bmac_xpf_lo;
1816 u32 rx_stat_bmac_xcf_hi;
1817 u32 rx_stat_bmac_xcf_lo;
1819 /* xoff_state_entered */
1820 u32 rx_stat_xoffstateentered_hi;
1821 u32 rx_stat_xoffstateentered_lo;
1822 /* pause_xon_frames_received */
1823 u32 rx_stat_xonpauseframesreceived_hi;
1824 u32 rx_stat_xonpauseframesreceived_lo;
1825 /* pause_xoff_frames_received */
1826 u32 rx_stat_xoffpauseframesreceived_hi;
1827 u32 rx_stat_xoffpauseframesreceived_lo;
1828 /* pause_xon_frames_transmitted */
1829 u32 tx_stat_outxonsent_hi;
1830 u32 tx_stat_outxonsent_lo;
1831 /* pause_xoff_frames_transmitted */
1832 u32 tx_stat_outxoffsent_hi;
1833 u32 tx_stat_outxoffsent_lo;
1834 /* flow_control_done */
1835 u32 tx_stat_flowcontroldone_hi;
1836 u32 tx_stat_flowcontroldone_lo;
1838 /* ether_stats_collisions */
1839 u32 tx_stat_etherstatscollisions_hi;
1840 u32 tx_stat_etherstatscollisions_lo;
1841 /* single_collision_transmit_frames */
1842 u32 tx_stat_dot3statssinglecollisionframes_hi;
1843 u32 tx_stat_dot3statssinglecollisionframes_lo;
1844 /* multiple_collision_transmit_frames */
1845 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
1846 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
1847 /* deferred_transmissions */
1848 u32 tx_stat_dot3statsdeferredtransmissions_hi;
1849 u32 tx_stat_dot3statsdeferredtransmissions_lo;
1850 /* excessive_collision_frames */
1851 u32 tx_stat_dot3statsexcessivecollisions_hi;
1852 u32 tx_stat_dot3statsexcessivecollisions_lo;
1853 /* late_collision_frames */
1854 u32 tx_stat_dot3statslatecollisions_hi;
1855 u32 tx_stat_dot3statslatecollisions_lo;
1857 /* frames_transmitted_64_bytes */
1858 u32 tx_stat_etherstatspkts64octets_hi;
1859 u32 tx_stat_etherstatspkts64octets_lo;
1860 /* frames_transmitted_65_127_bytes */
1861 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
1862 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
1863 /* frames_transmitted_128_255_bytes */
1864 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
1865 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
1866 /* frames_transmitted_256_511_bytes */
1867 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
1868 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
1869 /* frames_transmitted_512_1023_bytes */
1870 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
1871 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
1872 /* frames_transmitted_1024_1522_bytes */
1873 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
1874 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
1875 /* frames_transmitted_1523_9022_bytes */
1876 u32 tx_stat_etherstatspktsover1522octets_hi;
1877 u32 tx_stat_etherstatspktsover1522octets_lo;
1878 u32 tx_stat_bmac_2047_hi;
1879 u32 tx_stat_bmac_2047_lo;
1880 u32 tx_stat_bmac_4095_hi;
1881 u32 tx_stat_bmac_4095_lo;
1882 u32 tx_stat_bmac_9216_hi;
1883 u32 tx_stat_bmac_9216_lo;
1884 u32 tx_stat_bmac_16383_hi;
1885 u32 tx_stat_bmac_16383_lo;
1887 /* internal_mac_transmit_errors */
1888 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
1889 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
1891 /* if_out_discards */
1892 u32 tx_stat_bmac_ufl_hi;
1893 u32 tx_stat_bmac_ufl_lo;
1897 #define MAC_STX_IDX_MAX 2
1899 struct host_port_stats {
1900 u32 host_port_stats_start;
1902 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1907 u32 host_port_stats_end;
1911 struct host_func_stats {
1912 u32 host_func_stats_start;
1914 u32 total_bytes_received_hi;
1915 u32 total_bytes_received_lo;
1917 u32 total_bytes_transmitted_hi;
1918 u32 total_bytes_transmitted_lo;
1920 u32 total_unicast_packets_received_hi;
1921 u32 total_unicast_packets_received_lo;
1923 u32 total_multicast_packets_received_hi;
1924 u32 total_multicast_packets_received_lo;
1926 u32 total_broadcast_packets_received_hi;
1927 u32 total_broadcast_packets_received_lo;
1929 u32 total_unicast_packets_transmitted_hi;
1930 u32 total_unicast_packets_transmitted_lo;
1932 u32 total_multicast_packets_transmitted_hi;
1933 u32 total_multicast_packets_transmitted_lo;
1935 u32 total_broadcast_packets_transmitted_hi;
1936 u32 total_broadcast_packets_transmitted_lo;
1938 u32 valid_bytes_received_hi;
1939 u32 valid_bytes_received_lo;
1941 u32 host_func_stats_end;
1945 #define BCM_5710_FW_MAJOR_VERSION 6
1946 #define BCM_5710_FW_MINOR_VERSION 2
1947 #define BCM_5710_FW_REVISION_VERSION 9
1948 #define BCM_5710_FW_ENGINEERING_VERSION 0
1949 #define BCM_5710_FW_COMPILE_FLAGS 1
1955 struct atten_sp_status_block {
1957 __le32 attn_bits_ack;
1960 __le16 attn_bits_index;
1966 * common data for all protocols
1968 struct doorbell_hdr {
1970 #define DOORBELL_HDR_RX (0x1<<0)
1971 #define DOORBELL_HDR_RX_SHIFT 0
1972 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
1973 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1974 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
1975 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1976 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
1977 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1981 * doorbell message sent to the chip
1984 #if defined(__BIG_ENDIAN)
1987 struct doorbell_hdr header;
1988 #elif defined(__LITTLE_ENDIAN)
1989 struct doorbell_hdr header;
1997 * doorbell message sent to the chip
1999 struct doorbell_set_prod {
2000 #if defined(__BIG_ENDIAN)
2003 struct doorbell_hdr header;
2004 #elif defined(__LITTLE_ENDIAN)
2005 struct doorbell_hdr header;
2013 * 3 lines. status block
2015 struct hc_status_block_e1x {
2016 __le16 index_values[HC_SB_MAX_INDICES_E1X];
2017 __le16 running_index[HC_SB_MAX_SM];
2024 struct host_hc_status_block_e1x {
2025 struct hc_status_block_e1x sb;
2030 * 3 lines. status block
2032 struct hc_status_block_e2 {
2033 __le16 index_values[HC_SB_MAX_INDICES_E2];
2034 __le16 running_index[HC_SB_MAX_SM];
2041 struct host_hc_status_block_e2 {
2042 struct hc_status_block_e2 sb;
2047 * 5 lines. slow-path status block
2049 struct hc_sp_status_block {
2050 __le16 index_values[HC_SP_SB_MAX_INDICES];
2051 __le16 running_index;
2059 struct host_sp_status_block {
2060 struct atten_sp_status_block atten_status_block;
2061 struct hc_sp_status_block sp_sb;
2066 * IGU driver acknowledgment register
2068 struct igu_ack_register {
2069 #if defined(__BIG_ENDIAN)
2070 u16 sb_id_and_flags;
2071 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2072 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2073 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2074 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2075 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2076 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2077 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2078 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2079 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2080 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2081 u16 status_block_index;
2082 #elif defined(__LITTLE_ENDIAN)
2083 u16 status_block_index;
2084 u16 sb_id_and_flags;
2085 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2086 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2087 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2088 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2089 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2090 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2091 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2092 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2093 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2094 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2100 * IGU driver acknowledgement register
2102 struct igu_backward_compatible {
2103 u32 sb_id_and_flags;
2104 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
2105 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
2106 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
2107 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
2108 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
2109 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
2110 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
2111 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
2112 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
2113 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
2114 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
2115 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
2121 * IGU driver acknowledgement register
2123 struct igu_regular {
2124 u32 sb_id_and_flags;
2125 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
2126 #define IGU_REGULAR_SB_INDEX_SHIFT 0
2127 #define IGU_REGULAR_RESERVED0 (0x1<<20)
2128 #define IGU_REGULAR_RESERVED0_SHIFT 20
2129 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
2130 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
2131 #define IGU_REGULAR_BUPDATE (0x1<<24)
2132 #define IGU_REGULAR_BUPDATE_SHIFT 24
2133 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
2134 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
2135 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
2136 #define IGU_REGULAR_RESERVED_1_SHIFT 27
2137 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
2138 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
2139 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
2140 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
2141 #define IGU_REGULAR_BCLEANUP (0x1<<31)
2142 #define IGU_REGULAR_BCLEANUP_SHIFT 31
2147 * IGU driver acknowledgement register
2149 union igu_consprod_reg {
2150 struct igu_regular regular;
2151 struct igu_backward_compatible backward_compatible;
2156 * Control register for the IGU command register
2158 struct igu_ctrl_reg {
2160 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
2161 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
2162 #define IGU_CTRL_REG_FID (0x7F<<12)
2163 #define IGU_CTRL_REG_FID_SHIFT 12
2164 #define IGU_CTRL_REG_RESERVED (0x1<<19)
2165 #define IGU_CTRL_REG_RESERVED_SHIFT 19
2166 #define IGU_CTRL_REG_TYPE (0x1<<20)
2167 #define IGU_CTRL_REG_TYPE_SHIFT 20
2168 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
2169 #define IGU_CTRL_REG_UNUSED_SHIFT 21
2174 * Parser parsing flags field
2176 struct parsing_flags {
2178 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
2179 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
2180 #define PARSING_FLAGS_VLAN (0x1<<1)
2181 #define PARSING_FLAGS_VLAN_SHIFT 1
2182 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
2183 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
2184 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
2185 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
2186 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
2187 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
2188 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
2189 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
2190 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
2191 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
2192 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
2193 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
2194 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
2195 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
2196 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
2197 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
2198 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
2199 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
2200 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
2201 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
2202 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
2203 #define PARSING_FLAGS_RESERVED0_SHIFT 14
2214 * dmae command structure
2216 struct dmae_command {
2218 #define DMAE_COMMAND_SRC (0x1<<0)
2219 #define DMAE_COMMAND_SRC_SHIFT 0
2220 #define DMAE_COMMAND_DST (0x3<<1)
2221 #define DMAE_COMMAND_DST_SHIFT 1
2222 #define DMAE_COMMAND_C_DST (0x1<<3)
2223 #define DMAE_COMMAND_C_DST_SHIFT 3
2224 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2225 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2226 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2227 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2228 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2229 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2230 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2231 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2232 #define DMAE_COMMAND_PORT (0x1<<11)
2233 #define DMAE_COMMAND_PORT_SHIFT 11
2234 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2235 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2236 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2237 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2238 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2239 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2240 #define DMAE_COMMAND_E1HVN (0x3<<15)
2241 #define DMAE_COMMAND_E1HVN_SHIFT 15
2242 #define DMAE_COMMAND_DST_VN (0x3<<17)
2243 #define DMAE_COMMAND_DST_VN_SHIFT 17
2244 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2245 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2246 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2247 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2248 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2249 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2254 #if defined(__BIG_ENDIAN)
2257 #elif defined(__LITTLE_ENDIAN)
2266 #if defined(__BIG_ENDIAN)
2269 #elif defined(__LITTLE_ENDIAN)
2273 #if defined(__BIG_ENDIAN)
2276 #elif defined(__LITTLE_ENDIAN)
2280 #if defined(__BIG_ENDIAN)
2283 #elif defined(__LITTLE_ENDIAN)
2290 struct double_regpair {
2299 * SDM operation gen command (generate aggregative interrupt)
2303 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
2304 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
2305 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
2306 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
2307 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
2308 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
2309 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
2310 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
2311 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
2312 #define SDM_OP_GEN_RESERVED_SHIFT 17
2316 * The eth Rx Buffer Descriptor
2324 * The eth Rx SGE Descriptor
2334 * The eth storm context of Ustorm
2336 struct ustorm_eth_st_context {
2341 * The eth storm context of Tstorm
2343 struct tstorm_eth_st_context {
2344 u32 __reserved0[28];
2348 * The eth aggregative context of Xstorm
2350 struct xstorm_eth_ag_context {
2352 #if defined(__BIG_ENDIAN)
2356 #elif defined(__LITTLE_ENDIAN)
2365 * The eth aggregative context of Tstorm
2367 struct tstorm_eth_ag_context {
2368 u32 __reserved0[14];
2373 * The eth aggregative context of Cstorm
2375 struct cstorm_eth_ag_context {
2376 u32 __reserved0[10];
2381 * The eth aggregative context of Ustorm
2383 struct ustorm_eth_ag_context {
2385 #if defined(__BIG_ENDIAN)
2389 #elif defined(__LITTLE_ENDIAN)
2398 * Timers connection context
2400 struct timers_block_context {
2405 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
2406 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
2407 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
2408 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
2409 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
2410 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
2414 * structure for easy accessibility to assembler
2416 struct eth_tx_bd_flags {
2418 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
2419 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
2420 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
2421 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
2422 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
2423 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
2424 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
2425 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
2426 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
2427 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
2428 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
2429 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
2430 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
2431 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
2435 * The eth Tx Buffer Descriptor
2437 struct eth_tx_start_bd {
2442 __le16 vlan_or_ethertype;
2443 struct eth_tx_bd_flags bd_flags;
2445 #define ETH_TX_START_BD_HDR_NBDS (0x3F<<0)
2446 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
2447 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
2448 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
2452 * Tx regular BD structure
2457 __le16 total_pkt_bytes;
2463 * Tx parsing BD structure for ETH E1/E1h
2465 struct eth_tx_parse_bd_e1x {
2467 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
2468 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
2469 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
2470 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
2471 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
2472 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
2473 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
2474 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
2475 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
2476 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
2478 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
2479 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
2480 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
2481 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
2482 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
2483 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
2484 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
2485 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
2486 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
2487 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
2488 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
2489 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
2490 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
2491 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
2492 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
2493 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
2496 __le16 total_hlen_w;
2497 __le16 tcp_pseudo_csum;
2500 __le32 tcp_send_seq;
2504 * Tx parsing BD structure for ETH E2
2506 struct eth_tx_parse_bd_e2 {
2507 __le16 dst_mac_addr_lo;
2508 __le16 dst_mac_addr_mid;
2509 __le16 dst_mac_addr_hi;
2510 __le16 src_mac_addr_lo;
2511 __le16 src_mac_addr_mid;
2512 __le16 src_mac_addr_hi;
2513 __le32 parsing_data;
2514 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
2515 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
2516 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
2517 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
2518 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
2519 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
2520 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
2521 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
2525 * The last BD in the BD memory will hold a pointer to the next BD memory
2527 struct eth_tx_next_bd {
2534 * union for 4 Bd types
2536 union eth_tx_bd_types {
2537 struct eth_tx_start_bd start_bd;
2538 struct eth_tx_bd reg_bd;
2539 struct eth_tx_parse_bd_e1x parse_bd_e1x;
2540 struct eth_tx_parse_bd_e2 parse_bd_e2;
2541 struct eth_tx_next_bd next_bd;
2546 * The eth storm context of Xstorm
2548 struct xstorm_eth_st_context {
2553 * The eth storm context of Cstorm
2555 struct cstorm_eth_st_context {
2560 * Ethernet connection context
2562 struct eth_context {
2563 struct ustorm_eth_st_context ustorm_st_context;
2564 struct tstorm_eth_st_context tstorm_st_context;
2565 struct xstorm_eth_ag_context xstorm_ag_context;
2566 struct tstorm_eth_ag_context tstorm_ag_context;
2567 struct cstorm_eth_ag_context cstorm_ag_context;
2568 struct ustorm_eth_ag_context ustorm_ag_context;
2569 struct timers_block_context timers_context;
2570 struct xstorm_eth_st_context xstorm_st_context;
2571 struct cstorm_eth_st_context cstorm_st_context;
2578 struct eth_tx_doorbell {
2579 #if defined(__BIG_ENDIAN)
2582 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2583 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2584 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2585 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2586 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2587 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2588 struct doorbell_hdr hdr;
2589 #elif defined(__LITTLE_ENDIAN)
2590 struct doorbell_hdr hdr;
2592 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2593 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2594 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2595 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2596 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2597 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2604 * client init fc data
2606 struct client_init_fc_data {
2607 __le16 cqe_pause_thr_low;
2608 __le16 cqe_pause_thr_high;
2609 __le16 bd_pause_thr_low;
2610 __le16 bd_pause_thr_high;
2611 __le16 sge_pause_thr_low;
2612 __le16 sge_pause_thr_high;
2615 u8 safc_group_en_flg;
2624 * client init ramrod data
2626 struct client_init_general_data {
2628 u8 statistics_counter_id;
2629 u8 statistics_en_flg;
2634 __le32 reserved1[2];
2639 * client init rx data
2641 struct client_init_rx_data {
2643 u8 vmqueue_mode_en_flg;
2644 u8 extra_data_over_sgl_en_flg;
2645 u8 cache_line_alignment_log_size;
2646 u8 enable_dynamic_hc;
2647 u8 max_sges_for_packet;
2649 u8 drop_ip_cs_err_flg;
2650 u8 drop_tcp_cs_err_flg;
2652 u8 drop_udp_cs_err_flg;
2653 u8 inner_vlan_removal_enable_flg;
2654 u8 outer_vlan_removal_enable_flg;
2656 u8 rx_sb_index_number;
2658 __le16 bd_buff_size;
2659 __le16 sge_buff_size;
2661 struct regpair bd_page_base;
2662 struct regpair sge_page_base;
2663 struct regpair cqe_page_base;
2666 __le16 max_agg_size;
2667 __le32 reserved2[3];
2671 * client init tx data
2673 struct client_init_tx_data {
2674 u8 enforce_security_flg;
2675 u8 tx_status_block_id;
2676 u8 tx_sb_index_number;
2680 struct regpair tx_bd_page_base;
2681 __le32 reserved2[2];
2685 * client init ramrod data
2687 struct client_init_ramrod_data {
2688 struct client_init_general_data general;
2689 struct client_init_rx_data rx;
2690 struct client_init_tx_data tx;
2691 struct client_init_fc_data fc;
2696 * The data contain client ID need to the ramrod
2698 struct eth_common_ramrod_data {
2705 * union for sgl and raw data.
2707 union eth_sgl_or_raw_data {
2713 * regular eth FP CQE parameters struct
2715 struct eth_fast_path_rx_cqe {
2716 u8 type_error_flags;
2717 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1<<0)
2718 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2719 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<1)
2720 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2721 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<2)
2722 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2723 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<3)
2724 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2725 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1<<4)
2726 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2727 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1<<5)
2728 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2729 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x3<<6)
2730 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 6
2732 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
2733 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2734 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
2735 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2736 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
2737 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2738 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
2739 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2740 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
2741 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2742 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
2743 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2744 u8 placement_offset;
2746 __le32 rss_hash_result;
2750 struct parsing_flags pars_flags;
2751 union eth_sgl_or_raw_data sgl_or_raw_data;
2756 * The data for RSS setup ramrod
2758 struct eth_halt_ramrod_data {
2764 * The data for statistics query ramrod
2766 struct common_query_ramrod_data {
2767 #if defined(__BIG_ENDIAN)
2771 #elif defined(__LITTLE_ENDIAN)
2781 * Place holder for ramrods protocol specific data
2783 struct ramrod_data {
2789 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
2791 union eth_ramrod_data {
2792 struct ramrod_data general;
2797 * Eth Rx Cqe structure- general structure for ramrods
2799 struct common_ramrod_eth_rx_cqe {
2801 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1<<0)
2802 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2803 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<1)
2804 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1
2805 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F<<2)
2806 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2
2809 __le32 conn_and_cmd_data;
2810 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
2811 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2812 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
2813 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2814 struct ramrod_data protocol_data;
2815 __le32 reserved2[4];
2819 * Rx Last CQE in page (in ETH)
2821 struct eth_rx_cqe_next_page {
2828 * union for all eth rx cqe types (fix their sizes)
2831 struct eth_fast_path_rx_cqe fast_path_cqe;
2832 struct common_ramrod_eth_rx_cqe ramrod_cqe;
2833 struct eth_rx_cqe_next_page next_page_cqe;
2838 * common data for all protocols
2841 __le32 conn_and_cmd_data;
2842 #define SPE_HDR_CID (0xFFFFFF<<0)
2843 #define SPE_HDR_CID_SHIFT 0
2844 #define SPE_HDR_CMD_ID (0xFF<<24)
2845 #define SPE_HDR_CMD_ID_SHIFT 24
2847 #define SPE_HDR_CONN_TYPE (0xFF<<0)
2848 #define SPE_HDR_CONN_TYPE_SHIFT 0
2849 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
2850 #define SPE_HDR_FUNCTION_ID_SHIFT 8
2855 * Ethernet slow path element
2857 union eth_specific_data {
2858 u8 protocol_data[8];
2859 struct regpair client_init_ramrod_init_data;
2860 struct eth_halt_ramrod_data halt_ramrod_data;
2861 struct regpair update_data_addr;
2862 struct eth_common_ramrod_data common_ramrod_data;
2866 * Ethernet slow path element
2870 union eth_specific_data data;
2875 * array of 13 bds as appears in the eth xstorm context
2877 struct eth_tx_bds_array {
2878 union eth_tx_bd_types bds[13];
2883 * Common configuration parameters per function in Tstorm
2885 struct tstorm_eth_function_common_config {
2886 #if defined(__BIG_ENDIAN)
2890 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2891 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2892 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2893 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2894 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2895 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2896 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2897 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2898 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2899 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2900 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2901 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2902 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2903 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2904 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2905 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2906 #elif defined(__LITTLE_ENDIAN)
2908 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
2909 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2910 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
2911 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2912 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
2913 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2914 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
2915 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2916 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
2917 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2918 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1<<7)
2919 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 7
2920 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<8)
2921 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 8
2922 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x7F<<9)
2923 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 9
2931 * RSS idirection table update configuration
2933 struct rss_update_config {
2934 #if defined(__BIG_ENDIAN)
2937 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2938 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2939 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2940 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2941 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2942 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2943 #elif defined(__LITTLE_ENDIAN)
2945 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1<<0)
2946 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2947 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1<<1)
2948 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2949 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF<<2)
2950 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2957 * parameters for eth update ramrod
2959 struct eth_update_ramrod_data {
2960 struct tstorm_eth_function_common_config func_config;
2961 u8 indirectionTable[128];
2962 struct rss_update_config rss_config;
2967 * MAC filtering configuration command header
2969 struct mac_configuration_hdr {
2978 * MAC address in list for ramrod
2980 struct mac_configuration_entry {
2981 __le16 lsb_mac_addr;
2982 __le16 middle_mac_addr;
2983 __le16 msb_mac_addr;
2987 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
2988 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
2989 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
2990 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
2991 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
2992 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
2993 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
2994 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
2995 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
2996 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
2997 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
2998 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
3000 u32 clients_bit_vector;
3004 * MAC filtering configuration command
3006 struct mac_configuration_cmd {
3007 struct mac_configuration_hdr hdr;
3008 struct mac_configuration_entry config_table[64];
3013 * approximate-match multicast filtering for E1H per function in Tstorm
3015 struct tstorm_eth_approximate_match_multicast_filtering {
3016 u32 mcast_add_hash_bit_array[8];
3021 * MAC filtering configuration parameters per port in Tstorm
3023 struct tstorm_eth_mac_filter_config {
3025 u32 ucast_accept_all;
3027 u32 mcast_accept_all;
3029 u32 bcast_accept_all;
3031 u32 unmatched_unicast;
3037 * common flag to indicate existence of TPA.
3039 struct tstorm_eth_tpa_exist {
3040 #if defined(__BIG_ENDIAN)
3044 #elif defined(__LITTLE_ENDIAN)
3054 * Three RX producers for ETH
3056 struct ustorm_eth_rx_producers {
3057 #if defined(__BIG_ENDIAN)
3060 #elif defined(__LITTLE_ENDIAN)
3064 #if defined(__BIG_ENDIAN)
3067 #elif defined(__LITTLE_ENDIAN)
3075 * cfc delete event data
3077 struct cfc_del_event_data {
3087 * per-port SAFC demo variables
3089 struct cmng_flags_per_port {
3090 u8 con_number[NUM_OF_PROTOCOLS];
3092 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
3093 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
3094 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
3095 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
3096 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1<<2)
3097 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
3098 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1<<3)
3099 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
3100 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<4)
3101 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
3102 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<5)
3103 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 5
3104 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x3FFFFFF<<6)
3105 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 6
3110 * per-port rate shaping variables
3112 struct rate_shaping_vars_per_port {
3113 u32 rs_periodic_timeout;
3118 * per-port fairness variables
3120 struct fairness_vars_per_port {
3123 u32 fairness_timeout;
3127 * per-port SAFC variables
3129 struct safc_struct_per_port {
3130 #if defined(__BIG_ENDIAN)
3133 u8 safc_timeout_usec;
3134 #elif defined(__LITTLE_ENDIAN)
3135 u8 safc_timeout_usec;
3139 u8 cos_to_traffic_types[MAX_COS_NUMBER];
3141 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
3145 * per-port PFC variables
3147 struct pfc_struct_per_port {
3148 u8 priority_to_traffic_types[MAX_PFC_PRIORITIES];
3149 #if defined(__BIG_ENDIAN)
3150 u16 pfc_pause_quanta_in_nanosec;
3152 u8 priority_non_pausable_mask;
3153 #elif defined(__LITTLE_ENDIAN)
3154 u8 priority_non_pausable_mask;
3156 u16 pfc_pause_quanta_in_nanosec;
3163 struct priority_cos {
3164 #if defined(__BIG_ENDIAN)
3168 #elif defined(__LITTLE_ENDIAN)
3177 * Per-port congestion management variables
3179 struct cmng_struct_per_port {
3180 struct rate_shaping_vars_per_port rs_vars;
3181 struct fairness_vars_per_port fair_vars;
3182 struct safc_struct_per_port safc_vars;
3183 struct pfc_struct_per_port pfc_vars;
3184 #if defined(__BIG_ENDIAN)
3188 #elif defined(__LITTLE_ENDIAN)
3194 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
3195 struct cmng_flags_per_port flags;
3201 * Dynamic HC counters set by the driver
3203 struct hc_dynamic_drv_counter {
3204 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
3208 * zone A per-queue data
3210 struct cstorm_queue_zone_data {
3211 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
3212 struct regpair reserved[2];
3216 * Dynamic host coalescing init parameters
3218 struct dynamic_hc_config {
3220 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
3221 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
3222 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
3223 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
3224 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
3229 * Protocol-common statistics collected by the Xstorm (per client)
3231 struct xstorm_per_client_stats {
3233 __le32 unicast_pkts_sent;
3234 struct regpair unicast_bytes_sent;
3235 struct regpair multicast_bytes_sent;
3236 __le32 multicast_pkts_sent;
3237 __le32 broadcast_pkts_sent;
3238 struct regpair broadcast_bytes_sent;
3239 __le16 stats_counter;
3245 * Common statistics collected by the Xstorm (per port)
3247 struct xstorm_common_stats {
3248 struct xstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3252 * Protocol-common statistics collected by the Tstorm (per port)
3254 struct tstorm_per_port_stats {
3255 __le32 mac_filter_discard;
3256 __le32 xxoverflow_discard;
3257 __le32 brb_truncate_discard;
3262 * Protocol-common statistics collected by the Tstorm (per client)
3264 struct tstorm_per_client_stats {
3265 struct regpair rcv_unicast_bytes;
3266 struct regpair rcv_broadcast_bytes;
3267 struct regpair rcv_multicast_bytes;
3268 struct regpair rcv_error_bytes;
3269 __le32 checksum_discard;
3270 __le32 packets_too_big_discard;
3271 __le32 rcv_unicast_pkts;
3272 __le32 rcv_broadcast_pkts;
3273 __le32 rcv_multicast_pkts;
3274 __le32 no_buff_discard;
3275 __le32 ttl0_discard;
3276 __le16 stats_counter;
3281 * Protocol-common statistics collected by the Tstorm
3283 struct tstorm_common_stats {
3284 struct tstorm_per_port_stats port_statistics;
3285 struct tstorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3289 * Protocol-common statistics collected by the Ustorm (per client)
3291 struct ustorm_per_client_stats {
3292 struct regpair ucast_no_buff_bytes;
3293 struct regpair mcast_no_buff_bytes;
3294 struct regpair bcast_no_buff_bytes;
3295 __le32 ucast_no_buff_pkts;
3296 __le32 mcast_no_buff_pkts;
3297 __le32 bcast_no_buff_pkts;
3298 __le16 stats_counter;
3303 * Protocol-common statistics collected by the Ustorm
3305 struct ustorm_common_stats {
3306 struct ustorm_per_client_stats client_statistics[MAX_STAT_COUNTER_ID];
3310 * Eth statistics query structure for the eth_stats_query ramrod
3312 struct eth_stats_query {
3313 struct xstorm_common_stats xstorm_common;
3314 struct tstorm_common_stats tstorm_common;
3315 struct ustorm_common_stats ustorm_common;
3320 * set mac event data
3322 struct set_mac_event_data {
3330 * union for all event ring message types
3333 struct set_mac_event_data set_mac_event;
3334 struct cfc_del_event_data cfc_del_event;
3339 * per PF event ring data
3341 struct event_ring_data {
3342 struct regpair base_addr;
3343 #if defined(__BIG_ENDIAN)
3347 #elif defined(__LITTLE_ENDIAN)
3357 * event ring message element (each element is 128 bits)
3359 struct event_ring_msg {
3363 union event_data data;
3367 * event ring next page element (128 bits)
3369 struct event_ring_next {
3370 struct regpair addr;
3375 * union for event ring element types (each element is 128 bits)
3377 union event_ring_elem {
3378 struct event_ring_msg message;
3379 struct event_ring_next next_page;
3384 * per-vnic fairness variables
3386 struct fairness_vars_per_vn {
3387 u32 cos_credit_delta[MAX_COS_NUMBER];
3388 u32 protocol_credit_delta[NUM_OF_PROTOCOLS];
3389 u32 vn_credit_delta;
3395 * The data for flow control configuration
3397 struct flow_control_configuration {
3399 traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
3400 #if defined(__BIG_ENDIAN)
3404 #elif defined(__LITTLE_ENDIAN)
3414 * FW version stored in the Xstorm RAM
3417 #if defined(__BIG_ENDIAN)
3422 #elif defined(__LITTLE_ENDIAN)
3429 #define FW_VERSION_OPTIMIZED (0x1<<0)
3430 #define FW_VERSION_OPTIMIZED_SHIFT 0
3431 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
3432 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
3433 #define FW_VERSION_CHIP_VERSION (0x3<<2)
3434 #define FW_VERSION_CHIP_VERSION_SHIFT 2
3435 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
3436 #define __FW_VERSION_RESERVED_SHIFT 4
3441 * Dynamic Host-Coalescing - Driver(host) counters
3443 struct hc_dynamic_sb_drv_counters {
3444 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
3449 * 2 bytes. configuration/state parameters for a single protocol index
3451 struct hc_index_data {
3452 #if defined(__BIG_ENDIAN)
3454 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3455 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3456 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3457 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3458 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3459 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3460 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3461 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3463 #elif defined(__LITTLE_ENDIAN)
3466 #define HC_INDEX_DATA_SM_ID (0x1<<0)
3467 #define HC_INDEX_DATA_SM_ID_SHIFT 0
3468 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
3469 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
3470 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
3471 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
3472 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
3473 #define HC_INDEX_DATA_RESERVE_SHIFT 3
3481 struct hc_status_block_sm {
3482 #if defined(__BIG_ENDIAN)
3487 #elif defined(__LITTLE_ENDIAN)
3497 * hold PCI identification variables- used in various places in firmware
3500 #if defined(__BIG_ENDIAN)
3505 #elif defined(__LITTLE_ENDIAN)
3514 * The fast-path status block meta-data, common to all chips
3517 struct regpair host_sb_addr;
3518 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
3519 struct pci_entity p_func;
3520 #if defined(__BIG_ENDIAN)
3523 u8 __dynamic_hc_level;
3525 #elif defined(__LITTLE_ENDIAN)
3527 u8 __dynamic_hc_level;
3531 struct regpair rsrv1[2];
3536 * The fast-path status block meta-data
3538 struct hc_sp_status_block_data {
3539 struct regpair host_sb_addr;
3540 #if defined(__BIG_ENDIAN)
3544 #elif defined(__LITTLE_ENDIAN)
3549 struct pci_entity p_func;
3554 * The fast-path status block meta-data
3556 struct hc_status_block_data_e1x {
3557 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
3558 struct hc_sb_data common;
3563 * The fast-path status block meta-data
3565 struct hc_status_block_data_e2 {
3566 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
3567 struct hc_sb_data common;
3572 * FW version stored in first line of pram
3574 struct pram_fw_version {
3580 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
3581 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
3582 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
3583 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
3584 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
3585 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
3586 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
3587 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
3588 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
3589 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
3594 * Ethernet slow path element
3596 union protocol_common_specific_data {
3597 u8 protocol_data[8];
3598 struct regpair phy_address;
3599 struct regpair mac_config_addr;
3600 struct common_query_ramrod_data query_ramrod_data;
3604 * The send queue element
3606 struct protocol_common_spe {
3608 union protocol_common_specific_data data;
3613 * a single rate shaping counter. can be used as protocol or vnic counter
3615 struct rate_shaping_counter {
3617 #if defined(__BIG_ENDIAN)
3620 #elif defined(__LITTLE_ENDIAN)
3628 * per-vnic rate shaping variables
3630 struct rate_shaping_vars_per_vn {
3631 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
3632 struct rate_shaping_counter vn_counter;
3637 * The send queue element
3639 struct slow_path_element {
3641 struct regpair protocol_data;
3646 * eth/toe flags that indicate if to query
3648 struct stats_indication_flags {
3655 * per-port PFC variables
3657 struct storm_pfc_struct_per_port {
3658 #if defined(__BIG_ENDIAN)
3661 #elif defined(__LITTLE_ENDIAN)
3665 #if defined(__BIG_ENDIAN)
3666 u16 pfc_pause_quanta_in_nanosec;
3668 #elif defined(__LITTLE_ENDIAN)
3670 u16 pfc_pause_quanta_in_nanosec;
3675 * Per-port congestion management variables
3677 struct storm_cmng_struct_per_port {
3678 struct storm_pfc_struct_per_port pfc_vars;
3683 * zone A per-queue data
3685 struct tstorm_queue_zone_data {
3686 struct regpair reserved[4];
3691 * zone B per-VF data
3693 struct tstorm_vf_zone_data {
3694 struct regpair reserved;
3699 * zone A per-queue data
3701 struct ustorm_queue_zone_data {
3702 struct ustorm_eth_rx_producers eth_rx_producers;
3703 struct regpair reserved[3];
3708 * zone B per-VF data
3710 struct ustorm_vf_zone_data {
3711 struct regpair reserved;
3716 * data per VF-PF channel
3718 struct vf_pf_channel_data {
3719 #if defined(__BIG_ENDIAN)
3723 #elif defined(__LITTLE_ENDIAN)
3733 * zone A per-queue data
3735 struct xstorm_queue_zone_data {
3736 struct regpair reserved[4];
3741 * zone B per-VF data
3743 struct xstorm_vf_zone_data {
3744 struct regpair reserved;
3747 #endif /* BNX2X_HSI_H */