drivers/net/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2010 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17 #include <linux/ethtool.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/types.h>
  20 #include <linux/sched.h>
  21 #include <linux/crc32.h>
  22
  23
  24 #include "bnx2x.h"
  25 #include "bnx2x_cmn.h"
  26 #include "bnx2x_dump.h"
  27
  28 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  29 {
  30         struct bnx2x *bp = netdev_priv(dev);
  31         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
  32         /* Dual Media boards present all available port types */
  33         cmd->supported = bp->port.supported[cfg_idx] |
  34                 (bp->port.supported[cfg_idx ^ 1] &
  35                  (SUPPORTED_TP | SUPPORTED_FIBRE));
  36         cmd->advertising = bp->port.advertising[cfg_idx];
  37
  38         if ((bp->state == BNX2X_STATE_OPEN) &&
  39             !(bp->flags & MF_FUNC_DIS) &&
  40             (bp->link_vars.link_up)) {
  41                 cmd->speed = bp->link_vars.line_speed;
  42                 cmd->duplex = bp->link_vars.duplex;
  43         } else {
  44
  45                 cmd->speed = bp->link_params.req_line_speed[cfg_idx];
  46                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
  47         }
  48
  49         if (IS_MF(bp))
  50                 cmd->speed = bnx2x_get_mf_speed(bp);
  51
  52         if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
  53                 cmd->port = PORT_TP;
  54         else if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
  55                 cmd->port = PORT_FIBRE;
  56         else
  57                 BNX2X_ERR("XGXS PHY Failure detected\n");
  58
  59         cmd->phy_address = bp->mdio.prtad;
  60         cmd->transceiver = XCVR_INTERNAL;
  61
  62         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
  63                 cmd->autoneg = AUTONEG_ENABLE;
  64         else
  65                 cmd->autoneg = AUTONEG_DISABLE;
  66
  67         cmd->maxtxpkt = 0;
  68         cmd->maxrxpkt = 0;
  69
  70         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
  71            DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
  72            DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
  73            DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
  74            cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
  75            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
  76            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
  77
  78         return 0;
  79 }
  80
  81 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  82 {
  83         struct bnx2x *bp = netdev_priv(dev);
  84         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
  85         u32 speed;
  86
  87         if (IS_MF_SD(bp))
  88                 return 0;
  89
  90         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
  91            "  supported 0x%x  advertising 0x%x  speed %d speed_hi %d\n"
  92            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
  93            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
  94            cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
  95            cmd->speed_hi,
  96            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
  97            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
  98
  99         speed = cmd->speed;
 100         speed |= (cmd->speed_hi << 16);
 101
 102         if (IS_MF_SI(bp)) {
 103                 u32 param = 0;
 104                 u32 line_speed = bp->link_vars.line_speed;
 105
 106                 /* use 10G if no link detected */
 107                 if (!line_speed)
 108                         line_speed = 10000;
 109
 110                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 111                         BNX2X_DEV_INFO("To set speed BC %X or higher "
 112                                        "is required, please upgrade BC\n",
 113                                        REQ_BC_VER_4_SET_MF_BW);
 114                         return -EINVAL;
 115                 }
 116                 if (line_speed < speed) {
 117                         BNX2X_DEV_INFO("New speed should be less or equal "
 118                                        "to actual line speed\n");
 119                         return -EINVAL;
 120                 }
 121                 /* load old values */
 122                 param = bp->mf_config[BP_VN(bp)];
 123
 124                 /* leave only MIN value */
 125                 param &= FUNC_MF_CFG_MIN_BW_MASK;
 126
 127                 /* set new MAX value */
 128                 param |= (((speed * 100) / line_speed)
 129                                  << FUNC_MF_CFG_MAX_BW_SHIFT)
 130                                   & FUNC_MF_CFG_MAX_BW_MASK;
 131
 132                 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, param);
 133                 return 0;
 134         }
 135
 136         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 137         old_multi_phy_config = bp->link_params.multi_phy_config;
 138         switch (cmd->port) {
 139         case PORT_TP:
 140                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 141                         break; /* no port change */
 142
 143                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 144                       bp->port.supported[1] & SUPPORTED_TP)) {
 145                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 146                         return -EINVAL;
 147                 }
 148                 bp->link_params.multi_phy_config &=
 149                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 150                 if (bp->link_params.multi_phy_config &
 151                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 152                         bp->link_params.multi_phy_config |=
 153                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 154                 else
 155                         bp->link_params.multi_phy_config |=
 156                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 157                 break;
 158         case PORT_FIBRE:
 159                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 160                         break; /* no port change */
 161
 162                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 163                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 164                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 165                         return -EINVAL;
 166                 }
 167                 bp->link_params.multi_phy_config &=
 168                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 169                 if (bp->link_params.multi_phy_config &
 170                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 171                         bp->link_params.multi_phy_config |=
 172                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 173                 else
 174                         bp->link_params.multi_phy_config |=
 175                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 176                 break;
 177         default:
 178                 DP(NETIF_MSG_LINK, "Unsupported port type\n");
 179                 return -EINVAL;
 180         }
 181         /* Save new config in case command complete successuly */
 182         new_multi_phy_config = bp->link_params.multi_phy_config;
 183         /* Get the new cfg_idx */
 184         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 185         /* Restore old config in case command failed */
 186         bp->link_params.multi_phy_config = old_multi_phy_config;
 187         DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
 188
 189         if (cmd->autoneg == AUTONEG_ENABLE) {
 190                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 191                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
 192                         return -EINVAL;
 193                 }
 194
 195                 /* advertise the requested speed and duplex if supported */
 196                 cmd->advertising &= bp->port.supported[cfg_idx];
 197
 198                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 199                 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
 200                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
 201                                          cmd->advertising);
 202
 203         } else { /* forced speed */
 204                 /* advertise the requested speed and duplex if supported */
 205                 switch (speed) {
 206                 case SPEED_10:
 207                         if (cmd->duplex == DUPLEX_FULL) {
 208                                 if (!(bp->port.supported[cfg_idx] &
 209                                       SUPPORTED_10baseT_Full)) {
 210                                         DP(NETIF_MSG_LINK,
 211                                            "10M full not supported\n");
 212                                         return -EINVAL;
 213                                 }
 214
 215                                 advertising = (ADVERTISED_10baseT_Full |
 216                                                ADVERTISED_TP);
 217                         } else {
 218                                 if (!(bp->port.supported[cfg_idx] &
 219                                       SUPPORTED_10baseT_Half)) {
 220                                         DP(NETIF_MSG_LINK,
 221                                            "10M half not supported\n");
 222                                         return -EINVAL;
 223                                 }
 224
 225                                 advertising = (ADVERTISED_10baseT_Half |
 226                                                ADVERTISED_TP);
 227                         }
 228                         break;
 229
 230                 case SPEED_100:
 231                         if (cmd->duplex == DUPLEX_FULL) {
 232                                 if (!(bp->port.supported[cfg_idx] &
 233                                                 SUPPORTED_100baseT_Full)) {
 234                                         DP(NETIF_MSG_LINK,
 235                                            "100M full not supported\n");
 236                                         return -EINVAL;
 237                                 }
 238
 239                                 advertising = (ADVERTISED_100baseT_Full |
 240                                                ADVERTISED_TP);
 241                         } else {
 242                                 if (!(bp->port.supported[cfg_idx] &
 243                                                 SUPPORTED_100baseT_Half)) {
 244                                         DP(NETIF_MSG_LINK,
 245                                            "100M half not supported\n");
 246                                         return -EINVAL;
 247                                 }
 248
 249                                 advertising = (ADVERTISED_100baseT_Half |
 250                                                ADVERTISED_TP);
 251                         }
 252                         break;
 253
 254                 case SPEED_1000:
 255                         if (cmd->duplex != DUPLEX_FULL) {
 256                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
 257                                 return -EINVAL;
 258                         }
 259
 260                         if (!(bp->port.supported[cfg_idx] &
 261                               SUPPORTED_1000baseT_Full)) {
 262                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
 263                                 return -EINVAL;
 264                         }
 265
 266                         advertising = (ADVERTISED_1000baseT_Full |
 267                                        ADVERTISED_TP);
 268                         break;
 269
 270                 case SPEED_2500:
 271                         if (cmd->duplex != DUPLEX_FULL) {
 272                                 DP(NETIF_MSG_LINK,
 273                                    "2.5G half not supported\n");
 274                                 return -EINVAL;
 275                         }
 276
 277                         if (!(bp->port.supported[cfg_idx]
 278                               & SUPPORTED_2500baseX_Full)) {
 279                                 DP(NETIF_MSG_LINK,
 280                                    "2.5G full not supported\n");
 281                                 return -EINVAL;
 282                         }
 283
 284                         advertising = (ADVERTISED_2500baseX_Full |
 285                                        ADVERTISED_TP);
 286                         break;
 287
 288                 case SPEED_10000:
 289                         if (cmd->duplex != DUPLEX_FULL) {
 290                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
 291                                 return -EINVAL;
 292                         }
 293
 294                         if (!(bp->port.supported[cfg_idx]
 295                               & SUPPORTED_10000baseT_Full)) {
 296                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
 297                                 return -EINVAL;
 298                         }
 299
 300                         advertising = (ADVERTISED_10000baseT_Full |
 301                                        ADVERTISED_FIBRE);
 302                         break;
 303
 304                 default:
 305                         DP(NETIF_MSG_LINK, "Unsupported speed %d\n", speed);
 306                         return -EINVAL;
 307                 }
 308
 309                 bp->link_params.req_line_speed[cfg_idx] = speed;
 310                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 311                 bp->port.advertising[cfg_idx] = advertising;
 312         }
 313
 314         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
 315            DP_LEVEL "  req_duplex %d  advertising 0x%x\n",
 316            bp->link_params.req_line_speed[cfg_idx],
 317            bp->link_params.req_duplex[cfg_idx],
 318            bp->port.advertising[cfg_idx]);
 319
 320         /* Set new config */
 321         bp->link_params.multi_phy_config = new_multi_phy_config;
 322         if (netif_running(dev)) {
 323                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 324                 bnx2x_link_set(bp);
 325         }
 326
 327         return 0;
 328 }
 329
 330 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 331 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 332 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 333
 334 static int bnx2x_get_regs_len(struct net_device *dev)
 335 {
 336         struct bnx2x *bp = netdev_priv(dev);
 337         int regdump_len = 0;
 338         int i;
 339
 340         if (CHIP_IS_E1(bp)) {
 341                 for (i = 0; i < REGS_COUNT; i++)
 342                         if (IS_E1_ONLINE(reg_addrs[i].info))
 343                                 regdump_len += reg_addrs[i].size;
 344
 345                 for (i = 0; i < WREGS_COUNT_E1; i++)
 346                         if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
 347                                 regdump_len += wreg_addrs_e1[i].size *
 348                                         (1 + wreg_addrs_e1[i].read_regs_count);
 349
 350         } else if (CHIP_IS_E1H(bp)) {
 351                 for (i = 0; i < REGS_COUNT; i++)
 352                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 353                                 regdump_len += reg_addrs[i].size;
 354
 355                 for (i = 0; i < WREGS_COUNT_E1H; i++)
 356                         if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
 357                                 regdump_len += wreg_addrs_e1h[i].size *
 358                                         (1 + wreg_addrs_e1h[i].read_regs_count);
 359         } else if (CHIP_IS_E2(bp)) {
 360                 for (i = 0; i < REGS_COUNT; i++)
 361                         if (IS_E2_ONLINE(reg_addrs[i].info))
 362                                 regdump_len += reg_addrs[i].size;
 363
 364                 for (i = 0; i < WREGS_COUNT_E2; i++)
 365                         if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
 366                                 regdump_len += wreg_addrs_e2[i].size *
 367                                         (1 + wreg_addrs_e2[i].read_regs_count);
 368         }
 369         regdump_len *= 4;
 370         regdump_len += sizeof(struct dump_hdr);
 371
 372         return regdump_len;
 373 }
 374
 375 static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
 376 {
 377         u32 i, j, k, n;
 378
 379         for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
 380                 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
 381                         REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
 382                         for (k = 0; k < PAGE_READ_REGS_E2; k++)
 383                                 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
 384                                         for (n = 0; n <
 385                                               page_read_regs_e2[k].size; n++)
 386                                                 *p++ = REG_RD(bp,
 387                                         page_read_regs_e2[k].addr + n*4);
 388                 }
 389         }
 390 }
 391
 392 static void bnx2x_get_regs(struct net_device *dev,
 393                            struct ethtool_regs *regs, void *_p)
 394 {
 395         u32 *p = _p, i, j;
 396         struct bnx2x *bp = netdev_priv(dev);
 397         struct dump_hdr dump_hdr = {0};
 398
 399         regs->version = 0;
 400         memset(p, 0, regs->len);
 401
 402         if (!netif_running(bp->dev))
 403                 return;
 404
 405         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 406         dump_hdr.dump_sign = dump_sign_all;
 407         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 408         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 409         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 410         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 411
 412         if (CHIP_IS_E1(bp))
 413                 dump_hdr.info = RI_E1_ONLINE;
 414         else if (CHIP_IS_E1H(bp))
 415                 dump_hdr.info = RI_E1H_ONLINE;
 416         else if (CHIP_IS_E2(bp))
 417                 dump_hdr.info = RI_E2_ONLINE |
 418                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 419
 420         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 421         p += dump_hdr.hdr_size + 1;
 422
 423         if (CHIP_IS_E1(bp)) {
 424                 for (i = 0; i < REGS_COUNT; i++)
 425                         if (IS_E1_ONLINE(reg_addrs[i].info))
 426                                 for (j = 0; j < reg_addrs[i].size; j++)
 427                                         *p++ = REG_RD(bp,
 428                                                       reg_addrs[i].addr + j*4);
 429
 430         } else if (CHIP_IS_E1H(bp)) {
 431                 for (i = 0; i < REGS_COUNT; i++)
 432                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 433                                 for (j = 0; j < reg_addrs[i].size; j++)
 434                                         *p++ = REG_RD(bp,
 435                                                       reg_addrs[i].addr + j*4);
 436
 437         } else if (CHIP_IS_E2(bp)) {
 438                 for (i = 0; i < REGS_COUNT; i++)
 439                         if (IS_E2_ONLINE(reg_addrs[i].info))
 440                                 for (j = 0; j < reg_addrs[i].size; j++)
 441                                         *p++ = REG_RD(bp,
 442                                               reg_addrs[i].addr + j*4);
 443
 444                 bnx2x_read_pages_regs_e2(bp, p);
 445         }
 446 }
 447
 448 #define PHY_FW_VER_LEN                  20
 449
 450 static void bnx2x_get_drvinfo(struct net_device *dev,
 451                               struct ethtool_drvinfo *info)
 452 {
 453         struct bnx2x *bp = netdev_priv(dev);
 454         u8 phy_fw_ver[PHY_FW_VER_LEN];
 455
 456         strcpy(info->driver, DRV_MODULE_NAME);
 457         strcpy(info->version, DRV_MODULE_VERSION);
 458
 459         phy_fw_ver[0] = '\0';
 460         if (bp->port.pmf) {
 461                 bnx2x_acquire_phy_lock(bp);
 462                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
 463                                              (bp->state != BNX2X_STATE_CLOSED),
 464                                              phy_fw_ver, PHY_FW_VER_LEN);
 465                 bnx2x_release_phy_lock(bp);
 466         }
 467
 468         strncpy(info->fw_version, bp->fw_ver, 32);
 469         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 470                  "bc %d.%d.%d%s%s",
 471                  (bp->common.bc_ver & 0xff0000) >> 16,
 472                  (bp->common.bc_ver & 0xff00) >> 8,
 473                  (bp->common.bc_ver & 0xff),
 474                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 475         strcpy(info->bus_info, pci_name(bp->pdev));
 476         info->n_stats = BNX2X_NUM_STATS;
 477         info->testinfo_len = BNX2X_NUM_TESTS;
 478         info->eedump_len = bp->common.flash_size;
 479         info->regdump_len = bnx2x_get_regs_len(dev);
 480 }
 481
 482 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 483 {
 484         struct bnx2x *bp = netdev_priv(dev);
 485
 486         if (bp->flags & NO_WOL_FLAG) {
 487                 wol->supported = 0;
 488                 wol->wolopts = 0;
 489         } else {
 490                 wol->supported = WAKE_MAGIC;
 491                 if (bp->wol)
 492                         wol->wolopts = WAKE_MAGIC;
 493                 else
 494                         wol->wolopts = 0;
 495         }
 496         memset(&wol->sopass, 0, sizeof(wol->sopass));
 497 }
 498
 499 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 500 {
 501         struct bnx2x *bp = netdev_priv(dev);
 502
 503         if (wol->wolopts & ~WAKE_MAGIC)
 504                 return -EINVAL;
 505
 506         if (wol->wolopts & WAKE_MAGIC) {
 507                 if (bp->flags & NO_WOL_FLAG)
 508                         return -EINVAL;
 509
 510                 bp->wol = 1;
 511         } else
 512                 bp->wol = 0;
 513
 514         return 0;
 515 }
 516
 517 static u32 bnx2x_get_msglevel(struct net_device *dev)
 518 {
 519         struct bnx2x *bp = netdev_priv(dev);
 520
 521         return bp->msg_enable;
 522 }
 523
 524 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 525 {
 526         struct bnx2x *bp = netdev_priv(dev);
 527
 528         if (capable(CAP_NET_ADMIN))
 529                 bp->msg_enable = level;
 530 }
 531
 532 static int bnx2x_nway_reset(struct net_device *dev)
 533 {
 534         struct bnx2x *bp = netdev_priv(dev);
 535
 536         if (!bp->port.pmf)
 537                 return 0;
 538
 539         if (netif_running(dev)) {
 540                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 541                 bnx2x_link_set(bp);
 542         }
 543
 544         return 0;
 545 }
 546
 547 static u32 bnx2x_get_link(struct net_device *dev)
 548 {
 549         struct bnx2x *bp = netdev_priv(dev);
 550
 551         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 552                 return 0;
 553
 554         return bp->link_vars.link_up;
 555 }
 556
 557 static int bnx2x_get_eeprom_len(struct net_device *dev)
 558 {
 559         struct bnx2x *bp = netdev_priv(dev);
 560
 561         return bp->common.flash_size;
 562 }
 563
 564 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 565 {
 566         int port = BP_PORT(bp);
 567         int count, i;
 568         u32 val = 0;
 569
 570         /* adjust timeout for emulation/FPGA */
 571         count = NVRAM_TIMEOUT_COUNT;
 572         if (CHIP_REV_IS_SLOW(bp))
 573                 count *= 100;
 574
 575         /* request access to nvram interface */
 576         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 577                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 578
 579         for (i = 0; i < count*10; i++) {
 580                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 581                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 582                         break;
 583
 584                 udelay(5);
 585         }
 586
 587         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 588                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
 589                 return -EBUSY;
 590         }
 591
 592         return 0;
 593 }
 594
 595 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 596 {
 597         int port = BP_PORT(bp);
 598         int count, i;
 599         u32 val = 0;
 600
 601         /* adjust timeout for emulation/FPGA */
 602         count = NVRAM_TIMEOUT_COUNT;
 603         if (CHIP_REV_IS_SLOW(bp))
 604                 count *= 100;
 605
 606         /* relinquish nvram interface */
 607         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 608                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 609
 610         for (i = 0; i < count*10; i++) {
 611                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 612                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 613                         break;
 614
 615                 udelay(5);
 616         }
 617
 618         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 619                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
 620                 return -EBUSY;
 621         }
 622
 623         return 0;
 624 }
 625
 626 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 627 {
 628         u32 val;
 629
 630         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 631
 632         /* enable both bits, even on read */
 633         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 634                (val | MCPR_NVM_ACCESS_ENABLE_EN |
 635                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
 636 }
 637
 638 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 639 {
 640         u32 val;
 641
 642         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 643
 644         /* disable both bits, even after read */
 645         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 646                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
 647                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 648 }
 649
 650 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
 651                                   u32 cmd_flags)
 652 {
 653         int count, i, rc;
 654         u32 val;
 655
 656         /* build the command word */
 657         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
 658
 659         /* need to clear DONE bit separately */
 660         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 661
 662         /* address of the NVRAM to read from */
 663         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 664                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 665
 666         /* issue a read command */
 667         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 668
 669         /* adjust timeout for emulation/FPGA */
 670         count = NVRAM_TIMEOUT_COUNT;
 671         if (CHIP_REV_IS_SLOW(bp))
 672                 count *= 100;
 673
 674         /* wait for completion */
 675         *ret_val = 0;
 676         rc = -EBUSY;
 677         for (i = 0; i < count; i++) {
 678                 udelay(5);
 679                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 680
 681                 if (val & MCPR_NVM_COMMAND_DONE) {
 682                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
 683                         /* we read nvram data in cpu order
 684                          * but ethtool sees it as an array of bytes
 685                          * converting to big-endian will do the work */
 686                         *ret_val = cpu_to_be32(val);
 687                         rc = 0;
 688                         break;
 689                 }
 690         }
 691
 692         return rc;
 693 }
 694
 695 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
 696                             int buf_size)
 697 {
 698         int rc;
 699         u32 cmd_flags;
 700         __be32 val;
 701
 702         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
 703                 DP(BNX2X_MSG_NVM,
 704                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
 705                    offset, buf_size);
 706                 return -EINVAL;
 707         }
 708
 709         if (offset + buf_size > bp->common.flash_size) {
 710                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 711                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 712                    offset, buf_size, bp->common.flash_size);
 713                 return -EINVAL;
 714         }
 715
 716         /* request access to nvram interface */
 717         rc = bnx2x_acquire_nvram_lock(bp);
 718         if (rc)
 719                 return rc;
 720
 721         /* enable access to nvram interface */
 722         bnx2x_enable_nvram_access(bp);
 723
 724         /* read the first word(s) */
 725         cmd_flags = MCPR_NVM_COMMAND_FIRST;
 726         while ((buf_size > sizeof(u32)) && (rc == 0)) {
 727                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 728                 memcpy(ret_buf, &val, 4);
 729
 730                 /* advance to the next dword */
 731                 offset += sizeof(u32);
 732                 ret_buf += sizeof(u32);
 733                 buf_size -= sizeof(u32);
 734                 cmd_flags = 0;
 735         }
 736
 737         if (rc == 0) {
 738                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
 739                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 740                 memcpy(ret_buf, &val, 4);
 741         }
 742
 743         /* disable access to nvram interface */
 744         bnx2x_disable_nvram_access(bp);
 745         bnx2x_release_nvram_lock(bp);
 746
 747         return rc;
 748 }
 749
 750 static int bnx2x_get_eeprom(struct net_device *dev,
 751                             struct ethtool_eeprom *eeprom, u8 *eebuf)
 752 {
 753         struct bnx2x *bp = netdev_priv(dev);
 754         int rc;
 755
 756         if (!netif_running(dev))
 757                 return -EAGAIN;
 758
 759         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
 760            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
 761            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
 762            eeprom->len, eeprom->len);
 763
 764         /* parameters already validated in ethtool_get_eeprom */
 765
 766         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
 767
 768         return rc;
 769 }
 770
 771 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
 772                                    u32 cmd_flags)
 773 {
 774         int count, i, rc;
 775
 776         /* build the command word */
 777         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
 778
 779         /* need to clear DONE bit separately */
 780         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 781
 782         /* write the data */
 783         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
 784
 785         /* address of the NVRAM to write to */
 786         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 787                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 788
 789         /* issue the write command */
 790         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 791
 792         /* adjust timeout for emulation/FPGA */
 793         count = NVRAM_TIMEOUT_COUNT;
 794         if (CHIP_REV_IS_SLOW(bp))
 795                 count *= 100;
 796
 797         /* wait for completion */
 798         rc = -EBUSY;
 799         for (i = 0; i < count; i++) {
 800                 udelay(5);
 801                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 802                 if (val & MCPR_NVM_COMMAND_DONE) {
 803                         rc = 0;
 804                         break;
 805                 }
 806         }
 807
 808         return rc;
 809 }
 810
 811 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
 812
 813 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
 814                               int buf_size)
 815 {
 816         int rc;
 817         u32 cmd_flags;
 818         u32 align_offset;
 819         __be32 val;
 820
 821         if (offset + buf_size > bp->common.flash_size) {
 822                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 823                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 824                    offset, buf_size, bp->common.flash_size);
 825                 return -EINVAL;
 826         }
 827
 828         /* request access to nvram interface */
 829         rc = bnx2x_acquire_nvram_lock(bp);
 830         if (rc)
 831                 return rc;
 832
 833         /* enable access to nvram interface */
 834         bnx2x_enable_nvram_access(bp);
 835
 836         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
 837         align_offset = (offset & ~0x03);
 838         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
 839
 840         if (rc == 0) {
 841                 val &= ~(0xff << BYTE_OFFSET(offset));
 842                 val |= (*data_buf << BYTE_OFFSET(offset));
 843
 844                 /* nvram data is returned as an array of bytes
 845                  * convert it back to cpu order */
 846                 val = be32_to_cpu(val);
 847
 848                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
 849                                              cmd_flags);
 850         }
 851
 852         /* disable access to nvram interface */
 853         bnx2x_disable_nvram_access(bp);
 854         bnx2x_release_nvram_lock(bp);
 855
 856         return rc;
 857 }
 858
 859 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
 860                              int buf_size)
 861 {
 862         int rc;
 863         u32 cmd_flags;
 864         u32 val;
 865         u32 written_so_far;
 866
 867         if (buf_size == 1)      /* ethtool */
 868                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
 869
 870         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
 871                 DP(BNX2X_MSG_NVM,
 872                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
 873                    offset, buf_size);
 874                 return -EINVAL;
 875         }
 876
 877         if (offset + buf_size > bp->common.flash_size) {
 878                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 879                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 880                    offset, buf_size, bp->common.flash_size);
 881                 return -EINVAL;
 882         }
 883
 884         /* request access to nvram interface */
 885         rc = bnx2x_acquire_nvram_lock(bp);
 886         if (rc)
 887                 return rc;
 888
 889         /* enable access to nvram interface */
 890         bnx2x_enable_nvram_access(bp);
 891
 892         written_so_far = 0;
 893         cmd_flags = MCPR_NVM_COMMAND_FIRST;
 894         while ((written_so_far < buf_size) && (rc == 0)) {
 895                 if (written_so_far == (buf_size - sizeof(u32)))
 896                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
 897                 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
 898                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
 899                 else if ((offset % NVRAM_PAGE_SIZE) == 0)
 900                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
 901
 902                 memcpy(&val, data_buf, 4);
 903
 904                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
 905
 906                 /* advance to the next dword */
 907                 offset += sizeof(u32);
 908                 data_buf += sizeof(u32);
 909                 written_so_far += sizeof(u32);
 910                 cmd_flags = 0;
 911         }
 912
 913         /* disable access to nvram interface */
 914         bnx2x_disable_nvram_access(bp);
 915         bnx2x_release_nvram_lock(bp);
 916
 917         return rc;
 918 }
 919
 920 static int bnx2x_set_eeprom(struct net_device *dev,
 921                             struct ethtool_eeprom *eeprom, u8 *eebuf)
 922 {
 923         struct bnx2x *bp = netdev_priv(dev);
 924         int port = BP_PORT(bp);
 925         int rc = 0;
 926         u32 ext_phy_config;
 927         if (!netif_running(dev))
 928                 return -EAGAIN;
 929
 930         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
 931            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
 932            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
 933            eeprom->len, eeprom->len);
 934
 935         /* parameters already validated in ethtool_set_eeprom */
 936
 937         /* PHY eeprom can be accessed only by the PMF */
 938         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
 939             !bp->port.pmf)
 940                 return -EINVAL;
 941
 942         ext_phy_config =
 943                 SHMEM_RD(bp,
 944                          dev_info.port_hw_config[port].external_phy_config);
 945
 946         if (eeprom->magic == 0x50485950) {
 947                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
 948                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 949
 950                 bnx2x_acquire_phy_lock(bp);
 951                 rc |= bnx2x_link_reset(&bp->link_params,
 952                                        &bp->link_vars, 0);
 953                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
 954                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
 955                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
 956                                        MISC_REGISTERS_GPIO_HIGH, port);
 957                 bnx2x_release_phy_lock(bp);
 958                 bnx2x_link_report(bp);
 959
 960         } else if (eeprom->magic == 0x50485952) {
 961                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
 962                 if (bp->state == BNX2X_STATE_OPEN) {
 963                         bnx2x_acquire_phy_lock(bp);
 964                         rc |= bnx2x_link_reset(&bp->link_params,
 965                                                &bp->link_vars, 1);
 966
 967                         rc |= bnx2x_phy_init(&bp->link_params,
 968                                              &bp->link_vars);
 969                         bnx2x_release_phy_lock(bp);
 970                         bnx2x_calc_fc_adv(bp);
 971                 }
 972         } else if (eeprom->magic == 0x53985943) {
 973                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
 974                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
 975                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
 976
 977                         /* DSP Remove Download Mode */
 978                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
 979                                        MISC_REGISTERS_GPIO_LOW, port);
 980
 981                         bnx2x_acquire_phy_lock(bp);
 982
 983                         bnx2x_sfx7101_sp_sw_reset(bp,
 984                                                 &bp->link_params.phy[EXT_PHY1]);
 985
 986                         /* wait 0.5 sec to allow it to run */
 987                         msleep(500);
 988                         bnx2x_ext_phy_hw_reset(bp, port);
 989                         msleep(500);
 990                         bnx2x_release_phy_lock(bp);
 991                 }
 992         } else
 993                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
 994
 995         return rc;
 996 }
 997
 998 static int bnx2x_get_coalesce(struct net_device *dev,
 999                               struct ethtool_coalesce *coal)
1000 {
1001         struct bnx2x *bp = netdev_priv(dev);
1002
1003         memset(coal, 0, sizeof(struct ethtool_coalesce));
1004
1005         coal->rx_coalesce_usecs = bp->rx_ticks;
1006         coal->tx_coalesce_usecs = bp->tx_ticks;
1007
1008         return 0;
1009 }
1010
1011 static int bnx2x_set_coalesce(struct net_device *dev,
1012                               struct ethtool_coalesce *coal)
1013 {
1014         struct bnx2x *bp = netdev_priv(dev);
1015
1016         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1017         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1018                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1019
1020         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1021         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1022                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1023
1024         if (netif_running(dev))
1025                 bnx2x_update_coalesce(bp);
1026
1027         return 0;
1028 }
1029
1030 static void bnx2x_get_ringparam(struct net_device *dev,
1031                                 struct ethtool_ringparam *ering)
1032 {
1033         struct bnx2x *bp = netdev_priv(dev);
1034
1035         ering->rx_max_pending = MAX_RX_AVAIL;
1036         ering->rx_mini_max_pending = 0;
1037         ering->rx_jumbo_max_pending = 0;
1038
1039         if (bp->rx_ring_size)
1040                 ering->rx_pending = bp->rx_ring_size;
1041         else
1042                 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1043                         ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1044                 else
1045                         ering->rx_pending = MAX_RX_AVAIL;
1046
1047         ering->rx_mini_pending = 0;
1048         ering->rx_jumbo_pending = 0;
1049
1050         ering->tx_max_pending = MAX_TX_AVAIL;
1051         ering->tx_pending = bp->tx_ring_size;
1052 }
1053
1054 static int bnx2x_set_ringparam(struct net_device *dev,
1055                                struct ethtool_ringparam *ering)
1056 {
1057         struct bnx2x *bp = netdev_priv(dev);
1058         int rc = 0;
1059
1060         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1061                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1062                 return -EAGAIN;
1063         }
1064
1065         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1066             (ering->rx_pending < MIN_RX_AVAIL) ||
1067             (ering->tx_pending > MAX_TX_AVAIL) ||
1068             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1069                 return -EINVAL;
1070
1071         bp->rx_ring_size = ering->rx_pending;
1072         bp->tx_ring_size = ering->tx_pending;
1073
1074         if (netif_running(dev)) {
1075                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1076                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1077         }
1078
1079         return rc;
1080 }
1081
1082 static void bnx2x_get_pauseparam(struct net_device *dev,
1083                                  struct ethtool_pauseparam *epause)
1084 {
1085         struct bnx2x *bp = netdev_priv(dev);
1086         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1087         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1088                            BNX2X_FLOW_CTRL_AUTO);
1089
1090         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1091                             BNX2X_FLOW_CTRL_RX);
1092         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1093                             BNX2X_FLOW_CTRL_TX);
1094
1095         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1096            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1097            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1098 }
1099
1100 static int bnx2x_set_pauseparam(struct net_device *dev,
1101                                 struct ethtool_pauseparam *epause)
1102 {
1103         struct bnx2x *bp = netdev_priv(dev);
1104         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1105         if (IS_MF(bp))
1106                 return 0;
1107
1108         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1109            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1110            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1111
1112         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1113
1114         if (epause->rx_pause)
1115                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1116
1117         if (epause->tx_pause)
1118                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1119
1120         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1121                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1122
1123         if (epause->autoneg) {
1124                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1125                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
1126                         return -EINVAL;
1127                 }
1128
1129                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1130                         bp->link_params.req_flow_ctrl[cfg_idx] =
1131                                 BNX2X_FLOW_CTRL_AUTO;
1132                 }
1133         }
1134
1135         DP(NETIF_MSG_LINK,
1136            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1137
1138         if (netif_running(dev)) {
1139                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1140                 bnx2x_link_set(bp);
1141         }
1142
1143         return 0;
1144 }
1145
1146 static int bnx2x_set_flags(struct net_device *dev, u32 data)
1147 {
1148         struct bnx2x *bp = netdev_priv(dev);
1149         int changed = 0;
1150         int rc = 0;
1151
1152         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1153                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1154                 return -EAGAIN;
1155         }
1156
1157         if (!(data & ETH_FLAG_RXVLAN))
1158                 return -EINVAL;
1159
1160         if ((data & ETH_FLAG_LRO) && bp->rx_csum && bp->disable_tpa)
1161                 return -EINVAL;
1162
1163         rc = ethtool_op_set_flags(dev, data, ETH_FLAG_LRO | ETH_FLAG_RXVLAN |
1164                                         ETH_FLAG_TXVLAN | ETH_FLAG_RXHASH);
1165         if (rc)
1166                 return rc;
1167
1168         /* TPA requires Rx CSUM offloading */
1169         if ((data & ETH_FLAG_LRO) && bp->rx_csum) {
1170                 if (!(bp->flags & TPA_ENABLE_FLAG)) {
1171                         bp->flags |= TPA_ENABLE_FLAG;
1172                         changed = 1;
1173                 }
1174         } else if (bp->flags & TPA_ENABLE_FLAG) {
1175                 dev->features &= ~NETIF_F_LRO;
1176                 bp->flags &= ~TPA_ENABLE_FLAG;
1177                 changed = 1;
1178         }
1179
1180         if (changed && netif_running(dev)) {
1181                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1182                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1183         }
1184
1185         return rc;
1186 }
1187
1188 static u32 bnx2x_get_rx_csum(struct net_device *dev)
1189 {
1190         struct bnx2x *bp = netdev_priv(dev);
1191
1192         return bp->rx_csum;
1193 }
1194
1195 static int bnx2x_set_rx_csum(struct net_device *dev, u32 data)
1196 {
1197         struct bnx2x *bp = netdev_priv(dev);
1198         int rc = 0;
1199
1200         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1201                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1202                 return -EAGAIN;
1203         }
1204
1205         bp->rx_csum = data;
1206
1207         /* Disable TPA, when Rx CSUM is disabled. Otherwise all
1208            TPA'ed packets will be discarded due to wrong TCP CSUM */
1209         if (!data) {
1210                 u32 flags = ethtool_op_get_flags(dev);
1211
1212                 rc = bnx2x_set_flags(dev, (flags & ~ETH_FLAG_LRO));
1213         }
1214
1215         return rc;
1216 }
1217
1218 static int bnx2x_set_tso(struct net_device *dev, u32 data)
1219 {
1220         if (data) {
1221                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
1222                 dev->features |= NETIF_F_TSO6;
1223         } else {
1224                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
1225                 dev->features &= ~NETIF_F_TSO6;
1226         }
1227
1228         return 0;
1229 }
1230
1231 static const struct {
1232         char string[ETH_GSTRING_LEN];
1233 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1234         { "register_test (offline)" },
1235         { "memory_test (offline)" },
1236         { "loopback_test (offline)" },
1237         { "nvram_test (online)" },
1238         { "interrupt_test (online)" },
1239         { "link_test (online)" },
1240         { "idle check (online)" }
1241 };
1242
1243 static int bnx2x_test_registers(struct bnx2x *bp)
1244 {
1245         int idx, i, rc = -ENODEV;
1246         u32 wr_val = 0;
1247         int port = BP_PORT(bp);
1248         static const struct {
1249                 u32 offset0;
1250                 u32 offset1;
1251                 u32 mask;
1252         } reg_tbl[] = {
1253 /* 0 */         { BRB1_REG_PAUSE_LOW_THRESHOLD_0,      4, 0x000003ff },
1254                 { DORQ_REG_DB_ADDR0,                   4, 0xffffffff },
1255                 { HC_REG_AGG_INT_0,                    4, 0x000003ff },
1256                 { PBF_REG_MAC_IF0_ENABLE,              4, 0x00000001 },
1257                 { PBF_REG_P0_INIT_CRD,                 4, 0x000007ff },
1258                 { PRS_REG_CID_PORT_0,                  4, 0x00ffffff },
1259                 { PXP2_REG_PSWRQ_CDU0_L2P,             4, 0x000fffff },
1260                 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR,    8, 0x0003ffff },
1261                 { PXP2_REG_PSWRQ_TM0_L2P,              4, 0x000fffff },
1262                 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR,   8, 0x0003ffff },
1263 /* 10 */        { PXP2_REG_PSWRQ_TSDM0_L2P,            4, 0x000fffff },
1264                 { QM_REG_CONNNUM_0,                    4, 0x000fffff },
1265                 { TM_REG_LIN0_MAX_ACTIVE_CID,          4, 0x0003ffff },
1266                 { SRC_REG_KEYRSS0_0,                  40, 0xffffffff },
1267                 { SRC_REG_KEYRSS0_7,                  40, 0xffffffff },
1268                 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1269                 { XCM_REG_WU_DA_CNT_CMD00,             4, 0x00000003 },
1270                 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0,       4, 0x000000ff },
1271                 { NIG_REG_LLH0_T_BIT,                  4, 0x00000001 },
1272                 { NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
1273 /* 20 */        { NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
1274                 { NIG_REG_XCM0_OUT_EN,                 4, 0x00000001 },
1275                 { NIG_REG_BRB0_OUT_EN,                 4, 0x00000001 },
1276                 { NIG_REG_LLH0_XCM_MASK,               4, 0x00000007 },
1277                 { NIG_REG_LLH0_ACPI_PAT_6_LEN,        68, 0x000000ff },
1278                 { NIG_REG_LLH0_ACPI_PAT_0_CRC,        68, 0xffffffff },
1279                 { NIG_REG_LLH0_DEST_MAC_0_0,         160, 0xffffffff },
1280                 { NIG_REG_LLH0_DEST_IP_0_1,          160, 0xffffffff },
1281                 { NIG_REG_LLH0_IPV4_IPV6_0,          160, 0x00000001 },
1282                 { NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
1283 /* 30 */        { NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
1284                 { NIG_REG_LLH0_VLAN_ID_0,            160, 0x00000fff },
1285                 { NIG_REG_XGXS_SERDES0_MODE_SEL,       4, 0x00000001 },
1286                 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1287                 { NIG_REG_STATUS_INTERRUPT_PORT0,      4, 0x07ffffff },
1288                 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1289                 { NIG_REG_SERDES0_CTRL_PHY_ADDR,      16, 0x0000001f },
1290
1291                 { 0xffffffff, 0, 0x00000000 }
1292         };
1293
1294         if (!netif_running(bp->dev))
1295                 return rc;
1296
1297         /* Repeat the test twice:
1298            First by writing 0x00000000, second by writing 0xffffffff */
1299         for (idx = 0; idx < 2; idx++) {
1300
1301                 switch (idx) {
1302                 case 0:
1303                         wr_val = 0;
1304                         break;
1305                 case 1:
1306                         wr_val = 0xffffffff;
1307                         break;
1308                 }
1309
1310                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1311                         u32 offset, mask, save_val, val;
1312                         if (CHIP_IS_E2(bp) &&
1313                             reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1314                                 continue;
1315
1316                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1317                         mask = reg_tbl[i].mask;
1318
1319                         save_val = REG_RD(bp, offset);
1320
1321                         REG_WR(bp, offset, (wr_val & mask));
1322
1323                         val = REG_RD(bp, offset);
1324
1325                         /* Restore the original register's value */
1326                         REG_WR(bp, offset, save_val);
1327
1328                         /* verify value is as expected */
1329                         if ((val & mask) != (wr_val & mask)) {
1330                                 DP(NETIF_MSG_PROBE,
1331                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1332                                    offset, val, wr_val, mask);
1333                                 goto test_reg_exit;
1334                         }
1335                 }
1336         }
1337
1338         rc = 0;
1339
1340 test_reg_exit:
1341         return rc;
1342 }
1343
1344 static int bnx2x_test_memory(struct bnx2x *bp)
1345 {
1346         int i, j, rc = -ENODEV;
1347         u32 val;
1348         static const struct {
1349                 u32 offset;
1350                 int size;
1351         } mem_tbl[] = {
1352                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1353                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1354                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1355                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1356                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1357                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1358                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1359
1360                 { 0xffffffff, 0 }
1361         };
1362         static const struct {
1363                 char *name;
1364                 u32 offset;
1365                 u32 e1_mask;
1366                 u32 e1h_mask;
1367                 u32 e2_mask;
1368         } prty_tbl[] = {
1369                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,   0x3ffc0, 0,   0 },
1370                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,   0x2,     0x2, 0 },
1371                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0,       0,   0 },
1372                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,   0x3ffc0, 0,   0 },
1373                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,   0x3ffc0, 0,   0 },
1374                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,   0x3ffc1, 0,   0 },
1375
1376                 { NULL, 0xffffffff, 0, 0, 0 }
1377         };
1378
1379         if (!netif_running(bp->dev))
1380                 return rc;
1381
1382         /* pre-Check the parity status */
1383         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1384                 val = REG_RD(bp, prty_tbl[i].offset);
1385                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1386                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1387                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1388                         DP(NETIF_MSG_HW,
1389                            "%s is 0x%x\n", prty_tbl[i].name, val);
1390                         goto test_mem_exit;
1391                 }
1392         }
1393
1394         /* Go through all the memories */
1395         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1396                 for (j = 0; j < mem_tbl[i].size; j++)
1397                         REG_RD(bp, mem_tbl[i].offset + j*4);
1398
1399         /* Check the parity status */
1400         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1401                 val = REG_RD(bp, prty_tbl[i].offset);
1402                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1403                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1404                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1405                         DP(NETIF_MSG_HW,
1406                            "%s is 0x%x\n", prty_tbl[i].name, val);
1407                         goto test_mem_exit;
1408                 }
1409         }
1410
1411         rc = 0;
1412
1413 test_mem_exit:
1414         return rc;
1415 }
1416
1417 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1418 {
1419         int cnt = 1400;
1420
1421         if (link_up)
1422                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1423                         msleep(10);
1424 }
1425
1426 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1427 {
1428         unsigned int pkt_size, num_pkts, i;
1429         struct sk_buff *skb;
1430         unsigned char *packet;
1431         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1432         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1433         u16 tx_start_idx, tx_idx;
1434         u16 rx_start_idx, rx_idx;
1435         u16 pkt_prod, bd_prod;
1436         struct sw_tx_bd *tx_buf;
1437         struct eth_tx_start_bd *tx_start_bd;
1438         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1439         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1440         dma_addr_t mapping;
1441         union eth_rx_cqe *cqe;
1442         u8 cqe_fp_flags;
1443         struct sw_rx_bd *rx_buf;
1444         u16 len;
1445         int rc = -ENODEV;
1446
1447         /* check the loopback mode */
1448         switch (loopback_mode) {
1449         case BNX2X_PHY_LOOPBACK:
1450                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1451                         return -EINVAL;
1452                 break;
1453         case BNX2X_MAC_LOOPBACK:
1454                 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1455                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1456                 break;
1457         default:
1458                 return -EINVAL;
1459         }
1460
1461         /* prepare the loopback packet */
1462         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1463                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1464         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1465         if (!skb) {
1466                 rc = -ENOMEM;
1467                 goto test_loopback_exit;
1468         }
1469         packet = skb_put(skb, pkt_size);
1470         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1471         memset(packet + ETH_ALEN, 0, ETH_ALEN);
1472         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1473         for (i = ETH_HLEN; i < pkt_size; i++)
1474                 packet[i] = (unsigned char) (i & 0xff);
1475
1476         /* send the loopback packet */
1477         num_pkts = 0;
1478         tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1479         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1480
1481         pkt_prod = fp_tx->tx_pkt_prod++;
1482         tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1483         tx_buf->first_bd = fp_tx->tx_bd_prod;
1484         tx_buf->skb = skb;
1485         tx_buf->flags = 0;
1486
1487         bd_prod = TX_BD(fp_tx->tx_bd_prod);
1488         tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1489         mapping = dma_map_single(&bp->pdev->dev, skb->data,
1490                                  skb_headlen(skb), DMA_TO_DEVICE);
1491         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1492         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1493         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1494         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1495         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1496         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1497         SET_FLAG(tx_start_bd->general_data,
1498                  ETH_TX_START_BD_ETH_ADDR_TYPE,
1499                  UNICAST_ADDRESS);
1500         SET_FLAG(tx_start_bd->general_data,
1501                  ETH_TX_START_BD_HDR_NBDS,
1502                  1);
1503
1504         /* turn on parsing and get a BD */
1505         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1506
1507         pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1508         pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1509
1510         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1511         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1512
1513         wmb();
1514
1515         fp_tx->tx_db.data.prod += 2;
1516         barrier();
1517         DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1518
1519         mmiowb();
1520
1521         num_pkts++;
1522         fp_tx->tx_bd_prod += 2; /* start + pbd */
1523
1524         udelay(100);
1525
1526         tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1527         if (tx_idx != tx_start_idx + num_pkts)
1528                 goto test_loopback_exit;
1529
1530         /* Unlike HC IGU won't generate an interrupt for status block
1531          * updates that have been performed while interrupts were
1532          * disabled.
1533          */
1534         if (bp->common.int_block == INT_BLOCK_IGU) {
1535                 /* Disable local BHes to prevent a dead-lock situation between
1536                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
1537                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
1538                  */
1539                 local_bh_disable();
1540                 bnx2x_tx_int(fp_tx);
1541                 local_bh_enable();
1542         }
1543
1544         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1545         if (rx_idx != rx_start_idx + num_pkts)
1546                 goto test_loopback_exit;
1547
1548         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1549         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1550         if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1551                 goto test_loopback_rx_exit;
1552
1553         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1554         if (len != pkt_size)
1555                 goto test_loopback_rx_exit;
1556
1557         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1558         skb = rx_buf->skb;
1559         skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1560         for (i = ETH_HLEN; i < pkt_size; i++)
1561                 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1562                         goto test_loopback_rx_exit;
1563
1564         rc = 0;
1565
1566 test_loopback_rx_exit:
1567
1568         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1569         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1570         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1571         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1572
1573         /* Update producers */
1574         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1575                              fp_rx->rx_sge_prod);
1576
1577 test_loopback_exit:
1578         bp->link_params.loopback_mode = LOOPBACK_NONE;
1579
1580         return rc;
1581 }
1582
1583 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1584 {
1585         int rc = 0, res;
1586
1587         if (BP_NOMCP(bp))
1588                 return rc;
1589
1590         if (!netif_running(bp->dev))
1591                 return BNX2X_LOOPBACK_FAILED;
1592
1593         bnx2x_netif_stop(bp, 1);
1594         bnx2x_acquire_phy_lock(bp);
1595
1596         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1597         if (res) {
1598                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
1599                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1600         }
1601
1602         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1603         if (res) {
1604                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
1605                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1606         }
1607
1608         bnx2x_release_phy_lock(bp);
1609         bnx2x_netif_start(bp);
1610
1611         return rc;
1612 }
1613
1614 #define CRC32_RESIDUAL                  0xdebb20e3
1615
1616 static int bnx2x_test_nvram(struct bnx2x *bp)
1617 {
1618         static const struct {
1619                 int offset;
1620                 int size;
1621         } nvram_tbl[] = {
1622                 {     0,  0x14 }, /* bootstrap */
1623                 {  0x14,  0xec }, /* dir */
1624                 { 0x100, 0x350 }, /* manuf_info */
1625                 { 0x450,  0xf0 }, /* feature_info */
1626                 { 0x640,  0x64 }, /* upgrade_key_info */
1627                 { 0x6a4,  0x64 },
1628                 { 0x708,  0x70 }, /* manuf_key_info */
1629                 { 0x778,  0x70 },
1630                 {     0,     0 }
1631         };
1632         __be32 buf[0x350 / 4];
1633         u8 *data = (u8 *)buf;
1634         int i, rc;
1635         u32 magic, crc;
1636
1637         if (BP_NOMCP(bp))
1638                 return 0;
1639
1640         rc = bnx2x_nvram_read(bp, 0, data, 4);
1641         if (rc) {
1642                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1643                 goto test_nvram_exit;
1644         }
1645
1646         magic = be32_to_cpu(buf[0]);
1647         if (magic != 0x669955aa) {
1648                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1649                 rc = -ENODEV;
1650                 goto test_nvram_exit;
1651         }
1652
1653         for (i = 0; nvram_tbl[i].size; i++) {
1654
1655                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1656                                       nvram_tbl[i].size);
1657                 if (rc) {
1658                         DP(NETIF_MSG_PROBE,
1659                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1660                         goto test_nvram_exit;
1661                 }
1662
1663                 crc = ether_crc_le(nvram_tbl[i].size, data);
1664                 if (crc != CRC32_RESIDUAL) {
1665                         DP(NETIF_MSG_PROBE,
1666                            "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1667                         rc = -ENODEV;
1668                         goto test_nvram_exit;
1669                 }
1670         }
1671
1672 test_nvram_exit:
1673         return rc;
1674 }
1675
1676 static int bnx2x_test_intr(struct bnx2x *bp)
1677 {
1678         struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1679         int i, rc;
1680
1681         if (!netif_running(bp->dev))
1682                 return -ENODEV;
1683
1684         config->hdr.length = 0;
1685         if (CHIP_IS_E1(bp))
1686                 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
1687         else
1688                 config->hdr.offset = BP_FUNC(bp);
1689         config->hdr.client_id = bp->fp->cl_id;
1690         config->hdr.reserved1 = 0;
1691
1692         bp->set_mac_pending++;
1693         smp_wmb();
1694         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
1695                            U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1696                            U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
1697         if (rc == 0) {
1698                 for (i = 0; i < 10; i++) {
1699                         if (!bp->set_mac_pending)
1700                                 break;
1701                         smp_rmb();
1702                         msleep_interruptible(10);
1703                 }
1704                 if (i == 10)
1705                         rc = -ENODEV;
1706         }
1707
1708         return rc;
1709 }
1710
1711 static void bnx2x_self_test(struct net_device *dev,
1712                             struct ethtool_test *etest, u64 *buf)
1713 {
1714         struct bnx2x *bp = netdev_priv(dev);
1715         u8 is_serdes;
1716         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1717                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1718                 etest->flags |= ETH_TEST_FL_FAILED;
1719                 return;
1720         }
1721
1722         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1723
1724         if (!netif_running(dev))
1725                 return;
1726
1727         /* offline tests are not supported in MF mode */
1728         if (IS_MF(bp))
1729                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1730         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1731
1732         if (etest->flags & ETH_TEST_FL_OFFLINE) {
1733                 int port = BP_PORT(bp);
1734                 u32 val;
1735                 u8 link_up;
1736
1737                 /* save current value of input enable for TX port IF */
1738                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1739                 /* disable input for TX port IF */
1740                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1741
1742                 link_up = bp->link_vars.link_up;
1743
1744                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1745                 bnx2x_nic_load(bp, LOAD_DIAG);
1746                 /* wait until link state is restored */
1747                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1748
1749                 if (bnx2x_test_registers(bp) != 0) {
1750                         buf[0] = 1;
1751                         etest->flags |= ETH_TEST_FL_FAILED;
1752                 }
1753                 if (bnx2x_test_memory(bp) != 0) {
1754                         buf[1] = 1;
1755                         etest->flags |= ETH_TEST_FL_FAILED;
1756                 }
1757
1758                 buf[2] = bnx2x_test_loopback(bp, link_up);
1759                 if (buf[2] != 0)
1760                         etest->flags |= ETH_TEST_FL_FAILED;
1761
1762                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1763
1764                 /* restore input for TX port IF */
1765                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1766
1767                 bnx2x_nic_load(bp, LOAD_NORMAL);
1768                 /* wait until link state is restored */
1769                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1770         }
1771         if (bnx2x_test_nvram(bp) != 0) {
1772                 buf[3] = 1;
1773                 etest->flags |= ETH_TEST_FL_FAILED;
1774         }
1775         if (bnx2x_test_intr(bp) != 0) {
1776                 buf[4] = 1;
1777                 etest->flags |= ETH_TEST_FL_FAILED;
1778         }
1779         if (bp->port.pmf)
1780                 if (bnx2x_link_test(bp, is_serdes) != 0) {
1781                         buf[5] = 1;
1782                         etest->flags |= ETH_TEST_FL_FAILED;
1783                 }
1784
1785 #ifdef BNX2X_EXTRA_DEBUG
1786         bnx2x_panic_dump(bp);
1787 #endif
1788 }
1789
1790 static const struct {
1791         long offset;
1792         int size;
1793         u8 string[ETH_GSTRING_LEN];
1794 } bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
1795 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
1796         { Q_STATS_OFFSET32(error_bytes_received_hi),
1797                                                 8, "[%d]: rx_error_bytes" },
1798         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
1799                                                 8, "[%d]: rx_ucast_packets" },
1800         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
1801                                                 8, "[%d]: rx_mcast_packets" },
1802         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
1803                                                 8, "[%d]: rx_bcast_packets" },
1804         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" },
1805         { Q_STATS_OFFSET32(rx_err_discard_pkt),
1806                                          4, "[%d]: rx_phy_ip_err_discards"},
1807         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
1808                                          4, "[%d]: rx_skb_alloc_discard" },
1809         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },
1810
1811 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" },
1812         { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
1813                                                 8, "[%d]: tx_ucast_packets" },
1814         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
1815                                                 8, "[%d]: tx_mcast_packets" },
1816         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
1817                                                 8, "[%d]: tx_bcast_packets" }
1818 };
1819
1820 static const struct {
1821         long offset;
1822         int size;
1823         u32 flags;
1824 #define STATS_FLAGS_PORT                1
1825 #define STATS_FLAGS_FUNC                2
1826 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
1827         u8 string[ETH_GSTRING_LEN];
1828 } bnx2x_stats_arr[BNX2X_NUM_STATS] = {
1829 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
1830                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
1831         { STATS_OFFSET32(error_bytes_received_hi),
1832                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
1833         { STATS_OFFSET32(total_unicast_packets_received_hi),
1834                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
1835         { STATS_OFFSET32(total_multicast_packets_received_hi),
1836                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
1837         { STATS_OFFSET32(total_broadcast_packets_received_hi),
1838                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
1839         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
1840                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
1841         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
1842                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
1843         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
1844                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
1845         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
1846                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
1847 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
1848                                 8, STATS_FLAGS_PORT, "rx_fragments" },
1849         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
1850                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
1851         { STATS_OFFSET32(no_buff_discard_hi),
1852                                 8, STATS_FLAGS_BOTH, "rx_discards" },
1853         { STATS_OFFSET32(mac_filter_discard),
1854                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
1855         { STATS_OFFSET32(xxoverflow_discard),
1856                                 4, STATS_FLAGS_PORT, "rx_fw_discards" },
1857         { STATS_OFFSET32(brb_drop_hi),
1858                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
1859         { STATS_OFFSET32(brb_truncate_hi),
1860                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
1861         { STATS_OFFSET32(pause_frames_received_hi),
1862                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
1863         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
1864                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
1865         { STATS_OFFSET32(nig_timer_max),
1866                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
1867 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
1868                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
1869         { STATS_OFFSET32(rx_skb_alloc_failed),
1870                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
1871         { STATS_OFFSET32(hw_csum_err),
1872                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
1873
1874         { STATS_OFFSET32(total_bytes_transmitted_hi),
1875                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
1876         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
1877                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
1878         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
1879                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
1880         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
1881                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
1882         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
1883                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
1884         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
1885                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
1886         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
1887                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
1888 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
1889                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
1890         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
1891                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
1892         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
1893                                 8, STATS_FLAGS_PORT, "tx_deferred" },
1894         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
1895                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
1896         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
1897                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
1898         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
1899                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
1900         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
1901                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
1902         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
1903                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
1904         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
1905                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
1906         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
1907                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
1908 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
1909                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
1910         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
1911                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
1912         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
1913                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
1914         { STATS_OFFSET32(pause_frames_sent_hi),
1915                                 8, STATS_FLAGS_PORT, "tx_pause_frames" }
1916 };
1917
1918 #define IS_PORT_STAT(i) \
1919         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1920 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1921 #define IS_MF_MODE_STAT(bp) \
1922                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1923
1924 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1925 {
1926         struct bnx2x *bp = netdev_priv(dev);
1927         int i, num_stats;
1928
1929         switch (stringset) {
1930         case ETH_SS_STATS:
1931                 if (is_multi(bp)) {
1932                         num_stats = BNX2X_NUM_Q_STATS * bp->num_queues;
1933                         if (!IS_MF_MODE_STAT(bp))
1934                                 num_stats += BNX2X_NUM_STATS;
1935                 } else {
1936                         if (IS_MF_MODE_STAT(bp)) {
1937                                 num_stats = 0;
1938                                 for (i = 0; i < BNX2X_NUM_STATS; i++)
1939                                         if (IS_FUNC_STAT(i))
1940                                                 num_stats++;
1941                         } else
1942                                 num_stats = BNX2X_NUM_STATS;
1943                 }
1944                 return num_stats;
1945
1946         case ETH_SS_TEST:
1947                 return BNX2X_NUM_TESTS;
1948
1949         default:
1950                 return -EINVAL;
1951         }
1952 }
1953
1954 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1955 {
1956         struct bnx2x *bp = netdev_priv(dev);
1957         int i, j, k;
1958
1959         switch (stringset) {
1960         case ETH_SS_STATS:
1961                 if (is_multi(bp)) {
1962                         k = 0;
1963                         for_each_queue(bp, i) {
1964                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1965                                         sprintf(buf + (k + j)*ETH_GSTRING_LEN,
1966                                                 bnx2x_q_stats_arr[j].string, i);
1967                                 k += BNX2X_NUM_Q_STATS;
1968                         }
1969                         if (IS_MF_MODE_STAT(bp))
1970                                 break;
1971                         for (j = 0; j < BNX2X_NUM_STATS; j++)
1972                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1973                                        bnx2x_stats_arr[j].string);
1974                 } else {
1975                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1976                                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
1977                                         continue;
1978                                 strcpy(buf + j*ETH_GSTRING_LEN,
1979                                        bnx2x_stats_arr[i].string);
1980                                 j++;
1981                         }
1982                 }
1983                 break;
1984
1985         case ETH_SS_TEST:
1986                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1987                 break;
1988         }
1989 }
1990
1991 static void bnx2x_get_ethtool_stats(struct net_device *dev,
1992                                     struct ethtool_stats *stats, u64 *buf)
1993 {
1994         struct bnx2x *bp = netdev_priv(dev);
1995         u32 *hw_stats, *offset;
1996         int i, j, k;
1997
1998         if (is_multi(bp)) {
1999                 k = 0;
2000                 for_each_queue(bp, i) {
2001                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
2002                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
2003                                 if (bnx2x_q_stats_arr[j].size == 0) {
2004                                         /* skip this counter */
2005                                         buf[k + j] = 0;
2006                                         continue;
2007                                 }
2008                                 offset = (hw_stats +
2009                                           bnx2x_q_stats_arr[j].offset);
2010                                 if (bnx2x_q_stats_arr[j].size == 4) {
2011                                         /* 4-byte counter */
2012                                         buf[k + j] = (u64) *offset;
2013                                         continue;
2014                                 }
2015                                 /* 8-byte counter */
2016                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
2017                         }
2018                         k += BNX2X_NUM_Q_STATS;
2019                 }
2020                 if (IS_MF_MODE_STAT(bp))
2021                         return;
2022                 hw_stats = (u32 *)&bp->eth_stats;
2023                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2024                         if (bnx2x_stats_arr[j].size == 0) {
2025                                 /* skip this counter */
2026                                 buf[k + j] = 0;
2027                                 continue;
2028                         }
2029                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
2030                         if (bnx2x_stats_arr[j].size == 4) {
2031                                 /* 4-byte counter */
2032                                 buf[k + j] = (u64) *offset;
2033                                 continue;
2034                         }
2035                         /* 8-byte counter */
2036                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
2037                 }
2038         } else {
2039                 hw_stats = (u32 *)&bp->eth_stats;
2040                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2041                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2042                                 continue;
2043                         if (bnx2x_stats_arr[i].size == 0) {
2044                                 /* skip this counter */
2045                                 buf[j] = 0;
2046                                 j++;
2047                                 continue;
2048                         }
2049                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
2050                         if (bnx2x_stats_arr[i].size == 4) {
2051                                 /* 4-byte counter */
2052                                 buf[j] = (u64) *offset;
2053                                 j++;
2054                                 continue;
2055                         }
2056                         /* 8-byte counter */
2057                         buf[j] = HILO_U64(*offset, *(offset + 1));
2058                         j++;
2059                 }
2060         }
2061 }
2062
2063 static int bnx2x_phys_id(struct net_device *dev, u32 data)
2064 {
2065         struct bnx2x *bp = netdev_priv(dev);
2066         int i;
2067
2068         if (!netif_running(dev))
2069                 return 0;
2070
2071         if (!bp->port.pmf)
2072                 return 0;
2073
2074         if (data == 0)
2075                 data = 2;
2076
2077         for (i = 0; i < (data * 2); i++) {
2078                 if ((i % 2) == 0)
2079                         bnx2x_set_led(&bp->link_params, &bp->link_vars,
2080                                       LED_MODE_OPER, SPEED_1000);
2081                 else
2082                         bnx2x_set_led(&bp->link_params, &bp->link_vars,
2083                                       LED_MODE_OFF, 0);
2084
2085                 msleep_interruptible(500);
2086                 if (signal_pending(current))
2087                         break;
2088         }
2089
2090         if (bp->link_vars.link_up)
2091                 bnx2x_set_led(&bp->link_params, &bp->link_vars, LED_MODE_OPER,
2092                               bp->link_vars.line_speed);
2093
2094         return 0;
2095 }
2096
2097 static const struct ethtool_ops bnx2x_ethtool_ops = {
2098         .get_settings           = bnx2x_get_settings,
2099         .set_settings           = bnx2x_set_settings,
2100         .get_drvinfo            = bnx2x_get_drvinfo,
2101         .get_regs_len           = bnx2x_get_regs_len,
2102         .get_regs               = bnx2x_get_regs,
2103         .get_wol                = bnx2x_get_wol,
2104         .set_wol                = bnx2x_set_wol,
2105         .get_msglevel           = bnx2x_get_msglevel,
2106         .set_msglevel           = bnx2x_set_msglevel,
2107         .nway_reset             = bnx2x_nway_reset,
2108         .get_link               = bnx2x_get_link,
2109         .get_eeprom_len         = bnx2x_get_eeprom_len,
2110         .get_eeprom             = bnx2x_get_eeprom,
2111         .set_eeprom             = bnx2x_set_eeprom,
2112         .get_coalesce           = bnx2x_get_coalesce,
2113         .set_coalesce           = bnx2x_set_coalesce,
2114         .get_ringparam          = bnx2x_get_ringparam,
2115         .set_ringparam          = bnx2x_set_ringparam,
2116         .get_pauseparam         = bnx2x_get_pauseparam,
2117         .set_pauseparam         = bnx2x_set_pauseparam,
2118         .get_rx_csum            = bnx2x_get_rx_csum,
2119         .set_rx_csum            = bnx2x_set_rx_csum,
2120         .get_tx_csum            = ethtool_op_get_tx_csum,
2121         .set_tx_csum            = ethtool_op_set_tx_hw_csum,
2122         .set_flags              = bnx2x_set_flags,
2123         .get_flags              = ethtool_op_get_flags,
2124         .get_sg                 = ethtool_op_get_sg,
2125         .set_sg                 = ethtool_op_set_sg,
2126         .get_tso                = ethtool_op_get_tso,
2127         .set_tso                = bnx2x_set_tso,
2128         .self_test              = bnx2x_self_test,
2129         .get_sset_count         = bnx2x_get_sset_count,
2130         .get_strings            = bnx2x_get_strings,
2131         .phys_id                = bnx2x_phys_id,
2132         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2133 };
2134
2135 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2136 {
2137         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2138 }