drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2008 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #include <linux/if_vlan.h>
  39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/zlib.h>
  50 #include <linux/log2.h>
  51
  52 #include "bnx2.h"
  53 #include "bnx2_fw.h"
  54 #include "bnx2_fw2.h"
  55
  56 #define FW_BUF_SIZE             0x10000
  57
  58 #define DRV_MODULE_NAME         "bnx2"
  59 #define PFX DRV_MODULE_NAME     ": "
  60 #define DRV_MODULE_VERSION      "1.8.2"
  61 #define DRV_MODULE_RELDATE      "Nov 10, 2008"
  62
  63 #define RUN_AT(x) (jiffies + (x))
  64
  65 /* Time in jiffies before concluding the transmitter is hung. */
  66 #define TX_TIMEOUT  (5*HZ)
  67
  68 static char version[] __devinitdata =
  69         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  70
  71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
  73 MODULE_LICENSE("GPL");
  74 MODULE_VERSION(DRV_MODULE_VERSION);
  75
  76 static int disable_msi = 0;
  77
  78 module_param(disable_msi, int, 0);
  79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  80
  81 typedef enum {
  82         BCM5706 = 0,
  83         NC370T,
  84         NC370I,
  85         BCM5706S,
  86         NC370F,
  87         BCM5708,
  88         BCM5708S,
  89         BCM5709,
  90         BCM5709S,
  91         BCM5716,
  92         BCM5716S,
  93 } board_t;
  94
  95 /* indexed by board_t, above */
  96 static struct {
  97         char *name;
  98 } board_info[] __devinitdata = {
  99         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
 100         { "HP NC370T Multifunction Gigabit Server Adapter" },
 101         { "HP NC370i Multifunction Gigabit Server Adapter" },
 102         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 103         { "HP NC370F Multifunction Gigabit Server Adapter" },
 104         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 105         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 106         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 107         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 108         { "Broadcom NetXtreme II BCM5716 1000Base-T" },
 109         { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
 110         };
 111
 112 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
 113         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 114           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 116           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 118           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 120           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 121         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 122           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 123         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 124           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 125         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 126           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 127         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 128           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 129         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 130           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 131         { PCI_VENDOR_ID_BROADCOM, 0x163b,
 132           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
 133         { PCI_VENDOR_ID_BROADCOM, 0x163c,
 134           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
 135         { 0, }
 136 };
 137
 138 static struct flash_spec flash_table[] =
 139 {
 140 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 141 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 142         /* Slow EEPROM */
 143         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 144          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 145          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 146          "EEPROM - slow"},
 147         /* Expansion entry 0001 */
 148         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 149          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 150          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 151          "Entry 0001"},
 152         /* Saifun SA25F010 (non-buffered flash) */
 153         /* strap, cfg1, & write1 need updates */
 154         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 155          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 156          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 157          "Non-buffered flash (128kB)"},
 158         /* Saifun SA25F020 (non-buffered flash) */
 159         /* strap, cfg1, & write1 need updates */
 160         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 161          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 162          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 163          "Non-buffered flash (256kB)"},
 164         /* Expansion entry 0100 */
 165         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 166          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 167          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 168          "Entry 0100"},
 169         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 170         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 171          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 172          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 173          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 174         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 175         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 176          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 177          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 178          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 179         /* Saifun SA25F005 (non-buffered flash) */
 180         /* strap, cfg1, & write1 need updates */
 181         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 182          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 183          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 184          "Non-buffered flash (64kB)"},
 185         /* Fast EEPROM */
 186         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 187          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 188          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 189          "EEPROM - fast"},
 190         /* Expansion entry 1001 */
 191         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 192          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 193          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 194          "Entry 1001"},
 195         /* Expansion entry 1010 */
 196         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 197          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 198          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 199          "Entry 1010"},
 200         /* ATMEL AT45DB011B (buffered flash) */
 201         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 202          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 203          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 204          "Buffered flash (128kB)"},
 205         /* Expansion entry 1100 */
 206         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 207          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 208          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 209          "Entry 1100"},
 210         /* Expansion entry 1101 */
 211         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 212          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 213          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 214          "Entry 1101"},
 215         /* Ateml Expansion entry 1110 */
 216         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 217          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 218          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 219          "Entry 1110 (Atmel)"},
 220         /* ATMEL AT45DB021B (buffered flash) */
 221         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 222          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 223          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 224          "Buffered flash (256kB)"},
 225 };
 226
 227 static struct flash_spec flash_5709 = {
 228         .flags          = BNX2_NV_BUFFERED,
 229         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 230         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 231         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 232         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 233         .name           = "5709 Buffered flash (256kB)",
 234 };
 235
 236 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 237
 238 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
 239 {
 240         u32 diff;
 241
 242         smp_mb();
 243
 244         /* The ring uses 256 indices for 255 entries, one of them
 245          * needs to be skipped.
 246          */
 247         diff = txr->tx_prod - txr->tx_cons;
 248         if (unlikely(diff >= TX_DESC_CNT)) {
 249                 diff &= 0xffff;
 250                 if (diff == TX_DESC_CNT)
 251                         diff = MAX_TX_DESC_CNT;
 252         }
 253         return (bp->tx_ring_size - diff);
 254 }
 255
 256 static u32
 257 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 258 {
 259         u32 val;
 260
 261         spin_lock_bh(&bp->indirect_lock);
 262         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 263         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 264         spin_unlock_bh(&bp->indirect_lock);
 265         return val;
 266 }
 267
 268 static void
 269 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 270 {
 271         spin_lock_bh(&bp->indirect_lock);
 272         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 273         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 274         spin_unlock_bh(&bp->indirect_lock);
 275 }
 276
 277 static void
 278 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
 279 {
 280         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
 281 }
 282
 283 static u32
 284 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
 285 {
 286         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
 287 }
 288
 289 static void
 290 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 291 {
 292         offset += cid_addr;
 293         spin_lock_bh(&bp->indirect_lock);
 294         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 295                 int i;
 296
 297                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 298                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 299                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 300                 for (i = 0; i < 5; i++) {
 301                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 302                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 303                                 break;
 304                         udelay(5);
 305                 }
 306         } else {
 307                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 308                 REG_WR(bp, BNX2_CTX_DATA, val);
 309         }
 310         spin_unlock_bh(&bp->indirect_lock);
 311 }
 312
 313 static int
 314 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 315 {
 316         u32 val1;
 317         int i, ret;
 318
 319         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 320                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 321                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 322
 323                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 324                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 325
 326                 udelay(40);
 327         }
 328
 329         val1 = (bp->phy_addr << 21) | (reg << 16) |
 330                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 331                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 332         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 333
 334         for (i = 0; i < 50; i++) {
 335                 udelay(10);
 336
 337                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 338                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 339                         udelay(5);
 340
 341                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 342                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 343
 344                         break;
 345                 }
 346         }
 347
 348         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 349                 *val = 0x0;
 350                 ret = -EBUSY;
 351         }
 352         else {
 353                 *val = val1;
 354                 ret = 0;
 355         }
 356
 357         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 358                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 359                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 360
 361                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 362                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 363
 364                 udelay(40);
 365         }
 366
 367         return ret;
 368 }
 369
 370 static int
 371 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 372 {
 373         u32 val1;
 374         int i, ret;
 375
 376         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 377                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 378                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 379
 380                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 381                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 382
 383                 udelay(40);
 384         }
 385
 386         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 387                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 388                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 389         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 390
 391         for (i = 0; i < 50; i++) {
 392                 udelay(10);
 393
 394                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 395                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 396                         udelay(5);
 397                         break;
 398                 }
 399         }
 400
 401         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 402                 ret = -EBUSY;
 403         else
 404                 ret = 0;
 405
 406         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 407                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 408                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 409
 410                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 411                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 412
 413                 udelay(40);
 414         }
 415
 416         return ret;
 417 }
 418
 419 static void
 420 bnx2_disable_int(struct bnx2 *bp)
 421 {
 422         int i;
 423         struct bnx2_napi *bnapi;
 424
 425         for (i = 0; i < bp->irq_nvecs; i++) {
 426                 bnapi = &bp->bnx2_napi[i];
 427                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 428                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 429         }
 430         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 431 }
 432
 433 static void
 434 bnx2_enable_int(struct bnx2 *bp)
 435 {
 436         int i;
 437         struct bnx2_napi *bnapi;
 438
 439         for (i = 0; i < bp->irq_nvecs; i++) {
 440                 bnapi = &bp->bnx2_napi[i];
 441
 442                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 443                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 444                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
 445                        bnapi->last_status_idx);
 446
 447                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 448                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 449                        bnapi->last_status_idx);
 450         }
 451         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 452 }
 453
 454 static void
 455 bnx2_disable_int_sync(struct bnx2 *bp)
 456 {
 457         int i;
 458
 459         atomic_inc(&bp->intr_sem);
 460         bnx2_disable_int(bp);
 461         for (i = 0; i < bp->irq_nvecs; i++)
 462                 synchronize_irq(bp->irq_tbl[i].vector);
 463 }
 464
 465 static void
 466 bnx2_napi_disable(struct bnx2 *bp)
 467 {
 468         int i;
 469
 470         for (i = 0; i < bp->irq_nvecs; i++)
 471                 napi_disable(&bp->bnx2_napi[i].napi);
 472 }
 473
 474 static void
 475 bnx2_napi_enable(struct bnx2 *bp)
 476 {
 477         int i;
 478
 479         for (i = 0; i < bp->irq_nvecs; i++)
 480                 napi_enable(&bp->bnx2_napi[i].napi);
 481 }
 482
 483 static void
 484 bnx2_netif_stop(struct bnx2 *bp)
 485 {
 486         bnx2_disable_int_sync(bp);
 487         if (netif_running(bp->dev)) {
 488                 bnx2_napi_disable(bp);
 489                 netif_tx_disable(bp->dev);
 490                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 491         }
 492 }
 493
 494 static void
 495 bnx2_netif_start(struct bnx2 *bp)
 496 {
 497         if (atomic_dec_and_test(&bp->intr_sem)) {
 498                 if (netif_running(bp->dev)) {
 499                         netif_tx_wake_all_queues(bp->dev);
 500                         bnx2_napi_enable(bp);
 501                         bnx2_enable_int(bp);
 502                 }
 503         }
 504 }
 505
 506 static void
 507 bnx2_free_tx_mem(struct bnx2 *bp)
 508 {
 509         int i;
 510
 511         for (i = 0; i < bp->num_tx_rings; i++) {
 512                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 513                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 514
 515                 if (txr->tx_desc_ring) {
 516                         pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
 517                                             txr->tx_desc_ring,
 518                                             txr->tx_desc_mapping);
 519                         txr->tx_desc_ring = NULL;
 520                 }
 521                 kfree(txr->tx_buf_ring);
 522                 txr->tx_buf_ring = NULL;
 523         }
 524 }
 525
 526 static void
 527 bnx2_free_rx_mem(struct bnx2 *bp)
 528 {
 529         int i;
 530
 531         for (i = 0; i < bp->num_rx_rings; i++) {
 532                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 533                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 534                 int j;
 535
 536                 for (j = 0; j < bp->rx_max_ring; j++) {
 537                         if (rxr->rx_desc_ring[j])
 538                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 539                                                     rxr->rx_desc_ring[j],
 540                                                     rxr->rx_desc_mapping[j]);
 541                         rxr->rx_desc_ring[j] = NULL;
 542                 }
 543                 if (rxr->rx_buf_ring)
 544                         vfree(rxr->rx_buf_ring);
 545                 rxr->rx_buf_ring = NULL;
 546
 547                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 548                         if (rxr->rx_pg_desc_ring[j])
 549                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 550                                                     rxr->rx_pg_desc_ring[i],
 551                                                     rxr->rx_pg_desc_mapping[i]);
 552                         rxr->rx_pg_desc_ring[i] = NULL;
 553                 }
 554                 if (rxr->rx_pg_ring)
 555                         vfree(rxr->rx_pg_ring);
 556                 rxr->rx_pg_ring = NULL;
 557         }
 558 }
 559
 560 static int
 561 bnx2_alloc_tx_mem(struct bnx2 *bp)
 562 {
 563         int i;
 564
 565         for (i = 0; i < bp->num_tx_rings; i++) {
 566                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 567                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 568
 569                 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
 570                 if (txr->tx_buf_ring == NULL)
 571                         return -ENOMEM;
 572
 573                 txr->tx_desc_ring =
 574                         pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
 575                                              &txr->tx_desc_mapping);
 576                 if (txr->tx_desc_ring == NULL)
 577                         return -ENOMEM;
 578         }
 579         return 0;
 580 }
 581
 582 static int
 583 bnx2_alloc_rx_mem(struct bnx2 *bp)
 584 {
 585         int i;
 586
 587         for (i = 0; i < bp->num_rx_rings; i++) {
 588                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 589                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 590                 int j;
 591
 592                 rxr->rx_buf_ring =
 593                         vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
 594                 if (rxr->rx_buf_ring == NULL)
 595                         return -ENOMEM;
 596
 597                 memset(rxr->rx_buf_ring, 0,
 598                        SW_RXBD_RING_SIZE * bp->rx_max_ring);
 599
 600                 for (j = 0; j < bp->rx_max_ring; j++) {
 601                         rxr->rx_desc_ring[j] =
 602                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 603                                                      &rxr->rx_desc_mapping[j]);
 604                         if (rxr->rx_desc_ring[j] == NULL)
 605                                 return -ENOMEM;
 606
 607                 }
 608
 609                 if (bp->rx_pg_ring_size) {
 610                         rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
 611                                                   bp->rx_max_pg_ring);
 612                         if (rxr->rx_pg_ring == NULL)
 613                                 return -ENOMEM;
 614
 615                         memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
 616                                bp->rx_max_pg_ring);
 617                 }
 618
 619                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 620                         rxr->rx_pg_desc_ring[j] =
 621                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 622                                                 &rxr->rx_pg_desc_mapping[j]);
 623                         if (rxr->rx_pg_desc_ring[j] == NULL)
 624                                 return -ENOMEM;
 625
 626                 }
 627         }
 628         return 0;
 629 }
 630
 631 static void
 632 bnx2_free_mem(struct bnx2 *bp)
 633 {
 634         int i;
 635         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 636
 637         bnx2_free_tx_mem(bp);
 638         bnx2_free_rx_mem(bp);
 639
 640         for (i = 0; i < bp->ctx_pages; i++) {
 641                 if (bp->ctx_blk[i]) {
 642                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 643                                             bp->ctx_blk[i],
 644                                             bp->ctx_blk_mapping[i]);
 645                         bp->ctx_blk[i] = NULL;
 646                 }
 647         }
 648         if (bnapi->status_blk.msi) {
 649                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 650                                     bnapi->status_blk.msi,
 651                                     bp->status_blk_mapping);
 652                 bnapi->status_blk.msi = NULL;
 653                 bp->stats_blk = NULL;
 654         }
 655 }
 656
 657 static int
 658 bnx2_alloc_mem(struct bnx2 *bp)
 659 {
 660         int i, status_blk_size, err;
 661         struct bnx2_napi *bnapi;
 662         void *status_blk;
 663
 664         /* Combine status and statistics blocks into one allocation. */
 665         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 666         if (bp->flags & BNX2_FLAG_MSIX_CAP)
 667                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
 668                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
 669         bp->status_stats_size = status_blk_size +
 670                                 sizeof(struct statistics_block);
 671
 672         status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 673                                           &bp->status_blk_mapping);
 674         if (status_blk == NULL)
 675                 goto alloc_mem_err;
 676
 677         memset(status_blk, 0, bp->status_stats_size);
 678
 679         bnapi = &bp->bnx2_napi[0];
 680         bnapi->status_blk.msi = status_blk;
 681         bnapi->hw_tx_cons_ptr =
 682                 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
 683         bnapi->hw_rx_cons_ptr =
 684                 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
 685         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
 686                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
 687                         struct status_block_msix *sblk;
 688
 689                         bnapi = &bp->bnx2_napi[i];
 690
 691                         sblk = (void *) (status_blk +
 692                                          BNX2_SBLK_MSIX_ALIGN_SIZE * i);
 693                         bnapi->status_blk.msix = sblk;
 694                         bnapi->hw_tx_cons_ptr =
 695                                 &sblk->status_tx_quick_consumer_index;
 696                         bnapi->hw_rx_cons_ptr =
 697                                 &sblk->status_rx_quick_consumer_index;
 698                         bnapi->int_num = i << 24;
 699                 }
 700         }
 701
 702         bp->stats_blk = status_blk + status_blk_size;
 703
 704         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 705
 706         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 707                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 708                 if (bp->ctx_pages == 0)
 709                         bp->ctx_pages = 1;
 710                 for (i = 0; i < bp->ctx_pages; i++) {
 711                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 712                                                 BCM_PAGE_SIZE,
 713                                                 &bp->ctx_blk_mapping[i]);
 714                         if (bp->ctx_blk[i] == NULL)
 715                                 goto alloc_mem_err;
 716                 }
 717         }
 718
 719         err = bnx2_alloc_rx_mem(bp);
 720         if (err)
 721                 goto alloc_mem_err;
 722
 723         err = bnx2_alloc_tx_mem(bp);
 724         if (err)
 725                 goto alloc_mem_err;
 726
 727         return 0;
 728
 729 alloc_mem_err:
 730         bnx2_free_mem(bp);
 731         return -ENOMEM;
 732 }
 733
 734 static void
 735 bnx2_report_fw_link(struct bnx2 *bp)
 736 {
 737         u32 fw_link_status = 0;
 738
 739         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
 740                 return;
 741
 742         if (bp->link_up) {
 743                 u32 bmsr;
 744
 745                 switch (bp->line_speed) {
 746                 case SPEED_10:
 747                         if (bp->duplex == DUPLEX_HALF)
 748                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 749                         else
 750                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 751                         break;
 752                 case SPEED_100:
 753                         if (bp->duplex == DUPLEX_HALF)
 754                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 755                         else
 756                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 757                         break;
 758                 case SPEED_1000:
 759                         if (bp->duplex == DUPLEX_HALF)
 760                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 761                         else
 762                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 763                         break;
 764                 case SPEED_2500:
 765                         if (bp->duplex == DUPLEX_HALF)
 766                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 767                         else
 768                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 769                         break;
 770                 }
 771
 772                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 773
 774                 if (bp->autoneg) {
 775                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 776
 777                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 778                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 779
 780                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 781                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
 782                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 783                         else
 784                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 785                 }
 786         }
 787         else
 788                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 789
 790         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 791 }
 792
 793 static char *
 794 bnx2_xceiver_str(struct bnx2 *bp)
 795 {
 796         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 797                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
 798                  "Copper"));
 799 }
 800
 801 static void
 802 bnx2_report_link(struct bnx2 *bp)
 803 {
 804         if (bp->link_up) {
 805                 netif_carrier_on(bp->dev);
 806                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 807                        bnx2_xceiver_str(bp));
 808
 809                 printk("%d Mbps ", bp->line_speed);
 810
 811                 if (bp->duplex == DUPLEX_FULL)
 812                         printk("full duplex");
 813                 else
 814                         printk("half duplex");
 815
 816                 if (bp->flow_ctrl) {
 817                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 818                                 printk(", receive ");
 819                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 820                                         printk("& transmit ");
 821                         }
 822                         else {
 823                                 printk(", transmit ");
 824                         }
 825                         printk("flow control ON");
 826                 }
 827                 printk("\n");
 828         }
 829         else {
 830                 netif_carrier_off(bp->dev);
 831                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 832                        bnx2_xceiver_str(bp));
 833         }
 834
 835         bnx2_report_fw_link(bp);
 836 }
 837
 838 static void
 839 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 840 {
 841         u32 local_adv, remote_adv;
 842
 843         bp->flow_ctrl = 0;
 844         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 845                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 846
 847                 if (bp->duplex == DUPLEX_FULL) {
 848                         bp->flow_ctrl = bp->req_flow_ctrl;
 849                 }
 850                 return;
 851         }
 852
 853         if (bp->duplex != DUPLEX_FULL) {
 854                 return;
 855         }
 856
 857         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
 858             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 859                 u32 val;
 860
 861                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 862                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 863                         bp->flow_ctrl |= FLOW_CTRL_TX;
 864                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 865                         bp->flow_ctrl |= FLOW_CTRL_RX;
 866                 return;
 867         }
 868
 869         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
 870         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
 871
 872         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
 873                 u32 new_local_adv = 0;
 874                 u32 new_remote_adv = 0;
 875
 876                 if (local_adv & ADVERTISE_1000XPAUSE)
 877                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 878                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 879                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 880                 if (remote_adv & ADVERTISE_1000XPAUSE)
 881                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 882                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 883                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 884
 885                 local_adv = new_local_adv;
 886                 remote_adv = new_remote_adv;
 887         }
 888
 889         /* See Table 28B-3 of 802.3ab-1999 spec. */
 890         if (local_adv & ADVERTISE_PAUSE_CAP) {
 891                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 892                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 893                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 894                         }
 895                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 896                                 bp->flow_ctrl = FLOW_CTRL_RX;
 897                         }
 898                 }
 899                 else {
 900                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 901                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 902                         }
 903                 }
 904         }
 905         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 906                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 907                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 908
 909                         bp->flow_ctrl = FLOW_CTRL_TX;
 910                 }
 911         }
 912 }
 913
 914 static int
 915 bnx2_5709s_linkup(struct bnx2 *bp)
 916 {
 917         u32 val, speed;
 918
 919         bp->link_up = 1;
 920
 921         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
 922         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
 923         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
 924
 925         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
 926                 bp->line_speed = bp->req_line_speed;
 927                 bp->duplex = bp->req_duplex;
 928                 return 0;
 929         }
 930         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
 931         switch (speed) {
 932                 case MII_BNX2_GP_TOP_AN_SPEED_10:
 933                         bp->line_speed = SPEED_10;
 934                         break;
 935                 case MII_BNX2_GP_TOP_AN_SPEED_100:
 936                         bp->line_speed = SPEED_100;
 937                         break;
 938                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
 939                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
 940                         bp->line_speed = SPEED_1000;
 941                         break;
 942                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
 943                         bp->line_speed = SPEED_2500;
 944                         break;
 945         }
 946         if (val & MII_BNX2_GP_TOP_AN_FD)
 947                 bp->duplex = DUPLEX_FULL;
 948         else
 949                 bp->duplex = DUPLEX_HALF;
 950         return 0;
 951 }
 952
 953 static int
 954 bnx2_5708s_linkup(struct bnx2 *bp)
 955 {
 956         u32 val;
 957
 958         bp->link_up = 1;
 959         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 960         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 961                 case BCM5708S_1000X_STAT1_SPEED_10:
 962                         bp->line_speed = SPEED_10;
 963                         break;
 964                 case BCM5708S_1000X_STAT1_SPEED_100:
 965                         bp->line_speed = SPEED_100;
 966                         break;
 967                 case BCM5708S_1000X_STAT1_SPEED_1G:
 968                         bp->line_speed = SPEED_1000;
 969                         break;
 970                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 971                         bp->line_speed = SPEED_2500;
 972                         break;
 973         }
 974         if (val & BCM5708S_1000X_STAT1_FD)
 975                 bp->duplex = DUPLEX_FULL;
 976         else
 977                 bp->duplex = DUPLEX_HALF;
 978
 979         return 0;
 980 }
 981
 982 static int
 983 bnx2_5706s_linkup(struct bnx2 *bp)
 984 {
 985         u32 bmcr, local_adv, remote_adv, common;
 986
 987         bp->link_up = 1;
 988         bp->line_speed = SPEED_1000;
 989
 990         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
 991         if (bmcr & BMCR_FULLDPLX) {
 992                 bp->duplex = DUPLEX_FULL;
 993         }
 994         else {
 995                 bp->duplex = DUPLEX_HALF;
 996         }
 997
 998         if (!(bmcr & BMCR_ANENABLE)) {
 999                 return 0;
1000         }
1001
1002         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1003         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1004
1005         common = local_adv & remote_adv;
1006         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1007
1008                 if (common & ADVERTISE_1000XFULL) {
1009                         bp->duplex = DUPLEX_FULL;
1010                 }
1011                 else {
1012                         bp->duplex = DUPLEX_HALF;
1013                 }
1014         }
1015
1016         return 0;
1017 }
1018
1019 static int
1020 bnx2_copper_linkup(struct bnx2 *bp)
1021 {
1022         u32 bmcr;
1023
1024         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1025         if (bmcr & BMCR_ANENABLE) {
1026                 u32 local_adv, remote_adv, common;
1027
1028                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1029                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1030
1031                 common = local_adv & (remote_adv >> 2);
1032                 if (common & ADVERTISE_1000FULL) {
1033                         bp->line_speed = SPEED_1000;
1034                         bp->duplex = DUPLEX_FULL;
1035                 }
1036                 else if (common & ADVERTISE_1000HALF) {
1037                         bp->line_speed = SPEED_1000;
1038                         bp->duplex = DUPLEX_HALF;
1039                 }
1040                 else {
1041                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1042                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1043
1044                         common = local_adv & remote_adv;
1045                         if (common & ADVERTISE_100FULL) {
1046                                 bp->line_speed = SPEED_100;
1047                                 bp->duplex = DUPLEX_FULL;
1048                         }
1049                         else if (common & ADVERTISE_100HALF) {
1050                                 bp->line_speed = SPEED_100;
1051                                 bp->duplex = DUPLEX_HALF;
1052                         }
1053                         else if (common & ADVERTISE_10FULL) {
1054                                 bp->line_speed = SPEED_10;
1055                                 bp->duplex = DUPLEX_FULL;
1056                         }
1057                         else if (common & ADVERTISE_10HALF) {
1058                                 bp->line_speed = SPEED_10;
1059                                 bp->duplex = DUPLEX_HALF;
1060                         }
1061                         else {
1062                                 bp->line_speed = 0;
1063                                 bp->link_up = 0;
1064                         }
1065                 }
1066         }
1067         else {
1068                 if (bmcr & BMCR_SPEED100) {
1069                         bp->line_speed = SPEED_100;
1070                 }
1071                 else {
1072                         bp->line_speed = SPEED_10;
1073                 }
1074                 if (bmcr & BMCR_FULLDPLX) {
1075                         bp->duplex = DUPLEX_FULL;
1076                 }
1077                 else {
1078                         bp->duplex = DUPLEX_HALF;
1079                 }
1080         }
1081
1082         return 0;
1083 }
1084
1085 static void
1086 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1087 {
1088         u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1089
1090         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1091         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1092         val |= 0x02 << 8;
1093
1094         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1095                 u32 lo_water, hi_water;
1096
1097                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1098                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1099                 else
1100                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1101                 if (lo_water >= bp->rx_ring_size)
1102                         lo_water = 0;
1103
1104                 hi_water = bp->rx_ring_size / 4;
1105
1106                 if (hi_water <= lo_water)
1107                         lo_water = 0;
1108
1109                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1110                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1111
1112                 if (hi_water > 0xf)
1113                         hi_water = 0xf;
1114                 else if (hi_water == 0)
1115                         lo_water = 0;
1116                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1117         }
1118         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1119 }
1120
1121 static void
1122 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1123 {
1124         int i;
1125         u32 cid;
1126
1127         for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1128                 if (i == 1)
1129                         cid = RX_RSS_CID;
1130                 bnx2_init_rx_context(bp, cid);
1131         }
1132 }
1133
1134 static void
1135 bnx2_set_mac_link(struct bnx2 *bp)
1136 {
1137         u32 val;
1138
1139         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1140         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1141                 (bp->duplex == DUPLEX_HALF)) {
1142                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1143         }
1144
1145         /* Configure the EMAC mode register. */
1146         val = REG_RD(bp, BNX2_EMAC_MODE);
1147
1148         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1149                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1150                 BNX2_EMAC_MODE_25G_MODE);
1151
1152         if (bp->link_up) {
1153                 switch (bp->line_speed) {
1154                         case SPEED_10:
1155                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1156                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1157                                         break;
1158                                 }
1159                                 /* fall through */
1160                         case SPEED_100:
1161                                 val |= BNX2_EMAC_MODE_PORT_MII;
1162                                 break;
1163                         case SPEED_2500:
1164                                 val |= BNX2_EMAC_MODE_25G_MODE;
1165                                 /* fall through */
1166                         case SPEED_1000:
1167                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1168                                 break;
1169                 }
1170         }
1171         else {
1172                 val |= BNX2_EMAC_MODE_PORT_GMII;
1173         }
1174
1175         /* Set the MAC to operate in the appropriate duplex mode. */
1176         if (bp->duplex == DUPLEX_HALF)
1177                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1178         REG_WR(bp, BNX2_EMAC_MODE, val);
1179
1180         /* Enable/disable rx PAUSE. */
1181         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1182
1183         if (bp->flow_ctrl & FLOW_CTRL_RX)
1184                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1185         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1186
1187         /* Enable/disable tx PAUSE. */
1188         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1189         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1190
1191         if (bp->flow_ctrl & FLOW_CTRL_TX)
1192                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1193         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1194
1195         /* Acknowledge the interrupt. */
1196         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1197
1198         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1199                 bnx2_init_all_rx_contexts(bp);
1200 }
1201
1202 static void
1203 bnx2_enable_bmsr1(struct bnx2 *bp)
1204 {
1205         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1206             (CHIP_NUM(bp) == CHIP_NUM_5709))
1207                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1208                                MII_BNX2_BLK_ADDR_GP_STATUS);
1209 }
1210
1211 static void
1212 bnx2_disable_bmsr1(struct bnx2 *bp)
1213 {
1214         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1215             (CHIP_NUM(bp) == CHIP_NUM_5709))
1216                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1217                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1218 }
1219
1220 static int
1221 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1222 {
1223         u32 up1;
1224         int ret = 1;
1225
1226         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1227                 return 0;
1228
1229         if (bp->autoneg & AUTONEG_SPEED)
1230                 bp->advertising |= ADVERTISED_2500baseX_Full;
1231
1232         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1233                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1234
1235         bnx2_read_phy(bp, bp->mii_up1, &up1);
1236         if (!(up1 & BCM5708S_UP1_2G5)) {
1237                 up1 |= BCM5708S_UP1_2G5;
1238                 bnx2_write_phy(bp, bp->mii_up1, up1);
1239                 ret = 0;
1240         }
1241
1242         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1243                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1244                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1245
1246         return ret;
1247 }
1248
1249 static int
1250 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1251 {
1252         u32 up1;
1253         int ret = 0;
1254
1255         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1256                 return 0;
1257
1258         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1259                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1260
1261         bnx2_read_phy(bp, bp->mii_up1, &up1);
1262         if (up1 & BCM5708S_UP1_2G5) {
1263                 up1 &= ~BCM5708S_UP1_2G5;
1264                 bnx2_write_phy(bp, bp->mii_up1, up1);
1265                 ret = 1;
1266         }
1267
1268         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1269                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1270                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1271
1272         return ret;
1273 }
1274
1275 static void
1276 bnx2_enable_forced_2g5(struct bnx2 *bp)
1277 {
1278         u32 bmcr;
1279
1280         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1281                 return;
1282
1283         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1284                 u32 val;
1285
1286                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1287                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1288                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1289                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1290                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1291                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1292
1293                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1294                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1295                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1296
1297         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1298                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1299                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1300         }
1301
1302         if (bp->autoneg & AUTONEG_SPEED) {
1303                 bmcr &= ~BMCR_ANENABLE;
1304                 if (bp->req_duplex == DUPLEX_FULL)
1305                         bmcr |= BMCR_FULLDPLX;
1306         }
1307         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1308 }
1309
1310 static void
1311 bnx2_disable_forced_2g5(struct bnx2 *bp)
1312 {
1313         u32 bmcr;
1314
1315         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1316                 return;
1317
1318         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1319                 u32 val;
1320
1321                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1322                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1323                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1324                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1325                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1326
1327                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1328                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1329                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1330
1331         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1332                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1333                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1334         }
1335
1336         if (bp->autoneg & AUTONEG_SPEED)
1337                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1338         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1339 }
1340
1341 static void
1342 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1343 {
1344         u32 val;
1345
1346         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1347         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1348         if (start)
1349                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1350         else
1351                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1352 }
1353
1354 static int
1355 bnx2_set_link(struct bnx2 *bp)
1356 {
1357         u32 bmsr;
1358         u8 link_up;
1359
1360         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1361                 bp->link_up = 1;
1362                 return 0;
1363         }
1364
1365         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1366                 return 0;
1367
1368         link_up = bp->link_up;
1369
1370         bnx2_enable_bmsr1(bp);
1371         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1372         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1373         bnx2_disable_bmsr1(bp);
1374
1375         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1376             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1377                 u32 val, an_dbg;
1378
1379                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1380                         bnx2_5706s_force_link_dn(bp, 0);
1381                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1382                 }
1383                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1384
1385                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1386                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1387                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1388
1389                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1390                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1391                         bmsr |= BMSR_LSTATUS;
1392                 else
1393                         bmsr &= ~BMSR_LSTATUS;
1394         }
1395
1396         if (bmsr & BMSR_LSTATUS) {
1397                 bp->link_up = 1;
1398
1399                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1400                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1401                                 bnx2_5706s_linkup(bp);
1402                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1403                                 bnx2_5708s_linkup(bp);
1404                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1405                                 bnx2_5709s_linkup(bp);
1406                 }
1407                 else {
1408                         bnx2_copper_linkup(bp);
1409                 }
1410                 bnx2_resolve_flow_ctrl(bp);
1411         }
1412         else {
1413                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1414                     (bp->autoneg & AUTONEG_SPEED))
1415                         bnx2_disable_forced_2g5(bp);
1416
1417                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1418                         u32 bmcr;
1419
1420                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1421                         bmcr |= BMCR_ANENABLE;
1422                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1423
1424                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1425                 }
1426                 bp->link_up = 0;
1427         }
1428
1429         if (bp->link_up != link_up) {
1430                 bnx2_report_link(bp);
1431         }
1432
1433         bnx2_set_mac_link(bp);
1434
1435         return 0;
1436 }
1437
1438 static int
1439 bnx2_reset_phy(struct bnx2 *bp)
1440 {
1441         int i;
1442         u32 reg;
1443
1444         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1445
1446 #define PHY_RESET_MAX_WAIT 100
1447         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1448                 udelay(10);
1449
1450                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1451                 if (!(reg & BMCR_RESET)) {
1452                         udelay(20);
1453                         break;
1454                 }
1455         }
1456         if (i == PHY_RESET_MAX_WAIT) {
1457                 return -EBUSY;
1458         }
1459         return 0;
1460 }
1461
1462 static u32
1463 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1464 {
1465         u32 adv = 0;
1466
1467         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1468                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1469
1470                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1471                         adv = ADVERTISE_1000XPAUSE;
1472                 }
1473                 else {
1474                         adv = ADVERTISE_PAUSE_CAP;
1475                 }
1476         }
1477         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1478                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1479                         adv = ADVERTISE_1000XPSE_ASYM;
1480                 }
1481                 else {
1482                         adv = ADVERTISE_PAUSE_ASYM;
1483                 }
1484         }
1485         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1486                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1487                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1488                 }
1489                 else {
1490                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1491                 }
1492         }
1493         return adv;
1494 }
1495
1496 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1497
1498 static int
1499 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1500 {
1501         u32 speed_arg = 0, pause_adv;
1502
1503         pause_adv = bnx2_phy_get_pause_adv(bp);
1504
1505         if (bp->autoneg & AUTONEG_SPEED) {
1506                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1507                 if (bp->advertising & ADVERTISED_10baseT_Half)
1508                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1509                 if (bp->advertising & ADVERTISED_10baseT_Full)
1510                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1511                 if (bp->advertising & ADVERTISED_100baseT_Half)
1512                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1513                 if (bp->advertising & ADVERTISED_100baseT_Full)
1514                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1515                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1516                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1517                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1518                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1519         } else {
1520                 if (bp->req_line_speed == SPEED_2500)
1521                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1522                 else if (bp->req_line_speed == SPEED_1000)
1523                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1524                 else if (bp->req_line_speed == SPEED_100) {
1525                         if (bp->req_duplex == DUPLEX_FULL)
1526                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1527                         else
1528                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1529                 } else if (bp->req_line_speed == SPEED_10) {
1530                         if (bp->req_duplex == DUPLEX_FULL)
1531                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1532                         else
1533                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1534                 }
1535         }
1536
1537         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1538                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1539         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1540                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1541
1542         if (port == PORT_TP)
1543                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1544                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1545
1546         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1547
1548         spin_unlock_bh(&bp->phy_lock);
1549         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1550         spin_lock_bh(&bp->phy_lock);
1551
1552         return 0;
1553 }
1554
1555 static int
1556 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1557 {
1558         u32 adv, bmcr;
1559         u32 new_adv = 0;
1560
1561         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1562                 return (bnx2_setup_remote_phy(bp, port));
1563
1564         if (!(bp->autoneg & AUTONEG_SPEED)) {
1565                 u32 new_bmcr;
1566                 int force_link_down = 0;
1567
1568                 if (bp->req_line_speed == SPEED_2500) {
1569                         if (!bnx2_test_and_enable_2g5(bp))
1570                                 force_link_down = 1;
1571                 } else if (bp->req_line_speed == SPEED_1000) {
1572                         if (bnx2_test_and_disable_2g5(bp))
1573                                 force_link_down = 1;
1574                 }
1575                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1576                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1577
1578                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1579                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1580                 new_bmcr |= BMCR_SPEED1000;
1581
1582                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1583                         if (bp->req_line_speed == SPEED_2500)
1584                                 bnx2_enable_forced_2g5(bp);
1585                         else if (bp->req_line_speed == SPEED_1000) {
1586                                 bnx2_disable_forced_2g5(bp);
1587                                 new_bmcr &= ~0x2000;
1588                         }
1589
1590                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1591                         if (bp->req_line_speed == SPEED_2500)
1592                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1593                         else
1594                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1595                 }
1596
1597                 if (bp->req_duplex == DUPLEX_FULL) {
1598                         adv |= ADVERTISE_1000XFULL;
1599                         new_bmcr |= BMCR_FULLDPLX;
1600                 }
1601                 else {
1602                         adv |= ADVERTISE_1000XHALF;
1603                         new_bmcr &= ~BMCR_FULLDPLX;
1604                 }
1605                 if ((new_bmcr != bmcr) || (force_link_down)) {
1606                         /* Force a link down visible on the other side */
1607                         if (bp->link_up) {
1608                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1609                                                ~(ADVERTISE_1000XFULL |
1610                                                  ADVERTISE_1000XHALF));
1611                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1612                                         BMCR_ANRESTART | BMCR_ANENABLE);
1613
1614                                 bp->link_up = 0;
1615                                 netif_carrier_off(bp->dev);
1616                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1617                                 bnx2_report_link(bp);
1618                         }
1619                         bnx2_write_phy(bp, bp->mii_adv, adv);
1620                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1621                 } else {
1622                         bnx2_resolve_flow_ctrl(bp);
1623                         bnx2_set_mac_link(bp);
1624                 }
1625                 return 0;
1626         }
1627
1628         bnx2_test_and_enable_2g5(bp);
1629
1630         if (bp->advertising & ADVERTISED_1000baseT_Full)
1631                 new_adv |= ADVERTISE_1000XFULL;
1632
1633         new_adv |= bnx2_phy_get_pause_adv(bp);
1634
1635         bnx2_read_phy(bp, bp->mii_adv, &adv);
1636         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1637
1638         bp->serdes_an_pending = 0;
1639         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1640                 /* Force a link down visible on the other side */
1641                 if (bp->link_up) {
1642                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1643                         spin_unlock_bh(&bp->phy_lock);
1644                         msleep(20);
1645                         spin_lock_bh(&bp->phy_lock);
1646                 }
1647
1648                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1649                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1650                         BMCR_ANENABLE);
1651                 /* Speed up link-up time when the link partner
1652                  * does not autonegotiate which is very common
1653                  * in blade servers. Some blade servers use
1654                  * IPMI for kerboard input and it's important
1655                  * to minimize link disruptions. Autoneg. involves
1656                  * exchanging base pages plus 3 next pages and
1657                  * normally completes in about 120 msec.
1658                  */
1659                 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1660                 bp->serdes_an_pending = 1;
1661                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1662         } else {
1663                 bnx2_resolve_flow_ctrl(bp);
1664                 bnx2_set_mac_link(bp);
1665         }
1666
1667         return 0;
1668 }
1669
1670 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1671         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1672                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1673                 (ADVERTISED_1000baseT_Full)
1674
1675 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1676         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1677         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1678         ADVERTISED_1000baseT_Full)
1679
1680 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1681         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1682
1683 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1684
1685 static void
1686 bnx2_set_default_remote_link(struct bnx2 *bp)
1687 {
1688         u32 link;
1689
1690         if (bp->phy_port == PORT_TP)
1691                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1692         else
1693                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1694
1695         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1696                 bp->req_line_speed = 0;
1697                 bp->autoneg |= AUTONEG_SPEED;
1698                 bp->advertising = ADVERTISED_Autoneg;
1699                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1700                         bp->advertising |= ADVERTISED_10baseT_Half;
1701                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1702                         bp->advertising |= ADVERTISED_10baseT_Full;
1703                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1704                         bp->advertising |= ADVERTISED_100baseT_Half;
1705                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1706                         bp->advertising |= ADVERTISED_100baseT_Full;
1707                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1708                         bp->advertising |= ADVERTISED_1000baseT_Full;
1709                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1710                         bp->advertising |= ADVERTISED_2500baseX_Full;
1711         } else {
1712                 bp->autoneg = 0;
1713                 bp->advertising = 0;
1714                 bp->req_duplex = DUPLEX_FULL;
1715                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1716                         bp->req_line_speed = SPEED_10;
1717                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1718                                 bp->req_duplex = DUPLEX_HALF;
1719                 }
1720                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1721                         bp->req_line_speed = SPEED_100;
1722                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1723                                 bp->req_duplex = DUPLEX_HALF;
1724                 }
1725                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1726                         bp->req_line_speed = SPEED_1000;
1727                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1728                         bp->req_line_speed = SPEED_2500;
1729         }
1730 }
1731
1732 static void
1733 bnx2_set_default_link(struct bnx2 *bp)
1734 {
1735         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1736                 bnx2_set_default_remote_link(bp);
1737                 return;
1738         }
1739
1740         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1741         bp->req_line_speed = 0;
1742         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1743                 u32 reg;
1744
1745                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1746
1747                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1748                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1749                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1750                         bp->autoneg = 0;
1751                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1752                         bp->req_duplex = DUPLEX_FULL;
1753                 }
1754         } else
1755                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1756 }
1757
1758 static void
1759 bnx2_send_heart_beat(struct bnx2 *bp)
1760 {
1761         u32 msg;
1762         u32 addr;
1763
1764         spin_lock(&bp->indirect_lock);
1765         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1766         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1767         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1768         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1769         spin_unlock(&bp->indirect_lock);
1770 }
1771
1772 static void
1773 bnx2_remote_phy_event(struct bnx2 *bp)
1774 {
1775         u32 msg;
1776         u8 link_up = bp->link_up;
1777         u8 old_port;
1778
1779         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1780
1781         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1782                 bnx2_send_heart_beat(bp);
1783
1784         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1785
1786         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1787                 bp->link_up = 0;
1788         else {
1789                 u32 speed;
1790
1791                 bp->link_up = 1;
1792                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1793                 bp->duplex = DUPLEX_FULL;
1794                 switch (speed) {
1795                         case BNX2_LINK_STATUS_10HALF:
1796                                 bp->duplex = DUPLEX_HALF;
1797                         case BNX2_LINK_STATUS_10FULL:
1798                                 bp->line_speed = SPEED_10;
1799                                 break;
1800                         case BNX2_LINK_STATUS_100HALF:
1801                                 bp->duplex = DUPLEX_HALF;
1802                         case BNX2_LINK_STATUS_100BASE_T4:
1803                         case BNX2_LINK_STATUS_100FULL:
1804                                 bp->line_speed = SPEED_100;
1805                                 break;
1806                         case BNX2_LINK_STATUS_1000HALF:
1807                                 bp->duplex = DUPLEX_HALF;
1808                         case BNX2_LINK_STATUS_1000FULL:
1809                                 bp->line_speed = SPEED_1000;
1810                                 break;
1811                         case BNX2_LINK_STATUS_2500HALF:
1812                                 bp->duplex = DUPLEX_HALF;
1813                         case BNX2_LINK_STATUS_2500FULL:
1814                                 bp->line_speed = SPEED_2500;
1815                                 break;
1816                         default:
1817                                 bp->line_speed = 0;
1818                                 break;
1819                 }
1820
1821                 bp->flow_ctrl = 0;
1822                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1823                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1824                         if (bp->duplex == DUPLEX_FULL)
1825                                 bp->flow_ctrl = bp->req_flow_ctrl;
1826                 } else {
1827                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1828                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1829                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1830                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1831                 }
1832
1833                 old_port = bp->phy_port;
1834                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1835                         bp->phy_port = PORT_FIBRE;
1836                 else
1837                         bp->phy_port = PORT_TP;
1838
1839                 if (old_port != bp->phy_port)
1840                         bnx2_set_default_link(bp);
1841
1842         }
1843         if (bp->link_up != link_up)
1844                 bnx2_report_link(bp);
1845
1846         bnx2_set_mac_link(bp);
1847 }
1848
1849 static int
1850 bnx2_set_remote_link(struct bnx2 *bp)
1851 {
1852         u32 evt_code;
1853
1854         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1855         switch (evt_code) {
1856                 case BNX2_FW_EVT_CODE_LINK_EVENT:
1857                         bnx2_remote_phy_event(bp);
1858                         break;
1859                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1860                 default:
1861                         bnx2_send_heart_beat(bp);
1862                         break;
1863         }
1864         return 0;
1865 }
1866
1867 static int
1868 bnx2_setup_copper_phy(struct bnx2 *bp)
1869 {
1870         u32 bmcr;
1871         u32 new_bmcr;
1872
1873         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1874
1875         if (bp->autoneg & AUTONEG_SPEED) {
1876                 u32 adv_reg, adv1000_reg;
1877                 u32 new_adv_reg = 0;
1878                 u32 new_adv1000_reg = 0;
1879
1880                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1881                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1882                         ADVERTISE_PAUSE_ASYM);
1883
1884                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1885                 adv1000_reg &= PHY_ALL_1000_SPEED;
1886
1887                 if (bp->advertising & ADVERTISED_10baseT_Half)
1888                         new_adv_reg |= ADVERTISE_10HALF;
1889                 if (bp->advertising & ADVERTISED_10baseT_Full)
1890                         new_adv_reg |= ADVERTISE_10FULL;
1891                 if (bp->advertising & ADVERTISED_100baseT_Half)
1892                         new_adv_reg |= ADVERTISE_100HALF;
1893                 if (bp->advertising & ADVERTISED_100baseT_Full)
1894                         new_adv_reg |= ADVERTISE_100FULL;
1895                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1896                         new_adv1000_reg |= ADVERTISE_1000FULL;
1897
1898                 new_adv_reg |= ADVERTISE_CSMA;
1899
1900                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1901
1902                 if ((adv1000_reg != new_adv1000_reg) ||
1903                         (adv_reg != new_adv_reg) ||
1904                         ((bmcr & BMCR_ANENABLE) == 0)) {
1905
1906                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1907                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1908                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1909                                 BMCR_ANENABLE);
1910                 }
1911                 else if (bp->link_up) {
1912                         /* Flow ctrl may have changed from auto to forced */
1913                         /* or vice-versa. */
1914
1915                         bnx2_resolve_flow_ctrl(bp);
1916                         bnx2_set_mac_link(bp);
1917                 }
1918                 return 0;
1919         }
1920
1921         new_bmcr = 0;
1922         if (bp->req_line_speed == SPEED_100) {
1923                 new_bmcr |= BMCR_SPEED100;
1924         }
1925         if (bp->req_duplex == DUPLEX_FULL) {
1926                 new_bmcr |= BMCR_FULLDPLX;
1927         }
1928         if (new_bmcr != bmcr) {
1929                 u32 bmsr;
1930
1931                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1932                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1933
1934                 if (bmsr & BMSR_LSTATUS) {
1935                         /* Force link down */
1936                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1937                         spin_unlock_bh(&bp->phy_lock);
1938                         msleep(50);
1939                         spin_lock_bh(&bp->phy_lock);
1940
1941                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1942                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1943                 }
1944
1945                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1946
1947                 /* Normally, the new speed is setup after the link has
1948                  * gone down and up again. In some cases, link will not go
1949                  * down so we need to set up the new speed here.
1950                  */
1951                 if (bmsr & BMSR_LSTATUS) {
1952                         bp->line_speed = bp->req_line_speed;
1953                         bp->duplex = bp->req_duplex;
1954                         bnx2_resolve_flow_ctrl(bp);
1955                         bnx2_set_mac_link(bp);
1956                 }
1957         } else {
1958                 bnx2_resolve_flow_ctrl(bp);
1959                 bnx2_set_mac_link(bp);
1960         }
1961         return 0;
1962 }
1963
1964 static int
1965 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1966 {
1967         if (bp->loopback == MAC_LOOPBACK)
1968                 return 0;
1969
1970         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1971                 return (bnx2_setup_serdes_phy(bp, port));
1972         }
1973         else {
1974                 return (bnx2_setup_copper_phy(bp));
1975         }
1976 }
1977
1978 static int
1979 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1980 {
1981         u32 val;
1982
1983         bp->mii_bmcr = MII_BMCR + 0x10;
1984         bp->mii_bmsr = MII_BMSR + 0x10;
1985         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1986         bp->mii_adv = MII_ADVERTISE + 0x10;
1987         bp->mii_lpa = MII_LPA + 0x10;
1988         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1989
1990         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1991         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1992
1993         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1994         if (reset_phy)
1995                 bnx2_reset_phy(bp);
1996
1997         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1998
1999         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2000         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2001         val |= MII_BNX2_SD_1000XCTL1_FIBER;
2002         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2003
2004         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2005         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2006         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2007                 val |= BCM5708S_UP1_2G5;
2008         else
2009                 val &= ~BCM5708S_UP1_2G5;
2010         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2011
2012         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2013         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2014         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2015         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2016
2017         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2018
2019         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2020               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2021         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2022
2023         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2024
2025         return 0;
2026 }
2027
2028 static int
2029 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2030 {
2031         u32 val;
2032
2033         if (reset_phy)
2034                 bnx2_reset_phy(bp);
2035
2036         bp->mii_up1 = BCM5708S_UP1;
2037
2038         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2039         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2040         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2041
2042         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2043         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2044         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2045
2046         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2047         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2048         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2049
2050         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2051                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2052                 val |= BCM5708S_UP1_2G5;
2053                 bnx2_write_phy(bp, BCM5708S_UP1, val);
2054         }
2055
2056         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2057             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2058             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2059                 /* increase tx signal amplitude */
2060                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2061                                BCM5708S_BLK_ADDR_TX_MISC);
2062                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2063                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2064                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2065                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2066         }
2067
2068         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2069               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2070
2071         if (val) {
2072                 u32 is_backplane;
2073
2074                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2075                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2076                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2077                                        BCM5708S_BLK_ADDR_TX_MISC);
2078                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2079                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2080                                        BCM5708S_BLK_ADDR_DIG);
2081                 }
2082         }
2083         return 0;
2084 }
2085
2086 static int
2087 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2088 {
2089         if (reset_phy)
2090                 bnx2_reset_phy(bp);
2091
2092         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2093
2094         if (CHIP_NUM(bp) == CHIP_NUM_5706)
2095                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2096
2097         if (bp->dev->mtu > 1500) {
2098                 u32 val;
2099
2100                 /* Set extended packet length bit */
2101                 bnx2_write_phy(bp, 0x18, 0x7);
2102                 bnx2_read_phy(bp, 0x18, &val);
2103                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2104
2105                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2106                 bnx2_read_phy(bp, 0x1c, &val);
2107                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2108         }
2109         else {
2110                 u32 val;
2111
2112                 bnx2_write_phy(bp, 0x18, 0x7);
2113                 bnx2_read_phy(bp, 0x18, &val);
2114                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2115
2116                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2117                 bnx2_read_phy(bp, 0x1c, &val);
2118                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2119         }
2120
2121         return 0;
2122 }
2123
2124 static int
2125 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2126 {
2127         u32 val;
2128
2129         if (reset_phy)
2130                 bnx2_reset_phy(bp);
2131
2132         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2133                 bnx2_write_phy(bp, 0x18, 0x0c00);
2134                 bnx2_write_phy(bp, 0x17, 0x000a);
2135                 bnx2_write_phy(bp, 0x15, 0x310b);
2136                 bnx2_write_phy(bp, 0x17, 0x201f);
2137                 bnx2_write_phy(bp, 0x15, 0x9506);
2138                 bnx2_write_phy(bp, 0x17, 0x401f);
2139                 bnx2_write_phy(bp, 0x15, 0x14e2);
2140                 bnx2_write_phy(bp, 0x18, 0x0400);
2141         }
2142
2143         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2144                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2145                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2146                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2147                 val &= ~(1 << 8);
2148                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2149         }
2150
2151         if (bp->dev->mtu > 1500) {
2152                 /* Set extended packet length bit */
2153                 bnx2_write_phy(bp, 0x18, 0x7);
2154                 bnx2_read_phy(bp, 0x18, &val);
2155                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2156
2157                 bnx2_read_phy(bp, 0x10, &val);
2158                 bnx2_write_phy(bp, 0x10, val | 0x1);
2159         }
2160         else {
2161                 bnx2_write_phy(bp, 0x18, 0x7);
2162                 bnx2_read_phy(bp, 0x18, &val);
2163                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2164
2165                 bnx2_read_phy(bp, 0x10, &val);
2166                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2167         }
2168
2169         /* ethernet@wirespeed */
2170         bnx2_write_phy(bp, 0x18, 0x7007);
2171         bnx2_read_phy(bp, 0x18, &val);
2172         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2173         return 0;
2174 }
2175
2176
2177 static int
2178 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2179 {
2180         u32 val;
2181         int rc = 0;
2182
2183         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2184         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2185
2186         bp->mii_bmcr = MII_BMCR;
2187         bp->mii_bmsr = MII_BMSR;
2188         bp->mii_bmsr1 = MII_BMSR;
2189         bp->mii_adv = MII_ADVERTISE;
2190         bp->mii_lpa = MII_LPA;
2191
2192         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2193
2194         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2195                 goto setup_phy;
2196
2197         bnx2_read_phy(bp, MII_PHYSID1, &val);
2198         bp->phy_id = val << 16;
2199         bnx2_read_phy(bp, MII_PHYSID2, &val);
2200         bp->phy_id |= val & 0xffff;
2201
2202         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2203                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2204                         rc = bnx2_init_5706s_phy(bp, reset_phy);
2205                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2206                         rc = bnx2_init_5708s_phy(bp, reset_phy);
2207                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2208                         rc = bnx2_init_5709s_phy(bp, reset_phy);
2209         }
2210         else {
2211                 rc = bnx2_init_copper_phy(bp, reset_phy);
2212         }
2213
2214 setup_phy:
2215         if (!rc)
2216                 rc = bnx2_setup_phy(bp, bp->phy_port);
2217
2218         return rc;
2219 }
2220
2221 static int
2222 bnx2_set_mac_loopback(struct bnx2 *bp)
2223 {
2224         u32 mac_mode;
2225
2226         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2227         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2228         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2229         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2230         bp->link_up = 1;
2231         return 0;
2232 }
2233
2234 static int bnx2_test_link(struct bnx2 *);
2235
2236 static int
2237 bnx2_set_phy_loopback(struct bnx2 *bp)
2238 {
2239         u32 mac_mode;
2240         int rc, i;
2241
2242         spin_lock_bh(&bp->phy_lock);
2243         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2244                             BMCR_SPEED1000);
2245         spin_unlock_bh(&bp->phy_lock);
2246         if (rc)
2247                 return rc;
2248
2249         for (i = 0; i < 10; i++) {
2250                 if (bnx2_test_link(bp) == 0)
2251                         break;
2252                 msleep(100);
2253         }
2254
2255         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2256         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2257                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2258                       BNX2_EMAC_MODE_25G_MODE);
2259
2260         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2261         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2262         bp->link_up = 1;
2263         return 0;
2264 }
2265
2266 static int
2267 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2268 {
2269         int i;
2270         u32 val;
2271
2272         bp->fw_wr_seq++;
2273         msg_data |= bp->fw_wr_seq;
2274
2275         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2276
2277         if (!ack)
2278                 return 0;
2279
2280         /* wait for an acknowledgement. */
2281         for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2282                 msleep(10);
2283
2284                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2285
2286                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2287                         break;
2288         }
2289         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2290                 return 0;
2291
2292         /* If we timed out, inform the firmware that this is the case. */
2293         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2294                 if (!silent)
2295                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2296                                             "%x\n", msg_data);
2297
2298                 msg_data &= ~BNX2_DRV_MSG_CODE;
2299                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2300
2301                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2302
2303                 return -EBUSY;
2304         }
2305
2306         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2307                 return -EIO;
2308
2309         return 0;
2310 }
2311
2312 static int
2313 bnx2_init_5709_context(struct bnx2 *bp)
2314 {
2315         int i, ret = 0;
2316         u32 val;
2317
2318         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2319         val |= (BCM_PAGE_BITS - 8) << 16;
2320         REG_WR(bp, BNX2_CTX_COMMAND, val);
2321         for (i = 0; i < 10; i++) {
2322                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2323                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2324                         break;
2325                 udelay(2);
2326         }
2327         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2328                 return -EBUSY;
2329
2330         for (i = 0; i < bp->ctx_pages; i++) {
2331                 int j;
2332
2333                 if (bp->ctx_blk[i])
2334                         memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2335                 else
2336                         return -ENOMEM;
2337
2338                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2339                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2340                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2341                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2342                        (u64) bp->ctx_blk_mapping[i] >> 32);
2343                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2344                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2345                 for (j = 0; j < 10; j++) {
2346
2347                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2348                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2349                                 break;
2350                         udelay(5);
2351                 }
2352                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2353                         ret = -EBUSY;
2354                         break;
2355                 }
2356         }
2357         return ret;
2358 }
2359
2360 static void
2361 bnx2_init_context(struct bnx2 *bp)
2362 {
2363         u32 vcid;
2364
2365         vcid = 96;
2366         while (vcid) {
2367                 u32 vcid_addr, pcid_addr, offset;
2368                 int i;
2369
2370                 vcid--;
2371
2372                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2373                         u32 new_vcid;
2374
2375                         vcid_addr = GET_PCID_ADDR(vcid);
2376                         if (vcid & 0x8) {
2377                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2378                         }
2379                         else {
2380                                 new_vcid = vcid;
2381                         }
2382                         pcid_addr = GET_PCID_ADDR(new_vcid);
2383                 }
2384                 else {
2385                         vcid_addr = GET_CID_ADDR(vcid);
2386                         pcid_addr = vcid_addr;
2387                 }
2388
2389                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2390                         vcid_addr += (i << PHY_CTX_SHIFT);
2391                         pcid_addr += (i << PHY_CTX_SHIFT);
2392
2393                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2394                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2395
2396                         /* Zero out the context. */
2397                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2398                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2399                 }
2400         }
2401 }
2402
2403 static int
2404 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2405 {
2406         u16 *good_mbuf;
2407         u32 good_mbuf_cnt;
2408         u32 val;
2409
2410         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2411         if (good_mbuf == NULL) {
2412                 printk(KERN_ERR PFX "Failed to allocate memory in "
2413                                     "bnx2_alloc_bad_rbuf\n");
2414                 return -ENOMEM;
2415         }
2416
2417         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2418                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2419
2420         good_mbuf_cnt = 0;
2421
2422         /* Allocate a bunch of mbufs and save the good ones in an array. */
2423         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2424         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2425                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2426                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2427
2428                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2429
2430                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2431
2432                 /* The addresses with Bit 9 set are bad memory blocks. */
2433                 if (!(val & (1 << 9))) {
2434                         good_mbuf[good_mbuf_cnt] = (u16) val;
2435                         good_mbuf_cnt++;
2436                 }
2437
2438                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2439         }
2440
2441         /* Free the good ones back to the mbuf pool thus discarding
2442          * all the bad ones. */
2443         while (good_mbuf_cnt) {
2444                 good_mbuf_cnt--;
2445
2446                 val = good_mbuf[good_mbuf_cnt];
2447                 val = (val << 9) | val | 1;
2448
2449                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2450         }
2451         kfree(good_mbuf);
2452         return 0;
2453 }
2454
2455 static void
2456 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2457 {
2458         u32 val;
2459
2460         val = (mac_addr[0] << 8) | mac_addr[1];
2461
2462         REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2463
2464         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2465                 (mac_addr[4] << 8) | mac_addr[5];
2466
2467         REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2468 }
2469
2470 static inline int
2471 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2472 {
2473         dma_addr_t mapping;
2474         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2475         struct rx_bd *rxbd =
2476                 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2477         struct page *page = alloc_page(GFP_ATOMIC);
2478
2479         if (!page)
2480                 return -ENOMEM;
2481         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2482                                PCI_DMA_FROMDEVICE);
2483         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2484                 __free_page(page);
2485                 return -EIO;
2486         }
2487
2488         rx_pg->page = page;
2489         pci_unmap_addr_set(rx_pg, mapping, mapping);
2490         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2491         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2492         return 0;
2493 }
2494
2495 static void
2496 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2497 {
2498         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2499         struct page *page = rx_pg->page;
2500
2501         if (!page)
2502                 return;
2503
2504         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2505                        PCI_DMA_FROMDEVICE);
2506
2507         __free_page(page);
2508         rx_pg->page = NULL;
2509 }
2510
2511 static inline int
2512 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2513 {
2514         struct sk_buff *skb;
2515         struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2516         dma_addr_t mapping;
2517         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2518         unsigned long align;
2519
2520         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2521         if (skb == NULL) {
2522                 return -ENOMEM;
2523         }
2524
2525         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2526                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2527
2528         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2529                 PCI_DMA_FROMDEVICE);
2530         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2531                 dev_kfree_skb(skb);
2532                 return -EIO;
2533         }
2534
2535         rx_buf->skb = skb;
2536         pci_unmap_addr_set(rx_buf, mapping, mapping);
2537
2538         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2539         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2540
2541         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2542
2543         return 0;
2544 }
2545
2546 static int
2547 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2548 {
2549         struct status_block *sblk = bnapi->status_blk.msi;
2550         u32 new_link_state, old_link_state;
2551         int is_set = 1;
2552
2553         new_link_state = sblk->status_attn_bits & event;
2554         old_link_state = sblk->status_attn_bits_ack & event;
2555         if (new_link_state != old_link_state) {
2556                 if (new_link_state)
2557                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2558                 else
2559                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2560         } else
2561                 is_set = 0;
2562
2563         return is_set;
2564 }
2565
2566 static void
2567 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2568 {
2569         spin_lock(&bp->phy_lock);
2570
2571         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2572                 bnx2_set_link(bp);
2573         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2574                 bnx2_set_remote_link(bp);
2575
2576         spin_unlock(&bp->phy_lock);
2577
2578 }
2579
2580 static inline u16
2581 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2582 {
2583         u16 cons;
2584
2585         /* Tell compiler that status block fields can change. */
2586         barrier();
2587         cons = *bnapi->hw_tx_cons_ptr;
2588         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2589                 cons++;
2590         return cons;
2591 }
2592
2593 static int
2594 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2595 {
2596         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2597         u16 hw_cons, sw_cons, sw_ring_cons;
2598         int tx_pkt = 0, index;
2599         struct netdev_queue *txq;
2600
2601         index = (bnapi - bp->bnx2_napi);
2602         txq = netdev_get_tx_queue(bp->dev, index);
2603
2604         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2605         sw_cons = txr->tx_cons;
2606
2607         while (sw_cons != hw_cons) {
2608                 struct sw_tx_bd *tx_buf;
2609                 struct sk_buff *skb;
2610                 int i, last;
2611
2612                 sw_ring_cons = TX_RING_IDX(sw_cons);
2613
2614                 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2615                 skb = tx_buf->skb;
2616
2617                 /* partial BD completions possible with TSO packets */
2618                 if (skb_is_gso(skb)) {
2619                         u16 last_idx, last_ring_idx;
2620
2621                         last_idx = sw_cons +
2622                                 skb_shinfo(skb)->nr_frags + 1;
2623                         last_ring_idx = sw_ring_cons +
2624                                 skb_shinfo(skb)->nr_frags + 1;
2625                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2626                                 last_idx++;
2627                         }
2628                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2629                                 break;
2630                         }
2631                 }
2632
2633                 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2634
2635                 tx_buf->skb = NULL;
2636                 last = skb_shinfo(skb)->nr_frags;
2637
2638                 for (i = 0; i < last; i++) {
2639                         sw_cons = NEXT_TX_BD(sw_cons);
2640                 }
2641
2642                 sw_cons = NEXT_TX_BD(sw_cons);
2643
2644                 dev_kfree_skb(skb);
2645                 tx_pkt++;
2646                 if (tx_pkt == budget)
2647                         break;
2648
2649                 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2650         }
2651
2652         txr->hw_tx_cons = hw_cons;
2653         txr->tx_cons = sw_cons;
2654
2655         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2656          * before checking for netif_tx_queue_stopped().  Without the
2657          * memory barrier, there is a small possibility that bnx2_start_xmit()
2658          * will miss it and cause the queue to be stopped forever.
2659          */
2660         smp_mb();
2661
2662         if (unlikely(netif_tx_queue_stopped(txq)) &&
2663                      (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2664                 __netif_tx_lock(txq, smp_processor_id());
2665                 if ((netif_tx_queue_stopped(txq)) &&
2666                     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2667                         netif_tx_wake_queue(txq);
2668                 __netif_tx_unlock(txq);
2669         }
2670
2671         return tx_pkt;
2672 }
2673
2674 static void
2675 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2676                         struct sk_buff *skb, int count)
2677 {
2678         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2679         struct rx_bd *cons_bd, *prod_bd;
2680         int i;
2681         u16 hw_prod, prod;
2682         u16 cons = rxr->rx_pg_cons;
2683
2684         cons_rx_pg = &rxr->rx_pg_ring[cons];
2685
2686         /* The caller was unable to allocate a new page to replace the
2687          * last one in the frags array, so we need to recycle that page
2688          * and then free the skb.
2689          */
2690         if (skb) {
2691                 struct page *page;
2692                 struct skb_shared_info *shinfo;
2693
2694                 shinfo = skb_shinfo(skb);
2695                 shinfo->nr_frags--;
2696                 page = shinfo->frags[shinfo->nr_frags].page;
2697                 shinfo->frags[shinfo->nr_frags].page = NULL;
2698
2699                 cons_rx_pg->page = page;
2700                 dev_kfree_skb(skb);
2701         }
2702
2703         hw_prod = rxr->rx_pg_prod;
2704
2705         for (i = 0; i < count; i++) {
2706                 prod = RX_PG_RING_IDX(hw_prod);
2707
2708                 prod_rx_pg = &rxr->rx_pg_ring[prod];
2709                 cons_rx_pg = &rxr->rx_pg_ring[cons];
2710                 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2711                 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2712
2713                 if (prod != cons) {
2714                         prod_rx_pg->page = cons_rx_pg->page;
2715                         cons_rx_pg->page = NULL;
2716                         pci_unmap_addr_set(prod_rx_pg, mapping,
2717                                 pci_unmap_addr(cons_rx_pg, mapping));
2718
2719                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2720                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2721
2722                 }
2723                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2724                 hw_prod = NEXT_RX_BD(hw_prod);
2725         }
2726         rxr->rx_pg_prod = hw_prod;
2727         rxr->rx_pg_cons = cons;
2728 }
2729
2730 static inline void
2731 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2732                   struct sk_buff *skb, u16 cons, u16 prod)
2733 {
2734         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2735         struct rx_bd *cons_bd, *prod_bd;
2736
2737         cons_rx_buf = &rxr->rx_buf_ring[cons];
2738         prod_rx_buf = &rxr->rx_buf_ring[prod];
2739
2740         pci_dma_sync_single_for_device(bp->pdev,
2741                 pci_unmap_addr(cons_rx_buf, mapping),
2742                 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2743
2744         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2745
2746         prod_rx_buf->skb = skb;
2747
2748         if (cons == prod)
2749                 return;
2750
2751         pci_unmap_addr_set(prod_rx_buf, mapping,
2752                         pci_unmap_addr(cons_rx_buf, mapping));
2753
2754         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2755         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2756         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2757         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2758 }
2759
2760 static int
2761 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2762             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2763             u32 ring_idx)
2764 {
2765         int err;
2766         u16 prod = ring_idx & 0xffff;
2767
2768         err = bnx2_alloc_rx_skb(bp, rxr, prod);
2769         if (unlikely(err)) {
2770                 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2771                 if (hdr_len) {
2772                         unsigned int raw_len = len + 4;
2773                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2774
2775                         bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2776                 }
2777                 return err;
2778         }
2779
2780         skb_reserve(skb, BNX2_RX_OFFSET);
2781         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2782                          PCI_DMA_FROMDEVICE);
2783
2784         if (hdr_len == 0) {
2785                 skb_put(skb, len);
2786                 return 0;
2787         } else {
2788                 unsigned int i, frag_len, frag_size, pages;
2789                 struct sw_pg *rx_pg;
2790                 u16 pg_cons = rxr->rx_pg_cons;
2791                 u16 pg_prod = rxr->rx_pg_prod;
2792
2793                 frag_size = len + 4 - hdr_len;
2794                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2795                 skb_put(skb, hdr_len);
2796
2797                 for (i = 0; i < pages; i++) {
2798                         dma_addr_t mapping_old;
2799
2800                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2801                         if (unlikely(frag_len <= 4)) {
2802                                 unsigned int tail = 4 - frag_len;
2803
2804                                 rxr->rx_pg_cons = pg_cons;
2805                                 rxr->rx_pg_prod = pg_prod;
2806                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2807                                                         pages - i);
2808                                 skb->len -= tail;
2809                                 if (i == 0) {
2810                                         skb->tail -= tail;
2811                                 } else {
2812                                         skb_frag_t *frag =
2813                                                 &skb_shinfo(skb)->frags[i - 1];
2814                                         frag->size -= tail;
2815                                         skb->data_len -= tail;
2816                                         skb->truesize -= tail;
2817                                 }
2818                                 return 0;
2819                         }
2820                         rx_pg = &rxr->rx_pg_ring[pg_cons];
2821
2822                         /* Don't unmap yet.  If we're unable to allocate a new
2823                          * page, we need to recycle the page and the DMA addr.
2824                          */
2825                         mapping_old = pci_unmap_addr(rx_pg, mapping);
2826                         if (i == pages - 1)
2827                                 frag_len -= 4;
2828
2829                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2830                         rx_pg->page = NULL;
2831
2832                         err = bnx2_alloc_rx_page(bp, rxr,
2833                                                  RX_PG_RING_IDX(pg_prod));
2834                         if (unlikely(err)) {
2835                                 rxr->rx_pg_cons = pg_cons;
2836                                 rxr->rx_pg_prod = pg_prod;
2837                                 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2838                                                         pages - i);
2839                                 return err;
2840                         }
2841
2842                         pci_unmap_page(bp->pdev, mapping_old,
2843                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
2844
2845                         frag_size -= frag_len;
2846                         skb->data_len += frag_len;
2847                         skb->truesize += frag_len;
2848                         skb->len += frag_len;
2849
2850                         pg_prod = NEXT_RX_BD(pg_prod);
2851                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2852                 }
2853                 rxr->rx_pg_prod = pg_prod;
2854                 rxr->rx_pg_cons = pg_cons;
2855         }
2856         return 0;
2857 }
2858
2859 static inline u16
2860 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2861 {
2862         u16 cons;
2863
2864         /* Tell compiler that status block fields can change. */
2865         barrier();
2866         cons = *bnapi->hw_rx_cons_ptr;
2867         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2868                 cons++;
2869         return cons;
2870 }
2871
2872 static int
2873 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2874 {
2875         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2876         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2877         struct l2_fhdr *rx_hdr;
2878         int rx_pkt = 0, pg_ring_used = 0;
2879
2880         hw_cons = bnx2_get_hw_rx_cons(bnapi);
2881         sw_cons = rxr->rx_cons;
2882         sw_prod = rxr->rx_prod;
2883
2884         /* Memory barrier necessary as speculative reads of the rx
2885          * buffer can be ahead of the index in the status block
2886          */
2887         rmb();
2888         while (sw_cons != hw_cons) {
2889                 unsigned int len, hdr_len;
2890                 u32 status;
2891                 struct sw_bd *rx_buf;
2892                 struct sk_buff *skb;
2893                 dma_addr_t dma_addr;
2894                 u16 vtag = 0;
2895                 int hw_vlan __maybe_unused = 0;
2896
2897                 sw_ring_cons = RX_RING_IDX(sw_cons);
2898                 sw_ring_prod = RX_RING_IDX(sw_prod);
2899
2900                 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2901                 skb = rx_buf->skb;
2902
2903                 rx_buf->skb = NULL;
2904
2905                 dma_addr = pci_unmap_addr(rx_buf, mapping);
2906
2907                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2908                         BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2909                         PCI_DMA_FROMDEVICE);
2910
2911                 rx_hdr = (struct l2_fhdr *) skb->data;
2912                 len = rx_hdr->l2_fhdr_pkt_len;
2913
2914                 if ((status = rx_hdr->l2_fhdr_status) &
2915                         (L2_FHDR_ERRORS_BAD_CRC |
2916                         L2_FHDR_ERRORS_PHY_DECODE |
2917                         L2_FHDR_ERRORS_ALIGNMENT |
2918                         L2_FHDR_ERRORS_TOO_SHORT |
2919                         L2_FHDR_ERRORS_GIANT_FRAME)) {
2920
2921                         bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2922                                           sw_ring_prod);
2923                         goto next_rx;
2924                 }
2925                 hdr_len = 0;
2926                 if (status & L2_FHDR_STATUS_SPLIT) {
2927                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2928                         pg_ring_used = 1;
2929                 } else if (len > bp->rx_jumbo_thresh) {
2930                         hdr_len = bp->rx_jumbo_thresh;
2931                         pg_ring_used = 1;
2932                 }
2933
2934                 len -= 4;
2935
2936                 if (len <= bp->rx_copy_thresh) {
2937                         struct sk_buff *new_skb;
2938
2939                         new_skb = netdev_alloc_skb(bp->dev, len + 6);
2940                         if (new_skb == NULL) {
2941                                 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2942                                                   sw_ring_prod);
2943                                 goto next_rx;
2944                         }
2945
2946                         /* aligned copy */
2947                         skb_copy_from_linear_data_offset(skb,
2948                                                          BNX2_RX_OFFSET - 6,
2949                                       new_skb->data, len + 6);
2950                         skb_reserve(new_skb, 6);
2951                         skb_put(new_skb, len);
2952
2953                         bnx2_reuse_rx_skb(bp, rxr, skb,
2954                                 sw_ring_cons, sw_ring_prod);
2955
2956                         skb = new_skb;
2957                 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2958                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2959                         goto next_rx;
2960
2961                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2962                     !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2963                         vtag = rx_hdr->l2_fhdr_vlan_tag;
2964 #ifdef BCM_VLAN
2965                         if (bp->vlgrp)
2966                                 hw_vlan = 1;
2967                         else
2968 #endif
2969                         {
2970                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2971                                         __skb_push(skb, 4);
2972
2973                                 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2974                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
2975                                 ve->h_vlan_TCI = htons(vtag);
2976                                 len += 4;
2977                         }
2978                 }
2979
2980                 skb->protocol = eth_type_trans(skb, bp->dev);
2981
2982                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2983                         (ntohs(skb->protocol) != 0x8100)) {
2984
2985                         dev_kfree_skb(skb);
2986                         goto next_rx;
2987
2988                 }
2989
2990                 skb->ip_summed = CHECKSUM_NONE;
2991                 if (bp->rx_csum &&
2992                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2993                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
2994
2995                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2996                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2997                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2998                 }
2999
3000 #ifdef BCM_VLAN
3001                 if (hw_vlan)
3002                         vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3003                 else
3004 #endif
3005                         netif_receive_skb(skb);
3006
3007                 rx_pkt++;
3008
3009 next_rx:
3010                 sw_cons = NEXT_RX_BD(sw_cons);
3011                 sw_prod = NEXT_RX_BD(sw_prod);
3012
3013                 if ((rx_pkt == budget))
3014                         break;
3015
3016                 /* Refresh hw_cons to see if there is new work */
3017                 if (sw_cons == hw_cons) {
3018                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3019                         rmb();
3020                 }
3021         }
3022         rxr->rx_cons = sw_cons;
3023         rxr->rx_prod = sw_prod;
3024
3025         if (pg_ring_used)
3026                 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3027
3028         REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3029
3030         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3031
3032         mmiowb();
3033
3034         return rx_pkt;
3035
3036 }
3037
3038 /* MSI ISR - The only difference between this and the INTx ISR
3039  * is that the MSI interrupt is always serviced.
3040  */
3041 static irqreturn_t
3042 bnx2_msi(int irq, void *dev_instance)
3043 {
3044         struct bnx2_napi *bnapi = dev_instance;
3045         struct bnx2 *bp = bnapi->bp;
3046         struct net_device *dev = bp->dev;
3047
3048         prefetch(bnapi->status_blk.msi);
3049         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3050                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3051                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3052
3053         /* Return here if interrupt is disabled. */
3054         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3055                 return IRQ_HANDLED;
3056
3057         netif_rx_schedule(dev, &bnapi->napi);
3058
3059         return IRQ_HANDLED;
3060 }
3061
3062 static irqreturn_t
3063 bnx2_msi_1shot(int irq, void *dev_instance)
3064 {
3065         struct bnx2_napi *bnapi = dev_instance;
3066         struct bnx2 *bp = bnapi->bp;
3067         struct net_device *dev = bp->dev;
3068
3069         prefetch(bnapi->status_blk.msi);
3070
3071         /* Return here if interrupt is disabled. */
3072         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3073                 return IRQ_HANDLED;
3074
3075         netif_rx_schedule(dev, &bnapi->napi);
3076
3077         return IRQ_HANDLED;
3078 }
3079
3080 static irqreturn_t
3081 bnx2_interrupt(int irq, void *dev_instance)
3082 {
3083         struct bnx2_napi *bnapi = dev_instance;
3084         struct bnx2 *bp = bnapi->bp;
3085         struct net_device *dev = bp->dev;
3086         struct status_block *sblk = bnapi->status_blk.msi;
3087
3088         /* When using INTx, it is possible for the interrupt to arrive
3089          * at the CPU before the status block posted prior to the
3090          * interrupt. Reading a register will flush the status block.
3091          * When using MSI, the MSI message will always complete after
3092          * the status block write.
3093          */
3094         if ((sblk->status_idx == bnapi->last_status_idx) &&
3095             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3096              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3097                 return IRQ_NONE;
3098
3099         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3100                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3101                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3102
3103         /* Read back to deassert IRQ immediately to avoid too many
3104          * spurious interrupts.
3105          */
3106         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3107
3108         /* Return here if interrupt is shared and is disabled. */
3109         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3110                 return IRQ_HANDLED;
3111
3112         if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
3113                 bnapi->last_status_idx = sblk->status_idx;
3114                 __netif_rx_schedule(dev, &bnapi->napi);
3115         }
3116
3117         return IRQ_HANDLED;
3118 }
3119
3120 static inline int
3121 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3122 {
3123         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3124         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3125
3126         if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3127             (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3128                 return 1;
3129         return 0;
3130 }
3131
3132 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
3133                                  STATUS_ATTN_BITS_TIMER_ABORT)
3134
3135 static inline int
3136 bnx2_has_work(struct bnx2_napi *bnapi)
3137 {
3138         struct status_block *sblk = bnapi->status_blk.msi;
3139
3140         if (bnx2_has_fast_work(bnapi))
3141                 return 1;
3142
3143         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3144             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3145                 return 1;
3146
3147         return 0;
3148 }
3149
3150 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3151 {
3152         struct status_block *sblk = bnapi->status_blk.msi;
3153         u32 status_attn_bits = sblk->status_attn_bits;
3154         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3155
3156         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3157             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3158
3159                 bnx2_phy_int(bp, bnapi);
3160
3161                 /* This is needed to take care of transient status
3162                  * during link changes.
3163                  */
3164                 REG_WR(bp, BNX2_HC_COMMAND,
3165                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3166                 REG_RD(bp, BNX2_HC_COMMAND);
3167         }
3168 }
3169
3170 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3171                           int work_done, int budget)
3172 {
3173         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3174         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3175
3176         if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3177                 bnx2_tx_int(bp, bnapi, 0);
3178
3179         if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3180                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3181
3182         return work_done;
3183 }
3184
3185 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3186 {
3187         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3188         struct bnx2 *bp = bnapi->bp;
3189         int work_done = 0;
3190         struct status_block_msix *sblk = bnapi->status_blk.msix;
3191
3192         while (1) {
3193                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3194                 if (unlikely(work_done >= budget))
3195                         break;
3196
3197                 bnapi->last_status_idx = sblk->status_idx;
3198                 /* status idx must be read before checking for more work. */
3199                 rmb();
3200                 if (likely(!bnx2_has_fast_work(bnapi))) {
3201
3202                         netif_rx_complete(bp->dev, napi);
3203                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3204                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3205                                bnapi->last_status_idx);
3206                         break;
3207                 }
3208         }
3209         return work_done;
3210 }
3211
3212 static int bnx2_poll(struct napi_struct *napi, int budget)
3213 {
3214         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3215         struct bnx2 *bp = bnapi->bp;
3216         int work_done = 0;
3217         struct status_block *sblk = bnapi->status_blk.msi;
3218
3219         while (1) {
3220                 bnx2_poll_link(bp, bnapi);
3221
3222                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3223
3224                 if (unlikely(work_done >= budget))
3225                         break;
3226
3227                 /* bnapi->last_status_idx is used below to tell the hw how
3228                  * much work has been processed, so we must read it before
3229                  * checking for more work.
3230                  */
3231                 bnapi->last_status_idx = sblk->status_idx;
3232                 rmb();
3233                 if (likely(!bnx2_has_work(bnapi))) {
3234                         netif_rx_complete(bp->dev, napi);
3235                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3236                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3237                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3238                                        bnapi->last_status_idx);
3239                                 break;
3240                         }
3241                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3242                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3243                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3244                                bnapi->last_status_idx);
3245
3246                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3247                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3248                                bnapi->last_status_idx);
3249                         break;
3250                 }
3251         }
3252
3253         return work_done;
3254 }
3255
3256 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3257  * from set_multicast.
3258  */
3259 static void
3260 bnx2_set_rx_mode(struct net_device *dev)
3261 {
3262         struct bnx2 *bp = netdev_priv(dev);
3263         u32 rx_mode, sort_mode;
3264         struct dev_addr_list *uc_ptr;
3265         int i;
3266
3267         if (!netif_running(dev))
3268                 return;
3269
3270         spin_lock_bh(&bp->phy_lock);
3271
3272         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3273                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3274         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3275 #ifdef BCM_VLAN
3276         if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3277                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3278 #else
3279         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3280                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3281 #endif
3282         if (dev->flags & IFF_PROMISC) {
3283                 /* Promiscuous mode. */
3284                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3285                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3286                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3287         }
3288         else if (dev->flags & IFF_ALLMULTI) {
3289                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3290                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3291                                0xffffffff);
3292                 }
3293                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3294         }
3295         else {
3296                 /* Accept one or more multicast(s). */
3297                 struct dev_mc_list *mclist;
3298                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3299                 u32 regidx;
3300                 u32 bit;
3301                 u32 crc;
3302
3303                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3304
3305                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3306                      i++, mclist = mclist->next) {
3307
3308                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3309                         bit = crc & 0xff;
3310                         regidx = (bit & 0xe0) >> 5;
3311                         bit &= 0x1f;
3312                         mc_filter[regidx] |= (1 << bit);
3313                 }
3314
3315                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3316                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3317                                mc_filter[i]);
3318                 }
3319
3320                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3321         }
3322
3323         uc_ptr = NULL;
3324         if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3325                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3326                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3327                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3328         } else if (!(dev->flags & IFF_PROMISC)) {
3329                 uc_ptr = dev->uc_list;
3330
3331                 /* Add all entries into to the match filter list */
3332                 for (i = 0; i < dev->uc_count; i++) {
3333                         bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3334                                           i + BNX2_START_UNICAST_ADDRESS_INDEX);
3335                         sort_mode |= (1 <<
3336                                       (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3337                         uc_ptr = uc_ptr->next;
3338                 }
3339
3340         }
3341
3342         if (rx_mode != bp->rx_mode) {
3343                 bp->rx_mode = rx_mode;
3344                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3345         }
3346
3347         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3348         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3349         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3350
3351         spin_unlock_bh(&bp->phy_lock);
3352 }
3353
3354 static void
3355 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3356         u32 rv2p_proc)
3357 {
3358         int i;
3359         u32 val;
3360
3361         if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3362                 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3363                 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3364                 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3365                 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3366         }
3367
3368         for (i = 0; i < rv2p_code_len; i += 8) {
3369                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3370                 rv2p_code++;
3371                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3372                 rv2p_code++;
3373
3374                 if (rv2p_proc == RV2P_PROC1) {
3375                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3376                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3377                 }
3378                 else {
3379                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3380                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3381                 }
3382         }
3383
3384         /* Reset the processor, un-stall is done later. */
3385         if (rv2p_proc == RV2P_PROC1) {
3386                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3387         }
3388         else {
3389                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3390         }
3391 }
3392
3393 static int
3394 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3395 {
3396         u32 offset;
3397         u32 val;
3398         int rc;
3399
3400         /* Halt the CPU. */
3401         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3402         val |= cpu_reg->mode_value_halt;
3403         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3404         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3405
3406         /* Load the Text area. */
3407         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3408         if (fw->gz_text) {
3409                 int j;
3410
3411                 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3412                                        fw->gz_text_len);
3413                 if (rc < 0)
3414                         return rc;
3415
3416                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3417                         bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3418                 }
3419         }
3420
3421         /* Load the Data area. */
3422         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3423         if (fw->data) {
3424                 int j;
3425
3426                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3427                         bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3428                 }
3429         }
3430
3431         /* Load the SBSS area. */
3432         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3433         if (fw->sbss_len) {
3434                 int j;
3435
3436                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3437                         bnx2_reg_wr_ind(bp, offset, 0);
3438                 }
3439         }
3440
3441         /* Load the BSS area. */
3442         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3443         if (fw->bss_len) {
3444                 int j;
3445
3446                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3447                         bnx2_reg_wr_ind(bp, offset, 0);
3448                 }
3449         }
3450
3451         /* Load the Read-Only area. */
3452         offset = cpu_reg->spad_base +
3453                 (fw->rodata_addr - cpu_reg->mips_view_base);
3454         if (fw->rodata) {
3455                 int j;
3456
3457                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3458                         bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3459                 }
3460         }
3461
3462         /* Clear the pre-fetch instruction. */
3463         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3464         bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3465
3466         /* Start the CPU. */
3467         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3468         val &= ~cpu_reg->mode_value_halt;
3469         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3470         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3471
3472         return 0;
3473 }
3474
3475 static int
3476 bnx2_init_cpus(struct bnx2 *bp)
3477 {
3478         struct fw_info *fw;
3479         int rc, rv2p_len;
3480         void *text, *rv2p;
3481
3482         /* Initialize the RV2P processor. */
3483         text = vmalloc(FW_BUF_SIZE);
3484         if (!text)
3485                 return -ENOMEM;
3486         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3487                 rv2p = bnx2_xi_rv2p_proc1;
3488                 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3489         } else {
3490                 rv2p = bnx2_rv2p_proc1;
3491                 rv2p_len = sizeof(bnx2_rv2p_proc1);
3492         }
3493         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3494         if (rc < 0)
3495                 goto init_cpu_err;
3496
3497         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3498
3499         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3500                 rv2p = bnx2_xi_rv2p_proc2;
3501                 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3502         } else {
3503                 rv2p = bnx2_rv2p_proc2;
3504                 rv2p_len = sizeof(bnx2_rv2p_proc2);
3505         }
3506         rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3507         if (rc < 0)
3508                 goto init_cpu_err;
3509
3510         load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3511
3512         /* Initialize the RX Processor. */
3513         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3514                 fw = &bnx2_rxp_fw_09;
3515         else
3516                 fw = &bnx2_rxp_fw_06;
3517
3518         fw->text = text;
3519         rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3520         if (rc)
3521                 goto init_cpu_err;
3522
3523         /* Initialize the TX Processor. */
3524         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3525                 fw = &bnx2_txp_fw_09;
3526         else
3527                 fw = &bnx2_txp_fw_06;
3528
3529         fw->text = text;
3530         rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3531         if (rc)
3532                 goto init_cpu_err;
3533
3534         /* Initialize the TX Patch-up Processor. */
3535         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3536                 fw = &bnx2_tpat_fw_09;
3537         else
3538                 fw = &bnx2_tpat_fw_06;
3539
3540         fw->text = text;
3541         rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3542         if (rc)
3543                 goto init_cpu_err;
3544
3545         /* Initialize the Completion Processor. */
3546         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3547                 fw = &bnx2_com_fw_09;
3548         else
3549                 fw = &bnx2_com_fw_06;
3550
3551         fw->text = text;
3552         rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3553         if (rc)
3554                 goto init_cpu_err;
3555
3556         /* Initialize the Command Processor. */
3557         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3558                 fw = &bnx2_cp_fw_09;
3559         else
3560                 fw = &bnx2_cp_fw_06;
3561
3562         fw->text = text;
3563         rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3564
3565 init_cpu_err:
3566         vfree(text);
3567         return rc;
3568 }
3569
3570 static int
3571 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3572 {
3573         u16 pmcsr;
3574
3575         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3576
3577         switch (state) {
3578         case PCI_D0: {
3579                 u32 val;
3580
3581                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3582                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3583                         PCI_PM_CTRL_PME_STATUS);
3584
3585                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3586                         /* delay required during transition out of D3hot */
3587                         msleep(20);
3588
3589                 val = REG_RD(bp, BNX2_EMAC_MODE);
3590                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3591                 val &= ~BNX2_EMAC_MODE_MPKT;
3592                 REG_WR(bp, BNX2_EMAC_MODE, val);
3593
3594                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3595                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3596                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3597                 break;
3598         }
3599         case PCI_D3hot: {
3600                 int i;
3601                 u32 val, wol_msg;
3602
3603                 if (bp->wol) {
3604                         u32 advertising;
3605                         u8 autoneg;
3606
3607                         autoneg = bp->autoneg;
3608                         advertising = bp->advertising;
3609
3610                         if (bp->phy_port == PORT_TP) {
3611                                 bp->autoneg = AUTONEG_SPEED;
3612                                 bp->advertising = ADVERTISED_10baseT_Half |
3613                                         ADVERTISED_10baseT_Full |
3614                                         ADVERTISED_100baseT_Half |
3615                                         ADVERTISED_100baseT_Full |
3616                                         ADVERTISED_Autoneg;
3617                         }
3618
3619                         spin_lock_bh(&bp->phy_lock);
3620                         bnx2_setup_phy(bp, bp->phy_port);
3621                         spin_unlock_bh(&bp->phy_lock);
3622
3623                         bp->autoneg = autoneg;
3624                         bp->advertising = advertising;
3625
3626                         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3627
3628                         val = REG_RD(bp, BNX2_EMAC_MODE);
3629
3630                         /* Enable port mode. */
3631                         val &= ~BNX2_EMAC_MODE_PORT;
3632                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3633                                BNX2_EMAC_MODE_ACPI_RCVD |
3634                                BNX2_EMAC_MODE_MPKT;
3635                         if (bp->phy_port == PORT_TP)
3636                                 val |= BNX2_EMAC_MODE_PORT_MII;
3637                         else {
3638                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3639                                 if (bp->line_speed == SPEED_2500)
3640                                         val |= BNX2_EMAC_MODE_25G_MODE;
3641                         }
3642
3643                         REG_WR(bp, BNX2_EMAC_MODE, val);
3644
3645                         /* receive all multicast */
3646                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3647                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3648                                        0xffffffff);
3649                         }
3650                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3651                                BNX2_EMAC_RX_MODE_SORT_MODE);
3652
3653                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3654                               BNX2_RPM_SORT_USER0_MC_EN;
3655                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3656                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3657                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3658                                BNX2_RPM_SORT_USER0_ENA);
3659
3660                         /* Need to enable EMAC and RPM for WOL. */
3661                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3662                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3663                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3664                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3665
3666                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3667                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3668                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3669
3670                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3671                 }
3672                 else {
3673                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3674                 }
3675
3676                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3677                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3678                                      1, 0);
3679
3680                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3681                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3682                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3683
3684                         if (bp->wol)
3685                                 pmcsr |= 3;
3686                 }
3687                 else {
3688                         pmcsr |= 3;
3689                 }
3690                 if (bp->wol) {
3691                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3692                 }
3693                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3694                                       pmcsr);
3695
3696                 /* No more memory access after this point until
3697                  * device is brought back to D0.
3698                  */
3699                 udelay(50);
3700                 break;
3701         }
3702         default:
3703                 return -EINVAL;
3704         }
3705         return 0;
3706 }
3707
3708 static int
3709 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3710 {
3711         u32 val;
3712         int j;
3713
3714         /* Request access to the flash interface. */
3715         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3716         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3717                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3718                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3719                         break;
3720
3721                 udelay(5);
3722         }
3723
3724         if (j >= NVRAM_TIMEOUT_COUNT)
3725                 return -EBUSY;
3726
3727         return 0;
3728 }
3729
3730 static int
3731 bnx2_release_nvram_lock(struct bnx2 *bp)
3732 {
3733         int j;
3734         u32 val;
3735
3736         /* Relinquish nvram interface. */
3737         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3738
3739         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3740                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3741                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3742                         break;
3743
3744                 udelay(5);
3745         }
3746
3747         if (j >= NVRAM_TIMEOUT_COUNT)
3748                 return -EBUSY;
3749
3750         return 0;
3751 }
3752
3753
3754 static int
3755 bnx2_enable_nvram_write(struct bnx2 *bp)
3756 {
3757         u32 val;
3758
3759         val = REG_RD(bp, BNX2_MISC_CFG);
3760         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3761
3762         if (bp->flash_info->flags & BNX2_NV_WREN) {
3763                 int j;
3764
3765                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3766                 REG_WR(bp, BNX2_NVM_COMMAND,
3767                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3768
3769                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3770                         udelay(5);
3771
3772                         val = REG_RD(bp, BNX2_NVM_COMMAND);
3773                         if (val & BNX2_NVM_COMMAND_DONE)
3774                                 break;
3775                 }
3776
3777                 if (j >= NVRAM_TIMEOUT_COUNT)
3778                         return -EBUSY;
3779         }
3780         return 0;
3781 }
3782
3783 static void
3784 bnx2_disable_nvram_write(struct bnx2 *bp)
3785 {
3786         u32 val;
3787
3788         val = REG_RD(bp, BNX2_MISC_CFG);
3789         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3790 }
3791
3792
3793 static void
3794 bnx2_enable_nvram_access(struct bnx2 *bp)
3795 {
3796         u32 val;
3797
3798         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3799         /* Enable both bits, even on read. */
3800         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3801                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3802 }
3803
3804 static void
3805 bnx2_disable_nvram_access(struct bnx2 *bp)
3806 {
3807         u32 val;
3808
3809         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3810         /* Disable both bits, even after read. */
3811         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3812                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3813                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
3814 }
3815
3816 static int
3817 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3818 {
3819         u32 cmd;
3820         int j;
3821
3822         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3823                 /* Buffered flash, no erase needed */
3824                 return 0;
3825
3826         /* Build an erase command */
3827         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3828               BNX2_NVM_COMMAND_DOIT;
3829
3830         /* Need to clear DONE bit separately. */
3831         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3832
3833         /* Address of the NVRAM to read from. */
3834         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3835
3836         /* Issue an erase command. */
3837         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3838
3839         /* Wait for completion. */
3840         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3841                 u32 val;
3842
3843                 udelay(5);
3844
3845                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3846                 if (val & BNX2_NVM_COMMAND_DONE)
3847                         break;
3848         }
3849
3850         if (j >= NVRAM_TIMEOUT_COUNT)
3851                 return -EBUSY;
3852
3853         return 0;
3854 }
3855
3856 static int
3857 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3858 {
3859         u32 cmd;
3860         int j;
3861
3862         /* Build the command word. */
3863         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3864
3865         /* Calculate an offset of a buffered flash, not needed for 5709. */
3866         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3867                 offset = ((offset / bp->flash_info->page_size) <<
3868                            bp->flash_info->page_bits) +
3869                           (offset % bp->flash_info->page_size);
3870         }
3871
3872         /* Need to clear DONE bit separately. */
3873         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3874
3875         /* Address of the NVRAM to read from. */
3876         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3877
3878         /* Issue a read command. */
3879         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3880
3881         /* Wait for completion. */
3882         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3883                 u32 val;
3884
3885                 udelay(5);
3886
3887                 val = REG_RD(bp, BNX2_NVM_COMMAND);
3888                 if (val & BNX2_NVM_COMMAND_DONE) {
3889                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3890                         memcpy(ret_val, &v, 4);
3891                         break;
3892                 }
3893         }
3894         if (j >= NVRAM_TIMEOUT_COUNT)
3895                 return -EBUSY;
3896
3897         return 0;
3898 }
3899
3900
3901 static int
3902 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3903 {
3904         u32 cmd;
3905         __be32 val32;
3906         int j;
3907
3908         /* Build the command word. */
3909         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3910
3911         /* Calculate an offset of a buffered flash, not needed for 5709. */
3912         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3913                 offset = ((offset / bp->flash_info->page_size) <<
3914                           bp->flash_info->page_bits) +
3915                          (offset % bp->flash_info->page_size);
3916         }
3917
3918         /* Need to clear DONE bit separately. */
3919         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3920
3921         memcpy(&val32, val, 4);
3922
3923         /* Write the data. */
3924         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3925
3926         /* Address of the NVRAM to write to. */
3927         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3928
3929         /* Issue the write command. */
3930         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3931
3932         /* Wait for completion. */
3933         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3934                 udelay(5);
3935
3936                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3937                         break;
3938         }
3939         if (j >= NVRAM_TIMEOUT_COUNT)
3940                 return -EBUSY;
3941
3942         return 0;
3943 }
3944
3945 static int
3946 bnx2_init_nvram(struct bnx2 *bp)
3947 {
3948         u32 val;
3949         int j, entry_count, rc = 0;
3950         struct flash_spec *flash;
3951
3952         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3953                 bp->flash_info = &flash_5709;
3954                 goto get_flash_size;
3955         }
3956
3957         /* Determine the selected interface. */
3958         val = REG_RD(bp, BNX2_NVM_CFG1);
3959
3960         entry_count = ARRAY_SIZE(flash_table);
3961
3962         if (val & 0x40000000) {
3963
3964                 /* Flash interface has been reconfigured */
3965                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3966                      j++, flash++) {
3967                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
3968                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3969                                 bp->flash_info = flash;
3970                                 break;
3971                         }
3972                 }
3973         }
3974         else {
3975                 u32 mask;
3976                 /* Not yet been reconfigured */
3977
3978                 if (val & (1 << 23))
3979                         mask = FLASH_BACKUP_STRAP_MASK;
3980                 else
3981                         mask = FLASH_STRAP_MASK;
3982
3983                 for (j = 0, flash = &flash_table[0]; j < entry_count;
3984                         j++, flash++) {
3985
3986                         if ((val & mask) == (flash->strapping & mask)) {
3987                                 bp->flash_info = flash;
3988
3989                                 /* Request access to the flash interface. */
3990                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3991                                         return rc;
3992
3993                                 /* Enable access to flash interface */
3994                                 bnx2_enable_nvram_access(bp);
3995
3996                                 /* Reconfigure the flash interface */
3997                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3998                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3999                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4000                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4001
4002                                 /* Disable access to flash interface */
4003                                 bnx2_disable_nvram_access(bp);
4004                                 bnx2_release_nvram_lock(bp);
4005
4006                                 break;
4007                         }
4008                 }
4009         } /* if (val & 0x40000000) */
4010
4011         if (j == entry_count) {
4012                 bp->flash_info = NULL;
4013                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4014                 return -ENODEV;
4015         }
4016
4017 get_flash_size:
4018         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4019         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4020         if (val)
4021                 bp->flash_size = val;
4022         else
4023                 bp->flash_size = bp->flash_info->total_size;
4024
4025         return rc;
4026 }
4027
4028 static int
4029 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4030                 int buf_size)
4031 {
4032         int rc = 0;
4033         u32 cmd_flags, offset32, len32, extra;
4034
4035         if (buf_size == 0)
4036                 return 0;
4037
4038         /* Request access to the flash interface. */
4039         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4040                 return rc;
4041
4042         /* Enable access to flash interface */
4043         bnx2_enable_nvram_access(bp);
4044
4045         len32 = buf_size;
4046         offset32 = offset;
4047         extra = 0;
4048
4049         cmd_flags = 0;
4050
4051         if (offset32 & 3) {
4052                 u8 buf[4];
4053                 u32 pre_len;
4054
4055                 offset32 &= ~3;
4056                 pre_len = 4 - (offset & 3);
4057
4058                 if (pre_len >= len32) {
4059                         pre_len = len32;
4060                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4061                                     BNX2_NVM_COMMAND_LAST;
4062                 }
4063                 else {
4064                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4065                 }
4066
4067                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4068
4069                 if (rc)
4070                         return rc;
4071
4072                 memcpy(ret_buf, buf + (offset & 3), pre_len);
4073
4074                 offset32 += 4;
4075                 ret_buf += pre_len;
4076                 len32 -= pre_len;
4077         }
4078         if (len32 & 3) {
4079                 extra = 4 - (len32 & 3);
4080                 len32 = (len32 + 4) & ~3;
4081         }
4082
4083         if (len32 == 4) {
4084                 u8 buf[4];
4085
4086                 if (cmd_flags)
4087                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4088                 else
4089                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4090                                     BNX2_NVM_COMMAND_LAST;
4091
4092                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4093
4094                 memcpy(ret_buf, buf, 4 - extra);
4095         }
4096         else if (len32 > 0) {
4097                 u8 buf[4];
4098
4099                 /* Read the first word. */
4100                 if (cmd_flags)
4101                         cmd_flags = 0;
4102                 else
4103                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4104
4105                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4106
4107                 /* Advance to the next dword. */
4108                 offset32 += 4;
4109                 ret_buf += 4;
4110                 len32 -= 4;
4111
4112                 while (len32 > 4 && rc == 0) {
4113                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4114
4115                         /* Advance to the next dword. */
4116                         offset32 += 4;
4117                         ret_buf += 4;
4118                         len32 -= 4;
4119                 }
4120
4121                 if (rc)
4122                         return rc;
4123
4124                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4125                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4126
4127                 memcpy(ret_buf, buf, 4 - extra);
4128         }
4129
4130         /* Disable access to flash interface */
4131         bnx2_disable_nvram_access(bp);
4132
4133         bnx2_release_nvram_lock(bp);
4134
4135         return rc;
4136 }
4137
4138 static int
4139 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4140                 int buf_size)
4141 {
4142         u32 written, offset32, len32;
4143         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4144         int rc = 0;
4145         int align_start, align_end;
4146
4147         buf = data_buf;
4148         offset32 = offset;
4149         len32 = buf_size;
4150         align_start = align_end = 0;
4151
4152         if ((align_start = (offset32 & 3))) {
4153                 offset32 &= ~3;
4154                 len32 += align_start;
4155                 if (len32 < 4)
4156                         len32 = 4;
4157                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4158                         return rc;
4159         }
4160
4161         if (len32 & 3) {
4162                 align_end = 4 - (len32 & 3);
4163                 len32 += align_end;
4164                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4165                         return rc;
4166         }
4167
4168         if (align_start || align_end) {
4169                 align_buf = kmalloc(len32, GFP_KERNEL);
4170                 if (align_buf == NULL)
4171                         return -ENOMEM;
4172                 if (align_start) {
4173                         memcpy(align_buf, start, 4);
4174                 }
4175                 if (align_end) {
4176                         memcpy(align_buf + len32 - 4, end, 4);
4177                 }
4178                 memcpy(align_buf + align_start, data_buf, buf_size);
4179                 buf = align_buf;
4180         }
4181
4182         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4183                 flash_buffer = kmalloc(264, GFP_KERNEL);
4184                 if (flash_buffer == NULL) {
4185                         rc = -ENOMEM;
4186                         goto nvram_write_end;
4187                 }
4188         }
4189
4190         written = 0;
4191         while ((written < len32) && (rc == 0)) {
4192                 u32 page_start, page_end, data_start, data_end;
4193                 u32 addr, cmd_flags;
4194                 int i;
4195
4196                 /* Find the page_start addr */
4197                 page_start = offset32 + written;
4198                 page_start -= (page_start % bp->flash_info->page_size);
4199                 /* Find the page_end addr */
4200                 page_end = page_start + bp->flash_info->page_size;
4201                 /* Find the data_start addr */
4202                 data_start = (written == 0) ? offset32 : page_start;
4203                 /* Find the data_end addr */
4204                 data_end = (page_end > offset32 + len32) ?
4205                         (offset32 + len32) : page_end;
4206
4207                 /* Request access to the flash interface. */
4208                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4209                         goto nvram_write_end;
4210
4211                 /* Enable access to flash interface */
4212                 bnx2_enable_nvram_access(bp);
4213
4214                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4215                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4216                         int j;
4217
4218                         /* Read the whole page into the buffer
4219                          * (non-buffer flash only) */
4220                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4221                                 if (j == (bp->flash_info->page_size - 4)) {
4222                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4223                                 }
4224                                 rc = bnx2_nvram_read_dword(bp,
4225                                         page_start + j,
4226                                         &flash_buffer[j],
4227                                         cmd_flags);
4228
4229                                 if (rc)
4230                                         goto nvram_write_end;
4231
4232                                 cmd_flags = 0;
4233                         }
4234                 }
4235
4236                 /* Enable writes to flash interface (unlock write-protect) */
4237                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4238                         goto nvram_write_end;
4239
4240                 /* Loop to write back the buffer data from page_start to
4241                  * data_start */
4242                 i = 0;
4243                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4244                         /* Erase the page */
4245                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4246                                 goto nvram_write_end;
4247
4248                         /* Re-enable the write again for the actual write */
4249                         bnx2_enable_nvram_write(bp);
4250
4251                         for (addr = page_start; addr < data_start;
4252                                 addr += 4, i += 4) {
4253
4254                                 rc = bnx2_nvram_write_dword(bp, addr,
4255                                         &flash_buffer[i], cmd_flags);
4256
4257                                 if (rc != 0)
4258                                         goto nvram_write_end;
4259
4260                                 cmd_flags = 0;
4261                         }
4262                 }
4263
4264                 /* Loop to write the new data from data_start to data_end */
4265                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4266                         if ((addr == page_end - 4) ||
4267                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4268                                  (addr == data_end - 4))) {
4269
4270                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4271                         }
4272                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4273                                 cmd_flags);
4274
4275                         if (rc != 0)
4276                                 goto nvram_write_end;
4277
4278                         cmd_flags = 0;
4279                         buf += 4;
4280                 }
4281
4282                 /* Loop to write back the buffer data from data_end
4283                  * to page_end */
4284                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4285                         for (addr = data_end; addr < page_end;
4286                                 addr += 4, i += 4) {
4287
4288                                 if (addr == page_end-4) {
4289                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4290                                 }
4291                                 rc = bnx2_nvram_write_dword(bp, addr,
4292                                         &flash_buffer[i], cmd_flags);
4293
4294                                 if (rc != 0)
4295                                         goto nvram_write_end;
4296
4297                                 cmd_flags = 0;
4298                         }
4299                 }
4300
4301                 /* Disable writes to flash interface (lock write-protect) */
4302                 bnx2_disable_nvram_write(bp);
4303
4304                 /* Disable access to flash interface */
4305                 bnx2_disable_nvram_access(bp);
4306                 bnx2_release_nvram_lock(bp);
4307
4308                 /* Increment written */
4309                 written += data_end - data_start;
4310         }
4311
4312 nvram_write_end:
4313         kfree(flash_buffer);
4314         kfree(align_buf);
4315         return rc;
4316 }
4317
4318 static void
4319 bnx2_init_fw_cap(struct bnx2 *bp)
4320 {
4321         u32 val, sig = 0;
4322
4323         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4324         bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4325
4326         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4327                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4328
4329         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4330         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4331                 return;
4332
4333         if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4334                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4335                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4336         }
4337
4338         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4339             (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4340                 u32 link;
4341
4342                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4343
4344                 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4345                 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4346                         bp->phy_port = PORT_FIBRE;
4347                 else
4348                         bp->phy_port = PORT_TP;
4349
4350                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4351                        BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4352         }
4353
4354         if (netif_running(bp->dev) && sig)
4355                 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4356 }
4357
4358 static void
4359 bnx2_setup_msix_tbl(struct bnx2 *bp)
4360 {
4361         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4362
4363         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4364         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4365 }
4366
4367 static int
4368 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4369 {
4370         u32 val;
4371         int i, rc = 0;
4372         u8 old_port;
4373
4374         /* Wait for the current PCI transaction to complete before
4375          * issuing a reset. */
4376         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4377                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4378                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4379                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4380                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4381         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4382         udelay(5);
4383
4384         /* Wait for the firmware to tell us it is ok to issue a reset. */
4385         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4386
4387         /* Deposit a driver reset signature so the firmware knows that
4388          * this is a soft reset. */
4389         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4390                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4391
4392         /* Do a dummy read to force the chip to complete all current transaction
4393          * before we issue a reset. */
4394         val = REG_RD(bp, BNX2_MISC_ID);
4395
4396         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4397                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4398                 REG_RD(bp, BNX2_MISC_COMMAND);
4399                 udelay(5);
4400
4401                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4402                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4403
4404                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4405
4406         } else {
4407                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4408                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4409                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4410
4411                 /* Chip reset. */
4412                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4413
4414                 /* Reading back any register after chip reset will hang the
4415                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4416                  * of margin for write posting.
4417                  */
4418                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4419                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4420                         msleep(20);
4421
4422                 /* Reset takes approximate 30 usec */
4423                 for (i = 0; i < 10; i++) {
4424                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4425                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4426                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4427                                 break;
4428                         udelay(10);
4429                 }
4430
4431                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4432                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4433                         printk(KERN_ERR PFX "Chip reset did not complete\n");
4434                         return -EBUSY;
4435                 }
4436         }
4437
4438         /* Make sure byte swapping is properly configured. */
4439         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4440         if (val != 0x01020304) {
4441                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4442                 return -ENODEV;
4443         }
4444
4445         /* Wait for the firmware to finish its initialization. */
4446         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4447         if (rc)
4448                 return rc;
4449
4450         spin_lock_bh(&bp->phy_lock);
4451         old_port = bp->phy_port;
4452         bnx2_init_fw_cap(bp);
4453         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4454             old_port != bp->phy_port)
4455                 bnx2_set_default_remote_link(bp);
4456         spin_unlock_bh(&bp->phy_lock);
4457
4458         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4459                 /* Adjust the voltage regular to two steps lower.  The default
4460                  * of this register is 0x0000000e. */
4461                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4462
4463                 /* Remove bad rbuf memory from the free pool. */
4464                 rc = bnx2_alloc_bad_rbuf(bp);
4465         }
4466
4467         if (bp->flags & BNX2_FLAG_USING_MSIX)
4468                 bnx2_setup_msix_tbl(bp);
4469
4470         return rc;
4471 }
4472
4473 static int
4474 bnx2_init_chip(struct bnx2 *bp)
4475 {
4476         u32 val, mtu;
4477         int rc, i;
4478
4479         /* Make sure the interrupt is not active. */
4480         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4481
4482         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4483               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4484 #ifdef __BIG_ENDIAN
4485               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4486 #endif
4487               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4488               DMA_READ_CHANS << 12 |
4489               DMA_WRITE_CHANS << 16;
4490
4491         val |= (0x2 << 20) | (1 << 11);
4492
4493         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4494                 val |= (1 << 23);
4495
4496         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4497             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4498                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4499
4500         REG_WR(bp, BNX2_DMA_CONFIG, val);
4501
4502         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4503                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4504                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4505                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4506         }
4507
4508         if (bp->flags & BNX2_FLAG_PCIX) {
4509                 u16 val16;
4510
4511                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4512                                      &val16);
4513                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4514                                       val16 & ~PCI_X_CMD_ERO);
4515         }
4516
4517         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4518                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4519                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4520                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4521
4522         /* Initialize context mapping and zero out the quick contexts.  The
4523          * context block must have already been enabled. */
4524         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4525                 rc = bnx2_init_5709_context(bp);
4526                 if (rc)
4527                         return rc;
4528         } else
4529                 bnx2_init_context(bp);
4530
4531         if ((rc = bnx2_init_cpus(bp)) != 0)
4532                 return rc;
4533
4534         bnx2_init_nvram(bp);
4535
4536         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4537
4538         val = REG_RD(bp, BNX2_MQ_CONFIG);
4539         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4540         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4541         if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4542                 val |= BNX2_MQ_CONFIG_HALT_DIS;
4543
4544         REG_WR(bp, BNX2_MQ_CONFIG, val);
4545
4546         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4547         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4548         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4549
4550         val = (BCM_PAGE_BITS - 8) << 24;
4551         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4552
4553         /* Configure page size. */
4554         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4555         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4556         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4557         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4558
4559         val = bp->mac_addr[0] +
4560               (bp->mac_addr[1] << 8) +
4561               (bp->mac_addr[2] << 16) +
4562               bp->mac_addr[3] +
4563               (bp->mac_addr[4] << 8) +
4564               (bp->mac_addr[5] << 16);
4565         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4566
4567         /* Program the MTU.  Also include 4 bytes for CRC32. */
4568         mtu = bp->dev->mtu;
4569         val = mtu + ETH_HLEN + ETH_FCS_LEN;
4570         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4571                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4572         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4573
4574         if (mtu < 1500)
4575                 mtu = 1500;
4576
4577         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4578         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4579         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4580
4581         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4582                 bp->bnx2_napi[i].last_status_idx = 0;
4583
4584         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4585
4586         /* Set up how to generate a link change interrupt. */
4587         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4588
4589         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4590                (u64) bp->status_blk_mapping & 0xffffffff);
4591         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4592
4593         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4594                (u64) bp->stats_blk_mapping & 0xffffffff);
4595         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4596                (u64) bp->stats_blk_mapping >> 32);
4597
4598         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4599                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4600
4601         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4602                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4603
4604         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4605                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4606
4607         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4608
4609         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4610
4611         REG_WR(bp, BNX2_HC_COM_TICKS,
4612                (bp->com_ticks_int << 16) | bp->com_ticks);
4613
4614         REG_WR(bp, BNX2_HC_CMD_TICKS,
4615                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4616
4617         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4618                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4619         else
4620                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4621         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4622
4623         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4624                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4625         else {
4626                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4627                       BNX2_HC_CONFIG_COLLECT_STATS;
4628         }
4629
4630         if (bp->irq_nvecs > 1) {
4631                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4632                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4633
4634                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4635         }
4636
4637         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4638                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4639
4640         REG_WR(bp, BNX2_HC_CONFIG, val);
4641
4642         for (i = 1; i < bp->irq_nvecs; i++) {
4643                 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4644                            BNX2_HC_SB_CONFIG_1;
4645
4646                 REG_WR(bp, base,
4647                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4648                         BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4649                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4650
4651                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4652                         (bp->tx_quick_cons_trip_int << 16) |
4653                          bp->tx_quick_cons_trip);
4654
4655                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4656                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4657
4658                 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4659                        (bp->rx_quick_cons_trip_int << 16) |
4660                         bp->rx_quick_cons_trip);
4661
4662                 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4663                         (bp->rx_ticks_int << 16) | bp->rx_ticks);
4664         }
4665
4666         /* Clear internal stats counters. */
4667         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4668
4669         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4670
4671         /* Initialize the receive filter. */
4672         bnx2_set_rx_mode(bp->dev);
4673
4674         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4675                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4676                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4677                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4678         }
4679         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4680                           1, 0);
4681
4682         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4683         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4684
4685         udelay(20);
4686
4687         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4688
4689         return rc;
4690 }
4691
4692 static void
4693 bnx2_clear_ring_states(struct bnx2 *bp)
4694 {
4695         struct bnx2_napi *bnapi;
4696         struct bnx2_tx_ring_info *txr;
4697         struct bnx2_rx_ring_info *rxr;
4698         int i;
4699
4700         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4701                 bnapi = &bp->bnx2_napi[i];
4702                 txr = &bnapi->tx_ring;
4703                 rxr = &bnapi->rx_ring;
4704
4705                 txr->tx_cons = 0;
4706                 txr->hw_tx_cons = 0;
4707                 rxr->rx_prod_bseq = 0;
4708                 rxr->rx_prod = 0;
4709                 rxr->rx_cons = 0;
4710                 rxr->rx_pg_prod = 0;
4711                 rxr->rx_pg_cons = 0;
4712         }
4713 }
4714
4715 static void
4716 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4717 {
4718         u32 val, offset0, offset1, offset2, offset3;
4719         u32 cid_addr = GET_CID_ADDR(cid);
4720
4721         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4722                 offset0 = BNX2_L2CTX_TYPE_XI;
4723                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4724                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4725                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4726         } else {
4727                 offset0 = BNX2_L2CTX_TYPE;
4728                 offset1 = BNX2_L2CTX_CMD_TYPE;
4729                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4730                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4731         }
4732         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4733         bnx2_ctx_wr(bp, cid_addr, offset0, val);
4734
4735         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4736         bnx2_ctx_wr(bp, cid_addr, offset1, val);
4737
4738         val = (u64) txr->tx_desc_mapping >> 32;
4739         bnx2_ctx_wr(bp, cid_addr, offset2, val);
4740
4741         val = (u64) txr->tx_desc_mapping & 0xffffffff;
4742         bnx2_ctx_wr(bp, cid_addr, offset3, val);
4743 }
4744
4745 static void
4746 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4747 {
4748         struct tx_bd *txbd;
4749         u32 cid = TX_CID;
4750         struct bnx2_napi *bnapi;
4751         struct bnx2_tx_ring_info *txr;
4752
4753         bnapi = &bp->bnx2_napi[ring_num];
4754         txr = &bnapi->tx_ring;
4755
4756         if (ring_num == 0)
4757                 cid = TX_CID;
4758         else
4759                 cid = TX_TSS_CID + ring_num - 1;
4760
4761         bp->tx_wake_thresh = bp->tx_ring_size / 2;
4762
4763         txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4764
4765         txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4766         txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4767
4768         txr->tx_prod = 0;
4769         txr->tx_prod_bseq = 0;
4770
4771         txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4772         txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4773
4774         bnx2_init_tx_context(bp, cid, txr);
4775 }
4776
4777 static void
4778 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4779                      int num_rings)
4780 {
4781         int i;
4782         struct rx_bd *rxbd;
4783
4784         for (i = 0; i < num_rings; i++) {
4785                 int j;
4786
4787                 rxbd = &rx_ring[i][0];
4788                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4789                         rxbd->rx_bd_len = buf_size;
4790                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4791                 }
4792                 if (i == (num_rings - 1))
4793                         j = 0;
4794                 else
4795                         j = i + 1;
4796                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4797                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4798         }
4799 }
4800
4801 static void
4802 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4803 {
4804         int i;
4805         u16 prod, ring_prod;
4806         u32 cid, rx_cid_addr, val;
4807         struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4808         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4809
4810         if (ring_num == 0)
4811                 cid = RX_CID;
4812         else
4813                 cid = RX_RSS_CID + ring_num - 1;
4814
4815         rx_cid_addr = GET_CID_ADDR(cid);
4816
4817         bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4818                              bp->rx_buf_use_size, bp->rx_max_ring);
4819
4820         bnx2_init_rx_context(bp, cid);
4821
4822         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4823                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4824                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4825         }
4826
4827         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4828         if (bp->rx_pg_ring_size) {
4829                 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4830                                      rxr->rx_pg_desc_mapping,
4831                                      PAGE_SIZE, bp->rx_max_pg_ring);
4832                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4833                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4834                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4835                        BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4836
4837                 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4838                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4839
4840                 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4841                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4842
4843                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4844                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4845         }
4846
4847         val = (u64) rxr->rx_desc_mapping[0] >> 32;
4848         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4849
4850         val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4851         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4852
4853         ring_prod = prod = rxr->rx_pg_prod;
4854         for (i = 0; i < bp->rx_pg_ring_size; i++) {
4855                 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4856                         break;
4857                 prod = NEXT_RX_BD(prod);
4858                 ring_prod = RX_PG_RING_IDX(prod);
4859         }
4860         rxr->rx_pg_prod = prod;
4861
4862         ring_prod = prod = rxr->rx_prod;
4863         for (i = 0; i < bp->rx_ring_size; i++) {
4864                 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4865                         break;
4866                 prod = NEXT_RX_BD(prod);
4867                 ring_prod = RX_RING_IDX(prod);
4868         }
4869         rxr->rx_prod = prod;
4870
4871         rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4872         rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4873         rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4874
4875         REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4876         REG_WR16(bp, rxr->rx_bidx_addr, prod);
4877
4878         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4879 }
4880
4881 static void
4882 bnx2_init_all_rings(struct bnx2 *bp)
4883 {
4884         int i;
4885         u32 val;
4886
4887         bnx2_clear_ring_states(bp);
4888
4889         REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4890         for (i = 0; i < bp->num_tx_rings; i++)
4891                 bnx2_init_tx_ring(bp, i);
4892
4893         if (bp->num_tx_rings > 1)
4894                 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4895                        (TX_TSS_CID << 7));
4896
4897         REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4898         bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4899
4900         for (i = 0; i < bp->num_rx_rings; i++)
4901                 bnx2_init_rx_ring(bp, i);
4902
4903         if (bp->num_rx_rings > 1) {
4904                 u32 tbl_32;
4905                 u8 *tbl = (u8 *) &tbl_32;
4906
4907                 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4908                                 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4909
4910                 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4911                         tbl[i % 4] = i % (bp->num_rx_rings - 1);
4912                         if ((i % 4) == 3)
4913                                 bnx2_reg_wr_ind(bp,
4914                                                 BNX2_RXP_SCRATCH_RSS_TBL + i,
4915                                                 cpu_to_be32(tbl_32));
4916                 }
4917
4918                 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4919                       BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4920
4921                 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4922
4923         }
4924 }
4925
4926 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4927 {
4928         u32 max, num_rings = 1;
4929
4930         while (ring_size > MAX_RX_DESC_CNT) {
4931                 ring_size -= MAX_RX_DESC_CNT;
4932                 num_rings++;
4933         }
4934         /* round to next power of 2 */
4935         max = max_size;
4936         while ((max & num_rings) == 0)
4937                 max >>= 1;
4938
4939         if (num_rings != max)
4940                 max <<= 1;
4941
4942         return max;
4943 }
4944
4945 static void
4946 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4947 {
4948         u32 rx_size, rx_space, jumbo_size;
4949
4950         /* 8 for CRC and VLAN */
4951         rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4952
4953         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4954                 sizeof(struct skb_shared_info);
4955
4956         bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4957         bp->rx_pg_ring_size = 0;
4958         bp->rx_max_pg_ring = 0;
4959         bp->rx_max_pg_ring_idx = 0;
4960         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4961                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4962
4963                 jumbo_size = size * pages;
4964                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4965                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4966
4967                 bp->rx_pg_ring_size = jumbo_size;
4968                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4969                                                         MAX_RX_PG_RINGS);
4970                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4971                 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
4972                 bp->rx_copy_thresh = 0;
4973         }
4974
4975         bp->rx_buf_use_size = rx_size;
4976         /* hw alignment */
4977         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4978         bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4979         bp->rx_ring_size = size;
4980         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4981         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4982 }
4983
4984 static void
4985 bnx2_free_tx_skbs(struct bnx2 *bp)
4986 {
4987         int i;
4988
4989         for (i = 0; i < bp->num_tx_rings; i++) {
4990                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4991                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
4992                 int j;
4993
4994                 if (txr->tx_buf_ring == NULL)
4995                         continue;
4996
4997                 for (j = 0; j < TX_DESC_CNT; ) {
4998                         struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
4999                         struct sk_buff *skb = tx_buf->skb;
5000
5001                         if (skb == NULL) {
5002                                 j++;
5003                                 continue;
5004                         }
5005
5006                         skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5007
5008                         tx_buf->skb = NULL;
5009
5010                         j += skb_shinfo(skb)->nr_frags + 1;
5011                         dev_kfree_skb(skb);
5012                 }
5013         }
5014 }
5015
5016 static void
5017 bnx2_free_rx_skbs(struct bnx2 *bp)
5018 {
5019         int i;
5020
5021         for (i = 0; i < bp->num_rx_rings; i++) {
5022                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5023                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5024                 int j;
5025
5026                 if (rxr->rx_buf_ring == NULL)
5027                         return;
5028
5029                 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5030                         struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5031                         struct sk_buff *skb = rx_buf->skb;
5032
5033                         if (skb == NULL)
5034                                 continue;
5035
5036                         pci_unmap_single(bp->pdev,
5037                                          pci_unmap_addr(rx_buf, mapping),
5038                                          bp->rx_buf_use_size,
5039                                          PCI_DMA_FROMDEVICE);
5040
5041                         rx_buf->skb = NULL;
5042
5043                         dev_kfree_skb(skb);
5044                 }
5045                 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5046                         bnx2_free_rx_page(bp, rxr, j);
5047         }
5048 }
5049
5050 static void
5051 bnx2_free_skbs(struct bnx2 *bp)
5052 {
5053         bnx2_free_tx_skbs(bp);
5054         bnx2_free_rx_skbs(bp);
5055 }
5056
5057 static int
5058 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5059 {
5060         int rc;
5061
5062         rc = bnx2_reset_chip(bp, reset_code);
5063         bnx2_free_skbs(bp);
5064         if (rc)
5065                 return rc;
5066
5067         if ((rc = bnx2_init_chip(bp)) != 0)
5068                 return rc;
5069
5070         bnx2_init_all_rings(bp);
5071         return 0;
5072 }
5073
5074 static int
5075 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5076 {
5077         int rc;
5078
5079         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5080                 return rc;
5081
5082         spin_lock_bh(&bp->phy_lock);
5083         bnx2_init_phy(bp, reset_phy);
5084         bnx2_set_link(bp);
5085         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5086                 bnx2_remote_phy_event(bp);
5087         spin_unlock_bh(&bp->phy_lock);
5088         return 0;
5089 }
5090
5091 static int
5092 bnx2_shutdown_chip(struct bnx2 *bp)
5093 {
5094         u32 reset_code;
5095
5096         if (bp->flags & BNX2_FLAG_NO_WOL)
5097                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5098         else if (bp->wol)
5099                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5100         else
5101                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5102
5103         return bnx2_reset_chip(bp, reset_code);
5104 }
5105
5106 static int
5107 bnx2_test_registers(struct bnx2 *bp)
5108 {
5109         int ret;
5110         int i, is_5709;
5111         static const struct {
5112                 u16   offset;
5113                 u16   flags;
5114 #define BNX2_FL_NOT_5709        1
5115                 u32   rw_mask;
5116                 u32   ro_mask;
5117         } reg_tbl[] = {
5118                 { 0x006c, 0, 0x00000000, 0x0000003f },
5119                 { 0x0090, 0, 0xffffffff, 0x00000000 },
5120                 { 0x0094, 0, 0x00000000, 0x00000000 },
5121
5122                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5123                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5124                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5125                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5126                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5127                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5128                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5129                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5130                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5131
5132                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5133                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5134                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5135                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5136                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5137                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5138
5139                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5140                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5141                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5142
5143                 { 0x1000, 0, 0x00000000, 0x00000001 },
5144                 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5145
5146                 { 0x1408, 0, 0x01c00800, 0x00000000 },
5147                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5148                 { 0x14a8, 0, 0x00000000, 0x000001ff },
5149                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5150                 { 0x14b0, 0, 0x00000002, 0x00000001 },
5151                 { 0x14b8, 0, 0x00000000, 0x00000000 },
5152                 { 0x14c0, 0, 0x00000000, 0x00000009 },
5153                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5154                 { 0x14cc, 0, 0x00000000, 0x00000001 },
5155                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5156
5157                 { 0x1800, 0, 0x00000000, 0x00000001 },
5158                 { 0x1804, 0, 0x00000000, 0x00000003 },
5159
5160                 { 0x2800, 0, 0x00000000, 0x00000001 },
5161                 { 0x2804, 0, 0x00000000, 0x00003f01 },
5162                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5163                 { 0x2810, 0, 0xffff0000, 0x00000000 },
5164                 { 0x2814, 0, 0xffff0000, 0x00000000 },
5165                 { 0x2818, 0, 0xffff0000, 0x00000000 },
5166                 { 0x281c, 0, 0xffff0000, 0x00000000 },
5167                 { 0x2834, 0, 0xffffffff, 0x00000000 },
5168                 { 0x2840, 0, 0x00000000, 0xffffffff },
5169                 { 0x2844, 0, 0x00000000, 0xffffffff },
5170                 { 0x2848, 0, 0xffffffff, 0x00000000 },
5171                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5172
5173                 { 0x2c00, 0, 0x00000000, 0x00000011 },
5174                 { 0x2c04, 0, 0x00000000, 0x00030007 },
5175
5176                 { 0x3c00, 0, 0x00000000, 0x00000001 },
5177                 { 0x3c04, 0, 0x00000000, 0x00070000 },
5178                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5179                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5180                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5181                 { 0x3c14, 0, 0x00000000, 0xffffffff },
5182                 { 0x3c18, 0, 0x00000000, 0xffffffff },
5183                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5184                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5185
5186                 { 0x5004, 0, 0x00000000, 0x0000007f },
5187                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5188
5189                 { 0x5c00, 0, 0x00000000, 0x00000001 },
5190                 { 0x5c04, 0, 0x00000000, 0x0003000f },
5191                 { 0x5c08, 0, 0x00000003, 0x00000000 },
5192                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5193                 { 0x5c10, 0, 0x00000000, 0xffffffff },
5194                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5195                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5196                 { 0x5c88, 0, 0x00000000, 0x00077373 },
5197                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5198
5199                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5200                 { 0x680c, 0, 0xffffffff, 0x00000000 },
5201                 { 0x6810, 0, 0xffffffff, 0x00000000 },
5202                 { 0x6814, 0, 0xffffffff, 0x00000000 },
5203                 { 0x6818, 0, 0xffffffff, 0x00000000 },
5204                 { 0x681c, 0, 0xffffffff, 0x00000000 },
5205                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5206                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5207                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5208                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5209                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5210                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5211                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5212                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5213                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5214                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5215                 { 0x684c, 0, 0xffffffff, 0x00000000 },
5216                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5217                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5218                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5219                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5220                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5221                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5222
5223                 { 0xffff, 0, 0x00000000, 0x00000000 },
5224         };
5225
5226         ret = 0;
5227         is_5709 = 0;
5228         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5229                 is_5709 = 1;
5230
5231         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5232                 u32 offset, rw_mask, ro_mask, save_val, val;
5233                 u16 flags = reg_tbl[i].flags;
5234
5235                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5236                         continue;
5237
5238                 offset = (u32) reg_tbl[i].offset;
5239                 rw_mask = reg_tbl[i].rw_mask;
5240                 ro_mask = reg_tbl[i].ro_mask;
5241
5242                 save_val = readl(bp->regview + offset);
5243
5244                 writel(0, bp->regview + offset);
5245
5246                 val = readl(bp->regview + offset);
5247                 if ((val & rw_mask) != 0) {
5248                         goto reg_test_err;
5249                 }
5250
5251                 if ((val & ro_mask) != (save_val & ro_mask)) {
5252                         goto reg_test_err;
5253                 }
5254
5255                 writel(0xffffffff, bp->regview + offset);
5256
5257                 val = readl(bp->regview + offset);
5258                 if ((val & rw_mask) != rw_mask) {
5259                         goto reg_test_err;
5260                 }
5261
5262                 if ((val & ro_mask) != (save_val & ro_mask)) {
5263                         goto reg_test_err;
5264                 }
5265
5266                 writel(save_val, bp->regview + offset);
5267                 continue;
5268
5269 reg_test_err:
5270                 writel(save_val, bp->regview + offset);
5271                 ret = -ENODEV;
5272                 break;
5273         }
5274         return ret;
5275 }
5276
5277 static int
5278 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5279 {
5280         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5281                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5282         int i;
5283
5284         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5285                 u32 offset;
5286
5287                 for (offset = 0; offset < size; offset += 4) {
5288
5289                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5290
5291                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5292                                 test_pattern[i]) {
5293                                 return -ENODEV;
5294                         }
5295                 }
5296         }
5297         return 0;
5298 }
5299
5300 static int
5301 bnx2_test_memory(struct bnx2 *bp)
5302 {
5303         int ret = 0;
5304         int i;
5305         static struct mem_entry {
5306                 u32   offset;
5307                 u32   len;
5308         } mem_tbl_5706[] = {
5309                 { 0x60000,  0x4000 },
5310                 { 0xa0000,  0x3000 },
5311                 { 0xe0000,  0x4000 },
5312                 { 0x120000, 0x4000 },
5313                 { 0x1a0000, 0x4000 },
5314                 { 0x160000, 0x4000 },
5315                 { 0xffffffff, 0    },
5316         },
5317         mem_tbl_5709[] = {
5318                 { 0x60000,  0x4000 },
5319                 { 0xa0000,  0x3000 },
5320                 { 0xe0000,  0x4000 },
5321                 { 0x120000, 0x4000 },
5322                 { 0x1a0000, 0x4000 },
5323                 { 0xffffffff, 0    },
5324         };
5325         struct mem_entry *mem_tbl;
5326
5327         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5328                 mem_tbl = mem_tbl_5709;
5329         else
5330                 mem_tbl = mem_tbl_5706;
5331
5332         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5333                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5334                         mem_tbl[i].len)) != 0) {
5335                         return ret;
5336                 }
5337         }
5338
5339         return ret;
5340 }
5341
5342 #define BNX2_MAC_LOOPBACK       0
5343 #define BNX2_PHY_LOOPBACK       1
5344
5345 static int
5346 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5347 {
5348         unsigned int pkt_size, num_pkts, i;
5349         struct sk_buff *skb, *rx_skb;
5350         unsigned char *packet;
5351         u16 rx_start_idx, rx_idx;
5352         dma_addr_t map;
5353         struct tx_bd *txbd;
5354         struct sw_bd *rx_buf;
5355         struct l2_fhdr *rx_hdr;
5356         int ret = -ENODEV;
5357         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5358         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5359         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5360
5361         tx_napi = bnapi;
5362
5363         txr = &tx_napi->tx_ring;
5364         rxr = &bnapi->rx_ring;
5365         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5366                 bp->loopback = MAC_LOOPBACK;
5367                 bnx2_set_mac_loopback(bp);
5368         }
5369         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5370                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5371                         return 0;
5372
5373                 bp->loopback = PHY_LOOPBACK;
5374                 bnx2_set_phy_loopback(bp);
5375         }
5376         else
5377                 return -EINVAL;
5378
5379         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5380         skb = netdev_alloc_skb(bp->dev, pkt_size);
5381         if (!skb)
5382                 return -ENOMEM;
5383         packet = skb_put(skb, pkt_size);
5384         memcpy(packet, bp->dev->dev_addr, 6);
5385         memset(packet + 6, 0x0, 8);
5386         for (i = 14; i < pkt_size; i++)
5387                 packet[i] = (unsigned char) (i & 0xff);
5388
5389         if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5390                 dev_kfree_skb(skb);
5391                 return -EIO;
5392         }
5393         map = skb_shinfo(skb)->dma_maps[0];
5394
5395         REG_WR(bp, BNX2_HC_COMMAND,
5396                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5397
5398         REG_RD(bp, BNX2_HC_COMMAND);
5399
5400         udelay(5);
5401         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5402
5403         num_pkts = 0;
5404
5405         txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5406
5407         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5408         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5409         txbd->tx_bd_mss_nbytes = pkt_size;
5410         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5411
5412         num_pkts++;
5413         txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5414         txr->tx_prod_bseq += pkt_size;
5415
5416         REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5417         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5418
5419         udelay(100);
5420
5421         REG_WR(bp, BNX2_HC_COMMAND,
5422                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5423
5424         REG_RD(bp, BNX2_HC_COMMAND);
5425
5426         udelay(5);
5427
5428         skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5429         dev_kfree_skb(skb);
5430
5431         if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5432                 goto loopback_test_done;
5433
5434         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5435         if (rx_idx != rx_start_idx + num_pkts) {
5436                 goto loopback_test_done;
5437         }
5438
5439         rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5440         rx_skb = rx_buf->skb;
5441
5442         rx_hdr = (struct l2_fhdr *) rx_skb->data;
5443         skb_reserve(rx_skb, BNX2_RX_OFFSET);
5444
5445         pci_dma_sync_single_for_cpu(bp->pdev,
5446                 pci_unmap_addr(rx_buf, mapping),
5447                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5448
5449         if (rx_hdr->l2_fhdr_status &
5450                 (L2_FHDR_ERRORS_BAD_CRC |
5451                 L2_FHDR_ERRORS_PHY_DECODE |
5452                 L2_FHDR_ERRORS_ALIGNMENT |
5453                 L2_FHDR_ERRORS_TOO_SHORT |
5454                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5455
5456                 goto loopback_test_done;
5457         }
5458
5459         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5460                 goto loopback_test_done;
5461         }
5462
5463         for (i = 14; i < pkt_size; i++) {
5464                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5465                         goto loopback_test_done;
5466                 }
5467         }
5468
5469         ret = 0;
5470
5471 loopback_test_done:
5472         bp->loopback = 0;
5473         return ret;
5474 }
5475
5476 #define BNX2_MAC_LOOPBACK_FAILED        1
5477 #define BNX2_PHY_LOOPBACK_FAILED        2
5478 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5479                                          BNX2_PHY_LOOPBACK_FAILED)
5480
5481 static int
5482 bnx2_test_loopback(struct bnx2 *bp)
5483 {
5484         int rc = 0;
5485
5486         if (!netif_running(bp->dev))
5487                 return BNX2_LOOPBACK_FAILED;
5488
5489         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5490         spin_lock_bh(&bp->phy_lock);
5491         bnx2_init_phy(bp, 1);
5492         spin_unlock_bh(&bp->phy_lock);
5493         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5494                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5495         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5496                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5497         return rc;
5498 }
5499
5500 #define NVRAM_SIZE 0x200
5501 #define CRC32_RESIDUAL 0xdebb20e3
5502
5503 static int
5504 bnx2_test_nvram(struct bnx2 *bp)
5505 {
5506         __be32 buf[NVRAM_SIZE / 4];
5507         u8 *data = (u8 *) buf;
5508         int rc = 0;
5509         u32 magic, csum;
5510
5511         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5512                 goto test_nvram_done;
5513
5514         magic = be32_to_cpu(buf[0]);
5515         if (magic != 0x669955aa) {
5516                 rc = -ENODEV;
5517                 goto test_nvram_done;
5518         }
5519
5520         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5521                 goto test_nvram_done;
5522
5523         csum = ether_crc_le(0x100, data);
5524         if (csum != CRC32_RESIDUAL) {
5525                 rc = -ENODEV;
5526                 goto test_nvram_done;
5527         }
5528
5529         csum = ether_crc_le(0x100, data + 0x100);
5530         if (csum != CRC32_RESIDUAL) {
5531                 rc = -ENODEV;
5532         }
5533
5534 test_nvram_done:
5535         return rc;
5536 }
5537
5538 static int
5539 bnx2_test_link(struct bnx2 *bp)
5540 {
5541         u32 bmsr;
5542
5543         if (!netif_running(bp->dev))
5544                 return -ENODEV;
5545
5546         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5547                 if (bp->link_up)
5548                         return 0;
5549                 return -ENODEV;
5550         }
5551         spin_lock_bh(&bp->phy_lock);
5552         bnx2_enable_bmsr1(bp);
5553         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5554         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5555         bnx2_disable_bmsr1(bp);
5556         spin_unlock_bh(&bp->phy_lock);
5557
5558         if (bmsr & BMSR_LSTATUS) {
5559                 return 0;
5560         }
5561         return -ENODEV;
5562 }
5563
5564 static int
5565 bnx2_test_intr(struct bnx2 *bp)
5566 {
5567         int i;
5568         u16 status_idx;
5569
5570         if (!netif_running(bp->dev))
5571                 return -ENODEV;
5572
5573         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5574
5575         /* This register is not touched during run-time. */
5576         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5577         REG_RD(bp, BNX2_HC_COMMAND);
5578
5579         for (i = 0; i < 10; i++) {
5580                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5581                         status_idx) {
5582
5583                         break;
5584                 }
5585
5586                 msleep_interruptible(10);
5587         }
5588         if (i < 10)
5589                 return 0;
5590
5591         return -ENODEV;
5592 }
5593
5594 /* Determining link for parallel detection. */
5595 static int
5596 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5597 {
5598         u32 mode_ctl, an_dbg, exp;
5599
5600         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5601                 return 0;
5602
5603         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5604         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5605
5606         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5607                 return 0;
5608
5609         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5610         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5611         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5612
5613         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5614                 return 0;
5615
5616         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5617         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5618         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5619
5620         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5621                 return 0;
5622
5623         return 1;
5624 }
5625
5626 static void
5627 bnx2_5706_serdes_timer(struct bnx2 *bp)
5628 {
5629         int check_link = 1;
5630
5631         spin_lock(&bp->phy_lock);
5632         if (bp->serdes_an_pending) {
5633                 bp->serdes_an_pending--;
5634                 check_link = 0;
5635         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5636                 u32 bmcr;
5637
5638                 bp->current_interval = BNX2_TIMER_INTERVAL;
5639
5640                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5641
5642                 if (bmcr & BMCR_ANENABLE) {
5643                         if (bnx2_5706_serdes_has_link(bp)) {
5644                                 bmcr &= ~BMCR_ANENABLE;
5645                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5646                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5647                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5648                         }
5649                 }
5650         }
5651         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5652                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5653                 u32 phy2;
5654
5655                 bnx2_write_phy(bp, 0x17, 0x0f01);
5656                 bnx2_read_phy(bp, 0x15, &phy2);
5657                 if (phy2 & 0x20) {
5658                         u32 bmcr;
5659
5660                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5661                         bmcr |= BMCR_ANENABLE;
5662                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5663
5664                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5665                 }
5666         } else
5667                 bp->current_interval = BNX2_TIMER_INTERVAL;
5668
5669         if (check_link) {
5670                 u32 val;
5671
5672                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5673                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5674                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5675
5676                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5677                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5678                                 bnx2_5706s_force_link_dn(bp, 1);
5679                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5680                         } else
5681                                 bnx2_set_link(bp);
5682                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5683                         bnx2_set_link(bp);
5684         }
5685         spin_unlock(&bp->phy_lock);
5686 }
5687
5688 static void
5689 bnx2_5708_serdes_timer(struct bnx2 *bp)
5690 {
5691         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5692                 return;
5693
5694         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5695                 bp->serdes_an_pending = 0;
5696                 return;
5697         }
5698
5699         spin_lock(&bp->phy_lock);
5700         if (bp->serdes_an_pending)
5701                 bp->serdes_an_pending--;
5702         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5703                 u32 bmcr;
5704
5705                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5706                 if (bmcr & BMCR_ANENABLE) {
5707                         bnx2_enable_forced_2g5(bp);
5708                         bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
5709                 } else {
5710                         bnx2_disable_forced_2g5(bp);
5711                         bp->serdes_an_pending = 2;
5712                         bp->current_interval = BNX2_TIMER_INTERVAL;
5713                 }
5714
5715         } else
5716                 bp->current_interval = BNX2_TIMER_INTERVAL;
5717
5718         spin_unlock(&bp->phy_lock);
5719 }
5720
5721 static void
5722 bnx2_timer(unsigned long data)
5723 {
5724         struct bnx2 *bp = (struct bnx2 *) data;
5725
5726         if (!netif_running(bp->dev))
5727                 return;
5728
5729         if (atomic_read(&bp->intr_sem) != 0)
5730                 goto bnx2_restart_timer;
5731
5732         bnx2_send_heart_beat(bp);
5733
5734         bp->stats_blk->stat_FwRxDrop =
5735                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5736
5737         /* workaround occasional corrupted counters */
5738         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5739                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5740                                             BNX2_HC_COMMAND_STATS_NOW);
5741
5742         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5743                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5744                         bnx2_5706_serdes_timer(bp);
5745                 else
5746                         bnx2_5708_serdes_timer(bp);
5747         }
5748
5749 bnx2_restart_timer:
5750         mod_timer(&bp->timer, jiffies + bp->current_interval);
5751 }
5752
5753 static int
5754 bnx2_request_irq(struct bnx2 *bp)
5755 {
5756         unsigned long flags;
5757         struct bnx2_irq *irq;
5758         int rc = 0, i;
5759
5760         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5761                 flags = 0;
5762         else
5763                 flags = IRQF_SHARED;
5764
5765         for (i = 0; i < bp->irq_nvecs; i++) {
5766                 irq = &bp->irq_tbl[i];
5767                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5768                                  &bp->bnx2_napi[i]);
5769                 if (rc)
5770                         break;
5771                 irq->requested = 1;
5772         }
5773         return rc;
5774 }
5775
5776 static void
5777 bnx2_free_irq(struct bnx2 *bp)
5778 {
5779         struct bnx2_irq *irq;
5780         int i;
5781
5782         for (i = 0; i < bp->irq_nvecs; i++) {
5783                 irq = &bp->irq_tbl[i];
5784                 if (irq->requested)
5785                         free_irq(irq->vector, &bp->bnx2_napi[i]);
5786                 irq->requested = 0;
5787         }
5788         if (bp->flags & BNX2_FLAG_USING_MSI)
5789                 pci_disable_msi(bp->pdev);
5790         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5791                 pci_disable_msix(bp->pdev);
5792
5793         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5794 }
5795
5796 static void
5797 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5798 {
5799         int i, rc;
5800         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5801
5802         bnx2_setup_msix_tbl(bp);
5803         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5804         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5805         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5806
5807         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5808                 msix_ent[i].entry = i;
5809                 msix_ent[i].vector = 0;
5810
5811                 strcpy(bp->irq_tbl[i].name, bp->dev->name);
5812                 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5813         }
5814
5815         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5816         if (rc != 0)
5817                 return;
5818
5819         bp->irq_nvecs = msix_vecs;
5820         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5821         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5822                 bp->irq_tbl[i].vector = msix_ent[i].vector;
5823 }
5824
5825 static void
5826 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5827 {
5828         int cpus = num_online_cpus();
5829         int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5830
5831         bp->irq_tbl[0].handler = bnx2_interrupt;
5832         strcpy(bp->irq_tbl[0].name, bp->dev->name);
5833         bp->irq_nvecs = 1;
5834         bp->irq_tbl[0].vector = bp->pdev->irq;
5835
5836         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5837                 bnx2_enable_msix(bp, msix_vecs);
5838
5839         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5840             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5841                 if (pci_enable_msi(bp->pdev) == 0) {
5842                         bp->flags |= BNX2_FLAG_USING_MSI;
5843                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5844                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5845                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5846                         } else
5847                                 bp->irq_tbl[0].handler = bnx2_msi;
5848
5849                         bp->irq_tbl[0].vector = bp->pdev->irq;
5850                 }
5851         }
5852
5853         bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5854         bp->dev->real_num_tx_queues = bp->num_tx_rings;
5855
5856         bp->num_rx_rings = bp->irq_nvecs;
5857 }
5858
5859 /* Called with rtnl_lock */
5860 static int
5861 bnx2_open(struct net_device *dev)
5862 {
5863         struct bnx2 *bp = netdev_priv(dev);
5864         int rc;
5865
5866         netif_carrier_off(dev);
5867
5868         bnx2_set_power_state(bp, PCI_D0);
5869         bnx2_disable_int(bp);
5870
5871         bnx2_setup_int_mode(bp, disable_msi);
5872         bnx2_napi_enable(bp);
5873         rc = bnx2_alloc_mem(bp);
5874         if (rc)
5875                 goto open_err;
5876
5877         rc = bnx2_request_irq(bp);
5878         if (rc)
5879                 goto open_err;
5880
5881         rc = bnx2_init_nic(bp, 1);
5882         if (rc)
5883                 goto open_err;
5884
5885         mod_timer(&bp->timer, jiffies + bp->current_interval);
5886
5887         atomic_set(&bp->intr_sem, 0);
5888
5889         bnx2_enable_int(bp);
5890
5891         if (bp->flags & BNX2_FLAG_USING_MSI) {
5892                 /* Test MSI to make sure it is working
5893                  * If MSI test fails, go back to INTx mode
5894                  */
5895                 if (bnx2_test_intr(bp) != 0) {
5896                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
5897                                " using MSI, switching to INTx mode. Please"
5898                                " report this failure to the PCI maintainer"
5899                                " and include system chipset information.\n",
5900                                bp->dev->name);
5901
5902                         bnx2_disable_int(bp);
5903                         bnx2_free_irq(bp);
5904
5905                         bnx2_setup_int_mode(bp, 1);
5906
5907                         rc = bnx2_init_nic(bp, 0);
5908
5909                         if (!rc)
5910                                 rc = bnx2_request_irq(bp);
5911
5912                         if (rc) {
5913                                 del_timer_sync(&bp->timer);
5914                                 goto open_err;
5915                         }
5916                         bnx2_enable_int(bp);
5917                 }
5918         }
5919         if (bp->flags & BNX2_FLAG_USING_MSI)
5920                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5921         else if (bp->flags & BNX2_FLAG_USING_MSIX)
5922                 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5923
5924         netif_tx_start_all_queues(dev);
5925
5926         return 0;
5927
5928 open_err:
5929         bnx2_napi_disable(bp);
5930         bnx2_free_skbs(bp);
5931         bnx2_free_irq(bp);
5932         bnx2_free_mem(bp);
5933         return rc;
5934 }
5935
5936 static void
5937 bnx2_reset_task(struct work_struct *work)
5938 {
5939         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5940
5941         if (!netif_running(bp->dev))
5942                 return;
5943
5944         bnx2_netif_stop(bp);
5945
5946         bnx2_init_nic(bp, 1);
5947
5948         atomic_set(&bp->intr_sem, 1);
5949         bnx2_netif_start(bp);
5950 }
5951
5952 static void
5953 bnx2_tx_timeout(struct net_device *dev)
5954 {
5955         struct bnx2 *bp = netdev_priv(dev);
5956
5957         /* This allows the netif to be shutdown gracefully before resetting */
5958         schedule_work(&bp->reset_task);
5959 }
5960
5961 #ifdef BCM_VLAN
5962 /* Called with rtnl_lock */
5963 static void
5964 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5965 {
5966         struct bnx2 *bp = netdev_priv(dev);
5967
5968         bnx2_netif_stop(bp);
5969
5970         bp->vlgrp = vlgrp;
5971         bnx2_set_rx_mode(dev);
5972         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5973                 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
5974
5975         bnx2_netif_start(bp);
5976 }
5977 #endif
5978
5979 /* Called with netif_tx_lock.
5980  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5981  * netif_wake_queue().
5982  */
5983 static int
5984 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5985 {
5986         struct bnx2 *bp = netdev_priv(dev);
5987         dma_addr_t mapping;
5988         struct tx_bd *txbd;
5989         struct sw_tx_bd *tx_buf;
5990         u32 len, vlan_tag_flags, last_frag, mss;
5991         u16 prod, ring_prod;
5992         int i;
5993         struct bnx2_napi *bnapi;
5994         struct bnx2_tx_ring_info *txr;
5995         struct netdev_queue *txq;
5996         struct skb_shared_info *sp;
5997
5998         /*  Determine which tx ring we will be placed on */
5999         i = skb_get_queue_mapping(skb);
6000         bnapi = &bp->bnx2_napi[i];
6001         txr = &bnapi->tx_ring;
6002         txq = netdev_get_tx_queue(dev, i);
6003
6004         if (unlikely(bnx2_tx_avail(bp, txr) <
6005             (skb_shinfo(skb)->nr_frags + 1))) {
6006                 netif_tx_stop_queue(txq);
6007                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6008                         dev->name);
6009
6010                 return NETDEV_TX_BUSY;
6011         }
6012         len = skb_headlen(skb);
6013         prod = txr->tx_prod;
6014         ring_prod = TX_RING_IDX(prod);
6015
6016         vlan_tag_flags = 0;
6017         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6018                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6019         }
6020
6021 #ifdef BCM_VLAN
6022         if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6023                 vlan_tag_flags |=
6024                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6025         }
6026 #endif
6027         if ((mss = skb_shinfo(skb)->gso_size)) {
6028                 u32 tcp_opt_len;
6029                 struct iphdr *iph;
6030
6031                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6032
6033                 tcp_opt_len = tcp_optlen(skb);
6034
6035                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6036                         u32 tcp_off = skb_transport_offset(skb) -
6037                                       sizeof(struct ipv6hdr) - ETH_HLEN;
6038
6039                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6040                                           TX_BD_FLAGS_SW_FLAGS;
6041                         if (likely(tcp_off == 0))
6042                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6043                         else {
6044                                 tcp_off >>= 3;
6045                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
6046                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
6047                                                   ((tcp_off & 0x10) <<
6048                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
6049                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6050                         }
6051                 } else {
6052                         iph = ip_hdr(skb);
6053                         if (tcp_opt_len || (iph->ihl > 5)) {
6054                                 vlan_tag_flags |= ((iph->ihl - 5) +
6055                                                    (tcp_opt_len >> 2)) << 8;
6056                         }
6057                 }
6058         } else
6059                 mss = 0;
6060
6061         if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
6062                 dev_kfree_skb(skb);
6063                 return NETDEV_TX_OK;
6064         }
6065
6066         sp = skb_shinfo(skb);
6067         mapping = sp->dma_maps[0];
6068
6069         tx_buf = &txr->tx_buf_ring[ring_prod];
6070         tx_buf->skb = skb;
6071
6072         txbd = &txr->tx_desc_ring[ring_prod];
6073
6074         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6075         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6076         txbd->tx_bd_mss_nbytes = len | (mss << 16);
6077         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6078
6079         last_frag = skb_shinfo(skb)->nr_frags;
6080
6081         for (i = 0; i < last_frag; i++) {
6082                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6083
6084                 prod = NEXT_TX_BD(prod);
6085                 ring_prod = TX_RING_IDX(prod);
6086                 txbd = &txr->tx_desc_ring[ring_prod];
6087
6088                 len = frag->size;
6089                 mapping = sp->dma_maps[i + 1];
6090
6091                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6092                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6093                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6094                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6095
6096         }
6097         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6098
6099         prod = NEXT_TX_BD(prod);
6100         txr->tx_prod_bseq += skb->len;
6101
6102         REG_WR16(bp, txr->tx_bidx_addr, prod);
6103         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6104
6105         mmiowb();
6106
6107         txr->tx_prod = prod;
6108         dev->trans_start = jiffies;
6109
6110         if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6111                 netif_tx_stop_queue(txq);
6112                 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6113                         netif_tx_wake_queue(txq);
6114         }
6115
6116         return NETDEV_TX_OK;
6117 }
6118
6119 /* Called with rtnl_lock */
6120 static int
6121 bnx2_close(struct net_device *dev)
6122 {
6123         struct bnx2 *bp = netdev_priv(dev);
6124
6125         cancel_work_sync(&bp->reset_task);
6126
6127         bnx2_disable_int_sync(bp);
6128         bnx2_napi_disable(bp);
6129         del_timer_sync(&bp->timer);
6130         bnx2_shutdown_chip(bp);
6131         bnx2_free_irq(bp);
6132         bnx2_free_skbs(bp);
6133         bnx2_free_mem(bp);
6134         bp->link_up = 0;
6135         netif_carrier_off(bp->dev);
6136         bnx2_set_power_state(bp, PCI_D3hot);
6137         return 0;
6138 }
6139
6140 #define GET_NET_STATS64(ctr)                                    \
6141         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
6142         (unsigned long) (ctr##_lo)
6143
6144 #define GET_NET_STATS32(ctr)            \
6145         (ctr##_lo)
6146
6147 #if (BITS_PER_LONG == 64)
6148 #define GET_NET_STATS   GET_NET_STATS64
6149 #else
6150 #define GET_NET_STATS   GET_NET_STATS32
6151 #endif
6152
6153 static struct net_device_stats *
6154 bnx2_get_stats(struct net_device *dev)
6155 {
6156         struct bnx2 *bp = netdev_priv(dev);
6157         struct statistics_block *stats_blk = bp->stats_blk;
6158         struct net_device_stats *net_stats = &bp->net_stats;
6159
6160         if (bp->stats_blk == NULL) {
6161                 return net_stats;
6162         }
6163         net_stats->rx_packets =
6164                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6165                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6166                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6167
6168         net_stats->tx_packets =
6169                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6170                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6171                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6172
6173         net_stats->rx_bytes =
6174                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6175
6176         net_stats->tx_bytes =
6177                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6178
6179         net_stats->multicast =
6180                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6181
6182         net_stats->collisions =
6183                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6184
6185         net_stats->rx_length_errors =
6186                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6187                 stats_blk->stat_EtherStatsOverrsizePkts);
6188
6189         net_stats->rx_over_errors =
6190                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6191
6192         net_stats->rx_frame_errors =
6193                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6194
6195         net_stats->rx_crc_errors =
6196                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6197
6198         net_stats->rx_errors = net_stats->rx_length_errors +
6199                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6200                 net_stats->rx_crc_errors;
6201
6202         net_stats->tx_aborted_errors =
6203                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6204                 stats_blk->stat_Dot3StatsLateCollisions);
6205
6206         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6207             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6208                 net_stats->tx_carrier_errors = 0;
6209         else {
6210                 net_stats->tx_carrier_errors =
6211                         (unsigned long)
6212                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
6213         }
6214
6215         net_stats->tx_errors =
6216                 (unsigned long)
6217                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6218                 +
6219                 net_stats->tx_aborted_errors +
6220                 net_stats->tx_carrier_errors;
6221
6222         net_stats->rx_missed_errors =
6223                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6224                 stats_blk->stat_FwRxDrop);
6225
6226         return net_stats;
6227 }
6228
6229 /* All ethtool functions called with rtnl_lock */
6230
6231 static int
6232 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6233 {
6234         struct bnx2 *bp = netdev_priv(dev);
6235         int support_serdes = 0, support_copper = 0;
6236
6237         cmd->supported = SUPPORTED_Autoneg;
6238         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6239                 support_serdes = 1;
6240                 support_copper = 1;
6241         } else if (bp->phy_port == PORT_FIBRE)
6242                 support_serdes = 1;
6243         else
6244                 support_copper = 1;
6245
6246         if (support_serdes) {
6247                 cmd->supported |= SUPPORTED_1000baseT_Full |
6248                         SUPPORTED_FIBRE;
6249                 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6250                         cmd->supported |= SUPPORTED_2500baseX_Full;
6251
6252         }
6253         if (support_copper) {
6254                 cmd->supported |= SUPPORTED_10baseT_Half |
6255                         SUPPORTED_10baseT_Full |
6256                         SUPPORTED_100baseT_Half |
6257                         SUPPORTED_100baseT_Full |
6258                         SUPPORTED_1000baseT_Full |
6259                         SUPPORTED_TP;
6260
6261         }
6262
6263         spin_lock_bh(&bp->phy_lock);
6264         cmd->port = bp->phy_port;
6265         cmd->advertising = bp->advertising;
6266
6267         if (bp->autoneg & AUTONEG_SPEED) {
6268                 cmd->autoneg = AUTONEG_ENABLE;
6269         }
6270         else {
6271                 cmd->autoneg = AUTONEG_DISABLE;
6272         }
6273
6274         if (netif_carrier_ok(dev)) {
6275                 cmd->speed = bp->line_speed;
6276                 cmd->duplex = bp->duplex;
6277         }
6278         else {
6279                 cmd->speed = -1;
6280                 cmd->duplex = -1;
6281         }
6282         spin_unlock_bh(&bp->phy_lock);
6283
6284         cmd->transceiver = XCVR_INTERNAL;
6285         cmd->phy_address = bp->phy_addr;
6286
6287         return 0;
6288 }
6289
6290 static int
6291 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6292 {
6293         struct bnx2 *bp = netdev_priv(dev);
6294         u8 autoneg = bp->autoneg;
6295         u8 req_duplex = bp->req_duplex;
6296         u16 req_line_speed = bp->req_line_speed;
6297         u32 advertising = bp->advertising;
6298         int err = -EINVAL;
6299
6300         spin_lock_bh(&bp->phy_lock);
6301
6302         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6303                 goto err_out_unlock;
6304
6305         if (cmd->port != bp->phy_port &&
6306             !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6307                 goto err_out_unlock;
6308
6309         /* If device is down, we can store the settings only if the user
6310          * is setting the currently active port.
6311          */
6312         if (!netif_running(dev) && cmd->port != bp->phy_port)
6313                 goto err_out_unlock;
6314
6315         if (cmd->autoneg == AUTONEG_ENABLE) {
6316                 autoneg |= AUTONEG_SPEED;
6317
6318                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6319
6320                 /* allow advertising 1 speed */
6321                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6322                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
6323                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
6324                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
6325
6326                         if (cmd->port == PORT_FIBRE)
6327                                 goto err_out_unlock;
6328
6329                         advertising = cmd->advertising;
6330
6331                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6332                         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6333                             (cmd->port == PORT_TP))
6334                                 goto err_out_unlock;
6335                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6336                         advertising = cmd->advertising;
6337                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6338                         goto err_out_unlock;
6339                 else {
6340                         if (cmd->port == PORT_FIBRE)
6341                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6342                         else
6343                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
6344                 }
6345                 advertising |= ADVERTISED_Autoneg;
6346         }
6347         else {
6348                 if (cmd->port == PORT_FIBRE) {
6349                         if ((cmd->speed != SPEED_1000 &&
6350                              cmd->speed != SPEED_2500) ||
6351                             (cmd->duplex != DUPLEX_FULL))
6352                                 goto err_out_unlock;
6353
6354                         if (cmd->speed == SPEED_2500 &&
6355                             !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6356                                 goto err_out_unlock;
6357                 }
6358                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6359                         goto err_out_unlock;
6360
6361                 autoneg &= ~AUTONEG_SPEED;
6362                 req_line_speed = cmd->speed;
6363                 req_duplex = cmd->duplex;
6364                 advertising = 0;
6365         }
6366
6367         bp->autoneg = autoneg;
6368         bp->advertising = advertising;
6369         bp->req_line_speed = req_line_speed;
6370         bp->req_duplex = req_duplex;
6371
6372         err = 0;
6373         /* If device is down, the new settings will be picked up when it is
6374          * brought up.
6375          */
6376         if (netif_running(dev))
6377                 err = bnx2_setup_phy(bp, cmd->port);
6378
6379 err_out_unlock:
6380         spin_unlock_bh(&bp->phy_lock);
6381
6382         return err;
6383 }
6384
6385 static void
6386 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6387 {
6388         struct bnx2 *bp = netdev_priv(dev);
6389
6390         strcpy(info->driver, DRV_MODULE_NAME);
6391         strcpy(info->version, DRV_MODULE_VERSION);
6392         strcpy(info->bus_info, pci_name(bp->pdev));
6393         strcpy(info->fw_version, bp->fw_version);
6394 }
6395
6396 #define BNX2_REGDUMP_LEN                (32 * 1024)
6397
6398 static int
6399 bnx2_get_regs_len(struct net_device *dev)
6400 {
6401         return BNX2_REGDUMP_LEN;
6402 }
6403
6404 static void
6405 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6406 {
6407         u32 *p = _p, i, offset;
6408         u8 *orig_p = _p;
6409         struct bnx2 *bp = netdev_priv(dev);
6410         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6411                                  0x0800, 0x0880, 0x0c00, 0x0c10,
6412                                  0x0c30, 0x0d08, 0x1000, 0x101c,
6413                                  0x1040, 0x1048, 0x1080, 0x10a4,
6414                                  0x1400, 0x1490, 0x1498, 0x14f0,
6415                                  0x1500, 0x155c, 0x1580, 0x15dc,
6416                                  0x1600, 0x1658, 0x1680, 0x16d8,
6417                                  0x1800, 0x1820, 0x1840, 0x1854,
6418                                  0x1880, 0x1894, 0x1900, 0x1984,
6419                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6420                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
6421                                  0x2000, 0x2030, 0x23c0, 0x2400,
6422                                  0x2800, 0x2820, 0x2830, 0x2850,
6423                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
6424                                  0x3c00, 0x3c94, 0x4000, 0x4010,
6425                                  0x4080, 0x4090, 0x43c0, 0x4458,
6426                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
6427                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
6428                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
6429                                  0x5fc0, 0x6000, 0x6400, 0x6428,
6430                                  0x6800, 0x6848, 0x684c, 0x6860,
6431                                  0x6888, 0x6910, 0x8000 };
6432
6433         regs->version = 0;
6434
6435         memset(p, 0, BNX2_REGDUMP_LEN);
6436
6437         if (!netif_running(bp->dev))
6438                 return;
6439
6440         i = 0;
6441         offset = reg_boundaries[0];
6442         p += offset;
6443         while (offset < BNX2_REGDUMP_LEN) {
6444                 *p++ = REG_RD(bp, offset);
6445                 offset += 4;
6446                 if (offset == reg_boundaries[i + 1]) {
6447                         offset = reg_boundaries[i + 2];
6448                         p = (u32 *) (orig_p + offset);
6449                         i += 2;
6450                 }
6451         }
6452 }
6453
6454 static void
6455 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6456 {
6457         struct bnx2 *bp = netdev_priv(dev);
6458
6459         if (bp->flags & BNX2_FLAG_NO_WOL) {
6460                 wol->supported = 0;
6461                 wol->wolopts = 0;
6462         }
6463         else {
6464                 wol->supported = WAKE_MAGIC;
6465                 if (bp->wol)
6466                         wol->wolopts = WAKE_MAGIC;
6467                 else
6468                         wol->wolopts = 0;
6469         }
6470         memset(&wol->sopass, 0, sizeof(wol->sopass));
6471 }
6472
6473 static int
6474 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6475 {
6476         struct bnx2 *bp = netdev_priv(dev);
6477
6478         if (wol->wolopts & ~WAKE_MAGIC)
6479                 return -EINVAL;
6480
6481         if (wol->wolopts & WAKE_MAGIC) {
6482                 if (bp->flags & BNX2_FLAG_NO_WOL)
6483                         return -EINVAL;
6484
6485                 bp->wol = 1;
6486         }
6487         else {
6488                 bp->wol = 0;
6489         }
6490         return 0;
6491 }
6492
6493 static int
6494 bnx2_nway_reset(struct net_device *dev)
6495 {
6496         struct bnx2 *bp = netdev_priv(dev);
6497         u32 bmcr;
6498
6499         if (!netif_running(dev))
6500                 return -EAGAIN;
6501
6502         if (!(bp->autoneg & AUTONEG_SPEED)) {
6503                 return -EINVAL;
6504         }
6505
6506         spin_lock_bh(&bp->phy_lock);
6507
6508         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6509                 int rc;
6510
6511                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6512                 spin_unlock_bh(&bp->phy_lock);
6513                 return rc;
6514         }
6515
6516         /* Force a link down visible on the other side */
6517         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6518                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6519                 spin_unlock_bh(&bp->phy_lock);
6520
6521                 msleep(20);
6522
6523                 spin_lock_bh(&bp->phy_lock);
6524
6525                 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6526                 bp->serdes_an_pending = 1;
6527                 mod_timer(&bp->timer, jiffies + bp->current_interval);
6528         }
6529
6530         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6531         bmcr &= ~BMCR_LOOPBACK;
6532         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6533
6534         spin_unlock_bh(&bp->phy_lock);
6535
6536         return 0;
6537 }
6538
6539 static int
6540 bnx2_get_eeprom_len(struct net_device *dev)
6541 {
6542         struct bnx2 *bp = netdev_priv(dev);
6543
6544         if (bp->flash_info == NULL)
6545                 return 0;
6546
6547         return (int) bp->flash_size;
6548 }
6549
6550 static int
6551 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6552                 u8 *eebuf)
6553 {
6554         struct bnx2 *bp = netdev_priv(dev);
6555         int rc;
6556
6557         if (!netif_running(dev))
6558                 return -EAGAIN;
6559
6560         /* parameters already validated in ethtool_get_eeprom */
6561
6562         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6563
6564         return rc;
6565 }
6566
6567 static int
6568 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6569                 u8 *eebuf)
6570 {
6571         struct bnx2 *bp = netdev_priv(dev);
6572         int rc;
6573
6574         if (!netif_running(dev))
6575                 return -EAGAIN;
6576
6577         /* parameters already validated in ethtool_set_eeprom */
6578
6579         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6580
6581         return rc;
6582 }
6583
6584 static int
6585 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6586 {
6587         struct bnx2 *bp = netdev_priv(dev);
6588
6589         memset(coal, 0, sizeof(struct ethtool_coalesce));
6590
6591         coal->rx_coalesce_usecs = bp->rx_ticks;
6592         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6593         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6594         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6595
6596         coal->tx_coalesce_usecs = bp->tx_ticks;
6597         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6598         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6599         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6600
6601         coal->stats_block_coalesce_usecs = bp->stats_ticks;
6602
6603         return 0;
6604 }
6605
6606 static int
6607 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6608 {
6609         struct bnx2 *bp = netdev_priv(dev);
6610
6611         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6612         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6613
6614         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6615         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6616
6617         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6618         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6619
6620         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6621         if (bp->rx_quick_cons_trip_int > 0xff)
6622                 bp->rx_quick_cons_trip_int = 0xff;
6623
6624         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6625         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6626
6627         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6628         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6629
6630         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6631         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6632
6633         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6634         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6635                 0xff;
6636
6637         bp->stats_ticks = coal->stats_block_coalesce_usecs;
6638         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6639                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6640                         bp->stats_ticks = USEC_PER_SEC;
6641         }
6642         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6643                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6644         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6645
6646         if (netif_running(bp->dev)) {
6647                 bnx2_netif_stop(bp);
6648                 bnx2_init_nic(bp, 0);
6649                 bnx2_netif_start(bp);
6650         }
6651
6652         return 0;
6653 }
6654
6655 static void
6656 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6657 {
6658         struct bnx2 *bp = netdev_priv(dev);
6659
6660         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6661         ering->rx_mini_max_pending = 0;
6662         ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6663
6664         ering->rx_pending = bp->rx_ring_size;
6665         ering->rx_mini_pending = 0;
6666         ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6667
6668         ering->tx_max_pending = MAX_TX_DESC_CNT;
6669         ering->tx_pending = bp->tx_ring_size;
6670 }
6671
6672 static int
6673 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6674 {
6675         if (netif_running(bp->dev)) {
6676                 bnx2_netif_stop(bp);
6677                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6678                 bnx2_free_skbs(bp);
6679                 bnx2_free_mem(bp);
6680         }
6681
6682         bnx2_set_rx_ring_size(bp, rx);
6683         bp->tx_ring_size = tx;
6684
6685         if (netif_running(bp->dev)) {
6686                 int rc;
6687
6688                 rc = bnx2_alloc_mem(bp);
6689                 if (rc)
6690                         return rc;
6691                 bnx2_init_nic(bp, 0);
6692                 bnx2_netif_start(bp);
6693         }
6694         return 0;
6695 }
6696
6697 static int
6698 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6699 {
6700         struct bnx2 *bp = netdev_priv(dev);
6701         int rc;
6702
6703         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6704                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6705                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6706
6707                 return -EINVAL;
6708         }
6709         rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6710         return rc;
6711 }
6712
6713 static void
6714 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6715 {
6716         struct bnx2 *bp = netdev_priv(dev);
6717
6718         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6719         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6720         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6721 }
6722
6723 static int
6724 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6725 {
6726         struct bnx2 *bp = netdev_priv(dev);
6727
6728         bp->req_flow_ctrl = 0;
6729         if (epause->rx_pause)
6730                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6731         if (epause->tx_pause)
6732                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6733
6734         if (epause->autoneg) {
6735                 bp->autoneg |= AUTONEG_FLOW_CTRL;
6736         }
6737         else {
6738                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6739         }
6740
6741         if (netif_running(dev)) {
6742                 spin_lock_bh(&bp->phy_lock);
6743                 bnx2_setup_phy(bp, bp->phy_port);
6744                 spin_unlock_bh(&bp->phy_lock);
6745         }
6746
6747         return 0;
6748 }
6749
6750 static u32
6751 bnx2_get_rx_csum(struct net_device *dev)
6752 {
6753         struct bnx2 *bp = netdev_priv(dev);
6754
6755         return bp->rx_csum;
6756 }
6757
6758 static int
6759 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6760 {
6761         struct bnx2 *bp = netdev_priv(dev);
6762
6763         bp->rx_csum = data;
6764         return 0;
6765 }
6766
6767 static int
6768 bnx2_set_tso(struct net_device *dev, u32 data)
6769 {
6770         struct bnx2 *bp = netdev_priv(dev);
6771
6772         if (data) {
6773                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6774                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6775                         dev->features |= NETIF_F_TSO6;
6776         } else
6777                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6778                                    NETIF_F_TSO_ECN);
6779         return 0;
6780 }
6781
6782 #define BNX2_NUM_STATS 46
6783
6784 static struct {
6785         char string[ETH_GSTRING_LEN];
6786 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6787         { "rx_bytes" },
6788         { "rx_error_bytes" },
6789         { "tx_bytes" },
6790         { "tx_error_bytes" },
6791         { "rx_ucast_packets" },
6792         { "rx_mcast_packets" },
6793         { "rx_bcast_packets" },
6794         { "tx_ucast_packets" },
6795         { "tx_mcast_packets" },
6796         { "tx_bcast_packets" },
6797         { "tx_mac_errors" },
6798         { "tx_carrier_errors" },
6799         { "rx_crc_errors" },
6800         { "rx_align_errors" },
6801         { "tx_single_collisions" },
6802         { "tx_multi_collisions" },
6803         { "tx_deferred" },
6804         { "tx_excess_collisions" },
6805         { "tx_late_collisions" },
6806         { "tx_total_collisions" },
6807         { "rx_fragments" },
6808         { "rx_jabbers" },
6809         { "rx_undersize_packets" },
6810         { "rx_oversize_packets" },
6811         { "rx_64_byte_packets" },
6812         { "rx_65_to_127_byte_packets" },
6813         { "rx_128_to_255_byte_packets" },
6814         { "rx_256_to_511_byte_packets" },
6815         { "rx_512_to_1023_byte_packets" },
6816         { "rx_1024_to_1522_byte_packets" },
6817         { "rx_1523_to_9022_byte_packets" },
6818         { "tx_64_byte_packets" },
6819         { "tx_65_to_127_byte_packets" },
6820         { "tx_128_to_255_byte_packets" },
6821         { "tx_256_to_511_byte_packets" },
6822         { "tx_512_to_1023_byte_packets" },
6823         { "tx_1024_to_1522_byte_packets" },
6824         { "tx_1523_to_9022_byte_packets" },
6825         { "rx_xon_frames" },
6826         { "rx_xoff_frames" },
6827         { "tx_xon_frames" },
6828         { "tx_xoff_frames" },
6829         { "rx_mac_ctrl_frames" },
6830         { "rx_filtered_packets" },
6831         { "rx_discards" },
6832         { "rx_fw_discards" },
6833 };
6834
6835 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6836
6837 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6838     STATS_OFFSET32(stat_IfHCInOctets_hi),
6839     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6840     STATS_OFFSET32(stat_IfHCOutOctets_hi),
6841     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6842     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6843     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6844     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6845     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6846     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6847     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6848     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6849     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6850     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6851     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6852     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6853     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6854     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6855     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6856     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6857     STATS_OFFSET32(stat_EtherStatsCollisions),
6858     STATS_OFFSET32(stat_EtherStatsFragments),
6859     STATS_OFFSET32(stat_EtherStatsJabbers),
6860     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6861     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6862     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6863     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6864     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6865     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6866     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6867     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6868     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6869     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6870     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6871     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6872     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6873     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6874     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6875     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6876     STATS_OFFSET32(stat_XonPauseFramesReceived),
6877     STATS_OFFSET32(stat_XoffPauseFramesReceived),
6878     STATS_OFFSET32(stat_OutXonSent),
6879     STATS_OFFSET32(stat_OutXoffSent),
6880     STATS_OFFSET32(stat_MacControlFramesReceived),
6881     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6882     STATS_OFFSET32(stat_IfInMBUFDiscards),
6883     STATS_OFFSET32(stat_FwRxDrop),
6884 };
6885
6886 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6887  * skipped because of errata.
6888  */
6889 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6890         8,0,8,8,8,8,8,8,8,8,
6891         4,0,4,4,4,4,4,4,4,4,
6892         4,4,4,4,4,4,4,4,4,4,
6893         4,4,4,4,4,4,4,4,4,4,
6894         4,4,4,4,4,4,
6895 };
6896
6897 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6898         8,0,8,8,8,8,8,8,8,8,
6899         4,4,4,4,4,4,4,4,4,4,
6900         4,4,4,4,4,4,4,4,4,4,
6901         4,4,4,4,4,4,4,4,4,4,
6902         4,4,4,4,4,4,
6903 };
6904
6905 #define BNX2_NUM_TESTS 6
6906
6907 static struct {
6908         char string[ETH_GSTRING_LEN];
6909 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6910         { "register_test (offline)" },
6911         { "memory_test (offline)" },
6912         { "loopback_test (offline)" },
6913         { "nvram_test (online)" },
6914         { "interrupt_test (online)" },
6915         { "link_test (online)" },
6916 };
6917
6918 static int
6919 bnx2_get_sset_count(struct net_device *dev, int sset)
6920 {
6921         switch (sset) {
6922         case ETH_SS_TEST:
6923                 return BNX2_NUM_TESTS;
6924         case ETH_SS_STATS:
6925                 return BNX2_NUM_STATS;
6926         default:
6927                 return -EOPNOTSUPP;
6928         }
6929 }
6930
6931 static void
6932 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6933 {
6934         struct bnx2 *bp = netdev_priv(dev);
6935
6936         bnx2_set_power_state(bp, PCI_D0);
6937
6938         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6939         if (etest->flags & ETH_TEST_FL_OFFLINE) {
6940                 int i;
6941
6942                 bnx2_netif_stop(bp);
6943                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6944                 bnx2_free_skbs(bp);
6945
6946                 if (bnx2_test_registers(bp) != 0) {
6947                         buf[0] = 1;
6948                         etest->flags |= ETH_TEST_FL_FAILED;
6949                 }
6950                 if (bnx2_test_memory(bp) != 0) {
6951                         buf[1] = 1;
6952                         etest->flags |= ETH_TEST_FL_FAILED;
6953                 }
6954                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6955                         etest->flags |= ETH_TEST_FL_FAILED;
6956
6957                 if (!netif_running(bp->dev))
6958                         bnx2_shutdown_chip(bp);
6959                 else {
6960                         bnx2_init_nic(bp, 1);
6961                         bnx2_netif_start(bp);
6962                 }
6963
6964                 /* wait for link up */
6965                 for (i = 0; i < 7; i++) {
6966                         if (bp->link_up)
6967                                 break;
6968                         msleep_interruptible(1000);
6969                 }
6970         }
6971
6972         if (bnx2_test_nvram(bp) != 0) {
6973                 buf[3] = 1;
6974                 etest->flags |= ETH_TEST_FL_FAILED;
6975         }
6976         if (bnx2_test_intr(bp) != 0) {
6977                 buf[4] = 1;
6978                 etest->flags |= ETH_TEST_FL_FAILED;
6979         }
6980
6981         if (bnx2_test_link(bp) != 0) {
6982                 buf[5] = 1;
6983                 etest->flags |= ETH_TEST_FL_FAILED;
6984
6985         }
6986         if (!netif_running(bp->dev))
6987                 bnx2_set_power_state(bp, PCI_D3hot);
6988 }
6989
6990 static void
6991 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6992 {
6993         switch (stringset) {
6994         case ETH_SS_STATS:
6995                 memcpy(buf, bnx2_stats_str_arr,
6996                         sizeof(bnx2_stats_str_arr));
6997                 break;
6998         case ETH_SS_TEST:
6999                 memcpy(buf, bnx2_tests_str_arr,
7000                         sizeof(bnx2_tests_str_arr));
7001                 break;
7002         }
7003 }
7004
7005 static void
7006 bnx2_get_ethtool_stats(struct net_device *dev,
7007                 struct ethtool_stats *stats, u64 *buf)
7008 {
7009         struct bnx2 *bp = netdev_priv(dev);
7010         int i;
7011         u32 *hw_stats = (u32 *) bp->stats_blk;
7012         u8 *stats_len_arr = NULL;
7013
7014         if (hw_stats == NULL) {
7015                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7016                 return;
7017         }
7018
7019         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7020             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7021             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7022             (CHIP_ID(bp) == CHIP_ID_5708_A0))
7023                 stats_len_arr = bnx2_5706_stats_len_arr;
7024         else
7025                 stats_len_arr = bnx2_5708_stats_len_arr;
7026
7027         for (i = 0; i < BNX2_NUM_STATS; i++) {
7028                 if (stats_len_arr[i] == 0) {
7029                         /* skip this counter */
7030                         buf[i] = 0;
7031                         continue;
7032                 }
7033                 if (stats_len_arr[i] == 4) {
7034                         /* 4-byte counter */
7035                         buf[i] = (u64)
7036                                 *(hw_stats + bnx2_stats_offset_arr[i]);
7037                         continue;
7038                 }
7039                 /* 8-byte counter */
7040                 buf[i] = (((u64) *(hw_stats +
7041                                         bnx2_stats_offset_arr[i])) << 32) +
7042                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7043         }
7044 }
7045
7046 static int
7047 bnx2_phys_id(struct net_device *dev, u32 data)
7048 {
7049         struct bnx2 *bp = netdev_priv(dev);
7050         int i;
7051         u32 save;
7052
7053         bnx2_set_power_state(bp, PCI_D0);
7054
7055         if (data == 0)
7056                 data = 2;
7057
7058         save = REG_RD(bp, BNX2_MISC_CFG);
7059         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7060
7061         for (i = 0; i < (data * 2); i++) {
7062                 if ((i % 2) == 0) {
7063                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7064                 }
7065                 else {
7066                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7067                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
7068                                 BNX2_EMAC_LED_100MB_OVERRIDE |
7069                                 BNX2_EMAC_LED_10MB_OVERRIDE |
7070                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7071                                 BNX2_EMAC_LED_TRAFFIC);
7072                 }
7073                 msleep_interruptible(500);
7074                 if (signal_pending(current))
7075                         break;
7076         }
7077         REG_WR(bp, BNX2_EMAC_LED, 0);
7078         REG_WR(bp, BNX2_MISC_CFG, save);
7079
7080         if (!netif_running(dev))
7081                 bnx2_set_power_state(bp, PCI_D3hot);
7082
7083         return 0;
7084 }
7085
7086 static int
7087 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7088 {
7089         struct bnx2 *bp = netdev_priv(dev);
7090
7091         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7092                 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7093         else
7094                 return (ethtool_op_set_tx_csum(dev, data));
7095 }
7096
7097 static const struct ethtool_ops bnx2_ethtool_ops = {
7098         .get_settings           = bnx2_get_settings,
7099         .set_settings           = bnx2_set_settings,
7100         .get_drvinfo            = bnx2_get_drvinfo,
7101         .get_regs_len           = bnx2_get_regs_len,
7102         .get_regs               = bnx2_get_regs,
7103         .get_wol                = bnx2_get_wol,
7104         .set_wol                = bnx2_set_wol,
7105         .nway_reset             = bnx2_nway_reset,
7106         .get_link               = ethtool_op_get_link,
7107         .get_eeprom_len         = bnx2_get_eeprom_len,
7108         .get_eeprom             = bnx2_get_eeprom,
7109         .set_eeprom             = bnx2_set_eeprom,
7110         .get_coalesce           = bnx2_get_coalesce,
7111         .set_coalesce           = bnx2_set_coalesce,
7112         .get_ringparam          = bnx2_get_ringparam,
7113         .set_ringparam          = bnx2_set_ringparam,
7114         .get_pauseparam         = bnx2_get_pauseparam,
7115         .set_pauseparam         = bnx2_set_pauseparam,
7116         .get_rx_csum            = bnx2_get_rx_csum,
7117         .set_rx_csum            = bnx2_set_rx_csum,
7118         .set_tx_csum            = bnx2_set_tx_csum,
7119         .set_sg                 = ethtool_op_set_sg,
7120         .set_tso                = bnx2_set_tso,
7121         .self_test              = bnx2_self_test,
7122         .get_strings            = bnx2_get_strings,
7123         .phys_id                = bnx2_phys_id,
7124         .get_ethtool_stats      = bnx2_get_ethtool_stats,
7125         .get_sset_count         = bnx2_get_sset_count,
7126 };
7127
7128 /* Called with rtnl_lock */
7129 static int
7130 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7131 {
7132         struct mii_ioctl_data *data = if_mii(ifr);
7133         struct bnx2 *bp = netdev_priv(dev);
7134         int err;
7135
7136         switch(cmd) {
7137         case SIOCGMIIPHY:
7138                 data->phy_id = bp->phy_addr;
7139
7140                 /* fallthru */
7141         case SIOCGMIIREG: {
7142                 u32 mii_regval;
7143
7144                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7145                         return -EOPNOTSUPP;
7146
7147                 if (!netif_running(dev))
7148                         return -EAGAIN;
7149
7150                 spin_lock_bh(&bp->phy_lock);
7151                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7152                 spin_unlock_bh(&bp->phy_lock);
7153
7154                 data->val_out = mii_regval;
7155
7156                 return err;
7157         }
7158
7159         case SIOCSMIIREG:
7160                 if (!capable(CAP_NET_ADMIN))
7161                         return -EPERM;
7162
7163                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7164                         return -EOPNOTSUPP;
7165
7166                 if (!netif_running(dev))
7167                         return -EAGAIN;
7168
7169                 spin_lock_bh(&bp->phy_lock);
7170                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7171                 spin_unlock_bh(&bp->phy_lock);
7172
7173                 return err;
7174
7175         default:
7176                 /* do nothing */
7177                 break;
7178         }
7179         return -EOPNOTSUPP;
7180 }
7181
7182 /* Called with rtnl_lock */
7183 static int
7184 bnx2_change_mac_addr(struct net_device *dev, void *p)
7185 {
7186         struct sockaddr *addr = p;
7187         struct bnx2 *bp = netdev_priv(dev);
7188
7189         if (!is_valid_ether_addr(addr->sa_data))
7190                 return -EINVAL;
7191
7192         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7193         if (netif_running(dev))
7194                 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7195
7196         return 0;
7197 }
7198
7199 /* Called with rtnl_lock */
7200 static int
7201 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7202 {
7203         struct bnx2 *bp = netdev_priv(dev);
7204
7205         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7206                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7207                 return -EINVAL;
7208
7209         dev->mtu = new_mtu;
7210         return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7211 }
7212
7213 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7214 static void
7215 poll_bnx2(struct net_device *dev)
7216 {
7217         struct bnx2 *bp = netdev_priv(dev);
7218         int i;
7219
7220         for (i = 0; i < bp->irq_nvecs; i++) {
7221                 disable_irq(bp->irq_tbl[i].vector);
7222                 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7223                 enable_irq(bp->irq_tbl[i].vector);
7224         }
7225 }
7226 #endif
7227
7228 static void __devinit
7229 bnx2_get_5709_media(struct bnx2 *bp)
7230 {
7231         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7232         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7233         u32 strap;
7234
7235         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7236                 return;
7237         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7238                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7239                 return;
7240         }
7241
7242         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7243                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7244         else
7245                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7246
7247         if (PCI_FUNC(bp->pdev->devfn) == 0) {
7248                 switch (strap) {
7249                 case 0x4:
7250                 case 0x5:
7251                 case 0x6:
7252                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7253                         return;
7254                 }
7255         } else {
7256                 switch (strap) {
7257                 case 0x1:
7258                 case 0x2:
7259                 case 0x4:
7260                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7261                         return;
7262                 }
7263         }
7264 }
7265
7266 static void __devinit
7267 bnx2_get_pci_speed(struct bnx2 *bp)
7268 {
7269         u32 reg;
7270
7271         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7272         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7273                 u32 clkreg;
7274
7275                 bp->flags |= BNX2_FLAG_PCIX;
7276
7277                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7278
7279                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7280                 switch (clkreg) {
7281                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7282                         bp->bus_speed_mhz = 133;
7283                         break;
7284
7285                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7286                         bp->bus_speed_mhz = 100;
7287                         break;
7288
7289                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7290                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7291                         bp->bus_speed_mhz = 66;
7292                         break;
7293
7294                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7295                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7296                         bp->bus_speed_mhz = 50;
7297                         break;
7298
7299                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7300                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7301                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7302                         bp->bus_speed_mhz = 33;
7303                         break;
7304                 }
7305         }
7306         else {
7307                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7308                         bp->bus_speed_mhz = 66;
7309                 else
7310                         bp->bus_speed_mhz = 33;
7311         }
7312
7313         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7314                 bp->flags |= BNX2_FLAG_PCI_32BIT;
7315
7316 }
7317
7318 static int __devinit
7319 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7320 {
7321         struct bnx2 *bp;
7322         unsigned long mem_len;
7323         int rc, i, j;
7324         u32 reg;
7325         u64 dma_mask, persist_dma_mask;
7326
7327         SET_NETDEV_DEV(dev, &pdev->dev);
7328         bp = netdev_priv(dev);
7329
7330         bp->flags = 0;
7331         bp->phy_flags = 0;
7332
7333         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7334         rc = pci_enable_device(pdev);
7335         if (rc) {
7336                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7337                 goto err_out;
7338         }
7339
7340         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7341                 dev_err(&pdev->dev,
7342                         "Cannot find PCI device base address, aborting.\n");
7343                 rc = -ENODEV;
7344                 goto err_out_disable;
7345         }
7346
7347         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7348         if (rc) {
7349                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7350                 goto err_out_disable;
7351         }
7352
7353         pci_set_master(pdev);
7354         pci_save_state(pdev);
7355
7356         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7357         if (bp->pm_cap == 0) {
7358                 dev_err(&pdev->dev,
7359                         "Cannot find power management capability, aborting.\n");
7360                 rc = -EIO;
7361                 goto err_out_release;
7362         }
7363
7364         bp->dev = dev;
7365         bp->pdev = pdev;
7366
7367         spin_lock_init(&bp->phy_lock);
7368         spin_lock_init(&bp->indirect_lock);
7369         INIT_WORK(&bp->reset_task, bnx2_reset_task);
7370
7371         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7372         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7373         dev->mem_end = dev->mem_start + mem_len;
7374         dev->irq = pdev->irq;
7375
7376         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7377
7378         if (!bp->regview) {
7379                 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7380                 rc = -ENOMEM;
7381                 goto err_out_release;
7382         }
7383
7384         /* Configure byte swap and enable write to the reg_window registers.
7385          * Rely on CPU to do target byte swapping on big endian systems
7386          * The chip's target access swapping will not swap all accesses
7387          */
7388         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7389                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7390                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7391
7392         bnx2_set_power_state(bp, PCI_D0);
7393
7394         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7395
7396         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7397                 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7398                         dev_err(&pdev->dev,
7399                                 "Cannot find PCIE capability, aborting.\n");
7400                         rc = -EIO;
7401                         goto err_out_unmap;
7402                 }
7403                 bp->flags |= BNX2_FLAG_PCIE;
7404                 if (CHIP_REV(bp) == CHIP_REV_Ax)
7405                         bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7406         } else {
7407                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7408                 if (bp->pcix_cap == 0) {
7409                         dev_err(&pdev->dev,
7410                                 "Cannot find PCIX capability, aborting.\n");
7411                         rc = -EIO;
7412                         goto err_out_unmap;
7413                 }
7414         }
7415
7416         if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7417                 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7418                         bp->flags |= BNX2_FLAG_MSIX_CAP;
7419         }
7420
7421         if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7422                 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7423                         bp->flags |= BNX2_FLAG_MSI_CAP;
7424         }
7425
7426         /* 5708 cannot support DMA addresses > 40-bit.  */
7427         if (CHIP_NUM(bp) == CHIP_NUM_5708)
7428                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7429         else
7430                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7431
7432         /* Configure DMA attributes. */
7433         if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7434                 dev->features |= NETIF_F_HIGHDMA;
7435                 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7436                 if (rc) {
7437                         dev_err(&pdev->dev,
7438                                 "pci_set_consistent_dma_mask failed, aborting.\n");
7439                         goto err_out_unmap;
7440                 }
7441         } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7442                 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7443                 goto err_out_unmap;
7444         }
7445
7446         if (!(bp->flags & BNX2_FLAG_PCIE))
7447                 bnx2_get_pci_speed(bp);
7448
7449         /* 5706A0 may falsely detect SERR and PERR. */
7450         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7451                 reg = REG_RD(bp, PCI_COMMAND);
7452                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7453                 REG_WR(bp, PCI_COMMAND, reg);
7454         }
7455         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7456                 !(bp->flags & BNX2_FLAG_PCIX)) {
7457
7458                 dev_err(&pdev->dev,
7459                         "5706 A1 can only be used in a PCIX bus, aborting.\n");
7460                 goto err_out_unmap;
7461         }
7462
7463         bnx2_init_nvram(bp);
7464
7465         reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7466
7467         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7468             BNX2_SHM_HDR_SIGNATURE_SIG) {
7469                 u32 off = PCI_FUNC(pdev->devfn) << 2;
7470
7471                 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7472         } else
7473                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7474
7475         /* Get the permanent MAC address.  First we need to make sure the
7476          * firmware is actually running.
7477          */
7478         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7479
7480         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7481             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7482                 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7483                 rc = -ENODEV;
7484                 goto err_out_unmap;
7485         }
7486
7487         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7488         for (i = 0, j = 0; i < 3; i++) {
7489                 u8 num, k, skip0;
7490
7491                 num = (u8) (reg >> (24 - (i * 8)));
7492                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7493                         if (num >= k || !skip0 || k == 1) {
7494                                 bp->fw_version[j++] = (num / k) + '0';
7495                                 skip0 = 0;
7496                         }
7497                 }
7498                 if (i != 2)
7499                         bp->fw_version[j++] = '.';
7500         }
7501         reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7502         if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7503                 bp->wol = 1;
7504
7505         if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7506                 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7507
7508                 for (i = 0; i < 30; i++) {
7509                         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7510                         if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7511                                 break;
7512                         msleep(10);
7513                 }
7514         }
7515         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7516         reg &= BNX2_CONDITION_MFW_RUN_MASK;
7517         if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7518             reg != BNX2_CONDITION_MFW_RUN_NONE) {
7519                 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7520
7521                 bp->fw_version[j++] = ' ';
7522                 for (i = 0; i < 3; i++) {
7523                         reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7524                         reg = swab32(reg);
7525                         memcpy(&bp->fw_version[j], &reg, 4);
7526                         j += 4;
7527                 }
7528         }
7529
7530         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7531         bp->mac_addr[0] = (u8) (reg >> 8);
7532         bp->mac_addr[1] = (u8) reg;
7533
7534         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7535         bp->mac_addr[2] = (u8) (reg >> 24);
7536         bp->mac_addr[3] = (u8) (reg >> 16);
7537         bp->mac_addr[4] = (u8) (reg >> 8);
7538         bp->mac_addr[5] = (u8) reg;
7539
7540         bp->tx_ring_size = MAX_TX_DESC_CNT;
7541         bnx2_set_rx_ring_size(bp, 255);
7542
7543         bp->rx_csum = 1;
7544
7545         bp->tx_quick_cons_trip_int = 20;
7546         bp->tx_quick_cons_trip = 20;
7547         bp->tx_ticks_int = 80;
7548         bp->tx_ticks = 80;
7549
7550         bp->rx_quick_cons_trip_int = 6;
7551         bp->rx_quick_cons_trip = 6;
7552         bp->rx_ticks_int = 18;
7553         bp->rx_ticks = 18;
7554
7555         bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7556
7557         bp->current_interval = BNX2_TIMER_INTERVAL;
7558
7559         bp->phy_addr = 1;
7560
7561         /* Disable WOL support if we are running on a SERDES chip. */
7562         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7563                 bnx2_get_5709_media(bp);
7564         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7565                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7566
7567         bp->phy_port = PORT_TP;
7568         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7569                 bp->phy_port = PORT_FIBRE;
7570                 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7571                 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7572                         bp->flags |= BNX2_FLAG_NO_WOL;
7573                         bp->wol = 0;
7574                 }
7575                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7576                         /* Don't do parallel detect on this board because of
7577                          * some board problems.  The link will not go down
7578                          * if we do parallel detect.
7579                          */
7580                         if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7581                             pdev->subsystem_device == 0x310c)
7582                                 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7583                 } else {
7584                         bp->phy_addr = 2;
7585                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7586                                 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7587                 }
7588         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7589                    CHIP_NUM(bp) == CHIP_NUM_5708)
7590                 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7591         else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7592                  (CHIP_REV(bp) == CHIP_REV_Ax ||
7593                   CHIP_REV(bp) == CHIP_REV_Bx))
7594                 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7595
7596         bnx2_init_fw_cap(bp);
7597
7598         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7599             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7600             (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
7601             !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7602                 bp->flags |= BNX2_FLAG_NO_WOL;
7603                 bp->wol = 0;
7604         }
7605
7606         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7607                 bp->tx_quick_cons_trip_int =
7608                         bp->tx_quick_cons_trip;
7609                 bp->tx_ticks_int = bp->tx_ticks;
7610                 bp->rx_quick_cons_trip_int =
7611                         bp->rx_quick_cons_trip;
7612                 bp->rx_ticks_int = bp->rx_ticks;
7613                 bp->comp_prod_trip_int = bp->comp_prod_trip;
7614                 bp->com_ticks_int = bp->com_ticks;
7615                 bp->cmd_ticks_int = bp->cmd_ticks;
7616         }
7617
7618         /* Disable MSI on 5706 if AMD 8132 bridge is found.
7619          *
7620          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
7621          * with byte enables disabled on the unused 32-bit word.  This is legal
7622          * but causes problems on the AMD 8132 which will eventually stop
7623          * responding after a while.
7624          *
7625          * AMD believes this incompatibility is unique to the 5706, and
7626          * prefers to locally disable MSI rather than globally disabling it.
7627          */
7628         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7629                 struct pci_dev *amd_8132 = NULL;
7630
7631                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7632                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
7633                                                   amd_8132))) {
7634
7635                         if (amd_8132->revision >= 0x10 &&
7636                             amd_8132->revision <= 0x13) {
7637                                 disable_msi = 1;
7638                                 pci_dev_put(amd_8132);
7639                                 break;
7640                         }
7641                 }
7642         }
7643
7644         bnx2_set_default_link(bp);
7645         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7646
7647         init_timer(&bp->timer);
7648         bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7649         bp->timer.data = (unsigned long) bp;
7650         bp->timer.function = bnx2_timer;
7651
7652         return 0;
7653
7654 err_out_unmap:
7655         if (bp->regview) {
7656                 iounmap(bp->regview);
7657                 bp->regview = NULL;
7658         }
7659
7660 err_out_release:
7661         pci_release_regions(pdev);
7662
7663 err_out_disable:
7664         pci_disable_device(pdev);
7665         pci_set_drvdata(pdev, NULL);
7666
7667 err_out:
7668         return rc;
7669 }
7670
7671 static char * __devinit
7672 bnx2_bus_string(struct bnx2 *bp, char *str)
7673 {
7674         char *s = str;
7675
7676         if (bp->flags & BNX2_FLAG_PCIE) {
7677                 s += sprintf(s, "PCI Express");
7678         } else {
7679                 s += sprintf(s, "PCI");
7680                 if (bp->flags & BNX2_FLAG_PCIX)
7681                         s += sprintf(s, "-X");
7682                 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7683                         s += sprintf(s, " 32-bit");
7684                 else
7685                         s += sprintf(s, " 64-bit");
7686                 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7687         }
7688         return str;
7689 }
7690
7691 static void __devinit
7692 bnx2_init_napi(struct bnx2 *bp)
7693 {
7694         int i;
7695
7696         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7697                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7698                 int (*poll)(struct napi_struct *, int);
7699
7700                 if (i == 0)
7701                         poll = bnx2_poll;
7702                 else
7703                         poll = bnx2_poll_msix;
7704
7705                 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7706                 bnapi->bp = bp;
7707         }
7708 }
7709
7710 static const struct net_device_ops bnx2_netdev_ops = {
7711         .ndo_open               = bnx2_open,
7712         .ndo_start_xmit         = bnx2_start_xmit,
7713         .ndo_stop               = bnx2_close,
7714         .ndo_get_stats          = bnx2_get_stats,
7715         .ndo_set_rx_mode        = bnx2_set_rx_mode,
7716         .ndo_do_ioctl           = bnx2_ioctl,
7717         .ndo_validate_addr      = eth_validate_addr,
7718         .ndo_set_mac_address    = bnx2_change_mac_addr,
7719         .ndo_change_mtu         = bnx2_change_mtu,
7720         .ndo_tx_timeout         = bnx2_tx_timeout,
7721 #ifdef BCM_VLAN
7722         .ndo_vlan_rx_register   = bnx2_vlan_rx_register,
7723 #endif
7724 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7725         .ndo_poll_controller    = poll_bnx2,
7726 #endif
7727 };
7728
7729 static int __devinit
7730 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7731 {
7732         static int version_printed = 0;
7733         struct net_device *dev = NULL;
7734         struct bnx2 *bp;
7735         int rc;
7736         char str[40];
7737
7738         if (version_printed++ == 0)
7739                 printk(KERN_INFO "%s", version);
7740
7741         /* dev zeroed in init_etherdev */
7742         dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7743
7744         if (!dev)
7745                 return -ENOMEM;
7746
7747         rc = bnx2_init_board(pdev, dev);
7748         if (rc < 0) {
7749                 free_netdev(dev);
7750                 return rc;
7751         }
7752
7753         dev->netdev_ops = &bnx2_netdev_ops;
7754         dev->watchdog_timeo = TX_TIMEOUT;
7755         dev->ethtool_ops = &bnx2_ethtool_ops;
7756
7757         bp = netdev_priv(dev);
7758         bnx2_init_napi(bp);
7759
7760         pci_set_drvdata(pdev, dev);
7761
7762         memcpy(dev->dev_addr, bp->mac_addr, 6);
7763         memcpy(dev->perm_addr, bp->mac_addr, 6);
7764
7765         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7766         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7767                 dev->features |= NETIF_F_IPV6_CSUM;
7768
7769 #ifdef BCM_VLAN
7770         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7771 #endif
7772         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7773         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7774                 dev->features |= NETIF_F_TSO6;
7775
7776         if ((rc = register_netdev(dev))) {
7777                 dev_err(&pdev->dev, "Cannot register net device\n");
7778                 if (bp->regview)
7779                         iounmap(bp->regview);
7780                 pci_release_regions(pdev);
7781                 pci_disable_device(pdev);
7782                 pci_set_drvdata(pdev, NULL);
7783                 free_netdev(dev);
7784                 return rc;
7785         }
7786
7787         printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7788                 "IRQ %d, node addr %pM\n",
7789                 dev->name,
7790                 board_info[ent->driver_data].name,
7791                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7792                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7793                 bnx2_bus_string(bp, str),
7794                 dev->base_addr,
7795                 bp->pdev->irq, dev->dev_addr);
7796
7797         return 0;
7798 }
7799
7800 static void __devexit
7801 bnx2_remove_one(struct pci_dev *pdev)
7802 {
7803         struct net_device *dev = pci_get_drvdata(pdev);
7804         struct bnx2 *bp = netdev_priv(dev);
7805
7806         flush_scheduled_work();
7807
7808         unregister_netdev(dev);
7809
7810         if (bp->regview)
7811                 iounmap(bp->regview);
7812
7813         free_netdev(dev);
7814         pci_release_regions(pdev);
7815         pci_disable_device(pdev);
7816         pci_set_drvdata(pdev, NULL);
7817 }
7818
7819 static int
7820 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7821 {
7822         struct net_device *dev = pci_get_drvdata(pdev);
7823         struct bnx2 *bp = netdev_priv(dev);
7824
7825         /* PCI register 4 needs to be saved whether netif_running() or not.
7826          * MSI address and data need to be saved if using MSI and
7827          * netif_running().
7828          */
7829         pci_save_state(pdev);
7830         if (!netif_running(dev))
7831                 return 0;
7832
7833         flush_scheduled_work();
7834         bnx2_netif_stop(bp);
7835         netif_device_detach(dev);
7836         del_timer_sync(&bp->timer);
7837         bnx2_shutdown_chip(bp);
7838         bnx2_free_skbs(bp);
7839         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7840         return 0;
7841 }
7842
7843 static int
7844 bnx2_resume(struct pci_dev *pdev)
7845 {
7846         struct net_device *dev = pci_get_drvdata(pdev);
7847         struct bnx2 *bp = netdev_priv(dev);
7848
7849         pci_restore_state(pdev);
7850         if (!netif_running(dev))
7851                 return 0;
7852
7853         bnx2_set_power_state(bp, PCI_D0);
7854         netif_device_attach(dev);
7855         bnx2_init_nic(bp, 1);
7856         bnx2_netif_start(bp);
7857         return 0;
7858 }
7859
7860 /**
7861  * bnx2_io_error_detected - called when PCI error is detected
7862  * @pdev: Pointer to PCI device
7863  * @state: The current pci connection state
7864  *
7865  * This function is called after a PCI bus error affecting
7866  * this device has been detected.
7867  */
7868 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7869                                                pci_channel_state_t state)
7870 {
7871         struct net_device *dev = pci_get_drvdata(pdev);
7872         struct bnx2 *bp = netdev_priv(dev);
7873
7874         rtnl_lock();
7875         netif_device_detach(dev);
7876
7877         if (netif_running(dev)) {
7878                 bnx2_netif_stop(bp);
7879                 del_timer_sync(&bp->timer);
7880                 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7881         }
7882
7883         pci_disable_device(pdev);
7884         rtnl_unlock();
7885
7886         /* Request a slot slot reset. */
7887         return PCI_ERS_RESULT_NEED_RESET;
7888 }
7889
7890 /**
7891  * bnx2_io_slot_reset - called after the pci bus has been reset.
7892  * @pdev: Pointer to PCI device
7893  *
7894  * Restart the card from scratch, as if from a cold-boot.
7895  */
7896 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7897 {
7898         struct net_device *dev = pci_get_drvdata(pdev);
7899         struct bnx2 *bp = netdev_priv(dev);
7900
7901         rtnl_lock();
7902         if (pci_enable_device(pdev)) {
7903                 dev_err(&pdev->dev,
7904                         "Cannot re-enable PCI device after reset.\n");
7905                 rtnl_unlock();
7906                 return PCI_ERS_RESULT_DISCONNECT;
7907         }
7908         pci_set_master(pdev);
7909         pci_restore_state(pdev);
7910
7911         if (netif_running(dev)) {
7912                 bnx2_set_power_state(bp, PCI_D0);
7913                 bnx2_init_nic(bp, 1);
7914         }
7915
7916         rtnl_unlock();
7917         return PCI_ERS_RESULT_RECOVERED;
7918 }
7919
7920 /**
7921  * bnx2_io_resume - called when traffic can start flowing again.
7922  * @pdev: Pointer to PCI device
7923  *
7924  * This callback is called when the error recovery driver tells us that
7925  * its OK to resume normal operation.
7926  */
7927 static void bnx2_io_resume(struct pci_dev *pdev)
7928 {
7929         struct net_device *dev = pci_get_drvdata(pdev);
7930         struct bnx2 *bp = netdev_priv(dev);
7931
7932         rtnl_lock();
7933         if (netif_running(dev))
7934                 bnx2_netif_start(bp);
7935
7936         netif_device_attach(dev);
7937         rtnl_unlock();
7938 }
7939
7940 static struct pci_error_handlers bnx2_err_handler = {
7941         .error_detected = bnx2_io_error_detected,
7942         .slot_reset     = bnx2_io_slot_reset,
7943         .resume         = bnx2_io_resume,
7944 };
7945
7946 static struct pci_driver bnx2_pci_driver = {
7947         .name           = DRV_MODULE_NAME,
7948         .id_table       = bnx2_pci_tbl,
7949         .probe          = bnx2_init_one,
7950         .remove         = __devexit_p(bnx2_remove_one),
7951         .suspend        = bnx2_suspend,
7952         .resume         = bnx2_resume,
7953         .err_handler    = &bnx2_err_handler,
7954 };
7955
7956 static int __init bnx2_init(void)
7957 {
7958         return pci_register_driver(&bnx2_pci_driver);
7959 }
7960
7961 static void __exit bnx2_cleanup(void)
7962 {
7963         pci_unregister_driver(&bnx2_pci_driver);
7964 }
7965
7966 module_init(bnx2_init);
7967 module_exit(bnx2_cleanup);
7968
7969
7970