drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2009 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #include <linux/if_vlan.h>
  39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  40 #define BCM_VLAN 1
  41 #endif
  42 #include <net/ip.h>
  43 #include <net/tcp.h>
  44 #include <net/checksum.h>
  45 #include <linux/workqueue.h>
  46 #include <linux/crc32.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/firmware.h>
  50 #include <linux/log2.h>
  51 #include <linux/list.h>
  52
  53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
  54 #define BCM_CNIC 1
  55 #include "cnic_if.h"
  56 #endif
  57 #include "bnx2.h"
  58 #include "bnx2_fw.h"
  59
  60 #define DRV_MODULE_NAME         "bnx2"
  61 #define PFX DRV_MODULE_NAME     ": "
  62 #define DRV_MODULE_VERSION      "2.0.1"
  63 #define DRV_MODULE_RELDATE      "May 6, 2009"
  64 #define FW_MIPS_FILE_06         "bnx2/bnx2-mips-06-4.6.16.fw"
  65 #define FW_RV2P_FILE_06         "bnx2/bnx2-rv2p-06-4.6.16.fw"
  66 #define FW_MIPS_FILE_09         "bnx2/bnx2-mips-09-4.6.17.fw"
  67 #define FW_RV2P_FILE_09         "bnx2/bnx2-rv2p-09-4.6.15.fw"
  68
  69 #define RUN_AT(x) (jiffies + (x))
  70
  71 /* Time in jiffies before concluding the transmitter is hung. */
  72 #define TX_TIMEOUT  (5*HZ)
  73
  74 static char version[] __devinitdata =
  75         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  76
  77 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  78 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
  79 MODULE_LICENSE("GPL");
  80 MODULE_VERSION(DRV_MODULE_VERSION);
  81 MODULE_FIRMWARE(FW_MIPS_FILE_06);
  82 MODULE_FIRMWARE(FW_RV2P_FILE_06);
  83 MODULE_FIRMWARE(FW_MIPS_FILE_09);
  84 MODULE_FIRMWARE(FW_RV2P_FILE_09);
  85
  86 static int disable_msi = 0;
  87
  88 module_param(disable_msi, int, 0);
  89 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  90
  91 typedef enum {
  92         BCM5706 = 0,
  93         NC370T,
  94         NC370I,
  95         BCM5706S,
  96         NC370F,
  97         BCM5708,
  98         BCM5708S,
  99         BCM5709,
 100         BCM5709S,
 101         BCM5716,
 102         BCM5716S,
 103 } board_t;
 104
 105 /* indexed by board_t, above */
 106 static struct {
 107         char *name;
 108 } board_info[] __devinitdata = {
 109         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
 110         { "HP NC370T Multifunction Gigabit Server Adapter" },
 111         { "HP NC370i Multifunction Gigabit Server Adapter" },
 112         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 113         { "HP NC370F Multifunction Gigabit Server Adapter" },
 114         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 115         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 116         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 117         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 118         { "Broadcom NetXtreme II BCM5716 1000Base-T" },
 119         { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
 120         };
 121
 122 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
 123         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 124           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 125         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 126           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 127         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 128           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 129         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 130           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 131         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 132           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 133         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 134           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 135         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 136           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 137         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 138           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 139         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 140           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 141         { PCI_VENDOR_ID_BROADCOM, 0x163b,
 142           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
 143         { PCI_VENDOR_ID_BROADCOM, 0x163c,
 144           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
 145         { 0, }
 146 };
 147
 148 static struct flash_spec flash_table[] =
 149 {
 150 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 151 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 152         /* Slow EEPROM */
 153         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 154          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 155          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 156          "EEPROM - slow"},
 157         /* Expansion entry 0001 */
 158         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 159          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 160          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 161          "Entry 0001"},
 162         /* Saifun SA25F010 (non-buffered flash) */
 163         /* strap, cfg1, & write1 need updates */
 164         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 165          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 166          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 167          "Non-buffered flash (128kB)"},
 168         /* Saifun SA25F020 (non-buffered flash) */
 169         /* strap, cfg1, & write1 need updates */
 170         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 171          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 172          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 173          "Non-buffered flash (256kB)"},
 174         /* Expansion entry 0100 */
 175         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 176          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 177          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 178          "Entry 0100"},
 179         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 180         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 181          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 182          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 183          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 184         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 185         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 186          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 187          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 188          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 189         /* Saifun SA25F005 (non-buffered flash) */
 190         /* strap, cfg1, & write1 need updates */
 191         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 192          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 193          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 194          "Non-buffered flash (64kB)"},
 195         /* Fast EEPROM */
 196         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 197          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 198          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 199          "EEPROM - fast"},
 200         /* Expansion entry 1001 */
 201         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 202          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 203          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 204          "Entry 1001"},
 205         /* Expansion entry 1010 */
 206         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 207          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 208          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 209          "Entry 1010"},
 210         /* ATMEL AT45DB011B (buffered flash) */
 211         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 212          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 213          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 214          "Buffered flash (128kB)"},
 215         /* Expansion entry 1100 */
 216         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 217          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 218          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 219          "Entry 1100"},
 220         /* Expansion entry 1101 */
 221         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 222          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 223          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 224          "Entry 1101"},
 225         /* Ateml Expansion entry 1110 */
 226         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 227          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 228          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 229          "Entry 1110 (Atmel)"},
 230         /* ATMEL AT45DB021B (buffered flash) */
 231         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 232          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 233          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 234          "Buffered flash (256kB)"},
 235 };
 236
 237 static struct flash_spec flash_5709 = {
 238         .flags          = BNX2_NV_BUFFERED,
 239         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 240         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 241         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 242         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 243         .name           = "5709 Buffered flash (256kB)",
 244 };
 245
 246 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 247
 248 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
 249 {
 250         u32 diff;
 251
 252         smp_mb();
 253
 254         /* The ring uses 256 indices for 255 entries, one of them
 255          * needs to be skipped.
 256          */
 257         diff = txr->tx_prod - txr->tx_cons;
 258         if (unlikely(diff >= TX_DESC_CNT)) {
 259                 diff &= 0xffff;
 260                 if (diff == TX_DESC_CNT)
 261                         diff = MAX_TX_DESC_CNT;
 262         }
 263         return (bp->tx_ring_size - diff);
 264 }
 265
 266 static u32
 267 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 268 {
 269         u32 val;
 270
 271         spin_lock_bh(&bp->indirect_lock);
 272         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 273         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 274         spin_unlock_bh(&bp->indirect_lock);
 275         return val;
 276 }
 277
 278 static void
 279 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 280 {
 281         spin_lock_bh(&bp->indirect_lock);
 282         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 283         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 284         spin_unlock_bh(&bp->indirect_lock);
 285 }
 286
 287 static void
 288 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
 289 {
 290         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
 291 }
 292
 293 static u32
 294 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
 295 {
 296         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
 297 }
 298
 299 static void
 300 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 301 {
 302         offset += cid_addr;
 303         spin_lock_bh(&bp->indirect_lock);
 304         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 305                 int i;
 306
 307                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 308                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 309                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 310                 for (i = 0; i < 5; i++) {
 311                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 312                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 313                                 break;
 314                         udelay(5);
 315                 }
 316         } else {
 317                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 318                 REG_WR(bp, BNX2_CTX_DATA, val);
 319         }
 320         spin_unlock_bh(&bp->indirect_lock);
 321 }
 322
 323 #ifdef BCM_CNIC
 324 static int
 325 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
 326 {
 327         struct bnx2 *bp = netdev_priv(dev);
 328         struct drv_ctl_io *io = &info->data.io;
 329
 330         switch (info->cmd) {
 331         case DRV_CTL_IO_WR_CMD:
 332                 bnx2_reg_wr_ind(bp, io->offset, io->data);
 333                 break;
 334         case DRV_CTL_IO_RD_CMD:
 335                 io->data = bnx2_reg_rd_ind(bp, io->offset);
 336                 break;
 337         case DRV_CTL_CTX_WR_CMD:
 338                 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
 339                 break;
 340         default:
 341                 return -EINVAL;
 342         }
 343         return 0;
 344 }
 345
 346 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
 347 {
 348         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
 349         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 350         int sb_id;
 351
 352         if (bp->flags & BNX2_FLAG_USING_MSIX) {
 353                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
 354                 bnapi->cnic_present = 0;
 355                 sb_id = bp->irq_nvecs;
 356                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
 357         } else {
 358                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
 359                 bnapi->cnic_tag = bnapi->last_status_idx;
 360                 bnapi->cnic_present = 1;
 361                 sb_id = 0;
 362                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
 363         }
 364
 365         cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
 366         cp->irq_arr[0].status_blk = (void *)
 367                 ((unsigned long) bnapi->status_blk.msi +
 368                 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
 369         cp->irq_arr[0].status_blk_num = sb_id;
 370         cp->num_irq = 1;
 371 }
 372
 373 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
 374                               void *data)
 375 {
 376         struct bnx2 *bp = netdev_priv(dev);
 377         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
 378
 379         if (ops == NULL)
 380                 return -EINVAL;
 381
 382         if (cp->drv_state & CNIC_DRV_STATE_REGD)
 383                 return -EBUSY;
 384
 385         bp->cnic_data = data;
 386         rcu_assign_pointer(bp->cnic_ops, ops);
 387
 388         cp->num_irq = 0;
 389         cp->drv_state = CNIC_DRV_STATE_REGD;
 390
 391         bnx2_setup_cnic_irq_info(bp);
 392
 393         return 0;
 394 }
 395
 396 static int bnx2_unregister_cnic(struct net_device *dev)
 397 {
 398         struct bnx2 *bp = netdev_priv(dev);
 399         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 400         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
 401
 402         cp->drv_state = 0;
 403         bnapi->cnic_present = 0;
 404         rcu_assign_pointer(bp->cnic_ops, NULL);
 405         synchronize_rcu();
 406         return 0;
 407 }
 408
 409 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
 410 {
 411         struct bnx2 *bp = netdev_priv(dev);
 412         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
 413
 414         cp->drv_owner = THIS_MODULE;
 415         cp->chip_id = bp->chip_id;
 416         cp->pdev = bp->pdev;
 417         cp->io_base = bp->regview;
 418         cp->drv_ctl = bnx2_drv_ctl;
 419         cp->drv_register_cnic = bnx2_register_cnic;
 420         cp->drv_unregister_cnic = bnx2_unregister_cnic;
 421
 422         return cp;
 423 }
 424 EXPORT_SYMBOL(bnx2_cnic_probe);
 425
 426 static void
 427 bnx2_cnic_stop(struct bnx2 *bp)
 428 {
 429         struct cnic_ops *c_ops;
 430         struct cnic_ctl_info info;
 431
 432         rcu_read_lock();
 433         c_ops = rcu_dereference(bp->cnic_ops);
 434         if (c_ops) {
 435                 info.cmd = CNIC_CTL_STOP_CMD;
 436                 c_ops->cnic_ctl(bp->cnic_data, &info);
 437         }
 438         rcu_read_unlock();
 439 }
 440
 441 static void
 442 bnx2_cnic_start(struct bnx2 *bp)
 443 {
 444         struct cnic_ops *c_ops;
 445         struct cnic_ctl_info info;
 446
 447         rcu_read_lock();
 448         c_ops = rcu_dereference(bp->cnic_ops);
 449         if (c_ops) {
 450                 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
 451                         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 452
 453                         bnapi->cnic_tag = bnapi->last_status_idx;
 454                 }
 455                 info.cmd = CNIC_CTL_START_CMD;
 456                 c_ops->cnic_ctl(bp->cnic_data, &info);
 457         }
 458         rcu_read_unlock();
 459 }
 460
 461 #else
 462
 463 static void
 464 bnx2_cnic_stop(struct bnx2 *bp)
 465 {
 466 }
 467
 468 static void
 469 bnx2_cnic_start(struct bnx2 *bp)
 470 {
 471 }
 472
 473 #endif
 474
 475 static int
 476 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 477 {
 478         u32 val1;
 479         int i, ret;
 480
 481         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 482                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 483                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 484
 485                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 486                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 487
 488                 udelay(40);
 489         }
 490
 491         val1 = (bp->phy_addr << 21) | (reg << 16) |
 492                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 493                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 494         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 495
 496         for (i = 0; i < 50; i++) {
 497                 udelay(10);
 498
 499                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 500                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 501                         udelay(5);
 502
 503                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 504                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 505
 506                         break;
 507                 }
 508         }
 509
 510         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 511                 *val = 0x0;
 512                 ret = -EBUSY;
 513         }
 514         else {
 515                 *val = val1;
 516                 ret = 0;
 517         }
 518
 519         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 520                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 521                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 522
 523                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 524                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 525
 526                 udelay(40);
 527         }
 528
 529         return ret;
 530 }
 531
 532 static int
 533 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 534 {
 535         u32 val1;
 536         int i, ret;
 537
 538         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 539                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 540                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 541
 542                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 543                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 544
 545                 udelay(40);
 546         }
 547
 548         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 549                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 550                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 551         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 552
 553         for (i = 0; i < 50; i++) {
 554                 udelay(10);
 555
 556                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 557                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 558                         udelay(5);
 559                         break;
 560                 }
 561         }
 562
 563         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 564                 ret = -EBUSY;
 565         else
 566                 ret = 0;
 567
 568         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 569                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 570                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 571
 572                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 573                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 574
 575                 udelay(40);
 576         }
 577
 578         return ret;
 579 }
 580
 581 static void
 582 bnx2_disable_int(struct bnx2 *bp)
 583 {
 584         int i;
 585         struct bnx2_napi *bnapi;
 586
 587         for (i = 0; i < bp->irq_nvecs; i++) {
 588                 bnapi = &bp->bnx2_napi[i];
 589                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 590                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 591         }
 592         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 593 }
 594
 595 static void
 596 bnx2_enable_int(struct bnx2 *bp)
 597 {
 598         int i;
 599         struct bnx2_napi *bnapi;
 600
 601         for (i = 0; i < bp->irq_nvecs; i++) {
 602                 bnapi = &bp->bnx2_napi[i];
 603
 604                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 605                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 606                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
 607                        bnapi->last_status_idx);
 608
 609                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 610                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 611                        bnapi->last_status_idx);
 612         }
 613         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 614 }
 615
 616 static void
 617 bnx2_disable_int_sync(struct bnx2 *bp)
 618 {
 619         int i;
 620
 621         atomic_inc(&bp->intr_sem);
 622         bnx2_disable_int(bp);
 623         for (i = 0; i < bp->irq_nvecs; i++)
 624                 synchronize_irq(bp->irq_tbl[i].vector);
 625 }
 626
 627 static void
 628 bnx2_napi_disable(struct bnx2 *bp)
 629 {
 630         int i;
 631
 632         for (i = 0; i < bp->irq_nvecs; i++)
 633                 napi_disable(&bp->bnx2_napi[i].napi);
 634 }
 635
 636 static void
 637 bnx2_napi_enable(struct bnx2 *bp)
 638 {
 639         int i;
 640
 641         for (i = 0; i < bp->irq_nvecs; i++)
 642                 napi_enable(&bp->bnx2_napi[i].napi);
 643 }
 644
 645 static void
 646 bnx2_netif_stop(struct bnx2 *bp)
 647 {
 648         bnx2_cnic_stop(bp);
 649         bnx2_disable_int_sync(bp);
 650         if (netif_running(bp->dev)) {
 651                 bnx2_napi_disable(bp);
 652                 netif_tx_disable(bp->dev);
 653                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 654         }
 655 }
 656
 657 static void
 658 bnx2_netif_start(struct bnx2 *bp)
 659 {
 660         if (atomic_dec_and_test(&bp->intr_sem)) {
 661                 if (netif_running(bp->dev)) {
 662                         netif_tx_wake_all_queues(bp->dev);
 663                         bnx2_napi_enable(bp);
 664                         bnx2_enable_int(bp);
 665                         bnx2_cnic_start(bp);
 666                 }
 667         }
 668 }
 669
 670 static void
 671 bnx2_free_tx_mem(struct bnx2 *bp)
 672 {
 673         int i;
 674
 675         for (i = 0; i < bp->num_tx_rings; i++) {
 676                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 677                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 678
 679                 if (txr->tx_desc_ring) {
 680                         pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
 681                                             txr->tx_desc_ring,
 682                                             txr->tx_desc_mapping);
 683                         txr->tx_desc_ring = NULL;
 684                 }
 685                 kfree(txr->tx_buf_ring);
 686                 txr->tx_buf_ring = NULL;
 687         }
 688 }
 689
 690 static void
 691 bnx2_free_rx_mem(struct bnx2 *bp)
 692 {
 693         int i;
 694
 695         for (i = 0; i < bp->num_rx_rings; i++) {
 696                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 697                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 698                 int j;
 699
 700                 for (j = 0; j < bp->rx_max_ring; j++) {
 701                         if (rxr->rx_desc_ring[j])
 702                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 703                                                     rxr->rx_desc_ring[j],
 704                                                     rxr->rx_desc_mapping[j]);
 705                         rxr->rx_desc_ring[j] = NULL;
 706                 }
 707                 vfree(rxr->rx_buf_ring);
 708                 rxr->rx_buf_ring = NULL;
 709
 710                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 711                         if (rxr->rx_pg_desc_ring[j])
 712                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 713                                                     rxr->rx_pg_desc_ring[j],
 714                                                     rxr->rx_pg_desc_mapping[j]);
 715                         rxr->rx_pg_desc_ring[j] = NULL;
 716                 }
 717                 vfree(rxr->rx_pg_ring);
 718                 rxr->rx_pg_ring = NULL;
 719         }
 720 }
 721
 722 static int
 723 bnx2_alloc_tx_mem(struct bnx2 *bp)
 724 {
 725         int i;
 726
 727         for (i = 0; i < bp->num_tx_rings; i++) {
 728                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 729                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 730
 731                 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
 732                 if (txr->tx_buf_ring == NULL)
 733                         return -ENOMEM;
 734
 735                 txr->tx_desc_ring =
 736                         pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
 737                                              &txr->tx_desc_mapping);
 738                 if (txr->tx_desc_ring == NULL)
 739                         return -ENOMEM;
 740         }
 741         return 0;
 742 }
 743
 744 static int
 745 bnx2_alloc_rx_mem(struct bnx2 *bp)
 746 {
 747         int i;
 748
 749         for (i = 0; i < bp->num_rx_rings; i++) {
 750                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 751                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 752                 int j;
 753
 754                 rxr->rx_buf_ring =
 755                         vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
 756                 if (rxr->rx_buf_ring == NULL)
 757                         return -ENOMEM;
 758
 759                 memset(rxr->rx_buf_ring, 0,
 760                        SW_RXBD_RING_SIZE * bp->rx_max_ring);
 761
 762                 for (j = 0; j < bp->rx_max_ring; j++) {
 763                         rxr->rx_desc_ring[j] =
 764                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 765                                                      &rxr->rx_desc_mapping[j]);
 766                         if (rxr->rx_desc_ring[j] == NULL)
 767                                 return -ENOMEM;
 768
 769                 }
 770
 771                 if (bp->rx_pg_ring_size) {
 772                         rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
 773                                                   bp->rx_max_pg_ring);
 774                         if (rxr->rx_pg_ring == NULL)
 775                                 return -ENOMEM;
 776
 777                         memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
 778                                bp->rx_max_pg_ring);
 779                 }
 780
 781                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 782                         rxr->rx_pg_desc_ring[j] =
 783                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 784                                                 &rxr->rx_pg_desc_mapping[j]);
 785                         if (rxr->rx_pg_desc_ring[j] == NULL)
 786                                 return -ENOMEM;
 787
 788                 }
 789         }
 790         return 0;
 791 }
 792
 793 static void
 794 bnx2_free_mem(struct bnx2 *bp)
 795 {
 796         int i;
 797         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 798
 799         bnx2_free_tx_mem(bp);
 800         bnx2_free_rx_mem(bp);
 801
 802         for (i = 0; i < bp->ctx_pages; i++) {
 803                 if (bp->ctx_blk[i]) {
 804                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 805                                             bp->ctx_blk[i],
 806                                             bp->ctx_blk_mapping[i]);
 807                         bp->ctx_blk[i] = NULL;
 808                 }
 809         }
 810         if (bnapi->status_blk.msi) {
 811                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 812                                     bnapi->status_blk.msi,
 813                                     bp->status_blk_mapping);
 814                 bnapi->status_blk.msi = NULL;
 815                 bp->stats_blk = NULL;
 816         }
 817 }
 818
 819 static int
 820 bnx2_alloc_mem(struct bnx2 *bp)
 821 {
 822         int i, status_blk_size, err;
 823         struct bnx2_napi *bnapi;
 824         void *status_blk;
 825
 826         /* Combine status and statistics blocks into one allocation. */
 827         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 828         if (bp->flags & BNX2_FLAG_MSIX_CAP)
 829                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
 830                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
 831         bp->status_stats_size = status_blk_size +
 832                                 sizeof(struct statistics_block);
 833
 834         status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 835                                           &bp->status_blk_mapping);
 836         if (status_blk == NULL)
 837                 goto alloc_mem_err;
 838
 839         memset(status_blk, 0, bp->status_stats_size);
 840
 841         bnapi = &bp->bnx2_napi[0];
 842         bnapi->status_blk.msi = status_blk;
 843         bnapi->hw_tx_cons_ptr =
 844                 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
 845         bnapi->hw_rx_cons_ptr =
 846                 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
 847         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
 848                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
 849                         struct status_block_msix *sblk;
 850
 851                         bnapi = &bp->bnx2_napi[i];
 852
 853                         sblk = (void *) (status_blk +
 854                                          BNX2_SBLK_MSIX_ALIGN_SIZE * i);
 855                         bnapi->status_blk.msix = sblk;
 856                         bnapi->hw_tx_cons_ptr =
 857                                 &sblk->status_tx_quick_consumer_index;
 858                         bnapi->hw_rx_cons_ptr =
 859                                 &sblk->status_rx_quick_consumer_index;
 860                         bnapi->int_num = i << 24;
 861                 }
 862         }
 863
 864         bp->stats_blk = status_blk + status_blk_size;
 865
 866         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 867
 868         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 869                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 870                 if (bp->ctx_pages == 0)
 871                         bp->ctx_pages = 1;
 872                 for (i = 0; i < bp->ctx_pages; i++) {
 873                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 874                                                 BCM_PAGE_SIZE,
 875                                                 &bp->ctx_blk_mapping[i]);
 876                         if (bp->ctx_blk[i] == NULL)
 877                                 goto alloc_mem_err;
 878                 }
 879         }
 880
 881         err = bnx2_alloc_rx_mem(bp);
 882         if (err)
 883                 goto alloc_mem_err;
 884
 885         err = bnx2_alloc_tx_mem(bp);
 886         if (err)
 887                 goto alloc_mem_err;
 888
 889         return 0;
 890
 891 alloc_mem_err:
 892         bnx2_free_mem(bp);
 893         return -ENOMEM;
 894 }
 895
 896 static void
 897 bnx2_report_fw_link(struct bnx2 *bp)
 898 {
 899         u32 fw_link_status = 0;
 900
 901         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
 902                 return;
 903
 904         if (bp->link_up) {
 905                 u32 bmsr;
 906
 907                 switch (bp->line_speed) {
 908                 case SPEED_10:
 909                         if (bp->duplex == DUPLEX_HALF)
 910                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 911                         else
 912                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 913                         break;
 914                 case SPEED_100:
 915                         if (bp->duplex == DUPLEX_HALF)
 916                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 917                         else
 918                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 919                         break;
 920                 case SPEED_1000:
 921                         if (bp->duplex == DUPLEX_HALF)
 922                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 923                         else
 924                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 925                         break;
 926                 case SPEED_2500:
 927                         if (bp->duplex == DUPLEX_HALF)
 928                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 929                         else
 930                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 931                         break;
 932                 }
 933
 934                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 935
 936                 if (bp->autoneg) {
 937                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 938
 939                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 940                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 941
 942                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 943                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
 944                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 945                         else
 946                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 947                 }
 948         }
 949         else
 950                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 951
 952         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 953 }
 954
 955 static char *
 956 bnx2_xceiver_str(struct bnx2 *bp)
 957 {
 958         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 959                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
 960                  "Copper"));
 961 }
 962
 963 static void
 964 bnx2_report_link(struct bnx2 *bp)
 965 {
 966         if (bp->link_up) {
 967                 netif_carrier_on(bp->dev);
 968                 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
 969                        bnx2_xceiver_str(bp));
 970
 971                 printk("%d Mbps ", bp->line_speed);
 972
 973                 if (bp->duplex == DUPLEX_FULL)
 974                         printk("full duplex");
 975                 else
 976                         printk("half duplex");
 977
 978                 if (bp->flow_ctrl) {
 979                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 980                                 printk(", receive ");
 981                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 982                                         printk("& transmit ");
 983                         }
 984                         else {
 985                                 printk(", transmit ");
 986                         }
 987                         printk("flow control ON");
 988                 }
 989                 printk("\n");
 990         }
 991         else {
 992                 netif_carrier_off(bp->dev);
 993                 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
 994                        bnx2_xceiver_str(bp));
 995         }
 996
 997         bnx2_report_fw_link(bp);
 998 }
 999
1000 static void
1001 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1002 {
1003         u32 local_adv, remote_adv;
1004
1005         bp->flow_ctrl = 0;
1006         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1007                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1008
1009                 if (bp->duplex == DUPLEX_FULL) {
1010                         bp->flow_ctrl = bp->req_flow_ctrl;
1011                 }
1012                 return;
1013         }
1014
1015         if (bp->duplex != DUPLEX_FULL) {
1016                 return;
1017         }
1018
1019         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1020             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1021                 u32 val;
1022
1023                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1024                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1025                         bp->flow_ctrl |= FLOW_CTRL_TX;
1026                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1027                         bp->flow_ctrl |= FLOW_CTRL_RX;
1028                 return;
1029         }
1030
1031         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1032         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1033
1034         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1035                 u32 new_local_adv = 0;
1036                 u32 new_remote_adv = 0;
1037
1038                 if (local_adv & ADVERTISE_1000XPAUSE)
1039                         new_local_adv |= ADVERTISE_PAUSE_CAP;
1040                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1041                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
1042                 if (remote_adv & ADVERTISE_1000XPAUSE)
1043                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
1044                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1045                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1046
1047                 local_adv = new_local_adv;
1048                 remote_adv = new_remote_adv;
1049         }
1050
1051         /* See Table 28B-3 of 802.3ab-1999 spec. */
1052         if (local_adv & ADVERTISE_PAUSE_CAP) {
1053                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1054                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
1055                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1056                         }
1057                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1058                                 bp->flow_ctrl = FLOW_CTRL_RX;
1059                         }
1060                 }
1061                 else {
1062                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
1063                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1064                         }
1065                 }
1066         }
1067         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1068                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1069                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1070
1071                         bp->flow_ctrl = FLOW_CTRL_TX;
1072                 }
1073         }
1074 }
1075
1076 static int
1077 bnx2_5709s_linkup(struct bnx2 *bp)
1078 {
1079         u32 val, speed;
1080
1081         bp->link_up = 1;
1082
1083         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1084         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1085         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1086
1087         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1088                 bp->line_speed = bp->req_line_speed;
1089                 bp->duplex = bp->req_duplex;
1090                 return 0;
1091         }
1092         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1093         switch (speed) {
1094                 case MII_BNX2_GP_TOP_AN_SPEED_10:
1095                         bp->line_speed = SPEED_10;
1096                         break;
1097                 case MII_BNX2_GP_TOP_AN_SPEED_100:
1098                         bp->line_speed = SPEED_100;
1099                         break;
1100                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1101                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1102                         bp->line_speed = SPEED_1000;
1103                         break;
1104                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1105                         bp->line_speed = SPEED_2500;
1106                         break;
1107         }
1108         if (val & MII_BNX2_GP_TOP_AN_FD)
1109                 bp->duplex = DUPLEX_FULL;
1110         else
1111                 bp->duplex = DUPLEX_HALF;
1112         return 0;
1113 }
1114
1115 static int
1116 bnx2_5708s_linkup(struct bnx2 *bp)
1117 {
1118         u32 val;
1119
1120         bp->link_up = 1;
1121         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1122         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1123                 case BCM5708S_1000X_STAT1_SPEED_10:
1124                         bp->line_speed = SPEED_10;
1125                         break;
1126                 case BCM5708S_1000X_STAT1_SPEED_100:
1127                         bp->line_speed = SPEED_100;
1128                         break;
1129                 case BCM5708S_1000X_STAT1_SPEED_1G:
1130                         bp->line_speed = SPEED_1000;
1131                         break;
1132                 case BCM5708S_1000X_STAT1_SPEED_2G5:
1133                         bp->line_speed = SPEED_2500;
1134                         break;
1135         }
1136         if (val & BCM5708S_1000X_STAT1_FD)
1137                 bp->duplex = DUPLEX_FULL;
1138         else
1139                 bp->duplex = DUPLEX_HALF;
1140
1141         return 0;
1142 }
1143
1144 static int
1145 bnx2_5706s_linkup(struct bnx2 *bp)
1146 {
1147         u32 bmcr, local_adv, remote_adv, common;
1148
1149         bp->link_up = 1;
1150         bp->line_speed = SPEED_1000;
1151
1152         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1153         if (bmcr & BMCR_FULLDPLX) {
1154                 bp->duplex = DUPLEX_FULL;
1155         }
1156         else {
1157                 bp->duplex = DUPLEX_HALF;
1158         }
1159
1160         if (!(bmcr & BMCR_ANENABLE)) {
1161                 return 0;
1162         }
1163
1164         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1165         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1166
1167         common = local_adv & remote_adv;
1168         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1169
1170                 if (common & ADVERTISE_1000XFULL) {
1171                         bp->duplex = DUPLEX_FULL;
1172                 }
1173                 else {
1174                         bp->duplex = DUPLEX_HALF;
1175                 }
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int
1182 bnx2_copper_linkup(struct bnx2 *bp)
1183 {
1184         u32 bmcr;
1185
1186         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1187         if (bmcr & BMCR_ANENABLE) {
1188                 u32 local_adv, remote_adv, common;
1189
1190                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1191                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1192
1193                 common = local_adv & (remote_adv >> 2);
1194                 if (common & ADVERTISE_1000FULL) {
1195                         bp->line_speed = SPEED_1000;
1196                         bp->duplex = DUPLEX_FULL;
1197                 }
1198                 else if (common & ADVERTISE_1000HALF) {
1199                         bp->line_speed = SPEED_1000;
1200                         bp->duplex = DUPLEX_HALF;
1201                 }
1202                 else {
1203                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1204                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1205
1206                         common = local_adv & remote_adv;
1207                         if (common & ADVERTISE_100FULL) {
1208                                 bp->line_speed = SPEED_100;
1209                                 bp->duplex = DUPLEX_FULL;
1210                         }
1211                         else if (common & ADVERTISE_100HALF) {
1212                                 bp->line_speed = SPEED_100;
1213                                 bp->duplex = DUPLEX_HALF;
1214                         }
1215                         else if (common & ADVERTISE_10FULL) {
1216                                 bp->line_speed = SPEED_10;
1217                                 bp->duplex = DUPLEX_FULL;
1218                         }
1219                         else if (common & ADVERTISE_10HALF) {
1220                                 bp->line_speed = SPEED_10;
1221                                 bp->duplex = DUPLEX_HALF;
1222                         }
1223                         else {
1224                                 bp->line_speed = 0;
1225                                 bp->link_up = 0;
1226                         }
1227                 }
1228         }
1229         else {
1230                 if (bmcr & BMCR_SPEED100) {
1231                         bp->line_speed = SPEED_100;
1232                 }
1233                 else {
1234                         bp->line_speed = SPEED_10;
1235                 }
1236                 if (bmcr & BMCR_FULLDPLX) {
1237                         bp->duplex = DUPLEX_FULL;
1238                 }
1239                 else {
1240                         bp->duplex = DUPLEX_HALF;
1241                 }
1242         }
1243
1244         return 0;
1245 }
1246
1247 static void
1248 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1249 {
1250         u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1251
1252         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1253         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1254         val |= 0x02 << 8;
1255
1256         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1257                 u32 lo_water, hi_water;
1258
1259                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1260                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1261                 else
1262                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1263                 if (lo_water >= bp->rx_ring_size)
1264                         lo_water = 0;
1265
1266                 hi_water = bp->rx_ring_size / 4;
1267
1268                 if (hi_water <= lo_water)
1269                         lo_water = 0;
1270
1271                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1272                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1273
1274                 if (hi_water > 0xf)
1275                         hi_water = 0xf;
1276                 else if (hi_water == 0)
1277                         lo_water = 0;
1278                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1279         }
1280         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1281 }
1282
1283 static void
1284 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1285 {
1286         int i;
1287         u32 cid;
1288
1289         for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1290                 if (i == 1)
1291                         cid = RX_RSS_CID;
1292                 bnx2_init_rx_context(bp, cid);
1293         }
1294 }
1295
1296 static void
1297 bnx2_set_mac_link(struct bnx2 *bp)
1298 {
1299         u32 val;
1300
1301         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1302         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1303                 (bp->duplex == DUPLEX_HALF)) {
1304                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1305         }
1306
1307         /* Configure the EMAC mode register. */
1308         val = REG_RD(bp, BNX2_EMAC_MODE);
1309
1310         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1311                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1312                 BNX2_EMAC_MODE_25G_MODE);
1313
1314         if (bp->link_up) {
1315                 switch (bp->line_speed) {
1316                         case SPEED_10:
1317                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1318                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1319                                         break;
1320                                 }
1321                                 /* fall through */
1322                         case SPEED_100:
1323                                 val |= BNX2_EMAC_MODE_PORT_MII;
1324                                 break;
1325                         case SPEED_2500:
1326                                 val |= BNX2_EMAC_MODE_25G_MODE;
1327                                 /* fall through */
1328                         case SPEED_1000:
1329                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1330                                 break;
1331                 }
1332         }
1333         else {
1334                 val |= BNX2_EMAC_MODE_PORT_GMII;
1335         }
1336
1337         /* Set the MAC to operate in the appropriate duplex mode. */
1338         if (bp->duplex == DUPLEX_HALF)
1339                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1340         REG_WR(bp, BNX2_EMAC_MODE, val);
1341
1342         /* Enable/disable rx PAUSE. */
1343         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1344
1345         if (bp->flow_ctrl & FLOW_CTRL_RX)
1346                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1347         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1348
1349         /* Enable/disable tx PAUSE. */
1350         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1351         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1352
1353         if (bp->flow_ctrl & FLOW_CTRL_TX)
1354                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1355         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1356
1357         /* Acknowledge the interrupt. */
1358         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1359
1360         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1361                 bnx2_init_all_rx_contexts(bp);
1362 }
1363
1364 static void
1365 bnx2_enable_bmsr1(struct bnx2 *bp)
1366 {
1367         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1368             (CHIP_NUM(bp) == CHIP_NUM_5709))
1369                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1370                                MII_BNX2_BLK_ADDR_GP_STATUS);
1371 }
1372
1373 static void
1374 bnx2_disable_bmsr1(struct bnx2 *bp)
1375 {
1376         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1377             (CHIP_NUM(bp) == CHIP_NUM_5709))
1378                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1379                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1380 }
1381
1382 static int
1383 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1384 {
1385         u32 up1;
1386         int ret = 1;
1387
1388         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1389                 return 0;
1390
1391         if (bp->autoneg & AUTONEG_SPEED)
1392                 bp->advertising |= ADVERTISED_2500baseX_Full;
1393
1394         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1395                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1396
1397         bnx2_read_phy(bp, bp->mii_up1, &up1);
1398         if (!(up1 & BCM5708S_UP1_2G5)) {
1399                 up1 |= BCM5708S_UP1_2G5;
1400                 bnx2_write_phy(bp, bp->mii_up1, up1);
1401                 ret = 0;
1402         }
1403
1404         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1405                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1406                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1407
1408         return ret;
1409 }
1410
1411 static int
1412 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1413 {
1414         u32 up1;
1415         int ret = 0;
1416
1417         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1418                 return 0;
1419
1420         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1421                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1422
1423         bnx2_read_phy(bp, bp->mii_up1, &up1);
1424         if (up1 & BCM5708S_UP1_2G5) {
1425                 up1 &= ~BCM5708S_UP1_2G5;
1426                 bnx2_write_phy(bp, bp->mii_up1, up1);
1427                 ret = 1;
1428         }
1429
1430         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1431                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1432                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1433
1434         return ret;
1435 }
1436
1437 static void
1438 bnx2_enable_forced_2g5(struct bnx2 *bp)
1439 {
1440         u32 bmcr;
1441
1442         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1443                 return;
1444
1445         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1446                 u32 val;
1447
1448                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1449                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1450                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1451                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1452                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1453                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1454
1455                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1456                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1457                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1458
1459         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1460                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1461                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1462         }
1463
1464         if (bp->autoneg & AUTONEG_SPEED) {
1465                 bmcr &= ~BMCR_ANENABLE;
1466                 if (bp->req_duplex == DUPLEX_FULL)
1467                         bmcr |= BMCR_FULLDPLX;
1468         }
1469         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1470 }
1471
1472 static void
1473 bnx2_disable_forced_2g5(struct bnx2 *bp)
1474 {
1475         u32 bmcr;
1476
1477         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1478                 return;
1479
1480         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1481                 u32 val;
1482
1483                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1484                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1485                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1486                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1487                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1488
1489                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1490                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1491                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1492
1493         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1494                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1495                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1496         }
1497
1498         if (bp->autoneg & AUTONEG_SPEED)
1499                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1500         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1501 }
1502
1503 static void
1504 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1505 {
1506         u32 val;
1507
1508         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1509         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1510         if (start)
1511                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1512         else
1513                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1514 }
1515
1516 static int
1517 bnx2_set_link(struct bnx2 *bp)
1518 {
1519         u32 bmsr;
1520         u8 link_up;
1521
1522         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1523                 bp->link_up = 1;
1524                 return 0;
1525         }
1526
1527         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1528                 return 0;
1529
1530         link_up = bp->link_up;
1531
1532         bnx2_enable_bmsr1(bp);
1533         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1534         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1535         bnx2_disable_bmsr1(bp);
1536
1537         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1538             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1539                 u32 val, an_dbg;
1540
1541                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1542                         bnx2_5706s_force_link_dn(bp, 0);
1543                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1544                 }
1545                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1546
1547                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1548                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1549                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1550
1551                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1552                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1553                         bmsr |= BMSR_LSTATUS;
1554                 else
1555                         bmsr &= ~BMSR_LSTATUS;
1556         }
1557
1558         if (bmsr & BMSR_LSTATUS) {
1559                 bp->link_up = 1;
1560
1561                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1562                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1563                                 bnx2_5706s_linkup(bp);
1564                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1565                                 bnx2_5708s_linkup(bp);
1566                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1567                                 bnx2_5709s_linkup(bp);
1568                 }
1569                 else {
1570                         bnx2_copper_linkup(bp);
1571                 }
1572                 bnx2_resolve_flow_ctrl(bp);
1573         }
1574         else {
1575                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1576                     (bp->autoneg & AUTONEG_SPEED))
1577                         bnx2_disable_forced_2g5(bp);
1578
1579                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1580                         u32 bmcr;
1581
1582                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1583                         bmcr |= BMCR_ANENABLE;
1584                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1585
1586                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1587                 }
1588                 bp->link_up = 0;
1589         }
1590
1591         if (bp->link_up != link_up) {
1592                 bnx2_report_link(bp);
1593         }
1594
1595         bnx2_set_mac_link(bp);
1596
1597         return 0;
1598 }
1599
1600 static int
1601 bnx2_reset_phy(struct bnx2 *bp)
1602 {
1603         int i;
1604         u32 reg;
1605
1606         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1607
1608 #define PHY_RESET_MAX_WAIT 100
1609         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1610                 udelay(10);
1611
1612                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1613                 if (!(reg & BMCR_RESET)) {
1614                         udelay(20);
1615                         break;
1616                 }
1617         }
1618         if (i == PHY_RESET_MAX_WAIT) {
1619                 return -EBUSY;
1620         }
1621         return 0;
1622 }
1623
1624 static u32
1625 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1626 {
1627         u32 adv = 0;
1628
1629         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1630                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1631
1632                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1633                         adv = ADVERTISE_1000XPAUSE;
1634                 }
1635                 else {
1636                         adv = ADVERTISE_PAUSE_CAP;
1637                 }
1638         }
1639         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1640                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1641                         adv = ADVERTISE_1000XPSE_ASYM;
1642                 }
1643                 else {
1644                         adv = ADVERTISE_PAUSE_ASYM;
1645                 }
1646         }
1647         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1648                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1649                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1650                 }
1651                 else {
1652                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1653                 }
1654         }
1655         return adv;
1656 }
1657
1658 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1659
1660 static int
1661 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1662 __releases(&bp->phy_lock)
1663 __acquires(&bp->phy_lock)
1664 {
1665         u32 speed_arg = 0, pause_adv;
1666
1667         pause_adv = bnx2_phy_get_pause_adv(bp);
1668
1669         if (bp->autoneg & AUTONEG_SPEED) {
1670                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1671                 if (bp->advertising & ADVERTISED_10baseT_Half)
1672                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1673                 if (bp->advertising & ADVERTISED_10baseT_Full)
1674                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1675                 if (bp->advertising & ADVERTISED_100baseT_Half)
1676                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1677                 if (bp->advertising & ADVERTISED_100baseT_Full)
1678                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1679                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1680                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1681                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1682                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1683         } else {
1684                 if (bp->req_line_speed == SPEED_2500)
1685                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1686                 else if (bp->req_line_speed == SPEED_1000)
1687                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1688                 else if (bp->req_line_speed == SPEED_100) {
1689                         if (bp->req_duplex == DUPLEX_FULL)
1690                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1691                         else
1692                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1693                 } else if (bp->req_line_speed == SPEED_10) {
1694                         if (bp->req_duplex == DUPLEX_FULL)
1695                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1696                         else
1697                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1698                 }
1699         }
1700
1701         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1702                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1703         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1704                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1705
1706         if (port == PORT_TP)
1707                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1708                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1709
1710         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1711
1712         spin_unlock_bh(&bp->phy_lock);
1713         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1714         spin_lock_bh(&bp->phy_lock);
1715
1716         return 0;
1717 }
1718
1719 static int
1720 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1721 __releases(&bp->phy_lock)
1722 __acquires(&bp->phy_lock)
1723 {
1724         u32 adv, bmcr;
1725         u32 new_adv = 0;
1726
1727         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1728                 return (bnx2_setup_remote_phy(bp, port));
1729
1730         if (!(bp->autoneg & AUTONEG_SPEED)) {
1731                 u32 new_bmcr;
1732                 int force_link_down = 0;
1733
1734                 if (bp->req_line_speed == SPEED_2500) {
1735                         if (!bnx2_test_and_enable_2g5(bp))
1736                                 force_link_down = 1;
1737                 } else if (bp->req_line_speed == SPEED_1000) {
1738                         if (bnx2_test_and_disable_2g5(bp))
1739                                 force_link_down = 1;
1740                 }
1741                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1742                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1743
1744                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1745                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1746                 new_bmcr |= BMCR_SPEED1000;
1747
1748                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1749                         if (bp->req_line_speed == SPEED_2500)
1750                                 bnx2_enable_forced_2g5(bp);
1751                         else if (bp->req_line_speed == SPEED_1000) {
1752                                 bnx2_disable_forced_2g5(bp);
1753                                 new_bmcr &= ~0x2000;
1754                         }
1755
1756                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1757                         if (bp->req_line_speed == SPEED_2500)
1758                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1759                         else
1760                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1761                 }
1762
1763                 if (bp->req_duplex == DUPLEX_FULL) {
1764                         adv |= ADVERTISE_1000XFULL;
1765                         new_bmcr |= BMCR_FULLDPLX;
1766                 }
1767                 else {
1768                         adv |= ADVERTISE_1000XHALF;
1769                         new_bmcr &= ~BMCR_FULLDPLX;
1770                 }
1771                 if ((new_bmcr != bmcr) || (force_link_down)) {
1772                         /* Force a link down visible on the other side */
1773                         if (bp->link_up) {
1774                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1775                                                ~(ADVERTISE_1000XFULL |
1776                                                  ADVERTISE_1000XHALF));
1777                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1778                                         BMCR_ANRESTART | BMCR_ANENABLE);
1779
1780                                 bp->link_up = 0;
1781                                 netif_carrier_off(bp->dev);
1782                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1783                                 bnx2_report_link(bp);
1784                         }
1785                         bnx2_write_phy(bp, bp->mii_adv, adv);
1786                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1787                 } else {
1788                         bnx2_resolve_flow_ctrl(bp);
1789                         bnx2_set_mac_link(bp);
1790                 }
1791                 return 0;
1792         }
1793
1794         bnx2_test_and_enable_2g5(bp);
1795
1796         if (bp->advertising & ADVERTISED_1000baseT_Full)
1797                 new_adv |= ADVERTISE_1000XFULL;
1798
1799         new_adv |= bnx2_phy_get_pause_adv(bp);
1800
1801         bnx2_read_phy(bp, bp->mii_adv, &adv);
1802         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1803
1804         bp->serdes_an_pending = 0;
1805         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1806                 /* Force a link down visible on the other side */
1807                 if (bp->link_up) {
1808                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1809                         spin_unlock_bh(&bp->phy_lock);
1810                         msleep(20);
1811                         spin_lock_bh(&bp->phy_lock);
1812                 }
1813
1814                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1815                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1816                         BMCR_ANENABLE);
1817                 /* Speed up link-up time when the link partner
1818                  * does not autonegotiate which is very common
1819                  * in blade servers. Some blade servers use
1820                  * IPMI for kerboard input and it's important
1821                  * to minimize link disruptions. Autoneg. involves
1822                  * exchanging base pages plus 3 next pages and
1823                  * normally completes in about 120 msec.
1824                  */
1825                 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1826                 bp->serdes_an_pending = 1;
1827                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1828         } else {
1829                 bnx2_resolve_flow_ctrl(bp);
1830                 bnx2_set_mac_link(bp);
1831         }
1832
1833         return 0;
1834 }
1835
1836 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1837         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1838                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1839                 (ADVERTISED_1000baseT_Full)
1840
1841 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1842         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1843         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1844         ADVERTISED_1000baseT_Full)
1845
1846 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1847         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1848
1849 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1850
1851 static void
1852 bnx2_set_default_remote_link(struct bnx2 *bp)
1853 {
1854         u32 link;
1855
1856         if (bp->phy_port == PORT_TP)
1857                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1858         else
1859                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1860
1861         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1862                 bp->req_line_speed = 0;
1863                 bp->autoneg |= AUTONEG_SPEED;
1864                 bp->advertising = ADVERTISED_Autoneg;
1865                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1866                         bp->advertising |= ADVERTISED_10baseT_Half;
1867                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1868                         bp->advertising |= ADVERTISED_10baseT_Full;
1869                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1870                         bp->advertising |= ADVERTISED_100baseT_Half;
1871                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1872                         bp->advertising |= ADVERTISED_100baseT_Full;
1873                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1874                         bp->advertising |= ADVERTISED_1000baseT_Full;
1875                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1876                         bp->advertising |= ADVERTISED_2500baseX_Full;
1877         } else {
1878                 bp->autoneg = 0;
1879                 bp->advertising = 0;
1880                 bp->req_duplex = DUPLEX_FULL;
1881                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1882                         bp->req_line_speed = SPEED_10;
1883                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1884                                 bp->req_duplex = DUPLEX_HALF;
1885                 }
1886                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1887                         bp->req_line_speed = SPEED_100;
1888                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1889                                 bp->req_duplex = DUPLEX_HALF;
1890                 }
1891                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1892                         bp->req_line_speed = SPEED_1000;
1893                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1894                         bp->req_line_speed = SPEED_2500;
1895         }
1896 }
1897
1898 static void
1899 bnx2_set_default_link(struct bnx2 *bp)
1900 {
1901         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1902                 bnx2_set_default_remote_link(bp);
1903                 return;
1904         }
1905
1906         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1907         bp->req_line_speed = 0;
1908         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1909                 u32 reg;
1910
1911                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1912
1913                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1914                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1915                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1916                         bp->autoneg = 0;
1917                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1918                         bp->req_duplex = DUPLEX_FULL;
1919                 }
1920         } else
1921                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1922 }
1923
1924 static void
1925 bnx2_send_heart_beat(struct bnx2 *bp)
1926 {
1927         u32 msg;
1928         u32 addr;
1929
1930         spin_lock(&bp->indirect_lock);
1931         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1932         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1933         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1934         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1935         spin_unlock(&bp->indirect_lock);
1936 }
1937
1938 static void
1939 bnx2_remote_phy_event(struct bnx2 *bp)
1940 {
1941         u32 msg;
1942         u8 link_up = bp->link_up;
1943         u8 old_port;
1944
1945         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1946
1947         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1948                 bnx2_send_heart_beat(bp);
1949
1950         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1951
1952         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1953                 bp->link_up = 0;
1954         else {
1955                 u32 speed;
1956
1957                 bp->link_up = 1;
1958                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1959                 bp->duplex = DUPLEX_FULL;
1960                 switch (speed) {
1961                         case BNX2_LINK_STATUS_10HALF:
1962                                 bp->duplex = DUPLEX_HALF;
1963                         case BNX2_LINK_STATUS_10FULL:
1964                                 bp->line_speed = SPEED_10;
1965                                 break;
1966                         case BNX2_LINK_STATUS_100HALF:
1967                                 bp->duplex = DUPLEX_HALF;
1968                         case BNX2_LINK_STATUS_100BASE_T4:
1969                         case BNX2_LINK_STATUS_100FULL:
1970                                 bp->line_speed = SPEED_100;
1971                                 break;
1972                         case BNX2_LINK_STATUS_1000HALF:
1973                                 bp->duplex = DUPLEX_HALF;
1974                         case BNX2_LINK_STATUS_1000FULL:
1975                                 bp->line_speed = SPEED_1000;
1976                                 break;
1977                         case BNX2_LINK_STATUS_2500HALF:
1978                                 bp->duplex = DUPLEX_HALF;
1979                         case BNX2_LINK_STATUS_2500FULL:
1980                                 bp->line_speed = SPEED_2500;
1981                                 break;
1982                         default:
1983                                 bp->line_speed = 0;
1984                                 break;
1985                 }
1986
1987                 bp->flow_ctrl = 0;
1988                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1989                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1990                         if (bp->duplex == DUPLEX_FULL)
1991                                 bp->flow_ctrl = bp->req_flow_ctrl;
1992                 } else {
1993                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1994                                 bp->flow_ctrl |= FLOW_CTRL_TX;
1995                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1996                                 bp->flow_ctrl |= FLOW_CTRL_RX;
1997                 }
1998
1999                 old_port = bp->phy_port;
2000                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2001                         bp->phy_port = PORT_FIBRE;
2002                 else
2003                         bp->phy_port = PORT_TP;
2004
2005                 if (old_port != bp->phy_port)
2006                         bnx2_set_default_link(bp);
2007
2008         }
2009         if (bp->link_up != link_up)
2010                 bnx2_report_link(bp);
2011
2012         bnx2_set_mac_link(bp);
2013 }
2014
2015 static int
2016 bnx2_set_remote_link(struct bnx2 *bp)
2017 {
2018         u32 evt_code;
2019
2020         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2021         switch (evt_code) {
2022                 case BNX2_FW_EVT_CODE_LINK_EVENT:
2023                         bnx2_remote_phy_event(bp);
2024                         break;
2025                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2026                 default:
2027                         bnx2_send_heart_beat(bp);
2028                         break;
2029         }
2030         return 0;
2031 }
2032
2033 static int
2034 bnx2_setup_copper_phy(struct bnx2 *bp)
2035 __releases(&bp->phy_lock)
2036 __acquires(&bp->phy_lock)
2037 {
2038         u32 bmcr;
2039         u32 new_bmcr;
2040
2041         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2042
2043         if (bp->autoneg & AUTONEG_SPEED) {
2044                 u32 adv_reg, adv1000_reg;
2045                 u32 new_adv_reg = 0;
2046                 u32 new_adv1000_reg = 0;
2047
2048                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2049                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2050                         ADVERTISE_PAUSE_ASYM);
2051
2052                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2053                 adv1000_reg &= PHY_ALL_1000_SPEED;
2054
2055                 if (bp->advertising & ADVERTISED_10baseT_Half)
2056                         new_adv_reg |= ADVERTISE_10HALF;
2057                 if (bp->advertising & ADVERTISED_10baseT_Full)
2058                         new_adv_reg |= ADVERTISE_10FULL;
2059                 if (bp->advertising & ADVERTISED_100baseT_Half)
2060                         new_adv_reg |= ADVERTISE_100HALF;
2061                 if (bp->advertising & ADVERTISED_100baseT_Full)
2062                         new_adv_reg |= ADVERTISE_100FULL;
2063                 if (bp->advertising & ADVERTISED_1000baseT_Full)
2064                         new_adv1000_reg |= ADVERTISE_1000FULL;
2065
2066                 new_adv_reg |= ADVERTISE_CSMA;
2067
2068                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2069
2070                 if ((adv1000_reg != new_adv1000_reg) ||
2071                         (adv_reg != new_adv_reg) ||
2072                         ((bmcr & BMCR_ANENABLE) == 0)) {
2073
2074                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2075                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2076                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2077                                 BMCR_ANENABLE);
2078                 }
2079                 else if (bp->link_up) {
2080                         /* Flow ctrl may have changed from auto to forced */
2081                         /* or vice-versa. */
2082
2083                         bnx2_resolve_flow_ctrl(bp);
2084                         bnx2_set_mac_link(bp);
2085                 }
2086                 return 0;
2087         }
2088
2089         new_bmcr = 0;
2090         if (bp->req_line_speed == SPEED_100) {
2091                 new_bmcr |= BMCR_SPEED100;
2092         }
2093         if (bp->req_duplex == DUPLEX_FULL) {
2094                 new_bmcr |= BMCR_FULLDPLX;
2095         }
2096         if (new_bmcr != bmcr) {
2097                 u32 bmsr;
2098
2099                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2100                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2101
2102                 if (bmsr & BMSR_LSTATUS) {
2103                         /* Force link down */
2104                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2105                         spin_unlock_bh(&bp->phy_lock);
2106                         msleep(50);
2107                         spin_lock_bh(&bp->phy_lock);
2108
2109                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2110                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2111                 }
2112
2113                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2114
2115                 /* Normally, the new speed is setup after the link has
2116                  * gone down and up again. In some cases, link will not go
2117                  * down so we need to set up the new speed here.
2118                  */
2119                 if (bmsr & BMSR_LSTATUS) {
2120                         bp->line_speed = bp->req_line_speed;
2121                         bp->duplex = bp->req_duplex;
2122                         bnx2_resolve_flow_ctrl(bp);
2123                         bnx2_set_mac_link(bp);
2124                 }
2125         } else {
2126                 bnx2_resolve_flow_ctrl(bp);
2127                 bnx2_set_mac_link(bp);
2128         }
2129         return 0;
2130 }
2131
2132 static int
2133 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2134 __releases(&bp->phy_lock)
2135 __acquires(&bp->phy_lock)
2136 {
2137         if (bp->loopback == MAC_LOOPBACK)
2138                 return 0;
2139
2140         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2141                 return (bnx2_setup_serdes_phy(bp, port));
2142         }
2143         else {
2144                 return (bnx2_setup_copper_phy(bp));
2145         }
2146 }
2147
2148 static int
2149 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2150 {
2151         u32 val;
2152
2153         bp->mii_bmcr = MII_BMCR + 0x10;
2154         bp->mii_bmsr = MII_BMSR + 0x10;
2155         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2156         bp->mii_adv = MII_ADVERTISE + 0x10;
2157         bp->mii_lpa = MII_LPA + 0x10;
2158         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2159
2160         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2161         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2162
2163         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2164         if (reset_phy)
2165                 bnx2_reset_phy(bp);
2166
2167         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2168
2169         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2170         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2171         val |= MII_BNX2_SD_1000XCTL1_FIBER;
2172         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2173
2174         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2175         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2176         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2177                 val |= BCM5708S_UP1_2G5;
2178         else
2179                 val &= ~BCM5708S_UP1_2G5;
2180         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2181
2182         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2183         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2184         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2185         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2186
2187         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2188
2189         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2190               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2191         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2192
2193         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2194
2195         return 0;
2196 }
2197
2198 static int
2199 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2200 {
2201         u32 val;
2202
2203         if (reset_phy)
2204                 bnx2_reset_phy(bp);
2205
2206         bp->mii_up1 = BCM5708S_UP1;
2207
2208         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2209         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2210         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2211
2212         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2213         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2214         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2215
2216         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2217         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2218         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2219
2220         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2221                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2222                 val |= BCM5708S_UP1_2G5;
2223                 bnx2_write_phy(bp, BCM5708S_UP1, val);
2224         }
2225
2226         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2227             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2228             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2229                 /* increase tx signal amplitude */
2230                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2231                                BCM5708S_BLK_ADDR_TX_MISC);
2232                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2233                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2234                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2235                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2236         }
2237
2238         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2239               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2240
2241         if (val) {
2242                 u32 is_backplane;
2243
2244                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2245                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2246                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2247                                        BCM5708S_BLK_ADDR_TX_MISC);
2248                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2249                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2250                                        BCM5708S_BLK_ADDR_DIG);
2251                 }
2252         }
2253         return 0;
2254 }
2255
2256 static int
2257 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2258 {
2259         if (reset_phy)
2260                 bnx2_reset_phy(bp);
2261
2262         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2263
2264         if (CHIP_NUM(bp) == CHIP_NUM_5706)
2265                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2266
2267         if (bp->dev->mtu > 1500) {
2268                 u32 val;
2269
2270                 /* Set extended packet length bit */
2271                 bnx2_write_phy(bp, 0x18, 0x7);
2272                 bnx2_read_phy(bp, 0x18, &val);
2273                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2274
2275                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2276                 bnx2_read_phy(bp, 0x1c, &val);
2277                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2278         }
2279         else {
2280                 u32 val;
2281
2282                 bnx2_write_phy(bp, 0x18, 0x7);
2283                 bnx2_read_phy(bp, 0x18, &val);
2284                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2285
2286                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2287                 bnx2_read_phy(bp, 0x1c, &val);
2288                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2289         }
2290
2291         return 0;
2292 }
2293
2294 static int
2295 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2296 {
2297         u32 val;
2298
2299         if (reset_phy)
2300                 bnx2_reset_phy(bp);
2301
2302         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2303                 bnx2_write_phy(bp, 0x18, 0x0c00);
2304                 bnx2_write_phy(bp, 0x17, 0x000a);
2305                 bnx2_write_phy(bp, 0x15, 0x310b);
2306                 bnx2_write_phy(bp, 0x17, 0x201f);
2307                 bnx2_write_phy(bp, 0x15, 0x9506);
2308                 bnx2_write_phy(bp, 0x17, 0x401f);
2309                 bnx2_write_phy(bp, 0x15, 0x14e2);
2310                 bnx2_write_phy(bp, 0x18, 0x0400);
2311         }
2312
2313         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2314                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2315                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2316                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2317                 val &= ~(1 << 8);
2318                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2319         }
2320
2321         if (bp->dev->mtu > 1500) {
2322                 /* Set extended packet length bit */
2323                 bnx2_write_phy(bp, 0x18, 0x7);
2324                 bnx2_read_phy(bp, 0x18, &val);
2325                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2326
2327                 bnx2_read_phy(bp, 0x10, &val);
2328                 bnx2_write_phy(bp, 0x10, val | 0x1);
2329         }
2330         else {
2331                 bnx2_write_phy(bp, 0x18, 0x7);
2332                 bnx2_read_phy(bp, 0x18, &val);
2333                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2334
2335                 bnx2_read_phy(bp, 0x10, &val);
2336                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2337         }
2338
2339         /* ethernet@wirespeed */
2340         bnx2_write_phy(bp, 0x18, 0x7007);
2341         bnx2_read_phy(bp, 0x18, &val);
2342         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2343         return 0;
2344 }
2345
2346
2347 static int
2348 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2349 __releases(&bp->phy_lock)
2350 __acquires(&bp->phy_lock)
2351 {
2352         u32 val;
2353         int rc = 0;
2354
2355         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2356         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2357
2358         bp->mii_bmcr = MII_BMCR;
2359         bp->mii_bmsr = MII_BMSR;
2360         bp->mii_bmsr1 = MII_BMSR;
2361         bp->mii_adv = MII_ADVERTISE;
2362         bp->mii_lpa = MII_LPA;
2363
2364         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2365
2366         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2367                 goto setup_phy;
2368
2369         bnx2_read_phy(bp, MII_PHYSID1, &val);
2370         bp->phy_id = val << 16;
2371         bnx2_read_phy(bp, MII_PHYSID2, &val);
2372         bp->phy_id |= val & 0xffff;
2373
2374         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2375                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2376                         rc = bnx2_init_5706s_phy(bp, reset_phy);
2377                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2378                         rc = bnx2_init_5708s_phy(bp, reset_phy);
2379                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2380                         rc = bnx2_init_5709s_phy(bp, reset_phy);
2381         }
2382         else {
2383                 rc = bnx2_init_copper_phy(bp, reset_phy);
2384         }
2385
2386 setup_phy:
2387         if (!rc)
2388                 rc = bnx2_setup_phy(bp, bp->phy_port);
2389
2390         return rc;
2391 }
2392
2393 static int
2394 bnx2_set_mac_loopback(struct bnx2 *bp)
2395 {
2396         u32 mac_mode;
2397
2398         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2399         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2400         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2401         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2402         bp->link_up = 1;
2403         return 0;
2404 }
2405
2406 static int bnx2_test_link(struct bnx2 *);
2407
2408 static int
2409 bnx2_set_phy_loopback(struct bnx2 *bp)
2410 {
2411         u32 mac_mode;
2412         int rc, i;
2413
2414         spin_lock_bh(&bp->phy_lock);
2415         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2416                             BMCR_SPEED1000);
2417         spin_unlock_bh(&bp->phy_lock);
2418         if (rc)
2419                 return rc;
2420
2421         for (i = 0; i < 10; i++) {
2422                 if (bnx2_test_link(bp) == 0)
2423                         break;
2424                 msleep(100);
2425         }
2426
2427         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2428         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2429                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2430                       BNX2_EMAC_MODE_25G_MODE);
2431
2432         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2433         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2434         bp->link_up = 1;
2435         return 0;
2436 }
2437
2438 static int
2439 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2440 {
2441         int i;
2442         u32 val;
2443
2444         bp->fw_wr_seq++;
2445         msg_data |= bp->fw_wr_seq;
2446
2447         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2448
2449         if (!ack)
2450                 return 0;
2451
2452         /* wait for an acknowledgement. */
2453         for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2454                 msleep(10);
2455
2456                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2457
2458                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2459                         break;
2460         }
2461         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2462                 return 0;
2463
2464         /* If we timed out, inform the firmware that this is the case. */
2465         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2466                 if (!silent)
2467                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
2468                                             "%x\n", msg_data);
2469
2470                 msg_data &= ~BNX2_DRV_MSG_CODE;
2471                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2472
2473                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2474
2475                 return -EBUSY;
2476         }
2477
2478         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2479                 return -EIO;
2480
2481         return 0;
2482 }
2483
2484 static int
2485 bnx2_init_5709_context(struct bnx2 *bp)
2486 {
2487         int i, ret = 0;
2488         u32 val;
2489
2490         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2491         val |= (BCM_PAGE_BITS - 8) << 16;
2492         REG_WR(bp, BNX2_CTX_COMMAND, val);
2493         for (i = 0; i < 10; i++) {
2494                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2495                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2496                         break;
2497                 udelay(2);
2498         }
2499         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2500                 return -EBUSY;
2501
2502         for (i = 0; i < bp->ctx_pages; i++) {
2503                 int j;
2504
2505                 if (bp->ctx_blk[i])
2506                         memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2507                 else
2508                         return -ENOMEM;
2509
2510                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2511                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2512                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2513                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2514                        (u64) bp->ctx_blk_mapping[i] >> 32);
2515                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2516                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2517                 for (j = 0; j < 10; j++) {
2518
2519                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2520                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2521                                 break;
2522                         udelay(5);
2523                 }
2524                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2525                         ret = -EBUSY;
2526                         break;
2527                 }
2528         }
2529         return ret;
2530 }
2531
2532 static void
2533 bnx2_init_context(struct bnx2 *bp)
2534 {
2535         u32 vcid;
2536
2537         vcid = 96;
2538         while (vcid) {
2539                 u32 vcid_addr, pcid_addr, offset;
2540                 int i;
2541
2542                 vcid--;
2543
2544                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2545                         u32 new_vcid;
2546
2547                         vcid_addr = GET_PCID_ADDR(vcid);
2548                         if (vcid & 0x8) {
2549                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2550                         }
2551                         else {
2552                                 new_vcid = vcid;
2553                         }
2554                         pcid_addr = GET_PCID_ADDR(new_vcid);
2555                 }
2556                 else {
2557                         vcid_addr = GET_CID_ADDR(vcid);
2558                         pcid_addr = vcid_addr;
2559                 }
2560
2561                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2562                         vcid_addr += (i << PHY_CTX_SHIFT);
2563                         pcid_addr += (i << PHY_CTX_SHIFT);
2564
2565                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2566                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2567
2568                         /* Zero out the context. */
2569                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2570                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2571                 }
2572         }
2573 }
2574
2575 static int
2576 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2577 {
2578         u16 *good_mbuf;
2579         u32 good_mbuf_cnt;
2580         u32 val;
2581
2582         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2583         if (good_mbuf == NULL) {
2584                 printk(KERN_ERR PFX "Failed to allocate memory in "
2585                                     "bnx2_alloc_bad_rbuf\n");
2586                 return -ENOMEM;
2587         }
2588
2589         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2590                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2591
2592         good_mbuf_cnt = 0;
2593
2594         /* Allocate a bunch of mbufs and save the good ones in an array. */
2595         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2596         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2597                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2598                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2599
2600                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2601
2602                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2603
2604                 /* The addresses with Bit 9 set are bad memory blocks. */
2605                 if (!(val & (1 << 9))) {
2606                         good_mbuf[good_mbuf_cnt] = (u16) val;
2607                         good_mbuf_cnt++;
2608                 }
2609
2610                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2611         }
2612
2613         /* Free the good ones back to the mbuf pool thus discarding
2614          * all the bad ones. */
2615         while (good_mbuf_cnt) {
2616                 good_mbuf_cnt--;
2617
2618                 val = good_mbuf[good_mbuf_cnt];
2619                 val = (val << 9) | val | 1;
2620
2621                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2622         }
2623         kfree(good_mbuf);
2624         return 0;
2625 }
2626
2627 static void
2628 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2629 {
2630         u32 val;
2631
2632         val = (mac_addr[0] << 8) | mac_addr[1];
2633
2634         REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2635
2636         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2637                 (mac_addr[4] << 8) | mac_addr[5];
2638
2639         REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2640 }
2641
2642 static inline int
2643 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2644 {
2645         dma_addr_t mapping;
2646         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2647         struct rx_bd *rxbd =
2648                 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2649         struct page *page = alloc_page(GFP_ATOMIC);
2650
2651         if (!page)
2652                 return -ENOMEM;
2653         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2654                                PCI_DMA_FROMDEVICE);
2655         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2656                 __free_page(page);
2657                 return -EIO;
2658         }
2659
2660         rx_pg->page = page;
2661         pci_unmap_addr_set(rx_pg, mapping, mapping);
2662         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2663         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2664         return 0;
2665 }
2666
2667 static void
2668 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2669 {
2670         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2671         struct page *page = rx_pg->page;
2672
2673         if (!page)
2674                 return;
2675
2676         pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2677                        PCI_DMA_FROMDEVICE);
2678
2679         __free_page(page);
2680         rx_pg->page = NULL;
2681 }
2682
2683 static inline int
2684 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2685 {
2686         struct sk_buff *skb;
2687         struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2688         dma_addr_t mapping;
2689         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2690         unsigned long align;
2691
2692         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2693         if (skb == NULL) {
2694                 return -ENOMEM;
2695         }
2696
2697         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2698                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2699
2700         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2701                 PCI_DMA_FROMDEVICE);
2702         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2703                 dev_kfree_skb(skb);
2704                 return -EIO;
2705         }
2706
2707         rx_buf->skb = skb;
2708         pci_unmap_addr_set(rx_buf, mapping, mapping);
2709
2710         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2711         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2712
2713         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2714
2715         return 0;
2716 }
2717
2718 static int
2719 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2720 {
2721         struct status_block *sblk = bnapi->status_blk.msi;
2722         u32 new_link_state, old_link_state;
2723         int is_set = 1;
2724
2725         new_link_state = sblk->status_attn_bits & event;
2726         old_link_state = sblk->status_attn_bits_ack & event;
2727         if (new_link_state != old_link_state) {
2728                 if (new_link_state)
2729                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2730                 else
2731                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2732         } else
2733                 is_set = 0;
2734
2735         return is_set;
2736 }
2737
2738 static void
2739 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2740 {
2741         spin_lock(&bp->phy_lock);
2742
2743         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2744                 bnx2_set_link(bp);
2745         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2746                 bnx2_set_remote_link(bp);
2747
2748         spin_unlock(&bp->phy_lock);
2749
2750 }
2751
2752 static inline u16
2753 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2754 {
2755         u16 cons;
2756
2757         /* Tell compiler that status block fields can change. */
2758         barrier();
2759         cons = *bnapi->hw_tx_cons_ptr;
2760         barrier();
2761         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2762                 cons++;
2763         return cons;
2764 }
2765
2766 static int
2767 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2768 {
2769         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2770         u16 hw_cons, sw_cons, sw_ring_cons;
2771         int tx_pkt = 0, index;
2772         struct netdev_queue *txq;
2773
2774         index = (bnapi - bp->bnx2_napi);
2775         txq = netdev_get_tx_queue(bp->dev, index);
2776
2777         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2778         sw_cons = txr->tx_cons;
2779
2780         while (sw_cons != hw_cons) {
2781                 struct sw_tx_bd *tx_buf;
2782                 struct sk_buff *skb;
2783                 int i, last;
2784
2785                 sw_ring_cons = TX_RING_IDX(sw_cons);
2786
2787                 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2788                 skb = tx_buf->skb;
2789
2790                 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2791                 prefetch(&skb->end);
2792
2793                 /* partial BD completions possible with TSO packets */
2794                 if (tx_buf->is_gso) {
2795                         u16 last_idx, last_ring_idx;
2796
2797                         last_idx = sw_cons + tx_buf->nr_frags + 1;
2798                         last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2799                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2800                                 last_idx++;
2801                         }
2802                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2803                                 break;
2804                         }
2805                 }
2806
2807                 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2808
2809                 tx_buf->skb = NULL;
2810                 last = tx_buf->nr_frags;
2811
2812                 for (i = 0; i < last; i++) {
2813                         sw_cons = NEXT_TX_BD(sw_cons);
2814                 }
2815
2816                 sw_cons = NEXT_TX_BD(sw_cons);
2817
2818                 dev_kfree_skb(skb);
2819                 tx_pkt++;
2820                 if (tx_pkt == budget)
2821                         break;
2822
2823                 if (hw_cons == sw_cons)
2824                         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2825         }
2826
2827         txr->hw_tx_cons = hw_cons;
2828         txr->tx_cons = sw_cons;
2829
2830         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2831          * before checking for netif_tx_queue_stopped().  Without the
2832          * memory barrier, there is a small possibility that bnx2_start_xmit()
2833          * will miss it and cause the queue to be stopped forever.
2834          */
2835         smp_mb();
2836
2837         if (unlikely(netif_tx_queue_stopped(txq)) &&
2838                      (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2839                 __netif_tx_lock(txq, smp_processor_id());
2840                 if ((netif_tx_queue_stopped(txq)) &&
2841                     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2842                         netif_tx_wake_queue(txq);
2843                 __netif_tx_unlock(txq);
2844         }
2845
2846         return tx_pkt;
2847 }
2848
2849 static void
2850 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2851                         struct sk_buff *skb, int count)
2852 {
2853         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2854         struct rx_bd *cons_bd, *prod_bd;
2855         int i;
2856         u16 hw_prod, prod;
2857         u16 cons = rxr->rx_pg_cons;
2858
2859         cons_rx_pg = &rxr->rx_pg_ring[cons];
2860
2861         /* The caller was unable to allocate a new page to replace the
2862          * last one in the frags array, so we need to recycle that page
2863          * and then free the skb.
2864          */
2865         if (skb) {
2866                 struct page *page;
2867                 struct skb_shared_info *shinfo;
2868
2869                 shinfo = skb_shinfo(skb);
2870                 shinfo->nr_frags--;
2871                 page = shinfo->frags[shinfo->nr_frags].page;
2872                 shinfo->frags[shinfo->nr_frags].page = NULL;
2873
2874                 cons_rx_pg->page = page;
2875                 dev_kfree_skb(skb);
2876         }
2877
2878         hw_prod = rxr->rx_pg_prod;
2879
2880         for (i = 0; i < count; i++) {
2881                 prod = RX_PG_RING_IDX(hw_prod);
2882
2883                 prod_rx_pg = &rxr->rx_pg_ring[prod];
2884                 cons_rx_pg = &rxr->rx_pg_ring[cons];
2885                 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2886                 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2887
2888                 if (prod != cons) {
2889                         prod_rx_pg->page = cons_rx_pg->page;
2890                         cons_rx_pg->page = NULL;
2891                         pci_unmap_addr_set(prod_rx_pg, mapping,
2892                                 pci_unmap_addr(cons_rx_pg, mapping));
2893
2894                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2895                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2896
2897                 }
2898                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2899                 hw_prod = NEXT_RX_BD(hw_prod);
2900         }
2901         rxr->rx_pg_prod = hw_prod;
2902         rxr->rx_pg_cons = cons;
2903 }
2904
2905 static inline void
2906 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2907                   struct sk_buff *skb, u16 cons, u16 prod)
2908 {
2909         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2910         struct rx_bd *cons_bd, *prod_bd;
2911
2912         cons_rx_buf = &rxr->rx_buf_ring[cons];
2913         prod_rx_buf = &rxr->rx_buf_ring[prod];
2914
2915         pci_dma_sync_single_for_device(bp->pdev,
2916                 pci_unmap_addr(cons_rx_buf, mapping),
2917                 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2918
2919         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2920
2921         prod_rx_buf->skb = skb;
2922
2923         if (cons == prod)
2924                 return;
2925
2926         pci_unmap_addr_set(prod_rx_buf, mapping,
2927                         pci_unmap_addr(cons_rx_buf, mapping));
2928
2929         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2930         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2931         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2932         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2933 }
2934
2935 static int
2936 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2937             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2938             u32 ring_idx)
2939 {
2940         int err;
2941         u16 prod = ring_idx & 0xffff;
2942
2943         err = bnx2_alloc_rx_skb(bp, rxr, prod);
2944         if (unlikely(err)) {
2945                 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2946                 if (hdr_len) {
2947                         unsigned int raw_len = len + 4;
2948                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2949
2950                         bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2951                 }
2952                 return err;
2953         }
2954
2955         skb_reserve(skb, BNX2_RX_OFFSET);
2956         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2957                          PCI_DMA_FROMDEVICE);
2958
2959         if (hdr_len == 0) {
2960                 skb_put(skb, len);
2961                 return 0;
2962         } else {
2963                 unsigned int i, frag_len, frag_size, pages;
2964                 struct sw_pg *rx_pg;
2965                 u16 pg_cons = rxr->rx_pg_cons;
2966                 u16 pg_prod = rxr->rx_pg_prod;
2967
2968                 frag_size = len + 4 - hdr_len;
2969                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2970                 skb_put(skb, hdr_len);
2971
2972                 for (i = 0; i < pages; i++) {
2973                         dma_addr_t mapping_old;
2974
2975                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2976                         if (unlikely(frag_len <= 4)) {
2977                                 unsigned int tail = 4 - frag_len;
2978
2979                                 rxr->rx_pg_cons = pg_cons;
2980                                 rxr->rx_pg_prod = pg_prod;
2981                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2982                                                         pages - i);
2983                                 skb->len -= tail;
2984                                 if (i == 0) {
2985                                         skb->tail -= tail;
2986                                 } else {
2987                                         skb_frag_t *frag =
2988                                                 &skb_shinfo(skb)->frags[i - 1];
2989                                         frag->size -= tail;
2990                                         skb->data_len -= tail;
2991                                         skb->truesize -= tail;
2992                                 }
2993                                 return 0;
2994                         }
2995                         rx_pg = &rxr->rx_pg_ring[pg_cons];
2996
2997                         /* Don't unmap yet.  If we're unable to allocate a new
2998                          * page, we need to recycle the page and the DMA addr.
2999                          */
3000                         mapping_old = pci_unmap_addr(rx_pg, mapping);
3001                         if (i == pages - 1)
3002                                 frag_len -= 4;
3003
3004                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3005                         rx_pg->page = NULL;
3006
3007                         err = bnx2_alloc_rx_page(bp, rxr,
3008                                                  RX_PG_RING_IDX(pg_prod));
3009                         if (unlikely(err)) {
3010                                 rxr->rx_pg_cons = pg_cons;
3011                                 rxr->rx_pg_prod = pg_prod;
3012                                 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3013                                                         pages - i);
3014                                 return err;
3015                         }
3016
3017                         pci_unmap_page(bp->pdev, mapping_old,
3018                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
3019
3020                         frag_size -= frag_len;
3021                         skb->data_len += frag_len;
3022                         skb->truesize += frag_len;
3023                         skb->len += frag_len;
3024
3025                         pg_prod = NEXT_RX_BD(pg_prod);
3026                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3027                 }
3028                 rxr->rx_pg_prod = pg_prod;
3029                 rxr->rx_pg_cons = pg_cons;
3030         }
3031         return 0;
3032 }
3033
3034 static inline u16
3035 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3036 {
3037         u16 cons;
3038
3039         /* Tell compiler that status block fields can change. */
3040         barrier();
3041         cons = *bnapi->hw_rx_cons_ptr;
3042         barrier();
3043         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3044                 cons++;
3045         return cons;
3046 }
3047
3048 static int
3049 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3050 {
3051         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3052         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3053         struct l2_fhdr *rx_hdr;
3054         int rx_pkt = 0, pg_ring_used = 0;
3055
3056         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3057         sw_cons = rxr->rx_cons;
3058         sw_prod = rxr->rx_prod;
3059
3060         /* Memory barrier necessary as speculative reads of the rx
3061          * buffer can be ahead of the index in the status block
3062          */
3063         rmb();
3064         while (sw_cons != hw_cons) {
3065                 unsigned int len, hdr_len;
3066                 u32 status;
3067                 struct sw_bd *rx_buf;
3068                 struct sk_buff *skb;
3069                 dma_addr_t dma_addr;
3070                 u16 vtag = 0;
3071                 int hw_vlan __maybe_unused = 0;
3072
3073                 sw_ring_cons = RX_RING_IDX(sw_cons);
3074                 sw_ring_prod = RX_RING_IDX(sw_prod);
3075
3076                 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3077                 skb = rx_buf->skb;
3078
3079                 rx_buf->skb = NULL;
3080
3081                 dma_addr = pci_unmap_addr(rx_buf, mapping);
3082
3083                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3084                         BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3085                         PCI_DMA_FROMDEVICE);
3086
3087                 rx_hdr = (struct l2_fhdr *) skb->data;
3088                 len = rx_hdr->l2_fhdr_pkt_len;
3089                 status = rx_hdr->l2_fhdr_status;
3090
3091                 hdr_len = 0;
3092                 if (status & L2_FHDR_STATUS_SPLIT) {
3093                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3094                         pg_ring_used = 1;
3095                 } else if (len > bp->rx_jumbo_thresh) {
3096                         hdr_len = bp->rx_jumbo_thresh;
3097                         pg_ring_used = 1;
3098                 }
3099
3100                 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3101                                        L2_FHDR_ERRORS_PHY_DECODE |
3102                                        L2_FHDR_ERRORS_ALIGNMENT |
3103                                        L2_FHDR_ERRORS_TOO_SHORT |
3104                                        L2_FHDR_ERRORS_GIANT_FRAME))) {
3105
3106                         bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3107                                           sw_ring_prod);
3108                         if (pg_ring_used) {
3109                                 int pages;
3110
3111                                 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3112
3113                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3114                         }
3115                         goto next_rx;
3116                 }
3117
3118                 len -= 4;
3119
3120                 if (len <= bp->rx_copy_thresh) {
3121                         struct sk_buff *new_skb;
3122
3123                         new_skb = netdev_alloc_skb(bp->dev, len + 6);
3124                         if (new_skb == NULL) {
3125                                 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3126                                                   sw_ring_prod);
3127                                 goto next_rx;
3128                         }
3129
3130                         /* aligned copy */
3131                         skb_copy_from_linear_data_offset(skb,
3132                                                          BNX2_RX_OFFSET - 6,
3133                                       new_skb->data, len + 6);
3134                         skb_reserve(new_skb, 6);
3135                         skb_put(new_skb, len);
3136
3137                         bnx2_reuse_rx_skb(bp, rxr, skb,
3138                                 sw_ring_cons, sw_ring_prod);
3139
3140                         skb = new_skb;
3141                 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3142                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3143                         goto next_rx;
3144
3145                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3146                     !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3147                         vtag = rx_hdr->l2_fhdr_vlan_tag;
3148 #ifdef BCM_VLAN
3149                         if (bp->vlgrp)
3150                                 hw_vlan = 1;
3151                         else
3152 #endif
3153                         {
3154                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3155                                         __skb_push(skb, 4);
3156
3157                                 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3158                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
3159                                 ve->h_vlan_TCI = htons(vtag);
3160                                 len += 4;
3161                         }
3162                 }
3163
3164                 skb->protocol = eth_type_trans(skb, bp->dev);
3165
3166                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3167                         (ntohs(skb->protocol) != 0x8100)) {
3168
3169                         dev_kfree_skb(skb);
3170                         goto next_rx;
3171
3172                 }
3173
3174                 skb->ip_summed = CHECKSUM_NONE;
3175                 if (bp->rx_csum &&
3176                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3177                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
3178
3179                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3180                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3181                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3182                 }
3183
3184                 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3185
3186 #ifdef BCM_VLAN
3187                 if (hw_vlan)
3188                         vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3189                 else
3190 #endif
3191                         netif_receive_skb(skb);
3192
3193                 rx_pkt++;
3194
3195 next_rx:
3196                 sw_cons = NEXT_RX_BD(sw_cons);
3197                 sw_prod = NEXT_RX_BD(sw_prod);
3198
3199                 if ((rx_pkt == budget))
3200                         break;
3201
3202                 /* Refresh hw_cons to see if there is new work */
3203                 if (sw_cons == hw_cons) {
3204                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3205                         rmb();
3206                 }
3207         }
3208         rxr->rx_cons = sw_cons;
3209         rxr->rx_prod = sw_prod;
3210
3211         if (pg_ring_used)
3212                 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3213
3214         REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3215
3216         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3217
3218         mmiowb();
3219
3220         return rx_pkt;
3221
3222 }
3223
3224 /* MSI ISR - The only difference between this and the INTx ISR
3225  * is that the MSI interrupt is always serviced.
3226  */
3227 static irqreturn_t
3228 bnx2_msi(int irq, void *dev_instance)
3229 {
3230         struct bnx2_napi *bnapi = dev_instance;
3231         struct bnx2 *bp = bnapi->bp;
3232
3233         prefetch(bnapi->status_blk.msi);
3234         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3235                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3236                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3237
3238         /* Return here if interrupt is disabled. */
3239         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3240                 return IRQ_HANDLED;
3241
3242         napi_schedule(&bnapi->napi);
3243
3244         return IRQ_HANDLED;
3245 }
3246
3247 static irqreturn_t
3248 bnx2_msi_1shot(int irq, void *dev_instance)
3249 {
3250         struct bnx2_napi *bnapi = dev_instance;
3251         struct bnx2 *bp = bnapi->bp;
3252
3253         prefetch(bnapi->status_blk.msi);
3254
3255         /* Return here if interrupt is disabled. */
3256         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3257                 return IRQ_HANDLED;
3258
3259         napi_schedule(&bnapi->napi);
3260
3261         return IRQ_HANDLED;
3262 }
3263
3264 static irqreturn_t
3265 bnx2_interrupt(int irq, void *dev_instance)
3266 {
3267         struct bnx2_napi *bnapi = dev_instance;
3268         struct bnx2 *bp = bnapi->bp;
3269         struct status_block *sblk = bnapi->status_blk.msi;
3270
3271         /* When using INTx, it is possible for the interrupt to arrive
3272          * at the CPU before the status block posted prior to the
3273          * interrupt. Reading a register will flush the status block.
3274          * When using MSI, the MSI message will always complete after
3275          * the status block write.
3276          */
3277         if ((sblk->status_idx == bnapi->last_status_idx) &&
3278             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3279              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3280                 return IRQ_NONE;
3281
3282         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3283                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3284                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3285
3286         /* Read back to deassert IRQ immediately to avoid too many
3287          * spurious interrupts.
3288          */
3289         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3290
3291         /* Return here if interrupt is shared and is disabled. */
3292         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3293                 return IRQ_HANDLED;
3294
3295         if (napi_schedule_prep(&bnapi->napi)) {
3296                 bnapi->last_status_idx = sblk->status_idx;
3297                 __napi_schedule(&bnapi->napi);
3298         }
3299
3300         return IRQ_HANDLED;
3301 }
3302
3303 static inline int
3304 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3305 {
3306         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3307         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3308
3309         if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3310             (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3311                 return 1;
3312         return 0;
3313 }
3314
3315 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
3316                                  STATUS_ATTN_BITS_TIMER_ABORT)
3317
3318 static inline int
3319 bnx2_has_work(struct bnx2_napi *bnapi)
3320 {
3321         struct status_block *sblk = bnapi->status_blk.msi;
3322
3323         if (bnx2_has_fast_work(bnapi))
3324                 return 1;
3325
3326 #ifdef BCM_CNIC
3327         if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3328                 return 1;
3329 #endif
3330
3331         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3332             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3333                 return 1;
3334
3335         return 0;
3336 }
3337
3338 static void
3339 bnx2_chk_missed_msi(struct bnx2 *bp)
3340 {
3341         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3342         u32 msi_ctrl;
3343
3344         if (bnx2_has_work(bnapi)) {
3345                 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3346                 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3347                         return;
3348
3349                 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3350                         REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3351                                ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3352                         REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3353                         bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3354                 }
3355         }
3356
3357         bp->idle_chk_status_idx = bnapi->last_status_idx;
3358 }
3359
3360 #ifdef BCM_CNIC
3361 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3362 {
3363         struct cnic_ops *c_ops;
3364
3365         if (!bnapi->cnic_present)
3366                 return;
3367
3368         rcu_read_lock();
3369         c_ops = rcu_dereference(bp->cnic_ops);
3370         if (c_ops)
3371                 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3372                                                       bnapi->status_blk.msi);
3373         rcu_read_unlock();
3374 }
3375 #endif
3376
3377 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3378 {
3379         struct status_block *sblk = bnapi->status_blk.msi;
3380         u32 status_attn_bits = sblk->status_attn_bits;
3381         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3382
3383         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3384             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3385
3386                 bnx2_phy_int(bp, bnapi);
3387
3388                 /* This is needed to take care of transient status
3389                  * during link changes.
3390                  */
3391                 REG_WR(bp, BNX2_HC_COMMAND,
3392                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3393                 REG_RD(bp, BNX2_HC_COMMAND);
3394         }
3395 }
3396
3397 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3398                           int work_done, int budget)
3399 {
3400         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3401         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3402
3403         if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3404                 bnx2_tx_int(bp, bnapi, 0);
3405
3406         if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3407                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3408
3409         return work_done;
3410 }
3411
3412 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3413 {
3414         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3415         struct bnx2 *bp = bnapi->bp;
3416         int work_done = 0;
3417         struct status_block_msix *sblk = bnapi->status_blk.msix;
3418
3419         while (1) {
3420                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3421                 if (unlikely(work_done >= budget))
3422                         break;
3423
3424                 bnapi->last_status_idx = sblk->status_idx;
3425                 /* status idx must be read before checking for more work. */
3426                 rmb();
3427                 if (likely(!bnx2_has_fast_work(bnapi))) {
3428
3429                         napi_complete(napi);
3430                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3431                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3432                                bnapi->last_status_idx);
3433                         break;
3434                 }
3435         }
3436         return work_done;
3437 }
3438
3439 static int bnx2_poll(struct napi_struct *napi, int budget)
3440 {
3441         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3442         struct bnx2 *bp = bnapi->bp;
3443         int work_done = 0;
3444         struct status_block *sblk = bnapi->status_blk.msi;
3445
3446         while (1) {
3447                 bnx2_poll_link(bp, bnapi);
3448
3449                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3450
3451 #ifdef BCM_CNIC
3452                 bnx2_poll_cnic(bp, bnapi);
3453 #endif
3454
3455                 /* bnapi->last_status_idx is used below to tell the hw how
3456                  * much work has been processed, so we must read it before
3457                  * checking for more work.
3458                  */
3459                 bnapi->last_status_idx = sblk->status_idx;
3460
3461                 if (unlikely(work_done >= budget))
3462                         break;
3463
3464                 rmb();
3465                 if (likely(!bnx2_has_work(bnapi))) {
3466                         napi_complete(napi);
3467                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3468                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3469                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3470                                        bnapi->last_status_idx);
3471                                 break;
3472                         }
3473                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3474                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3475                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3476                                bnapi->last_status_idx);
3477
3478                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3479                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3480                                bnapi->last_status_idx);
3481                         break;
3482                 }
3483         }
3484
3485         return work_done;
3486 }
3487
3488 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3489  * from set_multicast.
3490  */
3491 static void
3492 bnx2_set_rx_mode(struct net_device *dev)
3493 {
3494         struct bnx2 *bp = netdev_priv(dev);
3495         u32 rx_mode, sort_mode;
3496         struct netdev_hw_addr *ha;
3497         int i;
3498
3499         if (!netif_running(dev))
3500                 return;
3501
3502         spin_lock_bh(&bp->phy_lock);
3503
3504         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3505                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3506         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3507 #ifdef BCM_VLAN
3508         if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3509                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3510 #else
3511         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3512                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3513 #endif
3514         if (dev->flags & IFF_PROMISC) {
3515                 /* Promiscuous mode. */
3516                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3517                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3518                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3519         }
3520         else if (dev->flags & IFF_ALLMULTI) {
3521                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3522                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3523                                0xffffffff);
3524                 }
3525                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3526         }
3527         else {
3528                 /* Accept one or more multicast(s). */
3529                 struct dev_mc_list *mclist;
3530                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3531                 u32 regidx;
3532                 u32 bit;
3533                 u32 crc;
3534
3535                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3536
3537                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3538                      i++, mclist = mclist->next) {
3539
3540                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3541                         bit = crc & 0xff;
3542                         regidx = (bit & 0xe0) >> 5;
3543                         bit &= 0x1f;
3544                         mc_filter[regidx] |= (1 << bit);
3545                 }
3546
3547                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3548                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3549                                mc_filter[i]);
3550                 }
3551
3552                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3553         }
3554
3555         if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3556                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3557                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3558                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3559         } else if (!(dev->flags & IFF_PROMISC)) {
3560                 /* Add all entries into to the match filter list */
3561                 i = 0;
3562                 list_for_each_entry(ha, &dev->uc_list, list) {
3563                         bnx2_set_mac_addr(bp, ha->addr,
3564                                           i + BNX2_START_UNICAST_ADDRESS_INDEX);
3565                         sort_mode |= (1 <<
3566                                       (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3567                         i++;
3568                 }
3569
3570         }
3571
3572         if (rx_mode != bp->rx_mode) {
3573                 bp->rx_mode = rx_mode;
3574                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3575         }
3576
3577         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3578         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3579         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3580
3581         spin_unlock_bh(&bp->phy_lock);
3582 }
3583
3584 static int __devinit
3585 check_fw_section(const struct firmware *fw,
3586                  const struct bnx2_fw_file_section *section,
3587                  u32 alignment, bool non_empty)
3588 {
3589         u32 offset = be32_to_cpu(section->offset);
3590         u32 len = be32_to_cpu(section->len);
3591
3592         if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3593                 return -EINVAL;
3594         if ((non_empty && len == 0) || len > fw->size - offset ||
3595             len & (alignment - 1))
3596                 return -EINVAL;
3597         return 0;
3598 }
3599
3600 static int __devinit
3601 check_mips_fw_entry(const struct firmware *fw,
3602                     const struct bnx2_mips_fw_file_entry *entry)
3603 {
3604         if (check_fw_section(fw, &entry->text, 4, true) ||
3605             check_fw_section(fw, &entry->data, 4, false) ||
3606             check_fw_section(fw, &entry->rodata, 4, false))
3607                 return -EINVAL;
3608         return 0;
3609 }
3610
3611 static int __devinit
3612 bnx2_request_firmware(struct bnx2 *bp)
3613 {
3614         const char *mips_fw_file, *rv2p_fw_file;
3615         const struct bnx2_mips_fw_file *mips_fw;
3616         const struct bnx2_rv2p_fw_file *rv2p_fw;
3617         int rc;
3618
3619         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3620                 mips_fw_file = FW_MIPS_FILE_09;
3621                 rv2p_fw_file = FW_RV2P_FILE_09;
3622         } else {
3623                 mips_fw_file = FW_MIPS_FILE_06;
3624                 rv2p_fw_file = FW_RV2P_FILE_06;
3625         }
3626
3627         rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3628         if (rc) {
3629                 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3630                        mips_fw_file);
3631                 return rc;
3632         }
3633
3634         rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3635         if (rc) {
3636                 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3637                        rv2p_fw_file);
3638                 return rc;
3639         }
3640         mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3641         rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3642         if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3643             check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3644             check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3645             check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3646             check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3647             check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3648                 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3649                        mips_fw_file);
3650                 return -EINVAL;
3651         }
3652         if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3653             check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3654             check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3655                 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3656                        rv2p_fw_file);
3657                 return -EINVAL;
3658         }
3659
3660         return 0;
3661 }
3662
3663 static u32
3664 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3665 {
3666         switch (idx) {
3667         case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3668                 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3669                 rv2p_code |= RV2P_BD_PAGE_SIZE;
3670                 break;
3671         }
3672         return rv2p_code;
3673 }
3674
3675 static int
3676 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3677              const struct bnx2_rv2p_fw_file_entry *fw_entry)
3678 {
3679         u32 rv2p_code_len, file_offset;
3680         __be32 *rv2p_code;
3681         int i;
3682         u32 val, cmd, addr;
3683
3684         rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3685         file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3686
3687         rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3688
3689         if (rv2p_proc == RV2P_PROC1) {
3690                 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3691                 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3692         } else {
3693                 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3694                 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3695         }
3696
3697         for (i = 0; i < rv2p_code_len; i += 8) {
3698                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3699                 rv2p_code++;
3700                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3701                 rv2p_code++;
3702
3703                 val = (i / 8) | cmd;
3704                 REG_WR(bp, addr, val);
3705         }
3706
3707         rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3708         for (i = 0; i < 8; i++) {
3709                 u32 loc, code;
3710
3711                 loc = be32_to_cpu(fw_entry->fixup[i]);
3712                 if (loc && ((loc * 4) < rv2p_code_len)) {
3713                         code = be32_to_cpu(*(rv2p_code + loc - 1));
3714                         REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3715                         code = be32_to_cpu(*(rv2p_code + loc));
3716                         code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3717                         REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3718
3719                         val = (loc / 2) | cmd;
3720                         REG_WR(bp, addr, val);
3721                 }
3722         }
3723
3724         /* Reset the processor, un-stall is done later. */
3725         if (rv2p_proc == RV2P_PROC1) {
3726                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3727         }
3728         else {
3729                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3730         }
3731
3732         return 0;
3733 }
3734
3735 static int
3736 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3737             const struct bnx2_mips_fw_file_entry *fw_entry)
3738 {
3739         u32 addr, len, file_offset;
3740         __be32 *data;
3741         u32 offset;
3742         u32 val;
3743
3744         /* Halt the CPU. */
3745         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3746         val |= cpu_reg->mode_value_halt;
3747         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3748         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3749
3750         /* Load the Text area. */
3751         addr = be32_to_cpu(fw_entry->text.addr);
3752         len = be32_to_cpu(fw_entry->text.len);
3753         file_offset = be32_to_cpu(fw_entry->text.offset);
3754         data = (__be32 *)(bp->mips_firmware->data + file_offset);
3755
3756         offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3757         if (len) {
3758                 int j;
3759
3760                 for (j = 0; j < (len / 4); j++, offset += 4)
3761                         bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3762         }
3763
3764         /* Load the Data area. */
3765         addr = be32_to_cpu(fw_entry->data.addr);
3766         len = be32_to_cpu(fw_entry->data.len);
3767         file_offset = be32_to_cpu(fw_entry->data.offset);
3768         data = (__be32 *)(bp->mips_firmware->data + file_offset);
3769
3770         offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3771         if (len) {
3772                 int j;
3773
3774                 for (j = 0; j < (len / 4); j++, offset += 4)
3775                         bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3776         }
3777
3778         /* Load the Read-Only area. */
3779         addr = be32_to_cpu(fw_entry->rodata.addr);
3780         len = be32_to_cpu(fw_entry->rodata.len);
3781         file_offset = be32_to_cpu(fw_entry->rodata.offset);
3782         data = (__be32 *)(bp->mips_firmware->data + file_offset);
3783
3784         offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3785         if (len) {
3786                 int j;
3787
3788                 for (j = 0; j < (len / 4); j++, offset += 4)
3789                         bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3790         }
3791
3792         /* Clear the pre-fetch instruction. */
3793         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3794
3795         val = be32_to_cpu(fw_entry->start_addr);
3796         bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3797
3798         /* Start the CPU. */
3799         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3800         val &= ~cpu_reg->mode_value_halt;
3801         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3802         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3803
3804         return 0;
3805 }
3806
3807 static int
3808 bnx2_init_cpus(struct bnx2 *bp)
3809 {
3810         const struct bnx2_mips_fw_file *mips_fw =
3811                 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3812         const struct bnx2_rv2p_fw_file *rv2p_fw =
3813                 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3814         int rc;
3815
3816         /* Initialize the RV2P processor. */
3817         load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3818         load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3819
3820         /* Initialize the RX Processor. */
3821         rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3822         if (rc)
3823                 goto init_cpu_err;
3824
3825         /* Initialize the TX Processor. */
3826         rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3827         if (rc)
3828                 goto init_cpu_err;
3829
3830         /* Initialize the TX Patch-up Processor. */
3831         rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3832         if (rc)
3833                 goto init_cpu_err;
3834
3835         /* Initialize the Completion Processor. */
3836         rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3837         if (rc)
3838                 goto init_cpu_err;
3839
3840         /* Initialize the Command Processor. */
3841         rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3842
3843 init_cpu_err:
3844         return rc;
3845 }
3846
3847 static int
3848 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3849 {
3850         u16 pmcsr;
3851
3852         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3853
3854         switch (state) {
3855         case PCI_D0: {
3856                 u32 val;
3857
3858                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3859                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3860                         PCI_PM_CTRL_PME_STATUS);
3861
3862                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3863                         /* delay required during transition out of D3hot */
3864                         msleep(20);
3865
3866                 val = REG_RD(bp, BNX2_EMAC_MODE);
3867                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3868                 val &= ~BNX2_EMAC_MODE_MPKT;
3869                 REG_WR(bp, BNX2_EMAC_MODE, val);
3870
3871                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3872                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3873                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3874                 break;
3875         }
3876         case PCI_D3hot: {
3877                 int i;
3878                 u32 val, wol_msg;
3879
3880                 if (bp->wol) {
3881                         u32 advertising;
3882                         u8 autoneg;
3883
3884                         autoneg = bp->autoneg;
3885                         advertising = bp->advertising;
3886
3887                         if (bp->phy_port == PORT_TP) {
3888                                 bp->autoneg = AUTONEG_SPEED;
3889                                 bp->advertising = ADVERTISED_10baseT_Half |
3890                                         ADVERTISED_10baseT_Full |
3891                                         ADVERTISED_100baseT_Half |
3892                                         ADVERTISED_100baseT_Full |
3893                                         ADVERTISED_Autoneg;
3894                         }
3895
3896                         spin_lock_bh(&bp->phy_lock);
3897                         bnx2_setup_phy(bp, bp->phy_port);
3898                         spin_unlock_bh(&bp->phy_lock);
3899
3900                         bp->autoneg = autoneg;
3901                         bp->advertising = advertising;
3902
3903                         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3904
3905                         val = REG_RD(bp, BNX2_EMAC_MODE);
3906
3907                         /* Enable port mode. */
3908                         val &= ~BNX2_EMAC_MODE_PORT;
3909                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3910                                BNX2_EMAC_MODE_ACPI_RCVD |
3911                                BNX2_EMAC_MODE_MPKT;
3912                         if (bp->phy_port == PORT_TP)
3913                                 val |= BNX2_EMAC_MODE_PORT_MII;
3914                         else {
3915                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3916                                 if (bp->line_speed == SPEED_2500)
3917                                         val |= BNX2_EMAC_MODE_25G_MODE;
3918                         }
3919
3920                         REG_WR(bp, BNX2_EMAC_MODE, val);
3921
3922                         /* receive all multicast */
3923                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3924                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3925                                        0xffffffff);
3926                         }
3927                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3928                                BNX2_EMAC_RX_MODE_SORT_MODE);
3929
3930                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3931                               BNX2_RPM_SORT_USER0_MC_EN;
3932                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3933                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3934                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3935                                BNX2_RPM_SORT_USER0_ENA);
3936
3937                         /* Need to enable EMAC and RPM for WOL. */
3938                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3939                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3940                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3941                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3942
3943                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3944                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3945                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3946
3947                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3948                 }
3949                 else {
3950                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3951                 }
3952
3953                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3954                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3955                                      1, 0);
3956
3957                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3958                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3959                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3960
3961                         if (bp->wol)
3962                                 pmcsr |= 3;
3963                 }
3964                 else {
3965                         pmcsr |= 3;
3966                 }
3967                 if (bp->wol) {
3968                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3969                 }
3970                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3971                                       pmcsr);
3972
3973                 /* No more memory access after this point until
3974                  * device is brought back to D0.
3975                  */
3976                 udelay(50);
3977                 break;
3978         }
3979         default:
3980                 return -EINVAL;
3981         }
3982         return 0;
3983 }
3984
3985 static int
3986 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3987 {
3988         u32 val;
3989         int j;
3990
3991         /* Request access to the flash interface. */
3992         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3993         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3994                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3995                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3996                         break;
3997
3998                 udelay(5);
3999         }
4000
4001         if (j >= NVRAM_TIMEOUT_COUNT)
4002                 return -EBUSY;
4003
4004         return 0;
4005 }
4006
4007 static int
4008 bnx2_release_nvram_lock(struct bnx2 *bp)
4009 {
4010         int j;
4011         u32 val;
4012
4013         /* Relinquish nvram interface. */
4014         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4015
4016         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4017                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4018                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4019                         break;
4020
4021                 udelay(5);
4022         }
4023
4024         if (j >= NVRAM_TIMEOUT_COUNT)
4025                 return -EBUSY;
4026
4027         return 0;
4028 }
4029
4030
4031 static int
4032 bnx2_enable_nvram_write(struct bnx2 *bp)
4033 {
4034         u32 val;
4035
4036         val = REG_RD(bp, BNX2_MISC_CFG);
4037         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4038
4039         if (bp->flash_info->flags & BNX2_NV_WREN) {
4040                 int j;
4041
4042                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4043                 REG_WR(bp, BNX2_NVM_COMMAND,
4044                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4045
4046                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4047                         udelay(5);
4048
4049                         val = REG_RD(bp, BNX2_NVM_COMMAND);
4050                         if (val & BNX2_NVM_COMMAND_DONE)
4051                                 break;
4052                 }
4053
4054                 if (j >= NVRAM_TIMEOUT_COUNT)
4055                         return -EBUSY;
4056         }
4057         return 0;
4058 }
4059
4060 static void
4061 bnx2_disable_nvram_write(struct bnx2 *bp)
4062 {
4063         u32 val;
4064
4065         val = REG_RD(bp, BNX2_MISC_CFG);
4066         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4067 }
4068
4069
4070 static void
4071 bnx2_enable_nvram_access(struct bnx2 *bp)
4072 {
4073         u32 val;
4074
4075         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4076         /* Enable both bits, even on read. */
4077         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4078                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4079 }
4080
4081 static void
4082 bnx2_disable_nvram_access(struct bnx2 *bp)
4083 {
4084         u32 val;
4085
4086         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4087         /* Disable both bits, even after read. */
4088         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4089                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4090                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
4091 }
4092
4093 static int
4094 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4095 {
4096         u32 cmd;
4097         int j;
4098
4099         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4100                 /* Buffered flash, no erase needed */
4101                 return 0;
4102
4103         /* Build an erase command */
4104         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4105               BNX2_NVM_COMMAND_DOIT;
4106
4107         /* Need to clear DONE bit separately. */
4108         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4109
4110         /* Address of the NVRAM to read from. */
4111         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4112
4113         /* Issue an erase command. */
4114         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4115
4116         /* Wait for completion. */
4117         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4118                 u32 val;
4119
4120                 udelay(5);
4121
4122                 val = REG_RD(bp, BNX2_NVM_COMMAND);
4123                 if (val & BNX2_NVM_COMMAND_DONE)
4124                         break;
4125         }
4126
4127         if (j >= NVRAM_TIMEOUT_COUNT)
4128                 return -EBUSY;
4129
4130         return 0;
4131 }
4132
4133 static int
4134 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4135 {
4136         u32 cmd;
4137         int j;
4138
4139         /* Build the command word. */
4140         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4141
4142         /* Calculate an offset of a buffered flash, not needed for 5709. */
4143         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4144                 offset = ((offset / bp->flash_info->page_size) <<
4145                            bp->flash_info->page_bits) +
4146                           (offset % bp->flash_info->page_size);
4147         }
4148
4149         /* Need to clear DONE bit separately. */
4150         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4151
4152         /* Address of the NVRAM to read from. */
4153         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4154
4155         /* Issue a read command. */
4156         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4157
4158         /* Wait for completion. */
4159         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4160                 u32 val;
4161
4162                 udelay(5);
4163
4164                 val = REG_RD(bp, BNX2_NVM_COMMAND);
4165                 if (val & BNX2_NVM_COMMAND_DONE) {
4166                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4167                         memcpy(ret_val, &v, 4);
4168                         break;
4169                 }
4170         }
4171         if (j >= NVRAM_TIMEOUT_COUNT)
4172                 return -EBUSY;
4173
4174         return 0;
4175 }
4176
4177
4178 static int
4179 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4180 {
4181         u32 cmd;
4182         __be32 val32;
4183         int j;
4184
4185         /* Build the command word. */
4186         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4187
4188         /* Calculate an offset of a buffered flash, not needed for 5709. */
4189         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4190                 offset = ((offset / bp->flash_info->page_size) <<
4191                           bp->flash_info->page_bits) +
4192                          (offset % bp->flash_info->page_size);
4193         }
4194
4195         /* Need to clear DONE bit separately. */
4196         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4197
4198         memcpy(&val32, val, 4);
4199
4200         /* Write the data. */
4201         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4202
4203         /* Address of the NVRAM to write to. */
4204         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4205
4206         /* Issue the write command. */
4207         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4208
4209         /* Wait for completion. */
4210         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4211                 udelay(5);
4212
4213                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4214                         break;
4215         }
4216         if (j >= NVRAM_TIMEOUT_COUNT)
4217                 return -EBUSY;
4218
4219         return 0;
4220 }
4221
4222 static int
4223 bnx2_init_nvram(struct bnx2 *bp)
4224 {
4225         u32 val;
4226         int j, entry_count, rc = 0;
4227         struct flash_spec *flash;
4228
4229         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4230                 bp->flash_info = &flash_5709;
4231                 goto get_flash_size;
4232         }
4233
4234         /* Determine the selected interface. */
4235         val = REG_RD(bp, BNX2_NVM_CFG1);
4236
4237         entry_count = ARRAY_SIZE(flash_table);
4238
4239         if (val & 0x40000000) {
4240
4241                 /* Flash interface has been reconfigured */
4242                 for (j = 0, flash = &flash_table[0]; j < entry_count;
4243                      j++, flash++) {
4244                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
4245                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4246                                 bp->flash_info = flash;
4247                                 break;
4248                         }
4249                 }
4250         }
4251         else {
4252                 u32 mask;
4253                 /* Not yet been reconfigured */
4254
4255                 if (val & (1 << 23))
4256                         mask = FLASH_BACKUP_STRAP_MASK;
4257                 else
4258                         mask = FLASH_STRAP_MASK;
4259
4260                 for (j = 0, flash = &flash_table[0]; j < entry_count;
4261                         j++, flash++) {
4262
4263                         if ((val & mask) == (flash->strapping & mask)) {
4264                                 bp->flash_info = flash;
4265
4266                                 /* Request access to the flash interface. */
4267                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4268                                         return rc;
4269
4270                                 /* Enable access to flash interface */
4271                                 bnx2_enable_nvram_access(bp);
4272
4273                                 /* Reconfigure the flash interface */
4274                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4275                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4276                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4277                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4278
4279                                 /* Disable access to flash interface */
4280                                 bnx2_disable_nvram_access(bp);
4281                                 bnx2_release_nvram_lock(bp);
4282
4283                                 break;
4284                         }
4285                 }
4286         } /* if (val & 0x40000000) */
4287
4288         if (j == entry_count) {
4289                 bp->flash_info = NULL;
4290                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4291                 return -ENODEV;
4292         }
4293
4294 get_flash_size:
4295         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4296         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4297         if (val)
4298                 bp->flash_size = val;
4299         else
4300                 bp->flash_size = bp->flash_info->total_size;
4301
4302         return rc;
4303 }
4304
4305 static int
4306 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4307                 int buf_size)
4308 {
4309         int rc = 0;
4310         u32 cmd_flags, offset32, len32, extra;
4311
4312         if (buf_size == 0)
4313                 return 0;
4314
4315         /* Request access to the flash interface. */
4316         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4317                 return rc;
4318
4319         /* Enable access to flash interface */
4320         bnx2_enable_nvram_access(bp);
4321
4322         len32 = buf_size;
4323         offset32 = offset;
4324         extra = 0;
4325
4326         cmd_flags = 0;
4327
4328         if (offset32 & 3) {
4329                 u8 buf[4];
4330                 u32 pre_len;
4331
4332                 offset32 &= ~3;
4333                 pre_len = 4 - (offset & 3);
4334
4335                 if (pre_len >= len32) {
4336                         pre_len = len32;
4337                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4338                                     BNX2_NVM_COMMAND_LAST;
4339                 }
4340                 else {
4341                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4342                 }
4343
4344                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4345
4346                 if (rc)
4347                         return rc;
4348
4349                 memcpy(ret_buf, buf + (offset & 3), pre_len);
4350
4351                 offset32 += 4;
4352                 ret_buf += pre_len;
4353                 len32 -= pre_len;
4354         }
4355         if (len32 & 3) {
4356                 extra = 4 - (len32 & 3);
4357                 len32 = (len32 + 4) & ~3;
4358         }
4359
4360         if (len32 == 4) {
4361                 u8 buf[4];
4362
4363                 if (cmd_flags)
4364                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4365                 else
4366                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4367                                     BNX2_NVM_COMMAND_LAST;
4368
4369                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4370
4371                 memcpy(ret_buf, buf, 4 - extra);
4372         }
4373         else if (len32 > 0) {
4374                 u8 buf[4];
4375
4376                 /* Read the first word. */
4377                 if (cmd_flags)
4378                         cmd_flags = 0;
4379                 else
4380                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4381
4382                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4383
4384                 /* Advance to the next dword. */
4385                 offset32 += 4;
4386                 ret_buf += 4;
4387                 len32 -= 4;
4388
4389                 while (len32 > 4 && rc == 0) {
4390                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4391
4392                         /* Advance to the next dword. */
4393                         offset32 += 4;
4394                         ret_buf += 4;
4395                         len32 -= 4;
4396                 }
4397
4398                 if (rc)
4399                         return rc;
4400
4401                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4402                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4403
4404                 memcpy(ret_buf, buf, 4 - extra);
4405         }
4406
4407         /* Disable access to flash interface */
4408         bnx2_disable_nvram_access(bp);
4409
4410         bnx2_release_nvram_lock(bp);
4411
4412         return rc;
4413 }
4414
4415 static int
4416 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4417                 int buf_size)
4418 {
4419         u32 written, offset32, len32;
4420         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4421         int rc = 0;
4422         int align_start, align_end;
4423
4424         buf = data_buf;
4425         offset32 = offset;
4426         len32 = buf_size;
4427         align_start = align_end = 0;
4428
4429         if ((align_start = (offset32 & 3))) {
4430                 offset32 &= ~3;
4431                 len32 += align_start;
4432                 if (len32 < 4)
4433                         len32 = 4;
4434                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4435                         return rc;
4436         }
4437
4438         if (len32 & 3) {
4439                 align_end = 4 - (len32 & 3);
4440                 len32 += align_end;
4441                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4442                         return rc;
4443         }
4444
4445         if (align_start || align_end) {
4446                 align_buf = kmalloc(len32, GFP_KERNEL);
4447                 if (align_buf == NULL)
4448                         return -ENOMEM;
4449                 if (align_start) {
4450                         memcpy(align_buf, start, 4);
4451                 }
4452                 if (align_end) {
4453                         memcpy(align_buf + len32 - 4, end, 4);
4454                 }
4455                 memcpy(align_buf + align_start, data_buf, buf_size);
4456                 buf = align_buf;
4457         }
4458
4459         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4460                 flash_buffer = kmalloc(264, GFP_KERNEL);
4461                 if (flash_buffer == NULL) {
4462                         rc = -ENOMEM;
4463                         goto nvram_write_end;
4464                 }
4465         }
4466
4467         written = 0;
4468         while ((written < len32) && (rc == 0)) {
4469                 u32 page_start, page_end, data_start, data_end;
4470                 u32 addr, cmd_flags;
4471                 int i;
4472
4473                 /* Find the page_start addr */
4474                 page_start = offset32 + written;
4475                 page_start -= (page_start % bp->flash_info->page_size);
4476                 /* Find the page_end addr */
4477                 page_end = page_start + bp->flash_info->page_size;
4478                 /* Find the data_start addr */
4479                 data_start = (written == 0) ? offset32 : page_start;
4480                 /* Find the data_end addr */
4481                 data_end = (page_end > offset32 + len32) ?
4482                         (offset32 + len32) : page_end;
4483
4484                 /* Request access to the flash interface. */
4485                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4486                         goto nvram_write_end;
4487
4488                 /* Enable access to flash interface */
4489                 bnx2_enable_nvram_access(bp);
4490
4491                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4492                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4493                         int j;
4494
4495                         /* Read the whole page into the buffer
4496                          * (non-buffer flash only) */
4497                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4498                                 if (j == (bp->flash_info->page_size - 4)) {
4499                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4500                                 }
4501                                 rc = bnx2_nvram_read_dword(bp,
4502                                         page_start + j,
4503                                         &flash_buffer[j],
4504                                         cmd_flags);
4505
4506                                 if (rc)
4507                                         goto nvram_write_end;
4508
4509                                 cmd_flags = 0;
4510                         }
4511                 }
4512
4513                 /* Enable writes to flash interface (unlock write-protect) */
4514                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4515                         goto nvram_write_end;
4516
4517                 /* Loop to write back the buffer data from page_start to
4518                  * data_start */
4519                 i = 0;
4520                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4521                         /* Erase the page */
4522                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4523                                 goto nvram_write_end;
4524
4525                         /* Re-enable the write again for the actual write */
4526                         bnx2_enable_nvram_write(bp);
4527
4528                         for (addr = page_start; addr < data_start;
4529                                 addr += 4, i += 4) {
4530
4531                                 rc = bnx2_nvram_write_dword(bp, addr,
4532                                         &flash_buffer[i], cmd_flags);
4533
4534                                 if (rc != 0)
4535                                         goto nvram_write_end;
4536
4537                                 cmd_flags = 0;
4538                         }
4539                 }
4540
4541                 /* Loop to write the new data from data_start to data_end */
4542                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4543                         if ((addr == page_end - 4) ||
4544                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4545                                  (addr == data_end - 4))) {
4546
4547                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4548                         }
4549                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4550                                 cmd_flags);
4551
4552                         if (rc != 0)
4553                                 goto nvram_write_end;
4554
4555                         cmd_flags = 0;
4556                         buf += 4;
4557                 }
4558
4559                 /* Loop to write back the buffer data from data_end
4560                  * to page_end */
4561                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4562                         for (addr = data_end; addr < page_end;
4563                                 addr += 4, i += 4) {
4564
4565                                 if (addr == page_end-4) {
4566                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4567                                 }
4568                                 rc = bnx2_nvram_write_dword(bp, addr,
4569                                         &flash_buffer[i], cmd_flags);
4570
4571                                 if (rc != 0)
4572                                         goto nvram_write_end;
4573
4574                                 cmd_flags = 0;
4575                         }
4576                 }
4577
4578                 /* Disable writes to flash interface (lock write-protect) */
4579                 bnx2_disable_nvram_write(bp);
4580
4581                 /* Disable access to flash interface */
4582                 bnx2_disable_nvram_access(bp);
4583                 bnx2_release_nvram_lock(bp);
4584
4585                 /* Increment written */
4586                 written += data_end - data_start;
4587         }
4588
4589 nvram_write_end:
4590         kfree(flash_buffer);
4591         kfree(align_buf);
4592         return rc;
4593 }
4594
4595 static void
4596 bnx2_init_fw_cap(struct bnx2 *bp)
4597 {
4598         u32 val, sig = 0;
4599
4600         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4601         bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4602
4603         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4604                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4605
4606         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4607         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4608                 return;
4609
4610         if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4611                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4612                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4613         }
4614
4615         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4616             (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4617                 u32 link;
4618
4619                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4620
4621                 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4622                 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4623                         bp->phy_port = PORT_FIBRE;
4624                 else
4625                         bp->phy_port = PORT_TP;
4626
4627                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4628                        BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4629         }
4630
4631         if (netif_running(bp->dev) && sig)
4632                 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4633 }
4634
4635 static void
4636 bnx2_setup_msix_tbl(struct bnx2 *bp)
4637 {
4638         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4639
4640         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4641         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4642 }
4643
4644 static int
4645 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4646 {
4647         u32 val;
4648         int i, rc = 0;
4649         u8 old_port;
4650
4651         /* Wait for the current PCI transaction to complete before
4652          * issuing a reset. */
4653         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4654                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4655                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4656                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4657                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4658         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4659         udelay(5);
4660
4661         /* Wait for the firmware to tell us it is ok to issue a reset. */
4662         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4663
4664         /* Deposit a driver reset signature so the firmware knows that
4665          * this is a soft reset. */
4666         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4667                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4668
4669         /* Do a dummy read to force the chip to complete all current transaction
4670          * before we issue a reset. */
4671         val = REG_RD(bp, BNX2_MISC_ID);
4672
4673         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4674                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4675                 REG_RD(bp, BNX2_MISC_COMMAND);
4676                 udelay(5);
4677
4678                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4679                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4680
4681                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4682
4683         } else {
4684                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4685                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4686                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4687
4688                 /* Chip reset. */
4689                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4690
4691                 /* Reading back any register after chip reset will hang the
4692                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4693                  * of margin for write posting.
4694                  */
4695                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4696                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4697                         msleep(20);
4698
4699                 /* Reset takes approximate 30 usec */
4700                 for (i = 0; i < 10; i++) {
4701                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4702                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4703                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4704                                 break;
4705                         udelay(10);
4706                 }
4707
4708                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4709                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4710                         printk(KERN_ERR PFX "Chip reset did not complete\n");
4711                         return -EBUSY;
4712                 }
4713         }
4714
4715         /* Make sure byte swapping is properly configured. */
4716         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4717         if (val != 0x01020304) {
4718                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4719                 return -ENODEV;
4720         }
4721
4722         /* Wait for the firmware to finish its initialization. */
4723         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4724         if (rc)
4725                 return rc;
4726
4727         spin_lock_bh(&bp->phy_lock);
4728         old_port = bp->phy_port;
4729         bnx2_init_fw_cap(bp);
4730         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4731             old_port != bp->phy_port)
4732                 bnx2_set_default_remote_link(bp);
4733         spin_unlock_bh(&bp->phy_lock);
4734
4735         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4736                 /* Adjust the voltage regular to two steps lower.  The default
4737                  * of this register is 0x0000000e. */
4738                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4739
4740                 /* Remove bad rbuf memory from the free pool. */
4741                 rc = bnx2_alloc_bad_rbuf(bp);
4742         }
4743
4744         if (bp->flags & BNX2_FLAG_USING_MSIX)
4745                 bnx2_setup_msix_tbl(bp);
4746
4747         return rc;
4748 }
4749
4750 static int
4751 bnx2_init_chip(struct bnx2 *bp)
4752 {
4753         u32 val, mtu;
4754         int rc, i;
4755
4756         /* Make sure the interrupt is not active. */
4757         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4758
4759         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4760               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4761 #ifdef __BIG_ENDIAN
4762               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4763 #endif
4764               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4765               DMA_READ_CHANS << 12 |
4766               DMA_WRITE_CHANS << 16;
4767
4768         val |= (0x2 << 20) | (1 << 11);
4769
4770         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4771                 val |= (1 << 23);
4772
4773         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4774             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4775                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4776
4777         REG_WR(bp, BNX2_DMA_CONFIG, val);
4778
4779         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4780                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4781                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4782                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4783         }
4784
4785         if (bp->flags & BNX2_FLAG_PCIX) {
4786                 u16 val16;
4787
4788                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4789                                      &val16);
4790                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4791                                       val16 & ~PCI_X_CMD_ERO);
4792         }
4793
4794         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4795                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4796                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4797                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4798
4799         /* Initialize context mapping and zero out the quick contexts.  The
4800          * context block must have already been enabled. */
4801         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4802                 rc = bnx2_init_5709_context(bp);
4803                 if (rc)
4804                         return rc;
4805         } else
4806                 bnx2_init_context(bp);
4807
4808         if ((rc = bnx2_init_cpus(bp)) != 0)
4809                 return rc;
4810
4811         bnx2_init_nvram(bp);
4812
4813         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4814
4815         val = REG_RD(bp, BNX2_MQ_CONFIG);
4816         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4817         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4818         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4819                 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4820                 if (CHIP_REV(bp) == CHIP_REV_Ax)
4821                         val |= BNX2_MQ_CONFIG_HALT_DIS;
4822         }
4823
4824         REG_WR(bp, BNX2_MQ_CONFIG, val);
4825
4826         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4827         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4828         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4829
4830         val = (BCM_PAGE_BITS - 8) << 24;
4831         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4832
4833         /* Configure page size. */
4834         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4835         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4836         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4837         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4838
4839         val = bp->mac_addr[0] +
4840               (bp->mac_addr[1] << 8) +
4841               (bp->mac_addr[2] << 16) +
4842               bp->mac_addr[3] +
4843               (bp->mac_addr[4] << 8) +
4844               (bp->mac_addr[5] << 16);
4845         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4846
4847         /* Program the MTU.  Also include 4 bytes for CRC32. */
4848         mtu = bp->dev->mtu;
4849         val = mtu + ETH_HLEN + ETH_FCS_LEN;
4850         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4851                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4852         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4853
4854         if (mtu < 1500)
4855                 mtu = 1500;
4856
4857         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4858         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4859         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4860
4861         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4862                 bp->bnx2_napi[i].last_status_idx = 0;
4863
4864         bp->idle_chk_status_idx = 0xffff;
4865
4866         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4867
4868         /* Set up how to generate a link change interrupt. */
4869         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4870
4871         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4872                (u64) bp->status_blk_mapping & 0xffffffff);
4873         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4874
4875         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4876                (u64) bp->stats_blk_mapping & 0xffffffff);
4877         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4878                (u64) bp->stats_blk_mapping >> 32);
4879
4880         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4881                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4882
4883         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4884                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4885
4886         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4887                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4888
4889         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4890
4891         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4892
4893         REG_WR(bp, BNX2_HC_COM_TICKS,
4894                (bp->com_ticks_int << 16) | bp->com_ticks);
4895
4896         REG_WR(bp, BNX2_HC_CMD_TICKS,
4897                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4898
4899         if (CHIP_NUM(bp) == CHIP_NUM_5708)
4900                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4901         else
4902                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4903         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4904
4905         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4906                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4907         else {
4908                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4909                       BNX2_HC_CONFIG_COLLECT_STATS;
4910         }
4911
4912         if (bp->irq_nvecs > 1) {
4913                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4914                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4915
4916                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4917         }
4918
4919         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4920                 val |= BNX2_HC_CONFIG_ONE_SHOT;
4921
4922         REG_WR(bp, BNX2_HC_CONFIG, val);
4923
4924         for (i = 1; i < bp->irq_nvecs; i++) {
4925                 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4926                            BNX2_HC_SB_CONFIG_1;
4927
4928                 REG_WR(bp, base,
4929                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4930                         BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4931                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4932
4933                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4934                         (bp->tx_quick_cons_trip_int << 16) |
4935                          bp->tx_quick_cons_trip);
4936
4937                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4938                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4939
4940                 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4941                        (bp->rx_quick_cons_trip_int << 16) |
4942                         bp->rx_quick_cons_trip);
4943
4944                 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4945                         (bp->rx_ticks_int << 16) | bp->rx_ticks);
4946         }
4947
4948         /* Clear internal stats counters. */
4949         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4950
4951         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4952
4953         /* Initialize the receive filter. */
4954         bnx2_set_rx_mode(bp->dev);
4955
4956         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4957                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4958                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4959                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4960         }
4961         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4962                           1, 0);
4963
4964         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4965         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4966
4967         udelay(20);
4968
4969         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4970
4971         return rc;
4972 }
4973
4974 static void
4975 bnx2_clear_ring_states(struct bnx2 *bp)
4976 {
4977         struct bnx2_napi *bnapi;
4978         struct bnx2_tx_ring_info *txr;
4979         struct bnx2_rx_ring_info *rxr;
4980         int i;
4981
4982         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4983                 bnapi = &bp->bnx2_napi[i];
4984                 txr = &bnapi->tx_ring;
4985                 rxr = &bnapi->rx_ring;
4986
4987                 txr->tx_cons = 0;
4988                 txr->hw_tx_cons = 0;
4989                 rxr->rx_prod_bseq = 0;
4990                 rxr->rx_prod = 0;
4991                 rxr->rx_cons = 0;
4992                 rxr->rx_pg_prod = 0;
4993                 rxr->rx_pg_cons = 0;
4994         }
4995 }
4996
4997 static void
4998 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4999 {
5000         u32 val, offset0, offset1, offset2, offset3;
5001         u32 cid_addr = GET_CID_ADDR(cid);
5002
5003         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5004                 offset0 = BNX2_L2CTX_TYPE_XI;
5005                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5006                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5007                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5008         } else {
5009                 offset0 = BNX2_L2CTX_TYPE;
5010                 offset1 = BNX2_L2CTX_CMD_TYPE;
5011                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5012                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5013         }
5014         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5015         bnx2_ctx_wr(bp, cid_addr, offset0, val);
5016
5017         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5018         bnx2_ctx_wr(bp, cid_addr, offset1, val);
5019
5020         val = (u64) txr->tx_desc_mapping >> 32;
5021         bnx2_ctx_wr(bp, cid_addr, offset2, val);
5022
5023         val = (u64) txr->tx_desc_mapping & 0xffffffff;
5024         bnx2_ctx_wr(bp, cid_addr, offset3, val);
5025 }
5026
5027 static void
5028 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5029 {
5030         struct tx_bd *txbd;
5031         u32 cid = TX_CID;
5032         struct bnx2_napi *bnapi;
5033         struct bnx2_tx_ring_info *txr;
5034
5035         bnapi = &bp->bnx2_napi[ring_num];
5036         txr = &bnapi->tx_ring;
5037
5038         if (ring_num == 0)
5039                 cid = TX_CID;
5040         else
5041                 cid = TX_TSS_CID + ring_num - 1;
5042
5043         bp->tx_wake_thresh = bp->tx_ring_size / 2;
5044
5045         txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5046
5047         txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5048         txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5049
5050         txr->tx_prod = 0;
5051         txr->tx_prod_bseq = 0;
5052
5053         txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5054         txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5055
5056         bnx2_init_tx_context(bp, cid, txr);
5057 }
5058
5059 static void
5060 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5061                      int num_rings)
5062 {
5063         int i;
5064         struct rx_bd *rxbd;
5065
5066         for (i = 0; i < num_rings; i++) {
5067                 int j;
5068
5069                 rxbd = &rx_ring[i][0];
5070                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5071                         rxbd->rx_bd_len = buf_size;
5072                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5073                 }
5074                 if (i == (num_rings - 1))
5075                         j = 0;
5076                 else
5077                         j = i + 1;
5078                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5079                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5080         }
5081 }
5082
5083 static void
5084 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5085 {
5086         int i;
5087         u16 prod, ring_prod;
5088         u32 cid, rx_cid_addr, val;
5089         struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5090         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5091
5092         if (ring_num == 0)
5093                 cid = RX_CID;
5094         else
5095                 cid = RX_RSS_CID + ring_num - 1;
5096
5097         rx_cid_addr = GET_CID_ADDR(cid);
5098
5099         bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5100                              bp->rx_buf_use_size, bp->rx_max_ring);
5101
5102         bnx2_init_rx_context(bp, cid);
5103
5104         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5105                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5106                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5107         }
5108
5109         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5110         if (bp->rx_pg_ring_size) {
5111                 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5112                                      rxr->rx_pg_desc_mapping,
5113                                      PAGE_SIZE, bp->rx_max_pg_ring);
5114                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5115                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5116                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5117                        BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5118
5119                 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5120                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5121
5122                 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5123                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5124
5125                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5126                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5127         }
5128
5129         val = (u64) rxr->rx_desc_mapping[0] >> 32;
5130         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5131
5132         val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5133         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5134
5135         ring_prod = prod = rxr->rx_pg_prod;
5136         for (i = 0; i < bp->rx_pg_ring_size; i++) {
5137                 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
5138                         break;
5139                 prod = NEXT_RX_BD(prod);
5140                 ring_prod = RX_PG_RING_IDX(prod);
5141         }
5142         rxr->rx_pg_prod = prod;
5143
5144         ring_prod = prod = rxr->rx_prod;
5145         for (i = 0; i < bp->rx_ring_size; i++) {
5146                 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
5147                         break;
5148                 prod = NEXT_RX_BD(prod);
5149                 ring_prod = RX_RING_IDX(prod);
5150         }
5151         rxr->rx_prod = prod;
5152
5153         rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5154         rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5155         rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5156
5157         REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5158         REG_WR16(bp, rxr->rx_bidx_addr, prod);
5159
5160         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5161 }
5162
5163 static void
5164 bnx2_init_all_rings(struct bnx2 *bp)
5165 {
5166         int i;
5167         u32 val;
5168
5169         bnx2_clear_ring_states(bp);
5170
5171         REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5172         for (i = 0; i < bp->num_tx_rings; i++)
5173                 bnx2_init_tx_ring(bp, i);
5174
5175         if (bp->num_tx_rings > 1)
5176                 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5177                        (TX_TSS_CID << 7));
5178
5179         REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5180         bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5181
5182         for (i = 0; i < bp->num_rx_rings; i++)
5183                 bnx2_init_rx_ring(bp, i);
5184
5185         if (bp->num_rx_rings > 1) {
5186                 u32 tbl_32;
5187                 u8 *tbl = (u8 *) &tbl_32;
5188
5189                 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5190                                 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5191
5192                 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5193                         tbl[i % 4] = i % (bp->num_rx_rings - 1);
5194                         if ((i % 4) == 3)
5195                                 bnx2_reg_wr_ind(bp,
5196                                                 BNX2_RXP_SCRATCH_RSS_TBL + i,
5197                                                 cpu_to_be32(tbl_32));
5198                 }
5199
5200                 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5201                       BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5202
5203                 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5204
5205         }
5206 }
5207
5208 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5209 {
5210         u32 max, num_rings = 1;
5211
5212         while (ring_size > MAX_RX_DESC_CNT) {
5213                 ring_size -= MAX_RX_DESC_CNT;
5214                 num_rings++;
5215         }
5216         /* round to next power of 2 */
5217         max = max_size;
5218         while ((max & num_rings) == 0)
5219                 max >>= 1;
5220
5221         if (num_rings != max)
5222                 max <<= 1;
5223
5224         return max;
5225 }
5226
5227 static void
5228 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5229 {
5230         u32 rx_size, rx_space, jumbo_size;
5231
5232         /* 8 for CRC and VLAN */
5233         rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5234
5235         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5236                 sizeof(struct skb_shared_info);
5237
5238         bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5239         bp->rx_pg_ring_size = 0;
5240         bp->rx_max_pg_ring = 0;
5241         bp->rx_max_pg_ring_idx = 0;
5242         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5243                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5244
5245                 jumbo_size = size * pages;
5246                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5247                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5248
5249                 bp->rx_pg_ring_size = jumbo_size;
5250                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5251                                                         MAX_RX_PG_RINGS);
5252                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5253                 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5254                 bp->rx_copy_thresh = 0;
5255         }
5256
5257         bp->rx_buf_use_size = rx_size;
5258         /* hw alignment */
5259         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5260         bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5261         bp->rx_ring_size = size;
5262         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5263         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5264 }
5265
5266 static void
5267 bnx2_free_tx_skbs(struct bnx2 *bp)
5268 {
5269         int i;
5270
5271         for (i = 0; i < bp->num_tx_rings; i++) {
5272                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5273                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5274                 int j;
5275
5276                 if (txr->tx_buf_ring == NULL)
5277                         continue;
5278
5279                 for (j = 0; j < TX_DESC_CNT; ) {
5280                         struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5281                         struct sk_buff *skb = tx_buf->skb;
5282
5283                         if (skb == NULL) {
5284                                 j++;
5285                                 continue;
5286                         }
5287
5288                         skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5289
5290                         tx_buf->skb = NULL;
5291
5292                         j += skb_shinfo(skb)->nr_frags + 1;
5293                         dev_kfree_skb(skb);
5294                 }
5295         }
5296 }
5297
5298 static void
5299 bnx2_free_rx_skbs(struct bnx2 *bp)
5300 {
5301         int i;
5302
5303         for (i = 0; i < bp->num_rx_rings; i++) {
5304                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5305                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5306                 int j;
5307
5308                 if (rxr->rx_buf_ring == NULL)
5309                         return;
5310
5311                 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5312                         struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5313                         struct sk_buff *skb = rx_buf->skb;
5314
5315                         if (skb == NULL)
5316                                 continue;
5317
5318                         pci_unmap_single(bp->pdev,
5319                                          pci_unmap_addr(rx_buf, mapping),
5320                                          bp->rx_buf_use_size,
5321                                          PCI_DMA_FROMDEVICE);
5322
5323                         rx_buf->skb = NULL;
5324
5325                         dev_kfree_skb(skb);
5326                 }
5327                 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5328                         bnx2_free_rx_page(bp, rxr, j);
5329         }
5330 }
5331
5332 static void
5333 bnx2_free_skbs(struct bnx2 *bp)
5334 {
5335         bnx2_free_tx_skbs(bp);
5336         bnx2_free_rx_skbs(bp);
5337 }
5338
5339 static int
5340 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5341 {
5342         int rc;
5343
5344         rc = bnx2_reset_chip(bp, reset_code);
5345         bnx2_free_skbs(bp);
5346         if (rc)
5347                 return rc;
5348
5349         if ((rc = bnx2_init_chip(bp)) != 0)
5350                 return rc;
5351
5352         bnx2_init_all_rings(bp);
5353         return 0;
5354 }
5355
5356 static int
5357 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5358 {
5359         int rc;
5360
5361         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5362                 return rc;
5363
5364         spin_lock_bh(&bp->phy_lock);
5365         bnx2_init_phy(bp, reset_phy);
5366         bnx2_set_link(bp);
5367         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5368                 bnx2_remote_phy_event(bp);
5369         spin_unlock_bh(&bp->phy_lock);
5370         return 0;
5371 }
5372
5373 static int
5374 bnx2_shutdown_chip(struct bnx2 *bp)
5375 {
5376         u32 reset_code;
5377
5378         if (bp->flags & BNX2_FLAG_NO_WOL)
5379                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5380         else if (bp->wol)
5381                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5382         else
5383                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5384
5385         return bnx2_reset_chip(bp, reset_code);
5386 }
5387
5388 static int
5389 bnx2_test_registers(struct bnx2 *bp)
5390 {
5391         int ret;
5392         int i, is_5709;
5393         static const struct {
5394                 u16   offset;
5395                 u16   flags;
5396 #define BNX2_FL_NOT_5709        1
5397                 u32   rw_mask;
5398                 u32   ro_mask;
5399         } reg_tbl[] = {
5400                 { 0x006c, 0, 0x00000000, 0x0000003f },
5401                 { 0x0090, 0, 0xffffffff, 0x00000000 },
5402                 { 0x0094, 0, 0x00000000, 0x00000000 },
5403
5404                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5405                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5406                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5407                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5408                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5409                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5410                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5411                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5412                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5413
5414                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5415                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5416                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5417                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5418                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5419                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5420
5421                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5422                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5423                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5424
5425                 { 0x1000, 0, 0x00000000, 0x00000001 },
5426                 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5427
5428                 { 0x1408, 0, 0x01c00800, 0x00000000 },
5429                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5430                 { 0x14a8, 0, 0x00000000, 0x000001ff },
5431                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5432                 { 0x14b0, 0, 0x00000002, 0x00000001 },
5433                 { 0x14b8, 0, 0x00000000, 0x00000000 },
5434                 { 0x14c0, 0, 0x00000000, 0x00000009 },
5435                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5436                 { 0x14cc, 0, 0x00000000, 0x00000001 },
5437                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5438
5439                 { 0x1800, 0, 0x00000000, 0x00000001 },
5440                 { 0x1804, 0, 0x00000000, 0x00000003 },
5441
5442                 { 0x2800, 0, 0x00000000, 0x00000001 },
5443                 { 0x2804, 0, 0x00000000, 0x00003f01 },
5444                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5445                 { 0x2810, 0, 0xffff0000, 0x00000000 },
5446                 { 0x2814, 0, 0xffff0000, 0x00000000 },
5447                 { 0x2818, 0, 0xffff0000, 0x00000000 },
5448                 { 0x281c, 0, 0xffff0000, 0x00000000 },
5449                 { 0x2834, 0, 0xffffffff, 0x00000000 },
5450                 { 0x2840, 0, 0x00000000, 0xffffffff },
5451                 { 0x2844, 0, 0x00000000, 0xffffffff },
5452                 { 0x2848, 0, 0xffffffff, 0x00000000 },
5453                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5454
5455                 { 0x2c00, 0, 0x00000000, 0x00000011 },
5456                 { 0x2c04, 0, 0x00000000, 0x00030007 },
5457
5458                 { 0x3c00, 0, 0x00000000, 0x00000001 },
5459                 { 0x3c04, 0, 0x00000000, 0x00070000 },
5460                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5461                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5462                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5463                 { 0x3c14, 0, 0x00000000, 0xffffffff },
5464                 { 0x3c18, 0, 0x00000000, 0xffffffff },
5465                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5466                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5467
5468                 { 0x5004, 0, 0x00000000, 0x0000007f },
5469                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5470
5471                 { 0x5c00, 0, 0x00000000, 0x00000001 },
5472                 { 0x5c04, 0, 0x00000000, 0x0003000f },
5473                 { 0x5c08, 0, 0x00000003, 0x00000000 },
5474                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5475                 { 0x5c10, 0, 0x00000000, 0xffffffff },
5476                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5477                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5478                 { 0x5c88, 0, 0x00000000, 0x00077373 },
5479                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5480
5481                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5482                 { 0x680c, 0, 0xffffffff, 0x00000000 },
5483                 { 0x6810, 0, 0xffffffff, 0x00000000 },
5484                 { 0x6814, 0, 0xffffffff, 0x00000000 },
5485                 { 0x6818, 0, 0xffffffff, 0x00000000 },
5486                 { 0x681c, 0, 0xffffffff, 0x00000000 },
5487                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5488                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5489                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5490                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5491                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5492                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5493                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5494                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5495                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5496                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5497                 { 0x684c, 0, 0xffffffff, 0x00000000 },
5498                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5499                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5500                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5501                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5502                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5503                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5504
5505                 { 0xffff, 0, 0x00000000, 0x00000000 },
5506         };
5507
5508         ret = 0;
5509         is_5709 = 0;
5510         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5511                 is_5709 = 1;
5512
5513         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5514                 u32 offset, rw_mask, ro_mask, save_val, val;
5515                 u16 flags = reg_tbl[i].flags;
5516
5517                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5518                         continue;
5519
5520                 offset = (u32) reg_tbl[i].offset;
5521                 rw_mask = reg_tbl[i].rw_mask;
5522                 ro_mask = reg_tbl[i].ro_mask;
5523
5524                 save_val = readl(bp->regview + offset);
5525
5526                 writel(0, bp->regview + offset);
5527
5528                 val = readl(bp->regview + offset);
5529                 if ((val & rw_mask) != 0) {
5530                         goto reg_test_err;
5531                 }
5532
5533                 if ((val & ro_mask) != (save_val & ro_mask)) {
5534                         goto reg_test_err;
5535                 }
5536
5537                 writel(0xffffffff, bp->regview + offset);
5538
5539                 val = readl(bp->regview + offset);
5540                 if ((val & rw_mask) != rw_mask) {
5541                         goto reg_test_err;
5542                 }
5543
5544                 if ((val & ro_mask) != (save_val & ro_mask)) {
5545                         goto reg_test_err;
5546                 }
5547
5548                 writel(save_val, bp->regview + offset);
5549                 continue;
5550
5551 reg_test_err:
5552                 writel(save_val, bp->regview + offset);
5553                 ret = -ENODEV;
5554                 break;
5555         }
5556         return ret;
5557 }
5558
5559 static int
5560 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5561 {
5562         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5563                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5564         int i;
5565
5566         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5567                 u32 offset;
5568
5569                 for (offset = 0; offset < size; offset += 4) {
5570
5571                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5572
5573                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5574                                 test_pattern[i]) {
5575                                 return -ENODEV;
5576                         }
5577                 }
5578         }
5579         return 0;
5580 }
5581
5582 static int
5583 bnx2_test_memory(struct bnx2 *bp)
5584 {
5585         int ret = 0;
5586         int i;
5587         static struct mem_entry {
5588                 u32   offset;
5589                 u32   len;
5590         } mem_tbl_5706[] = {
5591                 { 0x60000,  0x4000 },
5592                 { 0xa0000,  0x3000 },
5593                 { 0xe0000,  0x4000 },
5594                 { 0x120000, 0x4000 },
5595                 { 0x1a0000, 0x4000 },
5596                 { 0x160000, 0x4000 },
5597                 { 0xffffffff, 0    },
5598         },
5599         mem_tbl_5709[] = {
5600                 { 0x60000,  0x4000 },
5601                 { 0xa0000,  0x3000 },
5602                 { 0xe0000,  0x4000 },
5603                 { 0x120000, 0x4000 },
5604                 { 0x1a0000, 0x4000 },
5605                 { 0xffffffff, 0    },
5606         };
5607         struct mem_entry *mem_tbl;
5608
5609         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5610                 mem_tbl = mem_tbl_5709;
5611         else
5612                 mem_tbl = mem_tbl_5706;
5613
5614         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5615                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5616                         mem_tbl[i].len)) != 0) {
5617                         return ret;
5618                 }
5619         }
5620
5621         return ret;
5622 }
5623
5624 #define BNX2_MAC_LOOPBACK       0
5625 #define BNX2_PHY_LOOPBACK       1
5626
5627 static int
5628 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5629 {
5630         unsigned int pkt_size, num_pkts, i;
5631         struct sk_buff *skb, *rx_skb;
5632         unsigned char *packet;
5633         u16 rx_start_idx, rx_idx;
5634         dma_addr_t map;
5635         struct tx_bd *txbd;
5636         struct sw_bd *rx_buf;
5637         struct l2_fhdr *rx_hdr;
5638         int ret = -ENODEV;
5639         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5640         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5641         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5642
5643         tx_napi = bnapi;
5644
5645         txr = &tx_napi->tx_ring;
5646         rxr = &bnapi->rx_ring;
5647         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5648                 bp->loopback = MAC_LOOPBACK;
5649                 bnx2_set_mac_loopback(bp);
5650         }
5651         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5652                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5653                         return 0;
5654
5655                 bp->loopback = PHY_LOOPBACK;
5656                 bnx2_set_phy_loopback(bp);
5657         }
5658         else
5659                 return -EINVAL;
5660
5661         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5662         skb = netdev_alloc_skb(bp->dev, pkt_size);
5663         if (!skb)
5664                 return -ENOMEM;
5665         packet = skb_put(skb, pkt_size);
5666         memcpy(packet, bp->dev->dev_addr, 6);
5667         memset(packet + 6, 0x0, 8);
5668         for (i = 14; i < pkt_size; i++)
5669                 packet[i] = (unsigned char) (i & 0xff);
5670
5671         if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5672                 dev_kfree_skb(skb);
5673                 return -EIO;
5674         }
5675         map = skb_shinfo(skb)->dma_head;
5676
5677         REG_WR(bp, BNX2_HC_COMMAND,
5678                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5679
5680         REG_RD(bp, BNX2_HC_COMMAND);
5681
5682         udelay(5);
5683         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5684
5685         num_pkts = 0;
5686
5687         txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5688
5689         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5690         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5691         txbd->tx_bd_mss_nbytes = pkt_size;
5692         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5693
5694         num_pkts++;
5695         txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5696         txr->tx_prod_bseq += pkt_size;
5697
5698         REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5699         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5700
5701         udelay(100);
5702
5703         REG_WR(bp, BNX2_HC_COMMAND,
5704                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5705
5706         REG_RD(bp, BNX2_HC_COMMAND);
5707
5708         udelay(5);
5709
5710         skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5711         dev_kfree_skb(skb);
5712
5713         if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5714                 goto loopback_test_done;
5715
5716         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5717         if (rx_idx != rx_start_idx + num_pkts) {
5718                 goto loopback_test_done;
5719         }
5720
5721         rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5722         rx_skb = rx_buf->skb;
5723
5724         rx_hdr = (struct l2_fhdr *) rx_skb->data;
5725         skb_reserve(rx_skb, BNX2_RX_OFFSET);
5726
5727         pci_dma_sync_single_for_cpu(bp->pdev,
5728                 pci_unmap_addr(rx_buf, mapping),
5729                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5730
5731         if (rx_hdr->l2_fhdr_status &
5732                 (L2_FHDR_ERRORS_BAD_CRC |
5733                 L2_FHDR_ERRORS_PHY_DECODE |
5734                 L2_FHDR_ERRORS_ALIGNMENT |
5735                 L2_FHDR_ERRORS_TOO_SHORT |
5736                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5737
5738                 goto loopback_test_done;
5739         }
5740
5741         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5742                 goto loopback_test_done;
5743         }
5744
5745         for (i = 14; i < pkt_size; i++) {
5746                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5747                         goto loopback_test_done;
5748                 }
5749         }
5750
5751         ret = 0;
5752
5753 loopback_test_done:
5754         bp->loopback = 0;
5755         return ret;
5756 }
5757
5758 #define BNX2_MAC_LOOPBACK_FAILED        1
5759 #define BNX2_PHY_LOOPBACK_FAILED        2
5760 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5761                                          BNX2_PHY_LOOPBACK_FAILED)
5762
5763 static int
5764 bnx2_test_loopback(struct bnx2 *bp)
5765 {
5766         int rc = 0;
5767
5768         if (!netif_running(bp->dev))
5769                 return BNX2_LOOPBACK_FAILED;
5770
5771         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5772         spin_lock_bh(&bp->phy_lock);
5773         bnx2_init_phy(bp, 1);
5774         spin_unlock_bh(&bp->phy_lock);
5775         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5776                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5777         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5778                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5779         return rc;
5780 }
5781
5782 #define NVRAM_SIZE 0x200
5783 #define CRC32_RESIDUAL 0xdebb20e3
5784
5785 static int
5786 bnx2_test_nvram(struct bnx2 *bp)
5787 {
5788         __be32 buf[NVRAM_SIZE / 4];
5789         u8 *data = (u8 *) buf;
5790         int rc = 0;
5791         u32 magic, csum;
5792
5793         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5794                 goto test_nvram_done;
5795
5796         magic = be32_to_cpu(buf[0]);
5797         if (magic != 0x669955aa) {
5798                 rc = -ENODEV;
5799                 goto test_nvram_done;
5800         }
5801
5802         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5803                 goto test_nvram_done;
5804
5805         csum = ether_crc_le(0x100, data);
5806         if (csum != CRC32_RESIDUAL) {
5807                 rc = -ENODEV;
5808                 goto test_nvram_done;
5809         }
5810
5811         csum = ether_crc_le(0x100, data + 0x100);
5812         if (csum != CRC32_RESIDUAL) {
5813                 rc = -ENODEV;
5814         }
5815
5816 test_nvram_done:
5817         return rc;
5818 }
5819
5820 static int
5821 bnx2_test_link(struct bnx2 *bp)
5822 {
5823         u32 bmsr;
5824
5825         if (!netif_running(bp->dev))
5826                 return -ENODEV;
5827
5828         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5829                 if (bp->link_up)
5830                         return 0;
5831                 return -ENODEV;
5832         }
5833         spin_lock_bh(&bp->phy_lock);
5834         bnx2_enable_bmsr1(bp);
5835         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5836         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5837         bnx2_disable_bmsr1(bp);
5838         spin_unlock_bh(&bp->phy_lock);
5839
5840         if (bmsr & BMSR_LSTATUS) {
5841                 return 0;
5842         }
5843         return -ENODEV;
5844 }
5845
5846 static int
5847 bnx2_test_intr(struct bnx2 *bp)
5848 {
5849         int i;
5850         u16 status_idx;
5851
5852         if (!netif_running(bp->dev))
5853                 return -ENODEV;
5854
5855         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5856
5857         /* This register is not touched during run-time. */
5858         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5859         REG_RD(bp, BNX2_HC_COMMAND);
5860
5861         for (i = 0; i < 10; i++) {
5862                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5863                         status_idx) {
5864
5865                         break;
5866                 }
5867
5868                 msleep_interruptible(10);
5869         }
5870         if (i < 10)
5871                 return 0;
5872
5873         return -ENODEV;
5874 }
5875
5876 /* Determining link for parallel detection. */
5877 static int
5878 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5879 {
5880         u32 mode_ctl, an_dbg, exp;
5881
5882         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5883                 return 0;
5884
5885         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5886         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5887
5888         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5889                 return 0;
5890
5891         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5892         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5893         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5894
5895         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5896                 return 0;
5897
5898         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5899         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5900         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5901
5902         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5903                 return 0;
5904
5905         return 1;
5906 }
5907
5908 static void
5909 bnx2_5706_serdes_timer(struct bnx2 *bp)
5910 {
5911         int check_link = 1;
5912
5913         spin_lock(&bp->phy_lock);
5914         if (bp->serdes_an_pending) {
5915                 bp->serdes_an_pending--;
5916                 check_link = 0;
5917         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5918                 u32 bmcr;
5919
5920                 bp->current_interval = BNX2_TIMER_INTERVAL;
5921
5922                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5923
5924                 if (bmcr & BMCR_ANENABLE) {
5925                         if (bnx2_5706_serdes_has_link(bp)) {
5926                                 bmcr &= ~BMCR_ANENABLE;
5927                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5928                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5929                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5930                         }
5931                 }
5932         }
5933         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5934                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5935                 u32 phy2;
5936
5937                 bnx2_write_phy(bp, 0x17, 0x0f01);
5938                 bnx2_read_phy(bp, 0x15, &phy2);
5939                 if (phy2 & 0x20) {
5940                         u32 bmcr;
5941
5942                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5943                         bmcr |= BMCR_ANENABLE;
5944                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5945
5946                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5947                 }
5948         } else
5949                 bp->current_interval = BNX2_TIMER_INTERVAL;
5950
5951         if (check_link) {
5952                 u32 val;
5953
5954                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5955                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5956                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5957
5958                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5959                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5960                                 bnx2_5706s_force_link_dn(bp, 1);
5961                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5962                         } else
5963                                 bnx2_set_link(bp);
5964                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5965                         bnx2_set_link(bp);
5966         }
5967         spin_unlock(&bp->phy_lock);
5968 }
5969
5970 static void
5971 bnx2_5708_serdes_timer(struct bnx2 *bp)
5972 {
5973         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5974                 return;
5975
5976         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5977                 bp->serdes_an_pending = 0;
5978                 return;
5979         }
5980
5981         spin_lock(&bp->phy_lock);
5982         if (bp->serdes_an_pending)
5983                 bp->serdes_an_pending--;
5984         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5985                 u32 bmcr;
5986
5987                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5988                 if (bmcr & BMCR_ANENABLE) {
5989                         bnx2_enable_forced_2g5(bp);
5990                         bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
5991                 } else {
5992                         bnx2_disable_forced_2g5(bp);
5993                         bp->serdes_an_pending = 2;
5994                         bp->current_interval = BNX2_TIMER_INTERVAL;
5995                 }
5996
5997         } else
5998                 bp->current_interval = BNX2_TIMER_INTERVAL;
5999
6000         spin_unlock(&bp->phy_lock);
6001 }
6002
6003 static void
6004 bnx2_timer(unsigned long data)
6005 {
6006         struct bnx2 *bp = (struct bnx2 *) data;
6007
6008         if (!netif_running(bp->dev))
6009                 return;
6010
6011         if (atomic_read(&bp->intr_sem) != 0)
6012                 goto bnx2_restart_timer;
6013
6014         if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6015              BNX2_FLAG_USING_MSI)
6016                 bnx2_chk_missed_msi(bp);
6017
6018         bnx2_send_heart_beat(bp);
6019
6020         bp->stats_blk->stat_FwRxDrop =
6021                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6022
6023         /* workaround occasional corrupted counters */
6024         if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
6025                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6026                                             BNX2_HC_COMMAND_STATS_NOW);
6027
6028         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6029                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6030                         bnx2_5706_serdes_timer(bp);
6031                 else
6032                         bnx2_5708_serdes_timer(bp);
6033         }
6034
6035 bnx2_restart_timer:
6036         mod_timer(&bp->timer, jiffies + bp->current_interval);
6037 }
6038
6039 static int
6040 bnx2_request_irq(struct bnx2 *bp)
6041 {
6042         unsigned long flags;
6043         struct bnx2_irq *irq;
6044         int rc = 0, i;
6045
6046         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6047                 flags = 0;
6048         else
6049                 flags = IRQF_SHARED;
6050
6051         for (i = 0; i < bp->irq_nvecs; i++) {
6052                 irq = &bp->irq_tbl[i];
6053                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6054                                  &bp->bnx2_napi[i]);
6055                 if (rc)
6056                         break;
6057                 irq->requested = 1;
6058         }
6059         return rc;
6060 }
6061
6062 static void
6063 bnx2_free_irq(struct bnx2 *bp)
6064 {
6065         struct bnx2_irq *irq;
6066         int i;
6067
6068         for (i = 0; i < bp->irq_nvecs; i++) {
6069                 irq = &bp->irq_tbl[i];
6070                 if (irq->requested)
6071                         free_irq(irq->vector, &bp->bnx2_napi[i]);
6072                 irq->requested = 0;
6073         }
6074         if (bp->flags & BNX2_FLAG_USING_MSI)
6075                 pci_disable_msi(bp->pdev);
6076         else if (bp->flags & BNX2_FLAG_USING_MSIX)
6077                 pci_disable_msix(bp->pdev);
6078
6079         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6080 }
6081
6082 static void
6083 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6084 {
6085         int i, rc;
6086         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6087         struct net_device *dev = bp->dev;
6088         const int len = sizeof(bp->irq_tbl[0].name);
6089
6090         bnx2_setup_msix_tbl(bp);
6091         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6092         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6093         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6094
6095         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6096                 msix_ent[i].entry = i;
6097                 msix_ent[i].vector = 0;
6098         }
6099
6100         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6101         if (rc != 0)
6102                 return;
6103
6104         bp->irq_nvecs = msix_vecs;
6105         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6106         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6107                 bp->irq_tbl[i].vector = msix_ent[i].vector;
6108                 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6109                 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6110         }
6111 }
6112
6113 static void
6114 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6115 {
6116         int cpus = num_online_cpus();
6117         int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6118
6119         bp->irq_tbl[0].handler = bnx2_interrupt;
6120         strcpy(bp->irq_tbl[0].name, bp->dev->name);
6121         bp->irq_nvecs = 1;
6122         bp->irq_tbl[0].vector = bp->pdev->irq;
6123
6124         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
6125                 bnx2_enable_msix(bp, msix_vecs);
6126
6127         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6128             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6129                 if (pci_enable_msi(bp->pdev) == 0) {
6130                         bp->flags |= BNX2_FLAG_USING_MSI;
6131                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6132                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6133                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6134                         } else
6135                                 bp->irq_tbl[0].handler = bnx2_msi;
6136
6137                         bp->irq_tbl[0].vector = bp->pdev->irq;
6138                 }
6139         }
6140
6141         bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6142         bp->dev->real_num_tx_queues = bp->num_tx_rings;
6143
6144         bp->num_rx_rings = bp->irq_nvecs;
6145 }
6146
6147 /* Called with rtnl_lock */
6148 static int
6149 bnx2_open(struct net_device *dev)
6150 {
6151         struct bnx2 *bp = netdev_priv(dev);
6152         int rc;
6153
6154         netif_carrier_off(dev);
6155
6156         bnx2_set_power_state(bp, PCI_D0);
6157         bnx2_disable_int(bp);
6158
6159         bnx2_setup_int_mode(bp, disable_msi);
6160         bnx2_napi_enable(bp);
6161         rc = bnx2_alloc_mem(bp);
6162         if (rc)
6163                 goto open_err;
6164
6165         rc = bnx2_request_irq(bp);
6166         if (rc)
6167                 goto open_err;
6168
6169         rc = bnx2_init_nic(bp, 1);
6170         if (rc)
6171                 goto open_err;
6172
6173         mod_timer(&bp->timer, jiffies + bp->current_interval);
6174
6175         atomic_set(&bp->intr_sem, 0);
6176
6177         bnx2_enable_int(bp);
6178
6179         if (bp->flags & BNX2_FLAG_USING_MSI) {
6180                 /* Test MSI to make sure it is working
6181                  * If MSI test fails, go back to INTx mode
6182                  */
6183                 if (bnx2_test_intr(bp) != 0) {
6184                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
6185                                " using MSI, switching to INTx mode. Please"
6186                                " report this failure to the PCI maintainer"
6187                                " and include system chipset information.\n",
6188                                bp->dev->name);
6189
6190                         bnx2_disable_int(bp);
6191                         bnx2_free_irq(bp);
6192
6193                         bnx2_setup_int_mode(bp, 1);
6194
6195                         rc = bnx2_init_nic(bp, 0);
6196
6197                         if (!rc)
6198                                 rc = bnx2_request_irq(bp);
6199
6200                         if (rc) {
6201                                 del_timer_sync(&bp->timer);
6202                                 goto open_err;
6203                         }
6204                         bnx2_enable_int(bp);
6205                 }
6206         }
6207         if (bp->flags & BNX2_FLAG_USING_MSI)
6208                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
6209         else if (bp->flags & BNX2_FLAG_USING_MSIX)
6210                 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
6211
6212         netif_tx_start_all_queues(dev);
6213
6214         return 0;
6215
6216 open_err:
6217         bnx2_napi_disable(bp);
6218         bnx2_free_skbs(bp);
6219         bnx2_free_irq(bp);
6220         bnx2_free_mem(bp);
6221         return rc;
6222 }
6223
6224 static void
6225 bnx2_reset_task(struct work_struct *work)
6226 {
6227         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6228
6229         if (!netif_running(bp->dev))
6230                 return;
6231
6232         bnx2_netif_stop(bp);
6233
6234         bnx2_init_nic(bp, 1);
6235
6236         atomic_set(&bp->intr_sem, 1);
6237         bnx2_netif_start(bp);
6238 }
6239
6240 static void
6241 bnx2_tx_timeout(struct net_device *dev)
6242 {
6243         struct bnx2 *bp = netdev_priv(dev);
6244
6245         /* This allows the netif to be shutdown gracefully before resetting */
6246         schedule_work(&bp->reset_task);
6247 }
6248
6249 #ifdef BCM_VLAN
6250 /* Called with rtnl_lock */
6251 static void
6252 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6253 {
6254         struct bnx2 *bp = netdev_priv(dev);
6255
6256         bnx2_netif_stop(bp);
6257
6258         bp->vlgrp = vlgrp;
6259         bnx2_set_rx_mode(dev);
6260         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6261                 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6262
6263         bnx2_netif_start(bp);
6264 }
6265 #endif
6266
6267 /* Called with netif_tx_lock.
6268  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6269  * netif_wake_queue().
6270  */
6271 static int
6272 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6273 {
6274         struct bnx2 *bp = netdev_priv(dev);
6275         dma_addr_t mapping;
6276         struct tx_bd *txbd;
6277         struct sw_tx_bd *tx_buf;
6278         u32 len, vlan_tag_flags, last_frag, mss;
6279         u16 prod, ring_prod;
6280         int i;
6281         struct bnx2_napi *bnapi;
6282         struct bnx2_tx_ring_info *txr;
6283         struct netdev_queue *txq;
6284         struct skb_shared_info *sp;
6285
6286         /*  Determine which tx ring we will be placed on */
6287         i = skb_get_queue_mapping(skb);
6288         bnapi = &bp->bnx2_napi[i];
6289         txr = &bnapi->tx_ring;
6290         txq = netdev_get_tx_queue(dev, i);
6291
6292         if (unlikely(bnx2_tx_avail(bp, txr) <
6293             (skb_shinfo(skb)->nr_frags + 1))) {
6294                 netif_tx_stop_queue(txq);
6295                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6296                         dev->name);
6297
6298                 return NETDEV_TX_BUSY;
6299         }
6300         len = skb_headlen(skb);
6301         prod = txr->tx_prod;
6302         ring_prod = TX_RING_IDX(prod);
6303
6304         vlan_tag_flags = 0;
6305         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6306                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6307         }
6308
6309 #ifdef BCM_VLAN
6310         if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6311                 vlan_tag_flags |=
6312                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6313         }
6314 #endif
6315         if ((mss = skb_shinfo(skb)->gso_size)) {
6316                 u32 tcp_opt_len;
6317                 struct iphdr *iph;
6318
6319                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6320
6321                 tcp_opt_len = tcp_optlen(skb);
6322
6323                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6324                         u32 tcp_off = skb_transport_offset(skb) -
6325                                       sizeof(struct ipv6hdr) - ETH_HLEN;
6326
6327                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6328                                           TX_BD_FLAGS_SW_FLAGS;
6329                         if (likely(tcp_off == 0))
6330                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6331                         else {
6332                                 tcp_off >>= 3;
6333                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
6334                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
6335                                                   ((tcp_off & 0x10) <<
6336                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
6337                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6338                         }
6339                 } else {
6340                         iph = ip_hdr(skb);
6341                         if (tcp_opt_len || (iph->ihl > 5)) {
6342                                 vlan_tag_flags |= ((iph->ihl - 5) +
6343                                                    (tcp_opt_len >> 2)) << 8;
6344                         }
6345                 }
6346         } else
6347                 mss = 0;
6348
6349         if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
6350                 dev_kfree_skb(skb);
6351                 return NETDEV_TX_OK;
6352         }
6353
6354         sp = skb_shinfo(skb);
6355         mapping = sp->dma_head;
6356
6357         tx_buf = &txr->tx_buf_ring[ring_prod];
6358         tx_buf->skb = skb;
6359
6360         txbd = &txr->tx_desc_ring[ring_prod];
6361
6362         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6363         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6364         txbd->tx_bd_mss_nbytes = len | (mss << 16);
6365         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6366
6367         last_frag = skb_shinfo(skb)->nr_frags;
6368         tx_buf->nr_frags = last_frag;
6369         tx_buf->is_gso = skb_is_gso(skb);
6370
6371         for (i = 0; i < last_frag; i++) {
6372                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6373
6374                 prod = NEXT_TX_BD(prod);
6375                 ring_prod = TX_RING_IDX(prod);
6376                 txbd = &txr->tx_desc_ring[ring_prod];
6377
6378                 len = frag->size;
6379                 mapping = sp->dma_maps[i];
6380
6381                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6382                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6383                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6384                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6385
6386         }
6387         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6388
6389         prod = NEXT_TX_BD(prod);
6390         txr->tx_prod_bseq += skb->len;
6391
6392         REG_WR16(bp, txr->tx_bidx_addr, prod);
6393         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6394
6395         mmiowb();
6396
6397         txr->tx_prod = prod;
6398
6399         if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6400                 netif_tx_stop_queue(txq);
6401                 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6402                         netif_tx_wake_queue(txq);
6403         }
6404
6405         return NETDEV_TX_OK;
6406 }
6407
6408 /* Called with rtnl_lock */
6409 static int
6410 bnx2_close(struct net_device *dev)
6411 {
6412         struct bnx2 *bp = netdev_priv(dev);
6413
6414         cancel_work_sync(&bp->reset_task);
6415
6416         bnx2_disable_int_sync(bp);
6417         bnx2_napi_disable(bp);
6418         del_timer_sync(&bp->timer);
6419         bnx2_shutdown_chip(bp);
6420         bnx2_free_irq(bp);
6421         bnx2_free_skbs(bp);
6422         bnx2_free_mem(bp);
6423         bp->link_up = 0;
6424         netif_carrier_off(bp->dev);
6425         bnx2_set_power_state(bp, PCI_D3hot);
6426         return 0;
6427 }
6428
6429 #define GET_NET_STATS64(ctr)                                    \
6430         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
6431         (unsigned long) (ctr##_lo)
6432
6433 #define GET_NET_STATS32(ctr)            \
6434         (ctr##_lo)
6435
6436 #if (BITS_PER_LONG == 64)
6437 #define GET_NET_STATS   GET_NET_STATS64
6438 #else
6439 #define GET_NET_STATS   GET_NET_STATS32
6440 #endif
6441
6442 static struct net_device_stats *
6443 bnx2_get_stats(struct net_device *dev)
6444 {
6445         struct bnx2 *bp = netdev_priv(dev);
6446         struct statistics_block *stats_blk = bp->stats_blk;
6447         struct net_device_stats *net_stats = &dev->stats;
6448
6449         if (bp->stats_blk == NULL) {
6450                 return net_stats;
6451         }
6452         net_stats->rx_packets =
6453                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6454                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6455                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6456
6457         net_stats->tx_packets =
6458                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6459                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6460                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6461
6462         net_stats->rx_bytes =
6463                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6464
6465         net_stats->tx_bytes =
6466                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6467
6468         net_stats->multicast =
6469                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6470
6471         net_stats->collisions =
6472                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6473
6474         net_stats->rx_length_errors =
6475                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6476                 stats_blk->stat_EtherStatsOverrsizePkts);
6477
6478         net_stats->rx_over_errors =
6479                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6480
6481         net_stats->rx_frame_errors =
6482                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6483
6484         net_stats->rx_crc_errors =
6485                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6486
6487         net_stats->rx_errors = net_stats->rx_length_errors +
6488                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6489                 net_stats->rx_crc_errors;
6490
6491         net_stats->tx_aborted_errors =
6492                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6493                 stats_blk->stat_Dot3StatsLateCollisions);
6494
6495         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6496             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6497                 net_stats->tx_carrier_errors = 0;
6498         else {
6499                 net_stats->tx_carrier_errors =
6500                         (unsigned long)
6501                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
6502         }
6503
6504         net_stats->tx_errors =
6505                 (unsigned long)
6506                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6507                 +
6508                 net_stats->tx_aborted_errors +
6509                 net_stats->tx_carrier_errors;
6510
6511         net_stats->rx_missed_errors =
6512                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6513                 stats_blk->stat_FwRxDrop);
6514
6515         return net_stats;
6516 }
6517
6518 /* All ethtool functions called with rtnl_lock */
6519
6520 static int
6521 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6522 {
6523         struct bnx2 *bp = netdev_priv(dev);
6524         int support_serdes = 0, support_copper = 0;
6525
6526         cmd->supported = SUPPORTED_Autoneg;
6527         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6528                 support_serdes = 1;
6529                 support_copper = 1;
6530         } else if (bp->phy_port == PORT_FIBRE)
6531                 support_serdes = 1;
6532         else
6533                 support_copper = 1;
6534
6535         if (support_serdes) {
6536                 cmd->supported |= SUPPORTED_1000baseT_Full |
6537                         SUPPORTED_FIBRE;
6538                 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6539                         cmd->supported |= SUPPORTED_2500baseX_Full;
6540
6541         }
6542         if (support_copper) {
6543                 cmd->supported |= SUPPORTED_10baseT_Half |
6544                         SUPPORTED_10baseT_Full |
6545                         SUPPORTED_100baseT_Half |
6546                         SUPPORTED_100baseT_Full |
6547                         SUPPORTED_1000baseT_Full |
6548                         SUPPORTED_TP;
6549
6550         }
6551
6552         spin_lock_bh(&bp->phy_lock);
6553         cmd->port = bp->phy_port;
6554         cmd->advertising = bp->advertising;
6555
6556         if (bp->autoneg & AUTONEG_SPEED) {
6557                 cmd->autoneg = AUTONEG_ENABLE;
6558         }
6559         else {
6560                 cmd->autoneg = AUTONEG_DISABLE;
6561         }
6562
6563         if (netif_carrier_ok(dev)) {
6564                 cmd->speed = bp->line_speed;
6565                 cmd->duplex = bp->duplex;
6566         }
6567         else {
6568                 cmd->speed = -1;
6569                 cmd->duplex = -1;
6570         }
6571         spin_unlock_bh(&bp->phy_lock);
6572
6573         cmd->transceiver = XCVR_INTERNAL;
6574         cmd->phy_address = bp->phy_addr;
6575
6576         return 0;
6577 }
6578
6579 static int
6580 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6581 {
6582         struct bnx2 *bp = netdev_priv(dev);
6583         u8 autoneg = bp->autoneg;
6584         u8 req_duplex = bp->req_duplex;
6585         u16 req_line_speed = bp->req_line_speed;
6586         u32 advertising = bp->advertising;
6587         int err = -EINVAL;
6588
6589         spin_lock_bh(&bp->phy_lock);
6590
6591         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6592                 goto err_out_unlock;
6593
6594         if (cmd->port != bp->phy_port &&
6595             !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6596                 goto err_out_unlock;
6597
6598         /* If device is down, we can store the settings only if the user
6599          * is setting the currently active port.
6600          */
6601         if (!netif_running(dev) && cmd->port != bp->phy_port)
6602                 goto err_out_unlock;
6603
6604         if (cmd->autoneg == AUTONEG_ENABLE) {
6605                 autoneg |= AUTONEG_SPEED;
6606
6607                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6608
6609                 /* allow advertising 1 speed */
6610                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6611                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
6612                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
6613                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
6614
6615                         if (cmd->port == PORT_FIBRE)
6616                                 goto err_out_unlock;
6617
6618                         advertising = cmd->advertising;
6619
6620                 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6621                         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6622                             (cmd->port == PORT_TP))
6623                                 goto err_out_unlock;
6624                 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6625                         advertising = cmd->advertising;
6626                 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6627                         goto err_out_unlock;
6628                 else {
6629                         if (cmd->port == PORT_FIBRE)
6630                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6631                         else
6632                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
6633                 }
6634                 advertising |= ADVERTISED_Autoneg;
6635         }
6636         else {
6637                 if (cmd->port == PORT_FIBRE) {
6638                         if ((cmd->speed != SPEED_1000 &&
6639                              cmd->speed != SPEED_2500) ||
6640                             (cmd->duplex != DUPLEX_FULL))
6641                                 goto err_out_unlock;
6642
6643                         if (cmd->speed == SPEED_2500 &&
6644                             !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6645                                 goto err_out_unlock;
6646                 }
6647                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6648                         goto err_out_unlock;
6649
6650                 autoneg &= ~AUTONEG_SPEED;
6651                 req_line_speed = cmd->speed;
6652                 req_duplex = cmd->duplex;
6653                 advertising = 0;
6654         }
6655
6656         bp->autoneg = autoneg;
6657         bp->advertising = advertising;
6658         bp->req_line_speed = req_line_speed;
6659         bp->req_duplex = req_duplex;
6660
6661         err = 0;
6662         /* If device is down, the new settings will be picked up when it is
6663          * brought up.
6664          */
6665         if (netif_running(dev))
6666                 err = bnx2_setup_phy(bp, cmd->port);
6667
6668 err_out_unlock:
6669         spin_unlock_bh(&bp->phy_lock);
6670
6671         return err;
6672 }
6673
6674 static void
6675 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6676 {
6677         struct bnx2 *bp = netdev_priv(dev);
6678
6679         strcpy(info->driver, DRV_MODULE_NAME);
6680         strcpy(info->version, DRV_MODULE_VERSION);
6681         strcpy(info->bus_info, pci_name(bp->pdev));
6682         strcpy(info->fw_version, bp->fw_version);
6683 }
6684
6685 #define BNX2_REGDUMP_LEN                (32 * 1024)
6686
6687 static int
6688 bnx2_get_regs_len(struct net_device *dev)
6689 {
6690         return BNX2_REGDUMP_LEN;
6691 }
6692
6693 static void
6694 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6695 {
6696         u32 *p = _p, i, offset;
6697         u8 *orig_p = _p;
6698         struct bnx2 *bp = netdev_priv(dev);
6699         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6700                                  0x0800, 0x0880, 0x0c00, 0x0c10,
6701                                  0x0c30, 0x0d08, 0x1000, 0x101c,
6702                                  0x1040, 0x1048, 0x1080, 0x10a4,
6703                                  0x1400, 0x1490, 0x1498, 0x14f0,
6704                                  0x1500, 0x155c, 0x1580, 0x15dc,
6705                                  0x1600, 0x1658, 0x1680, 0x16d8,
6706                                  0x1800, 0x1820, 0x1840, 0x1854,
6707                                  0x1880, 0x1894, 0x1900, 0x1984,
6708                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6709                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
6710                                  0x2000, 0x2030, 0x23c0, 0x2400,
6711                                  0x2800, 0x2820, 0x2830, 0x2850,
6712                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
6713                                  0x3c00, 0x3c94, 0x4000, 0x4010,
6714                                  0x4080, 0x4090, 0x43c0, 0x4458,
6715                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
6716                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
6717                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
6718                                  0x5fc0, 0x6000, 0x6400, 0x6428,
6719                                  0x6800, 0x6848, 0x684c, 0x6860,
6720                                  0x6888, 0x6910, 0x8000 };
6721
6722         regs->version = 0;
6723
6724         memset(p, 0, BNX2_REGDUMP_LEN);
6725
6726         if (!netif_running(bp->dev))
6727                 return;
6728
6729         i = 0;
6730         offset = reg_boundaries[0];
6731         p += offset;
6732         while (offset < BNX2_REGDUMP_LEN) {
6733                 *p++ = REG_RD(bp, offset);
6734                 offset += 4;
6735                 if (offset == reg_boundaries[i + 1]) {
6736                         offset = reg_boundaries[i + 2];
6737                         p = (u32 *) (orig_p + offset);
6738                         i += 2;
6739                 }
6740         }
6741 }
6742
6743 static void
6744 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6745 {
6746         struct bnx2 *bp = netdev_priv(dev);
6747
6748         if (bp->flags & BNX2_FLAG_NO_WOL) {
6749                 wol->supported = 0;
6750                 wol->wolopts = 0;
6751         }
6752         else {
6753                 wol->supported = WAKE_MAGIC;
6754                 if (bp->wol)
6755                         wol->wolopts = WAKE_MAGIC;
6756                 else
6757                         wol->wolopts = 0;
6758         }
6759         memset(&wol->sopass, 0, sizeof(wol->sopass));
6760 }
6761
6762 static int
6763 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6764 {
6765         struct bnx2 *bp = netdev_priv(dev);
6766
6767         if (wol->wolopts & ~WAKE_MAGIC)
6768                 return -EINVAL;
6769
6770         if (wol->wolopts & WAKE_MAGIC) {
6771                 if (bp->flags & BNX2_FLAG_NO_WOL)
6772                         return -EINVAL;
6773
6774                 bp->wol = 1;
6775         }
6776         else {
6777                 bp->wol = 0;
6778         }
6779         return 0;
6780 }
6781
6782 static int
6783 bnx2_nway_reset(struct net_device *dev)
6784 {
6785         struct bnx2 *bp = netdev_priv(dev);
6786         u32 bmcr;
6787
6788         if (!netif_running(dev))
6789                 return -EAGAIN;
6790
6791         if (!(bp->autoneg & AUTONEG_SPEED)) {
6792                 return -EINVAL;
6793         }
6794
6795         spin_lock_bh(&bp->phy_lock);
6796
6797         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6798                 int rc;
6799
6800                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6801                 spin_unlock_bh(&bp->phy_lock);
6802                 return rc;
6803         }
6804
6805         /* Force a link down visible on the other side */
6806         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6807                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6808                 spin_unlock_bh(&bp->phy_lock);
6809
6810                 msleep(20);
6811
6812                 spin_lock_bh(&bp->phy_lock);
6813
6814                 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6815                 bp->serdes_an_pending = 1;
6816                 mod_timer(&bp->timer, jiffies + bp->current_interval);
6817         }
6818
6819         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6820         bmcr &= ~BMCR_LOOPBACK;
6821         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6822
6823         spin_unlock_bh(&bp->phy_lock);
6824
6825         return 0;
6826 }
6827
6828 static int
6829 bnx2_get_eeprom_len(struct net_device *dev)
6830 {
6831         struct bnx2 *bp = netdev_priv(dev);
6832
6833         if (bp->flash_info == NULL)
6834                 return 0;
6835
6836         return (int) bp->flash_size;
6837 }
6838
6839 static int
6840 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6841                 u8 *eebuf)
6842 {
6843         struct bnx2 *bp = netdev_priv(dev);
6844         int rc;
6845
6846         if (!netif_running(dev))
6847                 return -EAGAIN;
6848
6849         /* parameters already validated in ethtool_get_eeprom */
6850
6851         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6852
6853         return rc;
6854 }
6855
6856 static int
6857 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6858                 u8 *eebuf)
6859 {
6860         struct bnx2 *bp = netdev_priv(dev);
6861         int rc;
6862
6863         if (!netif_running(dev))
6864                 return -EAGAIN;
6865
6866         /* parameters already validated in ethtool_set_eeprom */
6867
6868         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6869
6870         return rc;
6871 }
6872
6873 static int
6874 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6875 {
6876         struct bnx2 *bp = netdev_priv(dev);
6877
6878         memset(coal, 0, sizeof(struct ethtool_coalesce));
6879
6880         coal->rx_coalesce_usecs = bp->rx_ticks;
6881         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6882         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6883         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6884
6885         coal->tx_coalesce_usecs = bp->tx_ticks;
6886         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6887         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6888         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6889
6890         coal->stats_block_coalesce_usecs = bp->stats_ticks;
6891
6892         return 0;
6893 }
6894
6895 static int
6896 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6897 {
6898         struct bnx2 *bp = netdev_priv(dev);
6899
6900         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6901         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6902
6903         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6904         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6905
6906         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6907         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6908
6909         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6910         if (bp->rx_quick_cons_trip_int > 0xff)
6911                 bp->rx_quick_cons_trip_int = 0xff;
6912
6913         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6914         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6915
6916         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6917         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6918
6919         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6920         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6921
6922         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6923         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6924                 0xff;
6925
6926         bp->stats_ticks = coal->stats_block_coalesce_usecs;
6927         if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6928                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6929                         bp->stats_ticks = USEC_PER_SEC;
6930         }
6931         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6932                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6933         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6934
6935         if (netif_running(bp->dev)) {
6936                 bnx2_netif_stop(bp);
6937                 bnx2_init_nic(bp, 0);
6938                 bnx2_netif_start(bp);
6939         }
6940
6941         return 0;
6942 }
6943
6944 static void
6945 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6946 {
6947         struct bnx2 *bp = netdev_priv(dev);
6948
6949         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6950         ering->rx_mini_max_pending = 0;
6951         ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6952
6953         ering->rx_pending = bp->rx_ring_size;
6954         ering->rx_mini_pending = 0;
6955         ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6956
6957         ering->tx_max_pending = MAX_TX_DESC_CNT;
6958         ering->tx_pending = bp->tx_ring_size;
6959 }
6960
6961 static int
6962 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6963 {
6964         if (netif_running(bp->dev)) {
6965                 bnx2_netif_stop(bp);
6966                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6967                 bnx2_free_skbs(bp);
6968                 bnx2_free_mem(bp);
6969         }
6970
6971         bnx2_set_rx_ring_size(bp, rx);
6972         bp->tx_ring_size = tx;
6973
6974         if (netif_running(bp->dev)) {
6975                 int rc;
6976
6977                 rc = bnx2_alloc_mem(bp);
6978                 if (rc)
6979                         return rc;
6980                 bnx2_init_nic(bp, 0);
6981                 bnx2_netif_start(bp);
6982         }
6983         return 0;
6984 }
6985
6986 static int
6987 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6988 {
6989         struct bnx2 *bp = netdev_priv(dev);
6990         int rc;
6991
6992         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6993                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6994                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6995
6996                 return -EINVAL;
6997         }
6998         rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6999         return rc;
7000 }
7001
7002 static void
7003 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7004 {
7005         struct bnx2 *bp = netdev_priv(dev);
7006
7007         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7008         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7009         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7010 }
7011
7012 static int
7013 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7014 {
7015         struct bnx2 *bp = netdev_priv(dev);
7016
7017         bp->req_flow_ctrl = 0;
7018         if (epause->rx_pause)
7019                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7020         if (epause->tx_pause)
7021                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7022
7023         if (epause->autoneg) {
7024                 bp->autoneg |= AUTONEG_FLOW_CTRL;
7025         }
7026         else {
7027                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7028         }
7029
7030         if (netif_running(dev)) {
7031                 spin_lock_bh(&bp->phy_lock);
7032                 bnx2_setup_phy(bp, bp->phy_port);
7033                 spin_unlock_bh(&bp->phy_lock);
7034         }
7035
7036         return 0;
7037 }
7038
7039 static u32
7040 bnx2_get_rx_csum(struct net_device *dev)
7041 {
7042         struct bnx2 *bp = netdev_priv(dev);
7043
7044         return bp->rx_csum;
7045 }
7046
7047 static int
7048 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7049 {
7050         struct bnx2 *bp = netdev_priv(dev);
7051
7052         bp->rx_csum = data;
7053         return 0;
7054 }
7055
7056 static int
7057 bnx2_set_tso(struct net_device *dev, u32 data)
7058 {
7059         struct bnx2 *bp = netdev_priv(dev);
7060
7061         if (data) {
7062                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7063                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7064                         dev->features |= NETIF_F_TSO6;
7065         } else
7066                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7067                                    NETIF_F_TSO_ECN);
7068         return 0;
7069 }
7070
7071 #define BNX2_NUM_STATS 46
7072
7073 static struct {
7074         char string[ETH_GSTRING_LEN];
7075 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
7076         { "rx_bytes" },
7077         { "rx_error_bytes" },
7078         { "tx_bytes" },
7079         { "tx_error_bytes" },
7080         { "rx_ucast_packets" },
7081         { "rx_mcast_packets" },
7082         { "rx_bcast_packets" },
7083         { "tx_ucast_packets" },
7084         { "tx_mcast_packets" },
7085         { "tx_bcast_packets" },
7086         { "tx_mac_errors" },
7087         { "tx_carrier_errors" },
7088         { "rx_crc_errors" },
7089         { "rx_align_errors" },
7090         { "tx_single_collisions" },
7091         { "tx_multi_collisions" },
7092         { "tx_deferred" },
7093         { "tx_excess_collisions" },
7094         { "tx_late_collisions" },
7095         { "tx_total_collisions" },
7096         { "rx_fragments" },
7097         { "rx_jabbers" },
7098         { "rx_undersize_packets" },
7099         { "rx_oversize_packets" },
7100         { "rx_64_byte_packets" },
7101         { "rx_65_to_127_byte_packets" },
7102         { "rx_128_to_255_byte_packets" },
7103         { "rx_256_to_511_byte_packets" },
7104         { "rx_512_to_1023_byte_packets" },
7105         { "rx_1024_to_1522_byte_packets" },
7106         { "rx_1523_to_9022_byte_packets" },
7107         { "tx_64_byte_packets" },
7108         { "tx_65_to_127_byte_packets" },
7109         { "tx_128_to_255_byte_packets" },
7110         { "tx_256_to_511_byte_packets" },
7111         { "tx_512_to_1023_byte_packets" },
7112         { "tx_1024_to_1522_byte_packets" },
7113         { "tx_1523_to_9022_byte_packets" },
7114         { "rx_xon_frames" },
7115         { "rx_xoff_frames" },
7116         { "tx_xon_frames" },
7117         { "tx_xoff_frames" },
7118         { "rx_mac_ctrl_frames" },
7119         { "rx_filtered_packets" },
7120         { "rx_discards" },
7121         { "rx_fw_discards" },
7122 };
7123
7124 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7125
7126 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7127     STATS_OFFSET32(stat_IfHCInOctets_hi),
7128     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7129     STATS_OFFSET32(stat_IfHCOutOctets_hi),
7130     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7131     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7132     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7133     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7134     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7135     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7136     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7137     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7138     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7139     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7140     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7141     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7142     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7143     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7144     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7145     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7146     STATS_OFFSET32(stat_EtherStatsCollisions),
7147     STATS_OFFSET32(stat_EtherStatsFragments),
7148     STATS_OFFSET32(stat_EtherStatsJabbers),
7149     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7150     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7151     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7152     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7153     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7154     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7155     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7156     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7157     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7158     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7159     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7160     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7161     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7162     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7163     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7164     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7165     STATS_OFFSET32(stat_XonPauseFramesReceived),
7166     STATS_OFFSET32(stat_XoffPauseFramesReceived),
7167     STATS_OFFSET32(stat_OutXonSent),
7168     STATS_OFFSET32(stat_OutXoffSent),
7169     STATS_OFFSET32(stat_MacControlFramesReceived),
7170     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7171     STATS_OFFSET32(stat_IfInMBUFDiscards),
7172     STATS_OFFSET32(stat_FwRxDrop),
7173 };
7174
7175 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7176  * skipped because of errata.
7177  */
7178 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7179         8,0,8,8,8,8,8,8,8,8,
7180         4,0,4,4,4,4,4,4,4,4,
7181         4,4,4,4,4,4,4,4,4,4,
7182         4,4,4,4,4,4,4,4,4,4,
7183         4,4,4,4,4,4,
7184 };
7185
7186 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7187         8,0,8,8,8,8,8,8,8,8,
7188         4,4,4,4,4,4,4,4,4,4,
7189         4,4,4,4,4,4,4,4,4,4,
7190         4,4,4,4,4,4,4,4,4,4,
7191         4,4,4,4,4,4,
7192 };
7193
7194 #define BNX2_NUM_TESTS 6
7195
7196 static struct {
7197         char string[ETH_GSTRING_LEN];
7198 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7199         { "register_test (offline)" },
7200         { "memory_test (offline)" },
7201         { "loopback_test (offline)" },
7202         { "nvram_test (online)" },
7203         { "interrupt_test (online)" },
7204         { "link_test (online)" },
7205 };
7206
7207 static int
7208 bnx2_get_sset_count(struct net_device *dev, int sset)
7209 {
7210         switch (sset) {
7211         case ETH_SS_TEST:
7212                 return BNX2_NUM_TESTS;
7213         case ETH_SS_STATS:
7214                 return BNX2_NUM_STATS;
7215         default:
7216                 return -EOPNOTSUPP;
7217         }
7218 }
7219
7220 static void
7221 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7222 {
7223         struct bnx2 *bp = netdev_priv(dev);
7224
7225         bnx2_set_power_state(bp, PCI_D0);
7226
7227         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7228         if (etest->flags & ETH_TEST_FL_OFFLINE) {
7229                 int i;
7230
7231                 bnx2_netif_stop(bp);
7232                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7233                 bnx2_free_skbs(bp);
7234
7235                 if (bnx2_test_registers(bp) != 0) {
7236                         buf[0] = 1;
7237                         etest->flags |= ETH_TEST_FL_FAILED;
7238                 }
7239                 if (bnx2_test_memory(bp) != 0) {
7240                         buf[1] = 1;
7241                         etest->flags |= ETH_TEST_FL_FAILED;
7242                 }
7243                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7244                         etest->flags |= ETH_TEST_FL_FAILED;
7245
7246                 if (!netif_running(bp->dev))
7247                         bnx2_shutdown_chip(bp);
7248                 else {
7249                         bnx2_init_nic(bp, 1);
7250                         bnx2_netif_start(bp);
7251                 }
7252
7253                 /* wait for link up */
7254                 for (i = 0; i < 7; i++) {
7255                         if (bp->link_up)
7256                                 break;
7257                         msleep_interruptible(1000);
7258                 }
7259         }
7260
7261         if (bnx2_test_nvram(bp) != 0) {
7262                 buf[3] = 1;
7263                 etest->flags |= ETH_TEST_FL_FAILED;
7264         }
7265         if (bnx2_test_intr(bp) != 0) {
7266                 buf[4] = 1;
7267                 etest->flags |= ETH_TEST_FL_FAILED;
7268         }
7269
7270         if (bnx2_test_link(bp) != 0) {
7271                 buf[5] = 1;
7272                 etest->flags |= ETH_TEST_FL_FAILED;
7273
7274         }
7275         if (!netif_running(bp->dev))
7276                 bnx2_set_power_state(bp, PCI_D3hot);
7277 }
7278
7279 static void
7280 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7281 {
7282         switch (stringset) {
7283         case ETH_SS_STATS:
7284                 memcpy(buf, bnx2_stats_str_arr,
7285                         sizeof(bnx2_stats_str_arr));
7286                 break;
7287         case ETH_SS_TEST:
7288                 memcpy(buf, bnx2_tests_str_arr,
7289                         sizeof(bnx2_tests_str_arr));
7290                 break;
7291         }
7292 }
7293
7294 static void
7295 bnx2_get_ethtool_stats(struct net_device *dev,
7296                 struct ethtool_stats *stats, u64 *buf)
7297 {
7298         struct bnx2 *bp = netdev_priv(dev);
7299         int i;
7300         u32 *hw_stats = (u32 *) bp->stats_blk;
7301         u8 *stats_len_arr = NULL;
7302
7303         if (hw_stats == NULL) {
7304                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7305                 return;
7306         }
7307
7308         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7309             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7310             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7311             (CHIP_ID(bp) == CHIP_ID_5708_A0))
7312                 stats_len_arr = bnx2_5706_stats_len_arr;
7313         else
7314                 stats_len_arr = bnx2_5708_stats_len_arr;
7315
7316         for (i = 0; i < BNX2_NUM_STATS; i++) {
7317                 if (stats_len_arr[i] == 0) {
7318                         /* skip this counter */
7319                         buf[i] = 0;
7320                         continue;
7321                 }
7322                 if (stats_len_arr[i] == 4) {
7323                         /* 4-byte counter */
7324                         buf[i] = (u64)
7325                                 *(hw_stats + bnx2_stats_offset_arr[i]);
7326                         continue;
7327                 }
7328                 /* 8-byte counter */
7329                 buf[i] = (((u64) *(hw_stats +
7330                                         bnx2_stats_offset_arr[i])) << 32) +
7331                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7332         }
7333 }
7334
7335 static int
7336 bnx2_phys_id(struct net_device *dev, u32 data)
7337 {
7338         struct bnx2 *bp = netdev_priv(dev);
7339         int i;
7340         u32 save;
7341
7342         bnx2_set_power_state(bp, PCI_D0);
7343
7344         if (data == 0)
7345                 data = 2;
7346
7347         save = REG_RD(bp, BNX2_MISC_CFG);
7348         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7349
7350         for (i = 0; i < (data * 2); i++) {
7351                 if ((i % 2) == 0) {
7352                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7353                 }
7354                 else {
7355                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7356                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
7357                                 BNX2_EMAC_LED_100MB_OVERRIDE |
7358                                 BNX2_EMAC_LED_10MB_OVERRIDE |
7359                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7360                                 BNX2_EMAC_LED_TRAFFIC);
7361                 }
7362                 msleep_interruptible(500);
7363                 if (signal_pending(current))
7364                         break;
7365         }
7366         REG_WR(bp, BNX2_EMAC_LED, 0);
7367         REG_WR(bp, BNX2_MISC_CFG, save);
7368
7369         if (!netif_running(dev))
7370                 bnx2_set_power_state(bp, PCI_D3hot);
7371
7372         return 0;
7373 }
7374
7375 static int
7376 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7377 {
7378         struct bnx2 *bp = netdev_priv(dev);
7379
7380         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7381                 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7382         else
7383                 return (ethtool_op_set_tx_csum(dev, data));
7384 }
7385
7386 static const struct ethtool_ops bnx2_ethtool_ops = {
7387         .get_settings           = bnx2_get_settings,
7388         .set_settings           = bnx2_set_settings,
7389         .get_drvinfo            = bnx2_get_drvinfo,
7390         .get_regs_len           = bnx2_get_regs_len,
7391         .get_regs               = bnx2_get_regs,
7392         .get_wol                = bnx2_get_wol,
7393         .set_wol                = bnx2_set_wol,
7394         .nway_reset             = bnx2_nway_reset,
7395         .get_link               = ethtool_op_get_link,
7396         .get_eeprom_len         = bnx2_get_eeprom_len,
7397         .get_eeprom             = bnx2_get_eeprom,
7398         .set_eeprom             = bnx2_set_eeprom,
7399         .get_coalesce           = bnx2_get_coalesce,
7400         .set_coalesce           = bnx2_set_coalesce,
7401         .get_ringparam          = bnx2_get_ringparam,
7402         .set_ringparam          = bnx2_set_ringparam,
7403         .get_pauseparam         = bnx2_get_pauseparam,
7404         .set_pauseparam         = bnx2_set_pauseparam,
7405         .get_rx_csum            = bnx2_get_rx_csum,
7406         .set_rx_csum            = bnx2_set_rx_csum,
7407         .set_tx_csum            = bnx2_set_tx_csum,
7408         .set_sg                 = ethtool_op_set_sg,
7409         .set_tso                = bnx2_set_tso,
7410         .self_test              = bnx2_self_test,
7411         .get_strings            = bnx2_get_strings,
7412         .phys_id                = bnx2_phys_id,
7413         .get_ethtool_stats      = bnx2_get_ethtool_stats,
7414         .get_sset_count         = bnx2_get_sset_count,
7415 };
7416
7417 /* Called with rtnl_lock */
7418 static int
7419 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7420 {
7421         struct mii_ioctl_data *data = if_mii(ifr);
7422         struct bnx2 *bp = netdev_priv(dev);
7423         int err;
7424
7425         switch(cmd) {
7426         case SIOCGMIIPHY:
7427                 data->phy_id = bp->phy_addr;
7428
7429                 /* fallthru */
7430         case SIOCGMIIREG: {
7431                 u32 mii_regval;
7432
7433                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7434                         return -EOPNOTSUPP;
7435
7436                 if (!netif_running(dev))
7437                         return -EAGAIN;
7438
7439                 spin_lock_bh(&bp->phy_lock);
7440                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7441                 spin_unlock_bh(&bp->phy_lock);
7442
7443                 data->val_out = mii_regval;
7444
7445                 return err;
7446         }
7447
7448         case SIOCSMIIREG:
7449                 if (!capable(CAP_NET_ADMIN))
7450                         return -EPERM;
7451
7452                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7453                         return -EOPNOTSUPP;
7454
7455                 if (!netif_running(dev))
7456                         return -EAGAIN;
7457
7458                 spin_lock_bh(&bp->phy_lock);
7459                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7460                 spin_unlock_bh(&bp->phy_lock);
7461
7462                 return err;
7463
7464         default:
7465                 /* do nothing */
7466                 break;
7467         }
7468         return -EOPNOTSUPP;
7469 }
7470
7471 /* Called with rtnl_lock */
7472 static int
7473 bnx2_change_mac_addr(struct net_device *dev, void *p)
7474 {
7475         struct sockaddr *addr = p;
7476         struct bnx2 *bp = netdev_priv(dev);
7477
7478         if (!is_valid_ether_addr(addr->sa_data))
7479                 return -EINVAL;
7480
7481         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7482         if (netif_running(dev))
7483                 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7484
7485         return 0;
7486 }
7487
7488 /* Called with rtnl_lock */
7489 static int
7490 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7491 {
7492         struct bnx2 *bp = netdev_priv(dev);
7493
7494         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7495                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7496                 return -EINVAL;
7497
7498         dev->mtu = new_mtu;
7499         return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7500 }
7501
7502 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7503 static void
7504 poll_bnx2(struct net_device *dev)
7505 {
7506         struct bnx2 *bp = netdev_priv(dev);
7507         int i;
7508
7509         for (i = 0; i < bp->irq_nvecs; i++) {
7510                 disable_irq(bp->irq_tbl[i].vector);
7511                 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7512                 enable_irq(bp->irq_tbl[i].vector);
7513         }
7514 }
7515 #endif
7516
7517 static void __devinit
7518 bnx2_get_5709_media(struct bnx2 *bp)
7519 {
7520         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7521         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7522         u32 strap;
7523
7524         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7525                 return;
7526         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7527                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7528                 return;
7529         }
7530
7531         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7532                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7533         else
7534                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7535
7536         if (PCI_FUNC(bp->pdev->devfn) == 0) {
7537                 switch (strap) {
7538                 case 0x4:
7539                 case 0x5:
7540                 case 0x6:
7541                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7542                         return;
7543                 }
7544         } else {
7545                 switch (strap) {
7546                 case 0x1:
7547                 case 0x2:
7548                 case 0x4:
7549                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7550                         return;
7551                 }
7552         }
7553 }
7554
7555 static void __devinit
7556 bnx2_get_pci_speed(struct bnx2 *bp)
7557 {
7558         u32 reg;
7559
7560         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7561         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7562                 u32 clkreg;
7563
7564                 bp->flags |= BNX2_FLAG_PCIX;
7565
7566                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7567
7568                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7569                 switch (clkreg) {
7570                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7571                         bp->bus_speed_mhz = 133;
7572                         break;
7573
7574                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7575                         bp->bus_speed_mhz = 100;
7576                         break;
7577
7578                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7579                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7580                         bp->bus_speed_mhz = 66;
7581                         break;
7582
7583                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7584                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7585                         bp->bus_speed_mhz = 50;
7586                         break;
7587
7588                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7589                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7590                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7591                         bp->bus_speed_mhz = 33;
7592                         break;
7593                 }
7594         }
7595         else {
7596                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7597                         bp->bus_speed_mhz = 66;
7598                 else
7599                         bp->bus_speed_mhz = 33;
7600         }
7601
7602         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7603                 bp->flags |= BNX2_FLAG_PCI_32BIT;
7604
7605 }
7606
7607 static int __devinit
7608 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7609 {
7610         struct bnx2 *bp;
7611         unsigned long mem_len;
7612         int rc, i, j;
7613         u32 reg;
7614         u64 dma_mask, persist_dma_mask;
7615
7616         SET_NETDEV_DEV(dev, &pdev->dev);
7617         bp = netdev_priv(dev);
7618
7619         bp->flags = 0;
7620         bp->phy_flags = 0;
7621
7622         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7623         rc = pci_enable_device(pdev);
7624         if (rc) {
7625                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7626                 goto err_out;
7627         }
7628
7629         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7630                 dev_err(&pdev->dev,
7631                         "Cannot find PCI device base address, aborting.\n");
7632                 rc = -ENODEV;
7633                 goto err_out_disable;
7634         }
7635
7636         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7637         if (rc) {
7638                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7639                 goto err_out_disable;
7640         }
7641
7642         pci_set_master(pdev);
7643         pci_save_state(pdev);
7644
7645         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7646         if (bp->pm_cap == 0) {
7647                 dev_err(&pdev->dev,
7648                         "Cannot find power management capability, aborting.\n");
7649                 rc = -EIO;
7650                 goto err_out_release;
7651         }
7652
7653         bp->dev = dev;
7654         bp->pdev = pdev;
7655
7656         spin_lock_init(&bp->phy_lock);
7657         spin_lock_init(&bp->indirect_lock);
7658         INIT_WORK(&bp->reset_task, bnx2_reset_task);
7659
7660         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7661         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7662         dev->mem_end = dev->mem_start + mem_len;
7663         dev->irq = pdev->irq;
7664
7665         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7666
7667         if (!bp->regview) {
7668                 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7669                 rc = -ENOMEM;
7670                 goto err_out_release;
7671         }
7672
7673         /* Configure byte swap and enable write to the reg_window registers.
7674          * Rely on CPU to do target byte swapping on big endian systems
7675          * The chip's target access swapping will not swap all accesses
7676          */
7677         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7678                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7679                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7680
7681         bnx2_set_power_state(bp, PCI_D0);
7682
7683         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7684
7685         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7686                 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7687                         dev_err(&pdev->dev,
7688                                 "Cannot find PCIE capability, aborting.\n");
7689                         rc = -EIO;
7690                         goto err_out_unmap;
7691                 }
7692                 bp->flags |= BNX2_FLAG_PCIE;
7693                 if (CHIP_REV(bp) == CHIP_REV_Ax)
7694                         bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7695         } else {
7696                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7697                 if (bp->pcix_cap == 0) {
7698                         dev_err(&pdev->dev,
7699                                 "Cannot find PCIX capability, aborting.\n");
7700                         rc = -EIO;
7701                         goto err_out_unmap;
7702                 }
7703         }
7704
7705         if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7706                 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7707                         bp->flags |= BNX2_FLAG_MSIX_CAP;
7708         }
7709
7710         if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7711                 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7712                         bp->flags |= BNX2_FLAG_MSI_CAP;
7713         }
7714
7715         /* 5708 cannot support DMA addresses > 40-bit.  */
7716         if (CHIP_NUM(bp) == CHIP_NUM_5708)
7717                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7718         else
7719                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7720
7721         /* Configure DMA attributes. */
7722         if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7723                 dev->features |= NETIF_F_HIGHDMA;
7724                 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7725                 if (rc) {
7726                         dev_err(&pdev->dev,
7727                                 "pci_set_consistent_dma_mask failed, aborting.\n");
7728                         goto err_out_unmap;
7729                 }
7730         } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7731                 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7732                 goto err_out_unmap;
7733         }
7734
7735         if (!(bp->flags & BNX2_FLAG_PCIE))
7736                 bnx2_get_pci_speed(bp);
7737
7738         /* 5706A0 may falsely detect SERR and PERR. */
7739         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7740                 reg = REG_RD(bp, PCI_COMMAND);
7741                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7742                 REG_WR(bp, PCI_COMMAND, reg);
7743         }
7744         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7745                 !(bp->flags & BNX2_FLAG_PCIX)) {
7746
7747                 dev_err(&pdev->dev,
7748                         "5706 A1 can only be used in a PCIX bus, aborting.\n");
7749                 goto err_out_unmap;
7750         }
7751
7752         bnx2_init_nvram(bp);
7753
7754         reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7755
7756         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7757             BNX2_SHM_HDR_SIGNATURE_SIG) {
7758                 u32 off = PCI_FUNC(pdev->devfn) << 2;
7759
7760                 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7761         } else
7762                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7763
7764         /* Get the permanent MAC address.  First we need to make sure the
7765          * firmware is actually running.
7766          */
7767         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7768
7769         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7770             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7771                 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7772                 rc = -ENODEV;
7773                 goto err_out_unmap;
7774         }
7775
7776         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7777         for (i = 0, j = 0; i < 3; i++) {
7778                 u8 num, k, skip0;
7779
7780                 num = (u8) (reg >> (24 - (i * 8)));
7781                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7782                         if (num >= k || !skip0 || k == 1) {
7783                                 bp->fw_version[j++] = (num / k) + '0';
7784                                 skip0 = 0;
7785                         }
7786                 }
7787                 if (i != 2)
7788                         bp->fw_version[j++] = '.';
7789         }
7790         reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7791         if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7792                 bp->wol = 1;
7793
7794         if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7795                 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7796
7797                 for (i = 0; i < 30; i++) {
7798                         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7799                         if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7800                                 break;
7801                         msleep(10);
7802                 }
7803         }
7804         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7805         reg &= BNX2_CONDITION_MFW_RUN_MASK;
7806         if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7807             reg != BNX2_CONDITION_MFW_RUN_NONE) {
7808                 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7809
7810                 bp->fw_version[j++] = ' ';
7811                 for (i = 0; i < 3; i++) {
7812                         reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7813                         reg = swab32(reg);
7814                         memcpy(&bp->fw_version[j], &reg, 4);
7815                         j += 4;
7816                 }
7817         }
7818
7819         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7820         bp->mac_addr[0] = (u8) (reg >> 8);
7821         bp->mac_addr[1] = (u8) reg;
7822
7823         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7824         bp->mac_addr[2] = (u8) (reg >> 24);
7825         bp->mac_addr[3] = (u8) (reg >> 16);
7826         bp->mac_addr[4] = (u8) (reg >> 8);
7827         bp->mac_addr[5] = (u8) reg;
7828
7829         bp->tx_ring_size = MAX_TX_DESC_CNT;
7830         bnx2_set_rx_ring_size(bp, 255);
7831
7832         bp->rx_csum = 1;
7833
7834         bp->tx_quick_cons_trip_int = 20;
7835         bp->tx_quick_cons_trip = 20;
7836         bp->tx_ticks_int = 80;
7837         bp->tx_ticks = 80;
7838
7839         bp->rx_quick_cons_trip_int = 6;
7840         bp->rx_quick_cons_trip = 6;
7841         bp->rx_ticks_int = 18;
7842         bp->rx_ticks = 18;
7843
7844         bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7845
7846         bp->current_interval = BNX2_TIMER_INTERVAL;
7847
7848         bp->phy_addr = 1;
7849
7850         /* Disable WOL support if we are running on a SERDES chip. */
7851         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7852                 bnx2_get_5709_media(bp);
7853         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7854                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7855
7856         bp->phy_port = PORT_TP;
7857         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7858                 bp->phy_port = PORT_FIBRE;
7859                 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7860                 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7861                         bp->flags |= BNX2_FLAG_NO_WOL;
7862                         bp->wol = 0;
7863                 }
7864                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7865                         /* Don't do parallel detect on this board because of
7866                          * some board problems.  The link will not go down
7867                          * if we do parallel detect.
7868                          */
7869                         if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7870                             pdev->subsystem_device == 0x310c)
7871                                 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7872                 } else {
7873                         bp->phy_addr = 2;
7874                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7875                                 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7876                 }
7877         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7878                    CHIP_NUM(bp) == CHIP_NUM_5708)
7879                 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7880         else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7881                  (CHIP_REV(bp) == CHIP_REV_Ax ||
7882                   CHIP_REV(bp) == CHIP_REV_Bx))
7883                 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7884
7885         bnx2_init_fw_cap(bp);
7886
7887         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7888             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7889             (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
7890             !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7891                 bp->flags |= BNX2_FLAG_NO_WOL;
7892                 bp->wol = 0;
7893         }
7894
7895         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7896                 bp->tx_quick_cons_trip_int =
7897                         bp->tx_quick_cons_trip;
7898                 bp->tx_ticks_int = bp->tx_ticks;
7899                 bp->rx_quick_cons_trip_int =
7900                         bp->rx_quick_cons_trip;
7901                 bp->rx_ticks_int = bp->rx_ticks;
7902                 bp->comp_prod_trip_int = bp->comp_prod_trip;
7903                 bp->com_ticks_int = bp->com_ticks;
7904                 bp->cmd_ticks_int = bp->cmd_ticks;
7905         }
7906
7907         /* Disable MSI on 5706 if AMD 8132 bridge is found.
7908          *
7909          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
7910          * with byte enables disabled on the unused 32-bit word.  This is legal
7911          * but causes problems on the AMD 8132 which will eventually stop
7912          * responding after a while.
7913          *
7914          * AMD believes this incompatibility is unique to the 5706, and
7915          * prefers to locally disable MSI rather than globally disabling it.
7916          */
7917         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7918                 struct pci_dev *amd_8132 = NULL;
7919
7920                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7921                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
7922                                                   amd_8132))) {
7923
7924                         if (amd_8132->revision >= 0x10 &&
7925                             amd_8132->revision <= 0x13) {
7926                                 disable_msi = 1;
7927                                 pci_dev_put(amd_8132);
7928                                 break;
7929                         }
7930                 }
7931         }
7932
7933         bnx2_set_default_link(bp);
7934         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7935
7936         init_timer(&bp->timer);
7937         bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7938         bp->timer.data = (unsigned long) bp;
7939         bp->timer.function = bnx2_timer;
7940
7941         return 0;
7942
7943 err_out_unmap:
7944         if (bp->regview) {
7945                 iounmap(bp->regview);
7946                 bp->regview = NULL;
7947         }
7948
7949 err_out_release:
7950         pci_release_regions(pdev);
7951
7952 err_out_disable:
7953         pci_disable_device(pdev);
7954         pci_set_drvdata(pdev, NULL);
7955
7956 err_out:
7957         return rc;
7958 }
7959
7960 static char * __devinit
7961 bnx2_bus_string(struct bnx2 *bp, char *str)
7962 {
7963         char *s = str;
7964
7965         if (bp->flags & BNX2_FLAG_PCIE) {
7966                 s += sprintf(s, "PCI Express");
7967         } else {
7968                 s += sprintf(s, "PCI");
7969                 if (bp->flags & BNX2_FLAG_PCIX)
7970                         s += sprintf(s, "-X");
7971                 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7972                         s += sprintf(s, " 32-bit");
7973                 else
7974                         s += sprintf(s, " 64-bit");
7975                 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7976         }
7977         return str;
7978 }
7979
7980 static void __devinit
7981 bnx2_init_napi(struct bnx2 *bp)
7982 {
7983         int i;
7984
7985         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7986                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7987                 int (*poll)(struct napi_struct *, int);
7988
7989                 if (i == 0)
7990                         poll = bnx2_poll;
7991                 else
7992                         poll = bnx2_poll_msix;
7993
7994                 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7995                 bnapi->bp = bp;
7996         }
7997 }
7998
7999 static const struct net_device_ops bnx2_netdev_ops = {
8000         .ndo_open               = bnx2_open,
8001         .ndo_start_xmit         = bnx2_start_xmit,
8002         .ndo_stop               = bnx2_close,
8003         .ndo_get_stats          = bnx2_get_stats,
8004         .ndo_set_rx_mode        = bnx2_set_rx_mode,
8005         .ndo_do_ioctl           = bnx2_ioctl,
8006         .ndo_validate_addr      = eth_validate_addr,
8007         .ndo_set_mac_address    = bnx2_change_mac_addr,
8008         .ndo_change_mtu         = bnx2_change_mtu,
8009         .ndo_tx_timeout         = bnx2_tx_timeout,
8010 #ifdef BCM_VLAN
8011         .ndo_vlan_rx_register   = bnx2_vlan_rx_register,
8012 #endif
8013 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
8014         .ndo_poll_controller    = poll_bnx2,
8015 #endif
8016 };
8017
8018 static int __devinit
8019 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8020 {
8021         static int version_printed = 0;
8022         struct net_device *dev = NULL;
8023         struct bnx2 *bp;
8024         int rc;
8025         char str[40];
8026
8027         if (version_printed++ == 0)
8028                 printk(KERN_INFO "%s", version);
8029
8030         /* dev zeroed in init_etherdev */
8031         dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8032
8033         if (!dev)
8034                 return -ENOMEM;
8035
8036         rc = bnx2_init_board(pdev, dev);
8037         if (rc < 0) {
8038                 free_netdev(dev);
8039                 return rc;
8040         }
8041
8042         dev->netdev_ops = &bnx2_netdev_ops;
8043         dev->watchdog_timeo = TX_TIMEOUT;
8044         dev->ethtool_ops = &bnx2_ethtool_ops;
8045
8046         bp = netdev_priv(dev);
8047         bnx2_init_napi(bp);
8048
8049         pci_set_drvdata(pdev, dev);
8050
8051         rc = bnx2_request_firmware(bp);
8052         if (rc)
8053                 goto error;
8054
8055         memcpy(dev->dev_addr, bp->mac_addr, 6);
8056         memcpy(dev->perm_addr, bp->mac_addr, 6);
8057
8058         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
8059         if (CHIP_NUM(bp) == CHIP_NUM_5709)
8060                 dev->features |= NETIF_F_IPV6_CSUM;
8061
8062 #ifdef BCM_VLAN
8063         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8064 #endif
8065         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8066         if (CHIP_NUM(bp) == CHIP_NUM_5709)
8067                 dev->features |= NETIF_F_TSO6;
8068
8069         if ((rc = register_netdev(dev))) {
8070                 dev_err(&pdev->dev, "Cannot register net device\n");
8071                 goto error;
8072         }
8073
8074         printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
8075                 "IRQ %d, node addr %pM\n",
8076                 dev->name,
8077                 board_info[ent->driver_data].name,
8078                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8079                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8080                 bnx2_bus_string(bp, str),
8081                 dev->base_addr,
8082                 bp->pdev->irq, dev->dev_addr);
8083
8084         return 0;
8085
8086 error:
8087         if (bp->mips_firmware)
8088                 release_firmware(bp->mips_firmware);
8089         if (bp->rv2p_firmware)
8090                 release_firmware(bp->rv2p_firmware);
8091
8092         if (bp->regview)
8093                 iounmap(bp->regview);
8094         pci_release_regions(pdev);
8095         pci_disable_device(pdev);
8096         pci_set_drvdata(pdev, NULL);
8097         free_netdev(dev);
8098         return rc;
8099 }
8100
8101 static void __devexit
8102 bnx2_remove_one(struct pci_dev *pdev)
8103 {
8104         struct net_device *dev = pci_get_drvdata(pdev);
8105         struct bnx2 *bp = netdev_priv(dev);
8106
8107         flush_scheduled_work();
8108
8109         unregister_netdev(dev);
8110
8111         if (bp->mips_firmware)
8112                 release_firmware(bp->mips_firmware);
8113         if (bp->rv2p_firmware)
8114                 release_firmware(bp->rv2p_firmware);
8115
8116         if (bp->regview)
8117                 iounmap(bp->regview);
8118
8119         free_netdev(dev);
8120         pci_release_regions(pdev);
8121         pci_disable_device(pdev);
8122         pci_set_drvdata(pdev, NULL);
8123 }
8124
8125 static int
8126 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8127 {
8128         struct net_device *dev = pci_get_drvdata(pdev);
8129         struct bnx2 *bp = netdev_priv(dev);
8130
8131         /* PCI register 4 needs to be saved whether netif_running() or not.
8132          * MSI address and data need to be saved if using MSI and
8133          * netif_running().
8134          */
8135         pci_save_state(pdev);
8136         if (!netif_running(dev))
8137                 return 0;
8138
8139         flush_scheduled_work();
8140         bnx2_netif_stop(bp);
8141         netif_device_detach(dev);
8142         del_timer_sync(&bp->timer);
8143         bnx2_shutdown_chip(bp);
8144         bnx2_free_skbs(bp);
8145         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8146         return 0;
8147 }
8148
8149 static int
8150 bnx2_resume(struct pci_dev *pdev)
8151 {
8152         struct net_device *dev = pci_get_drvdata(pdev);
8153         struct bnx2 *bp = netdev_priv(dev);
8154
8155         pci_restore_state(pdev);
8156         if (!netif_running(dev))
8157                 return 0;
8158
8159         bnx2_set_power_state(bp, PCI_D0);
8160         netif_device_attach(dev);
8161         bnx2_init_nic(bp, 1);
8162         bnx2_netif_start(bp);
8163         return 0;
8164 }
8165
8166 /**
8167  * bnx2_io_error_detected - called when PCI error is detected
8168  * @pdev: Pointer to PCI device
8169  * @state: The current pci connection state
8170  *
8171  * This function is called after a PCI bus error affecting
8172  * this device has been detected.
8173  */
8174 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8175                                                pci_channel_state_t state)
8176 {
8177         struct net_device *dev = pci_get_drvdata(pdev);
8178         struct bnx2 *bp = netdev_priv(dev);
8179
8180         rtnl_lock();
8181         netif_device_detach(dev);
8182
8183         if (netif_running(dev)) {
8184                 bnx2_netif_stop(bp);
8185                 del_timer_sync(&bp->timer);
8186                 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8187         }
8188
8189         pci_disable_device(pdev);
8190         rtnl_unlock();
8191
8192         /* Request a slot slot reset. */
8193         return PCI_ERS_RESULT_NEED_RESET;
8194 }
8195
8196 /**
8197  * bnx2_io_slot_reset - called after the pci bus has been reset.
8198  * @pdev: Pointer to PCI device
8199  *
8200  * Restart the card from scratch, as if from a cold-boot.
8201  */
8202 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8203 {
8204         struct net_device *dev = pci_get_drvdata(pdev);
8205         struct bnx2 *bp = netdev_priv(dev);
8206
8207         rtnl_lock();
8208         if (pci_enable_device(pdev)) {
8209                 dev_err(&pdev->dev,
8210                         "Cannot re-enable PCI device after reset.\n");
8211                 rtnl_unlock();
8212                 return PCI_ERS_RESULT_DISCONNECT;
8213         }
8214         pci_set_master(pdev);
8215         pci_restore_state(pdev);
8216
8217         if (netif_running(dev)) {
8218                 bnx2_set_power_state(bp, PCI_D0);
8219                 bnx2_init_nic(bp, 1);
8220         }
8221
8222         rtnl_unlock();
8223         return PCI_ERS_RESULT_RECOVERED;
8224 }
8225
8226 /**
8227  * bnx2_io_resume - called when traffic can start flowing again.
8228  * @pdev: Pointer to PCI device
8229  *
8230  * This callback is called when the error recovery driver tells us that
8231  * its OK to resume normal operation.
8232  */
8233 static void bnx2_io_resume(struct pci_dev *pdev)
8234 {
8235         struct net_device *dev = pci_get_drvdata(pdev);
8236         struct bnx2 *bp = netdev_priv(dev);
8237
8238         rtnl_lock();
8239         if (netif_running(dev))
8240                 bnx2_netif_start(bp);
8241
8242         netif_device_attach(dev);
8243         rtnl_unlock();
8244 }
8245
8246 static struct pci_error_handlers bnx2_err_handler = {
8247         .error_detected = bnx2_io_error_detected,
8248         .slot_reset     = bnx2_io_slot_reset,
8249         .resume         = bnx2_io_resume,
8250 };
8251
8252 static struct pci_driver bnx2_pci_driver = {
8253         .name           = DRV_MODULE_NAME,
8254         .id_table       = bnx2_pci_tbl,
8255         .probe          = bnx2_init_one,
8256         .remove         = __devexit_p(bnx2_remove_one),
8257         .suspend        = bnx2_suspend,
8258         .resume         = bnx2_resume,
8259         .err_handler    = &bnx2_err_handler,
8260 };
8261
8262 static int __init bnx2_init(void)
8263 {
8264         return pci_register_driver(&bnx2_pci_driver);
8265 }
8266
8267 static void __exit bnx2_cleanup(void)
8268 {
8269         pci_unregister_driver(&bnx2_pci_driver);
8270 }
8271
8272 module_init(bnx2_init);
8273 module_exit(bnx2_cleanup);
8274
8275
8276