drivers/net/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0x0,
  55 /* The client does not have sufficient privileges to execute the command */
  56         MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
  57 /* A parameter in the command was invalid. */
  58         MCC_STATUS_INVALID_PARAMETER = 0x2,
  59 /* There are insufficient chip resources to execute the command */
  60         MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
  61 /* The command is completing because the queue was getting flushed */
  62         MCC_STATUS_QUEUE_FLUSHING = 0x4,
  63 /* The command is completing with a DMA error */
  64         MCC_STATUS_DMA_FAILED = 0x5
  65 };
  66
  67 #define CQE_STATUS_COMPL_MASK           0xFFFF
  68 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  69 #define CQE_STATUS_EXTD_MASK            0xFFFF
  70 #define CQE_STATUS_EXTD_SHIFT           0       /* bits 0 - 15 */
  71
  72 struct be_mcc_cq_entry {
  73         u32 status;             /* dword 0 */
  74         u32 tag0;               /* dword 1 */
  75         u32 tag1;               /* dword 2 */
  76         u32 flags;              /* dword 3 */
  77 };
  78
  79 /* When the async bit of mcc_compl is set, the last 4 bytes of
  80  * mcc_compl is interpreted as follows:
  81  */
  82 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  83 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  84 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  85 struct be_async_event_trailer {
  86         u32 code;
  87 };
  88
  89 enum {
  90         ASYNC_EVENT_LINK_DOWN   = 0x0,
  91         ASYNC_EVENT_LINK_UP     = 0x1
  92 };
  93
  94 /* When the event code of an async trailer is link-state, the mcc_compl
  95  * must be interpreted as follows
  96  */
  97 struct be_async_event_link_state {
  98         u8 physical_port;
  99         u8 port_link_status;
 100         u8 port_duplex;
 101         u8 port_speed;
 102         u8 port_fault;
 103         u8 rsvd0[7];
 104         struct be_async_event_trailer trailer;
 105 } __packed;
 106
 107 struct be_mcc_mailbox {
 108         struct be_mcc_wrb wrb;
 109         struct be_mcc_cq_entry cqe;
 110 };
 111
 112 #define CMD_SUBSYSTEM_COMMON    0x1
 113 #define CMD_SUBSYSTEM_ETH       0x3
 114
 115 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 116 #define OPCODE_COMMON_NTWK_MAC_SET                      2
 117 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 118 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 119 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 120 #define OPCODE_COMMON_CQ_CREATE                         12
 121 #define OPCODE_COMMON_EQ_CREATE                         13
 122 #define OPCODE_COMMON_MCC_CREATE                        21
 123 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
 124 #define OPCODE_COMMON_GET_FW_VERSION                    35
 125 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 126 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 127 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 128 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 129 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 130 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 131 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 132 #define OPCODE_COMMON_MCC_DESTROY                       53
 133 #define OPCODE_COMMON_CQ_DESTROY                        54
 134 #define OPCODE_COMMON_EQ_DESTROY                        55
 135 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 136 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 137 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 138
 139 #define OPCODE_ETH_ACPI_CONFIG                          2
 140 #define OPCODE_ETH_PROMISCUOUS                          3
 141 #define OPCODE_ETH_GET_STATISTICS                       4
 142 #define OPCODE_ETH_TX_CREATE                            7
 143 #define OPCODE_ETH_RX_CREATE                            8
 144 #define OPCODE_ETH_TX_DESTROY                           9
 145 #define OPCODE_ETH_RX_DESTROY                           10
 146
 147 struct be_cmd_req_hdr {
 148         u8 opcode;              /* dword 0 */
 149         u8 subsystem;           /* dword 0 */
 150         u8 port_number;         /* dword 0 */
 151         u8 domain;              /* dword 0 */
 152         u32 timeout;            /* dword 1 */
 153         u32 request_length;     /* dword 2 */
 154         u32 rsvd;               /* dword 3 */
 155 };
 156
 157 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 158 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 159 struct be_cmd_resp_hdr {
 160         u32 info;               /* dword 0 */
 161         u32 status;             /* dword 1 */
 162         u32 response_length;    /* dword 2 */
 163         u32 actual_resp_len;    /* dword 3 */
 164 };
 165
 166 struct phys_addr {
 167         u32 lo;
 168         u32 hi;
 169 };
 170
 171 /**************************
 172  * BE Command definitions *
 173  **************************/
 174
 175 /* Pseudo amap definition in which each bit of the actual structure is defined
 176  * as a byte: used to calculate offset/shift/mask of each field */
 177 struct amap_eq_context {
 178         u8 cidx[13];            /* dword 0*/
 179         u8 rsvd0[3];            /* dword 0*/
 180         u8 epidx[13];           /* dword 0*/
 181         u8 valid;               /* dword 0*/
 182         u8 rsvd1;               /* dword 0*/
 183         u8 size;                /* dword 0*/
 184         u8 pidx[13];            /* dword 1*/
 185         u8 rsvd2[3];            /* dword 1*/
 186         u8 pd[10];              /* dword 1*/
 187         u8 count[3];            /* dword 1*/
 188         u8 solevent;            /* dword 1*/
 189         u8 stalled;             /* dword 1*/
 190         u8 armed;               /* dword 1*/
 191         u8 rsvd3[4];            /* dword 2*/
 192         u8 func[8];             /* dword 2*/
 193         u8 rsvd4;               /* dword 2*/
 194         u8 delaymult[10];       /* dword 2*/
 195         u8 rsvd5[2];            /* dword 2*/
 196         u8 phase[2];            /* dword 2*/
 197         u8 nodelay;             /* dword 2*/
 198         u8 rsvd6[4];            /* dword 2*/
 199         u8 rsvd7[32];           /* dword 3*/
 200 } __packed;
 201
 202 struct be_cmd_req_eq_create {
 203         struct be_cmd_req_hdr hdr;
 204         u16 num_pages;          /* sword */
 205         u16 rsvd0;              /* sword */
 206         u8 context[sizeof(struct amap_eq_context) / 8];
 207         struct phys_addr pages[8];
 208 } __packed;
 209
 210 struct be_cmd_resp_eq_create {
 211         struct be_cmd_resp_hdr resp_hdr;
 212         u16 eq_id;              /* sword */
 213         u16 rsvd0;              /* sword */
 214 } __packed;
 215
 216 /******************** Mac query ***************************/
 217 enum {
 218         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 219         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 220         MAC_ADDRESS_TYPE_PD = 0x2,
 221         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 222 };
 223
 224 struct mac_addr {
 225         u16 size_of_struct;
 226         u8 addr[ETH_ALEN];
 227 } __packed;
 228
 229 struct be_cmd_req_mac_query {
 230         struct be_cmd_req_hdr hdr;
 231         u8 type;
 232         u8 permanent;
 233         u16 if_id;
 234 } __packed;
 235
 236 struct be_cmd_resp_mac_query {
 237         struct be_cmd_resp_hdr hdr;
 238         struct mac_addr mac;
 239 };
 240
 241 /******************** PMac Add ***************************/
 242 struct be_cmd_req_pmac_add {
 243         struct be_cmd_req_hdr hdr;
 244         u32 if_id;
 245         u8 mac_address[ETH_ALEN];
 246         u8 rsvd0[2];
 247 } __packed;
 248
 249 struct be_cmd_resp_pmac_add {
 250         struct be_cmd_resp_hdr hdr;
 251         u32 pmac_id;
 252 };
 253
 254 /******************** PMac Del ***************************/
 255 struct be_cmd_req_pmac_del {
 256         struct be_cmd_req_hdr hdr;
 257         u32 if_id;
 258         u32 pmac_id;
 259 };
 260
 261 /******************** Create CQ ***************************/
 262 /* Pseudo amap definition in which each bit of the actual structure is defined
 263  * as a byte: used to calculate offset/shift/mask of each field */
 264 struct amap_cq_context {
 265         u8 cidx[11];            /* dword 0*/
 266         u8 rsvd0;               /* dword 0*/
 267         u8 coalescwm[2];        /* dword 0*/
 268         u8 nodelay;             /* dword 0*/
 269         u8 epidx[11];           /* dword 0*/
 270         u8 rsvd1;               /* dword 0*/
 271         u8 count[2];            /* dword 0*/
 272         u8 valid;               /* dword 0*/
 273         u8 solevent;            /* dword 0*/
 274         u8 eventable;           /* dword 0*/
 275         u8 pidx[11];            /* dword 1*/
 276         u8 rsvd2;               /* dword 1*/
 277         u8 pd[10];              /* dword 1*/
 278         u8 eqid[8];             /* dword 1*/
 279         u8 stalled;             /* dword 1*/
 280         u8 armed;               /* dword 1*/
 281         u8 rsvd3[4];            /* dword 2*/
 282         u8 func[8];             /* dword 2*/
 283         u8 rsvd4[20];           /* dword 2*/
 284         u8 rsvd5[32];           /* dword 3*/
 285 } __packed;
 286
 287 struct be_cmd_req_cq_create {
 288         struct be_cmd_req_hdr hdr;
 289         u16 num_pages;
 290         u16 rsvd0;
 291         u8 context[sizeof(struct amap_cq_context) / 8];
 292         struct phys_addr pages[8];
 293 } __packed;
 294
 295 struct be_cmd_resp_cq_create {
 296         struct be_cmd_resp_hdr hdr;
 297         u16 cq_id;
 298         u16 rsvd0;
 299 } __packed;
 300
 301 /******************** Create MCCQ ***************************/
 302 /* Pseudo amap definition in which each bit of the actual structure is defined
 303  * as a byte: used to calculate offset/shift/mask of each field */
 304 struct amap_mcc_context {
 305         u8 con_index[14];
 306         u8 rsvd0[2];
 307         u8 ring_size[4];
 308         u8 fetch_wrb;
 309         u8 fetch_r2t;
 310         u8 cq_id[10];
 311         u8 prod_index[14];
 312         u8 fid[8];
 313         u8 pdid[9];
 314         u8 valid;
 315         u8 rsvd1[32];
 316         u8 rsvd2[32];
 317 } __packed;
 318
 319 struct be_cmd_req_mcc_create {
 320         struct be_cmd_req_hdr hdr;
 321         u16 num_pages;
 322         u16 rsvd0;
 323         u8 context[sizeof(struct amap_mcc_context) / 8];
 324         struct phys_addr pages[8];
 325 } __packed;
 326
 327 struct be_cmd_resp_mcc_create {
 328         struct be_cmd_resp_hdr hdr;
 329         u16 id;
 330         u16 rsvd0;
 331 } __packed;
 332
 333 /******************** Create TxQ ***************************/
 334 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 335 #define BE_ULP1_NUM                             1
 336
 337 /* Pseudo amap definition in which each bit of the actual structure is defined
 338  * as a byte: used to calculate offset/shift/mask of each field */
 339 struct amap_tx_context {
 340         u8 rsvd0[16];           /* dword 0 */
 341         u8 tx_ring_size[4];     /* dword 0 */
 342         u8 rsvd1[26];           /* dword 0 */
 343         u8 pci_func_id[8];      /* dword 1 */
 344         u8 rsvd2[9];            /* dword 1 */
 345         u8 ctx_valid;           /* dword 1 */
 346         u8 cq_id_send[16];      /* dword 2 */
 347         u8 rsvd3[16];           /* dword 2 */
 348         u8 rsvd4[32];           /* dword 3 */
 349         u8 rsvd5[32];           /* dword 4 */
 350         u8 rsvd6[32];           /* dword 5 */
 351         u8 rsvd7[32];           /* dword 6 */
 352         u8 rsvd8[32];           /* dword 7 */
 353         u8 rsvd9[32];           /* dword 8 */
 354         u8 rsvd10[32];          /* dword 9 */
 355         u8 rsvd11[32];          /* dword 10 */
 356         u8 rsvd12[32];          /* dword 11 */
 357         u8 rsvd13[32];          /* dword 12 */
 358         u8 rsvd14[32];          /* dword 13 */
 359         u8 rsvd15[32];          /* dword 14 */
 360         u8 rsvd16[32];          /* dword 15 */
 361 } __packed;
 362
 363 struct be_cmd_req_eth_tx_create {
 364         struct be_cmd_req_hdr hdr;
 365         u8 num_pages;
 366         u8 ulp_num;
 367         u8 type;
 368         u8 bound_port;
 369         u8 context[sizeof(struct amap_tx_context) / 8];
 370         struct phys_addr pages[8];
 371 } __packed;
 372
 373 struct be_cmd_resp_eth_tx_create {
 374         struct be_cmd_resp_hdr hdr;
 375         u16 cid;
 376         u16 rsvd0;
 377 } __packed;
 378
 379 /******************** Create RxQ ***************************/
 380 struct be_cmd_req_eth_rx_create {
 381         struct be_cmd_req_hdr hdr;
 382         u16 cq_id;
 383         u8 frag_size;
 384         u8 num_pages;
 385         struct phys_addr pages[2];
 386         u32 interface_id;
 387         u16 max_frame_size;
 388         u16 rsvd0;
 389         u32 rss_queue;
 390 } __packed;
 391
 392 struct be_cmd_resp_eth_rx_create {
 393         struct be_cmd_resp_hdr hdr;
 394         u16 id;
 395         u8 cpu_id;
 396         u8 rsvd0;
 397 } __packed;
 398
 399 /******************** Q Destroy  ***************************/
 400 /* Type of Queue to be destroyed */
 401 enum {
 402         QTYPE_EQ = 1,
 403         QTYPE_CQ,
 404         QTYPE_TXQ,
 405         QTYPE_RXQ,
 406         QTYPE_MCCQ
 407 };
 408
 409 struct be_cmd_req_q_destroy {
 410         struct be_cmd_req_hdr hdr;
 411         u16 id;
 412         u16 bypass_flush;       /* valid only for rx q destroy */
 413 } __packed;
 414
 415 /************ I/f Create (it's actually I/f Config Create)**********/
 416
 417 /* Capability flags for the i/f */
 418 enum be_if_flags {
 419         BE_IF_FLAGS_RSS = 0x4,
 420         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 421         BE_IF_FLAGS_BROADCAST = 0x10,
 422         BE_IF_FLAGS_UNTAGGED = 0x20,
 423         BE_IF_FLAGS_ULP = 0x40,
 424         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 425         BE_IF_FLAGS_VLAN = 0x100,
 426         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 427         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 428         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
 429 };
 430
 431 /* An RX interface is an object with one or more MAC addresses and
 432  * filtering capabilities. */
 433 struct be_cmd_req_if_create {
 434         struct be_cmd_req_hdr hdr;
 435         u32 version;            /* ignore currntly */
 436         u32 capability_flags;
 437         u32 enable_flags;
 438         u8 mac_addr[ETH_ALEN];
 439         u8 rsvd0;
 440         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 441         u32 vlan_tag;    /* not used currently */
 442 } __packed;
 443
 444 struct be_cmd_resp_if_create {
 445         struct be_cmd_resp_hdr hdr;
 446         u32 interface_id;
 447         u32 pmac_id;
 448 };
 449
 450 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 451 struct be_cmd_req_if_destroy {
 452         struct be_cmd_req_hdr hdr;
 453         u32 interface_id;
 454 };
 455
 456 /*************** HW Stats Get **********************************/
 457 struct be_port_rxf_stats {
 458         u32 rx_bytes_lsd;       /* dword 0*/
 459         u32 rx_bytes_msd;       /* dword 1*/
 460         u32 rx_total_frames;    /* dword 2*/
 461         u32 rx_unicast_frames;  /* dword 3*/
 462         u32 rx_multicast_frames;        /* dword 4*/
 463         u32 rx_broadcast_frames;        /* dword 5*/
 464         u32 rx_crc_errors;      /* dword 6*/
 465         u32 rx_alignment_symbol_errors; /* dword 7*/
 466         u32 rx_pause_frames;    /* dword 8*/
 467         u32 rx_control_frames;  /* dword 9*/
 468         u32 rx_in_range_errors; /* dword 10*/
 469         u32 rx_out_range_errors;        /* dword 11*/
 470         u32 rx_frame_too_long;  /* dword 12*/
 471         u32 rx_address_match_errors;    /* dword 13*/
 472         u32 rx_vlan_mismatch;   /* dword 14*/
 473         u32 rx_dropped_too_small;       /* dword 15*/
 474         u32 rx_dropped_too_short;       /* dword 16*/
 475         u32 rx_dropped_header_too_small;        /* dword 17*/
 476         u32 rx_dropped_tcp_length;      /* dword 18*/
 477         u32 rx_dropped_runt;    /* dword 19*/
 478         u32 rx_64_byte_packets; /* dword 20*/
 479         u32 rx_65_127_byte_packets;     /* dword 21*/
 480         u32 rx_128_256_byte_packets;    /* dword 22*/
 481         u32 rx_256_511_byte_packets;    /* dword 23*/
 482         u32 rx_512_1023_byte_packets;   /* dword 24*/
 483         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 484         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 485         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 486         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 487         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 488         u32 rx_ip_checksum_errs;        /* dword 30*/
 489         u32 rx_tcp_checksum_errs;       /* dword 31*/
 490         u32 rx_udp_checksum_errs;       /* dword 32*/
 491         u32 rx_non_rss_packets; /* dword 33*/
 492         u32 rx_ipv4_packets;    /* dword 34*/
 493         u32 rx_ipv6_packets;    /* dword 35*/
 494         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 495         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 496         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 497         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 498         u32 rx_chute1_packets;  /* dword 40*/
 499         u32 rx_chute2_packets;  /* dword 41*/
 500         u32 rx_chute3_packets;  /* dword 42*/
 501         u32 rx_management_packets;      /* dword 43*/
 502         u32 rx_switched_unicast_packets;        /* dword 44*/
 503         u32 rx_switched_multicast_packets;      /* dword 45*/
 504         u32 rx_switched_broadcast_packets;      /* dword 46*/
 505         u32 tx_bytes_lsd;       /* dword 47*/
 506         u32 tx_bytes_msd;       /* dword 48*/
 507         u32 tx_unicastframes;   /* dword 49*/
 508         u32 tx_multicastframes; /* dword 50*/
 509         u32 tx_broadcastframes; /* dword 51*/
 510         u32 tx_pauseframes;     /* dword 52*/
 511         u32 tx_controlframes;   /* dword 53*/
 512         u32 tx_64_byte_packets; /* dword 54*/
 513         u32 tx_65_127_byte_packets;     /* dword 55*/
 514         u32 tx_128_256_byte_packets;    /* dword 56*/
 515         u32 tx_256_511_byte_packets;    /* dword 57*/
 516         u32 tx_512_1023_byte_packets;   /* dword 58*/
 517         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 518         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 519         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 520         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 521         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 522         u32 rx_fifo_overflow;   /* dword 64*/
 523         u32 rx_input_fifo_overflow;     /* dword 65*/
 524 };
 525
 526 struct be_rxf_stats {
 527         struct be_port_rxf_stats port[2];
 528         u32 rx_drops_no_pbuf;   /* dword 132*/
 529         u32 rx_drops_no_txpb;   /* dword 133*/
 530         u32 rx_drops_no_erx_descr;      /* dword 134*/
 531         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 532         u32 management_rx_port_packets; /* dword 136*/
 533         u32 management_rx_port_bytes;   /* dword 137*/
 534         u32 management_rx_port_pause_frames;    /* dword 138*/
 535         u32 management_rx_port_errors;  /* dword 139*/
 536         u32 management_tx_port_packets; /* dword 140*/
 537         u32 management_tx_port_bytes;   /* dword 141*/
 538         u32 management_tx_port_pause;   /* dword 142*/
 539         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 540         u32 rx_drops_too_many_frags;    /* dword 144*/
 541         u32 rx_drops_invalid_ring;      /* dword 145*/
 542         u32 forwarded_packets;  /* dword 146*/
 543         u32 rx_drops_mtu;       /* dword 147*/
 544         u32 rsvd0[15];
 545 };
 546
 547 struct be_erx_stats {
 548         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 549         u32 debug_wdma_sent_hold;          /* dword 44*/
 550         u32 debug_wdma_pbfree_sent_hold;   /* dword 45*/
 551         u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
 552         u32 debug_pmem_pbuf_dealloc;       /* dword 47*/
 553 };
 554
 555 struct be_hw_stats {
 556         struct be_rxf_stats rxf;
 557         u32 rsvd[48];
 558         struct be_erx_stats erx;
 559 };
 560
 561 struct be_cmd_req_get_stats {
 562         struct be_cmd_req_hdr hdr;
 563         u8 rsvd[sizeof(struct be_hw_stats)];
 564 };
 565
 566 struct be_cmd_resp_get_stats {
 567         struct be_cmd_resp_hdr hdr;
 568         struct be_hw_stats hw_stats;
 569 };
 570
 571 struct be_cmd_req_vlan_config {
 572         struct be_cmd_req_hdr hdr;
 573         u8 interface_id;
 574         u8 promiscuous;
 575         u8 untagged;
 576         u8 num_vlan;
 577         u16 normal_vlan[64];
 578 } __packed;
 579
 580 struct be_cmd_req_promiscuous_config {
 581         struct be_cmd_req_hdr hdr;
 582         u8 port0_promiscuous;
 583         u8 port1_promiscuous;
 584         u16 rsvd0;
 585 } __packed;
 586
 587 struct macaddr {
 588         u8 byte[ETH_ALEN];
 589 };
 590
 591 struct be_cmd_req_mcast_mac_config {
 592         struct be_cmd_req_hdr hdr;
 593         u16 num_mac;
 594         u8 promiscuous;
 595         u8 interface_id;
 596         struct macaddr mac[32];
 597 } __packed;
 598
 599 static inline struct be_hw_stats *
 600 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
 601 {
 602         return &cmd->hw_stats;
 603 }
 604
 605 /******************** Link Status Query *******************/
 606 struct be_cmd_req_link_status {
 607         struct be_cmd_req_hdr hdr;
 608         u32 rsvd;
 609 };
 610
 611 enum {
 612         PHY_LINK_DUPLEX_NONE = 0x0,
 613         PHY_LINK_DUPLEX_HALF = 0x1,
 614         PHY_LINK_DUPLEX_FULL = 0x2
 615 };
 616
 617 enum {
 618         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 619         PHY_LINK_SPEED_10MBPS = 0x1,
 620         PHY_LINK_SPEED_100MBPS = 0x2,
 621         PHY_LINK_SPEED_1GBPS = 0x3,
 622         PHY_LINK_SPEED_10GBPS = 0x4
 623 };
 624
 625 struct be_cmd_resp_link_status {
 626         struct be_cmd_resp_hdr hdr;
 627         u8 physical_port;
 628         u8 mac_duplex;
 629         u8 mac_speed;
 630         u8 mac_fault;
 631         u8 mgmt_mac_duplex;
 632         u8 mgmt_mac_speed;
 633         u16 rsvd0;
 634 } __packed;
 635
 636 /******************** Get FW Version *******************/
 637 #define FW_VER_LEN                      32
 638 struct be_cmd_req_get_fw_version {
 639         struct be_cmd_req_hdr hdr;
 640         u8 rsvd0[FW_VER_LEN];
 641         u8 rsvd1[FW_VER_LEN];
 642 } __packed;
 643
 644 struct be_cmd_resp_get_fw_version {
 645         struct be_cmd_resp_hdr hdr;
 646         u8 firmware_version_string[FW_VER_LEN];
 647         u8 fw_on_flash_version_string[FW_VER_LEN];
 648 } __packed;
 649
 650 /******************** Set Flow Contrl *******************/
 651 struct be_cmd_req_set_flow_control {
 652         struct be_cmd_req_hdr hdr;
 653         u16 tx_flow_control;
 654         u16 rx_flow_control;
 655 } __packed;
 656
 657 /******************** Get Flow Contrl *******************/
 658 struct be_cmd_req_get_flow_control {
 659         struct be_cmd_req_hdr hdr;
 660         u32 rsvd;
 661 };
 662
 663 struct be_cmd_resp_get_flow_control {
 664         struct be_cmd_resp_hdr hdr;
 665         u16 tx_flow_control;
 666         u16 rx_flow_control;
 667 } __packed;
 668
 669 /******************** Modify EQ Delay *******************/
 670 struct be_cmd_req_modify_eq_delay {
 671         struct be_cmd_req_hdr hdr;
 672         u32 num_eq;
 673         struct {
 674                 u32 eq_id;
 675                 u32 phase;
 676                 u32 delay_multiplier;
 677         } delay[8];
 678 } __packed;
 679
 680 struct be_cmd_resp_modify_eq_delay {
 681         struct be_cmd_resp_hdr hdr;
 682         u32 rsvd0;
 683 } __packed;
 684
 685 /******************** Get FW Config *******************/
 686 struct be_cmd_req_query_fw_cfg {
 687         struct be_cmd_req_hdr hdr;
 688         u32 rsvd[30];
 689 };
 690
 691 struct be_cmd_resp_query_fw_cfg {
 692         struct be_cmd_resp_hdr hdr;
 693         u32 be_config_number;
 694         u32 asic_revision;
 695         u32 phys_port;
 696         u32 function_mode;
 697         u32 rsvd[26];
 698 };
 699
 700 extern int be_pci_fnum_get(struct be_ctrl_info *ctrl);
 701 extern int be_cmd_POST(struct be_ctrl_info *ctrl);
 702 extern int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr,
 703                         u8 type, bool permanent, u32 if_handle);
 704 extern int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr,
 705                         u32 if_id, u32 *pmac_id);
 706 extern int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id);
 707 extern int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 if_flags, u8 *mac,
 708                         bool pmac_invalid, u32 *if_handle, u32 *pmac_id);
 709 extern int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 if_handle);
 710 extern int be_cmd_eq_create(struct be_ctrl_info *ctrl,
 711                         struct be_queue_info *eq, int eq_delay);
 712 extern int be_cmd_cq_create(struct be_ctrl_info *ctrl,
 713                         struct be_queue_info *cq, struct be_queue_info *eq,
 714                         bool sol_evts, bool no_delay,
 715                         int num_cqe_dma_coalesce);
 716 extern int be_cmd_mccq_create(struct be_ctrl_info *ctrl,
 717                         struct be_queue_info *mccq,
 718                         struct be_queue_info *cq);
 719 extern int be_cmd_txq_create(struct be_ctrl_info *ctrl,
 720                         struct be_queue_info *txq,
 721                         struct be_queue_info *cq);
 722 extern int be_cmd_rxq_create(struct be_ctrl_info *ctrl,
 723                         struct be_queue_info *rxq, u16 cq_id,
 724                         u16 frag_size, u16 max_frame_size, u32 if_id,
 725                         u32 rss);
 726 extern int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
 727                         int type);
 728 extern int be_cmd_link_status_query(struct be_ctrl_info *ctrl,
 729                         bool *link_up);
 730 extern int be_cmd_reset(struct be_ctrl_info *ctrl);
 731 extern int be_cmd_get_stats(struct be_ctrl_info *ctrl,
 732                         struct be_dma_mem *nonemb_cmd);
 733 extern int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver);
 734
 735 extern int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd);
 736 extern int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id,
 737                         u16 *vtag_array, u32 num, bool untagged,
 738                         bool promiscuous);
 739 extern int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl,
 740                         u8 port_num, bool en);
 741 extern int be_cmd_multicast_set(struct be_ctrl_info *ctrl, u32 if_id,
 742                         struct dev_mc_list *mc_list, u32 mc_count);
 743 extern int be_cmd_set_flow_control(struct be_ctrl_info *ctrl,
 744                         u32 tx_fc, u32 rx_fc);
 745 extern int be_cmd_get_flow_control(struct be_ctrl_info *ctrl,
 746                         u32 *tx_fc, u32 *rx_fc);
 747 extern int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num);
 748 extern void be_process_mcc(struct be_ctrl_info *ctrl);