drivers/net/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 static void be_mcc_notify(struct be_adapter *adapter)
  22 {
  23         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  24         u32 val = 0;
  25
  26         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  27         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  28         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  29 }
  30
  31 /* To check if valid bit is set, check the entire word as we don't know
  32  * the endianness of the data (old entry is host endian while a new entry is
  33  * little endian) */
  34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  35 {
  36         if (compl->flags != 0) {
  37                 compl->flags = le32_to_cpu(compl->flags);
  38                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  39                 return true;
  40         } else {
  41                 return false;
  42         }
  43 }
  44
  45 /* Need to reset the entire word that houses the valid bit */
  46 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  47 {
  48         compl->flags = 0;
  49 }
  50
  51 static int be_mcc_compl_process(struct be_adapter *adapter,
  52         struct be_mcc_compl *compl)
  53 {
  54         u16 compl_status, extd_status;
  55
  56         /* Just swap the status to host endian; mcc tag is opaquely copied
  57          * from mcc_wrb */
  58         be_dws_le_to_cpu(compl, 4);
  59
  60         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  61                                 CQE_STATUS_COMPL_MASK;
  62         if (compl_status != MCC_STATUS_SUCCESS) {
  63                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
  64                                 CQE_STATUS_EXTD_MASK;
  65                 dev_warn(&adapter->pdev->dev,
  66                         "Error in cmd completion: status(compl/extd)=%d/%d\n",
  67                         compl_status, extd_status);
  68                 return -1;
  69         }
  70         return 0;
  71 }
  72
  73 /* Link state evt is a string of bytes; no need for endian swapping */
  74 static void be_async_link_state_process(struct be_adapter *adapter,
  75                 struct be_async_event_link_state *evt)
  76 {
  77         be_link_status_update(adapter,
  78                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
  79 }
  80
  81 static inline bool is_link_state_evt(u32 trailer)
  82 {
  83         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
  84                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
  85                                 ASYNC_EVENT_CODE_LINK_STATE);
  86 }
  87
  88 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
  89 {
  90         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
  91         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
  92
  93         if (be_mcc_compl_is_new(compl)) {
  94                 queue_tail_inc(mcc_cq);
  95                 return compl;
  96         }
  97         return NULL;
  98 }
  99
 100 void be_process_mcc(struct be_adapter *adapter)
 101 {
 102         struct be_mcc_compl *compl;
 103         int num = 0;
 104
 105         spin_lock_bh(&adapter->mcc_cq_lock);
 106         while ((compl = be_mcc_compl_get(adapter))) {
 107                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 108                         /* Interpret flags as an async trailer */
 109                         BUG_ON(!is_link_state_evt(compl->flags));
 110
 111                         /* Interpret compl as a async link evt */
 112                         be_async_link_state_process(adapter,
 113                                 (struct be_async_event_link_state *) compl);
 114                 } else {
 115                         be_mcc_compl_process(adapter, compl);
 116                         atomic_dec(&adapter->mcc_obj.q.used);
 117                 }
 118                 be_mcc_compl_use(compl);
 119                 num++;
 120         }
 121         if (num)
 122                 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, num);
 123         spin_unlock_bh(&adapter->mcc_cq_lock);
 124 }
 125
 126 /* Wait till no more pending mcc requests are present */
 127 static void be_mcc_wait_compl(struct be_adapter *adapter)
 128 {
 129 #define mcc_timeout             50000 /* 5s timeout */
 130         int i;
 131         for (i = 0; i < mcc_timeout; i++) {
 132                 be_process_mcc(adapter);
 133                 if (atomic_read(&adapter->mcc_obj.q.used) == 0)
 134                         break;
 135                 udelay(100);
 136         }
 137         if (i == mcc_timeout)
 138                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 139 }
 140
 141 /* Notify MCC requests and wait for completion */
 142 static void be_mcc_notify_wait(struct be_adapter *adapter)
 143 {
 144         be_mcc_notify(adapter);
 145         be_mcc_wait_compl(adapter);
 146 }
 147
 148 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 149 {
 150         int cnt = 0, wait = 5;
 151         u32 ready;
 152
 153         do {
 154                 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
 155                 if (ready)
 156                         break;
 157
 158                 if (cnt > 200000) {
 159                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 160                         return -1;
 161                 }
 162
 163                 if (cnt > 50)
 164                         wait = 200;
 165                 cnt += wait;
 166                 udelay(wait);
 167         } while (true);
 168
 169         return 0;
 170 }
 171
 172 /*
 173  * Insert the mailbox address into the doorbell in two steps
 174  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 175  */
 176 static int be_mbox_notify(struct be_adapter *adapter)
 177 {
 178         int status;
 179         u32 val = 0;
 180         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 181         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 182         struct be_mcc_mailbox *mbox = mbox_mem->va;
 183         struct be_mcc_compl *compl = &mbox->compl;
 184
 185         memset(compl, 0, sizeof(*compl));
 186
 187         val |= MPU_MAILBOX_DB_HI_MASK;
 188         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 189         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 190         iowrite32(val, db);
 191
 192         /* wait for ready to be set */
 193         status = be_mbox_db_ready_wait(adapter, db);
 194         if (status != 0)
 195                 return status;
 196
 197         val = 0;
 198         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 199         val |= (u32)(mbox_mem->dma >> 4) << 2;
 200         iowrite32(val, db);
 201
 202         status = be_mbox_db_ready_wait(adapter, db);
 203         if (status != 0)
 204                 return status;
 205
 206         /* A cq entry has been made now */
 207         if (be_mcc_compl_is_new(compl)) {
 208                 status = be_mcc_compl_process(adapter, &mbox->compl);
 209                 be_mcc_compl_use(compl);
 210                 if (status)
 211                         return status;
 212         } else {
 213                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 214                 return -1;
 215         }
 216         return 0;
 217 }
 218
 219 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 220 {
 221         u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 222
 223         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 224         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 225                 return -1;
 226         else
 227                 return 0;
 228 }
 229
 230 static int be_POST_stage_poll(struct be_adapter *adapter, u16 poll_stage)
 231 {
 232         u16 stage, cnt, error;
 233         for (cnt = 0; cnt < 5000; cnt++) {
 234                 error = be_POST_stage_get(adapter, &stage);
 235                 if (error)
 236                         return -1;
 237
 238                 if (stage == poll_stage)
 239                         break;
 240                 udelay(1000);
 241         }
 242         if (stage != poll_stage)
 243                 return -1;
 244         return 0;
 245 }
 246
 247
 248 int be_cmd_POST(struct be_adapter *adapter)
 249 {
 250         u16 stage, error;
 251
 252         error = be_POST_stage_get(adapter, &stage);
 253         if (error)
 254                 goto err;
 255
 256         if (stage == POST_STAGE_ARMFW_RDY)
 257                 return 0;
 258
 259         if (stage != POST_STAGE_AWAITING_HOST_RDY)
 260                 goto err;
 261
 262         /* On awaiting host rdy, reset and again poll on awaiting host rdy */
 263         iowrite32(POST_STAGE_BE_RESET, adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 264         error = be_POST_stage_poll(adapter, POST_STAGE_AWAITING_HOST_RDY);
 265         if (error)
 266                 goto err;
 267
 268         /* Now kickoff POST and poll on armfw ready */
 269         iowrite32(POST_STAGE_HOST_RDY, adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 270         error = be_POST_stage_poll(adapter, POST_STAGE_ARMFW_RDY);
 271         if (error)
 272                 goto err;
 273
 274         return 0;
 275 err:
 276         printk(KERN_WARNING DRV_NAME ": ERROR, stage=%d\n", stage);
 277         return -1;
 278 }
 279
 280 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 281 {
 282         return wrb->payload.embedded_payload;
 283 }
 284
 285 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 286 {
 287         return &wrb->payload.sgl[0];
 288 }
 289
 290 /* Don't touch the hdr after it's prepared */
 291 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 292                                 bool embedded, u8 sge_cnt)
 293 {
 294         if (embedded)
 295                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 296         else
 297                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 298                                 MCC_WRB_SGE_CNT_SHIFT;
 299         wrb->payload_length = payload_len;
 300         be_dws_cpu_to_le(wrb, 20);
 301 }
 302
 303 /* Don't touch the hdr after it's prepared */
 304 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 305                                 u8 subsystem, u8 opcode, int cmd_len)
 306 {
 307         req_hdr->opcode = opcode;
 308         req_hdr->subsystem = subsystem;
 309         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 310 }
 311
 312 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 313                         struct be_dma_mem *mem)
 314 {
 315         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 316         u64 dma = (u64)mem->dma;
 317
 318         for (i = 0; i < buf_pages; i++) {
 319                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 320                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 321                 dma += PAGE_SIZE_4K;
 322         }
 323 }
 324
 325 /* Converts interrupt delay in microseconds to multiplier value */
 326 static u32 eq_delay_to_mult(u32 usec_delay)
 327 {
 328 #define MAX_INTR_RATE                   651042
 329         const u32 round = 10;
 330         u32 multiplier;
 331
 332         if (usec_delay == 0)
 333                 multiplier = 0;
 334         else {
 335                 u32 interrupt_rate = 1000000 / usec_delay;
 336                 /* Max delay, corresponding to the lowest interrupt rate */
 337                 if (interrupt_rate == 0)
 338                         multiplier = 1023;
 339                 else {
 340                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 341                         multiplier /= interrupt_rate;
 342                         /* Round the multiplier to the closest value.*/
 343                         multiplier = (multiplier + round/2) / round;
 344                         multiplier = min(multiplier, (u32)1023);
 345                 }
 346         }
 347         return multiplier;
 348 }
 349
 350 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
 351 {
 352         return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 353 }
 354
 355 static inline struct be_mcc_wrb *wrb_from_mcc(struct be_queue_info *mccq)
 356 {
 357         struct be_mcc_wrb *wrb = NULL;
 358         if (atomic_read(&mccq->used) < mccq->len) {
 359                 wrb = queue_head_node(mccq);
 360                 queue_head_inc(mccq);
 361                 atomic_inc(&mccq->used);
 362                 memset(wrb, 0, sizeof(*wrb));
 363         }
 364         return wrb;
 365 }
 366
 367 int be_cmd_eq_create(struct be_adapter *adapter,
 368                 struct be_queue_info *eq, int eq_delay)
 369 {
 370         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 371         struct be_cmd_req_eq_create *req = embedded_payload(wrb);
 372         struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 373         struct be_dma_mem *q_mem = &eq->dma_mem;
 374         int status;
 375
 376         spin_lock(&adapter->mbox_lock);
 377         memset(wrb, 0, sizeof(*wrb));
 378
 379         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 380
 381         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 382                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 383
 384         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 385
 386         AMAP_SET_BITS(struct amap_eq_context, func, req->context,
 387                         be_pci_func(adapter));
 388         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 389         /* 4byte eqe*/
 390         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 391         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 392                         __ilog2_u32(eq->len/256));
 393         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 394                         eq_delay_to_mult(eq_delay));
 395         be_dws_cpu_to_le(req->context, sizeof(req->context));
 396
 397         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 398
 399         status = be_mbox_notify(adapter);
 400         if (!status) {
 401                 eq->id = le16_to_cpu(resp->eq_id);
 402                 eq->created = true;
 403         }
 404         spin_unlock(&adapter->mbox_lock);
 405         return status;
 406 }
 407
 408 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 409                         u8 type, bool permanent, u32 if_handle)
 410 {
 411         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 412         struct be_cmd_req_mac_query *req = embedded_payload(wrb);
 413         struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 414         int status;
 415
 416         spin_lock(&adapter->mbox_lock);
 417         memset(wrb, 0, sizeof(*wrb));
 418
 419         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 420
 421         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 422                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
 423
 424         req->type = type;
 425         if (permanent) {
 426                 req->permanent = 1;
 427         } else {
 428                 req->if_id = cpu_to_le16((u16)if_handle);
 429                 req->permanent = 0;
 430         }
 431
 432         status = be_mbox_notify(adapter);
 433         if (!status)
 434                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 435
 436         spin_unlock(&adapter->mbox_lock);
 437         return status;
 438 }
 439
 440 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 441                 u32 if_id, u32 *pmac_id)
 442 {
 443         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 444         struct be_cmd_req_pmac_add *req = embedded_payload(wrb);
 445         int status;
 446
 447         spin_lock(&adapter->mbox_lock);
 448         memset(wrb, 0, sizeof(*wrb));
 449
 450         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 451
 452         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 453                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
 454
 455         req->if_id = cpu_to_le32(if_id);
 456         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 457
 458         status = be_mbox_notify(adapter);
 459         if (!status) {
 460                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 461                 *pmac_id = le32_to_cpu(resp->pmac_id);
 462         }
 463
 464         spin_unlock(&adapter->mbox_lock);
 465         return status;
 466 }
 467
 468 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
 469 {
 470         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 471         struct be_cmd_req_pmac_del *req = embedded_payload(wrb);
 472         int status;
 473
 474         spin_lock(&adapter->mbox_lock);
 475         memset(wrb, 0, sizeof(*wrb));
 476
 477         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 478
 479         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 480                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
 481
 482         req->if_id = cpu_to_le32(if_id);
 483         req->pmac_id = cpu_to_le32(pmac_id);
 484
 485         status = be_mbox_notify(adapter);
 486         spin_unlock(&adapter->mbox_lock);
 487
 488         return status;
 489 }
 490
 491 int be_cmd_cq_create(struct be_adapter *adapter,
 492                 struct be_queue_info *cq, struct be_queue_info *eq,
 493                 bool sol_evts, bool no_delay, int coalesce_wm)
 494 {
 495         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 496         struct be_cmd_req_cq_create *req = embedded_payload(wrb);
 497         struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 498         struct be_dma_mem *q_mem = &cq->dma_mem;
 499         void *ctxt = &req->context;
 500         int status;
 501
 502         spin_lock(&adapter->mbox_lock);
 503         memset(wrb, 0, sizeof(*wrb));
 504
 505         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 506
 507         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 508                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 509
 510         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 511
 512         AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
 513         AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
 514         AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
 515                         __ilog2_u32(cq->len/256));
 516         AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
 517         AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
 518         AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
 519         AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
 520         AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
 521         AMAP_SET_BITS(struct amap_cq_context, func, ctxt, be_pci_func(adapter));
 522         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 523
 524         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 525
 526         status = be_mbox_notify(adapter);
 527         if (!status) {
 528                 cq->id = le16_to_cpu(resp->cq_id);
 529                 cq->created = true;
 530         }
 531         spin_unlock(&adapter->mbox_lock);
 532
 533         return status;
 534 }
 535
 536 static u32 be_encoded_q_len(int q_len)
 537 {
 538         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 539         if (len_encoded == 16)
 540                 len_encoded = 0;
 541         return len_encoded;
 542 }
 543
 544 int be_cmd_mccq_create(struct be_adapter *adapter,
 545                         struct be_queue_info *mccq,
 546                         struct be_queue_info *cq)
 547 {
 548         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 549         struct be_cmd_req_mcc_create *req = embedded_payload(wrb);
 550         struct be_dma_mem *q_mem = &mccq->dma_mem;
 551         void *ctxt = &req->context;
 552         int status;
 553
 554         spin_lock(&adapter->mbox_lock);
 555         memset(wrb, 0, sizeof(*wrb));
 556
 557         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 558
 559         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 560                         OPCODE_COMMON_MCC_CREATE, sizeof(*req));
 561
 562         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 563
 564         AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, be_pci_func(adapter));
 565         AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
 566         AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
 567                 be_encoded_q_len(mccq->len));
 568         AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
 569
 570         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 571
 572         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 573
 574         status = be_mbox_notify(adapter);
 575         if (!status) {
 576                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 577                 mccq->id = le16_to_cpu(resp->id);
 578                 mccq->created = true;
 579         }
 580         spin_unlock(&adapter->mbox_lock);
 581
 582         return status;
 583 }
 584
 585 int be_cmd_txq_create(struct be_adapter *adapter,
 586                         struct be_queue_info *txq,
 587                         struct be_queue_info *cq)
 588 {
 589         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 590         struct be_cmd_req_eth_tx_create *req = embedded_payload(wrb);
 591         struct be_dma_mem *q_mem = &txq->dma_mem;
 592         void *ctxt = &req->context;
 593         int status;
 594         u32 len_encoded;
 595
 596         spin_lock(&adapter->mbox_lock);
 597         memset(wrb, 0, sizeof(*wrb));
 598
 599         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 600
 601         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
 602                 sizeof(*req));
 603
 604         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 605         req->ulp_num = BE_ULP1_NUM;
 606         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 607
 608         len_encoded = fls(txq->len); /* log2(len) + 1 */
 609         if (len_encoded == 16)
 610                 len_encoded = 0;
 611         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, len_encoded);
 612         AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
 613                         be_pci_func(adapter));
 614         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 615         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 616
 617         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 618
 619         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 620
 621         status = be_mbox_notify(adapter);
 622         if (!status) {
 623                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 624                 txq->id = le16_to_cpu(resp->cid);
 625                 txq->created = true;
 626         }
 627         spin_unlock(&adapter->mbox_lock);
 628
 629         return status;
 630 }
 631
 632 int be_cmd_rxq_create(struct be_adapter *adapter,
 633                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 634                 u16 max_frame_size, u32 if_id, u32 rss)
 635 {
 636         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 637         struct be_cmd_req_eth_rx_create *req = embedded_payload(wrb);
 638         struct be_dma_mem *q_mem = &rxq->dma_mem;
 639         int status;
 640
 641         spin_lock(&adapter->mbox_lock);
 642         memset(wrb, 0, sizeof(*wrb));
 643
 644         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 645
 646         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
 647                 sizeof(*req));
 648
 649         req->cq_id = cpu_to_le16(cq_id);
 650         req->frag_size = fls(frag_size) - 1;
 651         req->num_pages = 2;
 652         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 653         req->interface_id = cpu_to_le32(if_id);
 654         req->max_frame_size = cpu_to_le16(max_frame_size);
 655         req->rss_queue = cpu_to_le32(rss);
 656
 657         status = be_mbox_notify(adapter);
 658         if (!status) {
 659                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
 660                 rxq->id = le16_to_cpu(resp->id);
 661                 rxq->created = true;
 662         }
 663         spin_unlock(&adapter->mbox_lock);
 664
 665         return status;
 666 }
 667
 668 /* Generic destroyer function for all types of queues */
 669 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 670                 int queue_type)
 671 {
 672         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 673         struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
 674         u8 subsys = 0, opcode = 0;
 675         int status;
 676
 677         spin_lock(&adapter->mbox_lock);
 678
 679         memset(wrb, 0, sizeof(*wrb));
 680         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 681
 682         switch (queue_type) {
 683         case QTYPE_EQ:
 684                 subsys = CMD_SUBSYSTEM_COMMON;
 685                 opcode = OPCODE_COMMON_EQ_DESTROY;
 686                 break;
 687         case QTYPE_CQ:
 688                 subsys = CMD_SUBSYSTEM_COMMON;
 689                 opcode = OPCODE_COMMON_CQ_DESTROY;
 690                 break;
 691         case QTYPE_TXQ:
 692                 subsys = CMD_SUBSYSTEM_ETH;
 693                 opcode = OPCODE_ETH_TX_DESTROY;
 694                 break;
 695         case QTYPE_RXQ:
 696                 subsys = CMD_SUBSYSTEM_ETH;
 697                 opcode = OPCODE_ETH_RX_DESTROY;
 698                 break;
 699         case QTYPE_MCCQ:
 700                 subsys = CMD_SUBSYSTEM_COMMON;
 701                 opcode = OPCODE_COMMON_MCC_DESTROY;
 702                 break;
 703         default:
 704                 BUG();
 705         }
 706         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
 707         req->id = cpu_to_le16(q->id);
 708
 709         status = be_mbox_notify(adapter);
 710
 711         spin_unlock(&adapter->mbox_lock);
 712
 713         return status;
 714 }
 715
 716 /* Create an rx filtering policy configuration on an i/f */
 717 int be_cmd_if_create(struct be_adapter *adapter, u32 flags, u8 *mac,
 718                 bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
 719 {
 720         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 721         struct be_cmd_req_if_create *req = embedded_payload(wrb);
 722         int status;
 723
 724         spin_lock(&adapter->mbox_lock);
 725         memset(wrb, 0, sizeof(*wrb));
 726
 727         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 728
 729         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 730                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
 731
 732         req->capability_flags = cpu_to_le32(flags);
 733         req->enable_flags = cpu_to_le32(flags);
 734         if (!pmac_invalid)
 735                 memcpy(req->mac_addr, mac, ETH_ALEN);
 736
 737         status = be_mbox_notify(adapter);
 738         if (!status) {
 739                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
 740                 *if_handle = le32_to_cpu(resp->interface_id);
 741                 if (!pmac_invalid)
 742                         *pmac_id = le32_to_cpu(resp->pmac_id);
 743         }
 744
 745         spin_unlock(&adapter->mbox_lock);
 746         return status;
 747 }
 748
 749 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
 750 {
 751         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 752         struct be_cmd_req_if_destroy *req = embedded_payload(wrb);
 753         int status;
 754
 755         spin_lock(&adapter->mbox_lock);
 756         memset(wrb, 0, sizeof(*wrb));
 757
 758         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 759
 760         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 761                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
 762
 763         req->interface_id = cpu_to_le32(interface_id);
 764         status = be_mbox_notify(adapter);
 765
 766         spin_unlock(&adapter->mbox_lock);
 767
 768         return status;
 769 }
 770
 771 /* Get stats is a non embedded command: the request is not embedded inside
 772  * WRB but is a separate dma memory block
 773  */
 774 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
 775 {
 776         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 777         struct be_cmd_req_get_stats *req = nonemb_cmd->va;
 778         struct be_sge *sge = nonembedded_sgl(wrb);
 779         int status;
 780
 781         spin_lock(&adapter->mbox_lock);
 782         memset(wrb, 0, sizeof(*wrb));
 783
 784         memset(req, 0, sizeof(*req));
 785
 786         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1);
 787
 788         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
 789                 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
 790         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
 791         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
 792         sge->len = cpu_to_le32(nonemb_cmd->size);
 793
 794         status = be_mbox_notify(adapter);
 795         if (!status) {
 796                 struct be_cmd_resp_get_stats *resp = nonemb_cmd->va;
 797                 be_dws_le_to_cpu(&resp->hw_stats, sizeof(resp->hw_stats));
 798         }
 799
 800         spin_unlock(&adapter->mbox_lock);
 801         return status;
 802 }
 803
 804 int be_cmd_link_status_query(struct be_adapter *adapter,
 805                         bool *link_up)
 806 {
 807         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 808         struct be_cmd_req_link_status *req = embedded_payload(wrb);
 809         int status;
 810
 811         spin_lock(&adapter->mbox_lock);
 812
 813         *link_up = false;
 814         memset(wrb, 0, sizeof(*wrb));
 815
 816         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 817
 818         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 819                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
 820
 821         status = be_mbox_notify(adapter);
 822         if (!status) {
 823                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
 824                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO)
 825                         *link_up = true;
 826         }
 827
 828         spin_unlock(&adapter->mbox_lock);
 829         return status;
 830 }
 831
 832 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
 833 {
 834         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 835         struct be_cmd_req_get_fw_version *req = embedded_payload(wrb);
 836         int status;
 837
 838         spin_lock(&adapter->mbox_lock);
 839         memset(wrb, 0, sizeof(*wrb));
 840
 841         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 842
 843         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 844                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
 845
 846         status = be_mbox_notify(adapter);
 847         if (!status) {
 848                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
 849                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
 850         }
 851
 852         spin_unlock(&adapter->mbox_lock);
 853         return status;
 854 }
 855
 856 /* set the EQ delay interval of an EQ to specified value */
 857 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
 858 {
 859         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 860         struct be_cmd_req_modify_eq_delay *req = embedded_payload(wrb);
 861         int status;
 862
 863         spin_lock(&adapter->mbox_lock);
 864         memset(wrb, 0, sizeof(*wrb));
 865
 866         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 867
 868         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 869                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
 870
 871         req->num_eq = cpu_to_le32(1);
 872         req->delay[0].eq_id = cpu_to_le32(eq_id);
 873         req->delay[0].phase = 0;
 874         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
 875
 876         status = be_mbox_notify(adapter);
 877
 878         spin_unlock(&adapter->mbox_lock);
 879         return status;
 880 }
 881
 882 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
 883                         u32 num, bool untagged, bool promiscuous)
 884 {
 885         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 886         struct be_cmd_req_vlan_config *req = embedded_payload(wrb);
 887         int status;
 888
 889         spin_lock(&adapter->mbox_lock);
 890         memset(wrb, 0, sizeof(*wrb));
 891
 892         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 893
 894         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 895                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
 896
 897         req->interface_id = if_id;
 898         req->promiscuous = promiscuous;
 899         req->untagged = untagged;
 900         req->num_vlan = num;
 901         if (!promiscuous) {
 902                 memcpy(req->normal_vlan, vtag_array,
 903                         req->num_vlan * sizeof(vtag_array[0]));
 904         }
 905
 906         status = be_mbox_notify(adapter);
 907
 908         spin_unlock(&adapter->mbox_lock);
 909         return status;
 910 }
 911
 912 /* Use MCC for this command as it may be called in BH context */
 913 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
 914 {
 915         struct be_mcc_wrb *wrb;
 916         struct be_cmd_req_promiscuous_config *req;
 917
 918         spin_lock_bh(&adapter->mcc_lock);
 919
 920         wrb = wrb_from_mcc(&adapter->mcc_obj.q);
 921         BUG_ON(!wrb);
 922
 923         req = embedded_payload(wrb);
 924
 925         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 926
 927         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
 928                 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
 929
 930         if (port_num)
 931                 req->port1_promiscuous = en;
 932         else
 933                 req->port0_promiscuous = en;
 934
 935         be_mcc_notify_wait(adapter);
 936
 937         spin_unlock_bh(&adapter->mcc_lock);
 938         return 0;
 939 }
 940
 941 /*
 942  * Use MCC for this command as it may be called in BH context
 943  * (mc == NULL) => multicast promiscous
 944  */
 945 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
 946                 struct dev_mc_list *mc_list, u32 mc_count)
 947 {
 948 #define BE_MAX_MC               32 /* set mcast promisc if > 32 */
 949         struct be_mcc_wrb *wrb;
 950         struct be_cmd_req_mcast_mac_config *req;
 951
 952         spin_lock_bh(&adapter->mcc_lock);
 953
 954         wrb = wrb_from_mcc(&adapter->mcc_obj.q);
 955         BUG_ON(!wrb);
 956
 957         req = embedded_payload(wrb);
 958
 959         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 960
 961         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 962                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
 963
 964         req->interface_id = if_id;
 965         if (mc_list && mc_count <= BE_MAX_MC) {
 966                 int i;
 967                 struct dev_mc_list *mc;
 968
 969                 req->num_mac = cpu_to_le16(mc_count);
 970
 971                 for (mc = mc_list, i = 0; mc; mc = mc->next, i++)
 972                         memcpy(req->mac[i].byte, mc->dmi_addr, ETH_ALEN);
 973         } else {
 974                 req->promiscuous = 1;
 975         }
 976
 977         be_mcc_notify_wait(adapter);
 978
 979         spin_unlock_bh(&adapter->mcc_lock);
 980
 981         return 0;
 982 }
 983
 984 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
 985 {
 986         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
 987         struct be_cmd_req_set_flow_control *req = embedded_payload(wrb);
 988         int status;
 989
 990         spin_lock(&adapter->mbox_lock);
 991
 992         memset(wrb, 0, sizeof(*wrb));
 993
 994         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
 995
 996         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 997                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
 998
 999         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1000         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1001
1002         status = be_mbox_notify(adapter);
1003
1004         spin_unlock(&adapter->mbox_lock);
1005         return status;
1006 }
1007
1008 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1009 {
1010         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
1011         struct be_cmd_req_get_flow_control *req = embedded_payload(wrb);
1012         int status;
1013
1014         spin_lock(&adapter->mbox_lock);
1015
1016         memset(wrb, 0, sizeof(*wrb));
1017
1018         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1019
1020         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1021                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1022
1023         status = be_mbox_notify(adapter);
1024         if (!status) {
1025                 struct be_cmd_resp_get_flow_control *resp =
1026                                                 embedded_payload(wrb);
1027                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1028                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1029         }
1030
1031         spin_unlock(&adapter->mbox_lock);
1032         return status;
1033 }
1034
1035 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num)
1036 {
1037         struct be_mcc_wrb *wrb = wrb_from_mbox(&adapter->mbox_mem);
1038         struct be_cmd_req_query_fw_cfg *req = embedded_payload(wrb);
1039         int status;
1040
1041         spin_lock(&adapter->mbox_lock);
1042
1043         memset(wrb, 0, sizeof(*wrb));
1044
1045         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1046
1047         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1048                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1049
1050         status = be_mbox_notify(adapter);
1051         if (!status) {
1052                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1053                 *port_num = le32_to_cpu(resp->phys_port);
1054         }
1055
1056         spin_unlock(&adapter->mbox_lock);
1057         return status;
1058 }