drivers/net/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include "be.h"
  19 #include "be_cmds.h"
  20
  21 /* Must be a power of 2 or else MODULO will BUG_ON */
  22 static int be_get_temp_freq = 32;
  23
  24 static void be_mcc_notify(struct be_adapter *adapter)
  25 {
  26         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  27         u32 val = 0;
  28
  29         if (adapter->eeh_err) {
  30                 dev_info(&adapter->pdev->dev,
  31                         "Error in Card Detected! Cannot issue commands\n");
  32                 return;
  33         }
  34
  35         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
  36         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
  37
  38         wmb();
  39         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
  40 }
  41
  42 /* To check if valid bit is set, check the entire word as we don't know
  43  * the endianness of the data (old entry is host endian while a new entry is
  44  * little endian) */
  45 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
  46 {
  47         if (compl->flags != 0) {
  48                 compl->flags = le32_to_cpu(compl->flags);
  49                 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
  50                 return true;
  51         } else {
  52                 return false;
  53         }
  54 }
  55
  56 /* Need to reset the entire word that houses the valid bit */
  57 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
  58 {
  59         compl->flags = 0;
  60 }
  61
  62 static int be_mcc_compl_process(struct be_adapter *adapter,
  63         struct be_mcc_compl *compl)
  64 {
  65         u16 compl_status, extd_status;
  66
  67         /* Just swap the status to host endian; mcc tag is opaquely copied
  68          * from mcc_wrb */
  69         be_dws_le_to_cpu(compl, 4);
  70
  71         compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
  72                                 CQE_STATUS_COMPL_MASK;
  73
  74         if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
  75                 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
  76                 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
  77                 adapter->flash_status = compl_status;
  78                 complete(&adapter->flash_compl);
  79         }
  80
  81         if (compl_status == MCC_STATUS_SUCCESS) {
  82                 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
  83                          (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
  84                         (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
  85                         if (adapter->generation == BE_GEN3) {
  86                                 if (lancer_chip(adapter)) {
  87                                         struct lancer_cmd_resp_pport_stats
  88                                                 *resp = adapter->stats_cmd.va;
  89                                         be_dws_le_to_cpu(&resp->pport_stats,
  90                                                 sizeof(resp->pport_stats));
  91                                 } else {
  92                                         struct be_cmd_resp_get_stats_v1 *resp =
  93                                                         adapter->stats_cmd.va;
  94
  95                                 be_dws_le_to_cpu(&resp->hw_stats,
  96                                                         sizeof(resp->hw_stats));
  97                                 }
  98                         } else {
  99                                 struct be_cmd_resp_get_stats_v0 *resp =
 100                                                         adapter->stats_cmd.va;
 101
 102                                 be_dws_le_to_cpu(&resp->hw_stats,
 103                                                         sizeof(resp->hw_stats));
 104                         }
 105                         be_parse_stats(adapter);
 106                         netdev_stats_update(adapter);
 107                         adapter->stats_cmd_sent = false;
 108                 }
 109         } else if ((compl_status != MCC_STATUS_NOT_SUPPORTED) &&
 110                    (compl->tag0 != OPCODE_COMMON_NTWK_MAC_QUERY)) {
 111                 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
 112                                 CQE_STATUS_EXTD_MASK;
 113                 dev_warn(&adapter->pdev->dev,
 114                 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
 115                         compl->tag0, compl_status, extd_status);
 116         }
 117         return compl_status;
 118 }
 119
 120 /* Link state evt is a string of bytes; no need for endian swapping */
 121 static void be_async_link_state_process(struct be_adapter *adapter,
 122                 struct be_async_event_link_state *evt)
 123 {
 124         be_link_status_update(adapter,
 125                 evt->port_link_status == ASYNC_EVENT_LINK_UP);
 126 }
 127
 128 /* Grp5 CoS Priority evt */
 129 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 130                 struct be_async_event_grp5_cos_priority *evt)
 131 {
 132         if (evt->valid) {
 133                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 134                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 135                 adapter->recommended_prio =
 136                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 137         }
 138 }
 139
 140 /* Grp5 QOS Speed evt */
 141 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 142                 struct be_async_event_grp5_qos_link_speed *evt)
 143 {
 144         if (evt->physical_port == adapter->port_num) {
 145                 /* qos_link_speed is in units of 10 Mbps */
 146                 adapter->link_speed = evt->qos_link_speed * 10;
 147         }
 148 }
 149
 150 /*Grp5 PVID evt*/
 151 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 152                 struct be_async_event_grp5_pvid_state *evt)
 153 {
 154         if (evt->enabled)
 155                 adapter->pvid = le16_to_cpu(evt->tag);
 156         else
 157                 adapter->pvid = 0;
 158 }
 159
 160 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 161                 u32 trailer, struct be_mcc_compl *evt)
 162 {
 163         u8 event_type = 0;
 164
 165         event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
 166                 ASYNC_TRAILER_EVENT_TYPE_MASK;
 167
 168         switch (event_type) {
 169         case ASYNC_EVENT_COS_PRIORITY:
 170                 be_async_grp5_cos_priority_process(adapter,
 171                 (struct be_async_event_grp5_cos_priority *)evt);
 172         break;
 173         case ASYNC_EVENT_QOS_SPEED:
 174                 be_async_grp5_qos_speed_process(adapter,
 175                 (struct be_async_event_grp5_qos_link_speed *)evt);
 176         break;
 177         case ASYNC_EVENT_PVID_STATE:
 178                 be_async_grp5_pvid_state_process(adapter,
 179                 (struct be_async_event_grp5_pvid_state *)evt);
 180         break;
 181         default:
 182                 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
 183                 break;
 184         }
 185 }
 186
 187 static inline bool is_link_state_evt(u32 trailer)
 188 {
 189         return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 190                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 191                                 ASYNC_EVENT_CODE_LINK_STATE;
 192 }
 193
 194 static inline bool is_grp5_evt(u32 trailer)
 195 {
 196         return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
 197                 ASYNC_TRAILER_EVENT_CODE_MASK) ==
 198                                 ASYNC_EVENT_CODE_GRP_5);
 199 }
 200
 201 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 202 {
 203         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 204         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 205
 206         if (be_mcc_compl_is_new(compl)) {
 207                 queue_tail_inc(mcc_cq);
 208                 return compl;
 209         }
 210         return NULL;
 211 }
 212
 213 void be_async_mcc_enable(struct be_adapter *adapter)
 214 {
 215         spin_lock_bh(&adapter->mcc_cq_lock);
 216
 217         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 218         adapter->mcc_obj.rearm_cq = true;
 219
 220         spin_unlock_bh(&adapter->mcc_cq_lock);
 221 }
 222
 223 void be_async_mcc_disable(struct be_adapter *adapter)
 224 {
 225         adapter->mcc_obj.rearm_cq = false;
 226 }
 227
 228 int be_process_mcc(struct be_adapter *adapter, int *status)
 229 {
 230         struct be_mcc_compl *compl;
 231         int num = 0;
 232         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 233
 234         spin_lock_bh(&adapter->mcc_cq_lock);
 235         while ((compl = be_mcc_compl_get(adapter))) {
 236                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 237                         /* Interpret flags as an async trailer */
 238                         if (is_link_state_evt(compl->flags))
 239                                 be_async_link_state_process(adapter,
 240                                 (struct be_async_event_link_state *) compl);
 241                         else if (is_grp5_evt(compl->flags))
 242                                 be_async_grp5_evt_process(adapter,
 243                                 compl->flags, compl);
 244                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 245                                 *status = be_mcc_compl_process(adapter, compl);
 246                                 atomic_dec(&mcc_obj->q.used);
 247                 }
 248                 be_mcc_compl_use(compl);
 249                 num++;
 250         }
 251
 252         spin_unlock_bh(&adapter->mcc_cq_lock);
 253         return num;
 254 }
 255
 256 /* Wait till no more pending mcc requests are present */
 257 static int be_mcc_wait_compl(struct be_adapter *adapter)
 258 {
 259 #define mcc_timeout             120000 /* 12s timeout */
 260         int i, num, status = 0;
 261         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 262
 263         if (adapter->eeh_err)
 264                 return -EIO;
 265
 266         for (i = 0; i < mcc_timeout; i++) {
 267                 num = be_process_mcc(adapter, &status);
 268                 if (num)
 269                         be_cq_notify(adapter, mcc_obj->cq.id,
 270                                 mcc_obj->rearm_cq, num);
 271
 272                 if (atomic_read(&mcc_obj->q.used) == 0)
 273                         break;
 274                 udelay(100);
 275         }
 276         if (i == mcc_timeout) {
 277                 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
 278                 return -1;
 279         }
 280         return status;
 281 }
 282
 283 /* Notify MCC requests and wait for completion */
 284 static int be_mcc_notify_wait(struct be_adapter *adapter)
 285 {
 286         be_mcc_notify(adapter);
 287         return be_mcc_wait_compl(adapter);
 288 }
 289
 290 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 291 {
 292         int msecs = 0;
 293         u32 ready;
 294
 295         if (adapter->eeh_err) {
 296                 dev_err(&adapter->pdev->dev,
 297                         "Error detected in card.Cannot issue commands\n");
 298                 return -EIO;
 299         }
 300
 301         do {
 302                 ready = ioread32(db);
 303                 if (ready == 0xffffffff) {
 304                         dev_err(&adapter->pdev->dev,
 305                                 "pci slot disconnected\n");
 306                         return -1;
 307                 }
 308
 309                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 310                 if (ready)
 311                         break;
 312
 313                 if (msecs > 4000) {
 314                         dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
 315                         if (!lancer_chip(adapter))
 316                                 be_detect_dump_ue(adapter);
 317                         return -1;
 318                 }
 319
 320                 msleep(1);
 321                 msecs++;
 322         } while (true);
 323
 324         return 0;
 325 }
 326
 327 /*
 328  * Insert the mailbox address into the doorbell in two steps
 329  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 330  */
 331 static int be_mbox_notify_wait(struct be_adapter *adapter)
 332 {
 333         int status;
 334         u32 val = 0;
 335         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 336         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 337         struct be_mcc_mailbox *mbox = mbox_mem->va;
 338         struct be_mcc_compl *compl = &mbox->compl;
 339
 340         /* wait for ready to be set */
 341         status = be_mbox_db_ready_wait(adapter, db);
 342         if (status != 0)
 343                 return status;
 344
 345         val |= MPU_MAILBOX_DB_HI_MASK;
 346         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 347         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 348         iowrite32(val, db);
 349
 350         /* wait for ready to be set */
 351         status = be_mbox_db_ready_wait(adapter, db);
 352         if (status != 0)
 353                 return status;
 354
 355         val = 0;
 356         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 357         val |= (u32)(mbox_mem->dma >> 4) << 2;
 358         iowrite32(val, db);
 359
 360         status = be_mbox_db_ready_wait(adapter, db);
 361         if (status != 0)
 362                 return status;
 363
 364         /* A cq entry has been made now */
 365         if (be_mcc_compl_is_new(compl)) {
 366                 status = be_mcc_compl_process(adapter, &mbox->compl);
 367                 be_mcc_compl_use(compl);
 368                 if (status)
 369                         return status;
 370         } else {
 371                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 372                 return -1;
 373         }
 374         return 0;
 375 }
 376
 377 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 378 {
 379         u32 sem;
 380
 381         if (lancer_chip(adapter))
 382                 sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
 383         else
 384                 sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 385
 386         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
 387         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
 388                 return -1;
 389         else
 390                 return 0;
 391 }
 392
 393 int be_cmd_POST(struct be_adapter *adapter)
 394 {
 395         u16 stage;
 396         int status, timeout = 0;
 397         struct device *dev = &adapter->pdev->dev;
 398
 399         do {
 400                 status = be_POST_stage_get(adapter, &stage);
 401                 if (status) {
 402                         dev_err(dev, "POST error; stage=0x%x\n", stage);
 403                         return -1;
 404                 } else if (stage != POST_STAGE_ARMFW_RDY) {
 405                         if (msleep_interruptible(2000)) {
 406                                 dev_err(dev, "Waiting for POST aborted\n");
 407                                 return -EINTR;
 408                         }
 409                         timeout += 2;
 410                 } else {
 411                         return 0;
 412                 }
 413         } while (timeout < 40);
 414
 415         dev_err(dev, "POST timeout; stage=0x%x\n", stage);
 416         return -1;
 417 }
 418
 419 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
 420 {
 421         return wrb->payload.embedded_payload;
 422 }
 423
 424 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 425 {
 426         return &wrb->payload.sgl[0];
 427 }
 428
 429 /* Don't touch the hdr after it's prepared */
 430 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
 431                                 bool embedded, u8 sge_cnt, u32 opcode)
 432 {
 433         if (embedded)
 434                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 435         else
 436                 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
 437                                 MCC_WRB_SGE_CNT_SHIFT;
 438         wrb->payload_length = payload_len;
 439         wrb->tag0 = opcode;
 440         be_dws_cpu_to_le(wrb, 8);
 441 }
 442
 443 /* Don't touch the hdr after it's prepared */
 444 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 445                                 u8 subsystem, u8 opcode, int cmd_len)
 446 {
 447         req_hdr->opcode = opcode;
 448         req_hdr->subsystem = subsystem;
 449         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 450         req_hdr->version = 0;
 451 }
 452
 453 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 454                         struct be_dma_mem *mem)
 455 {
 456         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 457         u64 dma = (u64)mem->dma;
 458
 459         for (i = 0; i < buf_pages; i++) {
 460                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 461                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 462                 dma += PAGE_SIZE_4K;
 463         }
 464 }
 465
 466 /* Converts interrupt delay in microseconds to multiplier value */
 467 static u32 eq_delay_to_mult(u32 usec_delay)
 468 {
 469 #define MAX_INTR_RATE                   651042
 470         const u32 round = 10;
 471         u32 multiplier;
 472
 473         if (usec_delay == 0)
 474                 multiplier = 0;
 475         else {
 476                 u32 interrupt_rate = 1000000 / usec_delay;
 477                 /* Max delay, corresponding to the lowest interrupt rate */
 478                 if (interrupt_rate == 0)
 479                         multiplier = 1023;
 480                 else {
 481                         multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
 482                         multiplier /= interrupt_rate;
 483                         /* Round the multiplier to the closest value.*/
 484                         multiplier = (multiplier + round/2) / round;
 485                         multiplier = min(multiplier, (u32)1023);
 486                 }
 487         }
 488         return multiplier;
 489 }
 490
 491 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 492 {
 493         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 494         struct be_mcc_wrb *wrb
 495                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 496         memset(wrb, 0, sizeof(*wrb));
 497         return wrb;
 498 }
 499
 500 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 501 {
 502         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 503         struct be_mcc_wrb *wrb;
 504
 505         if (atomic_read(&mccq->used) >= mccq->len) {
 506                 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
 507                 return NULL;
 508         }
 509
 510         wrb = queue_head_node(mccq);
 511         queue_head_inc(mccq);
 512         atomic_inc(&mccq->used);
 513         memset(wrb, 0, sizeof(*wrb));
 514         return wrb;
 515 }
 516
 517 /* Tell fw we're about to start firing cmds by writing a
 518  * special pattern across the wrb hdr; uses mbox
 519  */
 520 int be_cmd_fw_init(struct be_adapter *adapter)
 521 {
 522         u8 *wrb;
 523         int status;
 524
 525         if (mutex_lock_interruptible(&adapter->mbox_lock))
 526                 return -1;
 527
 528         wrb = (u8 *)wrb_from_mbox(adapter);
 529         *wrb++ = 0xFF;
 530         *wrb++ = 0x12;
 531         *wrb++ = 0x34;
 532         *wrb++ = 0xFF;
 533         *wrb++ = 0xFF;
 534         *wrb++ = 0x56;
 535         *wrb++ = 0x78;
 536         *wrb = 0xFF;
 537
 538         status = be_mbox_notify_wait(adapter);
 539
 540         mutex_unlock(&adapter->mbox_lock);
 541         return status;
 542 }
 543
 544 /* Tell fw we're done with firing cmds by writing a
 545  * special pattern across the wrb hdr; uses mbox
 546  */
 547 int be_cmd_fw_clean(struct be_adapter *adapter)
 548 {
 549         u8 *wrb;
 550         int status;
 551
 552         if (adapter->eeh_err)
 553                 return -EIO;
 554
 555         if (mutex_lock_interruptible(&adapter->mbox_lock))
 556                 return -1;
 557
 558         wrb = (u8 *)wrb_from_mbox(adapter);
 559         *wrb++ = 0xFF;
 560         *wrb++ = 0xAA;
 561         *wrb++ = 0xBB;
 562         *wrb++ = 0xFF;
 563         *wrb++ = 0xFF;
 564         *wrb++ = 0xCC;
 565         *wrb++ = 0xDD;
 566         *wrb = 0xFF;
 567
 568         status = be_mbox_notify_wait(adapter);
 569
 570         mutex_unlock(&adapter->mbox_lock);
 571         return status;
 572 }
 573 int be_cmd_eq_create(struct be_adapter *adapter,
 574                 struct be_queue_info *eq, int eq_delay)
 575 {
 576         struct be_mcc_wrb *wrb;
 577         struct be_cmd_req_eq_create *req;
 578         struct be_dma_mem *q_mem = &eq->dma_mem;
 579         int status;
 580
 581         if (mutex_lock_interruptible(&adapter->mbox_lock))
 582                 return -1;
 583
 584         wrb = wrb_from_mbox(adapter);
 585         req = embedded_payload(wrb);
 586
 587         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
 588
 589         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 590                 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
 591
 592         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 593
 594         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 595         /* 4byte eqe*/
 596         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 597         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 598                         __ilog2_u32(eq->len/256));
 599         AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
 600                         eq_delay_to_mult(eq_delay));
 601         be_dws_cpu_to_le(req->context, sizeof(req->context));
 602
 603         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 604
 605         status = be_mbox_notify_wait(adapter);
 606         if (!status) {
 607                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 608                 eq->id = le16_to_cpu(resp->eq_id);
 609                 eq->created = true;
 610         }
 611
 612         mutex_unlock(&adapter->mbox_lock);
 613         return status;
 614 }
 615
 616 /* Uses mbox */
 617 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 618                         u8 type, bool permanent, u32 if_handle)
 619 {
 620         struct be_mcc_wrb *wrb;
 621         struct be_cmd_req_mac_query *req;
 622         int status;
 623
 624         if (mutex_lock_interruptible(&adapter->mbox_lock))
 625                 return -1;
 626
 627         wrb = wrb_from_mbox(adapter);
 628         req = embedded_payload(wrb);
 629
 630         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 631                         OPCODE_COMMON_NTWK_MAC_QUERY);
 632
 633         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 634                 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
 635
 636         req->type = type;
 637         if (permanent) {
 638                 req->permanent = 1;
 639         } else {
 640                 req->if_id = cpu_to_le16((u16) if_handle);
 641                 req->permanent = 0;
 642         }
 643
 644         status = be_mbox_notify_wait(adapter);
 645         if (!status) {
 646                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
 647                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
 648         }
 649
 650         mutex_unlock(&adapter->mbox_lock);
 651         return status;
 652 }
 653
 654 /* Uses synchronous MCCQ */
 655 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 656                 u32 if_id, u32 *pmac_id, u32 domain)
 657 {
 658         struct be_mcc_wrb *wrb;
 659         struct be_cmd_req_pmac_add *req;
 660         int status;
 661
 662         spin_lock_bh(&adapter->mcc_lock);
 663
 664         wrb = wrb_from_mccq(adapter);
 665         if (!wrb) {
 666                 status = -EBUSY;
 667                 goto err;
 668         }
 669         req = embedded_payload(wrb);
 670
 671         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 672                         OPCODE_COMMON_NTWK_PMAC_ADD);
 673
 674         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 675                 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
 676
 677         req->hdr.domain = domain;
 678         req->if_id = cpu_to_le32(if_id);
 679         memcpy(req->mac_address, mac_addr, ETH_ALEN);
 680
 681         status = be_mcc_notify_wait(adapter);
 682         if (!status) {
 683                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
 684                 *pmac_id = le32_to_cpu(resp->pmac_id);
 685         }
 686
 687 err:
 688         spin_unlock_bh(&adapter->mcc_lock);
 689         return status;
 690 }
 691
 692 /* Uses synchronous MCCQ */
 693 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
 694 {
 695         struct be_mcc_wrb *wrb;
 696         struct be_cmd_req_pmac_del *req;
 697         int status;
 698
 699         spin_lock_bh(&adapter->mcc_lock);
 700
 701         wrb = wrb_from_mccq(adapter);
 702         if (!wrb) {
 703                 status = -EBUSY;
 704                 goto err;
 705         }
 706         req = embedded_payload(wrb);
 707
 708         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 709                         OPCODE_COMMON_NTWK_PMAC_DEL);
 710
 711         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 712                 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
 713
 714         req->hdr.domain = dom;
 715         req->if_id = cpu_to_le32(if_id);
 716         req->pmac_id = cpu_to_le32(pmac_id);
 717
 718         status = be_mcc_notify_wait(adapter);
 719
 720 err:
 721         spin_unlock_bh(&adapter->mcc_lock);
 722         return status;
 723 }
 724
 725 /* Uses Mbox */
 726 int be_cmd_cq_create(struct be_adapter *adapter,
 727                 struct be_queue_info *cq, struct be_queue_info *eq,
 728                 bool sol_evts, bool no_delay, int coalesce_wm)
 729 {
 730         struct be_mcc_wrb *wrb;
 731         struct be_cmd_req_cq_create *req;
 732         struct be_dma_mem *q_mem = &cq->dma_mem;
 733         void *ctxt;
 734         int status;
 735
 736         if (mutex_lock_interruptible(&adapter->mbox_lock))
 737                 return -1;
 738
 739         wrb = wrb_from_mbox(adapter);
 740         req = embedded_payload(wrb);
 741         ctxt = &req->context;
 742
 743         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 744                         OPCODE_COMMON_CQ_CREATE);
 745
 746         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 747                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 748
 749         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 750         if (lancer_chip(adapter)) {
 751                 req->hdr.version = 2;
 752                 req->page_size = 1; /* 1 for 4K */
 753                 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
 754                                                                 no_delay);
 755                 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
 756                                                 __ilog2_u32(cq->len/256));
 757                 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
 758                 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
 759                                                                 ctxt, 1);
 760                 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
 761                                                                 ctxt, eq->id);
 762                 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
 763         } else {
 764                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
 765                                                                 coalesce_wm);
 766                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
 767                                                                 ctxt, no_delay);
 768                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
 769                                                 __ilog2_u32(cq->len/256));
 770                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
 771                 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
 772                                                                 ctxt, sol_evts);
 773                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
 774                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
 775                 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
 776         }
 777
 778         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 779
 780         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 781
 782         status = be_mbox_notify_wait(adapter);
 783         if (!status) {
 784                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
 785                 cq->id = le16_to_cpu(resp->cq_id);
 786                 cq->created = true;
 787         }
 788
 789         mutex_unlock(&adapter->mbox_lock);
 790
 791         return status;
 792 }
 793
 794 static u32 be_encoded_q_len(int q_len)
 795 {
 796         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
 797         if (len_encoded == 16)
 798                 len_encoded = 0;
 799         return len_encoded;
 800 }
 801
 802 int be_cmd_mccq_create(struct be_adapter *adapter,
 803                         struct be_queue_info *mccq,
 804                         struct be_queue_info *cq)
 805 {
 806         struct be_mcc_wrb *wrb;
 807         struct be_cmd_req_mcc_create *req;
 808         struct be_dma_mem *q_mem = &mccq->dma_mem;
 809         void *ctxt;
 810         int status;
 811
 812         if (mutex_lock_interruptible(&adapter->mbox_lock))
 813                 return -1;
 814
 815         wrb = wrb_from_mbox(adapter);
 816         req = embedded_payload(wrb);
 817         ctxt = &req->context;
 818
 819         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 820                         OPCODE_COMMON_MCC_CREATE_EXT);
 821
 822         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 823                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
 824
 825         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 826         if (lancer_chip(adapter)) {
 827                 req->hdr.version = 1;
 828                 req->cq_id = cpu_to_le16(cq->id);
 829
 830                 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
 831                                                 be_encoded_q_len(mccq->len));
 832                 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
 833                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
 834                                                                 ctxt, cq->id);
 835                 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
 836                                                                  ctxt, 1);
 837
 838         } else {
 839                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
 840                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
 841                                                 be_encoded_q_len(mccq->len));
 842                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
 843         }
 844
 845         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
 846         req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
 847         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 848
 849         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 850
 851         status = be_mbox_notify_wait(adapter);
 852         if (!status) {
 853                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
 854                 mccq->id = le16_to_cpu(resp->id);
 855                 mccq->created = true;
 856         }
 857         mutex_unlock(&adapter->mbox_lock);
 858
 859         return status;
 860 }
 861
 862 int be_cmd_txq_create(struct be_adapter *adapter,
 863                         struct be_queue_info *txq,
 864                         struct be_queue_info *cq)
 865 {
 866         struct be_mcc_wrb *wrb;
 867         struct be_cmd_req_eth_tx_create *req;
 868         struct be_dma_mem *q_mem = &txq->dma_mem;
 869         void *ctxt;
 870         int status;
 871
 872         if (mutex_lock_interruptible(&adapter->mbox_lock))
 873                 return -1;
 874
 875         wrb = wrb_from_mbox(adapter);
 876         req = embedded_payload(wrb);
 877         ctxt = &req->context;
 878
 879         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 880                         OPCODE_ETH_TX_CREATE);
 881
 882         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
 883                 sizeof(*req));
 884
 885         if (lancer_chip(adapter)) {
 886                 req->hdr.version = 1;
 887                 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
 888                                         adapter->if_handle);
 889         }
 890
 891         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
 892         req->ulp_num = BE_ULP1_NUM;
 893         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
 894
 895         AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
 896                 be_encoded_q_len(txq->len));
 897         AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
 898         AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
 899
 900         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 901
 902         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 903
 904         status = be_mbox_notify_wait(adapter);
 905         if (!status) {
 906                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
 907                 txq->id = le16_to_cpu(resp->cid);
 908                 txq->created = true;
 909         }
 910
 911         mutex_unlock(&adapter->mbox_lock);
 912
 913         return status;
 914 }
 915
 916 /* Uses mbox */
 917 int be_cmd_rxq_create(struct be_adapter *adapter,
 918                 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
 919                 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
 920 {
 921         struct be_mcc_wrb *wrb;
 922         struct be_cmd_req_eth_rx_create *req;
 923         struct be_dma_mem *q_mem = &rxq->dma_mem;
 924         int status;
 925
 926         if (mutex_lock_interruptible(&adapter->mbox_lock))
 927                 return -1;
 928
 929         wrb = wrb_from_mbox(adapter);
 930         req = embedded_payload(wrb);
 931
 932         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
 933                         OPCODE_ETH_RX_CREATE);
 934
 935         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
 936                 sizeof(*req));
 937
 938         req->cq_id = cpu_to_le16(cq_id);
 939         req->frag_size = fls(frag_size) - 1;
 940         req->num_pages = 2;
 941         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 942         req->interface_id = cpu_to_le32(if_id);
 943         req->max_frame_size = cpu_to_le16(max_frame_size);
 944         req->rss_queue = cpu_to_le32(rss);
 945
 946         status = be_mbox_notify_wait(adapter);
 947         if (!status) {
 948                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
 949                 rxq->id = le16_to_cpu(resp->id);
 950                 rxq->created = true;
 951                 *rss_id = resp->rss_id;
 952         }
 953
 954         mutex_unlock(&adapter->mbox_lock);
 955
 956         return status;
 957 }
 958
 959 /* Generic destroyer function for all types of queues
 960  * Uses Mbox
 961  */
 962 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 963                 int queue_type)
 964 {
 965         struct be_mcc_wrb *wrb;
 966         struct be_cmd_req_q_destroy *req;
 967         u8 subsys = 0, opcode = 0;
 968         int status;
 969
 970         if (adapter->eeh_err)
 971                 return -EIO;
 972
 973         if (mutex_lock_interruptible(&adapter->mbox_lock))
 974                 return -1;
 975
 976         wrb = wrb_from_mbox(adapter);
 977         req = embedded_payload(wrb);
 978
 979         switch (queue_type) {
 980         case QTYPE_EQ:
 981                 subsys = CMD_SUBSYSTEM_COMMON;
 982                 opcode = OPCODE_COMMON_EQ_DESTROY;
 983                 break;
 984         case QTYPE_CQ:
 985                 subsys = CMD_SUBSYSTEM_COMMON;
 986                 opcode = OPCODE_COMMON_CQ_DESTROY;
 987                 break;
 988         case QTYPE_TXQ:
 989                 subsys = CMD_SUBSYSTEM_ETH;
 990                 opcode = OPCODE_ETH_TX_DESTROY;
 991                 break;
 992         case QTYPE_RXQ:
 993                 subsys = CMD_SUBSYSTEM_ETH;
 994                 opcode = OPCODE_ETH_RX_DESTROY;
 995                 break;
 996         case QTYPE_MCCQ:
 997                 subsys = CMD_SUBSYSTEM_COMMON;
 998                 opcode = OPCODE_COMMON_MCC_DESTROY;
 999                 break;
1000         default:
1001                 BUG();
1002         }
1003
1004         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
1005
1006         be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1007         req->id = cpu_to_le16(q->id);
1008
1009         status = be_mbox_notify_wait(adapter);
1010
1011         mutex_unlock(&adapter->mbox_lock);
1012
1013         return status;
1014 }
1015
1016 /* Create an rx filtering policy configuration on an i/f
1017  * Uses mbox
1018  */
1019 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1020                 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
1021                 u32 domain)
1022 {
1023         struct be_mcc_wrb *wrb;
1024         struct be_cmd_req_if_create *req;
1025         int status;
1026
1027         if (mutex_lock_interruptible(&adapter->mbox_lock))
1028                 return -1;
1029
1030         wrb = wrb_from_mbox(adapter);
1031         req = embedded_payload(wrb);
1032
1033         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1034                         OPCODE_COMMON_NTWK_INTERFACE_CREATE);
1035
1036         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1037                 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
1038
1039         req->hdr.domain = domain;
1040         req->capability_flags = cpu_to_le32(cap_flags);
1041         req->enable_flags = cpu_to_le32(en_flags);
1042         req->pmac_invalid = pmac_invalid;
1043         if (!pmac_invalid)
1044                 memcpy(req->mac_addr, mac, ETH_ALEN);
1045
1046         status = be_mbox_notify_wait(adapter);
1047         if (!status) {
1048                 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1049                 *if_handle = le32_to_cpu(resp->interface_id);
1050                 if (!pmac_invalid)
1051                         *pmac_id = le32_to_cpu(resp->pmac_id);
1052         }
1053
1054         mutex_unlock(&adapter->mbox_lock);
1055         return status;
1056 }
1057
1058 /* Uses mbox */
1059 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1060 {
1061         struct be_mcc_wrb *wrb;
1062         struct be_cmd_req_if_destroy *req;
1063         int status;
1064
1065         if (adapter->eeh_err)
1066                 return -EIO;
1067
1068         if (mutex_lock_interruptible(&adapter->mbox_lock))
1069                 return -1;
1070
1071         wrb = wrb_from_mbox(adapter);
1072         req = embedded_payload(wrb);
1073
1074         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1075                         OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1076
1077         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1078                 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1079
1080         req->hdr.domain = domain;
1081         req->interface_id = cpu_to_le32(interface_id);
1082
1083         status = be_mbox_notify_wait(adapter);
1084
1085         mutex_unlock(&adapter->mbox_lock);
1086
1087         return status;
1088 }
1089
1090 /* Get stats is a non embedded command: the request is not embedded inside
1091  * WRB but is a separate dma memory block
1092  * Uses asynchronous MCC
1093  */
1094 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1095 {
1096         struct be_mcc_wrb *wrb;
1097         struct be_cmd_req_hdr *hdr;
1098         struct be_sge *sge;
1099         int status = 0;
1100
1101         if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1102                 be_cmd_get_die_temperature(adapter);
1103
1104         spin_lock_bh(&adapter->mcc_lock);
1105
1106         wrb = wrb_from_mccq(adapter);
1107         if (!wrb) {
1108                 status = -EBUSY;
1109                 goto err;
1110         }
1111         hdr = nonemb_cmd->va;
1112         sge = nonembedded_sgl(wrb);
1113
1114         be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1115                         OPCODE_ETH_GET_STATISTICS);
1116
1117         be_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1118                 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size);
1119
1120         if (adapter->generation == BE_GEN3)
1121                 hdr->version = 1;
1122
1123         wrb->tag1 = CMD_SUBSYSTEM_ETH;
1124         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1125         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1126         sge->len = cpu_to_le32(nonemb_cmd->size);
1127
1128         be_mcc_notify(adapter);
1129         adapter->stats_cmd_sent = true;
1130
1131 err:
1132         spin_unlock_bh(&adapter->mcc_lock);
1133         return status;
1134 }
1135
1136 /* Lancer Stats */
1137 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1138                                 struct be_dma_mem *nonemb_cmd)
1139 {
1140
1141         struct be_mcc_wrb *wrb;
1142         struct lancer_cmd_req_pport_stats *req;
1143         struct be_sge *sge;
1144         int status = 0;
1145
1146         spin_lock_bh(&adapter->mcc_lock);
1147
1148         wrb = wrb_from_mccq(adapter);
1149         if (!wrb) {
1150                 status = -EBUSY;
1151                 goto err;
1152         }
1153         req = nonemb_cmd->va;
1154         sge = nonembedded_sgl(wrb);
1155
1156         be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1157                         OPCODE_ETH_GET_PPORT_STATS);
1158
1159         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1160                         OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size);
1161
1162
1163         req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1164         req->cmd_params.params.reset_stats = 0;
1165
1166         wrb->tag1 = CMD_SUBSYSTEM_ETH;
1167         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1168         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1169         sge->len = cpu_to_le32(nonemb_cmd->size);
1170
1171         be_mcc_notify(adapter);
1172         adapter->stats_cmd_sent = true;
1173
1174 err:
1175         spin_unlock_bh(&adapter->mcc_lock);
1176         return status;
1177 }
1178
1179 /* Uses synchronous mcc */
1180 int be_cmd_link_status_query(struct be_adapter *adapter,
1181                         bool *link_up, u8 *mac_speed, u16 *link_speed, u32 dom)
1182 {
1183         struct be_mcc_wrb *wrb;
1184         struct be_cmd_req_link_status *req;
1185         int status;
1186
1187         spin_lock_bh(&adapter->mcc_lock);
1188
1189         wrb = wrb_from_mccq(adapter);
1190         if (!wrb) {
1191                 status = -EBUSY;
1192                 goto err;
1193         }
1194         req = embedded_payload(wrb);
1195
1196         *link_up = false;
1197
1198         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1199                         OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1200
1201         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1202                 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1203
1204         status = be_mcc_notify_wait(adapter);
1205         if (!status) {
1206                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1207                 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1208                         *link_up = true;
1209                         *link_speed = le16_to_cpu(resp->link_speed);
1210                         *mac_speed = resp->mac_speed;
1211                 }
1212         }
1213
1214 err:
1215         spin_unlock_bh(&adapter->mcc_lock);
1216         return status;
1217 }
1218
1219 /* Uses synchronous mcc */
1220 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1221 {
1222         struct be_mcc_wrb *wrb;
1223         struct be_cmd_req_get_cntl_addnl_attribs *req;
1224         int status;
1225
1226         spin_lock_bh(&adapter->mcc_lock);
1227
1228         wrb = wrb_from_mccq(adapter);
1229         if (!wrb) {
1230                 status = -EBUSY;
1231                 goto err;
1232         }
1233         req = embedded_payload(wrb);
1234
1235         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1236                         OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES);
1237
1238         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1239                 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
1240
1241         status = be_mcc_notify_wait(adapter);
1242         if (!status) {
1243                 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
1244                                                 embedded_payload(wrb);
1245                 adapter->drv_stats.be_on_die_temperature =
1246                                                 resp->on_die_temperature;
1247         }
1248         /* If IOCTL fails once, do not bother issuing it again */
1249         else
1250                 be_get_temp_freq = 0;
1251
1252 err:
1253         spin_unlock_bh(&adapter->mcc_lock);
1254         return status;
1255 }
1256
1257 /* Uses synchronous mcc */
1258 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1259 {
1260         struct be_mcc_wrb *wrb;
1261         struct be_cmd_req_get_fat *req;
1262         int status;
1263
1264         spin_lock_bh(&adapter->mcc_lock);
1265
1266         wrb = wrb_from_mccq(adapter);
1267         if (!wrb) {
1268                 status = -EBUSY;
1269                 goto err;
1270         }
1271         req = embedded_payload(wrb);
1272
1273         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1274                         OPCODE_COMMON_MANAGE_FAT);
1275
1276         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1277                 OPCODE_COMMON_MANAGE_FAT, sizeof(*req));
1278         req->fat_operation = cpu_to_le32(QUERY_FAT);
1279         status = be_mcc_notify_wait(adapter);
1280         if (!status) {
1281                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1282                 if (log_size && resp->log_size)
1283                         *log_size = le32_to_cpu(resp->log_size) -
1284                                         sizeof(u32);
1285         }
1286 err:
1287         spin_unlock_bh(&adapter->mcc_lock);
1288         return status;
1289 }
1290
1291 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1292 {
1293         struct be_dma_mem get_fat_cmd;
1294         struct be_mcc_wrb *wrb;
1295         struct be_cmd_req_get_fat *req;
1296         struct be_sge *sge;
1297         u32 offset = 0, total_size, buf_size,
1298                                 log_offset = sizeof(u32), payload_len;
1299         int status;
1300
1301         if (buf_len == 0)
1302                 return;
1303
1304         total_size = buf_len;
1305
1306         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1307         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1308                         get_fat_cmd.size,
1309                         &get_fat_cmd.dma);
1310         if (!get_fat_cmd.va) {
1311                 status = -ENOMEM;
1312                 dev_err(&adapter->pdev->dev,
1313                 "Memory allocation failure while retrieving FAT data\n");
1314                 return;
1315         }
1316
1317         spin_lock_bh(&adapter->mcc_lock);
1318
1319         while (total_size) {
1320                 buf_size = min(total_size, (u32)60*1024);
1321                 total_size -= buf_size;
1322
1323                 wrb = wrb_from_mccq(adapter);
1324                 if (!wrb) {
1325                         status = -EBUSY;
1326                         goto err;
1327                 }
1328                 req = get_fat_cmd.va;
1329                 sge = nonembedded_sgl(wrb);
1330
1331                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1332                 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
1333                                 OPCODE_COMMON_MANAGE_FAT);
1334
1335                 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1336                                 OPCODE_COMMON_MANAGE_FAT, payload_len);
1337
1338                 sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.dma));
1339                 sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF);
1340                 sge->len = cpu_to_le32(get_fat_cmd.size);
1341
1342                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1343                 req->read_log_offset = cpu_to_le32(log_offset);
1344                 req->read_log_length = cpu_to_le32(buf_size);
1345                 req->data_buffer_size = cpu_to_le32(buf_size);
1346
1347                 status = be_mcc_notify_wait(adapter);
1348                 if (!status) {
1349                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1350                         memcpy(buf + offset,
1351                                 resp->data_buffer,
1352                                 resp->read_log_length);
1353                 } else {
1354                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1355                         goto err;
1356                 }
1357                 offset += buf_size;
1358                 log_offset += buf_size;
1359         }
1360 err:
1361         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1362                         get_fat_cmd.va,
1363                         get_fat_cmd.dma);
1364         spin_unlock_bh(&adapter->mcc_lock);
1365 }
1366
1367 /* Uses Mbox */
1368 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
1369 {
1370         struct be_mcc_wrb *wrb;
1371         struct be_cmd_req_get_fw_version *req;
1372         int status;
1373
1374         if (mutex_lock_interruptible(&adapter->mbox_lock))
1375                 return -1;
1376
1377         wrb = wrb_from_mbox(adapter);
1378         req = embedded_payload(wrb);
1379
1380         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1381                         OPCODE_COMMON_GET_FW_VERSION);
1382
1383         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1384                 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1385
1386         status = be_mbox_notify_wait(adapter);
1387         if (!status) {
1388                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1389                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1390         }
1391
1392         mutex_unlock(&adapter->mbox_lock);
1393         return status;
1394 }
1395
1396 /* set the EQ delay interval of an EQ to specified value
1397  * Uses async mcc
1398  */
1399 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1400 {
1401         struct be_mcc_wrb *wrb;
1402         struct be_cmd_req_modify_eq_delay *req;
1403         int status = 0;
1404
1405         spin_lock_bh(&adapter->mcc_lock);
1406
1407         wrb = wrb_from_mccq(adapter);
1408         if (!wrb) {
1409                 status = -EBUSY;
1410                 goto err;
1411         }
1412         req = embedded_payload(wrb);
1413
1414         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1415                         OPCODE_COMMON_MODIFY_EQ_DELAY);
1416
1417         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1418                 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1419
1420         req->num_eq = cpu_to_le32(1);
1421         req->delay[0].eq_id = cpu_to_le32(eq_id);
1422         req->delay[0].phase = 0;
1423         req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1424
1425         be_mcc_notify(adapter);
1426
1427 err:
1428         spin_unlock_bh(&adapter->mcc_lock);
1429         return status;
1430 }
1431
1432 /* Uses sycnhronous mcc */
1433 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1434                         u32 num, bool untagged, bool promiscuous)
1435 {
1436         struct be_mcc_wrb *wrb;
1437         struct be_cmd_req_vlan_config *req;
1438         int status;
1439
1440         spin_lock_bh(&adapter->mcc_lock);
1441
1442         wrb = wrb_from_mccq(adapter);
1443         if (!wrb) {
1444                 status = -EBUSY;
1445                 goto err;
1446         }
1447         req = embedded_payload(wrb);
1448
1449         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1450                         OPCODE_COMMON_NTWK_VLAN_CONFIG);
1451
1452         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1453                 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1454
1455         req->interface_id = if_id;
1456         req->promiscuous = promiscuous;
1457         req->untagged = untagged;
1458         req->num_vlan = num;
1459         if (!promiscuous) {
1460                 memcpy(req->normal_vlan, vtag_array,
1461                         req->num_vlan * sizeof(vtag_array[0]));
1462         }
1463
1464         status = be_mcc_notify_wait(adapter);
1465
1466 err:
1467         spin_unlock_bh(&adapter->mcc_lock);
1468         return status;
1469 }
1470
1471 /* Uses MCC for this command as it may be called in BH context
1472  * Uses synchronous mcc
1473  */
1474 int be_cmd_promiscuous_config(struct be_adapter *adapter, bool en)
1475 {
1476         struct be_mcc_wrb *wrb;
1477         struct be_cmd_req_rx_filter *req;
1478         struct be_dma_mem promiscous_cmd;
1479         struct be_sge *sge;
1480         int status;
1481
1482         memset(&promiscous_cmd, 0, sizeof(struct be_dma_mem));
1483         promiscous_cmd.size = sizeof(struct be_cmd_req_rx_filter);
1484         promiscous_cmd.va = pci_alloc_consistent(adapter->pdev,
1485                                 promiscous_cmd.size, &promiscous_cmd.dma);
1486         if (!promiscous_cmd.va) {
1487                 dev_err(&adapter->pdev->dev,
1488                                 "Memory allocation failure\n");
1489                 return -ENOMEM;
1490         }
1491
1492         spin_lock_bh(&adapter->mcc_lock);
1493
1494         wrb = wrb_from_mccq(adapter);
1495         if (!wrb) {
1496                 status = -EBUSY;
1497                 goto err;
1498         }
1499
1500         req = promiscous_cmd.va;
1501         sge = nonembedded_sgl(wrb);
1502
1503         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1504                                         OPCODE_COMMON_NTWK_RX_FILTER);
1505         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1506                         OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req));
1507
1508         req->if_id = cpu_to_le32(adapter->if_handle);
1509         req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1510         if (en)
1511                 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS);
1512
1513         sge->pa_hi = cpu_to_le32(upper_32_bits(promiscous_cmd.dma));
1514         sge->pa_lo = cpu_to_le32(promiscous_cmd.dma & 0xFFFFFFFF);
1515         sge->len = cpu_to_le32(promiscous_cmd.size);
1516
1517         status = be_mcc_notify_wait(adapter);
1518
1519 err:
1520         spin_unlock_bh(&adapter->mcc_lock);
1521         pci_free_consistent(adapter->pdev, promiscous_cmd.size,
1522                         promiscous_cmd.va, promiscous_cmd.dma);
1523         return status;
1524 }
1525
1526 /*
1527  * Uses MCC for this command as it may be called in BH context
1528  * (mc == NULL) => multicast promiscuous
1529  */
1530 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1531                 struct net_device *netdev, struct be_dma_mem *mem)
1532 {
1533         struct be_mcc_wrb *wrb;
1534         struct be_cmd_req_mcast_mac_config *req = mem->va;
1535         struct be_sge *sge;
1536         int status;
1537
1538         spin_lock_bh(&adapter->mcc_lock);
1539
1540         wrb = wrb_from_mccq(adapter);
1541         if (!wrb) {
1542                 status = -EBUSY;
1543                 goto err;
1544         }
1545         sge = nonembedded_sgl(wrb);
1546         memset(req, 0, sizeof(*req));
1547
1548         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1549                         OPCODE_COMMON_NTWK_MULTICAST_SET);
1550         sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1551         sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1552         sge->len = cpu_to_le32(mem->size);
1553
1554         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1555                 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1556
1557         req->interface_id = if_id;
1558         if (netdev) {
1559                 int i;
1560                 struct netdev_hw_addr *ha;
1561
1562                 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1563
1564                 i = 0;
1565                 netdev_for_each_mc_addr(ha, netdev)
1566                         memcpy(req->mac[i++].byte, ha->addr, ETH_ALEN);
1567         } else {
1568                 req->promiscuous = 1;
1569         }
1570
1571         status = be_mcc_notify_wait(adapter);
1572
1573 err:
1574         spin_unlock_bh(&adapter->mcc_lock);
1575         return status;
1576 }
1577
1578 /* Uses synchrounous mcc */
1579 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1580 {
1581         struct be_mcc_wrb *wrb;
1582         struct be_cmd_req_set_flow_control *req;
1583         int status;
1584
1585         spin_lock_bh(&adapter->mcc_lock);
1586
1587         wrb = wrb_from_mccq(adapter);
1588         if (!wrb) {
1589                 status = -EBUSY;
1590                 goto err;
1591         }
1592         req = embedded_payload(wrb);
1593
1594         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1595                         OPCODE_COMMON_SET_FLOW_CONTROL);
1596
1597         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1598                 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1599
1600         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1601         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1602
1603         status = be_mcc_notify_wait(adapter);
1604
1605 err:
1606         spin_unlock_bh(&adapter->mcc_lock);
1607         return status;
1608 }
1609
1610 /* Uses sycn mcc */
1611 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1612 {
1613         struct be_mcc_wrb *wrb;
1614         struct be_cmd_req_get_flow_control *req;
1615         int status;
1616
1617         spin_lock_bh(&adapter->mcc_lock);
1618
1619         wrb = wrb_from_mccq(adapter);
1620         if (!wrb) {
1621                 status = -EBUSY;
1622                 goto err;
1623         }
1624         req = embedded_payload(wrb);
1625
1626         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1627                         OPCODE_COMMON_GET_FLOW_CONTROL);
1628
1629         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1630                 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1631
1632         status = be_mcc_notify_wait(adapter);
1633         if (!status) {
1634                 struct be_cmd_resp_get_flow_control *resp =
1635                                                 embedded_payload(wrb);
1636                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1637                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1638         }
1639
1640 err:
1641         spin_unlock_bh(&adapter->mcc_lock);
1642         return status;
1643 }
1644
1645 /* Uses mbox */
1646 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1647                 u32 *mode, u32 *caps)
1648 {
1649         struct be_mcc_wrb *wrb;
1650         struct be_cmd_req_query_fw_cfg *req;
1651         int status;
1652
1653         if (mutex_lock_interruptible(&adapter->mbox_lock))
1654                 return -1;
1655
1656         wrb = wrb_from_mbox(adapter);
1657         req = embedded_payload(wrb);
1658
1659         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1660                         OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1661
1662         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1663                 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1664
1665         status = be_mbox_notify_wait(adapter);
1666         if (!status) {
1667                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1668                 *port_num = le32_to_cpu(resp->phys_port);
1669                 *mode = le32_to_cpu(resp->function_mode);
1670                 *caps = le32_to_cpu(resp->function_caps);
1671         }
1672
1673         mutex_unlock(&adapter->mbox_lock);
1674         return status;
1675 }
1676
1677 /* Uses mbox */
1678 int be_cmd_reset_function(struct be_adapter *adapter)
1679 {
1680         struct be_mcc_wrb *wrb;
1681         struct be_cmd_req_hdr *req;
1682         int status;
1683
1684         if (mutex_lock_interruptible(&adapter->mbox_lock))
1685                 return -1;
1686
1687         wrb = wrb_from_mbox(adapter);
1688         req = embedded_payload(wrb);
1689
1690         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1691                         OPCODE_COMMON_FUNCTION_RESET);
1692
1693         be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1694                 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1695
1696         status = be_mbox_notify_wait(adapter);
1697
1698         mutex_unlock(&adapter->mbox_lock);
1699         return status;
1700 }
1701
1702 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1703 {
1704         struct be_mcc_wrb *wrb;
1705         struct be_cmd_req_rss_config *req;
1706         u32 myhash[10];
1707         int status;
1708
1709         if (mutex_lock_interruptible(&adapter->mbox_lock))
1710                 return -1;
1711
1712         wrb = wrb_from_mbox(adapter);
1713         req = embedded_payload(wrb);
1714
1715         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1716                 OPCODE_ETH_RSS_CONFIG);
1717
1718         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1719                 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1720
1721         req->if_id = cpu_to_le32(adapter->if_handle);
1722         req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1723         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1724         memcpy(req->cpu_table, rsstable, table_size);
1725         memcpy(req->hash, myhash, sizeof(myhash));
1726         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1727
1728         status = be_mbox_notify_wait(adapter);
1729
1730         mutex_unlock(&adapter->mbox_lock);
1731         return status;
1732 }
1733
1734 /* Uses sync mcc */
1735 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1736                         u8 bcn, u8 sts, u8 state)
1737 {
1738         struct be_mcc_wrb *wrb;
1739         struct be_cmd_req_enable_disable_beacon *req;
1740         int status;
1741
1742         spin_lock_bh(&adapter->mcc_lock);
1743
1744         wrb = wrb_from_mccq(adapter);
1745         if (!wrb) {
1746                 status = -EBUSY;
1747                 goto err;
1748         }
1749         req = embedded_payload(wrb);
1750
1751         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1752                         OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1753
1754         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1755                 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1756
1757         req->port_num = port_num;
1758         req->beacon_state = state;
1759         req->beacon_duration = bcn;
1760         req->status_duration = sts;
1761
1762         status = be_mcc_notify_wait(adapter);
1763
1764 err:
1765         spin_unlock_bh(&adapter->mcc_lock);
1766         return status;
1767 }
1768
1769 /* Uses sync mcc */
1770 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1771 {
1772         struct be_mcc_wrb *wrb;
1773         struct be_cmd_req_get_beacon_state *req;
1774         int status;
1775
1776         spin_lock_bh(&adapter->mcc_lock);
1777
1778         wrb = wrb_from_mccq(adapter);
1779         if (!wrb) {
1780                 status = -EBUSY;
1781                 goto err;
1782         }
1783         req = embedded_payload(wrb);
1784
1785         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1786                         OPCODE_COMMON_GET_BEACON_STATE);
1787
1788         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1789                 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1790
1791         req->port_num = port_num;
1792
1793         status = be_mcc_notify_wait(adapter);
1794         if (!status) {
1795                 struct be_cmd_resp_get_beacon_state *resp =
1796                                                 embedded_payload(wrb);
1797                 *state = resp->beacon_state;
1798         }
1799
1800 err:
1801         spin_unlock_bh(&adapter->mcc_lock);
1802         return status;
1803 }
1804
1805 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1806                         u32 data_size, u32 data_offset, const char *obj_name,
1807                         u32 *data_written, u8 *addn_status)
1808 {
1809         struct be_mcc_wrb *wrb;
1810         struct lancer_cmd_req_write_object *req;
1811         struct lancer_cmd_resp_write_object *resp;
1812         void *ctxt = NULL;
1813         int status;
1814
1815         spin_lock_bh(&adapter->mcc_lock);
1816         adapter->flash_status = 0;
1817
1818         wrb = wrb_from_mccq(adapter);
1819         if (!wrb) {
1820                 status = -EBUSY;
1821                 goto err_unlock;
1822         }
1823
1824         req = embedded_payload(wrb);
1825
1826         be_wrb_hdr_prepare(wrb, sizeof(struct lancer_cmd_req_write_object),
1827                         true, 1, OPCODE_COMMON_WRITE_OBJECT);
1828         wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1829
1830         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1831                                 OPCODE_COMMON_WRITE_OBJECT,
1832                                 sizeof(struct lancer_cmd_req_write_object));
1833
1834         ctxt = &req->context;
1835         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1836                         write_length, ctxt, data_size);
1837
1838         if (data_size == 0)
1839                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1840                                 eof, ctxt, 1);
1841         else
1842                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1843                                 eof, ctxt, 0);
1844
1845         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1846         req->write_offset = cpu_to_le32(data_offset);
1847         strcpy(req->object_name, obj_name);
1848         req->descriptor_count = cpu_to_le32(1);
1849         req->buf_len = cpu_to_le32(data_size);
1850         req->addr_low = cpu_to_le32((cmd->dma +
1851                                 sizeof(struct lancer_cmd_req_write_object))
1852                                 & 0xFFFFFFFF);
1853         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1854                                 sizeof(struct lancer_cmd_req_write_object)));
1855
1856         be_mcc_notify(adapter);
1857         spin_unlock_bh(&adapter->mcc_lock);
1858
1859         if (!wait_for_completion_timeout(&adapter->flash_compl,
1860                         msecs_to_jiffies(12000)))
1861                 status = -1;
1862         else
1863                 status = adapter->flash_status;
1864
1865         resp = embedded_payload(wrb);
1866         if (!status) {
1867                 *data_written = le32_to_cpu(resp->actual_write_len);
1868         } else {
1869                 *addn_status = resp->additional_status;
1870                 status = resp->status;
1871         }
1872
1873         return status;
1874
1875 err_unlock:
1876         spin_unlock_bh(&adapter->mcc_lock);
1877         return status;
1878 }
1879
1880 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1881                         u32 flash_type, u32 flash_opcode, u32 buf_size)
1882 {
1883         struct be_mcc_wrb *wrb;
1884         struct be_cmd_write_flashrom *req;
1885         struct be_sge *sge;
1886         int status;
1887
1888         spin_lock_bh(&adapter->mcc_lock);
1889         adapter->flash_status = 0;
1890
1891         wrb = wrb_from_mccq(adapter);
1892         if (!wrb) {
1893                 status = -EBUSY;
1894                 goto err_unlock;
1895         }
1896         req = cmd->va;
1897         sge = nonembedded_sgl(wrb);
1898
1899         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1900                         OPCODE_COMMON_WRITE_FLASHROM);
1901         wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1902
1903         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1904                 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1905         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1906         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1907         sge->len = cpu_to_le32(cmd->size);
1908
1909         req->params.op_type = cpu_to_le32(flash_type);
1910         req->params.op_code = cpu_to_le32(flash_opcode);
1911         req->params.data_buf_size = cpu_to_le32(buf_size);
1912
1913         be_mcc_notify(adapter);
1914         spin_unlock_bh(&adapter->mcc_lock);
1915
1916         if (!wait_for_completion_timeout(&adapter->flash_compl,
1917                         msecs_to_jiffies(12000)))
1918                 status = -1;
1919         else
1920                 status = adapter->flash_status;
1921
1922         return status;
1923
1924 err_unlock:
1925         spin_unlock_bh(&adapter->mcc_lock);
1926         return status;
1927 }
1928
1929 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1930                          int offset)
1931 {
1932         struct be_mcc_wrb *wrb;
1933         struct be_cmd_write_flashrom *req;
1934         int status;
1935
1936         spin_lock_bh(&adapter->mcc_lock);
1937
1938         wrb = wrb_from_mccq(adapter);
1939         if (!wrb) {
1940                 status = -EBUSY;
1941                 goto err;
1942         }
1943         req = embedded_payload(wrb);
1944
1945         be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1946                         OPCODE_COMMON_READ_FLASHROM);
1947
1948         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1949                 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1950
1951         req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1952         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1953         req->params.offset = cpu_to_le32(offset);
1954         req->params.data_buf_size = cpu_to_le32(0x4);
1955
1956         status = be_mcc_notify_wait(adapter);
1957         if (!status)
1958                 memcpy(flashed_crc, req->params.data_buf, 4);
1959
1960 err:
1961         spin_unlock_bh(&adapter->mcc_lock);
1962         return status;
1963 }
1964
1965 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1966                                 struct be_dma_mem *nonemb_cmd)
1967 {
1968         struct be_mcc_wrb *wrb;
1969         struct be_cmd_req_acpi_wol_magic_config *req;
1970         struct be_sge *sge;
1971         int status;
1972
1973         spin_lock_bh(&adapter->mcc_lock);
1974
1975         wrb = wrb_from_mccq(adapter);
1976         if (!wrb) {
1977                 status = -EBUSY;
1978                 goto err;
1979         }
1980         req = nonemb_cmd->va;
1981         sge = nonembedded_sgl(wrb);
1982
1983         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1984                         OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1985
1986         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1987                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1988         memcpy(req->magic_mac, mac, ETH_ALEN);
1989
1990         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1991         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1992         sge->len = cpu_to_le32(nonemb_cmd->size);
1993
1994         status = be_mcc_notify_wait(adapter);
1995
1996 err:
1997         spin_unlock_bh(&adapter->mcc_lock);
1998         return status;
1999 }
2000
2001 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2002                         u8 loopback_type, u8 enable)
2003 {
2004         struct be_mcc_wrb *wrb;
2005         struct be_cmd_req_set_lmode *req;
2006         int status;
2007
2008         spin_lock_bh(&adapter->mcc_lock);
2009
2010         wrb = wrb_from_mccq(adapter);
2011         if (!wrb) {
2012                 status = -EBUSY;
2013                 goto err;
2014         }
2015
2016         req = embedded_payload(wrb);
2017
2018         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2019                                 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
2020
2021         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2022                         OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
2023                         sizeof(*req));
2024
2025         req->src_port = port_num;
2026         req->dest_port = port_num;
2027         req->loopback_type = loopback_type;
2028         req->loopback_state = enable;
2029
2030         status = be_mcc_notify_wait(adapter);
2031 err:
2032         spin_unlock_bh(&adapter->mcc_lock);
2033         return status;
2034 }
2035
2036 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2037                 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2038 {
2039         struct be_mcc_wrb *wrb;
2040         struct be_cmd_req_loopback_test *req;
2041         int status;
2042
2043         spin_lock_bh(&adapter->mcc_lock);
2044
2045         wrb = wrb_from_mccq(adapter);
2046         if (!wrb) {
2047                 status = -EBUSY;
2048                 goto err;
2049         }
2050
2051         req = embedded_payload(wrb);
2052
2053         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2054                                 OPCODE_LOWLEVEL_LOOPBACK_TEST);
2055
2056         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2057                         OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
2058         req->hdr.timeout = cpu_to_le32(4);
2059
2060         req->pattern = cpu_to_le64(pattern);
2061         req->src_port = cpu_to_le32(port_num);
2062         req->dest_port = cpu_to_le32(port_num);
2063         req->pkt_size = cpu_to_le32(pkt_size);
2064         req->num_pkts = cpu_to_le32(num_pkts);
2065         req->loopback_type = cpu_to_le32(loopback_type);
2066
2067         status = be_mcc_notify_wait(adapter);
2068         if (!status) {
2069                 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2070                 status = le32_to_cpu(resp->status);
2071         }
2072
2073 err:
2074         spin_unlock_bh(&adapter->mcc_lock);
2075         return status;
2076 }
2077
2078 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2079                                 u32 byte_cnt, struct be_dma_mem *cmd)
2080 {
2081         struct be_mcc_wrb *wrb;
2082         struct be_cmd_req_ddrdma_test *req;
2083         struct be_sge *sge;
2084         int status;
2085         int i, j = 0;
2086
2087         spin_lock_bh(&adapter->mcc_lock);
2088
2089         wrb = wrb_from_mccq(adapter);
2090         if (!wrb) {
2091                 status = -EBUSY;
2092                 goto err;
2093         }
2094         req = cmd->va;
2095         sge = nonembedded_sgl(wrb);
2096         be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
2097                                 OPCODE_LOWLEVEL_HOST_DDR_DMA);
2098         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2099                         OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
2100
2101         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2102         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2103         sge->len = cpu_to_le32(cmd->size);
2104
2105         req->pattern = cpu_to_le64(pattern);
2106         req->byte_count = cpu_to_le32(byte_cnt);
2107         for (i = 0; i < byte_cnt; i++) {
2108                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2109                 j++;
2110                 if (j > 7)
2111                         j = 0;
2112         }
2113
2114         status = be_mcc_notify_wait(adapter);
2115
2116         if (!status) {
2117                 struct be_cmd_resp_ddrdma_test *resp;
2118                 resp = cmd->va;
2119                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2120                                 resp->snd_err) {
2121                         status = -1;
2122                 }
2123         }
2124
2125 err:
2126         spin_unlock_bh(&adapter->mcc_lock);
2127         return status;
2128 }
2129
2130 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2131                                 struct be_dma_mem *nonemb_cmd)
2132 {
2133         struct be_mcc_wrb *wrb;
2134         struct be_cmd_req_seeprom_read *req;
2135         struct be_sge *sge;
2136         int status;
2137
2138         spin_lock_bh(&adapter->mcc_lock);
2139
2140         wrb = wrb_from_mccq(adapter);
2141         if (!wrb) {
2142                 status = -EBUSY;
2143                 goto err;
2144         }
2145         req = nonemb_cmd->va;
2146         sge = nonembedded_sgl(wrb);
2147
2148         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2149                         OPCODE_COMMON_SEEPROM_READ);
2150
2151         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2152                         OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
2153
2154         sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2155         sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2156         sge->len = cpu_to_le32(nonemb_cmd->size);
2157
2158         status = be_mcc_notify_wait(adapter);
2159
2160 err:
2161         spin_unlock_bh(&adapter->mcc_lock);
2162         return status;
2163 }
2164
2165 int be_cmd_get_phy_info(struct be_adapter *adapter, struct be_dma_mem *cmd)
2166 {
2167         struct be_mcc_wrb *wrb;
2168         struct be_cmd_req_get_phy_info *req;
2169         struct be_sge *sge;
2170         int status;
2171
2172         spin_lock_bh(&adapter->mcc_lock);
2173
2174         wrb = wrb_from_mccq(adapter);
2175         if (!wrb) {
2176                 status = -EBUSY;
2177                 goto err;
2178         }
2179
2180         req = cmd->va;
2181         sge = nonembedded_sgl(wrb);
2182
2183         be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2184                                 OPCODE_COMMON_GET_PHY_DETAILS);
2185
2186         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2187                         OPCODE_COMMON_GET_PHY_DETAILS,
2188                         sizeof(*req));
2189
2190         sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2191         sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2192         sge->len = cpu_to_le32(cmd->size);
2193
2194         status = be_mcc_notify_wait(adapter);
2195 err:
2196         spin_unlock_bh(&adapter->mcc_lock);
2197         return status;
2198 }
2199
2200 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2201 {
2202         struct be_mcc_wrb *wrb;
2203         struct be_cmd_req_set_qos *req;
2204         int status;
2205
2206         spin_lock_bh(&adapter->mcc_lock);
2207
2208         wrb = wrb_from_mccq(adapter);
2209         if (!wrb) {
2210                 status = -EBUSY;
2211                 goto err;
2212         }
2213
2214         req = embedded_payload(wrb);
2215
2216         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2217                                 OPCODE_COMMON_SET_QOS);
2218
2219         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2220                         OPCODE_COMMON_SET_QOS, sizeof(*req));
2221
2222         req->hdr.domain = domain;
2223         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2224         req->max_bps_nic = cpu_to_le32(bps);
2225
2226         status = be_mcc_notify_wait(adapter);
2227
2228 err:
2229         spin_unlock_bh(&adapter->mcc_lock);
2230         return status;
2231 }
2232
2233 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2234 {
2235         struct be_mcc_wrb *wrb;
2236         struct be_cmd_req_cntl_attribs *req;
2237         struct be_cmd_resp_cntl_attribs *resp;
2238         struct be_sge *sge;
2239         int status;
2240         int payload_len = max(sizeof(*req), sizeof(*resp));
2241         struct mgmt_controller_attrib *attribs;
2242         struct be_dma_mem attribs_cmd;
2243
2244         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2245         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2246         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2247                                                 &attribs_cmd.dma);
2248         if (!attribs_cmd.va) {
2249                 dev_err(&adapter->pdev->dev,
2250                                 "Memory allocation failure\n");
2251                 return -ENOMEM;
2252         }
2253
2254         if (mutex_lock_interruptible(&adapter->mbox_lock))
2255                 return -1;
2256
2257         wrb = wrb_from_mbox(adapter);
2258         if (!wrb) {
2259                 status = -EBUSY;
2260                 goto err;
2261         }
2262         req = attribs_cmd.va;
2263         sge = nonembedded_sgl(wrb);
2264
2265         be_wrb_hdr_prepare(wrb, payload_len, false, 1,
2266                         OPCODE_COMMON_GET_CNTL_ATTRIBUTES);
2267         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2268                          OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
2269         sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
2270         sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
2271         sge->len = cpu_to_le32(attribs_cmd.size);
2272
2273         status = be_mbox_notify_wait(adapter);
2274         if (!status) {
2275                 attribs = (struct mgmt_controller_attrib *)( attribs_cmd.va +
2276                                         sizeof(struct be_cmd_resp_hdr));
2277                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2278         }
2279
2280 err:
2281         mutex_unlock(&adapter->mbox_lock);
2282         pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2283                                         attribs_cmd.dma);
2284         return status;
2285 }
2286
2287 /* Uses mbox */
2288 int be_cmd_check_native_mode(struct be_adapter *adapter)
2289 {
2290         struct be_mcc_wrb *wrb;
2291         struct be_cmd_req_set_func_cap *req;
2292         int status;
2293
2294         if (mutex_lock_interruptible(&adapter->mbox_lock))
2295                 return -1;
2296
2297         wrb = wrb_from_mbox(adapter);
2298         if (!wrb) {
2299                 status = -EBUSY;
2300                 goto err;
2301         }
2302
2303         req = embedded_payload(wrb);
2304
2305         be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2306                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP);
2307
2308         be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2309                 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
2310
2311         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2312                                 CAPABILITY_BE3_NATIVE_ERX_API);
2313         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2314
2315         status = be_mbox_notify_wait(adapter);
2316         if (!status) {
2317                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2318                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2319                                         CAPABILITY_BE3_NATIVE_ERX_API;
2320         }
2321 err:
2322         mutex_unlock(&adapter->mbox_lock);
2323         return status;
2324 }