2 * Intel IXP4xx Ethernet driver for Linux
4 * Copyright (C) 2007 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * Ethernet port config (0x00 is not present on IXP42X):
12 * logical port 0x00 0x10 0x20
13 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
14 * physical PortId 2 0 1
16 * RX-free queue 26 27 28
17 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
21 * bits 0 -> 1 - NPE ID (RX and TX-done)
22 * bits 0 -> 2 - priority (TX, per 802.1D)
23 * bits 3 -> 4 - port ID (user-set?)
24 * bits 5 -> 31 - physical descriptor address
27 #include <linux/delay.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmapool.h>
30 #include <linux/etherdevice.h>
32 #include <linux/kernel.h>
33 #include <linux/net_tstamp.h>
34 #include <linux/phy.h>
35 #include <linux/platform_device.h>
36 #include <linux/ptp_classify.h>
37 #include <linux/slab.h>
38 #include <mach/ixp46x_ts.h>
40 #include <mach/qmgr.h>
45 #define DEBUG_PKT_BYTES 0
49 #define DRV_NAME "ixp4xx_eth"
53 #define RX_DESCS 64 /* also length of all RX queues */
54 #define TX_DESCS 16 /* also length of all TX queues */
55 #define TXDONE_QUEUE_LEN 64 /* dwords */
57 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
58 #define REGS_SIZE 0x1000
59 #define MAX_MRU 1536 /* 0x600 */
60 #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
62 #define NAPI_WEIGHT 16
63 #define MDIO_INTERVAL (3 * HZ)
64 #define MAX_MDIO_RETRIES 100 /* microseconds, typically 30 cycles */
65 #define MAX_CLOSE_WAIT 1000 /* microseconds, typically 2-3 cycles */
67 #define NPE_ID(port_id) ((port_id) >> 4)
68 #define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
69 #define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
70 #define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
71 #define TXDONE_QUEUE 31
73 #define PTP_SLAVE_MODE 1
74 #define PTP_MASTER_MODE 2
75 #define PORT2CHANNEL(p) NPE_ID(p->id)
77 /* TX Control Registers */
78 #define TX_CNTRL0_TX_EN 0x01
79 #define TX_CNTRL0_HALFDUPLEX 0x02
80 #define TX_CNTRL0_RETRY 0x04
81 #define TX_CNTRL0_PAD_EN 0x08
82 #define TX_CNTRL0_APPEND_FCS 0x10
83 #define TX_CNTRL0_2DEFER 0x20
84 #define TX_CNTRL0_RMII 0x40 /* reduced MII */
85 #define TX_CNTRL1_RETRIES 0x0F /* 4 bits */
87 /* RX Control Registers */
88 #define RX_CNTRL0_RX_EN 0x01
89 #define RX_CNTRL0_PADSTRIP_EN 0x02
90 #define RX_CNTRL0_SEND_FCS 0x04
91 #define RX_CNTRL0_PAUSE_EN 0x08
92 #define RX_CNTRL0_LOOP_EN 0x10
93 #define RX_CNTRL0_ADDR_FLTR_EN 0x20
94 #define RX_CNTRL0_RX_RUNT_EN 0x40
95 #define RX_CNTRL0_BCAST_DIS 0x80
96 #define RX_CNTRL1_DEFER_EN 0x01
98 /* Core Control Register */
99 #define CORE_RESET 0x01
100 #define CORE_RX_FIFO_FLUSH 0x02
101 #define CORE_TX_FIFO_FLUSH 0x04
102 #define CORE_SEND_JAM 0x08
103 #define CORE_MDC_EN 0x10 /* MDIO using NPE-B ETH-0 only */
105 #define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
106 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
108 #define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
109 #define DEFAULT_CORE_CNTRL CORE_MDC_EN
112 /* NPE message codes */
113 #define NPE_GETSTATUS 0x00
114 #define NPE_EDB_SETPORTADDRESS 0x01
115 #define NPE_EDB_GETMACADDRESSDATABASE 0x02
116 #define NPE_EDB_SETMACADDRESSSDATABASE 0x03
117 #define NPE_GETSTATS 0x04
118 #define NPE_RESETSTATS 0x05
119 #define NPE_SETMAXFRAMELENGTHS 0x06
120 #define NPE_VLAN_SETRXTAGMODE 0x07
121 #define NPE_VLAN_SETDEFAULTRXVID 0x08
122 #define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
123 #define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
124 #define NPE_VLAN_SETRXQOSENTRY 0x0B
125 #define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
126 #define NPE_STP_SETBLOCKINGSTATE 0x0D
127 #define NPE_FW_SETFIREWALLMODE 0x0E
128 #define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
129 #define NPE_PC_SETAPMACTABLE 0x11
130 #define NPE_SETLOOPBACK_MODE 0x12
131 #define NPE_PC_SETBSSIDTABLE 0x13
132 #define NPE_ADDRESS_FILTER_CONFIG 0x14
133 #define NPE_APPENDFCSCONFIG 0x15
134 #define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
135 #define NPE_MAC_RECOVERY_START 0x17
139 typedef struct sk_buff buffer_t;
140 #define free_buffer dev_kfree_skb
141 #define free_buffer_irq dev_kfree_skb_irq
143 typedef void buffer_t;
144 #define free_buffer kfree
145 #define free_buffer_irq kfree
149 u32 tx_control[2], __res1[2]; /* 000 */
150 u32 rx_control[2], __res2[2]; /* 010 */
151 u32 random_seed, __res3[3]; /* 020 */
152 u32 partial_empty_threshold, __res4; /* 030 */
153 u32 partial_full_threshold, __res5; /* 038 */
154 u32 tx_start_bytes, __res6[3]; /* 040 */
155 u32 tx_deferral, rx_deferral, __res7[2];/* 050 */
156 u32 tx_2part_deferral[2], __res8[2]; /* 060 */
157 u32 slot_time, __res9[3]; /* 070 */
158 u32 mdio_command[4]; /* 080 */
159 u32 mdio_status[4]; /* 090 */
160 u32 mcast_mask[6], __res10[2]; /* 0A0 */
161 u32 mcast_addr[6], __res11[2]; /* 0C0 */
162 u32 int_clock_threshold, __res12[3]; /* 0E0 */
163 u32 hw_addr[6], __res13[61]; /* 0F0 */
164 u32 core_control; /* 1FC */
168 struct resource *mem_res;
169 struct eth_regs __iomem *regs;
171 struct net_device *netdev;
172 struct napi_struct napi;
173 struct phy_device *phydev;
174 struct eth_plat_info *plat;
175 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
176 struct desc *desc_tab; /* coherent */
178 int id; /* logical port ID */
185 /* NPE message structure */
188 u8 cmd, eth_id, byte2, byte3;
189 u8 byte4, byte5, byte6, byte7;
191 u8 byte3, byte2, eth_id, cmd;
192 u8 byte7, byte6, byte5, byte4;
196 /* Ethernet packet descriptor */
198 u32 next; /* pointer to next buffer, unused */
201 u16 buf_len; /* buffer length */
202 u16 pkt_len; /* packet length */
203 u32 data; /* pointer to data buffer in RAM */
211 u16 pkt_len; /* packet length */
212 u16 buf_len; /* buffer length */
213 u32 data; /* pointer to data buffer in RAM */
223 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
224 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
225 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
227 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
228 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
229 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
234 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
235 (n) * sizeof(struct desc))
236 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
238 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
239 ((n) + RX_DESCS) * sizeof(struct desc))
240 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
243 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
246 for (i = 0; i < cnt; i++)
247 dest[i] = swab32(src[i]);
251 static spinlock_t mdio_lock;
252 static struct eth_regs __iomem *mdio_regs; /* mdio command and status only */
253 static struct mii_bus *mdio_bus;
254 static int ports_open;
255 static struct port *npe_port_tab[MAX_NPES];
256 static struct dma_pool *dma_pool;
258 static struct sock_filter ptp_filter[] = {
262 static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
264 u8 *data = skb->data;
269 if (sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4)
272 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
274 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
277 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
278 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
280 memcpy(&lo, &hi[1], sizeof(lo));
282 return (uid_hi == ntohs(*hi) &&
283 uid_lo == ntohl(lo) &&
284 seqid == ntohs(*id));
287 static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
289 struct skb_shared_hwtstamps *shhwtstamps;
290 struct ixp46x_ts_regs *regs;
295 if (!port->hwts_rx_en)
298 ch = PORT2CHANNEL(port);
300 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
302 val = __raw_readl(®s->channel[ch].ch_event);
304 if (!(val & RX_SNAPSHOT_LOCKED))
307 lo = __raw_readl(®s->channel[ch].src_uuid_lo);
308 hi = __raw_readl(®s->channel[ch].src_uuid_hi);
311 seq = (hi >> 16) & 0xffff;
313 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
316 lo = __raw_readl(®s->channel[ch].rx_snap_lo);
317 hi = __raw_readl(®s->channel[ch].rx_snap_hi);
318 ns = ((u64) hi) << 32;
320 ns <<= TICKS_NS_SHIFT;
322 shhwtstamps = skb_hwtstamps(skb);
323 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
324 shhwtstamps->hwtstamp = ns_to_ktime(ns);
326 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
329 static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
331 struct skb_shared_hwtstamps shhwtstamps;
332 struct ixp46x_ts_regs *regs;
333 struct skb_shared_info *shtx;
335 u32 ch, cnt, hi, lo, val;
337 shtx = skb_shinfo(skb);
338 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
339 shtx->tx_flags |= SKBTX_IN_PROGRESS;
343 ch = PORT2CHANNEL(port);
345 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
348 * This really stinks, but we have to poll for the Tx time stamp.
349 * Usually, the time stamp is ready after 4 to 6 microseconds.
351 for (cnt = 0; cnt < 100; cnt++) {
352 val = __raw_readl(®s->channel[ch].ch_event);
353 if (val & TX_SNAPSHOT_LOCKED)
357 if (!(val & TX_SNAPSHOT_LOCKED)) {
358 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
362 lo = __raw_readl(®s->channel[ch].tx_snap_lo);
363 hi = __raw_readl(®s->channel[ch].tx_snap_hi);
364 ns = ((u64) hi) << 32;
366 ns <<= TICKS_NS_SHIFT;
368 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
369 shhwtstamps.hwtstamp = ns_to_ktime(ns);
370 skb_tstamp_tx(skb, &shhwtstamps);
372 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
375 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
377 struct hwtstamp_config cfg;
378 struct ixp46x_ts_regs *regs;
379 struct port *port = netdev_priv(netdev);
382 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
385 if (cfg.flags) /* reserved for future extensions */
388 ch = PORT2CHANNEL(port);
389 regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
391 switch (cfg.tx_type) {
392 case HWTSTAMP_TX_OFF:
393 port->hwts_tx_en = 0;
396 port->hwts_tx_en = 1;
402 switch (cfg.rx_filter) {
403 case HWTSTAMP_FILTER_NONE:
404 port->hwts_rx_en = 0;
406 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
407 port->hwts_rx_en = PTP_SLAVE_MODE;
408 __raw_writel(0, ®s->channel[ch].ch_control);
410 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
411 port->hwts_rx_en = PTP_MASTER_MODE;
412 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control);
418 /* Clear out any old time stamps. */
419 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
420 ®s->channel[ch].ch_event);
422 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
425 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
430 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
431 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
436 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
437 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
439 __raw_writel(((phy_id << 5) | location) & 0xFF,
440 &mdio_regs->mdio_command[2]);
441 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,
442 &mdio_regs->mdio_command[3]);
444 while ((cycles < MAX_MDIO_RETRIES) &&
445 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
450 if (cycles == MAX_MDIO_RETRIES) {
451 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
457 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
458 phy_id, write ? "write" : "read", cycles);
464 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
466 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
469 return 0xFFFF; /* don't return error */
472 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
473 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
476 static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
481 spin_lock_irqsave(&mdio_lock, flags);
482 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
483 spin_unlock_irqrestore(&mdio_lock, flags);
485 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
486 phy_id, location, ret);
491 static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
497 spin_lock_irqsave(&mdio_lock, flags);
498 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
499 spin_unlock_irqrestore(&mdio_lock, flags);
501 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
502 bus->name, phy_id, location, val, ret);
507 static int ixp4xx_mdio_register(void)
511 if (!(mdio_bus = mdiobus_alloc()))
514 if (cpu_is_ixp43x()) {
515 /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */
516 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH))
518 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
520 /* All MII PHY accesses use NPE-B Ethernet registers */
521 if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0))
523 mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
526 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
527 spin_lock_init(&mdio_lock);
528 mdio_bus->name = "IXP4xx MII Bus";
529 mdio_bus->read = &ixp4xx_mdio_read;
530 mdio_bus->write = &ixp4xx_mdio_write;
531 strcpy(mdio_bus->id, "0");
533 if ((err = mdiobus_register(mdio_bus)))
534 mdiobus_free(mdio_bus);
538 static void ixp4xx_mdio_remove(void)
540 mdiobus_unregister(mdio_bus);
541 mdiobus_free(mdio_bus);
545 static void ixp4xx_adjust_link(struct net_device *dev)
547 struct port *port = netdev_priv(dev);
548 struct phy_device *phydev = port->phydev;
553 printk(KERN_INFO "%s: link down\n", dev->name);
558 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
561 port->speed = phydev->speed;
562 port->duplex = phydev->duplex;
565 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
566 &port->regs->tx_control[0]);
568 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
569 &port->regs->tx_control[0]);
571 printk(KERN_INFO "%s: link up, speed %u Mb/s, %s duplex\n",
572 dev->name, port->speed, port->duplex ? "full" : "half");
576 static inline void debug_pkt(struct net_device *dev, const char *func,
582 printk(KERN_DEBUG "%s: %s(%i) ", dev->name, func, len);
583 for (i = 0; i < len; i++) {
584 if (i >= DEBUG_PKT_BYTES)
587 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
595 static inline void debug_desc(u32 phys, struct desc *desc)
598 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
599 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
600 phys, desc->next, desc->buf_len, desc->pkt_len,
601 desc->data, desc->dest_id, desc->src_id, desc->flags,
602 desc->qos, desc->padlen, desc->vlan_tci,
603 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
604 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
605 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
606 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
610 static inline int queue_get_desc(unsigned int queue, struct port *port,
613 u32 phys, tab_phys, n_desc;
616 if (!(phys = qmgr_get_entry(queue)))
619 phys &= ~0x1F; /* mask out non-address bits */
620 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
621 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
622 n_desc = (phys - tab_phys) / sizeof(struct desc);
623 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
624 debug_desc(phys, &tab[n_desc]);
625 BUG_ON(tab[n_desc].next);
629 static inline void queue_put_desc(unsigned int queue, u32 phys,
632 debug_desc(phys, desc);
634 qmgr_put_entry(queue, phys);
635 /* Don't check for queue overflow here, we've allocated sufficient
636 length and queues >= 32 don't support this check anyway. */
640 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
643 dma_unmap_single(&port->netdev->dev, desc->data,
644 desc->buf_len, DMA_TO_DEVICE);
646 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
647 ALIGN((desc->data & 3) + desc->buf_len, 4),
653 static void eth_rx_irq(void *pdev)
655 struct net_device *dev = pdev;
656 struct port *port = netdev_priv(dev);
659 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
661 qmgr_disable_irq(port->plat->rxq);
662 napi_schedule(&port->napi);
665 static int eth_poll(struct napi_struct *napi, int budget)
667 struct port *port = container_of(napi, struct port, napi);
668 struct net_device *dev = port->netdev;
669 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
673 printk(KERN_DEBUG "%s: eth_poll\n", dev->name);
676 while (received < budget) {
681 struct sk_buff *temp;
685 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
687 printk(KERN_DEBUG "%s: eth_poll napi_complete\n",
691 qmgr_enable_irq(rxq);
692 if (!qmgr_stat_below_low_watermark(rxq) &&
693 napi_reschedule(napi)) { /* not empty again */
695 printk(KERN_DEBUG "%s: eth_poll"
696 " napi_reschedule successed\n",
699 qmgr_disable_irq(rxq);
703 printk(KERN_DEBUG "%s: eth_poll all done\n",
706 return received; /* all work done */
709 desc = rx_desc_ptr(port, n);
712 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
713 phys = dma_map_single(&dev->dev, skb->data,
714 RX_BUFF_SIZE, DMA_FROM_DEVICE);
715 if (dma_mapping_error(&dev->dev, phys)) {
721 skb = netdev_alloc_skb(dev,
722 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
726 dev->stats.rx_dropped++;
727 /* put the desc back on RX-ready queue */
728 desc->buf_len = MAX_MRU;
730 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
734 /* process received frame */
737 skb = port->rx_buff_tab[n];
738 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
739 RX_BUFF_SIZE, DMA_FROM_DEVICE);
741 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
742 RX_BUFF_SIZE, DMA_FROM_DEVICE);
743 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
744 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
746 skb_reserve(skb, NET_IP_ALIGN);
747 skb_put(skb, desc->pkt_len);
749 debug_pkt(dev, "eth_poll", skb->data, skb->len);
751 ixp_rx_timestamp(port, skb);
752 skb->protocol = eth_type_trans(skb, dev);
753 dev->stats.rx_packets++;
754 dev->stats.rx_bytes += skb->len;
755 netif_receive_skb(skb);
757 /* put the new buffer on RX-free queue */
759 port->rx_buff_tab[n] = temp;
760 desc->data = phys + NET_IP_ALIGN;
762 desc->buf_len = MAX_MRU;
764 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
769 printk(KERN_DEBUG "eth_poll(): end, not all work done\n");
771 return received; /* not all work done */
775 static void eth_txdone_irq(void *unused)
780 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
782 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
789 BUG_ON(npe_id >= MAX_NPES);
790 port = npe_port_tab[npe_id];
792 phys &= ~0x1F; /* mask out non-address bits */
793 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
794 BUG_ON(n_desc >= TX_DESCS);
795 desc = tx_desc_ptr(port, n_desc);
796 debug_desc(phys, desc);
798 if (port->tx_buff_tab[n_desc]) { /* not the draining packet */
799 port->netdev->stats.tx_packets++;
800 port->netdev->stats.tx_bytes += desc->pkt_len;
802 dma_unmap_tx(port, desc);
804 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
805 port->netdev->name, port->tx_buff_tab[n_desc]);
807 free_buffer_irq(port->tx_buff_tab[n_desc]);
808 port->tx_buff_tab[n_desc] = NULL;
811 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
812 queue_put_desc(port->plat->txreadyq, phys, desc);
813 if (start) { /* TX-ready queue was empty */
815 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
818 netif_wake_queue(port->netdev);
823 static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
825 struct port *port = netdev_priv(dev);
826 unsigned int txreadyq = port->plat->txreadyq;
827 int len, offset, bytes, n;
833 printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
836 if (unlikely(skb->len > MAX_MRU)) {
838 dev->stats.tx_errors++;
842 debug_pkt(dev, "eth_xmit", skb->data, skb->len);
846 offset = 0; /* no need to keep alignment */
850 offset = (int)skb->data & 3; /* keep 32-bit alignment */
851 bytes = ALIGN(offset + len, 4);
852 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
854 dev->stats.tx_dropped++;
857 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
860 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
861 if (dma_mapping_error(&dev->dev, phys)) {
866 dev->stats.tx_dropped++;
870 n = queue_get_desc(txreadyq, port, 1);
872 desc = tx_desc_ptr(port, n);
875 port->tx_buff_tab[n] = skb;
877 port->tx_buff_tab[n] = mem;
879 desc->data = phys + offset;
880 desc->buf_len = desc->pkt_len = len;
882 /* NPE firmware pads short frames with zeros internally */
884 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
886 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
888 printk(KERN_DEBUG "%s: eth_xmit queue full\n", dev->name);
890 netif_stop_queue(dev);
891 /* we could miss TX ready interrupt */
892 /* really empty in fact */
893 if (!qmgr_stat_below_low_watermark(txreadyq)) {
895 printk(KERN_DEBUG "%s: eth_xmit ready again\n",
898 netif_wake_queue(dev);
903 printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
906 ixp_tx_timestamp(port, skb);
907 skb_tx_timestamp(skb);
916 static void eth_set_mcast_list(struct net_device *dev)
918 struct port *port = netdev_priv(dev);
919 struct netdev_hw_addr *ha;
920 u8 diffs[ETH_ALEN], *addr;
922 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
924 if (dev->flags & IFF_ALLMULTI) {
925 for (i = 0; i < ETH_ALEN; i++) {
926 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
927 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
929 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
930 &port->regs->rx_control[0]);
934 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
935 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
936 &port->regs->rx_control[0]);
940 memset(diffs, 0, ETH_ALEN);
943 netdev_for_each_mc_addr(ha, dev) {
945 addr = ha->addr; /* first MAC address */
946 for (i = 0; i < ETH_ALEN; i++)
947 diffs[i] |= addr[i] ^ ha->addr[i];
950 for (i = 0; i < ETH_ALEN; i++) {
951 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
952 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
955 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
956 &port->regs->rx_control[0]);
960 static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
962 struct port *port = netdev_priv(dev);
964 if (!netif_running(dev))
967 if (cpu_is_ixp46x() && cmd == SIOCSHWTSTAMP)
968 return hwtstamp_ioctl(dev, req, cmd);
970 return phy_mii_ioctl(port->phydev, req, cmd);
973 /* ethtool support */
975 static void ixp4xx_get_drvinfo(struct net_device *dev,
976 struct ethtool_drvinfo *info)
978 struct port *port = netdev_priv(dev);
979 strcpy(info->driver, DRV_NAME);
980 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
981 port->firmware[0], port->firmware[1],
982 port->firmware[2], port->firmware[3]);
983 strcpy(info->bus_info, "internal");
986 static int ixp4xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
988 struct port *port = netdev_priv(dev);
989 return phy_ethtool_gset(port->phydev, cmd);
992 static int ixp4xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
994 struct port *port = netdev_priv(dev);
995 return phy_ethtool_sset(port->phydev, cmd);
998 static int ixp4xx_nway_reset(struct net_device *dev)
1000 struct port *port = netdev_priv(dev);
1001 return phy_start_aneg(port->phydev);
1004 static const struct ethtool_ops ixp4xx_ethtool_ops = {
1005 .get_drvinfo = ixp4xx_get_drvinfo,
1006 .get_settings = ixp4xx_get_settings,
1007 .set_settings = ixp4xx_set_settings,
1008 .nway_reset = ixp4xx_nway_reset,
1009 .get_link = ethtool_op_get_link,
1013 static int request_queues(struct port *port)
1017 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1018 "%s:RX-free", port->netdev->name);
1022 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1023 "%s:RX", port->netdev->name);
1027 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1028 "%s:TX", port->netdev->name);
1032 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1033 "%s:TX-ready", port->netdev->name);
1037 /* TX-done queue handles skbs sent out by the NPEs */
1039 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1040 "%s:TX-done", DRV_NAME);
1047 qmgr_release_queue(port->plat->txreadyq);
1049 qmgr_release_queue(TX_QUEUE(port->id));
1051 qmgr_release_queue(port->plat->rxq);
1053 qmgr_release_queue(RXFREE_QUEUE(port->id));
1054 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1055 port->netdev->name);
1059 static void release_queues(struct port *port)
1061 qmgr_release_queue(RXFREE_QUEUE(port->id));
1062 qmgr_release_queue(port->plat->rxq);
1063 qmgr_release_queue(TX_QUEUE(port->id));
1064 qmgr_release_queue(port->plat->txreadyq);
1067 qmgr_release_queue(TXDONE_QUEUE);
1070 static int init_queues(struct port *port)
1075 if (!(dma_pool = dma_pool_create(DRV_NAME, NULL,
1076 POOL_ALLOC_SIZE, 32, 0)))
1079 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
1080 &port->desc_tab_phys)))
1082 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
1083 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
1084 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1086 /* Setup RX buffers */
1087 for (i = 0; i < RX_DESCS; i++) {
1088 struct desc *desc = rx_desc_ptr(port, i);
1089 buffer_t *buff; /* skb or kmalloc()ated memory */
1092 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1096 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1100 desc->buf_len = MAX_MRU;
1101 desc->data = dma_map_single(&port->netdev->dev, data,
1102 RX_BUFF_SIZE, DMA_FROM_DEVICE);
1103 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1107 desc->data += NET_IP_ALIGN;
1108 port->rx_buff_tab[i] = buff;
1114 static void destroy_queues(struct port *port)
1118 if (port->desc_tab) {
1119 for (i = 0; i < RX_DESCS; i++) {
1120 struct desc *desc = rx_desc_ptr(port, i);
1121 buffer_t *buff = port->rx_buff_tab[i];
1123 dma_unmap_single(&port->netdev->dev,
1124 desc->data - NET_IP_ALIGN,
1125 RX_BUFF_SIZE, DMA_FROM_DEVICE);
1129 for (i = 0; i < TX_DESCS; i++) {
1130 struct desc *desc = tx_desc_ptr(port, i);
1131 buffer_t *buff = port->tx_buff_tab[i];
1133 dma_unmap_tx(port, desc);
1137 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1138 port->desc_tab = NULL;
1141 if (!ports_open && dma_pool) {
1142 dma_pool_destroy(dma_pool);
1147 static int eth_open(struct net_device *dev)
1149 struct port *port = netdev_priv(dev);
1150 struct npe *npe = port->npe;
1154 if (!npe_running(npe)) {
1155 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1159 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1160 printk(KERN_ERR "%s: %s not responding\n", dev->name,
1164 port->firmware[0] = msg.byte4;
1165 port->firmware[1] = msg.byte5;
1166 port->firmware[2] = msg.byte6;
1167 port->firmware[3] = msg.byte7;
1170 memset(&msg, 0, sizeof(msg));
1171 msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1172 msg.eth_id = port->id;
1173 msg.byte5 = port->plat->rxq | 0x80;
1174 msg.byte7 = port->plat->rxq << 4;
1175 for (i = 0; i < 8; i++) {
1177 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1181 msg.cmd = NPE_EDB_SETPORTADDRESS;
1182 msg.eth_id = PHYSICAL_ID(port->id);
1183 msg.byte2 = dev->dev_addr[0];
1184 msg.byte3 = dev->dev_addr[1];
1185 msg.byte4 = dev->dev_addr[2];
1186 msg.byte5 = dev->dev_addr[3];
1187 msg.byte6 = dev->dev_addr[4];
1188 msg.byte7 = dev->dev_addr[5];
1189 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1192 memset(&msg, 0, sizeof(msg));
1193 msg.cmd = NPE_FW_SETFIREWALLMODE;
1194 msg.eth_id = port->id;
1195 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1198 if ((err = request_queues(port)) != 0)
1201 if ((err = init_queues(port)) != 0) {
1202 destroy_queues(port);
1203 release_queues(port);
1207 port->speed = 0; /* force "link up" message */
1208 phy_start(port->phydev);
1210 for (i = 0; i < ETH_ALEN; i++)
1211 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1212 __raw_writel(0x08, &port->regs->random_seed);
1213 __raw_writel(0x12, &port->regs->partial_empty_threshold);
1214 __raw_writel(0x30, &port->regs->partial_full_threshold);
1215 __raw_writel(0x08, &port->regs->tx_start_bytes);
1216 __raw_writel(0x15, &port->regs->tx_deferral);
1217 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1218 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1219 __raw_writel(0x80, &port->regs->slot_time);
1220 __raw_writel(0x01, &port->regs->int_clock_threshold);
1222 /* Populate queues with buffers, no failure after this point */
1223 for (i = 0; i < TX_DESCS; i++)
1224 queue_put_desc(port->plat->txreadyq,
1225 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1227 for (i = 0; i < RX_DESCS; i++)
1228 queue_put_desc(RXFREE_QUEUE(port->id),
1229 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1231 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1232 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1233 __raw_writel(0, &port->regs->rx_control[1]);
1234 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1236 napi_enable(&port->napi);
1237 eth_set_mcast_list(dev);
1238 netif_start_queue(dev);
1240 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1243 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1244 eth_txdone_irq, NULL);
1245 qmgr_enable_irq(TXDONE_QUEUE);
1248 /* we may already have RX data, enables IRQ */
1249 napi_schedule(&port->napi);
1253 static int eth_close(struct net_device *dev)
1255 struct port *port = netdev_priv(dev);
1257 int buffs = RX_DESCS; /* allocated RX buffers */
1261 qmgr_disable_irq(port->plat->rxq);
1262 napi_disable(&port->napi);
1263 netif_stop_queue(dev);
1265 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1268 memset(&msg, 0, sizeof(msg));
1269 msg.cmd = NPE_SETLOOPBACK_MODE;
1270 msg.eth_id = port->id;
1272 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1273 printk(KERN_CRIT "%s: unable to enable loopback\n", dev->name);
1276 do { /* drain RX buffers */
1277 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1281 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1282 /* we have to inject some packet */
1285 int n = queue_get_desc(port->plat->txreadyq, port, 1);
1287 desc = tx_desc_ptr(port, n);
1288 phys = tx_desc_phys(port, n);
1289 desc->buf_len = desc->pkt_len = 1;
1291 queue_put_desc(TX_QUEUE(port->id), phys, desc);
1294 } while (++i < MAX_CLOSE_WAIT);
1297 printk(KERN_CRIT "%s: unable to drain RX queue, %i buffer(s)"
1298 " left in NPE\n", dev->name, buffs);
1301 printk(KERN_DEBUG "Draining RX queue took %i cycles\n", i);
1305 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1306 buffs--; /* cancel TX */
1310 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1314 } while (++i < MAX_CLOSE_WAIT);
1317 printk(KERN_CRIT "%s: unable to drain TX queue, %i buffer(s) "
1318 "left in NPE\n", dev->name, buffs);
1321 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1325 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1326 printk(KERN_CRIT "%s: unable to disable loopback\n",
1329 phy_stop(port->phydev);
1332 qmgr_disable_irq(TXDONE_QUEUE);
1333 destroy_queues(port);
1334 release_queues(port);
1338 static const struct net_device_ops ixp4xx_netdev_ops = {
1339 .ndo_open = eth_open,
1340 .ndo_stop = eth_close,
1341 .ndo_start_xmit = eth_xmit,
1342 .ndo_set_multicast_list = eth_set_mcast_list,
1343 .ndo_do_ioctl = eth_ioctl,
1344 .ndo_change_mtu = eth_change_mtu,
1345 .ndo_set_mac_address = eth_mac_addr,
1346 .ndo_validate_addr = eth_validate_addr,
1349 static int __devinit eth_init_one(struct platform_device *pdev)
1352 struct net_device *dev;
1353 struct eth_plat_info *plat = pdev->dev.platform_data;
1355 char phy_id[MII_BUS_ID_SIZE + 3];
1358 if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
1359 pr_err("ixp4xx_eth: bad ptp filter\n");
1363 if (!(dev = alloc_etherdev(sizeof(struct port))))
1366 SET_NETDEV_DEV(dev, &pdev->dev);
1367 port = netdev_priv(dev);
1369 port->id = pdev->id;
1372 case IXP4XX_ETH_NPEA:
1373 port->regs = (struct eth_regs __iomem *)IXP4XX_EthA_BASE_VIRT;
1374 regs_phys = IXP4XX_EthA_BASE_PHYS;
1376 case IXP4XX_ETH_NPEB:
1377 port->regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT;
1378 regs_phys = IXP4XX_EthB_BASE_PHYS;
1380 case IXP4XX_ETH_NPEC:
1381 port->regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT;
1382 regs_phys = IXP4XX_EthC_BASE_PHYS;
1389 dev->netdev_ops = &ixp4xx_netdev_ops;
1390 dev->ethtool_ops = &ixp4xx_ethtool_ops;
1391 dev->tx_queue_len = 100;
1393 netif_napi_add(dev, &port->napi, eth_poll, NAPI_WEIGHT);
1395 if (!(port->npe = npe_request(NPE_ID(port->id)))) {
1400 port->mem_res = request_mem_region(regs_phys, REGS_SIZE, dev->name);
1401 if (!port->mem_res) {
1407 npe_port_tab[NPE_ID(port->id)] = port;
1408 memcpy(dev->dev_addr, plat->hwaddr, ETH_ALEN);
1410 platform_set_drvdata(pdev, dev);
1412 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1413 &port->regs->core_control);
1415 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1418 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy);
1419 port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0,
1420 PHY_INTERFACE_MODE_MII);
1421 if (IS_ERR(port->phydev)) {
1422 err = PTR_ERR(port->phydev);
1426 port->phydev->irq = PHY_POLL;
1428 if ((err = register_netdev(dev)))
1431 printk(KERN_INFO "%s: MII PHY %i on %s\n", dev->name, plat->phy,
1432 npe_name(port->npe));
1437 phy_disconnect(port->phydev);
1439 npe_port_tab[NPE_ID(port->id)] = NULL;
1440 platform_set_drvdata(pdev, NULL);
1441 release_resource(port->mem_res);
1443 npe_release(port->npe);
1449 static int __devexit eth_remove_one(struct platform_device *pdev)
1451 struct net_device *dev = platform_get_drvdata(pdev);
1452 struct port *port = netdev_priv(dev);
1454 unregister_netdev(dev);
1455 phy_disconnect(port->phydev);
1456 npe_port_tab[NPE_ID(port->id)] = NULL;
1457 platform_set_drvdata(pdev, NULL);
1458 npe_release(port->npe);
1459 release_resource(port->mem_res);
1464 static struct platform_driver ixp4xx_eth_driver = {
1465 .driver.name = DRV_NAME,
1466 .probe = eth_init_one,
1467 .remove = eth_remove_one,
1470 static int __init eth_init_module(void)
1473 if ((err = ixp4xx_mdio_register()))
1475 return platform_driver_register(&ixp4xx_eth_driver);
1478 static void __exit eth_cleanup_module(void)
1480 platform_driver_unregister(&ixp4xx_eth_driver);
1481 ixp4xx_mdio_remove();
1484 MODULE_AUTHOR("Krzysztof Halasa");
1485 MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1486 MODULE_LICENSE("GPL v2");
1487 MODULE_ALIAS("platform:ixp4xx_eth");
1488 module_init(eth_init_module);
1489 module_exit(eth_cleanup_module);