drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2 / OMAP3
   5  *
   6  *  Copyright (C) 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/onenand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/delay.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/mach/flash.h>
  38 #include <mach/gpmc.h>
  39 #include <mach/onenand.h>
  40 #include <mach/gpio.h>
  41 #include <mach/pm.h>
  42
  43 #include <linux/dma-mapping.h>
  44 #include <asm/dma-mapping.h>
  45 #include <mach/dma.h>
  46
  47 #include <mach/board.h>
  48
  49 #define DRIVER_NAME "omap2-onenand"
  50
  51 #define ONENAND_IO_SIZE         SZ_128K
  52 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  53
  54 struct omap2_onenand {
  55         struct platform_device *pdev;
  56         int gpmc_cs;
  57         unsigned long phys_base;
  58         int gpio_irq;
  59         struct mtd_info mtd;
  60         struct mtd_partition *parts;
  61         struct onenand_chip onenand;
  62         struct completion irq_done;
  63         struct completion dma_done;
  64         int dma_channel;
  65         int freq;
  66         int (*setup)(void __iomem *base, int freq);
  67 };
  68
  69 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
  70 {
  71         struct omap2_onenand *c = data;
  72
  73         complete(&c->dma_done);
  74 }
  75
  76 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  77 {
  78         struct omap2_onenand *c = dev_id;
  79
  80         complete(&c->irq_done);
  81
  82         return IRQ_HANDLED;
  83 }
  84
  85 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
  86 {
  87         return readw(c->onenand.base + reg);
  88 }
  89
  90 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
  91                              int reg)
  92 {
  93         writew(value, c->onenand.base + reg);
  94 }
  95
  96 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
  97 {
  98         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
  99                msg, state, ctrl, intr);
 100 }
 101
 102 static void wait_warn(char *msg, int state, unsigned int ctrl,
 103                       unsigned int intr)
 104 {
 105         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
 106                "intr 0x%04x\n", msg, state, ctrl, intr);
 107 }
 108
 109 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 110 {
 111         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 112         unsigned int intr = 0;
 113         unsigned int ctrl;
 114         unsigned long timeout;
 115         u32 syscfg;
 116
 117         if (state == FL_RESETING) {
 118                 int i;
 119
 120                 for (i = 0; i < 20; i++) {
 121                         udelay(1);
 122                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 123                         if (intr & ONENAND_INT_MASTER)
 124                                 break;
 125                 }
 126                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 127                 if (ctrl & ONENAND_CTRL_ERROR) {
 128                         wait_err("controller error", state, ctrl, intr);
 129                         return -EIO;
 130                 }
 131                 if (!(intr & ONENAND_INT_RESET)) {
 132                         wait_err("timeout", state, ctrl, intr);
 133                         return -EIO;
 134                 }
 135                 return 0;
 136         }
 137
 138         if (state != FL_READING) {
 139                 int result;
 140
 141                 /* Turn interrupts on */
 142                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 143                 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
 144                         syscfg |= ONENAND_SYS_CFG1_IOBE;
 145                         write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 146                         if (cpu_is_omap34xx())
 147                                 /* Add a delay to let GPIO settle */
 148                                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 149                 }
 150
 151                 INIT_COMPLETION(c->irq_done);
 152                 if (c->gpio_irq) {
 153                         result = omap_get_gpio_datain(c->gpio_irq);
 154                         if (result == -1) {
 155                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 156                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 157                                 wait_err("gpio error", state, ctrl, intr);
 158                                 return -EIO;
 159                         }
 160                 } else
 161                         result = 0;
 162                 if (result == 0) {
 163                         int retry_cnt = 0;
 164 retry:
 165                         result = wait_for_completion_timeout(&c->irq_done,
 166                                                     msecs_to_jiffies(20));
 167                         if (result == 0) {
 168                                 /* Timeout after 20ms */
 169                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 170                                 if (ctrl & ONENAND_CTRL_ONGO) {
 171                                         /*
 172                                          * The operation seems to be still going
 173                                          * so give it some more time.
 174                                          */
 175                                         retry_cnt += 1;
 176                                         if (retry_cnt < 3)
 177                                                 goto retry;
 178                                         intr = read_reg(c,
 179                                                         ONENAND_REG_INTERRUPT);
 180                                         wait_err("timeout", state, ctrl, intr);
 181                                         return -EIO;
 182                                 }
 183                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 184                                 if ((intr & ONENAND_INT_MASTER) == 0)
 185                                         wait_warn("timeout", state, ctrl, intr);
 186                         }
 187                 }
 188         } else {
 189                 /* Turn interrupts off */
 190                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 191                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 192                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 193
 194                 timeout = jiffies + msecs_to_jiffies(20);
 195                 while (time_before(jiffies, timeout)) {
 196                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 197                         if (intr & ONENAND_INT_MASTER)
 198                                 break;
 199                 }
 200         }
 201
 202         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 203         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 204
 205         if (intr & ONENAND_INT_READ) {
 206                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
 207
 208                 if (ecc) {
 209                         unsigned int addr1, addr8;
 210
 211                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
 212                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
 213                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 214                                 printk(KERN_ERR "onenand_wait: ECC error = "
 215                                        "0x%04x, addr1 %#x, addr8 %#x\n",
 216                                        ecc, addr1, addr8);
 217                                 mtd->ecc_stats.failed++;
 218                                 return -EBADMSG;
 219                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
 220                                 printk(KERN_NOTICE "onenand_wait: correctable "
 221                                        "ECC error = 0x%04x, addr1 %#x, "
 222                                        "addr8 %#x\n", ecc, addr1, addr8);
 223                                 mtd->ecc_stats.corrected++;
 224                         }
 225                 }
 226         } else if (state == FL_READING) {
 227                 wait_err("timeout", state, ctrl, intr);
 228                 return -EIO;
 229         }
 230
 231         if (ctrl & ONENAND_CTRL_ERROR) {
 232                 wait_err("controller error", state, ctrl, intr);
 233                 if (ctrl & ONENAND_CTRL_LOCK)
 234                         printk(KERN_ERR "onenand_wait: "
 235                                         "Device is write protected!!!\n");
 236                 return -EIO;
 237         }
 238
 239         if (ctrl & 0xFE9F)
 240                 wait_warn("unexpected controller status", state, ctrl, intr);
 241
 242         return 0;
 243 }
 244
 245 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 246 {
 247         struct onenand_chip *this = mtd->priv;
 248
 249         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 250                 if (area == ONENAND_DATARAM)
 251                         return mtd->writesize;
 252                 if (area == ONENAND_SPARERAM)
 253                         return mtd->oobsize;
 254         }
 255
 256         return 0;
 257 }
 258
 259 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
 260
 261 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 262                                         unsigned char *buffer, int offset,
 263                                         size_t count)
 264 {
 265         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 266         struct onenand_chip *this = mtd->priv;
 267         dma_addr_t dma_src, dma_dst;
 268         int bram_offset;
 269         unsigned long timeout;
 270         void *buf = (void *)buffer;
 271         size_t xtra;
 272         volatile unsigned *done;
 273
 274         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 275         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 276                 goto out_copy;
 277
 278         if (buf >= high_memory) {
 279                 struct page *p1;
 280
 281                 if (((size_t)buf & PAGE_MASK) !=
 282                     ((size_t)(buf + count - 1) & PAGE_MASK))
 283                         goto out_copy;
 284                 p1 = vmalloc_to_page(buf);
 285                 if (!p1)
 286                         goto out_copy;
 287                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 288         }
 289
 290         xtra = count & 3;
 291         if (xtra) {
 292                 count -= xtra;
 293                 memcpy(buf + count, this->base + bram_offset + count, xtra);
 294         }
 295
 296         dma_src = c->phys_base + bram_offset;
 297         dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
 298         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 299                 dev_err(&c->pdev->dev,
 300                         "Couldn't DMA map a %d byte buffer\n",
 301                         count);
 302                 goto out_copy;
 303         }
 304
 305         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 306                                      count >> 2, 1, 0, 0, 0);
 307         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 308                                 dma_src, 0, 0);
 309         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 310                                  dma_dst, 0, 0);
 311
 312         INIT_COMPLETION(c->dma_done);
 313         omap_start_dma(c->dma_channel);
 314
 315         timeout = jiffies + msecs_to_jiffies(20);
 316         done = &c->dma_done.done;
 317         while (time_before(jiffies, timeout))
 318                 if (*done)
 319                         break;
 320
 321         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 322
 323         if (!*done) {
 324                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 325                 goto out_copy;
 326         }
 327
 328         return 0;
 329
 330 out_copy:
 331         memcpy(buf, this->base + bram_offset, count);
 332         return 0;
 333 }
 334
 335 static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 336                                          const unsigned char *buffer,
 337                                          int offset, size_t count)
 338 {
 339         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 340         struct onenand_chip *this = mtd->priv;
 341         dma_addr_t dma_src, dma_dst;
 342         int bram_offset;
 343         unsigned long timeout;
 344         void *buf = (void *)buffer;
 345         volatile unsigned *done;
 346
 347         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 348         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 349                 goto out_copy;
 350
 351         /* panic_write() may be in an interrupt context */
 352         if (in_interrupt())
 353                 goto out_copy;
 354
 355         if (buf >= high_memory) {
 356                 struct page *p1;
 357
 358                 if (((size_t)buf & PAGE_MASK) !=
 359                     ((size_t)(buf + count - 1) & PAGE_MASK))
 360                         goto out_copy;
 361                 p1 = vmalloc_to_page(buf);
 362                 if (!p1)
 363                         goto out_copy;
 364                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 365         }
 366
 367         dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
 368         dma_dst = c->phys_base + bram_offset;
 369         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 370                 dev_err(&c->pdev->dev,
 371                         "Couldn't DMA map a %d byte buffer\n",
 372                         count);
 373                 return -1;
 374         }
 375
 376         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 377                                      count >> 2, 1, 0, 0, 0);
 378         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 379                                 dma_src, 0, 0);
 380         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 381                                  dma_dst, 0, 0);
 382
 383         INIT_COMPLETION(c->dma_done);
 384         omap_start_dma(c->dma_channel);
 385
 386         timeout = jiffies + msecs_to_jiffies(20);
 387         done = &c->dma_done.done;
 388         while (time_before(jiffies, timeout))
 389                 if (*done)
 390                         break;
 391
 392         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
 393
 394         if (!*done) {
 395                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 396                 goto out_copy;
 397         }
 398
 399         return 0;
 400
 401 out_copy:
 402         memcpy(this->base + bram_offset, buf, count);
 403         return 0;
 404 }
 405
 406 #else
 407
 408 int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 409                                  unsigned char *buffer, int offset,
 410                                  size_t count);
 411
 412 int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 413                                   const unsigned char *buffer,
 414                                   int offset, size_t count);
 415
 416 #endif
 417
 418 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
 419
 420 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 421                                         unsigned char *buffer, int offset,
 422                                         size_t count)
 423 {
 424         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 425         struct onenand_chip *this = mtd->priv;
 426         dma_addr_t dma_src, dma_dst;
 427         int bram_offset;
 428
 429         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 430         /* DMA is not used.  Revisit PM requirements before enabling it. */
 431         if (1 || (c->dma_channel < 0) ||
 432             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
 433             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
 434                 memcpy(buffer, (__force void *)(this->base + bram_offset),
 435                        count);
 436                 return 0;
 437         }
 438
 439         dma_src = c->phys_base + bram_offset;
 440         dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
 441                                  DMA_FROM_DEVICE);
 442         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 443                 dev_err(&c->pdev->dev,
 444                         "Couldn't DMA map a %d byte buffer\n",
 445                         count);
 446                 return -1;
 447         }
 448
 449         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 450                                      count / 4, 1, 0, 0, 0);
 451         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 452                                 dma_src, 0, 0);
 453         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 454                                  dma_dst, 0, 0);
 455
 456         INIT_COMPLETION(c->dma_done);
 457         omap_start_dma(c->dma_channel);
 458         wait_for_completion(&c->dma_done);
 459
 460         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 461
 462         return 0;
 463 }
 464
 465 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 466                                          const unsigned char *buffer,
 467                                          int offset, size_t count)
 468 {
 469         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 470         struct onenand_chip *this = mtd->priv;
 471         dma_addr_t dma_src, dma_dst;
 472         int bram_offset;
 473
 474         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 475         /* DMA is not used.  Revisit PM requirements before enabling it. */
 476         if (1 || (c->dma_channel < 0) ||
 477             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
 478             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
 479                 memcpy((__force void *)(this->base + bram_offset), buffer,
 480                        count);
 481                 return 0;
 482         }
 483
 484         dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
 485                                  DMA_TO_DEVICE);
 486         dma_dst = c->phys_base + bram_offset;
 487         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 488                 dev_err(&c->pdev->dev,
 489                         "Couldn't DMA map a %d byte buffer\n",
 490                         count);
 491                 return -1;
 492         }
 493
 494         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
 495                                      count / 2, 1, 0, 0, 0);
 496         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 497                                 dma_src, 0, 0);
 498         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 499                                  dma_dst, 0, 0);
 500
 501         INIT_COMPLETION(c->dma_done);
 502         omap_start_dma(c->dma_channel);
 503         wait_for_completion(&c->dma_done);
 504
 505         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
 506
 507         return 0;
 508 }
 509
 510 #else
 511
 512 int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 513                                  unsigned char *buffer, int offset,
 514                                  size_t count);
 515
 516 int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 517                                   const unsigned char *buffer,
 518                                   int offset, size_t count);
 519
 520 #endif
 521
 522 static struct platform_driver omap2_onenand_driver;
 523
 524 static int __adjust_timing(struct device *dev, void *data)
 525 {
 526         int ret = 0;
 527         struct omap2_onenand *c;
 528
 529         c = dev_get_drvdata(dev);
 530
 531         BUG_ON(c->setup == NULL);
 532
 533         /* DMA is not in use so this is all that is needed */
 534         /* Revisit for OMAP3! */
 535         ret = c->setup(c->onenand.base, c->freq);
 536
 537         return ret;
 538 }
 539
 540 int omap2_onenand_rephase(void)
 541 {
 542         return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
 543                                       NULL, __adjust_timing);
 544 }
 545
 546 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
 547 {
 548         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 549
 550         /* With certain content in the buffer RAM, the OMAP boot ROM code
 551          * can recognize the flash chip incorrectly. Zero it out before
 552          * soft reset.
 553          */
 554         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 555 }
 556
 557 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
 558 {
 559         struct omap_onenand_platform_data *pdata;
 560         struct omap2_onenand *c;
 561         int r;
 562
 563         pdata = pdev->dev.platform_data;
 564         if (pdata == NULL) {
 565                 dev_err(&pdev->dev, "platform data missing\n");
 566                 return -ENODEV;
 567         }
 568
 569         c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 570         if (!c)
 571                 return -ENOMEM;
 572
 573         init_completion(&c->irq_done);
 574         init_completion(&c->dma_done);
 575         c->gpmc_cs = pdata->cs;
 576         c->gpio_irq = pdata->gpio_irq;
 577         c->dma_channel = pdata->dma_channel;
 578         if (c->dma_channel < 0) {
 579                 /* if -1, don't use DMA */
 580                 c->gpio_irq = 0;
 581         }
 582
 583         r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
 584         if (r < 0) {
 585                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
 586                 goto err_kfree;
 587         }
 588
 589         if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
 590                                pdev->dev.driver->name) == NULL) {
 591                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
 592                         "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
 593                 r = -EBUSY;
 594                 goto err_free_cs;
 595         }
 596         c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
 597         if (c->onenand.base == NULL) {
 598                 r = -ENOMEM;
 599                 goto err_release_mem_region;
 600         }
 601
 602         if (pdata->onenand_setup != NULL) {
 603                 r = pdata->onenand_setup(c->onenand.base, c->freq);
 604                 if (r < 0) {
 605                         dev_err(&pdev->dev, "Onenand platform setup failed: "
 606                                 "%d\n", r);
 607                         goto err_iounmap;
 608                 }
 609                 c->setup = pdata->onenand_setup;
 610         }
 611
 612         if (c->gpio_irq) {
 613                 if ((r = omap_request_gpio(c->gpio_irq)) < 0) {
 614                         dev_err(&pdev->dev,  "Failed to request GPIO%d for "
 615                                 "OneNAND\n", c->gpio_irq);
 616                         goto err_iounmap;
 617         }
 618         omap_set_gpio_direction(c->gpio_irq, 1);
 619
 620         if ((r = request_irq(OMAP_GPIO_IRQ(c->gpio_irq),
 621                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
 622                              pdev->dev.driver->name, c)) < 0)
 623                 goto err_release_gpio;
 624         }
 625
 626         if (c->dma_channel >= 0) {
 627                 r = omap_request_dma(0, pdev->dev.driver->name,
 628                                      omap2_onenand_dma_cb, (void *) c,
 629                                      &c->dma_channel);
 630                 if (r == 0) {
 631                         omap_set_dma_write_mode(c->dma_channel,
 632                                                 OMAP_DMA_WRITE_NON_POSTED);
 633                         omap_set_dma_src_data_pack(c->dma_channel, 1);
 634                         omap_set_dma_src_burst_mode(c->dma_channel,
 635                                                     OMAP_DMA_DATA_BURST_8);
 636                         omap_set_dma_dest_data_pack(c->dma_channel, 1);
 637                         omap_set_dma_dest_burst_mode(c->dma_channel,
 638                                                      OMAP_DMA_DATA_BURST_8);
 639                 } else {
 640                         dev_info(&pdev->dev,
 641                                  "failed to allocate DMA for OneNAND, "
 642                                  "using PIO instead\n");
 643                         c->dma_channel = -1;
 644                 }
 645         }
 646
 647         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
 648                  "base %p\n", c->gpmc_cs, c->phys_base,
 649                  c->onenand.base);
 650
 651         c->pdev = pdev;
 652         c->mtd.name = pdev->dev.bus_id;
 653         c->mtd.priv = &c->onenand;
 654         c->mtd.owner = THIS_MODULE;
 655
 656         if (c->dma_channel >= 0) {
 657                 struct onenand_chip *this = &c->onenand;
 658
 659                 this->wait = omap2_onenand_wait;
 660                 if (cpu_is_omap34xx()) {
 661                         this->read_bufferram = omap3_onenand_read_bufferram;
 662                         this->write_bufferram = omap3_onenand_write_bufferram;
 663                 } else {
 664                         this->read_bufferram = omap2_onenand_read_bufferram;
 665                         this->write_bufferram = omap2_onenand_write_bufferram;
 666                 }
 667         }
 668
 669         if ((r = onenand_scan(&c->mtd, 1)) < 0)
 670                 goto err_release_dma;
 671
 672         switch ((c->onenand.version_id >> 4) & 0xf) {
 673         case 0:
 674                 c->freq = 40;
 675                 break;
 676         case 1:
 677                 c->freq = 54;
 678                 break;
 679         case 2:
 680                 c->freq = 66;
 681                 break;
 682         case 3:
 683                 c->freq = 83;
 684                 break;
 685         }
 686
 687 #ifdef CONFIG_MTD_PARTITIONS
 688         if (pdata->parts != NULL)
 689                 r = add_mtd_partitions(&c->mtd, pdata->parts,
 690                                        pdata->nr_parts);
 691         else
 692 #endif
 693                 r = add_mtd_device(&c->mtd);
 694         if (r < 0)
 695                 goto err_release_onenand;
 696
 697         platform_set_drvdata(pdev, c);
 698
 699         return 0;
 700
 701 err_release_onenand:
 702         onenand_release(&c->mtd);
 703 err_release_dma:
 704         if (c->dma_channel != -1)
 705                 omap_free_dma(c->dma_channel);
 706         if (c->gpio_irq)
 707                 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
 708 err_release_gpio:
 709         if (c->gpio_irq)
 710                 omap_free_gpio(c->gpio_irq);
 711 err_iounmap:
 712         iounmap(c->onenand.base);
 713 err_release_mem_region:
 714         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
 715 err_free_cs:
 716         gpmc_cs_free(c->gpmc_cs);
 717 err_kfree:
 718         kfree(c);
 719
 720         return r;
 721 }
 722
 723 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
 724 {
 725         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 726
 727         BUG_ON(c == NULL);
 728
 729 #ifdef CONFIG_MTD_PARTITIONS
 730         if (c->parts)
 731                 del_mtd_partitions(&c->mtd);
 732         else
 733                 del_mtd_device(&c->mtd);
 734 #else
 735         del_mtd_device(&c->mtd);
 736 #endif
 737
 738         onenand_release(&c->mtd);
 739         if (c->dma_channel != -1)
 740                 omap_free_dma(c->dma_channel);
 741         omap2_onenand_shutdown(pdev);
 742         platform_set_drvdata(pdev, NULL);
 743         if (c->gpio_irq) {
 744                 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
 745                 omap_free_gpio(c->gpio_irq);
 746         }
 747         iounmap(c->onenand.base);
 748         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
 749         kfree(c);
 750
 751         return 0;
 752 }
 753
 754 static struct platform_driver omap2_onenand_driver = {
 755         .probe          = omap2_onenand_probe,
 756         .remove         = omap2_onenand_remove,
 757         .shutdown       = omap2_onenand_shutdown,
 758         .driver         = {
 759                 .name   = DRIVER_NAME,
 760                 .owner  = THIS_MODULE,
 761         },
 762 };
 763
 764 static int __init omap2_onenand_init(void)
 765 {
 766         printk(KERN_INFO "OneNAND driver initializing\n");
 767         return platform_driver_register(&omap2_onenand_driver);
 768 }
 769
 770 static void __exit omap2_onenand_exit(void)
 771 {
 772         platform_driver_unregister(&omap2_onenand_driver);
 773 }
 774
 775 module_init(omap2_onenand_init);
 776 module_exit(omap2_onenand_exit);
 777
 778 MODULE_ALIAS(DRIVER_NAME);
 779 MODULE_LICENSE("GPL");
 780 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 781 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");