drivers/mtd/nand/omap2.c

   1 /*
   2  * Copyright © 2004 Texas Instruments, Jian Zhang <jzhang@ti.com>
   3  * Copyright © 2004 Micron Technology Inc.
   4  * Copyright © 2004 David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/platform_device.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/sched.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/io.h>
  21 #include <linux/slab.h>
  22
  23 #include <plat/dma.h>
  24 #include <plat/gpmc.h>
  25 #include <plat/nand.h>
  26
  27 #define DRIVER_NAME     "omap2-nand"
  28 #define OMAP_NAND_TIMEOUT_MS    5000
  29
  30 #define NAND_Ecc_P1e            (1 << 0)
  31 #define NAND_Ecc_P2e            (1 << 1)
  32 #define NAND_Ecc_P4e            (1 << 2)
  33 #define NAND_Ecc_P8e            (1 << 3)
  34 #define NAND_Ecc_P16e           (1 << 4)
  35 #define NAND_Ecc_P32e           (1 << 5)
  36 #define NAND_Ecc_P64e           (1 << 6)
  37 #define NAND_Ecc_P128e          (1 << 7)
  38 #define NAND_Ecc_P256e          (1 << 8)
  39 #define NAND_Ecc_P512e          (1 << 9)
  40 #define NAND_Ecc_P1024e         (1 << 10)
  41 #define NAND_Ecc_P2048e         (1 << 11)
  42
  43 #define NAND_Ecc_P1o            (1 << 16)
  44 #define NAND_Ecc_P2o            (1 << 17)
  45 #define NAND_Ecc_P4o            (1 << 18)
  46 #define NAND_Ecc_P8o            (1 << 19)
  47 #define NAND_Ecc_P16o           (1 << 20)
  48 #define NAND_Ecc_P32o           (1 << 21)
  49 #define NAND_Ecc_P64o           (1 << 22)
  50 #define NAND_Ecc_P128o          (1 << 23)
  51 #define NAND_Ecc_P256o          (1 << 24)
  52 #define NAND_Ecc_P512o          (1 << 25)
  53 #define NAND_Ecc_P1024o         (1 << 26)
  54 #define NAND_Ecc_P2048o         (1 << 27)
  55
  56 #define TF(value)       (value ? 1 : 0)
  57
  58 #define P2048e(a)       (TF(a & NAND_Ecc_P2048e)        << 0)
  59 #define P2048o(a)       (TF(a & NAND_Ecc_P2048o)        << 1)
  60 #define P1e(a)          (TF(a & NAND_Ecc_P1e)           << 2)
  61 #define P1o(a)          (TF(a & NAND_Ecc_P1o)           << 3)
  62 #define P2e(a)          (TF(a & NAND_Ecc_P2e)           << 4)
  63 #define P2o(a)          (TF(a & NAND_Ecc_P2o)           << 5)
  64 #define P4e(a)          (TF(a & NAND_Ecc_P4e)           << 6)
  65 #define P4o(a)          (TF(a & NAND_Ecc_P4o)           << 7)
  66
  67 #define P8e(a)          (TF(a & NAND_Ecc_P8e)           << 0)
  68 #define P8o(a)          (TF(a & NAND_Ecc_P8o)           << 1)
  69 #define P16e(a)         (TF(a & NAND_Ecc_P16e)          << 2)
  70 #define P16o(a)         (TF(a & NAND_Ecc_P16o)          << 3)
  71 #define P32e(a)         (TF(a & NAND_Ecc_P32e)          << 4)
  72 #define P32o(a)         (TF(a & NAND_Ecc_P32o)          << 5)
  73 #define P64e(a)         (TF(a & NAND_Ecc_P64e)          << 6)
  74 #define P64o(a)         (TF(a & NAND_Ecc_P64o)          << 7)
  75
  76 #define P128e(a)        (TF(a & NAND_Ecc_P128e)         << 0)
  77 #define P128o(a)        (TF(a & NAND_Ecc_P128o)         << 1)
  78 #define P256e(a)        (TF(a & NAND_Ecc_P256e)         << 2)
  79 #define P256o(a)        (TF(a & NAND_Ecc_P256o)         << 3)
  80 #define P512e(a)        (TF(a & NAND_Ecc_P512e)         << 4)
  81 #define P512o(a)        (TF(a & NAND_Ecc_P512o)         << 5)
  82 #define P1024e(a)       (TF(a & NAND_Ecc_P1024e)        << 6)
  83 #define P1024o(a)       (TF(a & NAND_Ecc_P1024o)        << 7)
  84
  85 #define P8e_s(a)        (TF(a & NAND_Ecc_P8e)           << 0)
  86 #define P8o_s(a)        (TF(a & NAND_Ecc_P8o)           << 1)
  87 #define P16e_s(a)       (TF(a & NAND_Ecc_P16e)          << 2)
  88 #define P16o_s(a)       (TF(a & NAND_Ecc_P16o)          << 3)
  89 #define P1e_s(a)        (TF(a & NAND_Ecc_P1e)           << 4)
  90 #define P1o_s(a)        (TF(a & NAND_Ecc_P1o)           << 5)
  91 #define P2e_s(a)        (TF(a & NAND_Ecc_P2e)           << 6)
  92 #define P2o_s(a)        (TF(a & NAND_Ecc_P2o)           << 7)
  93
  94 #define P4e_s(a)        (TF(a & NAND_Ecc_P4e)           << 0)
  95 #define P4o_s(a)        (TF(a & NAND_Ecc_P4o)           << 1)
  96
  97 /* oob info generated runtime depending on ecc algorithm and layout selected */
  98 static struct nand_ecclayout omap_oobinfo;
  99 /* Define some generic bad / good block scan pattern which are used
 100  * while scanning a device for factory marked good / bad blocks
 101  */
 102 static uint8_t scan_ff_pattern[] = { 0xff };
 103 static struct nand_bbt_descr bb_descrip_flashbased = {
 104         .options = NAND_BBT_SCANEMPTY | NAND_BBT_SCANALLPAGES,
 105         .offs = 0,
 106         .len = 1,
 107         .pattern = scan_ff_pattern,
 108 };
 109
 110
 111 struct omap_nand_info {
 112         struct nand_hw_control          controller;
 113         struct omap_nand_platform_data  *pdata;
 114         struct mtd_info                 mtd;
 115         struct nand_chip                nand;
 116         struct platform_device          *pdev;
 117
 118         int                             gpmc_cs;
 119         unsigned long                   phys_base;
 120         struct completion               comp;
 121         int                             dma_ch;
 122         int                             gpmc_irq;
 123         enum {
 124                 OMAP_NAND_IO_READ = 0,  /* read */
 125                 OMAP_NAND_IO_WRITE,     /* write */
 126         } iomode;
 127         u_char                          *buf;
 128         int                                     buf_len;
 129 };
 130
 131 /**
 132  * omap_hwcontrol - hardware specific access to control-lines
 133  * @mtd: MTD device structure
 134  * @cmd: command to device
 135  * @ctrl:
 136  * NAND_NCE: bit 0 -> don't care
 137  * NAND_CLE: bit 1 -> Command Latch
 138  * NAND_ALE: bit 2 -> Address Latch
 139  *
 140  * NOTE: boards may use different bits for these!!
 141  */
 142 static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 143 {
 144         struct omap_nand_info *info = container_of(mtd,
 145                                         struct omap_nand_info, mtd);
 146
 147         if (cmd != NAND_CMD_NONE) {
 148                 if (ctrl & NAND_CLE)
 149                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd);
 150
 151                 else if (ctrl & NAND_ALE)
 152                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd);
 153
 154                 else /* NAND_NCE */
 155                         gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd);
 156         }
 157 }
 158
 159 /**
 160  * omap_read_buf8 - read data from NAND controller into buffer
 161  * @mtd: MTD device structure
 162  * @buf: buffer to store date
 163  * @len: number of bytes to read
 164  */
 165 static void omap_read_buf8(struct mtd_info *mtd, u_char *buf, int len)
 166 {
 167         struct nand_chip *nand = mtd->priv;
 168
 169         ioread8_rep(nand->IO_ADDR_R, buf, len);
 170 }
 171
 172 /**
 173  * omap_write_buf8 - write buffer to NAND controller
 174  * @mtd: MTD device structure
 175  * @buf: data buffer
 176  * @len: number of bytes to write
 177  */
 178 static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
 179 {
 180         struct omap_nand_info *info = container_of(mtd,
 181                                                 struct omap_nand_info, mtd);
 182         u_char *p = (u_char *)buf;
 183         u32     status = 0;
 184
 185         while (len--) {
 186                 iowrite8(*p++, info->nand.IO_ADDR_W);
 187                 /* wait until buffer is available for write */
 188                 do {
 189                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 190                 } while (!status);
 191         }
 192 }
 193
 194 /**
 195  * omap_read_buf16 - read data from NAND controller into buffer
 196  * @mtd: MTD device structure
 197  * @buf: buffer to store date
 198  * @len: number of bytes to read
 199  */
 200 static void omap_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 201 {
 202         struct nand_chip *nand = mtd->priv;
 203
 204         ioread16_rep(nand->IO_ADDR_R, buf, len / 2);
 205 }
 206
 207 /**
 208  * omap_write_buf16 - write buffer to NAND controller
 209  * @mtd: MTD device structure
 210  * @buf: data buffer
 211  * @len: number of bytes to write
 212  */
 213 static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
 214 {
 215         struct omap_nand_info *info = container_of(mtd,
 216                                                 struct omap_nand_info, mtd);
 217         u16 *p = (u16 *) buf;
 218         u32     status = 0;
 219         /* FIXME try bursts of writesw() or DMA ... */
 220         len >>= 1;
 221
 222         while (len--) {
 223                 iowrite16(*p++, info->nand.IO_ADDR_W);
 224                 /* wait until buffer is available for write */
 225                 do {
 226                         status = gpmc_read_status(GPMC_STATUS_BUFFER);
 227                 } while (!status);
 228         }
 229 }
 230
 231 /**
 232  * omap_read_buf_pref - read data from NAND controller into buffer
 233  * @mtd: MTD device structure
 234  * @buf: buffer to store date
 235  * @len: number of bytes to read
 236  */
 237 static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 238 {
 239         struct omap_nand_info *info = container_of(mtd,
 240                                                 struct omap_nand_info, mtd);
 241         uint32_t r_count = 0;
 242         int ret = 0;
 243         u32 *p = (u32 *)buf;
 244
 245         /* take care of subpage reads */
 246         if (len % 4) {
 247                 if (info->nand.options & NAND_BUSWIDTH_16)
 248                         omap_read_buf16(mtd, buf, len % 4);
 249                 else
 250                         omap_read_buf8(mtd, buf, len % 4);
 251                 p = (u32 *) (buf + len % 4);
 252                 len -= len % 4;
 253         }
 254
 255         /* configure and start prefetch transfer */
 256         ret = gpmc_prefetch_enable(info->gpmc_cs,
 257                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0);
 258         if (ret) {
 259                 /* PFPW engine is busy, use cpu copy method */
 260                 if (info->nand.options & NAND_BUSWIDTH_16)
 261                         omap_read_buf16(mtd, (u_char *)p, len);
 262                 else
 263                         omap_read_buf8(mtd, (u_char *)p, len);
 264         } else {
 265                 do {
 266                         r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 267                         r_count = r_count >> 2;
 268                         ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
 269                         p += r_count;
 270                         len -= r_count << 2;
 271                 } while (len);
 272                 /* disable and stop the PFPW engine */
 273                 gpmc_prefetch_reset(info->gpmc_cs);
 274         }
 275 }
 276
 277 /**
 278  * omap_write_buf_pref - write buffer to NAND controller
 279  * @mtd: MTD device structure
 280  * @buf: data buffer
 281  * @len: number of bytes to write
 282  */
 283 static void omap_write_buf_pref(struct mtd_info *mtd,
 284                                         const u_char *buf, int len)
 285 {
 286         struct omap_nand_info *info = container_of(mtd,
 287                                                 struct omap_nand_info, mtd);
 288         uint32_t w_count = 0;
 289         int i = 0, ret = 0;
 290         u16 *p = (u16 *)buf;
 291         unsigned long tim, limit;
 292
 293         /* take care of subpage writes */
 294         if (len % 2 != 0) {
 295                 writeb(*buf, info->nand.IO_ADDR_W);
 296                 p = (u16 *)(buf + 1);
 297                 len--;
 298         }
 299
 300         /*  configure and start prefetch transfer */
 301         ret = gpmc_prefetch_enable(info->gpmc_cs,
 302                         PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1);
 303         if (ret) {
 304                 /* PFPW engine is busy, use cpu copy method */
 305                 if (info->nand.options & NAND_BUSWIDTH_16)
 306                         omap_write_buf16(mtd, (u_char *)p, len);
 307                 else
 308                         omap_write_buf8(mtd, (u_char *)p, len);
 309         } else {
 310                 while (len) {
 311                         w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 312                         w_count = w_count >> 1;
 313                         for (i = 0; (i < w_count) && len; i++, len -= 2)
 314                                 iowrite16(*p++, info->nand.IO_ADDR_W);
 315                 }
 316                 /* wait for data to flushed-out before reset the prefetch */
 317                 tim = 0;
 318                 limit = (loops_per_jiffy *
 319                                         msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 320                 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 321                         cpu_relax();
 322
 323                 /* disable and stop the PFPW engine */
 324                 gpmc_prefetch_reset(info->gpmc_cs);
 325         }
 326 }
 327
 328 /*
 329  * omap_nand_dma_cb: callback on the completion of dma transfer
 330  * @lch: logical channel
 331  * @ch_satuts: channel status
 332  * @data: pointer to completion data structure
 333  */
 334 static void omap_nand_dma_cb(int lch, u16 ch_status, void *data)
 335 {
 336         complete((struct completion *) data);
 337 }
 338
 339 /*
 340  * omap_nand_dma_transfer: configer and start dma transfer
 341  * @mtd: MTD device structure
 342  * @addr: virtual address in RAM of source/destination
 343  * @len: number of data bytes to be transferred
 344  * @is_write: flag for read/write operation
 345  */
 346 static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 347                                         unsigned int len, int is_write)
 348 {
 349         struct omap_nand_info *info = container_of(mtd,
 350                                         struct omap_nand_info, mtd);
 351         enum dma_data_direction dir = is_write ? DMA_TO_DEVICE :
 352                                                         DMA_FROM_DEVICE;
 353         dma_addr_t dma_addr;
 354         int ret;
 355         unsigned long tim, limit;
 356
 357         /* The fifo depth is 64 bytes max.
 358          * But configure the FIFO-threahold to 32 to get a sync at each frame
 359          * and frame length is 32 bytes.
 360          */
 361         int buf_len = len >> 6;
 362
 363         if (addr >= high_memory) {
 364                 struct page *p1;
 365
 366                 if (((size_t)addr & PAGE_MASK) !=
 367                         ((size_t)(addr + len - 1) & PAGE_MASK))
 368                         goto out_copy;
 369                 p1 = vmalloc_to_page(addr);
 370                 if (!p1)
 371                         goto out_copy;
 372                 addr = page_address(p1) + ((size_t)addr & ~PAGE_MASK);
 373         }
 374
 375         dma_addr = dma_map_single(&info->pdev->dev, addr, len, dir);
 376         if (dma_mapping_error(&info->pdev->dev, dma_addr)) {
 377                 dev_err(&info->pdev->dev,
 378                         "Couldn't DMA map a %d byte buffer\n", len);
 379                 goto out_copy;
 380         }
 381
 382         if (is_write) {
 383             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 384                                                 info->phys_base, 0, 0);
 385             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 386                                                         dma_addr, 0, 0);
 387             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 388                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 389                                         OMAP24XX_DMA_GPMC, OMAP_DMA_DST_SYNC);
 390         } else {
 391             omap_set_dma_src_params(info->dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
 392                                                 info->phys_base, 0, 0);
 393             omap_set_dma_dest_params(info->dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
 394                                                         dma_addr, 0, 0);
 395             omap_set_dma_transfer_params(info->dma_ch, OMAP_DMA_DATA_TYPE_S32,
 396                                         0x10, buf_len, OMAP_DMA_SYNC_FRAME,
 397                                         OMAP24XX_DMA_GPMC, OMAP_DMA_SRC_SYNC);
 398         }
 399         /*  configure and start prefetch transfer */
 400         ret = gpmc_prefetch_enable(info->gpmc_cs,
 401                         PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write);
 402         if (ret)
 403                 /* PFPW engine is busy, use cpu copy method */
 404                 goto out_copy;
 405
 406         init_completion(&info->comp);
 407
 408         omap_start_dma(info->dma_ch);
 409
 410         /* setup and start DMA using dma_addr */
 411         wait_for_completion(&info->comp);
 412         tim = 0;
 413         limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 414         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 415                 cpu_relax();
 416
 417         /* disable and stop the PFPW engine */
 418         gpmc_prefetch_reset(info->gpmc_cs);
 419
 420         dma_unmap_single(&info->pdev->dev, dma_addr, len, dir);
 421         return 0;
 422
 423 out_copy:
 424         if (info->nand.options & NAND_BUSWIDTH_16)
 425                 is_write == 0 ? omap_read_buf16(mtd, (u_char *) addr, len)
 426                         : omap_write_buf16(mtd, (u_char *) addr, len);
 427         else
 428                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 429                         : omap_write_buf8(mtd, (u_char *) addr, len);
 430         return 0;
 431 }
 432
 433 /**
 434  * omap_read_buf_dma_pref - read data from NAND controller into buffer
 435  * @mtd: MTD device structure
 436  * @buf: buffer to store date
 437  * @len: number of bytes to read
 438  */
 439 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 440 {
 441         if (len <= mtd->oobsize)
 442                 omap_read_buf_pref(mtd, buf, len);
 443         else
 444                 /* start transfer in DMA mode */
 445                 omap_nand_dma_transfer(mtd, buf, len, 0x0);
 446 }
 447
 448 /**
 449  * omap_write_buf_dma_pref - write buffer to NAND controller
 450  * @mtd: MTD device structure
 451  * @buf: data buffer
 452  * @len: number of bytes to write
 453  */
 454 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 455                                         const u_char *buf, int len)
 456 {
 457         if (len <= mtd->oobsize)
 458                 omap_write_buf_pref(mtd, buf, len);
 459         else
 460                 /* start transfer in DMA mode */
 461                 omap_nand_dma_transfer(mtd, (u_char *) buf, len, 0x1);
 462 }
 463
 464 /*
 465  * omap_nand_irq - GMPC irq handler
 466  * @this_irq: gpmc irq number
 467  * @dev: omap_nand_info structure pointer is passed here
 468  */
 469 static irqreturn_t omap_nand_irq(int this_irq, void *dev)
 470 {
 471         struct omap_nand_info *info = (struct omap_nand_info *) dev;
 472         u32 bytes;
 473         u32 irq_stat;
 474
 475         irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 476         bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT);
 477         bytes = bytes  & 0xFFFC; /* io in multiple of 4 bytes */
 478         if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
 479                 if (irq_stat & 0x2)
 480                         goto done;
 481
 482                 if (info->buf_len && (info->buf_len < bytes))
 483                         bytes = info->buf_len;
 484                 else if (!info->buf_len)
 485                         bytes = 0;
 486                 iowrite32_rep(info->nand.IO_ADDR_W,
 487                                                 (u32 *)info->buf, bytes >> 2);
 488                 info->buf = info->buf + bytes;
 489                 info->buf_len -= bytes;
 490
 491         } else {
 492                 ioread32_rep(info->nand.IO_ADDR_R,
 493                                                 (u32 *)info->buf, bytes >> 2);
 494                 info->buf = info->buf + bytes;
 495
 496                 if (irq_stat & 0x2)
 497                         goto done;
 498         }
 499         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 500
 501         return IRQ_HANDLED;
 502
 503 done:
 504         complete(&info->comp);
 505         /* disable irq */
 506         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
 507
 508         /* clear status */
 509         gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
 510
 511         return IRQ_HANDLED;
 512 }
 513
 514 /*
 515  * omap_read_buf_irq_pref - read data from NAND controller into buffer
 516  * @mtd: MTD device structure
 517  * @buf: buffer to store date
 518  * @len: number of bytes to read
 519  */
 520 static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
 521 {
 522         struct omap_nand_info *info = container_of(mtd,
 523                                                 struct omap_nand_info, mtd);
 524         int ret = 0;
 525
 526         if (len <= mtd->oobsize) {
 527                 omap_read_buf_pref(mtd, buf, len);
 528                 return;
 529         }
 530
 531         info->iomode = OMAP_NAND_IO_READ;
 532         info->buf = buf;
 533         init_completion(&info->comp);
 534
 535         /*  configure and start prefetch transfer */
 536         ret = gpmc_prefetch_enable(info->gpmc_cs,
 537                         PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0);
 538         if (ret)
 539                 /* PFPW engine is busy, use cpu copy method */
 540                 goto out_copy;
 541
 542         info->buf_len = len;
 543         /* enable irq */
 544         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 545                 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 546
 547         /* waiting for read to complete */
 548         wait_for_completion(&info->comp);
 549
 550         /* disable and stop the PFPW engine */
 551         gpmc_prefetch_reset(info->gpmc_cs);
 552         return;
 553
 554 out_copy:
 555         if (info->nand.options & NAND_BUSWIDTH_16)
 556                 omap_read_buf16(mtd, buf, len);
 557         else
 558                 omap_read_buf8(mtd, buf, len);
 559 }
 560
 561 /*
 562  * omap_write_buf_irq_pref - write buffer to NAND controller
 563  * @mtd: MTD device structure
 564  * @buf: data buffer
 565  * @len: number of bytes to write
 566  */
 567 static void omap_write_buf_irq_pref(struct mtd_info *mtd,
 568                                         const u_char *buf, int len)
 569 {
 570         struct omap_nand_info *info = container_of(mtd,
 571                                                 struct omap_nand_info, mtd);
 572         int ret = 0;
 573         unsigned long tim, limit;
 574
 575         if (len <= mtd->oobsize) {
 576                 omap_write_buf_pref(mtd, buf, len);
 577                 return;
 578         }
 579
 580         info->iomode = OMAP_NAND_IO_WRITE;
 581         info->buf = (u_char *) buf;
 582         init_completion(&info->comp);
 583
 584         /* configure and start prefetch transfer : size=24 */
 585         ret = gpmc_prefetch_enable(info->gpmc_cs,
 586                         (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1);
 587         if (ret)
 588                 /* PFPW engine is busy, use cpu copy method */
 589                 goto out_copy;
 590
 591         info->buf_len = len;
 592         /* enable irq */
 593         gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ,
 594                         (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT));
 595
 596         /* waiting for write to complete */
 597         wait_for_completion(&info->comp);
 598         /* wait for data to flushed-out before reset the prefetch */
 599         tim = 0;
 600         limit = (loops_per_jiffy *  msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
 601         while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit))
 602                 cpu_relax();
 603
 604         /* disable and stop the PFPW engine */
 605         gpmc_prefetch_reset(info->gpmc_cs);
 606         return;
 607
 608 out_copy:
 609         if (info->nand.options & NAND_BUSWIDTH_16)
 610                 omap_write_buf16(mtd, buf, len);
 611         else
 612                 omap_write_buf8(mtd, buf, len);
 613 }
 614
 615 /**
 616  * omap_verify_buf - Verify chip data against buffer
 617  * @mtd: MTD device structure
 618  * @buf: buffer containing the data to compare
 619  * @len: number of bytes to compare
 620  */
 621 static int omap_verify_buf(struct mtd_info *mtd, const u_char * buf, int len)
 622 {
 623         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 624                                                         mtd);
 625         u16 *p = (u16 *) buf;
 626
 627         len >>= 1;
 628         while (len--) {
 629                 if (*p++ != cpu_to_le16(readw(info->nand.IO_ADDR_R)))
 630                         return -EFAULT;
 631         }
 632
 633         return 0;
 634 }
 635
 636 /**
 637  * gen_true_ecc - This function will generate true ECC value
 638  * @ecc_buf: buffer to store ecc code
 639  *
 640  * This generated true ECC value can be used when correcting
 641  * data read from NAND flash memory core
 642  */
 643 static void gen_true_ecc(u8 *ecc_buf)
 644 {
 645         u32 tmp = ecc_buf[0] | (ecc_buf[1] << 16) |
 646                 ((ecc_buf[2] & 0xF0) << 20) | ((ecc_buf[2] & 0x0F) << 8);
 647
 648         ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) |
 649                         P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
 650         ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) |
 651                         P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
 652         ecc_buf[2] = ~(P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) |
 653                         P1e(tmp) | P2048o(tmp) | P2048e(tmp));
 654 }
 655
 656 /**
 657  * omap_compare_ecc - Detect (2 bits) and correct (1 bit) error in data
 658  * @ecc_data1:  ecc code from nand spare area
 659  * @ecc_data2:  ecc code from hardware register obtained from hardware ecc
 660  * @page_data:  page data
 661  *
 662  * This function compares two ECC's and indicates if there is an error.
 663  * If the error can be corrected it will be corrected to the buffer.
 664  * If there is no error, %0 is returned. If there is an error but it
 665  * was corrected, %1 is returned. Otherwise, %-1 is returned.
 666  */
 667 static int omap_compare_ecc(u8 *ecc_data1,      /* read from NAND memory */
 668                             u8 *ecc_data2,      /* read from register */
 669                             u8 *page_data)
 670 {
 671         uint    i;
 672         u8      tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
 673         u8      comp0_bit[8], comp1_bit[8], comp2_bit[8];
 674         u8      ecc_bit[24];
 675         u8      ecc_sum = 0;
 676         u8      find_bit = 0;
 677         uint    find_byte = 0;
 678         int     isEccFF;
 679
 680         isEccFF = ((*(u32 *)ecc_data1 & 0xFFFFFF) == 0xFFFFFF);
 681
 682         gen_true_ecc(ecc_data1);
 683         gen_true_ecc(ecc_data2);
 684
 685         for (i = 0; i <= 2; i++) {
 686                 *(ecc_data1 + i) = ~(*(ecc_data1 + i));
 687                 *(ecc_data2 + i) = ~(*(ecc_data2 + i));
 688         }
 689
 690         for (i = 0; i < 8; i++) {
 691                 tmp0_bit[i]     = *ecc_data1 % 2;
 692                 *ecc_data1      = *ecc_data1 / 2;
 693         }
 694
 695         for (i = 0; i < 8; i++) {
 696                 tmp1_bit[i]      = *(ecc_data1 + 1) % 2;
 697                 *(ecc_data1 + 1) = *(ecc_data1 + 1) / 2;
 698         }
 699
 700         for (i = 0; i < 8; i++) {
 701                 tmp2_bit[i]      = *(ecc_data1 + 2) % 2;
 702                 *(ecc_data1 + 2) = *(ecc_data1 + 2) / 2;
 703         }
 704
 705         for (i = 0; i < 8; i++) {
 706                 comp0_bit[i]     = *ecc_data2 % 2;
 707                 *ecc_data2       = *ecc_data2 / 2;
 708         }
 709
 710         for (i = 0; i < 8; i++) {
 711                 comp1_bit[i]     = *(ecc_data2 + 1) % 2;
 712                 *(ecc_data2 + 1) = *(ecc_data2 + 1) / 2;
 713         }
 714
 715         for (i = 0; i < 8; i++) {
 716                 comp2_bit[i]     = *(ecc_data2 + 2) % 2;
 717                 *(ecc_data2 + 2) = *(ecc_data2 + 2) / 2;
 718         }
 719
 720         for (i = 0; i < 6; i++)
 721                 ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
 722
 723         for (i = 0; i < 8; i++)
 724                 ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
 725
 726         for (i = 0; i < 8; i++)
 727                 ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
 728
 729         ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
 730         ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
 731
 732         for (i = 0; i < 24; i++)
 733                 ecc_sum += ecc_bit[i];
 734
 735         switch (ecc_sum) {
 736         case 0:
 737                 /* Not reached because this function is not called if
 738                  *  ECC values are equal
 739                  */
 740                 return 0;
 741
 742         case 1:
 743                 /* Uncorrectable error */
 744                 pr_debug("ECC UNCORRECTED_ERROR 1\n");
 745                 return -1;
 746
 747         case 11:
 748                 /* UN-Correctable error */
 749                 pr_debug("ECC UNCORRECTED_ERROR B\n");
 750                 return -1;
 751
 752         case 12:
 753                 /* Correctable error */
 754                 find_byte = (ecc_bit[23] << 8) +
 755                             (ecc_bit[21] << 7) +
 756                             (ecc_bit[19] << 6) +
 757                             (ecc_bit[17] << 5) +
 758                             (ecc_bit[15] << 4) +
 759                             (ecc_bit[13] << 3) +
 760                             (ecc_bit[11] << 2) +
 761                             (ecc_bit[9]  << 1) +
 762                             ecc_bit[7];
 763
 764                 find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
 765
 766                 pr_debug("Correcting single bit ECC error at offset: "
 767                                 "%d, bit: %d\n", find_byte, find_bit);
 768
 769                 page_data[find_byte] ^= (1 << find_bit);
 770
 771                 return 1;
 772         default:
 773                 if (isEccFF) {
 774                         if (ecc_data2[0] == 0 &&
 775                             ecc_data2[1] == 0 &&
 776                             ecc_data2[2] == 0)
 777                                 return 0;
 778                 }
 779                 pr_debug("UNCORRECTED_ERROR default\n");
 780                 return -1;
 781         }
 782 }
 783
 784 /**
 785  * omap_correct_data - Compares the ECC read with HW generated ECC
 786  * @mtd: MTD device structure
 787  * @dat: page data
 788  * @read_ecc: ecc read from nand flash
 789  * @calc_ecc: ecc read from HW ECC registers
 790  *
 791  * Compares the ecc read from nand spare area with ECC registers values
 792  * and if ECC's mismatched, it will call 'omap_compare_ecc' for error
 793  * detection and correction. If there are no errors, %0 is returned. If
 794  * there were errors and all of the errors were corrected, the number of
 795  * corrected errors is returned. If uncorrectable errors exist, %-1 is
 796  * returned.
 797  */
 798 static int omap_correct_data(struct mtd_info *mtd, u_char *dat,
 799                                 u_char *read_ecc, u_char *calc_ecc)
 800 {
 801         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 802                                                         mtd);
 803         int blockCnt = 0, i = 0, ret = 0;
 804         int stat = 0;
 805
 806         /* Ex NAND_ECC_HW12_2048 */
 807         if ((info->nand.ecc.mode == NAND_ECC_HW) &&
 808                         (info->nand.ecc.size  == 2048))
 809                 blockCnt = 4;
 810         else
 811                 blockCnt = 1;
 812
 813         for (i = 0; i < blockCnt; i++) {
 814                 if (memcmp(read_ecc, calc_ecc, 3) != 0) {
 815                         ret = omap_compare_ecc(read_ecc, calc_ecc, dat);
 816                         if (ret < 0)
 817                                 return ret;
 818                         /* keep track of the number of corrected errors */
 819                         stat += ret;
 820                 }
 821                 read_ecc += 3;
 822                 calc_ecc += 3;
 823                 dat      += 512;
 824         }
 825         return stat;
 826 }
 827
 828 /**
 829  * omap_calcuate_ecc - Generate non-inverted ECC bytes.
 830  * @mtd: MTD device structure
 831  * @dat: The pointer to data on which ecc is computed
 832  * @ecc_code: The ecc_code buffer
 833  *
 834  * Using noninverted ECC can be considered ugly since writing a blank
 835  * page ie. padding will clear the ECC bytes. This is no problem as long
 836  * nobody is trying to write data on the seemingly unused page. Reading
 837  * an erased page will produce an ECC mismatch between generated and read
 838  * ECC bytes that has to be dealt with separately.
 839  */
 840 static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 841                                 u_char *ecc_code)
 842 {
 843         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 844                                                         mtd);
 845         return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code);
 846 }
 847
 848 /**
 849  * omap_enable_hwecc - This function enables the hardware ecc functionality
 850  * @mtd: MTD device structure
 851  * @mode: Read/Write mode
 852  */
 853 static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
 854 {
 855         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 856                                                         mtd);
 857         struct nand_chip *chip = mtd->priv;
 858         unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
 859
 860         gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size);
 861 }
 862
 863 /**
 864  * omap_wait - wait until the command is done
 865  * @mtd: MTD device structure
 866  * @chip: NAND Chip structure
 867  *
 868  * Wait function is called during Program and erase operations and
 869  * the way it is called from MTD layer, we should wait till the NAND
 870  * chip is ready after the programming/erase operation has completed.
 871  *
 872  * Erase can take up to 400ms and program up to 20ms according to
 873  * general NAND and SmartMedia specs
 874  */
 875 static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 876 {
 877         struct nand_chip *this = mtd->priv;
 878         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 879                                                         mtd);
 880         unsigned long timeo = jiffies;
 881         int status = NAND_STATUS_FAIL, state = this->state;
 882
 883         if (state == FL_ERASING)
 884                 timeo += (HZ * 400) / 1000;
 885         else
 886                 timeo += (HZ * 20) / 1000;
 887
 888         gpmc_nand_write(info->gpmc_cs,
 889                         GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
 890         while (time_before(jiffies, timeo)) {
 891                 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
 892                 if (status & NAND_STATUS_READY)
 893                         break;
 894                 cond_resched();
 895         }
 896         return status;
 897 }
 898
 899 /**
 900  * omap_dev_ready - calls the platform specific dev_ready function
 901  * @mtd: MTD device structure
 902  */
 903 static int omap_dev_ready(struct mtd_info *mtd)
 904 {
 905         unsigned int val = 0;
 906         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 907                                                         mtd);
 908
 909         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 910         if ((val & 0x100) == 0x100) {
 911                 /* Clear IRQ Interrupt */
 912                 val |= 0x100;
 913                 val &= ~(0x0);
 914                 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
 915         } else {
 916                 unsigned int cnt = 0;
 917                 while (cnt++ < 0x1FF) {
 918                         if  ((val & 0x100) == 0x100)
 919                                 return 0;
 920                         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 921                 }
 922         }
 923
 924         return 1;
 925 }
 926
 927 static int __devinit omap_nand_probe(struct platform_device *pdev)
 928 {
 929         struct omap_nand_info           *info;
 930         struct omap_nand_platform_data  *pdata;
 931         int                             err;
 932         int                             i, offset;
 933
 934         pdata = pdev->dev.platform_data;
 935         if (pdata == NULL) {
 936                 dev_err(&pdev->dev, "platform data missing\n");
 937                 return -ENODEV;
 938         }
 939
 940         info = kzalloc(sizeof(struct omap_nand_info), GFP_KERNEL);
 941         if (!info)
 942                 return -ENOMEM;
 943
 944         platform_set_drvdata(pdev, info);
 945
 946         spin_lock_init(&info->controller.lock);
 947         init_waitqueue_head(&info->controller.wq);
 948
 949         info->pdev = pdev;
 950
 951         info->gpmc_cs           = pdata->cs;
 952         info->phys_base         = pdata->phys_base;
 953
 954         info->mtd.priv          = &info->nand;
 955         info->mtd.name          = dev_name(&pdev->dev);
 956         info->mtd.owner         = THIS_MODULE;
 957
 958         info->nand.options      = pdata->devsize;
 959         info->nand.options      |= NAND_SKIP_BBTSCAN;
 960
 961         /* NAND write protect off */
 962         gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0);
 963
 964         if (!request_mem_region(info->phys_base, NAND_IO_SIZE,
 965                                 pdev->dev.driver->name)) {
 966                 err = -EBUSY;
 967                 goto out_free_info;
 968         }
 969
 970         info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE);
 971         if (!info->nand.IO_ADDR_R) {
 972                 err = -ENOMEM;
 973                 goto out_release_mem_region;
 974         }
 975
 976         info->nand.controller = &info->controller;
 977
 978         info->nand.IO_ADDR_W = info->nand.IO_ADDR_R;
 979         info->nand.cmd_ctrl  = omap_hwcontrol;
 980
 981         /*
 982          * If RDY/BSY line is connected to OMAP then use the omap ready
 983          * funcrtion and the generic nand_wait function which reads the status
 984          * register after monitoring the RDY/BSY line.Otherwise use a standard
 985          * chip delay which is slightly more than tR (AC Timing) of the NAND
 986          * device and read status register until you get a failure or success
 987          */
 988         if (pdata->dev_ready) {
 989                 info->nand.dev_ready = omap_dev_ready;
 990                 info->nand.chip_delay = 0;
 991         } else {
 992                 info->nand.waitfunc = omap_wait;
 993                 info->nand.chip_delay = 50;
 994         }
 995
 996         switch (pdata->xfer_type) {
 997         case NAND_OMAP_PREFETCH_POLLED:
 998                 info->nand.read_buf   = omap_read_buf_pref;
 999                 info->nand.write_buf  = omap_write_buf_pref;
1000                 break;
1001
1002         case NAND_OMAP_POLLED:
1003                 if (info->nand.options & NAND_BUSWIDTH_16) {
1004                         info->nand.read_buf   = omap_read_buf16;
1005                         info->nand.write_buf  = omap_write_buf16;
1006                 } else {
1007                         info->nand.read_buf   = omap_read_buf8;
1008                         info->nand.write_buf  = omap_write_buf8;
1009                 }
1010                 break;
1011
1012         case NAND_OMAP_PREFETCH_DMA:
1013                 err = omap_request_dma(OMAP24XX_DMA_GPMC, "NAND",
1014                                 omap_nand_dma_cb, &info->comp, &info->dma_ch);
1015                 if (err < 0) {
1016                         info->dma_ch = -1;
1017                         dev_err(&pdev->dev, "DMA request failed!\n");
1018                         goto out_release_mem_region;
1019                 } else {
1020                         omap_set_dma_dest_burst_mode(info->dma_ch,
1021                                         OMAP_DMA_DATA_BURST_16);
1022                         omap_set_dma_src_burst_mode(info->dma_ch,
1023                                         OMAP_DMA_DATA_BURST_16);
1024
1025                         info->nand.read_buf   = omap_read_buf_dma_pref;
1026                         info->nand.write_buf  = omap_write_buf_dma_pref;
1027                 }
1028                 break;
1029
1030         case NAND_OMAP_PREFETCH_IRQ:
1031                 err = request_irq(pdata->gpmc_irq,
1032                                 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info);
1033                 if (err) {
1034                         dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1035                                                         pdata->gpmc_irq, err);
1036                         goto out_release_mem_region;
1037                 } else {
1038                         info->gpmc_irq       = pdata->gpmc_irq;
1039                         info->nand.read_buf  = omap_read_buf_irq_pref;
1040                         info->nand.write_buf = omap_write_buf_irq_pref;
1041                 }
1042                 break;
1043
1044         default:
1045                 dev_err(&pdev->dev,
1046                         "xfer_type(%d) not supported!\n", pdata->xfer_type);
1047                 err = -EINVAL;
1048                 goto out_release_mem_region;
1049         }
1050
1051         info->nand.verify_buf = omap_verify_buf;
1052
1053         /* selsect the ecc type */
1054         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
1055                 info->nand.ecc.mode = NAND_ECC_SOFT;
1056         else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
1057                 (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
1058                 info->nand.ecc.bytes            = 3;
1059                 info->nand.ecc.size             = 512;
1060                 info->nand.ecc.calculate        = omap_calculate_ecc;
1061                 info->nand.ecc.hwctl            = omap_enable_hwecc;
1062                 info->nand.ecc.correct          = omap_correct_data;
1063                 info->nand.ecc.mode             = NAND_ECC_HW;
1064         }
1065
1066         /* DIP switches on some boards change between 8 and 16 bit
1067          * bus widths for flash.  Try the other width if the first try fails.
1068          */
1069         if (nand_scan_ident(&info->mtd, 1, NULL)) {
1070                 info->nand.options ^= NAND_BUSWIDTH_16;
1071                 if (nand_scan_ident(&info->mtd, 1, NULL)) {
1072                         err = -ENXIO;
1073                         goto out_release_mem_region;
1074                 }
1075         }
1076
1077         /* rom code layout */
1078         if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
1079
1080                 if (info->nand.options & NAND_BUSWIDTH_16)
1081                         offset = 2;
1082                 else {
1083                         offset = 1;
1084                         info->nand.badblock_pattern = &bb_descrip_flashbased;
1085                 }
1086                 omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
1087                 for (i = 0; i < omap_oobinfo.eccbytes; i++)
1088                         omap_oobinfo.eccpos[i] = i+offset;
1089
1090                 omap_oobinfo.oobfree->offset = offset + omap_oobinfo.eccbytes;
1091                 omap_oobinfo.oobfree->length = info->mtd.oobsize -
1092                                         (offset + omap_oobinfo.eccbytes);
1093
1094                 info->nand.ecc.layout = &omap_oobinfo;
1095         }
1096
1097         /* second phase scan */
1098         if (nand_scan_tail(&info->mtd)) {
1099                 err = -ENXIO;
1100                 goto out_release_mem_region;
1101         }
1102
1103         mtd_device_parse_register(&info->mtd, NULL, 0,
1104                         pdata->parts, pdata->nr_parts);
1105
1106         platform_set_drvdata(pdev, &info->mtd);
1107
1108         return 0;
1109
1110 out_release_mem_region:
1111         release_mem_region(info->phys_base, NAND_IO_SIZE);
1112 out_free_info:
1113         kfree(info);
1114
1115         return err;
1116 }
1117
1118 static int omap_nand_remove(struct platform_device *pdev)
1119 {
1120         struct mtd_info *mtd = platform_get_drvdata(pdev);
1121         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
1122                                                         mtd);
1123
1124         platform_set_drvdata(pdev, NULL);
1125         if (info->dma_ch != -1)
1126                 omap_free_dma(info->dma_ch);
1127
1128         if (info->gpmc_irq)
1129                 free_irq(info->gpmc_irq, info);
1130
1131         /* Release NAND device, its internal structures and partitions */
1132         nand_release(&info->mtd);
1133         iounmap(info->nand.IO_ADDR_R);
1134         kfree(&info->mtd);
1135         return 0;
1136 }
1137
1138 static struct platform_driver omap_nand_driver = {
1139         .probe          = omap_nand_probe,
1140         .remove         = omap_nand_remove,
1141         .driver         = {
1142                 .name   = DRIVER_NAME,
1143                 .owner  = THIS_MODULE,
1144         },
1145 };
1146
1147 static int __init omap_nand_init(void)
1148 {
1149         pr_info("%s driver initializing\n", DRIVER_NAME);
1150
1151         return platform_driver_register(&omap_nand_driver);
1152 }
1153
1154 static void __exit omap_nand_exit(void)
1155 {
1156         platform_driver_unregister(&omap_nand_driver);
1157 }
1158
1159 module_init(omap_nand_init);
1160 module_exit(omap_nand_exit);
1161
1162 MODULE_ALIAS("platform:" DRIVER_NAME);
1163 MODULE_LICENSE("GPL");
1164 MODULE_DESCRIPTION("Glue layer for NAND flash on TI OMAP boards");