drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33
  34 #include <asm/mach/flash.h>
  35 #include <mach/mxc_nand.h>
  36
  37 #define DRIVER_NAME "mxc_nand"
  38
  39 /* Addresses for NFC registers */
  40 #define NFC_BUF_SIZE            0xE00
  41 #define NFC_BUF_ADDR            0xE04
  42 #define NFC_FLASH_ADDR          0xE06
  43 #define NFC_FLASH_CMD           0xE08
  44 #define NFC_CONFIG              0xE0A
  45 #define NFC_ECC_STATUS_RESULT   0xE0C
  46 #define NFC_RSLTMAIN_AREA       0xE0E
  47 #define NFC_RSLTSPARE_AREA      0xE10
  48 #define NFC_WRPROT              0xE12
  49 #define NFC_UNLOCKSTART_BLKADDR 0xE14
  50 #define NFC_UNLOCKEND_BLKADDR   0xE16
  51 #define NFC_NF_WRPRST           0xE18
  52 #define NFC_CONFIG1             0xE1A
  53 #define NFC_CONFIG2             0xE1C
  54
  55 /* Addresses for NFC RAM BUFFER Main area 0 */
  56 #define MAIN_AREA0              0x000
  57 #define MAIN_AREA1              0x200
  58 #define MAIN_AREA2              0x400
  59 #define MAIN_AREA3              0x600
  60
  61 /* Addresses for NFC SPARE BUFFER Spare area 0 */
  62 #define SPARE_AREA0             0x800
  63 #define SPARE_AREA1             0x810
  64 #define SPARE_AREA2             0x820
  65 #define SPARE_AREA3             0x830
  66
  67 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
  68  * for Command operation */
  69 #define NFC_CMD            0x1
  70
  71 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
  72  * for Address operation */
  73 #define NFC_ADDR           0x2
  74
  75 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
  76  * for Input operation */
  77 #define NFC_INPUT          0x4
  78
  79 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
  80  * for Data Output operation */
  81 #define NFC_OUTPUT         0x8
  82
  83 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
  84  * for Read ID operation */
  85 #define NFC_ID             0x10
  86
  87 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
  88  * for Read Status operation */
  89 #define NFC_STATUS         0x20
  90
  91 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
  92  * Status operation */
  93 #define NFC_INT            0x8000
  94
  95 #define NFC_SP_EN           (1 << 2)
  96 #define NFC_ECC_EN          (1 << 3)
  97 #define NFC_INT_MSK         (1 << 4)
  98 #define NFC_BIG             (1 << 5)
  99 #define NFC_RST             (1 << 6)
 100 #define NFC_CE              (1 << 7)
 101 #define NFC_ONE_CYCLE       (1 << 8)
 102
 103 struct mxc_nand_host {
 104         struct mtd_info         mtd;
 105         struct nand_chip        nand;
 106         struct mtd_partition    *parts;
 107         struct device           *dev;
 108
 109         void __iomem            *regs;
 110         int                     spare_only;
 111         int                     status_request;
 112         int                     pagesize_2k;
 113         uint16_t                col_addr;
 114         struct clk              *clk;
 115         int                     clk_act;
 116         int                     irq;
 117
 118         wait_queue_head_t       irq_waitq;
 119 };
 120
 121 /* Define delays in microsec for NAND device operations */
 122 #define TROP_US_DELAY   2000
 123 /* Macros to get byte and bit positions of ECC */
 124 #define COLPOS(x)  ((x) >> 3)
 125 #define BITPOS(x) ((x) & 0xf)
 126
 127 /* Define single bit Error positions in Main & Spare area */
 128 #define MAIN_SINGLEBIT_ERROR 0x4
 129 #define SPARE_SINGLEBIT_ERROR 0x1
 130
 131 /* OOB placement block for use with hardware ecc generation */
 132 static struct nand_ecclayout nand_hw_eccoob_8 = {
 133         .eccbytes = 5,
 134         .eccpos = {6, 7, 8, 9, 10},
 135         .oobfree = {{0, 5}, {11, 5}, }
 136 };
 137
 138 static struct nand_ecclayout nand_hw_eccoob_16 = {
 139         .eccbytes = 5,
 140         .eccpos = {6, 7, 8, 9, 10},
 141         .oobfree = {{0, 6}, {12, 4}, }
 142 };
 143
 144 #ifdef CONFIG_MTD_PARTITIONS
 145 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
 146 #endif
 147
 148 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 149 {
 150         struct mxc_nand_host *host = dev_id;
 151
 152         uint16_t tmp;
 153
 154         tmp = readw(host->regs + NFC_CONFIG1);
 155         tmp |= NFC_INT_MSK; /* Disable interrupt */
 156         writew(tmp, host->regs + NFC_CONFIG1);
 157
 158         wake_up(&host->irq_waitq);
 159
 160         return IRQ_HANDLED;
 161 }
 162
 163 /* This function polls the NANDFC to wait for the basic operation to
 164  * complete by checking the INT bit of config2 register.
 165  */
 166 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 167                                 uint16_t param, int useirq)
 168 {
 169         uint32_t tmp;
 170
 171         if (useirq) {
 172                 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
 173
 174                         tmp = readw(host->regs + NFC_CONFIG1);
 175                         tmp  &= ~NFC_INT_MSK;   /* Enable interrupt */
 176                         writew(tmp, host->regs + NFC_CONFIG1);
 177
 178                         wait_event(host->irq_waitq,
 179                                 readw(host->regs + NFC_CONFIG2) & NFC_INT);
 180
 181                         tmp = readw(host->regs + NFC_CONFIG2);
 182                         tmp  &= ~NFC_INT;
 183                         writew(tmp, host->regs + NFC_CONFIG2);
 184                 }
 185         } else {
 186                 while (max_retries-- > 0) {
 187                         if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
 188                                 tmp = readw(host->regs + NFC_CONFIG2);
 189                                 tmp  &= ~NFC_INT;
 190                                 writew(tmp, host->regs + NFC_CONFIG2);
 191                                 break;
 192                         }
 193                         udelay(1);
 194                 }
 195                 if (max_retries <= 0)
 196                         DEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
 197                               __func__, param);
 198         }
 199 }
 200
 201 /* This function issues the specified command to the NAND device and
 202  * waits for completion. */
 203 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 204 {
 205         DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 206
 207         writew(cmd, host->regs + NFC_FLASH_CMD);
 208         writew(NFC_CMD, host->regs + NFC_CONFIG2);
 209
 210         /* Wait for operation to complete */
 211         wait_op_done(host, TROP_US_DELAY, cmd, useirq);
 212 }
 213
 214 /* This function sends an address (or partial address) to the
 215  * NAND device. The address is used to select the source/destination for
 216  * a NAND command. */
 217 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
 218 {
 219         DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
 220
 221         writew(addr, host->regs + NFC_FLASH_ADDR);
 222         writew(NFC_ADDR, host->regs + NFC_CONFIG2);
 223
 224         /* Wait for operation to complete */
 225         wait_op_done(host, TROP_US_DELAY, addr, islast);
 226 }
 227
 228 /* This function requests the NANDFC to initate the transfer
 229  * of data currently in the NANDFC RAM buffer to the NAND device. */
 230 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 231                         int spare_only)
 232 {
 233         DEBUG(MTD_DEBUG_LEVEL3, "send_prog_page (%d)\n", spare_only);
 234
 235         /* NANDFC buffer 0 is used for page read/write */
 236         writew(buf_id, host->regs + NFC_BUF_ADDR);
 237
 238         /* Configure spare or page+spare access */
 239         if (!host->pagesize_2k) {
 240                 uint16_t config1 = readw(host->regs + NFC_CONFIG1);
 241                 if (spare_only)
 242                         config1 |= NFC_SP_EN;
 243                 else
 244                         config1 &= ~(NFC_SP_EN);
 245                 writew(config1, host->regs + NFC_CONFIG1);
 246         }
 247
 248         writew(NFC_INPUT, host->regs + NFC_CONFIG2);
 249
 250         /* Wait for operation to complete */
 251         wait_op_done(host, TROP_US_DELAY, spare_only, true);
 252 }
 253
 254 /* Requests NANDFC to initated the transfer of data from the
 255  * NAND device into in the NANDFC ram buffer. */
 256 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 257                 int spare_only)
 258 {
 259         DEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
 260
 261         /* NANDFC buffer 0 is used for page read/write */
 262         writew(buf_id, host->regs + NFC_BUF_ADDR);
 263
 264         /* Configure spare or page+spare access */
 265         if (!host->pagesize_2k) {
 266                 uint32_t config1 = readw(host->regs + NFC_CONFIG1);
 267                 if (spare_only)
 268                         config1 |= NFC_SP_EN;
 269                 else
 270                         config1 &= ~NFC_SP_EN;
 271                 writew(config1, host->regs + NFC_CONFIG1);
 272         }
 273
 274         writew(NFC_OUTPUT, host->regs + NFC_CONFIG2);
 275
 276         /* Wait for operation to complete */
 277         wait_op_done(host, TROP_US_DELAY, spare_only, true);
 278 }
 279
 280 /* Request the NANDFC to perform a read of the NAND device ID. */
 281 static void send_read_id(struct mxc_nand_host *host)
 282 {
 283         struct nand_chip *this = &host->nand;
 284         uint16_t tmp;
 285
 286         /* NANDFC buffer 0 is used for device ID output */
 287         writew(0x0, host->regs + NFC_BUF_ADDR);
 288
 289         /* Read ID into main buffer */
 290         tmp = readw(host->regs + NFC_CONFIG1);
 291         tmp &= ~NFC_SP_EN;
 292         writew(tmp, host->regs + NFC_CONFIG1);
 293
 294         writew(NFC_ID, host->regs + NFC_CONFIG2);
 295
 296         /* Wait for operation to complete */
 297         wait_op_done(host, TROP_US_DELAY, 0, true);
 298
 299         if (this->options & NAND_BUSWIDTH_16) {
 300                 void __iomem *main_buf = host->regs + MAIN_AREA0;
 301                 /* compress the ID info */
 302                 writeb(readb(main_buf + 2), main_buf + 1);
 303                 writeb(readb(main_buf + 4), main_buf + 2);
 304                 writeb(readb(main_buf + 6), main_buf + 3);
 305                 writeb(readb(main_buf + 8), main_buf + 4);
 306                 writeb(readb(main_buf + 10), main_buf + 5);
 307         }
 308 }
 309
 310 /* This function requests the NANDFC to perform a read of the
 311  * NAND device status and returns the current status. */
 312 static uint16_t get_dev_status(struct mxc_nand_host *host)
 313 {
 314         void __iomem *main_buf = host->regs + MAIN_AREA1;
 315         uint32_t store;
 316         uint16_t ret, tmp;
 317         /* Issue status request to NAND device */
 318
 319         /* store the main area1 first word, later do recovery */
 320         store = readl(main_buf);
 321         /* NANDFC buffer 1 is used for device status to prevent
 322          * corruption of read/write buffer on status requests. */
 323         writew(1, host->regs + NFC_BUF_ADDR);
 324
 325         /* Read status into main buffer */
 326         tmp = readw(host->regs + NFC_CONFIG1);
 327         tmp &= ~NFC_SP_EN;
 328         writew(tmp, host->regs + NFC_CONFIG1);
 329
 330         writew(NFC_STATUS, host->regs + NFC_CONFIG2);
 331
 332         /* Wait for operation to complete */
 333         wait_op_done(host, TROP_US_DELAY, 0, true);
 334
 335         /* Status is placed in first word of main buffer */
 336         /* get status, then recovery area 1 data */
 337         ret = readw(main_buf);
 338         writel(store, main_buf);
 339
 340         return ret;
 341 }
 342
 343 /* This functions is used by upper layer to checks if device is ready */
 344 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 345 {
 346         /*
 347          * NFC handles R/B internally. Therefore, this function
 348          * always returns status as ready.
 349          */
 350         return 1;
 351 }
 352
 353 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 354 {
 355         /*
 356          * If HW ECC is enabled, we turn it on during init. There is
 357          * no need to enable again here.
 358          */
 359 }
 360
 361 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 362                                  u_char *read_ecc, u_char *calc_ecc)
 363 {
 364         struct nand_chip *nand_chip = mtd->priv;
 365         struct mxc_nand_host *host = nand_chip->priv;
 366
 367         /*
 368          * 1-Bit errors are automatically corrected in HW.  No need for
 369          * additional correction.  2-Bit errors cannot be corrected by
 370          * HW ECC, so we need to return failure
 371          */
 372         uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
 373
 374         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 375                 DEBUG(MTD_DEBUG_LEVEL0,
 376                       "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 377                 return -1;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 384                                   u_char *ecc_code)
 385 {
 386         return 0;
 387 }
 388
 389 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 390 {
 391         struct nand_chip *nand_chip = mtd->priv;
 392         struct mxc_nand_host *host = nand_chip->priv;
 393         uint8_t ret = 0;
 394         uint16_t col, rd_word;
 395         uint16_t __iomem *main_buf = host->regs + MAIN_AREA0;
 396         uint16_t __iomem *spare_buf = host->regs + SPARE_AREA0;
 397
 398         /* Check for status request */
 399         if (host->status_request)
 400                 return get_dev_status(host) & 0xFF;
 401
 402         /* Get column for 16-bit access */
 403         col = host->col_addr >> 1;
 404
 405         /* If we are accessing the spare region */
 406         if (host->spare_only)
 407                 rd_word = readw(&spare_buf[col]);
 408         else
 409                 rd_word = readw(&main_buf[col]);
 410
 411         /* Pick upper/lower byte of word from RAM buffer */
 412         if (host->col_addr & 0x1)
 413                 ret = (rd_word >> 8) & 0xFF;
 414         else
 415                 ret = rd_word & 0xFF;
 416
 417         /* Update saved column address */
 418         host->col_addr++;
 419
 420         return ret;
 421 }
 422
 423 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 424 {
 425         struct nand_chip *nand_chip = mtd->priv;
 426         struct mxc_nand_host *host = nand_chip->priv;
 427         uint16_t col, rd_word, ret;
 428         uint16_t __iomem *p;
 429
 430         DEBUG(MTD_DEBUG_LEVEL3,
 431               "mxc_nand_read_word(col = %d)\n", host->col_addr);
 432
 433         col = host->col_addr;
 434         /* Adjust saved column address */
 435         if (col < mtd->writesize && host->spare_only)
 436                 col += mtd->writesize;
 437
 438         if (col < mtd->writesize)
 439                 p = (host->regs + MAIN_AREA0) + (col >> 1);
 440         else
 441                 p = (host->regs + SPARE_AREA0) + ((col - mtd->writesize) >> 1);
 442
 443         if (col & 1) {
 444                 rd_word = readw(p);
 445                 ret = (rd_word >> 8) & 0xff;
 446                 rd_word = readw(&p[1]);
 447                 ret |= (rd_word << 8) & 0xff00;
 448
 449         } else
 450                 ret = readw(p);
 451
 452         /* Update saved column address */
 453         host->col_addr = col + 2;
 454
 455         return ret;
 456 }
 457
 458 /* Write data of length len to buffer buf. The data to be
 459  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 460  * Operation by the NFC, the data is written to NAND Flash */
 461 static void mxc_nand_write_buf(struct mtd_info *mtd,
 462                                 const u_char *buf, int len)
 463 {
 464         struct nand_chip *nand_chip = mtd->priv;
 465         struct mxc_nand_host *host = nand_chip->priv;
 466         int n, col, i = 0;
 467
 468         DEBUG(MTD_DEBUG_LEVEL3,
 469               "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 470               len);
 471
 472         col = host->col_addr;
 473
 474         /* Adjust saved column address */
 475         if (col < mtd->writesize && host->spare_only)
 476                 col += mtd->writesize;
 477
 478         n = mtd->writesize + mtd->oobsize - col;
 479         n = min(len, n);
 480
 481         DEBUG(MTD_DEBUG_LEVEL3,
 482               "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 483
 484         while (n) {
 485                 void __iomem *p;
 486
 487                 if (col < mtd->writesize)
 488                         p = host->regs + MAIN_AREA0 + (col & ~3);
 489                 else
 490                         p = host->regs + SPARE_AREA0 -
 491                                                 mtd->writesize + (col & ~3);
 492
 493                 DEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
 494                       __LINE__, p);
 495
 496                 if (((col | (int)&buf[i]) & 3) || n < 16) {
 497                         uint32_t data = 0;
 498
 499                         if (col & 3 || n < 4)
 500                                 data = readl(p);
 501
 502                         switch (col & 3) {
 503                         case 0:
 504                                 if (n) {
 505                                         data = (data & 0xffffff00) |
 506                                             (buf[i++] << 0);
 507                                         n--;
 508                                         col++;
 509                                 }
 510                         case 1:
 511                                 if (n) {
 512                                         data = (data & 0xffff00ff) |
 513                                             (buf[i++] << 8);
 514                                         n--;
 515                                         col++;
 516                                 }
 517                         case 2:
 518                                 if (n) {
 519                                         data = (data & 0xff00ffff) |
 520                                             (buf[i++] << 16);
 521                                         n--;
 522                                         col++;
 523                                 }
 524                         case 3:
 525                                 if (n) {
 526                                         data = (data & 0x00ffffff) |
 527                                             (buf[i++] << 24);
 528                                         n--;
 529                                         col++;
 530                                 }
 531                         }
 532
 533                         writel(data, p);
 534                 } else {
 535                         int m = mtd->writesize - col;
 536
 537                         if (col >= mtd->writesize)
 538                                 m += mtd->oobsize;
 539
 540                         m = min(n, m) & ~3;
 541
 542                         DEBUG(MTD_DEBUG_LEVEL3,
 543                               "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 544                               __func__,  __LINE__, n, m, i, col);
 545
 546                         memcpy(p, &buf[i], m);
 547                         col += m;
 548                         i += m;
 549                         n -= m;
 550                 }
 551         }
 552         /* Update saved column address */
 553         host->col_addr = col;
 554 }
 555
 556 /* Read the data buffer from the NAND Flash. To read the data from NAND
 557  * Flash first the data output cycle is initiated by the NFC, which copies
 558  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 559  */
 560 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 561 {
 562         struct nand_chip *nand_chip = mtd->priv;
 563         struct mxc_nand_host *host = nand_chip->priv;
 564         int n, col, i = 0;
 565
 566         DEBUG(MTD_DEBUG_LEVEL3,
 567               "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
 568
 569         col = host->col_addr;
 570
 571         /* Adjust saved column address */
 572         if (col < mtd->writesize && host->spare_only)
 573                 col += mtd->writesize;
 574
 575         n = mtd->writesize + mtd->oobsize - col;
 576         n = min(len, n);
 577
 578         while (n) {
 579                 void __iomem *p;
 580
 581                 if (col < mtd->writesize)
 582                         p = host->regs + MAIN_AREA0 + (col & ~3);
 583                 else
 584                         p = host->regs + SPARE_AREA0 -
 585                                         mtd->writesize + (col & ~3);
 586
 587                 if (((col | (int)&buf[i]) & 3) || n < 16) {
 588                         uint32_t data;
 589
 590                         data = readl(p);
 591                         switch (col & 3) {
 592                         case 0:
 593                                 if (n) {
 594                                         buf[i++] = (uint8_t) (data);
 595                                         n--;
 596                                         col++;
 597                                 }
 598                         case 1:
 599                                 if (n) {
 600                                         buf[i++] = (uint8_t) (data >> 8);
 601                                         n--;
 602                                         col++;
 603                                 }
 604                         case 2:
 605                                 if (n) {
 606                                         buf[i++] = (uint8_t) (data >> 16);
 607                                         n--;
 608                                         col++;
 609                                 }
 610                         case 3:
 611                                 if (n) {
 612                                         buf[i++] = (uint8_t) (data >> 24);
 613                                         n--;
 614                                         col++;
 615                                 }
 616                         }
 617                 } else {
 618                         int m = mtd->writesize - col;
 619
 620                         if (col >= mtd->writesize)
 621                                 m += mtd->oobsize;
 622
 623                         m = min(n, m) & ~3;
 624                         memcpy(&buf[i], p, m);
 625                         col += m;
 626                         i += m;
 627                         n -= m;
 628                 }
 629         }
 630         /* Update saved column address */
 631         host->col_addr = col;
 632
 633 }
 634
 635 /* Used by the upper layer to verify the data in NAND Flash
 636  * with the data in the buf. */
 637 static int mxc_nand_verify_buf(struct mtd_info *mtd,
 638                                 const u_char *buf, int len)
 639 {
 640         return -EFAULT;
 641 }
 642
 643 /* This function is used by upper layer for select and
 644  * deselect of the NAND chip */
 645 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 646 {
 647         struct nand_chip *nand_chip = mtd->priv;
 648         struct mxc_nand_host *host = nand_chip->priv;
 649
 650 #ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
 651         if (chip > 0) {
 652                 DEBUG(MTD_DEBUG_LEVEL0,
 653                       "ERROR:  Illegal chip select (chip = %d)\n", chip);
 654                 return;
 655         }
 656
 657         if (chip == -1) {
 658                 writew(readw(host->regs + NFC_CONFIG1) & ~NFC_CE,
 659                                 host->regs + NFC_CONFIG1);
 660                 return;
 661         }
 662
 663         writew(readw(host->regs + NFC_CONFIG1) | NFC_CE,
 664                         host->regs + NFC_CONFIG1);
 665 #endif
 666
 667         switch (chip) {
 668         case -1:
 669                 /* Disable the NFC clock */
 670                 if (host->clk_act) {
 671                         clk_disable(host->clk);
 672                         host->clk_act = 0;
 673                 }
 674                 break;
 675         case 0:
 676                 /* Enable the NFC clock */
 677                 if (!host->clk_act) {
 678                         clk_enable(host->clk);
 679                         host->clk_act = 1;
 680                 }
 681                 break;
 682
 683         default:
 684                 break;
 685         }
 686 }
 687
 688 /* Used by the upper layer to write command to NAND Flash for
 689  * different operations to be carried out on NAND Flash */
 690 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 691                                 int column, int page_addr)
 692 {
 693         struct nand_chip *nand_chip = mtd->priv;
 694         struct mxc_nand_host *host = nand_chip->priv;
 695         int useirq = true;
 696
 697         DEBUG(MTD_DEBUG_LEVEL3,
 698               "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 699               command, column, page_addr);
 700
 701         /* Reset command state information */
 702         host->status_request = false;
 703
 704         /* Command pre-processing step */
 705         switch (command) {
 706
 707         case NAND_CMD_STATUS:
 708                 host->col_addr = 0;
 709                 host->status_request = true;
 710                 break;
 711
 712         case NAND_CMD_READ0:
 713                 host->col_addr = column;
 714                 host->spare_only = false;
 715                 useirq = false;
 716                 break;
 717
 718         case NAND_CMD_READOOB:
 719                 host->col_addr = column;
 720                 host->spare_only = true;
 721                 useirq = false;
 722                 if (host->pagesize_2k)
 723                         command = NAND_CMD_READ0; /* only READ0 is valid */
 724                 break;
 725
 726         case NAND_CMD_SEQIN:
 727                 if (column >= mtd->writesize) {
 728                         /*
 729                          * FIXME: before send SEQIN command for write OOB,
 730                          * We must read one page out.
 731                          * For K9F1GXX has no READ1 command to set current HW
 732                          * pointer to spare area, we must write the whole page
 733                          * including OOB together.
 734                          */
 735                         if (host->pagesize_2k)
 736                                 /* call ourself to read a page */
 737                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
 738                                                 page_addr);
 739
 740                         host->col_addr = column - mtd->writesize;
 741                         host->spare_only = true;
 742
 743                         /* Set program pointer to spare region */
 744                         if (!host->pagesize_2k)
 745                                 send_cmd(host, NAND_CMD_READOOB, false);
 746                 } else {
 747                         host->spare_only = false;
 748                         host->col_addr = column;
 749
 750                         /* Set program pointer to page start */
 751                         if (!host->pagesize_2k)
 752                                 send_cmd(host, NAND_CMD_READ0, false);
 753                 }
 754                 useirq = false;
 755                 break;
 756
 757         case NAND_CMD_PAGEPROG:
 758                 send_prog_page(host, 0, host->spare_only);
 759
 760                 if (host->pagesize_2k) {
 761                         /* data in 4 areas datas */
 762                         send_prog_page(host, 1, host->spare_only);
 763                         send_prog_page(host, 2, host->spare_only);
 764                         send_prog_page(host, 3, host->spare_only);
 765                 }
 766
 767                 break;
 768
 769         case NAND_CMD_ERASE1:
 770                 useirq = false;
 771                 break;
 772         }
 773
 774         /* Write out the command to the device. */
 775         send_cmd(host, command, useirq);
 776
 777         /* Write out column address, if necessary */
 778         if (column != -1) {
 779                 /*
 780                  * MXC NANDFC can only perform full page+spare or
 781                  * spare-only read/write.  When the upper layers
 782                  * layers perform a read/write buf operation,
 783                  * we will used the saved column adress to index into
 784                  * the full page.
 785                  */
 786                 send_addr(host, 0, page_addr == -1);
 787                 if (host->pagesize_2k)
 788                         /* another col addr cycle for 2k page */
 789                         send_addr(host, 0, false);
 790         }
 791
 792         /* Write out page address, if necessary */
 793         if (page_addr != -1) {
 794                 /* paddr_0 - p_addr_7 */
 795                 send_addr(host, (page_addr & 0xff), false);
 796
 797                 if (host->pagesize_2k) {
 798                         send_addr(host, (page_addr >> 8) & 0xFF, false);
 799                         if (mtd->size >= 0x40000000)
 800                                 send_addr(host, (page_addr >> 16) & 0xff, true);
 801                 } else {
 802                         /* One more address cycle for higher density devices */
 803                         if (mtd->size >= 0x4000000) {
 804                                 /* paddr_8 - paddr_15 */
 805                                 send_addr(host, (page_addr >> 8) & 0xff, false);
 806                                 send_addr(host, (page_addr >> 16) & 0xff, true);
 807                         } else
 808                                 /* paddr_8 - paddr_15 */
 809                                 send_addr(host, (page_addr >> 8) & 0xff, true);
 810                 }
 811         }
 812
 813         /* Command post-processing step */
 814         switch (command) {
 815
 816         case NAND_CMD_RESET:
 817                 break;
 818
 819         case NAND_CMD_READOOB:
 820         case NAND_CMD_READ0:
 821                 if (host->pagesize_2k) {
 822                         /* send read confirm command */
 823                         send_cmd(host, NAND_CMD_READSTART, true);
 824                         /* read for each AREA */
 825                         send_read_page(host, 0, host->spare_only);
 826                         send_read_page(host, 1, host->spare_only);
 827                         send_read_page(host, 2, host->spare_only);
 828                         send_read_page(host, 3, host->spare_only);
 829                 } else
 830                         send_read_page(host, 0, host->spare_only);
 831                 break;
 832
 833         case NAND_CMD_READID:
 834                 host->col_addr = 0;
 835                 send_read_id(host);
 836                 break;
 837
 838         case NAND_CMD_PAGEPROG:
 839                 break;
 840
 841         case NAND_CMD_STATUS:
 842                 break;
 843
 844         case NAND_CMD_ERASE2:
 845                 break;
 846         }
 847 }
 848
 849 static int __init mxcnd_probe(struct platform_device *pdev)
 850 {
 851         struct nand_chip *this;
 852         struct mtd_info *mtd;
 853         struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
 854         struct mxc_nand_host *host;
 855         struct resource *res;
 856         uint16_t tmp;
 857         int err = 0, nr_parts = 0;
 858
 859         /* Allocate memory for MTD device structure and private data */
 860         host = kzalloc(sizeof(struct mxc_nand_host), GFP_KERNEL);
 861         if (!host)
 862                 return -ENOMEM;
 863
 864         host->dev = &pdev->dev;
 865         /* structures must be linked */
 866         this = &host->nand;
 867         mtd = &host->mtd;
 868         mtd->priv = this;
 869         mtd->owner = THIS_MODULE;
 870         mtd->dev.parent = &pdev->dev;
 871         mtd->name = "mxc_nand";
 872
 873         /* 50 us command delay time */
 874         this->chip_delay = 5;
 875
 876         this->priv = host;
 877         this->dev_ready = mxc_nand_dev_ready;
 878         this->cmdfunc = mxc_nand_command;
 879         this->select_chip = mxc_nand_select_chip;
 880         this->read_byte = mxc_nand_read_byte;
 881         this->read_word = mxc_nand_read_word;
 882         this->write_buf = mxc_nand_write_buf;
 883         this->read_buf = mxc_nand_read_buf;
 884         this->verify_buf = mxc_nand_verify_buf;
 885
 886         host->clk = clk_get(&pdev->dev, "nfc");
 887         if (IS_ERR(host->clk)) {
 888                 err = PTR_ERR(host->clk);
 889                 goto eclk;
 890         }
 891
 892         clk_enable(host->clk);
 893         host->clk_act = 1;
 894
 895         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 896         if (!res) {
 897                 err = -ENODEV;
 898                 goto eres;
 899         }
 900
 901         host->regs = ioremap(res->start, res->end - res->start + 1);
 902         if (!host->regs) {
 903                 err = -ENOMEM;
 904                 goto eres;
 905         }
 906
 907         tmp = readw(host->regs + NFC_CONFIG1);
 908         tmp |= NFC_INT_MSK;
 909         writew(tmp, host->regs + NFC_CONFIG1);
 910
 911         init_waitqueue_head(&host->irq_waitq);
 912
 913         host->irq = platform_get_irq(pdev, 0);
 914
 915         err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
 916         if (err)
 917                 goto eirq;
 918
 919         if (pdata->hw_ecc) {
 920                 this->ecc.calculate = mxc_nand_calculate_ecc;
 921                 this->ecc.hwctl = mxc_nand_enable_hwecc;
 922                 this->ecc.correct = mxc_nand_correct_data;
 923                 this->ecc.mode = NAND_ECC_HW;
 924                 this->ecc.size = 512;
 925                 this->ecc.bytes = 3;
 926                 this->ecc.layout = &nand_hw_eccoob_8;
 927                 tmp = readw(host->regs + NFC_CONFIG1);
 928                 tmp |= NFC_ECC_EN;
 929                 writew(tmp, host->regs + NFC_CONFIG1);
 930         } else {
 931                 this->ecc.size = 512;
 932                 this->ecc.bytes = 3;
 933                 this->ecc.layout = &nand_hw_eccoob_8;
 934                 this->ecc.mode = NAND_ECC_SOFT;
 935                 tmp = readw(host->regs + NFC_CONFIG1);
 936                 tmp &= ~NFC_ECC_EN;
 937                 writew(tmp, host->regs + NFC_CONFIG1);
 938         }
 939
 940         /* Reset NAND */
 941         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
 942
 943         /* preset operation */
 944         /* Unlock the internal RAM Buffer */
 945         writew(0x2, host->regs + NFC_CONFIG);
 946
 947         /* Blocks to be unlocked */
 948         writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
 949         writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
 950
 951         /* Unlock Block Command for given address range */
 952         writew(0x4, host->regs + NFC_WRPROT);
 953
 954         /* NAND bus width determines access funtions used by upper layer */
 955         if (pdata->width == 2) {
 956                 this->options |= NAND_BUSWIDTH_16;
 957                 this->ecc.layout = &nand_hw_eccoob_16;
 958         }
 959
 960         host->pagesize_2k = 0;
 961
 962         /* Scan to find existence of the device */
 963         if (nand_scan(mtd, 1)) {
 964                 DEBUG(MTD_DEBUG_LEVEL0,
 965                       "MXC_ND: Unable to find any NAND device.\n");
 966                 err = -ENXIO;
 967                 goto escan;
 968         }
 969
 970         /* Register the partitions */
 971 #ifdef CONFIG_MTD_PARTITIONS
 972         nr_parts =
 973             parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
 974         if (nr_parts > 0)
 975                 add_mtd_partitions(mtd, host->parts, nr_parts);
 976         else
 977 #endif
 978         {
 979                 pr_info("Registering %s as whole device\n", mtd->name);
 980                 add_mtd_device(mtd);
 981         }
 982
 983         platform_set_drvdata(pdev, host);
 984
 985         return 0;
 986
 987 escan:
 988         free_irq(host->irq, NULL);
 989 eirq:
 990         iounmap(host->regs);
 991 eres:
 992         clk_put(host->clk);
 993 eclk:
 994         kfree(host);
 995
 996         return err;
 997 }
 998
 999 static int __devexit mxcnd_remove(struct platform_device *pdev)
1000 {
1001         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1002
1003         clk_put(host->clk);
1004
1005         platform_set_drvdata(pdev, NULL);
1006
1007         nand_release(&host->mtd);
1008         free_irq(host->irq, NULL);
1009         iounmap(host->regs);
1010         kfree(host);
1011
1012         return 0;
1013 }
1014
1015 #ifdef CONFIG_PM
1016 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
1017 {
1018         struct mtd_info *mtd = platform_get_drvdata(pdev);
1019         struct nand_chip *nand_chip = mtd->priv;
1020         struct mxc_nand_host *host = nand_chip->priv;
1021         int ret = 0;
1022
1023         DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
1024         if (mtd) {
1025                 ret = mtd->suspend(mtd);
1026                 /* Disable the NFC clock */
1027                 clk_disable(host->clk);
1028         }
1029
1030         return ret;
1031 }
1032
1033 static int mxcnd_resume(struct platform_device *pdev)
1034 {
1035         struct mtd_info *mtd = platform_get_drvdata(pdev);
1036         struct nand_chip *nand_chip = mtd->priv;
1037         struct mxc_nand_host *host = nand_chip->priv;
1038         int ret = 0;
1039
1040         DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
1041
1042         if (mtd) {
1043                 /* Enable the NFC clock */
1044                 clk_enable(host->clk);
1045                 mtd->resume(mtd);
1046         }
1047
1048         return ret;
1049 }
1050
1051 #else
1052 # define mxcnd_suspend   NULL
1053 # define mxcnd_resume    NULL
1054 #endif                          /* CONFIG_PM */
1055
1056 static struct platform_driver mxcnd_driver = {
1057         .driver = {
1058                    .name = DRIVER_NAME,
1059                    },
1060         .remove = __exit_p(mxcnd_remove),
1061         .suspend = mxcnd_suspend,
1062         .resume = mxcnd_resume,
1063 };
1064
1065 static int __init mxc_nd_init(void)
1066 {
1067         return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1068 }
1069
1070 static void __exit mxc_nd_cleanup(void)
1071 {
1072         /* Unregister the device structure */
1073         platform_driver_unregister(&mxcnd_driver);
1074 }
1075
1076 module_init(mxc_nd_init);
1077 module_exit(mxc_nd_cleanup);
1078
1079 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1080 MODULE_DESCRIPTION("MXC NAND MTD driver");
1081 MODULE_LICENSE("GPL");