drivers/mtd/nand/cafe_nand.c

   1 /*
   2  * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
   3  *
   4  * The data sheet for this device can be found at:
   5  *    http://www.marvell.com/products/pcconn/88ALP01.jsp
   6  *
   7  * Copyright © 2006 Red Hat, Inc.
   8  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
   9  */
  10
  11 #define DEBUG
  12
  13 #include <linux/device.h>
  14 #undef DEBUG
  15 #include <linux/mtd/mtd.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/rslib.h>
  19 #include <linux/pci.h>
  20 #include <linux/delay.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/slab.h>
  24 #include <asm/io.h>
  25
  26 #define CAFE_NAND_CTRL1         0x00
  27 #define CAFE_NAND_CTRL2         0x04
  28 #define CAFE_NAND_CTRL3         0x08
  29 #define CAFE_NAND_STATUS        0x0c
  30 #define CAFE_NAND_IRQ           0x10
  31 #define CAFE_NAND_IRQ_MASK      0x14
  32 #define CAFE_NAND_DATA_LEN      0x18
  33 #define CAFE_NAND_ADDR1         0x1c
  34 #define CAFE_NAND_ADDR2         0x20
  35 #define CAFE_NAND_TIMING1       0x24
  36 #define CAFE_NAND_TIMING2       0x28
  37 #define CAFE_NAND_TIMING3       0x2c
  38 #define CAFE_NAND_NONMEM        0x30
  39 #define CAFE_NAND_ECC_RESULT    0x3C
  40 #define CAFE_NAND_DMA_CTRL      0x40
  41 #define CAFE_NAND_DMA_ADDR0     0x44
  42 #define CAFE_NAND_DMA_ADDR1     0x48
  43 #define CAFE_NAND_ECC_SYN01     0x50
  44 #define CAFE_NAND_ECC_SYN23     0x54
  45 #define CAFE_NAND_ECC_SYN45     0x58
  46 #define CAFE_NAND_ECC_SYN67     0x5c
  47 #define CAFE_NAND_READ_DATA     0x1000
  48 #define CAFE_NAND_WRITE_DATA    0x2000
  49
  50 #define CAFE_GLOBAL_CTRL        0x3004
  51 #define CAFE_GLOBAL_IRQ         0x3008
  52 #define CAFE_GLOBAL_IRQ_MASK    0x300c
  53 #define CAFE_NAND_RESET         0x3034
  54
  55 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
  56 #define CTRL1_CHIPSELECT        (1<<19)
  57
  58 struct cafe_priv {
  59         struct nand_chip nand;
  60         struct mtd_partition *parts;
  61         struct pci_dev *pdev;
  62         void __iomem *mmio;
  63         struct rs_control *rs;
  64         uint32_t ctl1;
  65         uint32_t ctl2;
  66         int datalen;
  67         int nr_data;
  68         int data_pos;
  69         int page_addr;
  70         dma_addr_t dmaaddr;
  71         unsigned char *dmabuf;
  72 };
  73
  74 static int usedma = 1;
  75 module_param(usedma, int, 0644);
  76
  77 static int skipbbt = 0;
  78 module_param(skipbbt, int, 0644);
  79
  80 static int debug = 0;
  81 module_param(debug, int, 0644);
  82
  83 static int regdebug = 0;
  84 module_param(regdebug, int, 0644);
  85
  86 static int checkecc = 1;
  87 module_param(checkecc, int, 0644);
  88
  89 static unsigned int numtimings;
  90 static int timing[3];
  91 module_param_array(timing, int, &numtimings, 0644);
  92
  93 #ifdef CONFIG_MTD_PARTITIONS
  94 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
  95 #endif
  96
  97 /* Hrm. Why isn't this already conditional on something in the struct device? */
  98 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
  99
 100 /* Make it easier to switch to PIO if we need to */
 101 #define cafe_readl(cafe, addr)                  readl((cafe)->mmio + CAFE_##addr)
 102 #define cafe_writel(cafe, datum, addr)          writel(datum, (cafe)->mmio + CAFE_##addr)
 103
 104 static int cafe_device_ready(struct mtd_info *mtd)
 105 {
 106         struct cafe_priv *cafe = mtd->priv;
 107         int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
 108         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
 109
 110         cafe_writel(cafe, irqs, NAND_IRQ);
 111
 112         cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
 113                 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
 114                 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
 115
 116         return result;
 117 }
 118
 119
 120 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 121 {
 122         struct cafe_priv *cafe = mtd->priv;
 123
 124         if (usedma)
 125                 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
 126         else
 127                 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
 128
 129         cafe->datalen += len;
 130
 131         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
 132                 len, cafe->datalen);
 133 }
 134
 135 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 136 {
 137         struct cafe_priv *cafe = mtd->priv;
 138
 139         if (usedma)
 140                 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
 141         else
 142                 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
 143
 144         cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
 145                   len, cafe->datalen);
 146         cafe->datalen += len;
 147 }
 148
 149 static uint8_t cafe_read_byte(struct mtd_info *mtd)
 150 {
 151         struct cafe_priv *cafe = mtd->priv;
 152         uint8_t d;
 153
 154         cafe_read_buf(mtd, &d, 1);
 155         cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
 156
 157         return d;
 158 }
 159
 160 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
 161                               int column, int page_addr)
 162 {
 163         struct cafe_priv *cafe = mtd->priv;
 164         int adrbytes = 0;
 165         uint32_t ctl1;
 166         uint32_t doneint = 0x80000000;
 167
 168         cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
 169                 command, column, page_addr);
 170
 171         if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
 172                 /* Second half of a command we already calculated */
 173                 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
 174                 ctl1 = cafe->ctl1;
 175                 cafe->ctl2 &= ~(1<<30);
 176                 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
 177                           cafe->ctl1, cafe->nr_data);
 178                 goto do_command;
 179         }
 180         /* Reset ECC engine */
 181         cafe_writel(cafe, 0, NAND_CTRL2);
 182
 183         /* Emulate NAND_CMD_READOOB on large-page chips */
 184         if (mtd->writesize > 512 &&
 185             command == NAND_CMD_READOOB) {
 186                 column += mtd->writesize;
 187                 command = NAND_CMD_READ0;
 188         }
 189
 190         /* FIXME: Do we need to send read command before sending data
 191            for small-page chips, to position the buffer correctly? */
 192
 193         if (column != -1) {
 194                 cafe_writel(cafe, column, NAND_ADDR1);
 195                 adrbytes = 2;
 196                 if (page_addr != -1)
 197                         goto write_adr2;
 198         } else if (page_addr != -1) {
 199                 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
 200                 page_addr >>= 16;
 201         write_adr2:
 202                 cafe_writel(cafe, page_addr, NAND_ADDR2);
 203                 adrbytes += 2;
 204                 if (mtd->size > mtd->writesize << 16)
 205                         adrbytes++;
 206         }
 207
 208         cafe->data_pos = cafe->datalen = 0;
 209
 210         /* Set command valid bit, mask in the chip select bit  */
 211         ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
 212
 213         /* Set RD or WR bits as appropriate */
 214         if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
 215                 ctl1 |= (1<<26); /* rd */
 216                 /* Always 5 bytes, for now */
 217                 cafe->datalen = 4;
 218                 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
 219                 adrbytes = 1;
 220         } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
 221                    command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
 222                 ctl1 |= 1<<26; /* rd */
 223                 /* For now, assume just read to end of page */
 224                 cafe->datalen = mtd->writesize + mtd->oobsize - column;
 225         } else if (command == NAND_CMD_SEQIN)
 226                 ctl1 |= 1<<25; /* wr */
 227
 228         /* Set number of address bytes */
 229         if (adrbytes)
 230                 ctl1 |= ((adrbytes-1)|8) << 27;
 231
 232         if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
 233                 /* Ignore the first command of a pair; the hardware
 234                    deals with them both at once, later */
 235                 cafe->ctl1 = ctl1;
 236                 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
 237                           cafe->ctl1, cafe->datalen);
 238                 return;
 239         }
 240         /* RNDOUT and READ0 commands need a following byte */
 241         if (command == NAND_CMD_RNDOUT)
 242                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
 243         else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
 244                 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
 245
 246  do_command:
 247         cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
 248                 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
 249
 250         /* NB: The datasheet lies -- we really should be subtracting 1 here */
 251         cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
 252         cafe_writel(cafe, 0x90000000, NAND_IRQ);
 253         if (usedma && (ctl1 & (3<<25))) {
 254                 uint32_t dmactl = 0xc0000000 + cafe->datalen;
 255                 /* If WR or RD bits set, set up DMA */
 256                 if (ctl1 & (1<<26)) {
 257                         /* It's a read */
 258                         dmactl |= (1<<29);
 259                         /* ... so it's done when the DMA is done, not just
 260                            the command. */
 261                         doneint = 0x10000000;
 262                 }
 263                 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
 264         }
 265         cafe->datalen = 0;
 266
 267         if (unlikely(regdebug)) {
 268                 int i;
 269                 printk("About to write command %08x to register 0\n", ctl1);
 270                 for (i=4; i< 0x5c; i+=4)
 271                         printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 272         }
 273
 274         cafe_writel(cafe, ctl1, NAND_CTRL1);
 275         /* Apply this short delay always to ensure that we do wait tWB in
 276          * any case on any machine. */
 277         ndelay(100);
 278
 279         if (1) {
 280                 int c;
 281                 uint32_t irqs;
 282
 283                 for (c = 500000; c != 0; c--) {
 284                         irqs = cafe_readl(cafe, NAND_IRQ);
 285                         if (irqs & doneint)
 286                                 break;
 287                         udelay(1);
 288                         if (!(c % 100000))
 289                                 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
 290                         cpu_relax();
 291                 }
 292                 cafe_writel(cafe, doneint, NAND_IRQ);
 293                 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
 294                              command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
 295         }
 296
 297         WARN_ON(cafe->ctl2 & (1<<30));
 298
 299         switch (command) {
 300
 301         case NAND_CMD_CACHEDPROG:
 302         case NAND_CMD_PAGEPROG:
 303         case NAND_CMD_ERASE1:
 304         case NAND_CMD_ERASE2:
 305         case NAND_CMD_SEQIN:
 306         case NAND_CMD_RNDIN:
 307         case NAND_CMD_STATUS:
 308         case NAND_CMD_DEPLETE1:
 309         case NAND_CMD_RNDOUT:
 310         case NAND_CMD_STATUS_ERROR:
 311         case NAND_CMD_STATUS_ERROR0:
 312         case NAND_CMD_STATUS_ERROR1:
 313         case NAND_CMD_STATUS_ERROR2:
 314         case NAND_CMD_STATUS_ERROR3:
 315                 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
 316                 return;
 317         }
 318         nand_wait_ready(mtd);
 319         cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
 320 }
 321
 322 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
 323 {
 324         struct cafe_priv *cafe = mtd->priv;
 325
 326         cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
 327
 328         /* Mask the appropriate bit into the stored value of ctl1
 329            which will be used by cafe_nand_cmdfunc() */
 330         if (chipnr)
 331                 cafe->ctl1 |= CTRL1_CHIPSELECT;
 332         else
 333                 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
 334 }
 335
 336 static irqreturn_t cafe_nand_interrupt(int irq, void *id)
 337 {
 338         struct mtd_info *mtd = id;
 339         struct cafe_priv *cafe = mtd->priv;
 340         uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
 341         cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
 342         if (!irqs)
 343                 return IRQ_NONE;
 344
 345         cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
 346         return IRQ_HANDLED;
 347 }
 348
 349 static void cafe_nand_bug(struct mtd_info *mtd)
 350 {
 351         BUG();
 352 }
 353
 354 static int cafe_nand_write_oob(struct mtd_info *mtd,
 355                                struct nand_chip *chip, int page)
 356 {
 357         int status = 0;
 358
 359         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 360         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 361         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 362         status = chip->waitfunc(mtd, chip);
 363
 364         return status & NAND_STATUS_FAIL ? -EIO : 0;
 365 }
 366
 367 /* Don't use -- use nand_read_oob_std for now */
 368 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
 369                               int page, int sndcmd)
 370 {
 371         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
 372         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 373         return 1;
 374 }
 375 /**
 376  * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
 377  * @mtd:        mtd info structure
 378  * @chip:       nand chip info structure
 379  * @buf:        buffer to store read data
 380  *
 381  * The hw generator calculates the error syndrome automatically. Therefor
 382  * we need a special oob layout and handling.
 383  */
 384 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 385                                uint8_t *buf, int page)
 386 {
 387         struct cafe_priv *cafe = mtd->priv;
 388
 389         cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
 390                      cafe_readl(cafe, NAND_ECC_RESULT),
 391                      cafe_readl(cafe, NAND_ECC_SYN01));
 392
 393         chip->read_buf(mtd, buf, mtd->writesize);
 394         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 395
 396         if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
 397                 unsigned short syn[8], pat[4];
 398                 int pos[4];
 399                 u8 *oob = chip->oob_poi;
 400                 int i, n;
 401
 402                 for (i=0; i<8; i+=2) {
 403                         uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
 404                         syn[i] = cafe->rs->index_of[tmp & 0xfff];
 405                         syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
 406                 }
 407
 408                 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
 409                                 pat);
 410
 411                 for (i = 0; i < n; i++) {
 412                         int p = pos[i];
 413
 414                         /* The 12-bit symbols are mapped to bytes here */
 415
 416                         if (p > 1374) {
 417                                 /* out of range */
 418                                 n = -1374;
 419                         } else if (p == 0) {
 420                                 /* high four bits do not correspond to data */
 421                                 if (pat[i] > 0xff)
 422                                         n = -2048;
 423                                 else
 424                                         buf[0] ^= pat[i];
 425                         } else if (p == 1365) {
 426                                 buf[2047] ^= pat[i] >> 4;
 427                                 oob[0] ^= pat[i] << 4;
 428                         } else if (p > 1365) {
 429                                 if ((p & 1) == 1) {
 430                                         oob[3*p/2 - 2048] ^= pat[i] >> 4;
 431                                         oob[3*p/2 - 2047] ^= pat[i] << 4;
 432                                 } else {
 433                                         oob[3*p/2 - 2049] ^= pat[i] >> 8;
 434                                         oob[3*p/2 - 2048] ^= pat[i];
 435                                 }
 436                         } else if ((p & 1) == 1) {
 437                                 buf[3*p/2] ^= pat[i] >> 4;
 438                                 buf[3*p/2 + 1] ^= pat[i] << 4;
 439                         } else {
 440                                 buf[3*p/2 - 1] ^= pat[i] >> 8;
 441                                 buf[3*p/2] ^= pat[i];
 442                         }
 443                 }
 444
 445                 if (n < 0) {
 446                         dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
 447                                 cafe_readl(cafe, NAND_ADDR2) * 2048);
 448                         for (i = 0; i < 0x5c; i += 4)
 449                                 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
 450                         mtd->ecc_stats.failed++;
 451                 } else {
 452                         dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
 453                         mtd->ecc_stats.corrected += n;
 454                 }
 455         }
 456
 457         return 0;
 458 }
 459
 460 static struct nand_ecclayout cafe_oobinfo_2048 = {
 461         .eccbytes = 14,
 462         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 463         .oobfree = {{14, 50}}
 464 };
 465
 466 /* Ick. The BBT code really ought to be able to work this bit out
 467    for itself from the above, at least for the 2KiB case */
 468 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
 469 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
 470
 471 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
 472 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
 473
 474
 475 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
 476         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 477                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
 478         .offs = 14,
 479         .len = 4,
 480         .veroffs = 18,
 481         .maxblocks = 4,
 482         .pattern = cafe_bbt_pattern_2048
 483 };
 484
 485 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
 486         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 487                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
 488         .offs = 14,
 489         .len = 4,
 490         .veroffs = 18,
 491         .maxblocks = 4,
 492         .pattern = cafe_mirror_pattern_2048
 493 };
 494
 495 static struct nand_ecclayout cafe_oobinfo_512 = {
 496         .eccbytes = 14,
 497         .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
 498         .oobfree = {{14, 2}}
 499 };
 500
 501 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
 502         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 503                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
 504         .offs = 14,
 505         .len = 1,
 506         .veroffs = 15,
 507         .maxblocks = 4,
 508         .pattern = cafe_bbt_pattern_512
 509 };
 510
 511 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
 512         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 513                 | NAND_BBT_2BIT | NAND_BBT_VERSION,
 514         .offs = 14,
 515         .len = 1,
 516         .veroffs = 15,
 517         .maxblocks = 4,
 518         .pattern = cafe_mirror_pattern_512
 519 };
 520
 521
 522 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
 523                                           struct nand_chip *chip, const uint8_t *buf)
 524 {
 525         struct cafe_priv *cafe = mtd->priv;
 526
 527         chip->write_buf(mtd, buf, mtd->writesize);
 528         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
 529
 530         /* Set up ECC autogeneration */
 531         cafe->ctl2 |= (1<<30);
 532 }
 533
 534 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 535                                 const uint8_t *buf, int page, int cached, int raw)
 536 {
 537         int status;
 538
 539         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
 540
 541         if (unlikely(raw))
 542                 chip->ecc.write_page_raw(mtd, chip, buf);
 543         else
 544                 chip->ecc.write_page(mtd, chip, buf);
 545
 546         /*
 547          * Cached progamming disabled for now, Not sure if its worth the
 548          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
 549          */
 550         cached = 0;
 551
 552         if (!cached || !(chip->options & NAND_CACHEPRG)) {
 553
 554                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 555                 status = chip->waitfunc(mtd, chip);
 556                 /*
 557                  * See if operation failed and additional status checks are
 558                  * available
 559                  */
 560                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
 561                         status = chip->errstat(mtd, chip, FL_WRITING, status,
 562                                                page);
 563
 564                 if (status & NAND_STATUS_FAIL)
 565                         return -EIO;
 566         } else {
 567                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
 568                 status = chip->waitfunc(mtd, chip);
 569         }
 570
 571 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
 572         /* Send command to read back the data */
 573         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
 574
 575         if (chip->verify_buf(mtd, buf, mtd->writesize))
 576                 return -EIO;
 577 #endif
 578         return 0;
 579 }
 580
 581 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 582 {
 583         return 0;
 584 }
 585
 586 /* F_2[X]/(X**6+X+1)  */
 587 static unsigned short __devinit gf64_mul(u8 a, u8 b)
 588 {
 589         u8 c;
 590         unsigned int i;
 591
 592         c = 0;
 593         for (i = 0; i < 6; i++) {
 594                 if (a & 1)
 595                         c ^= b;
 596                 a >>= 1;
 597                 b <<= 1;
 598                 if ((b & 0x40) != 0)
 599                         b ^= 0x43;
 600         }
 601
 602         return c;
 603 }
 604
 605 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X]  */
 606 static u16 __devinit gf4096_mul(u16 a, u16 b)
 607 {
 608         u8 ah, al, bh, bl, ch, cl;
 609
 610         ah = a >> 6;
 611         al = a & 0x3f;
 612         bh = b >> 6;
 613         bl = b & 0x3f;
 614
 615         ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
 616         cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
 617
 618         return (ch << 6) ^ cl;
 619 }
 620
 621 static int __devinit cafe_mul(int x)
 622 {
 623         if (x == 0)
 624                 return 1;
 625         return gf4096_mul(x, 0xe01);
 626 }
 627
 628 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
 629                                      const struct pci_device_id *ent)
 630 {
 631         struct mtd_info *mtd;
 632         struct cafe_priv *cafe;
 633         uint32_t ctrl;
 634         int err = 0;
 635 #ifdef CONFIG_MTD_PARTITIONS
 636         struct mtd_partition *parts;
 637         int nr_parts;
 638 #endif
 639
 640         /* Very old versions shared the same PCI ident for all three
 641            functions on the chip. Verify the class too... */
 642         if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
 643                 return -ENODEV;
 644
 645         err = pci_enable_device(pdev);
 646         if (err)
 647                 return err;
 648
 649         pci_set_master(pdev);
 650
 651         mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
 652         if (!mtd) {
 653                 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
 654                 return  -ENOMEM;
 655         }
 656         cafe = (void *)(&mtd[1]);
 657
 658         mtd->dev.parent = &pdev->dev;
 659         mtd->priv = cafe;
 660         mtd->owner = THIS_MODULE;
 661
 662         cafe->pdev = pdev;
 663         cafe->mmio = pci_iomap(pdev, 0, 0);
 664         if (!cafe->mmio) {
 665                 dev_warn(&pdev->dev, "failed to iomap\n");
 666                 err = -ENOMEM;
 667                 goto out_free_mtd;
 668         }
 669         cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
 670                                           &cafe->dmaaddr, GFP_KERNEL);
 671         if (!cafe->dmabuf) {
 672                 err = -ENOMEM;
 673                 goto out_ior;
 674         }
 675         cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
 676
 677         cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
 678         if (!cafe->rs) {
 679                 err = -ENOMEM;
 680                 goto out_ior;
 681         }
 682
 683         cafe->nand.cmdfunc = cafe_nand_cmdfunc;
 684         cafe->nand.dev_ready = cafe_device_ready;
 685         cafe->nand.read_byte = cafe_read_byte;
 686         cafe->nand.read_buf = cafe_read_buf;
 687         cafe->nand.write_buf = cafe_write_buf;
 688         cafe->nand.select_chip = cafe_select_chip;
 689
 690         cafe->nand.chip_delay = 0;
 691
 692         /* Enable the following for a flash based bad block table */
 693         cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
 694
 695         if (skipbbt) {
 696                 cafe->nand.options |= NAND_SKIP_BBTSCAN;
 697                 cafe->nand.block_bad = cafe_nand_block_bad;
 698         }
 699
 700         if (numtimings && numtimings != 3) {
 701                 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
 702         }
 703
 704         if (numtimings == 3) {
 705                 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
 706                              timing[0], timing[1], timing[2]);
 707         } else {
 708                 timing[0] = cafe_readl(cafe, NAND_TIMING1);
 709                 timing[1] = cafe_readl(cafe, NAND_TIMING2);
 710                 timing[2] = cafe_readl(cafe, NAND_TIMING3);
 711
 712                 if (timing[0] | timing[1] | timing[2]) {
 713                         cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
 714                                      timing[0], timing[1], timing[2]);
 715                 } else {
 716                         dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
 717                         timing[0] = timing[1] = timing[2] = 0xffffffff;
 718                 }
 719         }
 720
 721         /* Start off by resetting the NAND controller completely */
 722         cafe_writel(cafe, 1, NAND_RESET);
 723         cafe_writel(cafe, 0, NAND_RESET);
 724
 725         cafe_writel(cafe, timing[0], NAND_TIMING1);
 726         cafe_writel(cafe, timing[1], NAND_TIMING2);
 727         cafe_writel(cafe, timing[2], NAND_TIMING3);
 728
 729         cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
 730         err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
 731                           "CAFE NAND", mtd);
 732         if (err) {
 733                 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
 734                 goto out_free_dma;
 735         }
 736
 737         /* Disable master reset, enable NAND clock */
 738         ctrl = cafe_readl(cafe, GLOBAL_CTRL);
 739         ctrl &= 0xffffeff0;
 740         ctrl |= 0x00007000;
 741         cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
 742         cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
 743         cafe_writel(cafe, 0, NAND_DMA_CTRL);
 744
 745         cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
 746         cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
 747
 748         /* Set up DMA address */
 749         cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
 750         if (sizeof(cafe->dmaaddr) > 4)
 751                 /* Shift in two parts to shut the compiler up */
 752                 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
 753         else
 754                 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
 755
 756         cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
 757                 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
 758
 759         /* Enable NAND IRQ in global IRQ mask register */
 760         cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
 761         cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
 762                 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
 763
 764         /* Scan to find existence of the device */
 765         if (nand_scan_ident(mtd, 2, NULL)) {
 766                 err = -ENXIO;
 767                 goto out_irq;
 768         }
 769
 770         cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
 771         if (mtd->writesize == 2048)
 772                 cafe->ctl2 |= 1<<29; /* 2KiB page size */
 773
 774         /* Set up ECC according to the type of chip we found */
 775         if (mtd->writesize == 2048) {
 776                 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
 777                 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
 778                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
 779         } else if (mtd->writesize == 512) {
 780                 cafe->nand.ecc.layout = &cafe_oobinfo_512;
 781                 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
 782                 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
 783         } else {
 784                 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
 785                        mtd->writesize);
 786                 goto out_irq;
 787         }
 788         cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
 789         cafe->nand.ecc.size = mtd->writesize;
 790         cafe->nand.ecc.bytes = 14;
 791         cafe->nand.ecc.hwctl  = (void *)cafe_nand_bug;
 792         cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
 793         cafe->nand.ecc.correct  = (void *)cafe_nand_bug;
 794         cafe->nand.write_page = cafe_nand_write_page;
 795         cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
 796         cafe->nand.ecc.write_oob = cafe_nand_write_oob;
 797         cafe->nand.ecc.read_page = cafe_nand_read_page;
 798         cafe->nand.ecc.read_oob = cafe_nand_read_oob;
 799
 800         err = nand_scan_tail(mtd);
 801         if (err)
 802                 goto out_irq;
 803
 804         pci_set_drvdata(pdev, mtd);
 805
 806         /* We register the whole device first, separate from the partitions */
 807         add_mtd_device(mtd);
 808
 809 #ifdef CONFIG_MTD_PARTITIONS
 810 #ifdef CONFIG_MTD_CMDLINE_PARTS
 811         mtd->name = "cafe_nand";
 812 #endif
 813         nr_parts = parse_mtd_partitions(mtd, part_probes, &parts, 0);
 814         if (nr_parts > 0) {
 815                 cafe->parts = parts;
 816                 dev_info(&cafe->pdev->dev, "%d partitions found\n", nr_parts);
 817                 add_mtd_partitions(mtd, parts, nr_parts);
 818         }
 819 #endif
 820         goto out;
 821
 822  out_irq:
 823         /* Disable NAND IRQ in global IRQ mask register */
 824         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
 825         free_irq(pdev->irq, mtd);
 826  out_free_dma:
 827         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 828  out_ior:
 829         pci_iounmap(pdev, cafe->mmio);
 830  out_free_mtd:
 831         kfree(mtd);
 832  out:
 833         return err;
 834 }
 835
 836 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
 837 {
 838         struct mtd_info *mtd = pci_get_drvdata(pdev);
 839         struct cafe_priv *cafe = mtd->priv;
 840
 841         del_mtd_device(mtd);
 842         /* Disable NAND IRQ in global IRQ mask register */
 843         cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
 844         free_irq(pdev->irq, mtd);
 845         nand_release(mtd);
 846         free_rs(cafe->rs);
 847         pci_iounmap(pdev, cafe->mmio);
 848         dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
 849         kfree(mtd);
 850 }
 851
 852 static const struct pci_device_id cafe_nand_tbl[] = {
 853         { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
 854           PCI_ANY_ID, PCI_ANY_ID },
 855         { }
 856 };
 857
 858 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
 859
 860 static int cafe_nand_resume(struct pci_dev *pdev)
 861 {
 862         uint32_t ctrl;
 863         struct mtd_info *mtd = pci_get_drvdata(pdev);
 864         struct cafe_priv *cafe = mtd->priv;
 865
 866        /* Start off by resetting the NAND controller completely */
 867         cafe_writel(cafe, 1, NAND_RESET);
 868         cafe_writel(cafe, 0, NAND_RESET);
 869         cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
 870
 871         /* Restore timing configuration */
 872         cafe_writel(cafe, timing[0], NAND_TIMING1);
 873         cafe_writel(cafe, timing[1], NAND_TIMING2);
 874         cafe_writel(cafe, timing[2], NAND_TIMING3);
 875
 876         /* Disable master reset, enable NAND clock */
 877         ctrl = cafe_readl(cafe, GLOBAL_CTRL);
 878         ctrl &= 0xffffeff0;
 879         ctrl |= 0x00007000;
 880         cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
 881         cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
 882         cafe_writel(cafe, 0, NAND_DMA_CTRL);
 883         cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
 884         cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
 885
 886         /* Set up DMA address */
 887         cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
 888         if (sizeof(cafe->dmaaddr) > 4)
 889         /* Shift in two parts to shut the compiler up */
 890                 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
 891         else
 892                 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
 893
 894         /* Enable NAND IRQ in global IRQ mask register */
 895         cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
 896         return 0;
 897 }
 898
 899 static struct pci_driver cafe_nand_pci_driver = {
 900         .name = "CAFÉ NAND",
 901         .id_table = cafe_nand_tbl,
 902         .probe = cafe_nand_probe,
 903         .remove = __devexit_p(cafe_nand_remove),
 904         .resume = cafe_nand_resume,
 905 };
 906
 907 static int __init cafe_nand_init(void)
 908 {
 909         return pci_register_driver(&cafe_nand_pci_driver);
 910 }
 911
 912 static void __exit cafe_nand_exit(void)
 913 {
 914         pci_unregister_driver(&cafe_nand_pci_driver);
 915 }
 916 module_init(cafe_nand_init);
 917 module_exit(cafe_nand_exit);
 918
 919 MODULE_LICENSE("GPL");
 920 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 921 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");