2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
4 * Copyright © 2006 Red Hat, Inc.
5 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
10 #include <linux/device.h>
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/nand.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
19 #define CAFE_NAND_CTRL1 0x00
20 #define CAFE_NAND_CTRL2 0x04
21 #define CAFE_NAND_CTRL3 0x08
22 #define CAFE_NAND_STATUS 0x0c
23 #define CAFE_NAND_IRQ 0x10
24 #define CAFE_NAND_IRQ_MASK 0x14
25 #define CAFE_NAND_DATA_LEN 0x18
26 #define CAFE_NAND_ADDR1 0x1c
27 #define CAFE_NAND_ADDR2 0x20
28 #define CAFE_NAND_TIMING1 0x24
29 #define CAFE_NAND_TIMING2 0x28
30 #define CAFE_NAND_TIMING3 0x2c
31 #define CAFE_NAND_NONMEM 0x30
32 #define CAFE_NAND_ECC_RESULT 0x3C
33 #define CAFE_NAND_DMA_CTRL 0x40
34 #define CAFE_NAND_DMA_ADDR0 0x44
35 #define CAFE_NAND_DMA_ADDR1 0x48
36 #define CAFE_NAND_ECC_SYN01 0x50
37 #define CAFE_NAND_ECC_SYN23 0x54
38 #define CAFE_NAND_ECC_SYN45 0x58
39 #define CAFE_NAND_ECC_SYN67 0x5c
40 #define CAFE_NAND_READ_DATA 0x1000
41 #define CAFE_NAND_WRITE_DATA 0x2000
43 #define CAFE_GLOBAL_CTRL 0x3004
44 #define CAFE_GLOBAL_IRQ 0x3008
45 #define CAFE_GLOBAL_IRQ_MASK 0x300c
46 #define CAFE_NAND_RESET 0x3034
48 int cafe_correct_ecc(unsigned char *buf,
49 unsigned short *chk_syndrome_list);
52 struct nand_chip nand;
62 unsigned char *dmabuf;
65 static int usedma = 1;
66 module_param(usedma, int, 0644);
68 static int skipbbt = 0;
69 module_param(skipbbt, int, 0644);
72 module_param(debug, int, 0644);
74 static int regdebug = 0;
75 module_param(regdebug, int, 0644);
77 static int checkecc = 1;
78 module_param(checkecc, int, 0644);
80 static int numtimings;
82 module_param_array(timing, int, &numtimings, 0644);
84 /* Hrm. Why isn't this already conditional on something in the struct device? */
85 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
87 /* Make it easier to switch to PIO if we need to */
88 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
89 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
91 static int cafe_device_ready(struct mtd_info *mtd)
93 struct cafe_priv *cafe = mtd->priv;
94 int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
95 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
97 cafe_writel(cafe, irqs, NAND_IRQ);
99 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
100 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
101 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
107 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
109 struct cafe_priv *cafe = mtd->priv;
112 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
114 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
116 cafe->datalen += len;
118 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
122 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
124 struct cafe_priv *cafe = mtd->priv;
127 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
129 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
133 cafe->datalen += len;
136 static uint8_t cafe_read_byte(struct mtd_info *mtd)
138 struct cafe_priv *cafe = mtd->priv;
141 cafe_read_buf(mtd, &d, 1);
142 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
147 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
148 int column, int page_addr)
150 struct cafe_priv *cafe = mtd->priv;
153 uint32_t doneint = 0x80000000;
155 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
156 command, column, page_addr);
158 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
159 /* Second half of a command we already calculated */
160 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
162 cafe->ctl2 &= ~(1<<30);
163 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
164 cafe->ctl1, cafe->nr_data);
167 /* Reset ECC engine */
168 cafe_writel(cafe, 0, NAND_CTRL2);
170 /* Emulate NAND_CMD_READOOB on large-page chips */
171 if (mtd->writesize > 512 &&
172 command == NAND_CMD_READOOB) {
173 column += mtd->writesize;
174 command = NAND_CMD_READ0;
177 /* FIXME: Do we need to send read command before sending data
178 for small-page chips, to position the buffer correctly? */
181 cafe_writel(cafe, column, NAND_ADDR1);
185 } else if (page_addr != -1) {
186 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
189 cafe_writel(cafe, page_addr, NAND_ADDR2);
191 if (mtd->size > mtd->writesize << 16)
195 cafe->data_pos = cafe->datalen = 0;
197 /* Set command valid bit */
198 ctl1 = 0x80000000 | command;
200 /* Set RD or WR bits as appropriate */
201 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
202 ctl1 |= (1<<26); /* rd */
203 /* Always 5 bytes, for now */
205 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
207 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
208 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
209 ctl1 |= 1<<26; /* rd */
210 /* For now, assume just read to end of page */
211 cafe->datalen = mtd->writesize + mtd->oobsize - column;
212 } else if (command == NAND_CMD_SEQIN)
213 ctl1 |= 1<<25; /* wr */
215 /* Set number of address bytes */
217 ctl1 |= ((adrbytes-1)|8) << 27;
219 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
220 /* Ignore the first command of a pair; the hardware
221 deals with them both at once, later */
223 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
224 cafe->ctl1, cafe->datalen);
227 /* RNDOUT and READ0 commands need a following byte */
228 if (command == NAND_CMD_RNDOUT)
229 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
230 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
231 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
234 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
235 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
237 /* NB: The datasheet lies -- we really should be subtracting 1 here */
238 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
239 cafe_writel(cafe, 0x90000000, NAND_IRQ);
240 if (usedma && (ctl1 & (3<<25))) {
241 uint32_t dmactl = 0xc0000000 + cafe->datalen;
242 /* If WR or RD bits set, set up DMA */
243 if (ctl1 & (1<<26)) {
246 /* ... so it's done when the DMA is done, not just
248 doneint = 0x10000000;
250 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
254 if (unlikely(regdebug)) {
256 printk("About to write command %08x to register 0\n", ctl1);
257 for (i=4; i< 0x5c; i+=4)
258 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
261 cafe_writel(cafe, ctl1, NAND_CTRL1);
262 /* Apply this short delay always to ensure that we do wait tWB in
263 * any case on any machine. */
271 irqs = cafe_readl(cafe, NAND_IRQ);
276 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
279 cafe_writel(cafe, doneint, NAND_IRQ);
280 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
281 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
284 WARN_ON(cafe->ctl2 & (1<<30));
288 case NAND_CMD_CACHEDPROG:
289 case NAND_CMD_PAGEPROG:
290 case NAND_CMD_ERASE1:
291 case NAND_CMD_ERASE2:
294 case NAND_CMD_STATUS:
295 case NAND_CMD_DEPLETE1:
296 case NAND_CMD_RNDOUT:
297 case NAND_CMD_STATUS_ERROR:
298 case NAND_CMD_STATUS_ERROR0:
299 case NAND_CMD_STATUS_ERROR1:
300 case NAND_CMD_STATUS_ERROR2:
301 case NAND_CMD_STATUS_ERROR3:
302 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
305 nand_wait_ready(mtd);
306 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
309 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
311 //struct cafe_priv *cafe = mtd->priv;
312 // cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
315 static int cafe_nand_interrupt(int irq, void *id)
317 struct mtd_info *mtd = id;
318 struct cafe_priv *cafe = mtd->priv;
319 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
320 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
324 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
328 static void cafe_nand_bug(struct mtd_info *mtd)
333 static int cafe_nand_write_oob(struct mtd_info *mtd,
334 struct nand_chip *chip, int page)
338 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
339 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
340 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
341 status = chip->waitfunc(mtd, chip);
343 return status & NAND_STATUS_FAIL ? -EIO : 0;
346 /* Don't use -- use nand_read_oob_std for now */
347 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
348 int page, int sndcmd)
350 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
351 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
355 * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
356 * @mtd: mtd info structure
357 * @chip: nand chip info structure
358 * @buf: buffer to store read data
360 * The hw generator calculates the error syndrome automatically. Therefor
361 * we need a special oob layout and handling.
363 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
366 struct cafe_priv *cafe = mtd->priv;
368 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
369 cafe_readl(cafe, NAND_ECC_RESULT),
370 cafe_readl(cafe, NAND_ECC_SYN01));
372 chip->read_buf(mtd, buf, mtd->writesize);
373 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
375 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
376 unsigned short syn[8];
379 for (i=0; i<8; i+=2) {
380 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
381 syn[i] = tmp & 0xfff;
382 syn[i+1] = (tmp >> 16) & 0xfff;
385 if ((i = cafe_correct_ecc(buf, syn)) < 0) {
386 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
387 cafe_readl(cafe, NAND_ADDR2) * 2048);
388 for (i=0; i< 0x5c; i+=4)
389 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
390 mtd->ecc_stats.failed++;
392 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i);
393 mtd->ecc_stats.corrected += i;
401 static struct nand_ecclayout cafe_oobinfo_2048 = {
403 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
404 .oobfree = {{14, 50}}
407 /* Ick. The BBT code really ought to be able to work this bit out
408 for itself from the above, at least for the 2KiB case */
409 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
410 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
412 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
413 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
416 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
417 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
418 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
423 .pattern = cafe_bbt_pattern_2048
426 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
427 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
428 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
433 .pattern = cafe_mirror_pattern_2048
436 static struct nand_ecclayout cafe_oobinfo_512 = {
438 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
442 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
443 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
444 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
449 .pattern = cafe_bbt_pattern_512
452 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
453 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
454 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
459 .pattern = cafe_mirror_pattern_512
463 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
464 struct nand_chip *chip, const uint8_t *buf)
466 struct cafe_priv *cafe = mtd->priv;
468 chip->write_buf(mtd, buf, mtd->writesize);
469 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
471 /* Set up ECC autogeneration */
472 cafe->ctl2 |= (1<<30);
475 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
476 const uint8_t *buf, int page, int cached, int raw)
480 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
483 chip->ecc.write_page_raw(mtd, chip, buf);
485 chip->ecc.write_page(mtd, chip, buf);
488 * Cached progamming disabled for now, Not sure if its worth the
489 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
493 if (!cached || !(chip->options & NAND_CACHEPRG)) {
495 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
496 status = chip->waitfunc(mtd, chip);
498 * See if operation failed and additional status checks are
501 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
502 status = chip->errstat(mtd, chip, FL_WRITING, status,
505 if (status & NAND_STATUS_FAIL)
508 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
509 status = chip->waitfunc(mtd, chip);
512 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
513 /* Send command to read back the data */
514 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
516 if (chip->verify_buf(mtd, buf, mtd->writesize))
522 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
527 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
528 const struct pci_device_id *ent)
530 struct mtd_info *mtd;
531 struct cafe_priv *cafe;
532 uint32_t timing1, timing2, timing3;
536 err = pci_enable_device(pdev);
540 pci_set_master(pdev);
542 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
544 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
547 cafe = (void *)(&mtd[1]);
550 mtd->owner = THIS_MODULE;
553 cafe->mmio = pci_iomap(pdev, 0, 0);
555 dev_warn(&pdev->dev, "failed to iomap\n");
559 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
560 &cafe->dmaaddr, GFP_KERNEL);
565 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
567 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
568 cafe->nand.dev_ready = cafe_device_ready;
569 cafe->nand.read_byte = cafe_read_byte;
570 cafe->nand.read_buf = cafe_read_buf;
571 cafe->nand.write_buf = cafe_write_buf;
572 cafe->nand.select_chip = cafe_select_chip;
574 cafe->nand.chip_delay = 0;
576 /* Enable the following for a flash based bad block table */
577 cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
580 cafe->nand.options |= NAND_SKIP_BBTSCAN;
581 cafe->nand.block_bad = cafe_nand_block_bad;
584 if (numtimings && numtimings != 3) {
585 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
588 if (numtimings == 3) {
592 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
593 timing1, timing2, timing3);
595 timing1 = cafe_readl(cafe, NAND_TIMING1);
596 timing2 = cafe_readl(cafe, NAND_TIMING2);
597 timing3 = cafe_readl(cafe, NAND_TIMING3);
599 if (timing1 | timing2 | timing3) {
600 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n", timing1, timing2, timing3);
602 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
603 timing1 = timing2 = timing3 = 0xffffffff;
607 /* Start off by resetting the NAND controller completely */
608 cafe_writel(cafe, 1, NAND_RESET);
609 cafe_writel(cafe, 0, NAND_RESET);
611 cafe_writel(cafe, timing1, NAND_TIMING1);
612 cafe_writel(cafe, timing2, NAND_TIMING2);
613 cafe_writel(cafe, timing3, NAND_TIMING3);
615 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
616 err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
618 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
622 /* Disable master reset, enable NAND clock */
623 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
626 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
627 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
628 cafe_writel(cafe, 0, NAND_DMA_CTRL);
630 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
631 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
633 /* Set up DMA address */
634 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
635 if (sizeof(cafe->dmaaddr) > 4)
636 /* Shift in two parts to shut the compiler up */
637 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
639 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
641 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
642 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
644 /* Enable NAND IRQ in global IRQ mask register */
645 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
646 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
647 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
649 /* Scan to find existence of the device */
650 if (nand_scan_ident(mtd, 1)) {
655 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
656 if (mtd->writesize == 2048)
657 cafe->ctl2 |= 1<<29; /* 2KiB page size */
659 /* Set up ECC according to the type of chip we found */
660 if (mtd->writesize == 2048) {
661 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
662 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
663 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
664 } else if (mtd->writesize == 512) {
665 cafe->nand.ecc.layout = &cafe_oobinfo_512;
666 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
667 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
669 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
673 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
674 cafe->nand.ecc.size = mtd->writesize;
675 cafe->nand.ecc.bytes = 14;
676 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
677 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
678 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
679 cafe->nand.write_page = cafe_nand_write_page;
680 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
681 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
682 cafe->nand.ecc.read_page = cafe_nand_read_page;
683 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
685 err = nand_scan_tail(mtd);
689 pci_set_drvdata(pdev, mtd);
694 /* Disable NAND IRQ in global IRQ mask register */
695 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
696 free_irq(pdev->irq, mtd);
698 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
700 pci_iounmap(pdev, cafe->mmio);
707 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
709 struct mtd_info *mtd = pci_get_drvdata(pdev);
710 struct cafe_priv *cafe = mtd->priv;
713 /* Disable NAND IRQ in global IRQ mask register */
714 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
715 free_irq(pdev->irq, mtd);
717 pci_iounmap(pdev, cafe->mmio);
718 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
722 static struct pci_device_id cafe_nand_tbl[] = {
723 { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 }
726 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
728 static struct pci_driver cafe_nand_pci_driver = {
730 .id_table = cafe_nand_tbl,
731 .probe = cafe_nand_probe,
732 .remove = __devexit_p(cafe_nand_remove),
734 .suspend = cafe_nand_suspend,
735 .resume = cafe_nand_resume,
739 static int cafe_nand_init(void)
741 return pci_register_driver(&cafe_nand_pci_driver);
744 static void cafe_nand_exit(void)
746 pci_unregister_driver(&cafe_nand_pci_driver);
748 module_init(cafe_nand_init);
749 module_exit(cafe_nand_exit);
751 MODULE_LICENSE("GPL");
752 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
753 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");