2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
4 * Copyright © 2006 Red Hat, Inc.
5 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
10 #include <linux/device.h>
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/nand.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
19 #define CAFE_NAND_CTRL1 0x00
20 #define CAFE_NAND_CTRL2 0x04
21 #define CAFE_NAND_CTRL3 0x08
22 #define CAFE_NAND_STATUS 0x0c
23 #define CAFE_NAND_IRQ 0x10
24 #define CAFE_NAND_IRQ_MASK 0x14
25 #define CAFE_NAND_DATA_LEN 0x18
26 #define CAFE_NAND_ADDR1 0x1c
27 #define CAFE_NAND_ADDR2 0x20
28 #define CAFE_NAND_TIMING1 0x24
29 #define CAFE_NAND_TIMING2 0x28
30 #define CAFE_NAND_TIMING3 0x2c
31 #define CAFE_NAND_NONMEM 0x30
32 #define CAFE_NAND_ECC_RESULT 0x3C
33 #define CAFE_NAND_DMA_CTRL 0x40
34 #define CAFE_NAND_DMA_ADDR0 0x44
35 #define CAFE_NAND_DMA_ADDR1 0x48
36 #define CAFE_NAND_ECC_SYN01 0x50
37 #define CAFE_NAND_ECC_SYN23 0x54
38 #define CAFE_NAND_ECC_SYN45 0x58
39 #define CAFE_NAND_ECC_SYN67 0x5c
40 #define CAFE_NAND_READ_DATA 0x1000
41 #define CAFE_NAND_WRITE_DATA 0x2000
43 #define CAFE_GLOBAL_CTRL 0x3004
44 #define CAFE_GLOBAL_IRQ 0x3008
45 #define CAFE_GLOBAL_IRQ_MASK 0x300c
46 #define CAFE_NAND_RESET 0x3034
48 int cafe_correct_ecc(unsigned char *buf,
49 unsigned short *chk_syndrome_list);
52 struct nand_chip nand;
62 unsigned char *dmabuf;
66 static int usedma = 1;
67 module_param(usedma, int, 0644);
69 static int skipbbt = 0;
70 module_param(skipbbt, int, 0644);
73 module_param(debug, int, 0644);
75 static int checkecc = 1;
76 module_param(checkecc, int, 0644);
78 static int slowtiming = 0;
79 module_param(slowtiming, int, 0644);
81 /* Hrm. Why isn't this already conditional on something in the struct device? */
82 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
84 /* Make it easier to switch to PIO if we need to */
85 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
86 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
88 static int cafe_device_ready(struct mtd_info *mtd)
90 struct cafe_priv *cafe = mtd->priv;
91 int result = !!(cafe_readl(cafe, NAND_STATUS) | 0x40000000);
92 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
94 cafe_writel(cafe, irqs, NAND_IRQ);
96 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
97 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
98 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
104 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
106 struct cafe_priv *cafe = mtd->priv;
109 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
111 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
113 cafe->datalen += len;
115 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
119 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
121 struct cafe_priv *cafe = mtd->priv;
124 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
126 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
128 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
130 cafe->datalen += len;
133 static uint8_t cafe_read_byte(struct mtd_info *mtd)
135 struct cafe_priv *cafe = mtd->priv;
138 cafe_read_buf(mtd, &d, 1);
139 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
144 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
145 int column, int page_addr)
147 struct cafe_priv *cafe = mtd->priv;
150 uint32_t doneint = 0x80000000;
152 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
153 command, column, page_addr);
155 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
156 /* Second half of a command we already calculated */
157 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
159 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
160 cafe->ctl1, cafe->nr_data);
163 /* Reset ECC engine */
164 cafe_writel(cafe, 0, NAND_CTRL2);
166 /* Emulate NAND_CMD_READOOB on large-page chips */
167 if (mtd->writesize > 512 &&
168 command == NAND_CMD_READOOB) {
169 column += mtd->writesize;
170 command = NAND_CMD_READ0;
173 /* FIXME: Do we need to send read command before sending data
174 for small-page chips, to position the buffer correctly? */
177 cafe_writel(cafe, column, NAND_ADDR1);
181 } else if (page_addr != -1) {
182 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
185 cafe_writel(cafe, page_addr, NAND_ADDR2);
187 if (mtd->size > mtd->writesize << 16)
191 cafe->data_pos = cafe->datalen = 0;
193 /* Set command valid bit */
194 ctl1 = 0x80000000 | command;
196 /* Set RD or WR bits as appropriate */
197 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
198 ctl1 |= (1<<26); /* rd */
199 /* Always 5 bytes, for now */
201 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
203 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
204 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
205 ctl1 |= 1<<26; /* rd */
206 /* For now, assume just read to end of page */
207 cafe->datalen = mtd->writesize + mtd->oobsize - column;
208 } else if (command == NAND_CMD_SEQIN)
209 ctl1 |= 1<<25; /* wr */
211 /* Set number of address bytes */
213 ctl1 |= ((adrbytes-1)|8) << 27;
215 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
216 /* Ignore the first command of a pair; the hardware
217 deals with them both at once, later */
220 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
221 cafe->ctl1, cafe->datalen);
224 /* RNDOUT and READ0 commands need a following byte */
225 if (command == NAND_CMD_RNDOUT)
226 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
227 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
228 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
232 /* http://dev.laptop.org/ticket/200
233 ECC on read only works if we read precisely 0x80e bytes */
234 if (cafe->datalen == 2112)
235 cafe->datalen = 2062;
237 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
238 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
240 /* NB: The datasheet lies -- we really should be subtracting 1 here */
241 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
242 cafe_writel(cafe, 0x90000000, NAND_IRQ);
243 if (usedma && (ctl1 & (3<<25))) {
244 uint32_t dmactl = 0xc0000000 + cafe->datalen;
245 /* If WR or RD bits set, set up DMA */
246 if (ctl1 & (1<<26)) {
249 /* ... so it's done when the DMA is done, not just
251 doneint = 0x10000000;
253 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
259 printk("About to write command %08x\n", ctl1);
260 for (i=0; i< 0x5c; i+=4)
261 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
264 cafe_writel(cafe, ctl1, NAND_CTRL1);
265 /* Apply this short delay always to ensure that we do wait tWB in
266 * any case on any machine. */
274 irqs = cafe_readl(cafe, NAND_IRQ);
279 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
282 cafe_writel(cafe, doneint, NAND_IRQ);
283 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
284 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
288 cafe->ctl2 &= ~(1<<8);
289 cafe->ctl2 &= ~(1<<30);
293 case NAND_CMD_CACHEDPROG:
294 case NAND_CMD_PAGEPROG:
295 case NAND_CMD_ERASE1:
296 case NAND_CMD_ERASE2:
299 case NAND_CMD_STATUS:
300 case NAND_CMD_DEPLETE1:
301 case NAND_CMD_RNDOUT:
302 case NAND_CMD_STATUS_ERROR:
303 case NAND_CMD_STATUS_ERROR0:
304 case NAND_CMD_STATUS_ERROR1:
305 case NAND_CMD_STATUS_ERROR2:
306 case NAND_CMD_STATUS_ERROR3:
307 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
310 nand_wait_ready(mtd);
311 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
314 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
316 //struct cafe_priv *cafe = mtd->priv;
317 // cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
320 static int cafe_nand_interrupt(int irq, void *id, struct pt_regs *regs)
322 struct mtd_info *mtd = id;
323 struct cafe_priv *cafe = mtd->priv;
324 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
325 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
329 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
333 static void cafe_nand_bug(struct mtd_info *mtd)
338 static int cafe_nand_write_oob(struct mtd_info *mtd,
339 struct nand_chip *chip, int page)
343 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
344 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
345 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
346 status = chip->waitfunc(mtd, chip);
348 return status & NAND_STATUS_FAIL ? -EIO : 0;
351 /* Don't use -- use nand_read_oob_std for now */
352 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
353 int page, int sndcmd)
355 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
356 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
360 * cafe_nand_read_page_syndrome - {REPLACABLE] hardware ecc syndrom based page read
361 * @mtd: mtd info structure
362 * @chip: nand chip info structure
363 * @buf: buffer to store read data
365 * The hw generator calculates the error syndrome automatically. Therefor
366 * we need a special oob layout and handling.
368 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
371 struct cafe_priv *cafe = mtd->priv;
373 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
374 cafe_readl(cafe, NAND_ECC_RESULT),
375 cafe_readl(cafe, NAND_ECC_SYN01));
377 chip->read_buf(mtd, buf, mtd->writesize);
378 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
380 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
381 unsigned short syn[8];
384 for (i=0; i<8; i+=2) {
385 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
386 syn[i] = tmp & 0xfff;
387 syn[i+1] = (tmp >> 16) & 0xfff;
390 if ((i = cafe_correct_ecc(buf, syn)) < 0) {
391 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC\n");
392 mtd->ecc_stats.failed++;
394 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", i);
395 mtd->ecc_stats.corrected += i;
403 static struct nand_ecclayout cafe_oobinfo_2048 = {
405 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
406 .oobfree = {{14, 50}}
409 /* Ick. The BBT code really ought to be able to work this bit out
410 for itself from the above, at least for the 2KiB case */
411 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
412 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
414 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
415 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
418 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
419 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
420 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
425 .pattern = cafe_bbt_pattern_2048
428 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
429 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
430 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
435 .pattern = cafe_mirror_pattern_2048
438 static struct nand_ecclayout cafe_oobinfo_512 = {
440 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
444 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
445 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
446 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
451 .pattern = cafe_bbt_pattern_512
454 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
455 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
456 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
461 .pattern = cafe_mirror_pattern_512
465 static void cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
466 struct nand_chip *chip, const uint8_t *buf)
468 struct cafe_priv *cafe = mtd->priv;
470 chip->write_buf(mtd, buf, mtd->writesize);
471 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
473 /* Set up ECC autogeneration */
474 cafe->ctl2 |= (1<<27) | (1<<30);
475 if (mtd->writesize == 2048)
476 cafe->ctl2 |= (1<<29);
479 static int cafe_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
480 const uint8_t *buf, int page, int cached, int raw)
484 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
487 chip->ecc.write_page_raw(mtd, chip, buf);
489 chip->ecc.write_page(mtd, chip, buf);
492 * Cached progamming disabled for now, Not sure if its worth the
493 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
497 if (!cached || !(chip->options & NAND_CACHEPRG)) {
499 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
500 status = chip->waitfunc(mtd, chip);
502 * See if operation failed and additional status checks are
505 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
506 status = chip->errstat(mtd, chip, FL_WRITING, status,
509 if (status & NAND_STATUS_FAIL)
512 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
513 status = chip->waitfunc(mtd, chip);
516 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
517 /* Send command to read back the data */
518 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
520 if (chip->verify_buf(mtd, buf, mtd->writesize))
526 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
531 static int __devinit cafe_nand_probe(struct pci_dev *pdev,
532 const struct pci_device_id *ent)
534 struct mtd_info *mtd;
535 struct cafe_priv *cafe;
539 err = pci_enable_device(pdev);
543 pci_set_master(pdev);
545 mtd = kzalloc(sizeof(*mtd) + sizeof(struct cafe_priv), GFP_KERNEL);
547 dev_warn(&pdev->dev, "failed to alloc mtd_info\n");
550 cafe = (void *)(&mtd[1]);
553 mtd->owner = THIS_MODULE;
556 cafe->mmio = pci_iomap(pdev, 0, 0);
558 dev_warn(&pdev->dev, "failed to iomap\n");
562 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112 + sizeof(struct nand_buffers),
563 &cafe->dmaaddr, GFP_KERNEL);
568 cafe->nand.buffers = (void *)cafe->dmabuf + 2112;
570 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
571 cafe->nand.dev_ready = cafe_device_ready;
572 cafe->nand.read_byte = cafe_read_byte;
573 cafe->nand.read_buf = cafe_read_buf;
574 cafe->nand.write_buf = cafe_write_buf;
575 cafe->nand.select_chip = cafe_select_chip;
577 cafe->nand.chip_delay = 0;
579 /* Enable the following for a flash based bad block table */
580 cafe->nand.options = NAND_USE_FLASH_BBT | NAND_NO_AUTOINCR | NAND_OWN_BUFFERS;
583 cafe->nand.options |= NAND_SKIP_BBTSCAN;
584 cafe->nand.block_bad = cafe_nand_block_bad;
587 /* Start off by resetting the NAND controller completely */
588 cafe_writel(cafe, 1, NAND_RESET);
589 cafe_writel(cafe, 0, NAND_RESET);
591 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
593 /* Timings from Marvell's test code (not verified or calculated by us) */
595 cafe_writel(cafe, 0x01010a0a, NAND_TIMING1);
596 cafe_writel(cafe, 0x24121212, NAND_TIMING2);
597 cafe_writel(cafe, 0x11000000, NAND_TIMING3);
599 cafe_writel(cafe, 0xffffffff, NAND_TIMING1);
600 cafe_writel(cafe, 0xffffffff, NAND_TIMING2);
601 cafe_writel(cafe, 0xffffffff, NAND_TIMING3);
603 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
604 err = request_irq(pdev->irq, &cafe_nand_interrupt, SA_SHIRQ, "CAFE NAND", mtd);
606 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
611 /* Disable master reset, enable NAND clock */
612 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
615 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
616 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
617 cafe_writel(cafe, 0, NAND_DMA_CTRL);
619 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
620 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
622 /* Set up DMA address */
623 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
624 if (sizeof(cafe->dmaaddr) > 4)
625 /* Shift in two parts to shut the compiler up */
626 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
628 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
630 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
631 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
633 /* Enable NAND IRQ in global IRQ mask register */
634 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
635 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
636 cafe_readl(cafe, GLOBAL_CTRL), cafe_readl(cafe, GLOBAL_IRQ_MASK));
641 memset(cafe->dmabuf, 0x5a, 2112);
642 cafe->nand.cmdfunc(mtd, NAND_CMD_READID, 0, -1);
643 cafe->nand.read_byte(mtd);
644 cafe->nand.read_byte(mtd);
645 cafe->nand.read_byte(mtd);
646 cafe->nand.read_byte(mtd);
647 cafe->nand.read_byte(mtd);
650 cafe->nand.cmdfunc(mtd, NAND_CMD_READ0, 0, 0);
651 // nand_wait_ready(mtd);
652 cafe->nand.read_byte(mtd);
653 cafe->nand.read_byte(mtd);
654 cafe->nand.read_byte(mtd);
655 cafe->nand.read_byte(mtd);
658 writel(0x84600070, cafe->mmio);
660 cafe_dev_dbg(&cafe->pdev->dev, "Status %x\n", cafe_readl(cafe, NAND_NONMEM));
662 /* Scan to find existance of the device */
663 if (nand_scan_ident(mtd, 1)) {
668 cafe->ctl2 = 1<<27; /* Reed-Solomon ECC */
669 if (mtd->writesize == 2048)
670 cafe->ctl2 |= 1<<29; /* 2KiB page size */
672 /* Set up ECC according to the type of chip we found */
673 if (mtd->writesize == 2048) {
674 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
675 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
676 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
677 } else if (mtd->writesize == 512) {
678 cafe->nand.ecc.layout = &cafe_oobinfo_512;
679 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
680 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
682 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
686 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
687 cafe->nand.ecc.size = mtd->writesize;
688 cafe->nand.ecc.bytes = 14;
689 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
690 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
691 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
692 cafe->nand.write_page = cafe_nand_write_page;
693 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
694 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
695 cafe->nand.ecc.read_page = cafe_nand_read_page;
696 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
698 err = nand_scan_tail(mtd);
702 pci_set_drvdata(pdev, mtd);
707 /* Disable NAND IRQ in global IRQ mask register */
708 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
709 free_irq(pdev->irq, mtd);
711 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
713 pci_iounmap(pdev, cafe->mmio);
720 static void __devexit cafe_nand_remove(struct pci_dev *pdev)
722 struct mtd_info *mtd = pci_get_drvdata(pdev);
723 struct cafe_priv *cafe = mtd->priv;
726 /* Disable NAND IRQ in global IRQ mask register */
727 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
728 free_irq(pdev->irq, mtd);
730 pci_iounmap(pdev, cafe->mmio);
731 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
735 static struct pci_device_id cafe_nand_tbl[] = {
736 { 0x11ab, 0x4100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MEMORY_FLASH << 8, 0xFFFF0 }
739 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
741 static struct pci_driver cafe_nand_pci_driver = {
743 .id_table = cafe_nand_tbl,
744 .probe = cafe_nand_probe,
745 .remove = __devexit_p(cafe_nand_remove),
747 .suspend = cafe_nand_suspend,
748 .resume = cafe_nand_resume,
752 static int cafe_nand_init(void)
754 return pci_register_driver(&cafe_nand_pci_driver);
757 static void cafe_nand_exit(void)
759 pci_unregister_driver(&cafe_nand_pci_driver);
761 module_init(cafe_nand_init);
762 module_exit(cafe_nand_exit);
764 MODULE_LICENSE("GPL");
765 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
766 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFE chip");
768 /* Correct ECC for 2048 bytes of 0xff:
769 41 a0 71 65 54 27 f3 93 ec a9 be ed 0b a1 */
771 /* dwmw2's B-test board, in case of completely screwing it:
772 Bad eraseblock 2394 at 0x12b40000
773 Bad eraseblock 2627 at 0x14860000
774 Bad eraseblock 3349 at 0x1a2a0000