drivers/mtd/nand/bf5xx_nand.c

   1 /* linux/drivers/mtd/nand/bf5xx_nand.c
   2  *
   3  * Copyright 2006-2008 Analog Devices Inc.
   4  *      http://blackfin.uclinux.org/
   5  *      Bryan Wu <bryan.wu@analog.com>
   6  *
   7  * Blackfin BF5xx on-chip NAND flash controller driver
   8  *
   9  * Derived from drivers/mtd/nand/s3c2410.c
  10  * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
  11  *
  12  * Derived from drivers/mtd/nand/cafe.c
  13  * Copyright © 2006 Red Hat, Inc.
  14  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
  15  *
  16  * Changelog:
  17  *      12-Jun-2007  Bryan Wu:  Initial version
  18  *      18-Jul-2007  Bryan Wu:
  19  *              - ECC_HW and ECC_SW supported
  20  *              - DMA supported in ECC_HW
  21  *              - YAFFS tested as rootfs in both ECC_HW and ECC_SW
  22  *
  23  * TODO:
  24  *      Enable JFFS2 over NAND as rootfs
  25  *
  26  * This program is free software; you can redistribute it and/or modify
  27  * it under the terms of the GNU General Public License as published by
  28  * the Free Software Foundation; either version 2 of the License, or
  29  * (at your option) any later version.
  30  *
  31  * This program is distributed in the hope that it will be useful,
  32  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34  * GNU General Public License for more details.
  35  *
  36  * You should have received a copy of the GNU General Public License
  37  * along with this program; if not, write to the Free Software
  38  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  39 */
  40
  41 #include <linux/module.h>
  42 #include <linux/types.h>
  43 #include <linux/init.h>
  44 #include <linux/kernel.h>
  45 #include <linux/string.h>
  46 #include <linux/ioport.h>
  47 #include <linux/platform_device.h>
  48 #include <linux/delay.h>
  49 #include <linux/dma-mapping.h>
  50 #include <linux/err.h>
  51 #include <linux/slab.h>
  52 #include <linux/io.h>
  53 #include <linux/bitops.h>
  54
  55 #include <linux/mtd/mtd.h>
  56 #include <linux/mtd/nand.h>
  57 #include <linux/mtd/nand_ecc.h>
  58 #include <linux/mtd/partitions.h>
  59
  60 #include <asm/blackfin.h>
  61 #include <asm/dma.h>
  62 #include <asm/cacheflush.h>
  63 #include <asm/nand.h>
  64 #include <asm/portmux.h>
  65
  66 #define DRV_NAME        "bf5xx-nand"
  67 #define DRV_VERSION     "1.2"
  68 #define DRV_AUTHOR      "Bryan Wu <bryan.wu@analog.com>"
  69 #define DRV_DESC        "BF5xx on-chip NAND FLash Controller Driver"
  70
  71 /* NFC_STAT Masks */
  72 #define NBUSY       0x01  /* Not Busy */
  73 #define WB_FULL     0x02  /* Write Buffer Full */
  74 #define PG_WR_STAT  0x04  /* Page Write Pending */
  75 #define PG_RD_STAT  0x08  /* Page Read Pending */
  76 #define WB_EMPTY    0x10  /* Write Buffer Empty */
  77
  78 /* NFC_IRQSTAT Masks */
  79 #define NBUSYIRQ    0x01  /* Not Busy IRQ */
  80 #define WB_OVF      0x02  /* Write Buffer Overflow */
  81 #define WB_EDGE     0x04  /* Write Buffer Edge Detect */
  82 #define RD_RDY      0x08  /* Read Data Ready */
  83 #define WR_DONE     0x10  /* Page Write Done */
  84
  85 /* NFC_RST Masks */
  86 #define ECC_RST     0x01  /* ECC (and NFC counters) Reset */
  87
  88 /* NFC_PGCTL Masks */
  89 #define PG_RD_START 0x01  /* Page Read Start */
  90 #define PG_WR_START 0x02  /* Page Write Start */
  91
  92 #ifdef CONFIG_MTD_NAND_BF5XX_HWECC
  93 static int hardware_ecc = 1;
  94 #else
  95 static int hardware_ecc;
  96 #endif
  97
  98 static const unsigned short bfin_nfc_pin_req[] =
  99         {P_NAND_CE,
 100          P_NAND_RB,
 101          P_NAND_D0,
 102          P_NAND_D1,
 103          P_NAND_D2,
 104          P_NAND_D3,
 105          P_NAND_D4,
 106          P_NAND_D5,
 107          P_NAND_D6,
 108          P_NAND_D7,
 109          P_NAND_WE,
 110          P_NAND_RE,
 111          P_NAND_CLE,
 112          P_NAND_ALE,
 113          0};
 114
 115 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 116 static uint8_t bbt_pattern[] = { 0xff };
 117
 118 static struct nand_bbt_descr bootrom_bbt = {
 119         .options = 0,
 120         .offs = 63,
 121         .len = 1,
 122         .pattern = bbt_pattern,
 123 };
 124
 125 static struct nand_ecclayout bootrom_ecclayout = {
 126         .eccbytes = 24,
 127         .eccpos = {
 128                 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
 129                 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
 130                 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
 131                 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
 132                 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
 133                 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
 134                 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
 135                 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
 136         },
 137         .oobfree = {
 138                 { 0x8 * 0 + 3, 5 },
 139                 { 0x8 * 1 + 3, 5 },
 140                 { 0x8 * 2 + 3, 5 },
 141                 { 0x8 * 3 + 3, 5 },
 142                 { 0x8 * 4 + 3, 5 },
 143                 { 0x8 * 5 + 3, 5 },
 144                 { 0x8 * 6 + 3, 5 },
 145                 { 0x8 * 7 + 3, 5 },
 146         }
 147 };
 148 #endif
 149
 150 /*
 151  * Data structures for bf5xx nand flash controller driver
 152  */
 153
 154 /* bf5xx nand info */
 155 struct bf5xx_nand_info {
 156         /* mtd info */
 157         struct nand_hw_control          controller;
 158         struct mtd_info                 mtd;
 159         struct nand_chip                chip;
 160
 161         /* platform info */
 162         struct bf5xx_nand_platform      *platform;
 163
 164         /* device info */
 165         struct device                   *device;
 166
 167         /* DMA stuff */
 168         struct completion               dma_completion;
 169 };
 170
 171 /*
 172  * Conversion functions
 173  */
 174 static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
 175 {
 176         return container_of(mtd, struct bf5xx_nand_info, mtd);
 177 }
 178
 179 static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
 180 {
 181         return platform_get_drvdata(pdev);
 182 }
 183
 184 static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
 185 {
 186         return pdev->dev.platform_data;
 187 }
 188
 189 /*
 190  * struct nand_chip interface function pointers
 191  */
 192
 193 /*
 194  * bf5xx_nand_hwcontrol
 195  *
 196  * Issue command and address cycles to the chip
 197  */
 198 static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 199                                    unsigned int ctrl)
 200 {
 201         if (cmd == NAND_CMD_NONE)
 202                 return;
 203
 204         while (bfin_read_NFC_STAT() & WB_FULL)
 205                 cpu_relax();
 206
 207         if (ctrl & NAND_CLE)
 208                 bfin_write_NFC_CMD(cmd);
 209         else
 210                 bfin_write_NFC_ADDR(cmd);
 211         SSYNC();
 212 }
 213
 214 /*
 215  * bf5xx_nand_devready()
 216  *
 217  * returns 0 if the nand is busy, 1 if it is ready
 218  */
 219 static int bf5xx_nand_devready(struct mtd_info *mtd)
 220 {
 221         unsigned short val = bfin_read_NFC_IRQSTAT();
 222
 223         if ((val & NBUSYIRQ) == NBUSYIRQ)
 224                 return 1;
 225         else
 226                 return 0;
 227 }
 228
 229 /*
 230  * ECC functions
 231  * These allow the bf5xx to use the controller's ECC
 232  * generator block to ECC the data as it passes through
 233  */
 234
 235 /*
 236  * ECC error correction function
 237  */
 238 static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
 239                                         u_char *read_ecc, u_char *calc_ecc)
 240 {
 241         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 242         u32 syndrome[5];
 243         u32 calced, stored;
 244         int i;
 245         unsigned short failing_bit, failing_byte;
 246         u_char data;
 247
 248         calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
 249         stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
 250
 251         syndrome[0] = (calced ^ stored);
 252
 253         /*
 254          * syndrome 0: all zero
 255          * No error in data
 256          * No action
 257          */
 258         if (!syndrome[0] || !calced || !stored)
 259                 return 0;
 260
 261         /*
 262          * sysdrome 0: only one bit is one
 263          * ECC data was incorrect
 264          * No action
 265          */
 266         if (hweight32(syndrome[0]) == 1) {
 267                 dev_err(info->device, "ECC data was incorrect!\n");
 268                 return 1;
 269         }
 270
 271         syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
 272         syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
 273         syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
 274         syndrome[4] = syndrome[2] ^ syndrome[3];
 275
 276         for (i = 0; i < 5; i++)
 277                 dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
 278
 279         dev_info(info->device,
 280                 "calced[0x%08x], stored[0x%08x]\n",
 281                 calced, stored);
 282
 283         /*
 284          * sysdrome 0: exactly 11 bits are one, each parity
 285          * and parity' pair is 1 & 0 or 0 & 1.
 286          * 1-bit correctable error
 287          * Correct the error
 288          */
 289         if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
 290                 dev_info(info->device,
 291                         "1-bit correctable error, correct it.\n");
 292                 dev_info(info->device,
 293                         "syndrome[1] 0x%08x\n", syndrome[1]);
 294
 295                 failing_bit = syndrome[1] & 0x7;
 296                 failing_byte = syndrome[1] >> 0x3;
 297                 data = *(dat + failing_byte);
 298                 data = data ^ (0x1 << failing_bit);
 299                 *(dat + failing_byte) = data;
 300
 301                 return 0;
 302         }
 303
 304         /*
 305          * sysdrome 0: random data
 306          * More than 1-bit error, non-correctable error
 307          * Discard data, mark bad block
 308          */
 309         dev_err(info->device,
 310                 "More than 1-bit error, non-correctable error.\n");
 311         dev_err(info->device,
 312                 "Please discard data, mark bad block\n");
 313
 314         return 1;
 315 }
 316
 317 static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 318                                         u_char *read_ecc, u_char *calc_ecc)
 319 {
 320         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 321         struct bf5xx_nand_platform *plat = info->platform;
 322         unsigned short page_size = (plat->page_size ? 512 : 256);
 323         int ret;
 324
 325         ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 326
 327         /* If page size is 512, correct second 256 bytes */
 328         if (page_size == 512) {
 329                 dat += 256;
 330                 read_ecc += 8;
 331                 calc_ecc += 8;
 332                 ret |= bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 333         }
 334
 335         return ret;
 336 }
 337
 338 static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 339 {
 340         return;
 341 }
 342
 343 static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
 344                 const u_char *dat, u_char *ecc_code)
 345 {
 346         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 347         struct bf5xx_nand_platform *plat = info->platform;
 348         u16 page_size = (plat->page_size ? 512 : 256);
 349         u16 ecc0, ecc1;
 350         u32 code[2];
 351         u8 *p;
 352
 353         /* first 4 bytes ECC code for 256 page size */
 354         ecc0 = bfin_read_NFC_ECC0();
 355         ecc1 = bfin_read_NFC_ECC1();
 356
 357         code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 358
 359         dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
 360
 361         /* first 3 bytes in ecc_code for 256 page size */
 362         p = (u8 *) code;
 363         memcpy(ecc_code, p, 3);
 364
 365         /* second 4 bytes ECC code for 512 page size */
 366         if (page_size == 512) {
 367                 ecc0 = bfin_read_NFC_ECC2();
 368                 ecc1 = bfin_read_NFC_ECC3();
 369                 code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 370
 371                 /* second 3 bytes in ecc_code for second 256
 372                  * bytes of 512 page size
 373                  */
 374                 p = (u8 *) (code + 1);
 375                 memcpy((ecc_code + 3), p, 3);
 376                 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
 377         }
 378
 379         return 0;
 380 }
 381
 382 /*
 383  * PIO mode for buffer writing and reading
 384  */
 385 static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 386 {
 387         int i;
 388         unsigned short val;
 389
 390         /*
 391          * Data reads are requested by first writing to NFC_DATA_RD
 392          * and then reading back from NFC_READ.
 393          */
 394         for (i = 0; i < len; i++) {
 395                 while (bfin_read_NFC_STAT() & WB_FULL)
 396                         cpu_relax();
 397
 398                 /* Contents do not matter */
 399                 bfin_write_NFC_DATA_RD(0x0000);
 400                 SSYNC();
 401
 402                 while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
 403                         cpu_relax();
 404
 405                 buf[i] = bfin_read_NFC_READ();
 406
 407                 val = bfin_read_NFC_IRQSTAT();
 408                 val |= RD_RDY;
 409                 bfin_write_NFC_IRQSTAT(val);
 410                 SSYNC();
 411         }
 412 }
 413
 414 static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
 415 {
 416         uint8_t val;
 417
 418         bf5xx_nand_read_buf(mtd, &val, 1);
 419
 420         return val;
 421 }
 422
 423 static void bf5xx_nand_write_buf(struct mtd_info *mtd,
 424                                 const uint8_t *buf, int len)
 425 {
 426         int i;
 427
 428         for (i = 0; i < len; i++) {
 429                 while (bfin_read_NFC_STAT() & WB_FULL)
 430                         cpu_relax();
 431
 432                 bfin_write_NFC_DATA_WR(buf[i]);
 433                 SSYNC();
 434         }
 435 }
 436
 437 static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 438 {
 439         int i;
 440         u16 *p = (u16 *) buf;
 441         len >>= 1;
 442
 443         /*
 444          * Data reads are requested by first writing to NFC_DATA_RD
 445          * and then reading back from NFC_READ.
 446          */
 447         bfin_write_NFC_DATA_RD(0x5555);
 448
 449         SSYNC();
 450
 451         for (i = 0; i < len; i++)
 452                 p[i] = bfin_read_NFC_READ();
 453 }
 454
 455 static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
 456                                 const uint8_t *buf, int len)
 457 {
 458         int i;
 459         u16 *p = (u16 *) buf;
 460         len >>= 1;
 461
 462         for (i = 0; i < len; i++)
 463                 bfin_write_NFC_DATA_WR(p[i]);
 464
 465         SSYNC();
 466 }
 467
 468 /*
 469  * DMA functions for buffer writing and reading
 470  */
 471 static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
 472 {
 473         struct bf5xx_nand_info *info = dev_id;
 474
 475         clear_dma_irqstat(CH_NFC);
 476         disable_dma(CH_NFC);
 477         complete(&info->dma_completion);
 478
 479         return IRQ_HANDLED;
 480 }
 481
 482 static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
 483                                 uint8_t *buf, int is_read)
 484 {
 485         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 486         struct bf5xx_nand_platform *plat = info->platform;
 487         unsigned short page_size = (plat->page_size ? 512 : 256);
 488         unsigned short val;
 489
 490         dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
 491                         mtd, buf, is_read);
 492
 493         /*
 494          * Before starting a dma transfer, be sure to invalidate/flush
 495          * the cache over the address range of your DMA buffer to
 496          * prevent cache coherency problems. Otherwise very subtle bugs
 497          * can be introduced to your driver.
 498          */
 499         if (is_read)
 500                 invalidate_dcache_range((unsigned int)buf,
 501                                 (unsigned int)(buf + page_size));
 502         else
 503                 flush_dcache_range((unsigned int)buf,
 504                                 (unsigned int)(buf + page_size));
 505
 506         /*
 507          * This register must be written before each page is
 508          * transferred to generate the correct ECC register
 509          * values.
 510          */
 511         bfin_write_NFC_RST(ECC_RST);
 512         SSYNC();
 513
 514         disable_dma(CH_NFC);
 515         clear_dma_irqstat(CH_NFC);
 516
 517         /* setup DMA register with Blackfin DMA API */
 518         set_dma_config(CH_NFC, 0x0);
 519         set_dma_start_addr(CH_NFC, (unsigned long) buf);
 520
 521         /* The DMAs have different size on BF52x and BF54x */
 522 #ifdef CONFIG_BF52x
 523         set_dma_x_count(CH_NFC, (page_size >> 1));
 524         set_dma_x_modify(CH_NFC, 2);
 525         val = DI_EN | WDSIZE_16;
 526 #endif
 527
 528 #ifdef CONFIG_BF54x
 529         set_dma_x_count(CH_NFC, (page_size >> 2));
 530         set_dma_x_modify(CH_NFC, 4);
 531         val = DI_EN | WDSIZE_32;
 532 #endif
 533         /* setup write or read operation */
 534         if (is_read)
 535                 val |= WNR;
 536         set_dma_config(CH_NFC, val);
 537         enable_dma(CH_NFC);
 538
 539         /* Start PAGE read/write operation */
 540         if (is_read)
 541                 bfin_write_NFC_PGCTL(PG_RD_START);
 542         else
 543                 bfin_write_NFC_PGCTL(PG_WR_START);
 544         wait_for_completion(&info->dma_completion);
 545 }
 546
 547 static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
 548                                         uint8_t *buf, int len)
 549 {
 550         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 551         struct bf5xx_nand_platform *plat = info->platform;
 552         unsigned short page_size = (plat->page_size ? 512 : 256);
 553
 554         dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
 555
 556         if (len == page_size)
 557                 bf5xx_nand_dma_rw(mtd, buf, 1);
 558         else
 559                 bf5xx_nand_read_buf(mtd, buf, len);
 560 }
 561
 562 static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
 563                                 const uint8_t *buf, int len)
 564 {
 565         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 566         struct bf5xx_nand_platform *plat = info->platform;
 567         unsigned short page_size = (plat->page_size ? 512 : 256);
 568
 569         dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
 570
 571         if (len == page_size)
 572                 bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
 573         else
 574                 bf5xx_nand_write_buf(mtd, buf, len);
 575 }
 576
 577 /*
 578  * System initialization functions
 579  */
 580 static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
 581 {
 582         int ret;
 583
 584         /* Do not use dma */
 585         if (!hardware_ecc)
 586                 return 0;
 587
 588         init_completion(&info->dma_completion);
 589
 590         /* Request NFC DMA channel */
 591         ret = request_dma(CH_NFC, "BF5XX NFC driver");
 592         if (ret < 0) {
 593                 dev_err(info->device, " unable to get DMA channel\n");
 594                 return ret;
 595         }
 596
 597 #ifdef CONFIG_BF54x
 598         /* Setup DMAC1 channel mux for NFC which shared with SDH */
 599         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1);
 600         SSYNC();
 601 #endif
 602
 603         set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info);
 604
 605         /* Turn off the DMA channel first */
 606         disable_dma(CH_NFC);
 607         return 0;
 608 }
 609
 610 static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info)
 611 {
 612         /* Free NFC DMA channel */
 613         if (hardware_ecc)
 614                 free_dma(CH_NFC);
 615 }
 616
 617 /*
 618  * BF5XX NFC hardware initialization
 619  *  - pin mux setup
 620  *  - clear interrupt status
 621  */
 622 static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
 623 {
 624         int err = 0;
 625         unsigned short val;
 626         struct bf5xx_nand_platform *plat = info->platform;
 627
 628         /* setup NFC_CTL register */
 629         dev_info(info->device,
 630                 "page_size=%d, data_width=%d, wr_dly=%d, rd_dly=%d\n",
 631                 (plat->page_size ? 512 : 256),
 632                 (plat->data_width ? 16 : 8),
 633                 plat->wr_dly, plat->rd_dly);
 634
 635         val = (plat->page_size << NFC_PG_SIZE_OFFSET) |
 636                 (plat->data_width << NFC_NWIDTH_OFFSET) |
 637                 (plat->rd_dly << NFC_RDDLY_OFFSET) |
 638                 (plat->rd_dly << NFC_WRDLY_OFFSET);
 639         dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
 640
 641         bfin_write_NFC_CTL(val);
 642         SSYNC();
 643
 644         /* clear interrupt status */
 645         bfin_write_NFC_IRQMASK(0x0);
 646         SSYNC();
 647         val = bfin_read_NFC_IRQSTAT();
 648         bfin_write_NFC_IRQSTAT(val);
 649         SSYNC();
 650
 651         /* DMA initialization  */
 652         if (bf5xx_nand_dma_init(info))
 653                 err = -ENXIO;
 654
 655         return err;
 656 }
 657
 658 /*
 659  * Device management interface
 660  */
 661 static int __devinit bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
 662 {
 663         struct mtd_info *mtd = &info->mtd;
 664
 665 #ifdef CONFIG_MTD_PARTITIONS
 666         struct mtd_partition *parts = info->platform->partitions;
 667         int nr = info->platform->nr_partitions;
 668
 669         return add_mtd_partitions(mtd, parts, nr);
 670 #else
 671         return add_mtd_device(mtd);
 672 #endif
 673 }
 674
 675 static int __devexit bf5xx_nand_remove(struct platform_device *pdev)
 676 {
 677         struct bf5xx_nand_info *info = to_nand_info(pdev);
 678         struct mtd_info *mtd = NULL;
 679
 680         platform_set_drvdata(pdev, NULL);
 681
 682         /* first thing we need to do is release all our mtds
 683          * and their partitions, then go through freeing the
 684          * resources used
 685          */
 686         mtd = &info->mtd;
 687         if (mtd) {
 688                 nand_release(mtd);
 689                 kfree(mtd);
 690         }
 691
 692         peripheral_free_list(bfin_nfc_pin_req);
 693         bf5xx_nand_dma_remove(info);
 694
 695         /* free the common resources */
 696         kfree(info);
 697
 698         return 0;
 699 }
 700
 701 /*
 702  * bf5xx_nand_probe
 703  *
 704  * called by device layer when it finds a device matching
 705  * one our driver can handled. This code checks to see if
 706  * it can allocate all necessary resources then calls the
 707  * nand layer to look for devices
 708  */
 709 static int __devinit bf5xx_nand_probe(struct platform_device *pdev)
 710 {
 711         struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
 712         struct bf5xx_nand_info *info = NULL;
 713         struct nand_chip *chip = NULL;
 714         struct mtd_info *mtd = NULL;
 715         int err = 0;
 716
 717         dev_dbg(&pdev->dev, "(%p)\n", pdev);
 718
 719         if (!plat) {
 720                 dev_err(&pdev->dev, "no platform specific information\n");
 721                 return -EINVAL;
 722         }
 723
 724         if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
 725                 dev_err(&pdev->dev, "requesting Peripherals failed\n");
 726                 return -EFAULT;
 727         }
 728
 729         info = kzalloc(sizeof(*info), GFP_KERNEL);
 730         if (info == NULL) {
 731                 dev_err(&pdev->dev, "no memory for flash info\n");
 732                 err = -ENOMEM;
 733                 goto out_err_kzalloc;
 734         }
 735
 736         platform_set_drvdata(pdev, info);
 737
 738         spin_lock_init(&info->controller.lock);
 739         init_waitqueue_head(&info->controller.wq);
 740
 741         info->device     = &pdev->dev;
 742         info->platform   = plat;
 743
 744         /* initialise chip data struct */
 745         chip = &info->chip;
 746
 747         if (plat->data_width)
 748                 chip->options |= NAND_BUSWIDTH_16;
 749
 750         chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
 751
 752         chip->read_buf = (plat->data_width) ?
 753                 bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
 754         chip->write_buf = (plat->data_width) ?
 755                 bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
 756
 757         chip->read_byte    = bf5xx_nand_read_byte;
 758
 759         chip->cmd_ctrl     = bf5xx_nand_hwcontrol;
 760         chip->dev_ready    = bf5xx_nand_devready;
 761
 762         chip->priv         = &info->mtd;
 763         chip->controller   = &info->controller;
 764
 765         chip->IO_ADDR_R    = (void __iomem *) NFC_READ;
 766         chip->IO_ADDR_W    = (void __iomem *) NFC_DATA_WR;
 767
 768         chip->chip_delay   = 0;
 769
 770         /* initialise mtd info data struct */
 771         mtd             = &info->mtd;
 772         mtd->priv       = chip;
 773         mtd->owner      = THIS_MODULE;
 774
 775         /* initialise the hardware */
 776         err = bf5xx_nand_hw_init(info);
 777         if (err)
 778                 goto out_err_hw_init;
 779
 780         /* setup hardware ECC data struct */
 781         if (hardware_ecc) {
 782 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 783                 chip->badblock_pattern = &bootrom_bbt;
 784                 chip->ecc.layout = &bootrom_ecclayout;
 785 #endif
 786
 787                 if (plat->page_size == NFC_PG_SIZE_256) {
 788                         chip->ecc.bytes = 3;
 789                         chip->ecc.size = 256;
 790                 } else if (plat->page_size == NFC_PG_SIZE_512) {
 791                         chip->ecc.bytes = 6;
 792                         chip->ecc.size = 512;
 793                 }
 794
 795                 chip->read_buf      = bf5xx_nand_dma_read_buf;
 796                 chip->write_buf     = bf5xx_nand_dma_write_buf;
 797                 chip->ecc.calculate = bf5xx_nand_calculate_ecc;
 798                 chip->ecc.correct   = bf5xx_nand_correct_data;
 799                 chip->ecc.mode      = NAND_ECC_HW;
 800                 chip->ecc.hwctl     = bf5xx_nand_enable_hwecc;
 801         } else {
 802                 chip->ecc.mode      = NAND_ECC_SOFT;
 803         }
 804
 805         /* scan hardware nand chip and setup mtd info data struct */
 806         if (nand_scan(mtd, 1)) {
 807                 err = -ENXIO;
 808                 goto out_err_nand_scan;
 809         }
 810
 811         /* add NAND partition */
 812         bf5xx_nand_add_partition(info);
 813
 814         dev_dbg(&pdev->dev, "initialised ok\n");
 815         return 0;
 816
 817 out_err_nand_scan:
 818         bf5xx_nand_dma_remove(info);
 819 out_err_hw_init:
 820         platform_set_drvdata(pdev, NULL);
 821         kfree(info);
 822 out_err_kzalloc:
 823         peripheral_free_list(bfin_nfc_pin_req);
 824
 825         return err;
 826 }
 827
 828 /* PM Support */
 829 #ifdef CONFIG_PM
 830
 831 static int bf5xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
 832 {
 833         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
 834
 835         return 0;
 836 }
 837
 838 static int bf5xx_nand_resume(struct platform_device *dev)
 839 {
 840         struct bf5xx_nand_info *info = platform_get_drvdata(dev);
 841
 842         return 0;
 843 }
 844
 845 #else
 846 #define bf5xx_nand_suspend NULL
 847 #define bf5xx_nand_resume NULL
 848 #endif
 849
 850 /* driver device registration */
 851 static struct platform_driver bf5xx_nand_driver = {
 852         .probe          = bf5xx_nand_probe,
 853         .remove         = __devexit_p(bf5xx_nand_remove),
 854         .suspend        = bf5xx_nand_suspend,
 855         .resume         = bf5xx_nand_resume,
 856         .driver         = {
 857                 .name   = DRV_NAME,
 858                 .owner  = THIS_MODULE,
 859         },
 860 };
 861
 862 static int __init bf5xx_nand_init(void)
 863 {
 864         printk(KERN_INFO "%s, Version %s (c) 2007 Analog Devices, Inc.\n",
 865                 DRV_DESC, DRV_VERSION);
 866
 867         return platform_driver_register(&bf5xx_nand_driver);
 868 }
 869
 870 static void __exit bf5xx_nand_exit(void)
 871 {
 872         platform_driver_unregister(&bf5xx_nand_driver);
 873 }
 874
 875 module_init(bf5xx_nand_init);
 876 module_exit(bf5xx_nand_exit);
 877
 878 MODULE_LICENSE("GPL");
 879 MODULE_AUTHOR(DRV_AUTHOR);
 880 MODULE_DESCRIPTION(DRV_DESC);
 881 MODULE_ALIAS("platform:" DRV_NAME);