drivers/mtd/devices/ps3vram.c

   1 /**
   2  * ps3vram - Use extra PS3 video ram as MTD block device.
   3  *
   4  * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
   5  * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
   6  */
   7
   8 #include <linux/io.h>
   9 #include <linux/init.h>
  10 #include <linux/kernel.h>
  11 #include <linux/list.h>
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/slab.h>
  15 #include <linux/version.h>
  16 #include <linux/gfp.h>
  17 #include <linux/delay.h>
  18 #include <linux/mtd/mtd.h>
  19
  20 #include <asm/lv1call.h>
  21 #include <asm/ps3.h>
  22
  23 #define DEVICE_NAME             "ps3vram"
  24
  25 #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  26 #define XDR_IOIF 0x0c000000
  27
  28 #define FIFO_BASE XDR_IOIF
  29 #define FIFO_SIZE (64 * 1024)
  30
  31 #define DMA_PAGE_SIZE (4 * 1024)
  32
  33 #define CACHE_PAGE_SIZE (256 * 1024)
  34 #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  35
  36 #define CACHE_OFFSET CACHE_PAGE_SIZE
  37 #define FIFO_OFFSET 0
  38
  39 #define CTRL_PUT 0x10
  40 #define CTRL_GET 0x11
  41 #define CTRL_TOP 0x15
  42
  43 #define UPLOAD_SUBCH    1
  44 #define DOWNLOAD_SUBCH  2
  45
  46 #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN    0x0000030c
  47 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY       0x00000104
  48
  49 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
  50
  51 struct mtd_info ps3vram_mtd;
  52
  53 #define CACHE_PAGE_PRESENT 1
  54 #define CACHE_PAGE_DIRTY   2
  55
  56 struct ps3vram_tag {
  57         unsigned int address;
  58         unsigned int flags;
  59 };
  60
  61 struct ps3vram_cache {
  62         unsigned int page_count;
  63         unsigned int page_size;
  64         struct ps3vram_tag *tags;
  65 };
  66
  67 struct ps3vram_priv {
  68         uint64_t memory_handle;
  69         uint64_t context_handle;
  70         uint8_t *base;
  71         uint32_t *ctrl;
  72         uint32_t *reports;
  73         uint8_t *xdr_buf;
  74
  75         uint32_t *fifo_base;
  76         uint32_t *fifo_ptr;
  77
  78         struct device *dev;
  79         struct ps3vram_cache cache;
  80
  81         /* Used to serialize cache/DMA operations */
  82         struct mutex lock;
  83 };
  84
  85 #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  86 #define DMA_NOTIFIER_OFFSET_BASE 0x1000     /* first DMA notifier offset */
  87 #define DMA_NOTIFIER_SIZE        0x40
  88 #define NOTIFIER 7      /* notifier used for completion report */
  89
  90 /* A trailing '-' means to subtract off ps3fb_videomemory.size */
  91 char *size = "256M-";
  92 module_param(size, charp, 0);
  93 MODULE_PARM_DESC(size, "memory size");
  94
  95 static inline uint32_t *ps3vram_get_notifier(uint32_t *reports, int notifier)
  96 {
  97         return (void *) reports +
  98                 DMA_NOTIFIER_OFFSET_BASE +
  99                 DMA_NOTIFIER_SIZE * notifier;
 100 }
 101
 102 static void ps3vram_notifier_reset(struct mtd_info *mtd)
 103 {
 104         int i;
 105         struct ps3vram_priv *priv = mtd->priv;
 106         uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
 107         for (i = 0; i < 4; i++)
 108                 notify[i] = 0xffffffff;
 109 }
 110
 111 static int ps3vram_notifier_wait(struct mtd_info *mtd, int timeout_ms)
 112 {
 113         struct ps3vram_priv *priv = mtd->priv;
 114         uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
 115
 116         timeout_ms *= 1000;
 117
 118         do {
 119                 if (notify[3] == 0)
 120                         return 0;
 121
 122                 if (timeout_ms)
 123                         udelay(1);
 124         } while (timeout_ms--);
 125
 126         return -1;
 127 }
 128
 129 static void ps3vram_init_ring(struct mtd_info *mtd)
 130 {
 131         struct ps3vram_priv *priv = mtd->priv;
 132
 133         priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
 134         priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
 135 }
 136
 137 static int ps3vram_wait_ring(struct mtd_info *mtd, int timeout)
 138 {
 139         struct ps3vram_priv *priv = mtd->priv;
 140
 141         /* wait until setup commands are processed */
 142         timeout *= 1000;
 143         while (--timeout) {
 144                 if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
 145                         break;
 146                 udelay(1);
 147         }
 148         if (timeout == 0) {
 149                 dev_dbg(priv->dev, "%s:%d: FIFO timeout (%08x/%08x/%08x)\n",
 150                         __func__, __LINE__, priv->ctrl[CTRL_PUT],
 151                         priv->ctrl[CTRL_GET], priv->ctrl[CTRL_TOP]);
 152                 return -ETIMEDOUT;
 153         }
 154
 155         return 0;
 156 }
 157
 158 static inline void ps3vram_out_ring(struct ps3vram_priv *priv, uint32_t data)
 159 {
 160         *(priv->fifo_ptr)++ = data;
 161 }
 162
 163 static inline void ps3vram_begin_ring(struct ps3vram_priv *priv, uint32_t chan,
 164                                       uint32_t tag, uint32_t size)
 165 {
 166         ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
 167 }
 168
 169 static void ps3vram_rewind_ring(struct mtd_info *mtd)
 170 {
 171         struct ps3vram_priv *priv = mtd->priv;
 172         u64 status;
 173
 174         ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
 175
 176         priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
 177
 178         /* asking the HV for a blit will kick the fifo */
 179         status = lv1_gpu_context_attribute(priv->context_handle,
 180                                            L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
 181                                            0, 0, 0, 0);
 182         if (status)
 183                 dev_err(priv->dev, "%s:%d: lv1_gpu_context_attribute failed\n",
 184                         __func__, __LINE__);
 185
 186         priv->fifo_ptr = priv->fifo_base;
 187 }
 188
 189 static void ps3vram_fire_ring(struct mtd_info *mtd)
 190 {
 191         struct ps3vram_priv *priv = mtd->priv;
 192         u64 status;
 193
 194         mutex_lock(&ps3_gpu_mutex);
 195
 196         priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
 197                 (priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t);
 198
 199         /* asking the HV for a blit will kick the fifo */
 200         status = lv1_gpu_context_attribute(priv->context_handle,
 201                                            L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
 202                                            0, 0, 0, 0);
 203         if (status)
 204                 dev_err(priv->dev, "%s:%d: lv1_gpu_context_attribute failed\n",
 205                         __func__, __LINE__);
 206
 207         if ((priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t) >
 208             FIFO_SIZE - 1024) {
 209                 dev_dbg(priv->dev, "%s:%d: fifo full, rewinding\n", __func__,
 210                         __LINE__);
 211                 ps3vram_wait_ring(mtd, 200);
 212                 ps3vram_rewind_ring(mtd);
 213         }
 214
 215         mutex_unlock(&ps3_gpu_mutex);
 216 }
 217
 218 static void ps3vram_bind(struct mtd_info *mtd)
 219 {
 220         struct ps3vram_priv *priv = mtd->priv;
 221
 222         ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
 223         ps3vram_out_ring(priv, 0x31337303);
 224         ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
 225         ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
 226         ps3vram_out_ring(priv, 0xfeed0001);     /* DMA system RAM instance */
 227         ps3vram_out_ring(priv, 0xfeed0000);     /* DMA video RAM instance */
 228
 229         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
 230         ps3vram_out_ring(priv, 0x3137c0de);
 231         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
 232         ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
 233         ps3vram_out_ring(priv, 0xfeed0000);     /* DMA video RAM instance */
 234         ps3vram_out_ring(priv, 0xfeed0001);     /* DMA system RAM instance */
 235
 236         ps3vram_fire_ring(mtd);
 237 }
 238
 239 static int ps3vram_upload(struct mtd_info *mtd, unsigned int src_offset,
 240                           unsigned int dst_offset, int len, int count)
 241 {
 242         struct ps3vram_priv *priv = mtd->priv;
 243
 244         ps3vram_begin_ring(priv, UPLOAD_SUBCH,
 245                            NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 246         ps3vram_out_ring(priv, XDR_IOIF + src_offset);
 247         ps3vram_out_ring(priv, dst_offset);
 248         ps3vram_out_ring(priv, len);
 249         ps3vram_out_ring(priv, len);
 250         ps3vram_out_ring(priv, len);
 251         ps3vram_out_ring(priv, count);
 252         ps3vram_out_ring(priv, (1 << 8) | 1);
 253         ps3vram_out_ring(priv, 0);
 254
 255         ps3vram_notifier_reset(mtd);
 256         ps3vram_begin_ring(priv, UPLOAD_SUBCH,
 257                            NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
 258         ps3vram_out_ring(priv, 0);
 259         ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
 260         ps3vram_out_ring(priv, 0);
 261         ps3vram_fire_ring(mtd);
 262         if (ps3vram_notifier_wait(mtd, 200) < 0) {
 263                 dev_dbg(priv->dev, "%s:%d: notifier timeout\n", __func__,
 264                         __LINE__);
 265                 return -1;
 266         }
 267
 268         return 0;
 269 }
 270
 271 static int ps3vram_download(struct mtd_info *mtd, unsigned int src_offset,
 272                             unsigned int dst_offset, int len, int count)
 273 {
 274         struct ps3vram_priv *priv = mtd->priv;
 275
 276         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
 277                            NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 278         ps3vram_out_ring(priv, src_offset);
 279         ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
 280         ps3vram_out_ring(priv, len);
 281         ps3vram_out_ring(priv, len);
 282         ps3vram_out_ring(priv, len);
 283         ps3vram_out_ring(priv, count);
 284         ps3vram_out_ring(priv, (1 << 8) | 1);
 285         ps3vram_out_ring(priv, 0);
 286
 287         ps3vram_notifier_reset(mtd);
 288         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
 289                            NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
 290         ps3vram_out_ring(priv, 0);
 291         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
 292         ps3vram_out_ring(priv, 0);
 293         ps3vram_fire_ring(mtd);
 294         if (ps3vram_notifier_wait(mtd, 200) < 0) {
 295                 dev_dbg(priv->dev, "%s:%d: notifier timeout\n", __func__,
 296                         __LINE__);
 297                 return -1;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static void ps3vram_cache_evict(struct mtd_info *mtd, int entry)
 304 {
 305         struct ps3vram_priv *priv = mtd->priv;
 306         struct ps3vram_cache *cache = &priv->cache;
 307
 308         if (cache->tags[entry].flags & CACHE_PAGE_DIRTY) {
 309                 dev_dbg(priv->dev, "%s:%d: flushing %d : 0x%08x\n", __func__,
 310                         __LINE__, entry, cache->tags[entry].address);
 311                 if (ps3vram_upload(mtd,
 312                                    CACHE_OFFSET + entry * cache->page_size,
 313                                    cache->tags[entry].address,
 314                                    DMA_PAGE_SIZE,
 315                                    cache->page_size / DMA_PAGE_SIZE) < 0) {
 316                         dev_dbg(priv->dev, "%s:%d: failed to upload from "
 317                                 "0x%x to 0x%x size 0x%x\n", __func__, __LINE__,
 318                                 entry * cache->page_size,
 319                                 cache->tags[entry].address, cache->page_size);
 320                 }
 321                 cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
 322         }
 323 }
 324
 325 static void ps3vram_cache_load(struct mtd_info *mtd, int entry,
 326                                unsigned int address)
 327 {
 328         struct ps3vram_priv *priv = mtd->priv;
 329         struct ps3vram_cache *cache = &priv->cache;
 330
 331         dev_dbg(priv->dev, "%s:%d: fetching %d : 0x%08x\n", __func__, __LINE__,
 332                 entry, address);
 333         if (ps3vram_download(mtd,
 334                              address,
 335                              CACHE_OFFSET + entry * cache->page_size,
 336                              DMA_PAGE_SIZE,
 337                              cache->page_size / DMA_PAGE_SIZE) < 0) {
 338                 dev_err(priv->dev, "%s:%d: failed to download from "
 339                         "0x%x to 0x%x size 0x%x\n", __func__, __LINE__, address,
 340                         entry * cache->page_size, cache->page_size);
 341         }
 342
 343         cache->tags[entry].address = address;
 344         cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
 345 }
 346
 347
 348 static void ps3vram_cache_flush(struct mtd_info *mtd)
 349 {
 350         struct ps3vram_priv *priv = mtd->priv;
 351         struct ps3vram_cache *cache = &priv->cache;
 352         int i;
 353
 354         dev_dbg(priv->dev, "%s:%d: FLUSH\n", __func__, __LINE__);
 355         for (i = 0; i < cache->page_count; i++) {
 356                 ps3vram_cache_evict(mtd, i);
 357                 cache->tags[i].flags = 0;
 358         }
 359 }
 360
 361 static unsigned int ps3vram_cache_match(struct mtd_info *mtd, loff_t address)
 362 {
 363         struct ps3vram_priv *priv = mtd->priv;
 364         struct ps3vram_cache *cache = &priv->cache;
 365         unsigned int base;
 366         unsigned int offset;
 367         int i;
 368         static int counter;
 369
 370         offset = (unsigned int) (address & (cache->page_size - 1));
 371         base = (unsigned int) (address - offset);
 372
 373         /* fully associative check */
 374         for (i = 0; i < cache->page_count; i++) {
 375                 if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
 376                     cache->tags[i].address == base) {
 377                         dev_dbg(priv->dev, "%s:%d: found entry %d : 0x%08x\n",
 378                                 __func__, __LINE__, i, cache->tags[i].address);
 379                         return i;
 380                 }
 381         }
 382
 383         /* choose a random entry */
 384         i = (jiffies + (counter++)) % cache->page_count;
 385         dev_dbg(priv->dev, "%s:%d: using entry %d\n", __func__, __LINE__, i);
 386
 387         ps3vram_cache_evict(mtd, i);
 388         ps3vram_cache_load(mtd, i, base);
 389
 390         return i;
 391 }
 392
 393 static int ps3vram_cache_init(struct mtd_info *mtd)
 394 {
 395         struct ps3vram_priv *priv = mtd->priv;
 396
 397         priv->cache.page_count = CACHE_PAGE_COUNT;
 398         priv->cache.page_size = CACHE_PAGE_SIZE;
 399         priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
 400                                    CACHE_PAGE_COUNT, GFP_KERNEL);
 401         if (priv->cache.tags == NULL) {
 402                 dev_err(priv->dev, "%s:%d: could not allocate cache tags\n",
 403                         __func__, __LINE__);
 404                 return -ENOMEM;
 405         }
 406
 407         dev_info(priv->dev, "created ram cache: %d entries, %d KiB each\n",
 408                 CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024);
 409
 410         return 0;
 411 }
 412
 413 static void ps3vram_cache_cleanup(struct mtd_info *mtd)
 414 {
 415         struct ps3vram_priv *priv = mtd->priv;
 416
 417         ps3vram_cache_flush(mtd);
 418         kfree(priv->cache.tags);
 419 }
 420
 421 static int ps3vram_erase(struct mtd_info *mtd, struct erase_info *instr)
 422 {
 423         struct ps3vram_priv *priv = mtd->priv;
 424
 425         if (instr->addr + instr->len > mtd->size)
 426                 return -EINVAL;
 427
 428         mutex_lock(&priv->lock);
 429
 430         ps3vram_cache_flush(mtd);
 431
 432         /* Set bytes to 0xFF */
 433         memset(priv->base + instr->addr, 0xFF, instr->len);
 434
 435         mutex_unlock(&priv->lock);
 436
 437         instr->state = MTD_ERASE_DONE;
 438         mtd_erase_callback(instr);
 439
 440         return 0;
 441 }
 442
 443 static int ps3vram_read(struct mtd_info *mtd, loff_t from, size_t len,
 444                         size_t *retlen, u_char *buf)
 445 {
 446         struct ps3vram_priv *priv = mtd->priv;
 447         unsigned int cached, count;
 448
 449         dev_dbg(priv->dev, "%s:%d: from=0x%08x len=0x%zx\n", __func__, __LINE__,
 450                 (unsigned int)from, len);
 451
 452         if (from >= mtd->size)
 453                 return -EINVAL;
 454
 455         if (len > mtd->size - from)
 456                 len = mtd->size - from;
 457
 458         /* Copy from vram to buf */
 459         count = len;
 460         while (count) {
 461                 unsigned int offset, avail;
 462                 unsigned int entry;
 463
 464                 offset = (unsigned int) (from & (priv->cache.page_size - 1));
 465                 avail  = priv->cache.page_size - offset;
 466
 467                 mutex_lock(&priv->lock);
 468
 469                 entry = ps3vram_cache_match(mtd, from);
 470                 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
 471
 472                 dev_dbg(priv->dev, "%s:%d: from=%08x cached=%08x offset=%08x "
 473                         "avail=%08x count=%08x\n", __func__, __LINE__,
 474                         (unsigned int)from, cached, offset, avail, count);
 475
 476                 if (avail > count)
 477                         avail = count;
 478                 memcpy(buf, priv->xdr_buf + cached, avail);
 479
 480                 mutex_unlock(&priv->lock);
 481
 482                 buf += avail;
 483                 count -= avail;
 484                 from += avail;
 485         }
 486
 487         *retlen = len;
 488         return 0;
 489 }
 490
 491 static int ps3vram_write(struct mtd_info *mtd, loff_t to, size_t len,
 492                          size_t *retlen, const u_char *buf)
 493 {
 494         struct ps3vram_priv *priv = mtd->priv;
 495         unsigned int cached, count;
 496
 497         if (to >= mtd->size)
 498                 return -EINVAL;
 499
 500         if (len > mtd->size - to)
 501                 len = mtd->size - to;
 502
 503         /* Copy from buf to vram */
 504         count = len;
 505         while (count) {
 506                 unsigned int offset, avail;
 507                 unsigned int entry;
 508
 509                 offset = (unsigned int) (to & (priv->cache.page_size - 1));
 510                 avail  = priv->cache.page_size - offset;
 511
 512                 mutex_lock(&priv->lock);
 513
 514                 entry = ps3vram_cache_match(mtd, to);
 515                 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
 516
 517                 dev_dbg(priv->dev, "%s:%d: to=%08x cached=%08x offset=%08x "
 518                         "avail=%08x count=%08x\n", __func__, __LINE__,
 519                         (unsigned int)to, cached, offset, avail, count);
 520
 521                 if (avail > count)
 522                         avail = count;
 523                 memcpy(priv->xdr_buf + cached, buf, avail);
 524
 525                 priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
 526
 527                 mutex_unlock(&priv->lock);
 528
 529                 buf += avail;
 530                 count -= avail;
 531                 to += avail;
 532         }
 533
 534         *retlen = len;
 535         return 0;
 536 }
 537
 538 static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
 539 {
 540         struct ps3vram_priv *priv;
 541         uint64_t status;
 542         uint64_t ddr_lpar, ctrl_lpar, info_lpar, reports_lpar;
 543         int64_t ddr_size;
 544         uint64_t reports_size;
 545         int ret = -ENOMEM;
 546         char *rest;
 547
 548         ret = -EIO;
 549         ps3vram_mtd.priv = kzalloc(sizeof(struct ps3vram_priv), GFP_KERNEL);
 550         if (!ps3vram_mtd.priv)
 551                 goto out;
 552         priv = ps3vram_mtd.priv;
 553
 554         mutex_init(&priv->lock);
 555         priv->dev = &dev->core;
 556
 557         /* Allocate XDR buffer (1MiB aligned) */
 558         priv->xdr_buf = (uint8_t *) __get_free_pages(GFP_KERNEL,
 559                                                      get_order(XDR_BUF_SIZE));
 560         if (priv->xdr_buf == NULL) {
 561                 dev_dbg(&dev->core, "%s:%d: could not allocate XDR buffer\n",
 562                         __func__, __LINE__);
 563                 ret = -ENOMEM;
 564                 goto out_free_priv;
 565         }
 566
 567         /* Put FIFO at begginning of XDR buffer */
 568         priv->fifo_base = (uint32_t *) (priv->xdr_buf + FIFO_OFFSET);
 569         priv->fifo_ptr = priv->fifo_base;
 570
 571         /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
 572         if (ps3_open_hv_device(dev)) {
 573                 dev_err(&dev->core, "%s:%d: ps3_open_hv_device failed\n",
 574                         __func__, __LINE__);
 575                 ret = -EAGAIN;
 576                 goto out_close_gpu;
 577         }
 578
 579         /* Request memory */
 580         status = -1;
 581         ddr_size = memparse(size, &rest);
 582         if (*rest == '-')
 583                 ddr_size -= ps3fb_videomemory.size;
 584         ddr_size = ALIGN(ddr_size, 1024*1024);
 585         if (ddr_size <= 0) {
 586                 dev_err(&dev->core, "%s:%d: specified size is too small\n",
 587                         __func__, __LINE__);
 588                 ret = -EINVAL;
 589                 goto out_close_gpu;
 590         }
 591
 592         while (ddr_size > 0) {
 593                 status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
 594                                                  &priv->memory_handle,
 595                                                  &ddr_lpar);
 596                 if (status == 0)
 597                         break;
 598                 ddr_size -= 1024*1024;
 599         }
 600         if (status != 0 || ddr_size <= 0) {
 601                 dev_err(&dev->core, "%s:%d: lv1_gpu_memory_allocate failed\n",
 602                         __func__, __LINE__);
 603                 ret = -ENOMEM;
 604                 goto out_free_xdr_buf;
 605         }
 606
 607         /* Request context */
 608         status = lv1_gpu_context_allocate(priv->memory_handle,
 609                                           0,
 610                                           &priv->context_handle,
 611                                           &ctrl_lpar,
 612                                           &info_lpar,
 613                                           &reports_lpar,
 614                                           &reports_size);
 615         if (status) {
 616                 dev_err(&dev->core, "%s:%d: lv1_gpu_context_allocate failed\n",
 617                         __func__, __LINE__);
 618                 ret = -ENOMEM;
 619                 goto out_free_memory;
 620         }
 621
 622         /* Map XDR buffer to RSX */
 623         status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
 624                                        ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
 625                                        XDR_BUF_SIZE, 0);
 626         if (status) {
 627                 dev_err(&dev->core, "%s:%d: lv1_gpu_context_iomap failed\n",
 628                         __func__, __LINE__);
 629                 ret = -ENOMEM;
 630                 goto out_free_context;
 631         }
 632
 633         priv->base = ioremap(ddr_lpar, ddr_size);
 634         if (!priv->base) {
 635                 dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__,
 636                         __LINE__);
 637                 ret = -ENOMEM;
 638                 goto out_free_context;
 639         }
 640
 641         priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
 642         if (!priv->ctrl) {
 643                 dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__,
 644                         __LINE__);
 645                 ret = -ENOMEM;
 646                 goto out_unmap_vram;
 647         }
 648
 649         priv->reports = ioremap(reports_lpar, reports_size);
 650         if (!priv->reports) {
 651                 dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__,
 652                         __LINE__);
 653                 ret = -ENOMEM;
 654                 goto out_unmap_ctrl;
 655         }
 656
 657         mutex_lock(&ps3_gpu_mutex);
 658         ps3vram_init_ring(&ps3vram_mtd);
 659         mutex_unlock(&ps3_gpu_mutex);
 660
 661         ps3vram_mtd.name = "ps3vram";
 662         ps3vram_mtd.size = ddr_size;
 663         ps3vram_mtd.flags = MTD_CAP_RAM;
 664         ps3vram_mtd.erase = ps3vram_erase;
 665         ps3vram_mtd.point = NULL;
 666         ps3vram_mtd.unpoint = NULL;
 667         ps3vram_mtd.read = ps3vram_read;
 668         ps3vram_mtd.write = ps3vram_write;
 669         ps3vram_mtd.owner = THIS_MODULE;
 670         ps3vram_mtd.type = MTD_RAM;
 671         ps3vram_mtd.erasesize = CACHE_PAGE_SIZE;
 672         ps3vram_mtd.writesize = 1;
 673
 674         ps3vram_bind(&ps3vram_mtd);
 675
 676         mutex_lock(&ps3_gpu_mutex);
 677         ret = ps3vram_wait_ring(&ps3vram_mtd, 100);
 678         mutex_unlock(&ps3_gpu_mutex);
 679         if (ret < 0) {
 680                 dev_err(&dev->core, "%s:%d: failed to initialize channels\n",
 681                         __func__, __LINE__);
 682                 ret = -ETIMEDOUT;
 683                 goto out_unmap_reports;
 684         }
 685
 686         ps3vram_cache_init(&ps3vram_mtd);
 687
 688         if (add_mtd_device(&ps3vram_mtd)) {
 689                 dev_err(&dev->core, "%s:%d: add_mtd_device failed\n",
 690                         __func__, __LINE__);
 691                 ret = -EAGAIN;
 692                 goto out_cache_cleanup;
 693         }
 694
 695         dev_info(&dev->core, "reserved %u MiB of gpu memory\n",
 696                 (unsigned int)(ddr_size / 1024 / 1024));
 697
 698         return 0;
 699
 700 out_cache_cleanup:
 701         ps3vram_cache_cleanup(&ps3vram_mtd);
 702 out_unmap_reports:
 703         iounmap(priv->reports);
 704 out_unmap_ctrl:
 705         iounmap(priv->ctrl);
 706 out_unmap_vram:
 707         iounmap(priv->base);
 708 out_free_context:
 709         lv1_gpu_context_free(priv->context_handle);
 710 out_free_memory:
 711         lv1_gpu_memory_free(priv->memory_handle);
 712 out_close_gpu:
 713         ps3_close_hv_device(dev);
 714 out_free_xdr_buf:
 715         free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
 716 out_free_priv:
 717         kfree(ps3vram_mtd.priv);
 718         ps3vram_mtd.priv = NULL;
 719 out:
 720         return ret;
 721 }
 722
 723 static int ps3vram_shutdown(struct ps3_system_bus_device *dev)
 724 {
 725         struct ps3vram_priv *priv;
 726
 727         priv = ps3vram_mtd.priv;
 728
 729         del_mtd_device(&ps3vram_mtd);
 730         ps3vram_cache_cleanup(&ps3vram_mtd);
 731         iounmap(priv->reports);
 732         iounmap(priv->ctrl);
 733         iounmap(priv->base);
 734         lv1_gpu_context_free(priv->context_handle);
 735         lv1_gpu_memory_free(priv->memory_handle);
 736         ps3_close_hv_device(dev);
 737         free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
 738         kfree(priv);
 739         return 0;
 740 }
 741
 742 static struct ps3_system_bus_driver ps3vram_driver = {
 743         .match_id       = PS3_MATCH_ID_GPU,
 744         .match_sub_id   = PS3_MATCH_SUB_ID_GPU_RAMDISK,
 745         .core.name      = DEVICE_NAME,
 746         .core.owner     = THIS_MODULE,
 747         .probe          = ps3vram_probe,
 748         .remove         = ps3vram_shutdown,
 749         .shutdown       = ps3vram_shutdown,
 750 };
 751
 752 static int __init ps3vram_init(void)
 753 {
 754         return ps3_system_bus_driver_register(&ps3vram_driver);
 755 }
 756
 757 static void __exit ps3vram_exit(void)
 758 {
 759         ps3_system_bus_driver_unregister(&ps3vram_driver);
 760 }
 761
 762 module_init(ps3vram_init);
 763 module_exit(ps3vram_exit);
 764
 765 MODULE_LICENSE("GPL");
 766 MODULE_AUTHOR("Jim Paris <jim@jtan.com>");
 767 MODULE_DESCRIPTION("MTD driver for PS3 video RAM");
 768 MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);