2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
29 #include <asm/byteorder.h>
31 #include <linux/errno.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/reboot.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
45 #define MAX_WORD_RETRIES 3
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
63 static void cfi_amdstd_destroy(struct mtd_info *);
65 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
66 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
68 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
69 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
72 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
73 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
75 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
76 .probe = NULL, /* Not usable directly */
77 .destroy = cfi_amdstd_destroy,
78 .name = "cfi_cmdset_0002",
83 /* #define DEBUG_CFI_FEATURES */
86 #ifdef DEBUG_CFI_FEATURES
87 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
89 const char* erase_suspend[3] = {
90 "Not supported", "Read only", "Read/write"
92 const char* top_bottom[6] = {
93 "No WP", "8x8KiB sectors at top & bottom, no WP",
94 "Bottom boot", "Top boot",
95 "Uniform, Bottom WP", "Uniform, Top WP"
98 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
99 printk(" Address sensitive unlock: %s\n",
100 (extp->SiliconRevision & 1) ? "Not required" : "Required");
102 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
103 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
105 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
107 if (extp->BlkProt == 0)
108 printk(" Block protection: Not supported\n");
110 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
113 printk(" Temporary block unprotect: %s\n",
114 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
115 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
116 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
117 printk(" Burst mode: %s\n",
118 extp->BurstMode ? "Supported" : "Not supported");
119 if (extp->PageMode == 0)
120 printk(" Page mode: Not supported\n");
122 printk(" Page mode: %d word page\n", extp->PageMode << 2);
124 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
125 extp->VppMin >> 4, extp->VppMin & 0xf);
126 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
127 extp->VppMax >> 4, extp->VppMax & 0xf);
129 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
130 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
132 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
136 #ifdef AMD_BOOTLOC_BUG
137 /* Wheee. Bring me the head of someone at AMD. */
138 static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
140 struct map_info *map = mtd->priv;
141 struct cfi_private *cfi = map->fldrv_priv;
142 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
143 __u8 major = extp->MajorVersion;
144 __u8 minor = extp->MinorVersion;
146 if (((major << 8) | minor) < 0x3131) {
147 /* CFI version 1.0 => don't trust bootloc */
149 DEBUG(MTD_DEBUG_LEVEL1,
150 "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
151 map->name, cfi->mfr, cfi->id);
153 /* AFAICS all 29LV400 with a bottom boot block have a device ID
154 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
155 * These were badly detected as they have the 0x80 bit set
156 * so treat them as a special case.
158 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
160 /* Macronix added CFI to their 2nd generation
161 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
162 * Fujitsu, Spansion, EON, ESI and older Macronix)
165 * Therefore also check the manufacturer.
166 * This reduces the risk of false detection due to
167 * the 8-bit device ID.
169 (cfi->mfr == CFI_MFR_MACRONIX)) {
170 DEBUG(MTD_DEBUG_LEVEL1,
171 "%s: Macronix MX29LV400C with bottom boot block"
172 " detected\n", map->name);
173 extp->TopBottom = 2; /* bottom boot */
175 if (cfi->id & 0x80) {
176 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
177 extp->TopBottom = 3; /* top boot */
179 extp->TopBottom = 2; /* bottom boot */
182 DEBUG(MTD_DEBUG_LEVEL1,
183 "%s: AMD CFI PRI V%c.%c has no boot block field;"
184 " deduced %s from Device ID\n", map->name, major, minor,
185 extp->TopBottom == 2 ? "bottom" : "top");
190 static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
192 struct map_info *map = mtd->priv;
193 struct cfi_private *cfi = map->fldrv_priv;
194 if (cfi->cfiq->BufWriteTimeoutTyp) {
195 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
196 mtd->write = cfi_amdstd_write_buffers;
200 /* Atmel chips don't use the same PRI format as AMD chips */
201 static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
203 struct map_info *map = mtd->priv;
204 struct cfi_private *cfi = map->fldrv_priv;
205 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
206 struct cfi_pri_atmel atmel_pri;
208 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
209 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
211 if (atmel_pri.Features & 0x02)
212 extp->EraseSuspend = 2;
214 /* Some chips got it backwards... */
215 if (cfi->id == AT49BV6416) {
216 if (atmel_pri.BottomBoot)
221 if (atmel_pri.BottomBoot)
227 /* burst write mode not supported */
228 cfi->cfiq->BufWriteTimeoutTyp = 0;
229 cfi->cfiq->BufWriteTimeoutMax = 0;
232 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
234 /* Setup for chips with a secsi area */
235 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
236 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
239 static void fixup_use_erase_chip(struct mtd_info *mtd, void *param)
241 struct map_info *map = mtd->priv;
242 struct cfi_private *cfi = map->fldrv_priv;
243 if ((cfi->cfiq->NumEraseRegions == 1) &&
244 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
245 mtd->erase = cfi_amdstd_erase_chip;
251 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
254 static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
256 mtd->lock = cfi_atmel_lock;
257 mtd->unlock = cfi_atmel_unlock;
258 mtd->flags |= MTD_POWERUP_LOCK;
261 static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param)
263 struct map_info *map = mtd->priv;
264 struct cfi_private *cfi = map->fldrv_priv;
266 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
267 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
268 pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name);
272 static void fixup_s29gl032n_sectors(struct mtd_info *mtd, void *param)
274 struct map_info *map = mtd->priv;
275 struct cfi_private *cfi = map->fldrv_priv;
277 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
278 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
279 pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name);
283 static struct cfi_fixup cfi_fixup_table[] = {
284 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
285 #ifdef AMD_BOOTLOC_BUG
286 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
287 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock, NULL },
289 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
290 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },
291 { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, },
292 { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, },
293 { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, },
294 { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, },
295 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors, NULL, },
296 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors, NULL, },
297 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors, NULL, },
298 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors, NULL, },
299 #if !FORCE_WORD_WRITE
300 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
304 static struct cfi_fixup jedec_fixup_table[] = {
305 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
306 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock, NULL, },
307 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
311 static struct cfi_fixup fixup_table[] = {
312 /* The CFI vendor ids and the JEDEC vendor IDs appear
313 * to be common. It is like the devices id's are as
314 * well. This table is to pick all cases where
315 * we know that is the case.
317 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
318 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
323 static void cfi_fixup_major_minor(struct cfi_private *cfi,
324 struct cfi_pri_amdstd *extp)
326 if (cfi->mfr == CFI_MFR_SAMSUNG && cfi->id == 0x257e &&
327 extp->MajorVersion == '0')
328 extp->MajorVersion = '1';
331 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
333 struct cfi_private *cfi = map->fldrv_priv;
334 struct mtd_info *mtd;
337 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
339 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
343 mtd->type = MTD_NORFLASH;
345 /* Fill in the default mtd operations */
346 mtd->erase = cfi_amdstd_erase_varsize;
347 mtd->write = cfi_amdstd_write_words;
348 mtd->read = cfi_amdstd_read;
349 mtd->sync = cfi_amdstd_sync;
350 mtd->suspend = cfi_amdstd_suspend;
351 mtd->resume = cfi_amdstd_resume;
352 mtd->flags = MTD_CAP_NORFLASH;
353 mtd->name = map->name;
356 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
358 if (cfi->cfi_mode==CFI_MODE_CFI){
359 unsigned char bootloc;
361 * It's a real CFI chip, not one for which the probe
362 * routine faked a CFI structure. So we read the feature
365 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
366 struct cfi_pri_amdstd *extp;
368 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
374 cfi_fixup_major_minor(cfi, extp);
376 if (extp->MajorVersion != '1' ||
377 (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
378 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
379 "version %c.%c.\n", extp->MajorVersion,
386 /* Install our own private info structure */
387 cfi->cmdset_priv = extp;
389 /* Apply cfi device specific fixups */
390 cfi_fixup(mtd, cfi_fixup_table);
392 #ifdef DEBUG_CFI_FEATURES
393 /* Tell the user about it in lots of lovely detail */
394 cfi_tell_features(extp);
397 bootloc = extp->TopBottom;
398 if ((bootloc != 2) && (bootloc != 3)) {
399 printk(KERN_WARNING "%s: CFI does not contain boot "
400 "bank location. Assuming top.\n", map->name);
404 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
405 printk(KERN_WARNING "%s: Swapping erase regions for broken CFI table.\n", map->name);
407 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
408 int j = (cfi->cfiq->NumEraseRegions-1)-i;
411 swap = cfi->cfiq->EraseRegionInfo[i];
412 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
413 cfi->cfiq->EraseRegionInfo[j] = swap;
416 /* Set the default CFI lock/unlock addresses */
417 cfi->addr_unlock1 = 0x555;
418 cfi->addr_unlock2 = 0x2aa;
421 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
422 /* Apply jedec specific fixups */
423 cfi_fixup(mtd, jedec_fixup_table);
425 /* Apply generic fixups */
426 cfi_fixup(mtd, fixup_table);
428 for (i=0; i< cfi->numchips; i++) {
429 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
430 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
431 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
432 cfi->chips[i].ref_point_counter = 0;
433 init_waitqueue_head(&(cfi->chips[i].wq));
436 map->fldrv = &cfi_amdstd_chipdrv;
438 return cfi_amdstd_setup(mtd);
440 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
442 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
444 struct map_info *map = mtd->priv;
445 struct cfi_private *cfi = map->fldrv_priv;
446 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
447 unsigned long offset = 0;
450 printk(KERN_NOTICE "number of %s chips: %d\n",
451 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
452 /* Select the correct geometry setup */
453 mtd->size = devsize * cfi->numchips;
455 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
456 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
457 * mtd->numeraseregions, GFP_KERNEL);
458 if (!mtd->eraseregions) {
459 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
463 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
464 unsigned long ernum, ersize;
465 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
466 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
468 if (mtd->erasesize < ersize) {
469 mtd->erasesize = ersize;
471 for (j=0; j<cfi->numchips; j++) {
472 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
473 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
474 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
476 offset += (ersize * ernum);
478 if (offset != devsize) {
480 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
485 for (i=0; i<mtd->numeraseregions;i++){
486 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
487 i,mtd->eraseregions[i].offset,
488 mtd->eraseregions[i].erasesize,
489 mtd->eraseregions[i].numblocks);
493 __module_get(THIS_MODULE);
494 register_reboot_notifier(&mtd->reboot_notifier);
498 kfree(mtd->eraseregions);
500 kfree(cfi->cmdset_priv);
506 * Return true if the chip is ready.
508 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
509 * non-suspended sector) and is indicated by no toggle bits toggling.
511 * Note that anything more complicated than checking if no bits are toggling
512 * (including checking DQ5 for an error status) is tricky to get working
513 * correctly and is therefore not done (particulary with interleaved chips
514 * as each chip must be checked independantly of the others).
516 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
520 d = map_read(map, addr);
521 t = map_read(map, addr);
523 return map_word_equal(map, d, t);
527 * Return true if the chip is ready and has the correct value.
529 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
530 * non-suspended sector) and it is indicated by no bits toggling.
532 * Error are indicated by toggling bits or bits held with the wrong value,
533 * or with bits toggling.
535 * Note that anything more complicated than checking if no bits are toggling
536 * (including checking DQ5 for an error status) is tricky to get working
537 * correctly and is therefore not done (particulary with interleaved chips
538 * as each chip must be checked independantly of the others).
541 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
545 oldd = map_read(map, addr);
546 curd = map_read(map, addr);
548 return map_word_equal(map, oldd, curd) &&
549 map_word_equal(map, curd, expected);
552 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
554 DECLARE_WAITQUEUE(wait, current);
555 struct cfi_private *cfi = map->fldrv_priv;
557 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
560 timeo = jiffies + HZ;
562 switch (chip->state) {
566 if (chip_ready(map, adr))
569 if (time_after(jiffies, timeo)) {
570 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
573 mutex_unlock(&chip->mutex);
575 mutex_lock(&chip->mutex);
576 /* Someone else might have been playing with it. */
586 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
587 !(mode == FL_READY || mode == FL_POINT ||
588 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
591 /* We could check to see if we're trying to access the sector
592 * that is currently being erased. However, no user will try
593 * anything like that so we just wait for the timeout. */
596 /* It's harmless to issue the Erase-Suspend and Erase-Resume
597 * commands when the erase algorithm isn't in progress. */
598 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
599 chip->oldstate = FL_ERASING;
600 chip->state = FL_ERASE_SUSPENDING;
601 chip->erase_suspended = 1;
603 if (chip_ready(map, adr))
606 if (time_after(jiffies, timeo)) {
607 /* Should have suspended the erase by now.
608 * Send an Erase-Resume command as either
609 * there was an error (so leave the erase
610 * routine to recover from it) or we trying to
611 * use the erase-in-progress sector. */
612 map_write(map, CMD(0x30), chip->in_progress_block_addr);
613 chip->state = FL_ERASING;
614 chip->oldstate = FL_READY;
615 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
619 mutex_unlock(&chip->mutex);
621 mutex_lock(&chip->mutex);
622 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
623 So we can just loop here. */
625 chip->state = FL_READY;
628 case FL_XIP_WHILE_ERASING:
629 if (mode != FL_READY && mode != FL_POINT &&
630 (!cfip || !(cfip->EraseSuspend&2)))
632 chip->oldstate = chip->state;
633 chip->state = FL_READY;
637 /* The machine is rebooting */
641 /* Only if there's no operation suspended... */
642 if (mode == FL_READY && chip->oldstate == FL_READY)
647 set_current_state(TASK_UNINTERRUPTIBLE);
648 add_wait_queue(&chip->wq, &wait);
649 mutex_unlock(&chip->mutex);
651 remove_wait_queue(&chip->wq, &wait);
652 mutex_lock(&chip->mutex);
658 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
660 struct cfi_private *cfi = map->fldrv_priv;
662 switch(chip->oldstate) {
664 chip->state = chip->oldstate;
665 map_write(map, CMD(0x30), chip->in_progress_block_addr);
666 chip->oldstate = FL_READY;
667 chip->state = FL_ERASING;
670 case FL_XIP_WHILE_ERASING:
671 chip->state = chip->oldstate;
672 chip->oldstate = FL_READY;
677 /* We should really make set_vpp() count, rather than doing this */
681 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
686 #ifdef CONFIG_MTD_XIP
689 * No interrupt what so ever can be serviced while the flash isn't in array
690 * mode. This is ensured by the xip_disable() and xip_enable() functions
691 * enclosing any code path where the flash is known not to be in array mode.
692 * And within a XIP disabled code path, only functions marked with __xipram
693 * may be called and nothing else (it's a good thing to inspect generated
694 * assembly to make sure inline functions were actually inlined and that gcc
695 * didn't emit calls to its own support functions). Also configuring MTD CFI
696 * support to a single buswidth and a single interleave is also recommended.
699 static void xip_disable(struct map_info *map, struct flchip *chip,
702 /* TODO: chips with no XIP use should ignore and return */
703 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
707 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
710 struct cfi_private *cfi = map->fldrv_priv;
712 if (chip->state != FL_POINT && chip->state != FL_READY) {
713 map_write(map, CMD(0xf0), adr);
714 chip->state = FL_READY;
716 (void) map_read(map, adr);
722 * When a delay is required for the flash operation to complete, the
723 * xip_udelay() function is polling for both the given timeout and pending
724 * (but still masked) hardware interrupts. Whenever there is an interrupt
725 * pending then the flash erase operation is suspended, array mode restored
726 * and interrupts unmasked. Task scheduling might also happen at that
727 * point. The CPU eventually returns from the interrupt or the call to
728 * schedule() and the suspended flash operation is resumed for the remaining
729 * of the delay period.
731 * Warning: this function _will_ fool interrupt latency tracing tools.
734 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
735 unsigned long adr, int usec)
737 struct cfi_private *cfi = map->fldrv_priv;
738 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
739 map_word status, OK = CMD(0x80);
740 unsigned long suspended, start = xip_currtime();
745 if (xip_irqpending() && extp &&
746 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
747 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
749 * Let's suspend the erase operation when supported.
750 * Note that we currently don't try to suspend
751 * interleaved chips if there is already another
752 * operation suspended (imagine what happens
753 * when one chip was already done with the current
754 * operation while another chip suspended it, then
755 * we resume the whole thing at once). Yes, it
758 map_write(map, CMD(0xb0), adr);
759 usec -= xip_elapsed_since(start);
760 suspended = xip_currtime();
762 if (xip_elapsed_since(suspended) > 100000) {
764 * The chip doesn't want to suspend
765 * after waiting for 100 msecs.
766 * This is a critical error but there
767 * is not much we can do here.
771 status = map_read(map, adr);
772 } while (!map_word_andequal(map, status, OK, OK));
774 /* Suspend succeeded */
775 oldstate = chip->state;
776 if (!map_word_bitsset(map, status, CMD(0x40)))
778 chip->state = FL_XIP_WHILE_ERASING;
779 chip->erase_suspended = 1;
780 map_write(map, CMD(0xf0), adr);
781 (void) map_read(map, adr);
784 mutex_unlock(&chip->mutex);
789 * We're back. However someone else might have
790 * decided to go write to the chip if we are in
791 * a suspended erase state. If so let's wait
794 mutex_lock(&chip->mutex);
795 while (chip->state != FL_XIP_WHILE_ERASING) {
796 DECLARE_WAITQUEUE(wait, current);
797 set_current_state(TASK_UNINTERRUPTIBLE);
798 add_wait_queue(&chip->wq, &wait);
799 mutex_unlock(&chip->mutex);
801 remove_wait_queue(&chip->wq, &wait);
802 mutex_lock(&chip->mutex);
804 /* Disallow XIP again */
807 /* Resume the write or erase operation */
808 map_write(map, CMD(0x30), adr);
809 chip->state = oldstate;
810 start = xip_currtime();
811 } else if (usec >= 1000000/HZ) {
813 * Try to save on CPU power when waiting delay
814 * is at least a system timer tick period.
815 * No need to be extremely accurate here.
819 status = map_read(map, adr);
820 } while (!map_word_andequal(map, status, OK, OK)
821 && xip_elapsed_since(start) < usec);
824 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
827 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
828 * the flash is actively programming or erasing since we have to poll for
829 * the operation to complete anyway. We can't do that in a generic way with
830 * a XIP setup so do it before the actual flash operation in this case
831 * and stub it out from INVALIDATE_CACHE_UDELAY.
833 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
834 INVALIDATE_CACHED_RANGE(map, from, size)
836 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
837 UDELAY(map, chip, adr, usec)
842 * Activating this XIP support changes the way the code works a bit. For
843 * example the code to suspend the current process when concurrent access
844 * happens is never executed because xip_udelay() will always return with the
845 * same chip state as it was entered with. This is why there is no care for
846 * the presence of add_wait_queue() or schedule() calls from within a couple
847 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
848 * The queueing and scheduling are always happening within xip_udelay().
850 * Similarly, get_chip() and put_chip() just happen to always be executed
851 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
852 * is in array mode, therefore never executing many cases therein and not
853 * causing any problem with XIP.
858 #define xip_disable(map, chip, adr)
859 #define xip_enable(map, chip, adr)
860 #define XIP_INVAL_CACHED_RANGE(x...)
862 #define UDELAY(map, chip, adr, usec) \
864 mutex_unlock(&chip->mutex); \
866 mutex_lock(&chip->mutex); \
869 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
871 mutex_unlock(&chip->mutex); \
872 INVALIDATE_CACHED_RANGE(map, adr, len); \
874 mutex_lock(&chip->mutex); \
879 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
881 unsigned long cmd_addr;
882 struct cfi_private *cfi = map->fldrv_priv;
887 /* Ensure cmd read/writes are aligned. */
888 cmd_addr = adr & ~(map_bankwidth(map)-1);
890 mutex_lock(&chip->mutex);
891 ret = get_chip(map, chip, cmd_addr, FL_READY);
893 mutex_unlock(&chip->mutex);
897 if (chip->state != FL_POINT && chip->state != FL_READY) {
898 map_write(map, CMD(0xf0), cmd_addr);
899 chip->state = FL_READY;
902 map_copy_from(map, buf, adr, len);
904 put_chip(map, chip, cmd_addr);
906 mutex_unlock(&chip->mutex);
911 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
913 struct map_info *map = mtd->priv;
914 struct cfi_private *cfi = map->fldrv_priv;
919 /* ofs: offset within the first chip that the first read should start */
921 chipnum = (from >> cfi->chipshift);
922 ofs = from - (chipnum << cfi->chipshift);
928 unsigned long thislen;
930 if (chipnum >= cfi->numchips)
933 if ((len + ofs -1) >> cfi->chipshift)
934 thislen = (1<<cfi->chipshift) - ofs;
938 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
953 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
955 DECLARE_WAITQUEUE(wait, current);
956 unsigned long timeo = jiffies + HZ;
957 struct cfi_private *cfi = map->fldrv_priv;
960 mutex_lock(&chip->mutex);
962 if (chip->state != FL_READY){
964 printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
966 set_current_state(TASK_UNINTERRUPTIBLE);
967 add_wait_queue(&chip->wq, &wait);
969 mutex_unlock(&chip->mutex);
972 remove_wait_queue(&chip->wq, &wait);
974 if(signal_pending(current))
977 timeo = jiffies + HZ;
984 chip->state = FL_READY;
986 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
987 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
988 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
990 map_copy_from(map, buf, adr, len);
992 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
993 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
994 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
995 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
998 mutex_unlock(&chip->mutex);
1003 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1005 struct map_info *map = mtd->priv;
1006 struct cfi_private *cfi = map->fldrv_priv;
1012 /* ofs: offset within the first chip that the first read should start */
1014 /* 8 secsi bytes per chip */
1022 unsigned long thislen;
1024 if (chipnum >= cfi->numchips)
1027 if ((len + ofs -1) >> 3)
1028 thislen = (1<<3) - ofs;
1032 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1047 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
1049 struct cfi_private *cfi = map->fldrv_priv;
1050 unsigned long timeo = jiffies + HZ;
1052 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1053 * have a max write time of a few hundreds usec). However, we should
1054 * use the maximum timeout value given by the chip at probe time
1055 * instead. Unfortunately, struct flchip does have a field for
1056 * maximum timeout, only for typical which can be far too short
1057 * depending of the conditions. The ' + 1' is to avoid having a
1058 * timeout of 0 jiffies if HZ is smaller than 1000.
1060 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1067 mutex_lock(&chip->mutex);
1068 ret = get_chip(map, chip, adr, FL_WRITING);
1070 mutex_unlock(&chip->mutex);
1074 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1075 __func__, adr, datum.x[0] );
1078 * Check for a NOP for the case when the datum to write is already
1079 * present - it saves time and works around buggy chips that corrupt
1080 * data at other locations when 0xff is written to a location that
1081 * already contains 0xff.
1083 oldd = map_read(map, adr);
1084 if (map_word_equal(map, oldd, datum)) {
1085 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1090 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1092 xip_disable(map, chip, adr);
1094 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1095 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1096 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1097 map_write(map, datum, adr);
1098 chip->state = FL_WRITING;
1100 INVALIDATE_CACHE_UDELAY(map, chip,
1101 adr, map_bankwidth(map),
1102 chip->word_write_time);
1104 /* See comment above for timeout value. */
1105 timeo = jiffies + uWriteTimeout;
1107 if (chip->state != FL_WRITING) {
1108 /* Someone's suspended the write. Sleep */
1109 DECLARE_WAITQUEUE(wait, current);
1111 set_current_state(TASK_UNINTERRUPTIBLE);
1112 add_wait_queue(&chip->wq, &wait);
1113 mutex_unlock(&chip->mutex);
1115 remove_wait_queue(&chip->wq, &wait);
1116 timeo = jiffies + (HZ / 2); /* FIXME */
1117 mutex_lock(&chip->mutex);
1121 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1122 xip_enable(map, chip, adr);
1123 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1124 xip_disable(map, chip, adr);
1128 if (chip_ready(map, adr))
1131 /* Latency issues. Drop the lock, wait a while and retry */
1132 UDELAY(map, chip, adr, 1);
1134 /* Did we succeed? */
1135 if (!chip_good(map, adr, datum)) {
1136 /* reset on all failures. */
1137 map_write( map, CMD(0xF0), chip->start );
1138 /* FIXME - should have reset delay before continuing */
1140 if (++retry_cnt <= MAX_WORD_RETRIES)
1145 xip_enable(map, chip, adr);
1147 chip->state = FL_READY;
1148 put_chip(map, chip, adr);
1149 mutex_unlock(&chip->mutex);
1155 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1156 size_t *retlen, const u_char *buf)
1158 struct map_info *map = mtd->priv;
1159 struct cfi_private *cfi = map->fldrv_priv;
1162 unsigned long ofs, chipstart;
1163 DECLARE_WAITQUEUE(wait, current);
1169 chipnum = to >> cfi->chipshift;
1170 ofs = to - (chipnum << cfi->chipshift);
1171 chipstart = cfi->chips[chipnum].start;
1173 /* If it's not bus-aligned, do the first byte write */
1174 if (ofs & (map_bankwidth(map)-1)) {
1175 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1176 int i = ofs - bus_ofs;
1181 mutex_lock(&cfi->chips[chipnum].mutex);
1183 if (cfi->chips[chipnum].state != FL_READY) {
1185 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1187 set_current_state(TASK_UNINTERRUPTIBLE);
1188 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1190 mutex_unlock(&cfi->chips[chipnum].mutex);
1193 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1195 if(signal_pending(current))
1201 /* Load 'tmp_buf' with old contents of flash */
1202 tmp_buf = map_read(map, bus_ofs+chipstart);
1204 mutex_unlock(&cfi->chips[chipnum].mutex);
1206 /* Number of bytes to copy from buffer */
1207 n = min_t(int, len, map_bankwidth(map)-i);
1209 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1211 ret = do_write_oneword(map, &cfi->chips[chipnum],
1221 if (ofs >> cfi->chipshift) {
1224 if (chipnum == cfi->numchips)
1229 /* We are now aligned, write as much as possible */
1230 while(len >= map_bankwidth(map)) {
1233 datum = map_word_load(map, buf);
1235 ret = do_write_oneword(map, &cfi->chips[chipnum],
1240 ofs += map_bankwidth(map);
1241 buf += map_bankwidth(map);
1242 (*retlen) += map_bankwidth(map);
1243 len -= map_bankwidth(map);
1245 if (ofs >> cfi->chipshift) {
1248 if (chipnum == cfi->numchips)
1250 chipstart = cfi->chips[chipnum].start;
1254 /* Write the trailing bytes if any */
1255 if (len & (map_bankwidth(map)-1)) {
1259 mutex_lock(&cfi->chips[chipnum].mutex);
1261 if (cfi->chips[chipnum].state != FL_READY) {
1263 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1265 set_current_state(TASK_UNINTERRUPTIBLE);
1266 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1268 mutex_unlock(&cfi->chips[chipnum].mutex);
1271 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1273 if(signal_pending(current))
1279 tmp_buf = map_read(map, ofs + chipstart);
1281 mutex_unlock(&cfi->chips[chipnum].mutex);
1283 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1285 ret = do_write_oneword(map, &cfi->chips[chipnum],
1298 * FIXME: interleaved mode not tested, and probably not supported!
1300 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1301 unsigned long adr, const u_char *buf,
1304 struct cfi_private *cfi = map->fldrv_priv;
1305 unsigned long timeo = jiffies + HZ;
1306 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1307 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1309 unsigned long cmd_adr;
1316 mutex_lock(&chip->mutex);
1317 ret = get_chip(map, chip, adr, FL_WRITING);
1319 mutex_unlock(&chip->mutex);
1323 datum = map_word_load(map, buf);
1325 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1326 __func__, adr, datum.x[0] );
1328 XIP_INVAL_CACHED_RANGE(map, adr, len);
1330 xip_disable(map, chip, cmd_adr);
1332 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1333 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1334 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1336 /* Write Buffer Load */
1337 map_write(map, CMD(0x25), cmd_adr);
1339 chip->state = FL_WRITING_TO_BUFFER;
1341 /* Write length of data to come */
1342 words = len / map_bankwidth(map);
1343 map_write(map, CMD(words - 1), cmd_adr);
1346 while(z < words * map_bankwidth(map)) {
1347 datum = map_word_load(map, buf);
1348 map_write(map, datum, adr + z);
1350 z += map_bankwidth(map);
1351 buf += map_bankwidth(map);
1353 z -= map_bankwidth(map);
1357 /* Write Buffer Program Confirm: GO GO GO */
1358 map_write(map, CMD(0x29), cmd_adr);
1359 chip->state = FL_WRITING;
1361 INVALIDATE_CACHE_UDELAY(map, chip,
1362 adr, map_bankwidth(map),
1363 chip->word_write_time);
1365 timeo = jiffies + uWriteTimeout;
1368 if (chip->state != FL_WRITING) {
1369 /* Someone's suspended the write. Sleep */
1370 DECLARE_WAITQUEUE(wait, current);
1372 set_current_state(TASK_UNINTERRUPTIBLE);
1373 add_wait_queue(&chip->wq, &wait);
1374 mutex_unlock(&chip->mutex);
1376 remove_wait_queue(&chip->wq, &wait);
1377 timeo = jiffies + (HZ / 2); /* FIXME */
1378 mutex_lock(&chip->mutex);
1382 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1385 if (chip_ready(map, adr)) {
1386 xip_enable(map, chip, adr);
1390 /* Latency issues. Drop the lock, wait a while and retry */
1391 UDELAY(map, chip, adr, 1);
1394 /* reset on all failures. */
1395 map_write( map, CMD(0xF0), chip->start );
1396 xip_enable(map, chip, adr);
1397 /* FIXME - should have reset delay before continuing */
1399 printk(KERN_WARNING "MTD %s(): software timeout\n",
1404 chip->state = FL_READY;
1405 put_chip(map, chip, adr);
1406 mutex_unlock(&chip->mutex);
1412 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1413 size_t *retlen, const u_char *buf)
1415 struct map_info *map = mtd->priv;
1416 struct cfi_private *cfi = map->fldrv_priv;
1417 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1426 chipnum = to >> cfi->chipshift;
1427 ofs = to - (chipnum << cfi->chipshift);
1429 /* If it's not bus-aligned, do the first word write */
1430 if (ofs & (map_bankwidth(map)-1)) {
1431 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1432 if (local_len > len)
1434 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1435 local_len, retlen, buf);
1442 if (ofs >> cfi->chipshift) {
1445 if (chipnum == cfi->numchips)
1450 /* Write buffer is worth it only if more than one word to write... */
1451 while (len >= map_bankwidth(map) * 2) {
1452 /* We must not cross write block boundaries */
1453 int size = wbufsize - (ofs & (wbufsize-1));
1457 if (size % map_bankwidth(map))
1458 size -= size % map_bankwidth(map);
1460 ret = do_write_buffer(map, &cfi->chips[chipnum],
1470 if (ofs >> cfi->chipshift) {
1473 if (chipnum == cfi->numchips)
1479 size_t retlen_dregs = 0;
1481 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1482 len, &retlen_dregs, buf);
1484 *retlen += retlen_dregs;
1493 * Handle devices with one erase region, that only implement
1494 * the chip erase command.
1496 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1498 struct cfi_private *cfi = map->fldrv_priv;
1499 unsigned long timeo = jiffies + HZ;
1500 unsigned long int adr;
1501 DECLARE_WAITQUEUE(wait, current);
1504 adr = cfi->addr_unlock1;
1506 mutex_lock(&chip->mutex);
1507 ret = get_chip(map, chip, adr, FL_WRITING);
1509 mutex_unlock(&chip->mutex);
1513 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1514 __func__, chip->start );
1516 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1518 xip_disable(map, chip, adr);
1520 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1521 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1522 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1523 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1524 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1525 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1527 chip->state = FL_ERASING;
1528 chip->erase_suspended = 0;
1529 chip->in_progress_block_addr = adr;
1531 INVALIDATE_CACHE_UDELAY(map, chip,
1533 chip->erase_time*500);
1535 timeo = jiffies + (HZ*20);
1538 if (chip->state != FL_ERASING) {
1539 /* Someone's suspended the erase. Sleep */
1540 set_current_state(TASK_UNINTERRUPTIBLE);
1541 add_wait_queue(&chip->wq, &wait);
1542 mutex_unlock(&chip->mutex);
1544 remove_wait_queue(&chip->wq, &wait);
1545 mutex_lock(&chip->mutex);
1548 if (chip->erase_suspended) {
1549 /* This erase was suspended and resumed.
1550 Adjust the timeout */
1551 timeo = jiffies + (HZ*20); /* FIXME */
1552 chip->erase_suspended = 0;
1555 if (chip_ready(map, adr))
1558 if (time_after(jiffies, timeo)) {
1559 printk(KERN_WARNING "MTD %s(): software timeout\n",
1564 /* Latency issues. Drop the lock, wait a while and retry */
1565 UDELAY(map, chip, adr, 1000000/HZ);
1567 /* Did we succeed? */
1568 if (!chip_good(map, adr, map_word_ff(map))) {
1569 /* reset on all failures. */
1570 map_write( map, CMD(0xF0), chip->start );
1571 /* FIXME - should have reset delay before continuing */
1576 chip->state = FL_READY;
1577 xip_enable(map, chip, adr);
1578 put_chip(map, chip, adr);
1579 mutex_unlock(&chip->mutex);
1585 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1587 struct cfi_private *cfi = map->fldrv_priv;
1588 unsigned long timeo = jiffies + HZ;
1589 DECLARE_WAITQUEUE(wait, current);
1594 mutex_lock(&chip->mutex);
1595 ret = get_chip(map, chip, adr, FL_ERASING);
1597 mutex_unlock(&chip->mutex);
1601 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1604 XIP_INVAL_CACHED_RANGE(map, adr, len);
1606 xip_disable(map, chip, adr);
1608 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1609 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1610 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1611 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1612 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1613 map_write(map, CMD(0x30), adr);
1615 chip->state = FL_ERASING;
1616 chip->erase_suspended = 0;
1617 chip->in_progress_block_addr = adr;
1619 INVALIDATE_CACHE_UDELAY(map, chip,
1621 chip->erase_time*500);
1623 timeo = jiffies + (HZ*20);
1626 if (chip->state != FL_ERASING) {
1627 /* Someone's suspended the erase. Sleep */
1628 set_current_state(TASK_UNINTERRUPTIBLE);
1629 add_wait_queue(&chip->wq, &wait);
1630 mutex_unlock(&chip->mutex);
1632 remove_wait_queue(&chip->wq, &wait);
1633 mutex_lock(&chip->mutex);
1636 if (chip->erase_suspended) {
1637 /* This erase was suspended and resumed.
1638 Adjust the timeout */
1639 timeo = jiffies + (HZ*20); /* FIXME */
1640 chip->erase_suspended = 0;
1643 if (chip_ready(map, adr)) {
1644 xip_enable(map, chip, adr);
1648 if (time_after(jiffies, timeo)) {
1649 xip_enable(map, chip, adr);
1650 printk(KERN_WARNING "MTD %s(): software timeout\n",
1655 /* Latency issues. Drop the lock, wait a while and retry */
1656 UDELAY(map, chip, adr, 1000000/HZ);
1658 /* Did we succeed? */
1659 if (!chip_good(map, adr, map_word_ff(map))) {
1660 /* reset on all failures. */
1661 map_write( map, CMD(0xF0), chip->start );
1662 /* FIXME - should have reset delay before continuing */
1667 chip->state = FL_READY;
1668 put_chip(map, chip, adr);
1669 mutex_unlock(&chip->mutex);
1674 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1676 unsigned long ofs, len;
1682 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1686 instr->state = MTD_ERASE_DONE;
1687 mtd_erase_callback(instr);
1693 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1695 struct map_info *map = mtd->priv;
1696 struct cfi_private *cfi = map->fldrv_priv;
1699 if (instr->addr != 0)
1702 if (instr->len != mtd->size)
1705 ret = do_erase_chip(map, &cfi->chips[0]);
1709 instr->state = MTD_ERASE_DONE;
1710 mtd_erase_callback(instr);
1715 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1716 unsigned long adr, int len, void *thunk)
1718 struct cfi_private *cfi = map->fldrv_priv;
1721 mutex_lock(&chip->mutex);
1722 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1725 chip->state = FL_LOCKING;
1727 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1728 __func__, adr, len);
1730 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1731 cfi->device_type, NULL);
1732 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1733 cfi->device_type, NULL);
1734 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1735 cfi->device_type, NULL);
1736 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1737 cfi->device_type, NULL);
1738 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1739 cfi->device_type, NULL);
1740 map_write(map, CMD(0x40), chip->start + adr);
1742 chip->state = FL_READY;
1743 put_chip(map, chip, adr + chip->start);
1747 mutex_unlock(&chip->mutex);
1751 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1752 unsigned long adr, int len, void *thunk)
1754 struct cfi_private *cfi = map->fldrv_priv;
1757 mutex_lock(&chip->mutex);
1758 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1761 chip->state = FL_UNLOCKING;
1763 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1764 __func__, adr, len);
1766 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1767 cfi->device_type, NULL);
1768 map_write(map, CMD(0x70), adr);
1770 chip->state = FL_READY;
1771 put_chip(map, chip, adr + chip->start);
1775 mutex_unlock(&chip->mutex);
1779 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1781 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1784 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1786 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1790 static void cfi_amdstd_sync (struct mtd_info *mtd)
1792 struct map_info *map = mtd->priv;
1793 struct cfi_private *cfi = map->fldrv_priv;
1795 struct flchip *chip;
1797 DECLARE_WAITQUEUE(wait, current);
1799 for (i=0; !ret && i<cfi->numchips; i++) {
1800 chip = &cfi->chips[i];
1803 mutex_lock(&chip->mutex);
1805 switch(chip->state) {
1809 case FL_JEDEC_QUERY:
1810 chip->oldstate = chip->state;
1811 chip->state = FL_SYNCING;
1812 /* No need to wake_up() on this state change -
1813 * as the whole point is that nobody can do anything
1814 * with the chip now anyway.
1817 mutex_unlock(&chip->mutex);
1821 /* Not an idle state */
1822 set_current_state(TASK_UNINTERRUPTIBLE);
1823 add_wait_queue(&chip->wq, &wait);
1825 mutex_unlock(&chip->mutex);
1829 remove_wait_queue(&chip->wq, &wait);
1835 /* Unlock the chips again */
1837 for (i--; i >=0; i--) {
1838 chip = &cfi->chips[i];
1840 mutex_lock(&chip->mutex);
1842 if (chip->state == FL_SYNCING) {
1843 chip->state = chip->oldstate;
1846 mutex_unlock(&chip->mutex);
1851 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1853 struct map_info *map = mtd->priv;
1854 struct cfi_private *cfi = map->fldrv_priv;
1856 struct flchip *chip;
1859 for (i=0; !ret && i<cfi->numchips; i++) {
1860 chip = &cfi->chips[i];
1862 mutex_lock(&chip->mutex);
1864 switch(chip->state) {
1868 case FL_JEDEC_QUERY:
1869 chip->oldstate = chip->state;
1870 chip->state = FL_PM_SUSPENDED;
1871 /* No need to wake_up() on this state change -
1872 * as the whole point is that nobody can do anything
1873 * with the chip now anyway.
1875 case FL_PM_SUSPENDED:
1882 mutex_unlock(&chip->mutex);
1885 /* Unlock the chips again */
1888 for (i--; i >=0; i--) {
1889 chip = &cfi->chips[i];
1891 mutex_lock(&chip->mutex);
1893 if (chip->state == FL_PM_SUSPENDED) {
1894 chip->state = chip->oldstate;
1897 mutex_unlock(&chip->mutex);
1905 static void cfi_amdstd_resume(struct mtd_info *mtd)
1907 struct map_info *map = mtd->priv;
1908 struct cfi_private *cfi = map->fldrv_priv;
1910 struct flchip *chip;
1912 for (i=0; i<cfi->numchips; i++) {
1914 chip = &cfi->chips[i];
1916 mutex_lock(&chip->mutex);
1918 if (chip->state == FL_PM_SUSPENDED) {
1919 chip->state = FL_READY;
1920 map_write(map, CMD(0xF0), chip->start);
1924 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1926 mutex_unlock(&chip->mutex);
1932 * Ensure that the flash device is put back into read array mode before
1933 * unloading the driver or rebooting. On some systems, rebooting while
1934 * the flash is in query/program/erase mode will prevent the CPU from
1935 * fetching the bootloader code, requiring a hard reset or power cycle.
1937 static int cfi_amdstd_reset(struct mtd_info *mtd)
1939 struct map_info *map = mtd->priv;
1940 struct cfi_private *cfi = map->fldrv_priv;
1942 struct flchip *chip;
1944 for (i = 0; i < cfi->numchips; i++) {
1946 chip = &cfi->chips[i];
1948 mutex_lock(&chip->mutex);
1950 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
1952 map_write(map, CMD(0xF0), chip->start);
1953 chip->state = FL_SHUTDOWN;
1954 put_chip(map, chip, chip->start);
1957 mutex_unlock(&chip->mutex);
1964 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
1967 struct mtd_info *mtd;
1969 mtd = container_of(nb, struct mtd_info, reboot_notifier);
1970 cfi_amdstd_reset(mtd);
1975 static void cfi_amdstd_destroy(struct mtd_info *mtd)
1977 struct map_info *map = mtd->priv;
1978 struct cfi_private *cfi = map->fldrv_priv;
1980 cfi_amdstd_reset(mtd);
1981 unregister_reboot_notifier(&mtd->reboot_notifier);
1982 kfree(cfi->cmdset_priv);
1985 kfree(mtd->eraseregions);
1988 MODULE_LICENSE("GPL");
1989 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1990 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");