2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
29 #include <asm/byteorder.h>
31 #include <linux/errno.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/reboot.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
45 #define MAX_WORD_RETRIES 3
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
63 static void cfi_amdstd_destroy(struct mtd_info *);
65 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
66 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
68 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
69 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
72 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
73 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
75 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
76 .probe = NULL, /* Not usable directly */
77 .destroy = cfi_amdstd_destroy,
78 .name = "cfi_cmdset_0002",
83 /* #define DEBUG_CFI_FEATURES */
86 #ifdef DEBUG_CFI_FEATURES
87 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
89 const char* erase_suspend[3] = {
90 "Not supported", "Read only", "Read/write"
92 const char* top_bottom[6] = {
93 "No WP", "8x8KiB sectors at top & bottom, no WP",
94 "Bottom boot", "Top boot",
95 "Uniform, Bottom WP", "Uniform, Top WP"
98 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
99 printk(" Address sensitive unlock: %s\n",
100 (extp->SiliconRevision & 1) ? "Not required" : "Required");
102 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
103 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
105 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
107 if (extp->BlkProt == 0)
108 printk(" Block protection: Not supported\n");
110 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
113 printk(" Temporary block unprotect: %s\n",
114 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
115 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
116 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
117 printk(" Burst mode: %s\n",
118 extp->BurstMode ? "Supported" : "Not supported");
119 if (extp->PageMode == 0)
120 printk(" Page mode: Not supported\n");
122 printk(" Page mode: %d word page\n", extp->PageMode << 2);
124 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
125 extp->VppMin >> 4, extp->VppMin & 0xf);
126 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
127 extp->VppMax >> 4, extp->VppMax & 0xf);
129 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
130 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
132 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
136 #ifdef AMD_BOOTLOC_BUG
137 /* Wheee. Bring me the head of someone at AMD. */
138 static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
140 struct map_info *map = mtd->priv;
141 struct cfi_private *cfi = map->fldrv_priv;
142 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
143 __u8 major = extp->MajorVersion;
144 __u8 minor = extp->MinorVersion;
146 if (((major << 8) | minor) < 0x3131) {
147 /* CFI version 1.0 => don't trust bootloc */
149 DEBUG(MTD_DEBUG_LEVEL1,
150 "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
151 map->name, cfi->mfr, cfi->id);
153 /* AFAICS all 29LV400 with a bottom boot block have a device ID
154 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
155 * These were badly detected as they have the 0x80 bit set
156 * so treat them as a special case.
158 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
160 /* Macronix added CFI to their 2nd generation
161 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
162 * Fujitsu, Spansion, EON, ESI and older Macronix)
165 * Therefore also check the manufacturer.
166 * This reduces the risk of false detection due to
167 * the 8-bit device ID.
169 (cfi->mfr == CFI_MFR_MACRONIX)) {
170 DEBUG(MTD_DEBUG_LEVEL1,
171 "%s: Macronix MX29LV400C with bottom boot block"
172 " detected\n", map->name);
173 extp->TopBottom = 2; /* bottom boot */
175 if (cfi->id & 0x80) {
176 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
177 extp->TopBottom = 3; /* top boot */
179 extp->TopBottom = 2; /* bottom boot */
182 DEBUG(MTD_DEBUG_LEVEL1,
183 "%s: AMD CFI PRI V%c.%c has no boot block field;"
184 " deduced %s from Device ID\n", map->name, major, minor,
185 extp->TopBottom == 2 ? "bottom" : "top");
190 static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
192 struct map_info *map = mtd->priv;
193 struct cfi_private *cfi = map->fldrv_priv;
194 if (cfi->cfiq->BufWriteTimeoutTyp) {
195 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
196 mtd->write = cfi_amdstd_write_buffers;
200 /* Atmel chips don't use the same PRI format as AMD chips */
201 static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
203 struct map_info *map = mtd->priv;
204 struct cfi_private *cfi = map->fldrv_priv;
205 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
206 struct cfi_pri_atmel atmel_pri;
208 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
209 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
211 if (atmel_pri.Features & 0x02)
212 extp->EraseSuspend = 2;
214 /* Some chips got it backwards... */
215 if (cfi->id == AT49BV6416) {
216 if (atmel_pri.BottomBoot)
221 if (atmel_pri.BottomBoot)
227 /* burst write mode not supported */
228 cfi->cfiq->BufWriteTimeoutTyp = 0;
229 cfi->cfiq->BufWriteTimeoutMax = 0;
232 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
234 /* Setup for chips with a secsi area */
235 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
236 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
239 static void fixup_use_erase_chip(struct mtd_info *mtd, void *param)
241 struct map_info *map = mtd->priv;
242 struct cfi_private *cfi = map->fldrv_priv;
243 if ((cfi->cfiq->NumEraseRegions == 1) &&
244 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
245 mtd->erase = cfi_amdstd_erase_chip;
251 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
254 static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
256 mtd->lock = cfi_atmel_lock;
257 mtd->unlock = cfi_atmel_unlock;
258 mtd->flags |= MTD_POWERUP_LOCK;
261 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
263 struct map_info *map = mtd->priv;
264 struct cfi_private *cfi = map->fldrv_priv;
267 * These flashes report two seperate eraseblock regions based on the
268 * sector_erase-size and block_erase-size, although they both operate on the
269 * same memory. This is not allowed according to CFI, so we just pick the
272 cfi->cfiq->NumEraseRegions = 1;
275 static void fixup_sst39vf(struct mtd_info *mtd, void *param)
277 struct map_info *map = mtd->priv;
278 struct cfi_private *cfi = map->fldrv_priv;
280 fixup_old_sst_eraseregion(mtd);
282 cfi->addr_unlock1 = 0x5555;
283 cfi->addr_unlock2 = 0x2AAA;
286 static void fixup_sst39vf_rev_b(struct mtd_info *mtd, void *param)
288 struct map_info *map = mtd->priv;
289 struct cfi_private *cfi = map->fldrv_priv;
291 fixup_old_sst_eraseregion(mtd);
293 cfi->addr_unlock1 = 0x555;
294 cfi->addr_unlock2 = 0x2AA;
297 static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param)
299 struct map_info *map = mtd->priv;
300 struct cfi_private *cfi = map->fldrv_priv;
302 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
303 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
304 pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name);
308 static void fixup_s29gl032n_sectors(struct mtd_info *mtd, void *param)
310 struct map_info *map = mtd->priv;
311 struct cfi_private *cfi = map->fldrv_priv;
313 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
314 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
315 pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name);
319 /* Used to fix CFI-Tables of chips without Extended Query Tables */
320 static struct cfi_fixup cfi_nopri_fixup_table[] = {
321 { CFI_MFR_SST, 0x234A, fixup_sst39vf, NULL, }, // SST39VF1602
322 { CFI_MFR_SST, 0x234B, fixup_sst39vf, NULL, }, // SST39VF1601
323 { CFI_MFR_SST, 0x235A, fixup_sst39vf, NULL, }, // SST39VF3202
324 { CFI_MFR_SST, 0x235B, fixup_sst39vf, NULL, }, // SST39VF3201
325 { CFI_MFR_SST, 0x235C, fixup_sst39vf_rev_b, NULL, }, // SST39VF3202B
326 { CFI_MFR_SST, 0x235D, fixup_sst39vf_rev_b, NULL, }, // SST39VF3201B
327 { CFI_MFR_SST, 0x236C, fixup_sst39vf_rev_b, NULL, }, // SST39VF6402B
328 { CFI_MFR_SST, 0x236D, fixup_sst39vf_rev_b, NULL, }, // SST39VF6401B
332 static struct cfi_fixup cfi_fixup_table[] = {
333 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
334 #ifdef AMD_BOOTLOC_BUG
335 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
336 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock, NULL },
338 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
339 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },
340 { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, },
341 { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, },
342 { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, },
343 { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, },
344 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors, NULL, },
345 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors, NULL, },
346 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors, NULL, },
347 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors, NULL, },
348 #if !FORCE_WORD_WRITE
349 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
353 static struct cfi_fixup jedec_fixup_table[] = {
354 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
355 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock, NULL, },
356 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
360 static struct cfi_fixup fixup_table[] = {
361 /* The CFI vendor ids and the JEDEC vendor IDs appear
362 * to be common. It is like the devices id's are as
363 * well. This table is to pick all cases where
364 * we know that is the case.
366 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
367 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
372 static void cfi_fixup_major_minor(struct cfi_private *cfi,
373 struct cfi_pri_amdstd *extp)
375 if (cfi->mfr == CFI_MFR_SAMSUNG && cfi->id == 0x257e &&
376 extp->MajorVersion == '0')
377 extp->MajorVersion = '1';
380 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
382 struct cfi_private *cfi = map->fldrv_priv;
383 struct mtd_info *mtd;
386 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
388 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
392 mtd->type = MTD_NORFLASH;
394 /* Fill in the default mtd operations */
395 mtd->erase = cfi_amdstd_erase_varsize;
396 mtd->write = cfi_amdstd_write_words;
397 mtd->read = cfi_amdstd_read;
398 mtd->sync = cfi_amdstd_sync;
399 mtd->suspend = cfi_amdstd_suspend;
400 mtd->resume = cfi_amdstd_resume;
401 mtd->flags = MTD_CAP_NORFLASH;
402 mtd->name = map->name;
405 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
407 if (cfi->cfi_mode==CFI_MODE_CFI){
408 unsigned char bootloc;
409 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
410 struct cfi_pri_amdstd *extp;
412 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
415 * It's a real CFI chip, not one for which the probe
416 * routine faked a CFI structure.
418 cfi_fixup_major_minor(cfi, extp);
420 if (extp->MajorVersion != '1' ||
421 (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
422 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
423 "version %c.%c.\n", extp->MajorVersion,
430 /* Install our own private info structure */
431 cfi->cmdset_priv = extp;
433 /* Apply cfi device specific fixups */
434 cfi_fixup(mtd, cfi_fixup_table);
436 #ifdef DEBUG_CFI_FEATURES
437 /* Tell the user about it in lots of lovely detail */
438 cfi_tell_features(extp);
441 bootloc = extp->TopBottom;
442 if ((bootloc < 2) || (bootloc > 5)) {
443 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
444 "bank location (%d). Assuming bottom.\n",
449 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
450 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
452 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
453 int j = (cfi->cfiq->NumEraseRegions-1)-i;
456 swap = cfi->cfiq->EraseRegionInfo[i];
457 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
458 cfi->cfiq->EraseRegionInfo[j] = swap;
461 /* Set the default CFI lock/unlock addresses */
462 cfi->addr_unlock1 = 0x555;
463 cfi->addr_unlock2 = 0x2aa;
465 cfi_fixup(mtd, cfi_nopri_fixup_table);
467 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
473 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
474 /* Apply jedec specific fixups */
475 cfi_fixup(mtd, jedec_fixup_table);
477 /* Apply generic fixups */
478 cfi_fixup(mtd, fixup_table);
480 for (i=0; i< cfi->numchips; i++) {
481 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
482 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
483 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
484 cfi->chips[i].ref_point_counter = 0;
485 init_waitqueue_head(&(cfi->chips[i].wq));
488 map->fldrv = &cfi_amdstd_chipdrv;
490 return cfi_amdstd_setup(mtd);
492 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
494 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
496 struct map_info *map = mtd->priv;
497 struct cfi_private *cfi = map->fldrv_priv;
498 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
499 unsigned long offset = 0;
502 printk(KERN_NOTICE "number of %s chips: %d\n",
503 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
504 /* Select the correct geometry setup */
505 mtd->size = devsize * cfi->numchips;
507 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
508 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
509 * mtd->numeraseregions, GFP_KERNEL);
510 if (!mtd->eraseregions) {
511 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
515 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
516 unsigned long ernum, ersize;
517 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
518 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
520 if (mtd->erasesize < ersize) {
521 mtd->erasesize = ersize;
523 for (j=0; j<cfi->numchips; j++) {
524 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
525 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
526 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
528 offset += (ersize * ernum);
530 if (offset != devsize) {
532 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
537 for (i=0; i<mtd->numeraseregions;i++){
538 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
539 i,mtd->eraseregions[i].offset,
540 mtd->eraseregions[i].erasesize,
541 mtd->eraseregions[i].numblocks);
545 __module_get(THIS_MODULE);
546 register_reboot_notifier(&mtd->reboot_notifier);
550 kfree(mtd->eraseregions);
552 kfree(cfi->cmdset_priv);
558 * Return true if the chip is ready.
560 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
561 * non-suspended sector) and is indicated by no toggle bits toggling.
563 * Note that anything more complicated than checking if no bits are toggling
564 * (including checking DQ5 for an error status) is tricky to get working
565 * correctly and is therefore not done (particulary with interleaved chips
566 * as each chip must be checked independantly of the others).
568 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
572 d = map_read(map, addr);
573 t = map_read(map, addr);
575 return map_word_equal(map, d, t);
579 * Return true if the chip is ready and has the correct value.
581 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
582 * non-suspended sector) and it is indicated by no bits toggling.
584 * Error are indicated by toggling bits or bits held with the wrong value,
585 * or with bits toggling.
587 * Note that anything more complicated than checking if no bits are toggling
588 * (including checking DQ5 for an error status) is tricky to get working
589 * correctly and is therefore not done (particulary with interleaved chips
590 * as each chip must be checked independantly of the others).
593 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
597 oldd = map_read(map, addr);
598 curd = map_read(map, addr);
600 return map_word_equal(map, oldd, curd) &&
601 map_word_equal(map, curd, expected);
604 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
606 DECLARE_WAITQUEUE(wait, current);
607 struct cfi_private *cfi = map->fldrv_priv;
609 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
612 timeo = jiffies + HZ;
614 switch (chip->state) {
618 if (chip_ready(map, adr))
621 if (time_after(jiffies, timeo)) {
622 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
625 mutex_unlock(&chip->mutex);
627 mutex_lock(&chip->mutex);
628 /* Someone else might have been playing with it. */
638 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
639 !(mode == FL_READY || mode == FL_POINT ||
640 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
643 /* We could check to see if we're trying to access the sector
644 * that is currently being erased. However, no user will try
645 * anything like that so we just wait for the timeout. */
648 /* It's harmless to issue the Erase-Suspend and Erase-Resume
649 * commands when the erase algorithm isn't in progress. */
650 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
651 chip->oldstate = FL_ERASING;
652 chip->state = FL_ERASE_SUSPENDING;
653 chip->erase_suspended = 1;
655 if (chip_ready(map, adr))
658 if (time_after(jiffies, timeo)) {
659 /* Should have suspended the erase by now.
660 * Send an Erase-Resume command as either
661 * there was an error (so leave the erase
662 * routine to recover from it) or we trying to
663 * use the erase-in-progress sector. */
664 map_write(map, CMD(0x30), chip->in_progress_block_addr);
665 chip->state = FL_ERASING;
666 chip->oldstate = FL_READY;
667 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
671 mutex_unlock(&chip->mutex);
673 mutex_lock(&chip->mutex);
674 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
675 So we can just loop here. */
677 chip->state = FL_READY;
680 case FL_XIP_WHILE_ERASING:
681 if (mode != FL_READY && mode != FL_POINT &&
682 (!cfip || !(cfip->EraseSuspend&2)))
684 chip->oldstate = chip->state;
685 chip->state = FL_READY;
689 /* The machine is rebooting */
693 /* Only if there's no operation suspended... */
694 if (mode == FL_READY && chip->oldstate == FL_READY)
699 set_current_state(TASK_UNINTERRUPTIBLE);
700 add_wait_queue(&chip->wq, &wait);
701 mutex_unlock(&chip->mutex);
703 remove_wait_queue(&chip->wq, &wait);
704 mutex_lock(&chip->mutex);
710 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
712 struct cfi_private *cfi = map->fldrv_priv;
714 switch(chip->oldstate) {
716 chip->state = chip->oldstate;
717 map_write(map, CMD(0x30), chip->in_progress_block_addr);
718 chip->oldstate = FL_READY;
719 chip->state = FL_ERASING;
722 case FL_XIP_WHILE_ERASING:
723 chip->state = chip->oldstate;
724 chip->oldstate = FL_READY;
729 /* We should really make set_vpp() count, rather than doing this */
733 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
738 #ifdef CONFIG_MTD_XIP
741 * No interrupt what so ever can be serviced while the flash isn't in array
742 * mode. This is ensured by the xip_disable() and xip_enable() functions
743 * enclosing any code path where the flash is known not to be in array mode.
744 * And within a XIP disabled code path, only functions marked with __xipram
745 * may be called and nothing else (it's a good thing to inspect generated
746 * assembly to make sure inline functions were actually inlined and that gcc
747 * didn't emit calls to its own support functions). Also configuring MTD CFI
748 * support to a single buswidth and a single interleave is also recommended.
751 static void xip_disable(struct map_info *map, struct flchip *chip,
754 /* TODO: chips with no XIP use should ignore and return */
755 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
759 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
762 struct cfi_private *cfi = map->fldrv_priv;
764 if (chip->state != FL_POINT && chip->state != FL_READY) {
765 map_write(map, CMD(0xf0), adr);
766 chip->state = FL_READY;
768 (void) map_read(map, adr);
774 * When a delay is required for the flash operation to complete, the
775 * xip_udelay() function is polling for both the given timeout and pending
776 * (but still masked) hardware interrupts. Whenever there is an interrupt
777 * pending then the flash erase operation is suspended, array mode restored
778 * and interrupts unmasked. Task scheduling might also happen at that
779 * point. The CPU eventually returns from the interrupt or the call to
780 * schedule() and the suspended flash operation is resumed for the remaining
781 * of the delay period.
783 * Warning: this function _will_ fool interrupt latency tracing tools.
786 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
787 unsigned long adr, int usec)
789 struct cfi_private *cfi = map->fldrv_priv;
790 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
791 map_word status, OK = CMD(0x80);
792 unsigned long suspended, start = xip_currtime();
797 if (xip_irqpending() && extp &&
798 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
799 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
801 * Let's suspend the erase operation when supported.
802 * Note that we currently don't try to suspend
803 * interleaved chips if there is already another
804 * operation suspended (imagine what happens
805 * when one chip was already done with the current
806 * operation while another chip suspended it, then
807 * we resume the whole thing at once). Yes, it
810 map_write(map, CMD(0xb0), adr);
811 usec -= xip_elapsed_since(start);
812 suspended = xip_currtime();
814 if (xip_elapsed_since(suspended) > 100000) {
816 * The chip doesn't want to suspend
817 * after waiting for 100 msecs.
818 * This is a critical error but there
819 * is not much we can do here.
823 status = map_read(map, adr);
824 } while (!map_word_andequal(map, status, OK, OK));
826 /* Suspend succeeded */
827 oldstate = chip->state;
828 if (!map_word_bitsset(map, status, CMD(0x40)))
830 chip->state = FL_XIP_WHILE_ERASING;
831 chip->erase_suspended = 1;
832 map_write(map, CMD(0xf0), adr);
833 (void) map_read(map, adr);
836 mutex_unlock(&chip->mutex);
841 * We're back. However someone else might have
842 * decided to go write to the chip if we are in
843 * a suspended erase state. If so let's wait
846 mutex_lock(&chip->mutex);
847 while (chip->state != FL_XIP_WHILE_ERASING) {
848 DECLARE_WAITQUEUE(wait, current);
849 set_current_state(TASK_UNINTERRUPTIBLE);
850 add_wait_queue(&chip->wq, &wait);
851 mutex_unlock(&chip->mutex);
853 remove_wait_queue(&chip->wq, &wait);
854 mutex_lock(&chip->mutex);
856 /* Disallow XIP again */
859 /* Resume the write or erase operation */
860 map_write(map, CMD(0x30), adr);
861 chip->state = oldstate;
862 start = xip_currtime();
863 } else if (usec >= 1000000/HZ) {
865 * Try to save on CPU power when waiting delay
866 * is at least a system timer tick period.
867 * No need to be extremely accurate here.
871 status = map_read(map, adr);
872 } while (!map_word_andequal(map, status, OK, OK)
873 && xip_elapsed_since(start) < usec);
876 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
879 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
880 * the flash is actively programming or erasing since we have to poll for
881 * the operation to complete anyway. We can't do that in a generic way with
882 * a XIP setup so do it before the actual flash operation in this case
883 * and stub it out from INVALIDATE_CACHE_UDELAY.
885 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
886 INVALIDATE_CACHED_RANGE(map, from, size)
888 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
889 UDELAY(map, chip, adr, usec)
894 * Activating this XIP support changes the way the code works a bit. For
895 * example the code to suspend the current process when concurrent access
896 * happens is never executed because xip_udelay() will always return with the
897 * same chip state as it was entered with. This is why there is no care for
898 * the presence of add_wait_queue() or schedule() calls from within a couple
899 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
900 * The queueing and scheduling are always happening within xip_udelay().
902 * Similarly, get_chip() and put_chip() just happen to always be executed
903 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
904 * is in array mode, therefore never executing many cases therein and not
905 * causing any problem with XIP.
910 #define xip_disable(map, chip, adr)
911 #define xip_enable(map, chip, adr)
912 #define XIP_INVAL_CACHED_RANGE(x...)
914 #define UDELAY(map, chip, adr, usec) \
916 mutex_unlock(&chip->mutex); \
918 mutex_lock(&chip->mutex); \
921 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
923 mutex_unlock(&chip->mutex); \
924 INVALIDATE_CACHED_RANGE(map, adr, len); \
926 mutex_lock(&chip->mutex); \
931 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
933 unsigned long cmd_addr;
934 struct cfi_private *cfi = map->fldrv_priv;
939 /* Ensure cmd read/writes are aligned. */
940 cmd_addr = adr & ~(map_bankwidth(map)-1);
942 mutex_lock(&chip->mutex);
943 ret = get_chip(map, chip, cmd_addr, FL_READY);
945 mutex_unlock(&chip->mutex);
949 if (chip->state != FL_POINT && chip->state != FL_READY) {
950 map_write(map, CMD(0xf0), cmd_addr);
951 chip->state = FL_READY;
954 map_copy_from(map, buf, adr, len);
956 put_chip(map, chip, cmd_addr);
958 mutex_unlock(&chip->mutex);
963 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
965 struct map_info *map = mtd->priv;
966 struct cfi_private *cfi = map->fldrv_priv;
971 /* ofs: offset within the first chip that the first read should start */
973 chipnum = (from >> cfi->chipshift);
974 ofs = from - (chipnum << cfi->chipshift);
980 unsigned long thislen;
982 if (chipnum >= cfi->numchips)
985 if ((len + ofs -1) >> cfi->chipshift)
986 thislen = (1<<cfi->chipshift) - ofs;
990 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1005 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1007 DECLARE_WAITQUEUE(wait, current);
1008 unsigned long timeo = jiffies + HZ;
1009 struct cfi_private *cfi = map->fldrv_priv;
1012 mutex_lock(&chip->mutex);
1014 if (chip->state != FL_READY){
1016 printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
1018 set_current_state(TASK_UNINTERRUPTIBLE);
1019 add_wait_queue(&chip->wq, &wait);
1021 mutex_unlock(&chip->mutex);
1024 remove_wait_queue(&chip->wq, &wait);
1026 if(signal_pending(current))
1029 timeo = jiffies + HZ;
1036 chip->state = FL_READY;
1038 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1039 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1040 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1042 map_copy_from(map, buf, adr, len);
1044 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1045 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1046 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1047 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1050 mutex_unlock(&chip->mutex);
1055 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1057 struct map_info *map = mtd->priv;
1058 struct cfi_private *cfi = map->fldrv_priv;
1064 /* ofs: offset within the first chip that the first read should start */
1066 /* 8 secsi bytes per chip */
1074 unsigned long thislen;
1076 if (chipnum >= cfi->numchips)
1079 if ((len + ofs -1) >> 3)
1080 thislen = (1<<3) - ofs;
1084 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1099 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
1101 struct cfi_private *cfi = map->fldrv_priv;
1102 unsigned long timeo = jiffies + HZ;
1104 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1105 * have a max write time of a few hundreds usec). However, we should
1106 * use the maximum timeout value given by the chip at probe time
1107 * instead. Unfortunately, struct flchip does have a field for
1108 * maximum timeout, only for typical which can be far too short
1109 * depending of the conditions. The ' + 1' is to avoid having a
1110 * timeout of 0 jiffies if HZ is smaller than 1000.
1112 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1119 mutex_lock(&chip->mutex);
1120 ret = get_chip(map, chip, adr, FL_WRITING);
1122 mutex_unlock(&chip->mutex);
1126 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1127 __func__, adr, datum.x[0] );
1130 * Check for a NOP for the case when the datum to write is already
1131 * present - it saves time and works around buggy chips that corrupt
1132 * data at other locations when 0xff is written to a location that
1133 * already contains 0xff.
1135 oldd = map_read(map, adr);
1136 if (map_word_equal(map, oldd, datum)) {
1137 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1142 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1144 xip_disable(map, chip, adr);
1146 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1147 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1148 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1149 map_write(map, datum, adr);
1150 chip->state = FL_WRITING;
1152 INVALIDATE_CACHE_UDELAY(map, chip,
1153 adr, map_bankwidth(map),
1154 chip->word_write_time);
1156 /* See comment above for timeout value. */
1157 timeo = jiffies + uWriteTimeout;
1159 if (chip->state != FL_WRITING) {
1160 /* Someone's suspended the write. Sleep */
1161 DECLARE_WAITQUEUE(wait, current);
1163 set_current_state(TASK_UNINTERRUPTIBLE);
1164 add_wait_queue(&chip->wq, &wait);
1165 mutex_unlock(&chip->mutex);
1167 remove_wait_queue(&chip->wq, &wait);
1168 timeo = jiffies + (HZ / 2); /* FIXME */
1169 mutex_lock(&chip->mutex);
1173 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1174 xip_enable(map, chip, adr);
1175 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1176 xip_disable(map, chip, adr);
1180 if (chip_ready(map, adr))
1183 /* Latency issues. Drop the lock, wait a while and retry */
1184 UDELAY(map, chip, adr, 1);
1186 /* Did we succeed? */
1187 if (!chip_good(map, adr, datum)) {
1188 /* reset on all failures. */
1189 map_write( map, CMD(0xF0), chip->start );
1190 /* FIXME - should have reset delay before continuing */
1192 if (++retry_cnt <= MAX_WORD_RETRIES)
1197 xip_enable(map, chip, adr);
1199 chip->state = FL_READY;
1200 put_chip(map, chip, adr);
1201 mutex_unlock(&chip->mutex);
1207 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1208 size_t *retlen, const u_char *buf)
1210 struct map_info *map = mtd->priv;
1211 struct cfi_private *cfi = map->fldrv_priv;
1214 unsigned long ofs, chipstart;
1215 DECLARE_WAITQUEUE(wait, current);
1221 chipnum = to >> cfi->chipshift;
1222 ofs = to - (chipnum << cfi->chipshift);
1223 chipstart = cfi->chips[chipnum].start;
1225 /* If it's not bus-aligned, do the first byte write */
1226 if (ofs & (map_bankwidth(map)-1)) {
1227 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1228 int i = ofs - bus_ofs;
1233 mutex_lock(&cfi->chips[chipnum].mutex);
1235 if (cfi->chips[chipnum].state != FL_READY) {
1237 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1239 set_current_state(TASK_UNINTERRUPTIBLE);
1240 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1242 mutex_unlock(&cfi->chips[chipnum].mutex);
1245 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1247 if(signal_pending(current))
1253 /* Load 'tmp_buf' with old contents of flash */
1254 tmp_buf = map_read(map, bus_ofs+chipstart);
1256 mutex_unlock(&cfi->chips[chipnum].mutex);
1258 /* Number of bytes to copy from buffer */
1259 n = min_t(int, len, map_bankwidth(map)-i);
1261 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1263 ret = do_write_oneword(map, &cfi->chips[chipnum],
1273 if (ofs >> cfi->chipshift) {
1276 if (chipnum == cfi->numchips)
1281 /* We are now aligned, write as much as possible */
1282 while(len >= map_bankwidth(map)) {
1285 datum = map_word_load(map, buf);
1287 ret = do_write_oneword(map, &cfi->chips[chipnum],
1292 ofs += map_bankwidth(map);
1293 buf += map_bankwidth(map);
1294 (*retlen) += map_bankwidth(map);
1295 len -= map_bankwidth(map);
1297 if (ofs >> cfi->chipshift) {
1300 if (chipnum == cfi->numchips)
1302 chipstart = cfi->chips[chipnum].start;
1306 /* Write the trailing bytes if any */
1307 if (len & (map_bankwidth(map)-1)) {
1311 mutex_lock(&cfi->chips[chipnum].mutex);
1313 if (cfi->chips[chipnum].state != FL_READY) {
1315 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1317 set_current_state(TASK_UNINTERRUPTIBLE);
1318 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1320 mutex_unlock(&cfi->chips[chipnum].mutex);
1323 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1325 if(signal_pending(current))
1331 tmp_buf = map_read(map, ofs + chipstart);
1333 mutex_unlock(&cfi->chips[chipnum].mutex);
1335 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1337 ret = do_write_oneword(map, &cfi->chips[chipnum],
1350 * FIXME: interleaved mode not tested, and probably not supported!
1352 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1353 unsigned long adr, const u_char *buf,
1356 struct cfi_private *cfi = map->fldrv_priv;
1357 unsigned long timeo = jiffies + HZ;
1358 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1359 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1361 unsigned long cmd_adr;
1368 mutex_lock(&chip->mutex);
1369 ret = get_chip(map, chip, adr, FL_WRITING);
1371 mutex_unlock(&chip->mutex);
1375 datum = map_word_load(map, buf);
1377 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1378 __func__, adr, datum.x[0] );
1380 XIP_INVAL_CACHED_RANGE(map, adr, len);
1382 xip_disable(map, chip, cmd_adr);
1384 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1385 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1386 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1388 /* Write Buffer Load */
1389 map_write(map, CMD(0x25), cmd_adr);
1391 chip->state = FL_WRITING_TO_BUFFER;
1393 /* Write length of data to come */
1394 words = len / map_bankwidth(map);
1395 map_write(map, CMD(words - 1), cmd_adr);
1398 while(z < words * map_bankwidth(map)) {
1399 datum = map_word_load(map, buf);
1400 map_write(map, datum, adr + z);
1402 z += map_bankwidth(map);
1403 buf += map_bankwidth(map);
1405 z -= map_bankwidth(map);
1409 /* Write Buffer Program Confirm: GO GO GO */
1410 map_write(map, CMD(0x29), cmd_adr);
1411 chip->state = FL_WRITING;
1413 INVALIDATE_CACHE_UDELAY(map, chip,
1414 adr, map_bankwidth(map),
1415 chip->word_write_time);
1417 timeo = jiffies + uWriteTimeout;
1420 if (chip->state != FL_WRITING) {
1421 /* Someone's suspended the write. Sleep */
1422 DECLARE_WAITQUEUE(wait, current);
1424 set_current_state(TASK_UNINTERRUPTIBLE);
1425 add_wait_queue(&chip->wq, &wait);
1426 mutex_unlock(&chip->mutex);
1428 remove_wait_queue(&chip->wq, &wait);
1429 timeo = jiffies + (HZ / 2); /* FIXME */
1430 mutex_lock(&chip->mutex);
1434 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1437 if (chip_ready(map, adr)) {
1438 xip_enable(map, chip, adr);
1442 /* Latency issues. Drop the lock, wait a while and retry */
1443 UDELAY(map, chip, adr, 1);
1446 /* reset on all failures. */
1447 map_write( map, CMD(0xF0), chip->start );
1448 xip_enable(map, chip, adr);
1449 /* FIXME - should have reset delay before continuing */
1451 printk(KERN_WARNING "MTD %s(): software timeout\n",
1456 chip->state = FL_READY;
1457 put_chip(map, chip, adr);
1458 mutex_unlock(&chip->mutex);
1464 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1465 size_t *retlen, const u_char *buf)
1467 struct map_info *map = mtd->priv;
1468 struct cfi_private *cfi = map->fldrv_priv;
1469 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1478 chipnum = to >> cfi->chipshift;
1479 ofs = to - (chipnum << cfi->chipshift);
1481 /* If it's not bus-aligned, do the first word write */
1482 if (ofs & (map_bankwidth(map)-1)) {
1483 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1484 if (local_len > len)
1486 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1487 local_len, retlen, buf);
1494 if (ofs >> cfi->chipshift) {
1497 if (chipnum == cfi->numchips)
1502 /* Write buffer is worth it only if more than one word to write... */
1503 while (len >= map_bankwidth(map) * 2) {
1504 /* We must not cross write block boundaries */
1505 int size = wbufsize - (ofs & (wbufsize-1));
1509 if (size % map_bankwidth(map))
1510 size -= size % map_bankwidth(map);
1512 ret = do_write_buffer(map, &cfi->chips[chipnum],
1522 if (ofs >> cfi->chipshift) {
1525 if (chipnum == cfi->numchips)
1531 size_t retlen_dregs = 0;
1533 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1534 len, &retlen_dregs, buf);
1536 *retlen += retlen_dregs;
1545 * Handle devices with one erase region, that only implement
1546 * the chip erase command.
1548 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1550 struct cfi_private *cfi = map->fldrv_priv;
1551 unsigned long timeo = jiffies + HZ;
1552 unsigned long int adr;
1553 DECLARE_WAITQUEUE(wait, current);
1556 adr = cfi->addr_unlock1;
1558 mutex_lock(&chip->mutex);
1559 ret = get_chip(map, chip, adr, FL_WRITING);
1561 mutex_unlock(&chip->mutex);
1565 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1566 __func__, chip->start );
1568 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1570 xip_disable(map, chip, adr);
1572 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1573 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1574 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1575 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1576 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1577 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1579 chip->state = FL_ERASING;
1580 chip->erase_suspended = 0;
1581 chip->in_progress_block_addr = adr;
1583 INVALIDATE_CACHE_UDELAY(map, chip,
1585 chip->erase_time*500);
1587 timeo = jiffies + (HZ*20);
1590 if (chip->state != FL_ERASING) {
1591 /* Someone's suspended the erase. Sleep */
1592 set_current_state(TASK_UNINTERRUPTIBLE);
1593 add_wait_queue(&chip->wq, &wait);
1594 mutex_unlock(&chip->mutex);
1596 remove_wait_queue(&chip->wq, &wait);
1597 mutex_lock(&chip->mutex);
1600 if (chip->erase_suspended) {
1601 /* This erase was suspended and resumed.
1602 Adjust the timeout */
1603 timeo = jiffies + (HZ*20); /* FIXME */
1604 chip->erase_suspended = 0;
1607 if (chip_ready(map, adr))
1610 if (time_after(jiffies, timeo)) {
1611 printk(KERN_WARNING "MTD %s(): software timeout\n",
1616 /* Latency issues. Drop the lock, wait a while and retry */
1617 UDELAY(map, chip, adr, 1000000/HZ);
1619 /* Did we succeed? */
1620 if (!chip_good(map, adr, map_word_ff(map))) {
1621 /* reset on all failures. */
1622 map_write( map, CMD(0xF0), chip->start );
1623 /* FIXME - should have reset delay before continuing */
1628 chip->state = FL_READY;
1629 xip_enable(map, chip, adr);
1630 put_chip(map, chip, adr);
1631 mutex_unlock(&chip->mutex);
1637 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1639 struct cfi_private *cfi = map->fldrv_priv;
1640 unsigned long timeo = jiffies + HZ;
1641 DECLARE_WAITQUEUE(wait, current);
1646 mutex_lock(&chip->mutex);
1647 ret = get_chip(map, chip, adr, FL_ERASING);
1649 mutex_unlock(&chip->mutex);
1653 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1656 XIP_INVAL_CACHED_RANGE(map, adr, len);
1658 xip_disable(map, chip, adr);
1660 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1661 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1662 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1663 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1664 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1665 map_write(map, CMD(0x30), adr);
1667 chip->state = FL_ERASING;
1668 chip->erase_suspended = 0;
1669 chip->in_progress_block_addr = adr;
1671 INVALIDATE_CACHE_UDELAY(map, chip,
1673 chip->erase_time*500);
1675 timeo = jiffies + (HZ*20);
1678 if (chip->state != FL_ERASING) {
1679 /* Someone's suspended the erase. Sleep */
1680 set_current_state(TASK_UNINTERRUPTIBLE);
1681 add_wait_queue(&chip->wq, &wait);
1682 mutex_unlock(&chip->mutex);
1684 remove_wait_queue(&chip->wq, &wait);
1685 mutex_lock(&chip->mutex);
1688 if (chip->erase_suspended) {
1689 /* This erase was suspended and resumed.
1690 Adjust the timeout */
1691 timeo = jiffies + (HZ*20); /* FIXME */
1692 chip->erase_suspended = 0;
1695 if (chip_ready(map, adr)) {
1696 xip_enable(map, chip, adr);
1700 if (time_after(jiffies, timeo)) {
1701 xip_enable(map, chip, adr);
1702 printk(KERN_WARNING "MTD %s(): software timeout\n",
1707 /* Latency issues. Drop the lock, wait a while and retry */
1708 UDELAY(map, chip, adr, 1000000/HZ);
1710 /* Did we succeed? */
1711 if (!chip_good(map, adr, map_word_ff(map))) {
1712 /* reset on all failures. */
1713 map_write( map, CMD(0xF0), chip->start );
1714 /* FIXME - should have reset delay before continuing */
1719 chip->state = FL_READY;
1720 put_chip(map, chip, adr);
1721 mutex_unlock(&chip->mutex);
1726 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1728 unsigned long ofs, len;
1734 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1738 instr->state = MTD_ERASE_DONE;
1739 mtd_erase_callback(instr);
1745 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1747 struct map_info *map = mtd->priv;
1748 struct cfi_private *cfi = map->fldrv_priv;
1751 if (instr->addr != 0)
1754 if (instr->len != mtd->size)
1757 ret = do_erase_chip(map, &cfi->chips[0]);
1761 instr->state = MTD_ERASE_DONE;
1762 mtd_erase_callback(instr);
1767 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1768 unsigned long adr, int len, void *thunk)
1770 struct cfi_private *cfi = map->fldrv_priv;
1773 mutex_lock(&chip->mutex);
1774 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1777 chip->state = FL_LOCKING;
1779 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1780 __func__, adr, len);
1782 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1783 cfi->device_type, NULL);
1784 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1785 cfi->device_type, NULL);
1786 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1787 cfi->device_type, NULL);
1788 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1789 cfi->device_type, NULL);
1790 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1791 cfi->device_type, NULL);
1792 map_write(map, CMD(0x40), chip->start + adr);
1794 chip->state = FL_READY;
1795 put_chip(map, chip, adr + chip->start);
1799 mutex_unlock(&chip->mutex);
1803 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1804 unsigned long adr, int len, void *thunk)
1806 struct cfi_private *cfi = map->fldrv_priv;
1809 mutex_lock(&chip->mutex);
1810 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1813 chip->state = FL_UNLOCKING;
1815 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1816 __func__, adr, len);
1818 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1819 cfi->device_type, NULL);
1820 map_write(map, CMD(0x70), adr);
1822 chip->state = FL_READY;
1823 put_chip(map, chip, adr + chip->start);
1827 mutex_unlock(&chip->mutex);
1831 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1833 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1836 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1838 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1842 static void cfi_amdstd_sync (struct mtd_info *mtd)
1844 struct map_info *map = mtd->priv;
1845 struct cfi_private *cfi = map->fldrv_priv;
1847 struct flchip *chip;
1849 DECLARE_WAITQUEUE(wait, current);
1851 for (i=0; !ret && i<cfi->numchips; i++) {
1852 chip = &cfi->chips[i];
1855 mutex_lock(&chip->mutex);
1857 switch(chip->state) {
1861 case FL_JEDEC_QUERY:
1862 chip->oldstate = chip->state;
1863 chip->state = FL_SYNCING;
1864 /* No need to wake_up() on this state change -
1865 * as the whole point is that nobody can do anything
1866 * with the chip now anyway.
1869 mutex_unlock(&chip->mutex);
1873 /* Not an idle state */
1874 set_current_state(TASK_UNINTERRUPTIBLE);
1875 add_wait_queue(&chip->wq, &wait);
1877 mutex_unlock(&chip->mutex);
1881 remove_wait_queue(&chip->wq, &wait);
1887 /* Unlock the chips again */
1889 for (i--; i >=0; i--) {
1890 chip = &cfi->chips[i];
1892 mutex_lock(&chip->mutex);
1894 if (chip->state == FL_SYNCING) {
1895 chip->state = chip->oldstate;
1898 mutex_unlock(&chip->mutex);
1903 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1905 struct map_info *map = mtd->priv;
1906 struct cfi_private *cfi = map->fldrv_priv;
1908 struct flchip *chip;
1911 for (i=0; !ret && i<cfi->numchips; i++) {
1912 chip = &cfi->chips[i];
1914 mutex_lock(&chip->mutex);
1916 switch(chip->state) {
1920 case FL_JEDEC_QUERY:
1921 chip->oldstate = chip->state;
1922 chip->state = FL_PM_SUSPENDED;
1923 /* No need to wake_up() on this state change -
1924 * as the whole point is that nobody can do anything
1925 * with the chip now anyway.
1927 case FL_PM_SUSPENDED:
1934 mutex_unlock(&chip->mutex);
1937 /* Unlock the chips again */
1940 for (i--; i >=0; i--) {
1941 chip = &cfi->chips[i];
1943 mutex_lock(&chip->mutex);
1945 if (chip->state == FL_PM_SUSPENDED) {
1946 chip->state = chip->oldstate;
1949 mutex_unlock(&chip->mutex);
1957 static void cfi_amdstd_resume(struct mtd_info *mtd)
1959 struct map_info *map = mtd->priv;
1960 struct cfi_private *cfi = map->fldrv_priv;
1962 struct flchip *chip;
1964 for (i=0; i<cfi->numchips; i++) {
1966 chip = &cfi->chips[i];
1968 mutex_lock(&chip->mutex);
1970 if (chip->state == FL_PM_SUSPENDED) {
1971 chip->state = FL_READY;
1972 map_write(map, CMD(0xF0), chip->start);
1976 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1978 mutex_unlock(&chip->mutex);
1984 * Ensure that the flash device is put back into read array mode before
1985 * unloading the driver or rebooting. On some systems, rebooting while
1986 * the flash is in query/program/erase mode will prevent the CPU from
1987 * fetching the bootloader code, requiring a hard reset or power cycle.
1989 static int cfi_amdstd_reset(struct mtd_info *mtd)
1991 struct map_info *map = mtd->priv;
1992 struct cfi_private *cfi = map->fldrv_priv;
1994 struct flchip *chip;
1996 for (i = 0; i < cfi->numchips; i++) {
1998 chip = &cfi->chips[i];
2000 mutex_lock(&chip->mutex);
2002 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2004 map_write(map, CMD(0xF0), chip->start);
2005 chip->state = FL_SHUTDOWN;
2006 put_chip(map, chip, chip->start);
2009 mutex_unlock(&chip->mutex);
2016 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2019 struct mtd_info *mtd;
2021 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2022 cfi_amdstd_reset(mtd);
2027 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2029 struct map_info *map = mtd->priv;
2030 struct cfi_private *cfi = map->fldrv_priv;
2032 cfi_amdstd_reset(mtd);
2033 unregister_reboot_notifier(&mtd->reboot_notifier);
2034 kfree(cfi->cmdset_priv);
2037 kfree(mtd->eraseregions);
2040 MODULE_LICENSE("GPL");
2041 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2042 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");