2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/init.h>
29 #include <asm/byteorder.h>
31 #include <linux/errno.h>
32 #include <linux/slab.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/reboot.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
45 #define MAX_WORD_RETRIES 3
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
63 static void cfi_amdstd_destroy(struct mtd_info *);
65 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
66 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
68 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
69 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
72 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
73 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
75 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
76 .probe = NULL, /* Not usable directly */
77 .destroy = cfi_amdstd_destroy,
78 .name = "cfi_cmdset_0002",
83 /* #define DEBUG_CFI_FEATURES */
86 #ifdef DEBUG_CFI_FEATURES
87 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
89 const char* erase_suspend[3] = {
90 "Not supported", "Read only", "Read/write"
92 const char* top_bottom[6] = {
93 "No WP", "8x8KiB sectors at top & bottom, no WP",
94 "Bottom boot", "Top boot",
95 "Uniform, Bottom WP", "Uniform, Top WP"
98 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
99 printk(" Address sensitive unlock: %s\n",
100 (extp->SiliconRevision & 1) ? "Not required" : "Required");
102 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
103 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
105 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
107 if (extp->BlkProt == 0)
108 printk(" Block protection: Not supported\n");
110 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
113 printk(" Temporary block unprotect: %s\n",
114 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
115 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
116 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
117 printk(" Burst mode: %s\n",
118 extp->BurstMode ? "Supported" : "Not supported");
119 if (extp->PageMode == 0)
120 printk(" Page mode: Not supported\n");
122 printk(" Page mode: %d word page\n", extp->PageMode << 2);
124 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
125 extp->VppMin >> 4, extp->VppMin & 0xf);
126 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
127 extp->VppMax >> 4, extp->VppMax & 0xf);
129 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
130 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
132 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
136 #ifdef AMD_BOOTLOC_BUG
137 /* Wheee. Bring me the head of someone at AMD. */
138 static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
140 struct map_info *map = mtd->priv;
141 struct cfi_private *cfi = map->fldrv_priv;
142 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
143 __u8 major = extp->MajorVersion;
144 __u8 minor = extp->MinorVersion;
146 if (((major << 8) | minor) < 0x3131) {
147 /* CFI version 1.0 => don't trust bootloc */
149 DEBUG(MTD_DEBUG_LEVEL1,
150 "%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
151 map->name, cfi->mfr, cfi->id);
153 /* AFAICS all 29LV400 with a bottom boot block have a device ID
154 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
155 * These were badly detected as they have the 0x80 bit set
156 * so treat them as a special case.
158 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
160 /* Macronix added CFI to their 2nd generation
161 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
162 * Fujitsu, Spansion, EON, ESI and older Macronix)
165 * Therefore also check the manufacturer.
166 * This reduces the risk of false detection due to
167 * the 8-bit device ID.
169 (cfi->mfr == CFI_MFR_MACRONIX)) {
170 DEBUG(MTD_DEBUG_LEVEL1,
171 "%s: Macronix MX29LV400C with bottom boot block"
172 " detected\n", map->name);
173 extp->TopBottom = 2; /* bottom boot */
175 if (cfi->id & 0x80) {
176 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
177 extp->TopBottom = 3; /* top boot */
179 extp->TopBottom = 2; /* bottom boot */
182 DEBUG(MTD_DEBUG_LEVEL1,
183 "%s: AMD CFI PRI V%c.%c has no boot block field;"
184 " deduced %s from Device ID\n", map->name, major, minor,
185 extp->TopBottom == 2 ? "bottom" : "top");
190 static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
192 struct map_info *map = mtd->priv;
193 struct cfi_private *cfi = map->fldrv_priv;
194 if (cfi->cfiq->BufWriteTimeoutTyp) {
195 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
196 mtd->write = cfi_amdstd_write_buffers;
200 /* Atmel chips don't use the same PRI format as AMD chips */
201 static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
203 struct map_info *map = mtd->priv;
204 struct cfi_private *cfi = map->fldrv_priv;
205 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
206 struct cfi_pri_atmel atmel_pri;
208 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
209 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
211 if (atmel_pri.Features & 0x02)
212 extp->EraseSuspend = 2;
214 /* Some chips got it backwards... */
215 if (cfi->id == AT49BV6416) {
216 if (atmel_pri.BottomBoot)
221 if (atmel_pri.BottomBoot)
227 /* burst write mode not supported */
228 cfi->cfiq->BufWriteTimeoutTyp = 0;
229 cfi->cfiq->BufWriteTimeoutMax = 0;
232 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
234 /* Setup for chips with a secsi area */
235 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
236 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
239 static void fixup_use_erase_chip(struct mtd_info *mtd, void *param)
241 struct map_info *map = mtd->priv;
242 struct cfi_private *cfi = map->fldrv_priv;
243 if ((cfi->cfiq->NumEraseRegions == 1) &&
244 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
245 mtd->erase = cfi_amdstd_erase_chip;
251 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
254 static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
256 mtd->lock = cfi_atmel_lock;
257 mtd->unlock = cfi_atmel_unlock;
258 mtd->flags |= MTD_POWERUP_LOCK;
261 static void fixup_s29gl064n_sectors(struct mtd_info *mtd, void *param)
263 struct map_info *map = mtd->priv;
264 struct cfi_private *cfi = map->fldrv_priv;
266 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
267 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
268 pr_warning("%s: Bad S29GL064N CFI data, adjust from 64 to 128 sectors\n", mtd->name);
272 static void fixup_s29gl032n_sectors(struct mtd_info *mtd, void *param)
274 struct map_info *map = mtd->priv;
275 struct cfi_private *cfi = map->fldrv_priv;
277 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
278 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
279 pr_warning("%s: Bad S29GL032N CFI data, adjust from 127 to 63 sectors\n", mtd->name);
283 static struct cfi_fixup cfi_fixup_table[] = {
284 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
285 #ifdef AMD_BOOTLOC_BUG
286 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
287 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock, NULL },
289 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
290 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },
291 { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, },
292 { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, },
293 { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, },
294 { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, },
295 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors, NULL, },
296 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors, NULL, },
297 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors, NULL, },
298 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors, NULL, },
299 #if !FORCE_WORD_WRITE
300 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
304 static struct cfi_fixup jedec_fixup_table[] = {
305 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
306 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock, NULL, },
307 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
311 static struct cfi_fixup fixup_table[] = {
312 /* The CFI vendor ids and the JEDEC vendor IDs appear
313 * to be common. It is like the devices id's are as
314 * well. This table is to pick all cases where
315 * we know that is the case.
317 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
318 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
323 static void cfi_fixup_major_minor(struct cfi_private *cfi,
324 struct cfi_pri_amdstd *extp)
326 if (cfi->mfr == CFI_MFR_SAMSUNG && cfi->id == 0x257e &&
327 extp->MajorVersion == '0')
328 extp->MajorVersion = '1';
331 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
333 struct cfi_private *cfi = map->fldrv_priv;
334 struct mtd_info *mtd;
337 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
339 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
343 mtd->type = MTD_NORFLASH;
345 /* Fill in the default mtd operations */
346 mtd->erase = cfi_amdstd_erase_varsize;
347 mtd->write = cfi_amdstd_write_words;
348 mtd->read = cfi_amdstd_read;
349 mtd->sync = cfi_amdstd_sync;
350 mtd->suspend = cfi_amdstd_suspend;
351 mtd->resume = cfi_amdstd_resume;
352 mtd->flags = MTD_CAP_NORFLASH;
353 mtd->name = map->name;
356 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
358 if (cfi->cfi_mode==CFI_MODE_CFI){
359 unsigned char bootloc;
360 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
361 struct cfi_pri_amdstd *extp;
363 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
366 * It's a real CFI chip, not one for which the probe
367 * routine faked a CFI structure.
369 cfi_fixup_major_minor(cfi, extp);
371 if (extp->MajorVersion != '1' ||
372 (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
373 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
374 "version %c.%c.\n", extp->MajorVersion,
381 /* Install our own private info structure */
382 cfi->cmdset_priv = extp;
384 /* Apply cfi device specific fixups */
385 cfi_fixup(mtd, cfi_fixup_table);
387 #ifdef DEBUG_CFI_FEATURES
388 /* Tell the user about it in lots of lovely detail */
389 cfi_tell_features(extp);
392 bootloc = extp->TopBottom;
393 if ((bootloc < 2) || (bootloc > 5)) {
394 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
395 "bank location (%d). Assuming bottom.\n",
400 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
401 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
403 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
404 int j = (cfi->cfiq->NumEraseRegions-1)-i;
407 swap = cfi->cfiq->EraseRegionInfo[i];
408 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
409 cfi->cfiq->EraseRegionInfo[j] = swap;
412 /* Set the default CFI lock/unlock addresses */
413 cfi->addr_unlock1 = 0x555;
414 cfi->addr_unlock2 = 0x2aa;
417 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
423 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
424 /* Apply jedec specific fixups */
425 cfi_fixup(mtd, jedec_fixup_table);
427 /* Apply generic fixups */
428 cfi_fixup(mtd, fixup_table);
430 for (i=0; i< cfi->numchips; i++) {
431 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
432 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
433 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
434 cfi->chips[i].ref_point_counter = 0;
435 init_waitqueue_head(&(cfi->chips[i].wq));
438 map->fldrv = &cfi_amdstd_chipdrv;
440 return cfi_amdstd_setup(mtd);
442 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
444 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
446 struct map_info *map = mtd->priv;
447 struct cfi_private *cfi = map->fldrv_priv;
448 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
449 unsigned long offset = 0;
452 printk(KERN_NOTICE "number of %s chips: %d\n",
453 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
454 /* Select the correct geometry setup */
455 mtd->size = devsize * cfi->numchips;
457 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
458 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
459 * mtd->numeraseregions, GFP_KERNEL);
460 if (!mtd->eraseregions) {
461 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
465 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
466 unsigned long ernum, ersize;
467 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
468 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
470 if (mtd->erasesize < ersize) {
471 mtd->erasesize = ersize;
473 for (j=0; j<cfi->numchips; j++) {
474 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
475 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
476 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
478 offset += (ersize * ernum);
480 if (offset != devsize) {
482 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
487 for (i=0; i<mtd->numeraseregions;i++){
488 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
489 i,mtd->eraseregions[i].offset,
490 mtd->eraseregions[i].erasesize,
491 mtd->eraseregions[i].numblocks);
495 __module_get(THIS_MODULE);
496 register_reboot_notifier(&mtd->reboot_notifier);
500 kfree(mtd->eraseregions);
502 kfree(cfi->cmdset_priv);
508 * Return true if the chip is ready.
510 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
511 * non-suspended sector) and is indicated by no toggle bits toggling.
513 * Note that anything more complicated than checking if no bits are toggling
514 * (including checking DQ5 for an error status) is tricky to get working
515 * correctly and is therefore not done (particulary with interleaved chips
516 * as each chip must be checked independantly of the others).
518 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
522 d = map_read(map, addr);
523 t = map_read(map, addr);
525 return map_word_equal(map, d, t);
529 * Return true if the chip is ready and has the correct value.
531 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
532 * non-suspended sector) and it is indicated by no bits toggling.
534 * Error are indicated by toggling bits or bits held with the wrong value,
535 * or with bits toggling.
537 * Note that anything more complicated than checking if no bits are toggling
538 * (including checking DQ5 for an error status) is tricky to get working
539 * correctly and is therefore not done (particulary with interleaved chips
540 * as each chip must be checked independantly of the others).
543 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
547 oldd = map_read(map, addr);
548 curd = map_read(map, addr);
550 return map_word_equal(map, oldd, curd) &&
551 map_word_equal(map, curd, expected);
554 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
556 DECLARE_WAITQUEUE(wait, current);
557 struct cfi_private *cfi = map->fldrv_priv;
559 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
562 timeo = jiffies + HZ;
564 switch (chip->state) {
568 if (chip_ready(map, adr))
571 if (time_after(jiffies, timeo)) {
572 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
575 mutex_unlock(&chip->mutex);
577 mutex_lock(&chip->mutex);
578 /* Someone else might have been playing with it. */
588 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
589 !(mode == FL_READY || mode == FL_POINT ||
590 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
593 /* We could check to see if we're trying to access the sector
594 * that is currently being erased. However, no user will try
595 * anything like that so we just wait for the timeout. */
598 /* It's harmless to issue the Erase-Suspend and Erase-Resume
599 * commands when the erase algorithm isn't in progress. */
600 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
601 chip->oldstate = FL_ERASING;
602 chip->state = FL_ERASE_SUSPENDING;
603 chip->erase_suspended = 1;
605 if (chip_ready(map, adr))
608 if (time_after(jiffies, timeo)) {
609 /* Should have suspended the erase by now.
610 * Send an Erase-Resume command as either
611 * there was an error (so leave the erase
612 * routine to recover from it) or we trying to
613 * use the erase-in-progress sector. */
614 map_write(map, CMD(0x30), chip->in_progress_block_addr);
615 chip->state = FL_ERASING;
616 chip->oldstate = FL_READY;
617 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
621 mutex_unlock(&chip->mutex);
623 mutex_lock(&chip->mutex);
624 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
625 So we can just loop here. */
627 chip->state = FL_READY;
630 case FL_XIP_WHILE_ERASING:
631 if (mode != FL_READY && mode != FL_POINT &&
632 (!cfip || !(cfip->EraseSuspend&2)))
634 chip->oldstate = chip->state;
635 chip->state = FL_READY;
639 /* The machine is rebooting */
643 /* Only if there's no operation suspended... */
644 if (mode == FL_READY && chip->oldstate == FL_READY)
649 set_current_state(TASK_UNINTERRUPTIBLE);
650 add_wait_queue(&chip->wq, &wait);
651 mutex_unlock(&chip->mutex);
653 remove_wait_queue(&chip->wq, &wait);
654 mutex_lock(&chip->mutex);
660 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
662 struct cfi_private *cfi = map->fldrv_priv;
664 switch(chip->oldstate) {
666 chip->state = chip->oldstate;
667 map_write(map, CMD(0x30), chip->in_progress_block_addr);
668 chip->oldstate = FL_READY;
669 chip->state = FL_ERASING;
672 case FL_XIP_WHILE_ERASING:
673 chip->state = chip->oldstate;
674 chip->oldstate = FL_READY;
679 /* We should really make set_vpp() count, rather than doing this */
683 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
688 #ifdef CONFIG_MTD_XIP
691 * No interrupt what so ever can be serviced while the flash isn't in array
692 * mode. This is ensured by the xip_disable() and xip_enable() functions
693 * enclosing any code path where the flash is known not to be in array mode.
694 * And within a XIP disabled code path, only functions marked with __xipram
695 * may be called and nothing else (it's a good thing to inspect generated
696 * assembly to make sure inline functions were actually inlined and that gcc
697 * didn't emit calls to its own support functions). Also configuring MTD CFI
698 * support to a single buswidth and a single interleave is also recommended.
701 static void xip_disable(struct map_info *map, struct flchip *chip,
704 /* TODO: chips with no XIP use should ignore and return */
705 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
709 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
712 struct cfi_private *cfi = map->fldrv_priv;
714 if (chip->state != FL_POINT && chip->state != FL_READY) {
715 map_write(map, CMD(0xf0), adr);
716 chip->state = FL_READY;
718 (void) map_read(map, adr);
724 * When a delay is required for the flash operation to complete, the
725 * xip_udelay() function is polling for both the given timeout and pending
726 * (but still masked) hardware interrupts. Whenever there is an interrupt
727 * pending then the flash erase operation is suspended, array mode restored
728 * and interrupts unmasked. Task scheduling might also happen at that
729 * point. The CPU eventually returns from the interrupt or the call to
730 * schedule() and the suspended flash operation is resumed for the remaining
731 * of the delay period.
733 * Warning: this function _will_ fool interrupt latency tracing tools.
736 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
737 unsigned long adr, int usec)
739 struct cfi_private *cfi = map->fldrv_priv;
740 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
741 map_word status, OK = CMD(0x80);
742 unsigned long suspended, start = xip_currtime();
747 if (xip_irqpending() && extp &&
748 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
749 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
751 * Let's suspend the erase operation when supported.
752 * Note that we currently don't try to suspend
753 * interleaved chips if there is already another
754 * operation suspended (imagine what happens
755 * when one chip was already done with the current
756 * operation while another chip suspended it, then
757 * we resume the whole thing at once). Yes, it
760 map_write(map, CMD(0xb0), adr);
761 usec -= xip_elapsed_since(start);
762 suspended = xip_currtime();
764 if (xip_elapsed_since(suspended) > 100000) {
766 * The chip doesn't want to suspend
767 * after waiting for 100 msecs.
768 * This is a critical error but there
769 * is not much we can do here.
773 status = map_read(map, adr);
774 } while (!map_word_andequal(map, status, OK, OK));
776 /* Suspend succeeded */
777 oldstate = chip->state;
778 if (!map_word_bitsset(map, status, CMD(0x40)))
780 chip->state = FL_XIP_WHILE_ERASING;
781 chip->erase_suspended = 1;
782 map_write(map, CMD(0xf0), adr);
783 (void) map_read(map, adr);
786 mutex_unlock(&chip->mutex);
791 * We're back. However someone else might have
792 * decided to go write to the chip if we are in
793 * a suspended erase state. If so let's wait
796 mutex_lock(&chip->mutex);
797 while (chip->state != FL_XIP_WHILE_ERASING) {
798 DECLARE_WAITQUEUE(wait, current);
799 set_current_state(TASK_UNINTERRUPTIBLE);
800 add_wait_queue(&chip->wq, &wait);
801 mutex_unlock(&chip->mutex);
803 remove_wait_queue(&chip->wq, &wait);
804 mutex_lock(&chip->mutex);
806 /* Disallow XIP again */
809 /* Resume the write or erase operation */
810 map_write(map, CMD(0x30), adr);
811 chip->state = oldstate;
812 start = xip_currtime();
813 } else if (usec >= 1000000/HZ) {
815 * Try to save on CPU power when waiting delay
816 * is at least a system timer tick period.
817 * No need to be extremely accurate here.
821 status = map_read(map, adr);
822 } while (!map_word_andequal(map, status, OK, OK)
823 && xip_elapsed_since(start) < usec);
826 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
829 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
830 * the flash is actively programming or erasing since we have to poll for
831 * the operation to complete anyway. We can't do that in a generic way with
832 * a XIP setup so do it before the actual flash operation in this case
833 * and stub it out from INVALIDATE_CACHE_UDELAY.
835 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
836 INVALIDATE_CACHED_RANGE(map, from, size)
838 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
839 UDELAY(map, chip, adr, usec)
844 * Activating this XIP support changes the way the code works a bit. For
845 * example the code to suspend the current process when concurrent access
846 * happens is never executed because xip_udelay() will always return with the
847 * same chip state as it was entered with. This is why there is no care for
848 * the presence of add_wait_queue() or schedule() calls from within a couple
849 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
850 * The queueing and scheduling are always happening within xip_udelay().
852 * Similarly, get_chip() and put_chip() just happen to always be executed
853 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
854 * is in array mode, therefore never executing many cases therein and not
855 * causing any problem with XIP.
860 #define xip_disable(map, chip, adr)
861 #define xip_enable(map, chip, adr)
862 #define XIP_INVAL_CACHED_RANGE(x...)
864 #define UDELAY(map, chip, adr, usec) \
866 mutex_unlock(&chip->mutex); \
868 mutex_lock(&chip->mutex); \
871 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
873 mutex_unlock(&chip->mutex); \
874 INVALIDATE_CACHED_RANGE(map, adr, len); \
876 mutex_lock(&chip->mutex); \
881 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
883 unsigned long cmd_addr;
884 struct cfi_private *cfi = map->fldrv_priv;
889 /* Ensure cmd read/writes are aligned. */
890 cmd_addr = adr & ~(map_bankwidth(map)-1);
892 mutex_lock(&chip->mutex);
893 ret = get_chip(map, chip, cmd_addr, FL_READY);
895 mutex_unlock(&chip->mutex);
899 if (chip->state != FL_POINT && chip->state != FL_READY) {
900 map_write(map, CMD(0xf0), cmd_addr);
901 chip->state = FL_READY;
904 map_copy_from(map, buf, adr, len);
906 put_chip(map, chip, cmd_addr);
908 mutex_unlock(&chip->mutex);
913 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
915 struct map_info *map = mtd->priv;
916 struct cfi_private *cfi = map->fldrv_priv;
921 /* ofs: offset within the first chip that the first read should start */
923 chipnum = (from >> cfi->chipshift);
924 ofs = from - (chipnum << cfi->chipshift);
930 unsigned long thislen;
932 if (chipnum >= cfi->numchips)
935 if ((len + ofs -1) >> cfi->chipshift)
936 thislen = (1<<cfi->chipshift) - ofs;
940 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
955 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
957 DECLARE_WAITQUEUE(wait, current);
958 unsigned long timeo = jiffies + HZ;
959 struct cfi_private *cfi = map->fldrv_priv;
962 mutex_lock(&chip->mutex);
964 if (chip->state != FL_READY){
966 printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
968 set_current_state(TASK_UNINTERRUPTIBLE);
969 add_wait_queue(&chip->wq, &wait);
971 mutex_unlock(&chip->mutex);
974 remove_wait_queue(&chip->wq, &wait);
976 if(signal_pending(current))
979 timeo = jiffies + HZ;
986 chip->state = FL_READY;
988 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
989 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
990 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
992 map_copy_from(map, buf, adr, len);
994 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
995 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
996 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
997 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1000 mutex_unlock(&chip->mutex);
1005 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1007 struct map_info *map = mtd->priv;
1008 struct cfi_private *cfi = map->fldrv_priv;
1014 /* ofs: offset within the first chip that the first read should start */
1016 /* 8 secsi bytes per chip */
1024 unsigned long thislen;
1026 if (chipnum >= cfi->numchips)
1029 if ((len + ofs -1) >> 3)
1030 thislen = (1<<3) - ofs;
1034 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1049 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
1051 struct cfi_private *cfi = map->fldrv_priv;
1052 unsigned long timeo = jiffies + HZ;
1054 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1055 * have a max write time of a few hundreds usec). However, we should
1056 * use the maximum timeout value given by the chip at probe time
1057 * instead. Unfortunately, struct flchip does have a field for
1058 * maximum timeout, only for typical which can be far too short
1059 * depending of the conditions. The ' + 1' is to avoid having a
1060 * timeout of 0 jiffies if HZ is smaller than 1000.
1062 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1069 mutex_lock(&chip->mutex);
1070 ret = get_chip(map, chip, adr, FL_WRITING);
1072 mutex_unlock(&chip->mutex);
1076 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1077 __func__, adr, datum.x[0] );
1080 * Check for a NOP for the case when the datum to write is already
1081 * present - it saves time and works around buggy chips that corrupt
1082 * data at other locations when 0xff is written to a location that
1083 * already contains 0xff.
1085 oldd = map_read(map, adr);
1086 if (map_word_equal(map, oldd, datum)) {
1087 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1092 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1094 xip_disable(map, chip, adr);
1096 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1097 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1098 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1099 map_write(map, datum, adr);
1100 chip->state = FL_WRITING;
1102 INVALIDATE_CACHE_UDELAY(map, chip,
1103 adr, map_bankwidth(map),
1104 chip->word_write_time);
1106 /* See comment above for timeout value. */
1107 timeo = jiffies + uWriteTimeout;
1109 if (chip->state != FL_WRITING) {
1110 /* Someone's suspended the write. Sleep */
1111 DECLARE_WAITQUEUE(wait, current);
1113 set_current_state(TASK_UNINTERRUPTIBLE);
1114 add_wait_queue(&chip->wq, &wait);
1115 mutex_unlock(&chip->mutex);
1117 remove_wait_queue(&chip->wq, &wait);
1118 timeo = jiffies + (HZ / 2); /* FIXME */
1119 mutex_lock(&chip->mutex);
1123 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1124 xip_enable(map, chip, adr);
1125 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1126 xip_disable(map, chip, adr);
1130 if (chip_ready(map, adr))
1133 /* Latency issues. Drop the lock, wait a while and retry */
1134 UDELAY(map, chip, adr, 1);
1136 /* Did we succeed? */
1137 if (!chip_good(map, adr, datum)) {
1138 /* reset on all failures. */
1139 map_write( map, CMD(0xF0), chip->start );
1140 /* FIXME - should have reset delay before continuing */
1142 if (++retry_cnt <= MAX_WORD_RETRIES)
1147 xip_enable(map, chip, adr);
1149 chip->state = FL_READY;
1150 put_chip(map, chip, adr);
1151 mutex_unlock(&chip->mutex);
1157 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1158 size_t *retlen, const u_char *buf)
1160 struct map_info *map = mtd->priv;
1161 struct cfi_private *cfi = map->fldrv_priv;
1164 unsigned long ofs, chipstart;
1165 DECLARE_WAITQUEUE(wait, current);
1171 chipnum = to >> cfi->chipshift;
1172 ofs = to - (chipnum << cfi->chipshift);
1173 chipstart = cfi->chips[chipnum].start;
1175 /* If it's not bus-aligned, do the first byte write */
1176 if (ofs & (map_bankwidth(map)-1)) {
1177 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1178 int i = ofs - bus_ofs;
1183 mutex_lock(&cfi->chips[chipnum].mutex);
1185 if (cfi->chips[chipnum].state != FL_READY) {
1187 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1189 set_current_state(TASK_UNINTERRUPTIBLE);
1190 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1192 mutex_unlock(&cfi->chips[chipnum].mutex);
1195 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1197 if(signal_pending(current))
1203 /* Load 'tmp_buf' with old contents of flash */
1204 tmp_buf = map_read(map, bus_ofs+chipstart);
1206 mutex_unlock(&cfi->chips[chipnum].mutex);
1208 /* Number of bytes to copy from buffer */
1209 n = min_t(int, len, map_bankwidth(map)-i);
1211 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1213 ret = do_write_oneword(map, &cfi->chips[chipnum],
1223 if (ofs >> cfi->chipshift) {
1226 if (chipnum == cfi->numchips)
1231 /* We are now aligned, write as much as possible */
1232 while(len >= map_bankwidth(map)) {
1235 datum = map_word_load(map, buf);
1237 ret = do_write_oneword(map, &cfi->chips[chipnum],
1242 ofs += map_bankwidth(map);
1243 buf += map_bankwidth(map);
1244 (*retlen) += map_bankwidth(map);
1245 len -= map_bankwidth(map);
1247 if (ofs >> cfi->chipshift) {
1250 if (chipnum == cfi->numchips)
1252 chipstart = cfi->chips[chipnum].start;
1256 /* Write the trailing bytes if any */
1257 if (len & (map_bankwidth(map)-1)) {
1261 mutex_lock(&cfi->chips[chipnum].mutex);
1263 if (cfi->chips[chipnum].state != FL_READY) {
1265 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1267 set_current_state(TASK_UNINTERRUPTIBLE);
1268 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1270 mutex_unlock(&cfi->chips[chipnum].mutex);
1273 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1275 if(signal_pending(current))
1281 tmp_buf = map_read(map, ofs + chipstart);
1283 mutex_unlock(&cfi->chips[chipnum].mutex);
1285 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1287 ret = do_write_oneword(map, &cfi->chips[chipnum],
1300 * FIXME: interleaved mode not tested, and probably not supported!
1302 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1303 unsigned long adr, const u_char *buf,
1306 struct cfi_private *cfi = map->fldrv_priv;
1307 unsigned long timeo = jiffies + HZ;
1308 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1309 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1311 unsigned long cmd_adr;
1318 mutex_lock(&chip->mutex);
1319 ret = get_chip(map, chip, adr, FL_WRITING);
1321 mutex_unlock(&chip->mutex);
1325 datum = map_word_load(map, buf);
1327 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1328 __func__, adr, datum.x[0] );
1330 XIP_INVAL_CACHED_RANGE(map, adr, len);
1332 xip_disable(map, chip, cmd_adr);
1334 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1335 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1336 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1338 /* Write Buffer Load */
1339 map_write(map, CMD(0x25), cmd_adr);
1341 chip->state = FL_WRITING_TO_BUFFER;
1343 /* Write length of data to come */
1344 words = len / map_bankwidth(map);
1345 map_write(map, CMD(words - 1), cmd_adr);
1348 while(z < words * map_bankwidth(map)) {
1349 datum = map_word_load(map, buf);
1350 map_write(map, datum, adr + z);
1352 z += map_bankwidth(map);
1353 buf += map_bankwidth(map);
1355 z -= map_bankwidth(map);
1359 /* Write Buffer Program Confirm: GO GO GO */
1360 map_write(map, CMD(0x29), cmd_adr);
1361 chip->state = FL_WRITING;
1363 INVALIDATE_CACHE_UDELAY(map, chip,
1364 adr, map_bankwidth(map),
1365 chip->word_write_time);
1367 timeo = jiffies + uWriteTimeout;
1370 if (chip->state != FL_WRITING) {
1371 /* Someone's suspended the write. Sleep */
1372 DECLARE_WAITQUEUE(wait, current);
1374 set_current_state(TASK_UNINTERRUPTIBLE);
1375 add_wait_queue(&chip->wq, &wait);
1376 mutex_unlock(&chip->mutex);
1378 remove_wait_queue(&chip->wq, &wait);
1379 timeo = jiffies + (HZ / 2); /* FIXME */
1380 mutex_lock(&chip->mutex);
1384 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1387 if (chip_ready(map, adr)) {
1388 xip_enable(map, chip, adr);
1392 /* Latency issues. Drop the lock, wait a while and retry */
1393 UDELAY(map, chip, adr, 1);
1396 /* reset on all failures. */
1397 map_write( map, CMD(0xF0), chip->start );
1398 xip_enable(map, chip, adr);
1399 /* FIXME - should have reset delay before continuing */
1401 printk(KERN_WARNING "MTD %s(): software timeout\n",
1406 chip->state = FL_READY;
1407 put_chip(map, chip, adr);
1408 mutex_unlock(&chip->mutex);
1414 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1415 size_t *retlen, const u_char *buf)
1417 struct map_info *map = mtd->priv;
1418 struct cfi_private *cfi = map->fldrv_priv;
1419 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1428 chipnum = to >> cfi->chipshift;
1429 ofs = to - (chipnum << cfi->chipshift);
1431 /* If it's not bus-aligned, do the first word write */
1432 if (ofs & (map_bankwidth(map)-1)) {
1433 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1434 if (local_len > len)
1436 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1437 local_len, retlen, buf);
1444 if (ofs >> cfi->chipshift) {
1447 if (chipnum == cfi->numchips)
1452 /* Write buffer is worth it only if more than one word to write... */
1453 while (len >= map_bankwidth(map) * 2) {
1454 /* We must not cross write block boundaries */
1455 int size = wbufsize - (ofs & (wbufsize-1));
1459 if (size % map_bankwidth(map))
1460 size -= size % map_bankwidth(map);
1462 ret = do_write_buffer(map, &cfi->chips[chipnum],
1472 if (ofs >> cfi->chipshift) {
1475 if (chipnum == cfi->numchips)
1481 size_t retlen_dregs = 0;
1483 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1484 len, &retlen_dregs, buf);
1486 *retlen += retlen_dregs;
1495 * Handle devices with one erase region, that only implement
1496 * the chip erase command.
1498 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1500 struct cfi_private *cfi = map->fldrv_priv;
1501 unsigned long timeo = jiffies + HZ;
1502 unsigned long int adr;
1503 DECLARE_WAITQUEUE(wait, current);
1506 adr = cfi->addr_unlock1;
1508 mutex_lock(&chip->mutex);
1509 ret = get_chip(map, chip, adr, FL_WRITING);
1511 mutex_unlock(&chip->mutex);
1515 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1516 __func__, chip->start );
1518 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1520 xip_disable(map, chip, adr);
1522 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1523 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1524 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1525 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1526 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1527 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1529 chip->state = FL_ERASING;
1530 chip->erase_suspended = 0;
1531 chip->in_progress_block_addr = adr;
1533 INVALIDATE_CACHE_UDELAY(map, chip,
1535 chip->erase_time*500);
1537 timeo = jiffies + (HZ*20);
1540 if (chip->state != FL_ERASING) {
1541 /* Someone's suspended the erase. Sleep */
1542 set_current_state(TASK_UNINTERRUPTIBLE);
1543 add_wait_queue(&chip->wq, &wait);
1544 mutex_unlock(&chip->mutex);
1546 remove_wait_queue(&chip->wq, &wait);
1547 mutex_lock(&chip->mutex);
1550 if (chip->erase_suspended) {
1551 /* This erase was suspended and resumed.
1552 Adjust the timeout */
1553 timeo = jiffies + (HZ*20); /* FIXME */
1554 chip->erase_suspended = 0;
1557 if (chip_ready(map, adr))
1560 if (time_after(jiffies, timeo)) {
1561 printk(KERN_WARNING "MTD %s(): software timeout\n",
1566 /* Latency issues. Drop the lock, wait a while and retry */
1567 UDELAY(map, chip, adr, 1000000/HZ);
1569 /* Did we succeed? */
1570 if (!chip_good(map, adr, map_word_ff(map))) {
1571 /* reset on all failures. */
1572 map_write( map, CMD(0xF0), chip->start );
1573 /* FIXME - should have reset delay before continuing */
1578 chip->state = FL_READY;
1579 xip_enable(map, chip, adr);
1580 put_chip(map, chip, adr);
1581 mutex_unlock(&chip->mutex);
1587 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1589 struct cfi_private *cfi = map->fldrv_priv;
1590 unsigned long timeo = jiffies + HZ;
1591 DECLARE_WAITQUEUE(wait, current);
1596 mutex_lock(&chip->mutex);
1597 ret = get_chip(map, chip, adr, FL_ERASING);
1599 mutex_unlock(&chip->mutex);
1603 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1606 XIP_INVAL_CACHED_RANGE(map, adr, len);
1608 xip_disable(map, chip, adr);
1610 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1611 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1612 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1613 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1614 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1615 map_write(map, CMD(0x30), adr);
1617 chip->state = FL_ERASING;
1618 chip->erase_suspended = 0;
1619 chip->in_progress_block_addr = adr;
1621 INVALIDATE_CACHE_UDELAY(map, chip,
1623 chip->erase_time*500);
1625 timeo = jiffies + (HZ*20);
1628 if (chip->state != FL_ERASING) {
1629 /* Someone's suspended the erase. Sleep */
1630 set_current_state(TASK_UNINTERRUPTIBLE);
1631 add_wait_queue(&chip->wq, &wait);
1632 mutex_unlock(&chip->mutex);
1634 remove_wait_queue(&chip->wq, &wait);
1635 mutex_lock(&chip->mutex);
1638 if (chip->erase_suspended) {
1639 /* This erase was suspended and resumed.
1640 Adjust the timeout */
1641 timeo = jiffies + (HZ*20); /* FIXME */
1642 chip->erase_suspended = 0;
1645 if (chip_ready(map, adr)) {
1646 xip_enable(map, chip, adr);
1650 if (time_after(jiffies, timeo)) {
1651 xip_enable(map, chip, adr);
1652 printk(KERN_WARNING "MTD %s(): software timeout\n",
1657 /* Latency issues. Drop the lock, wait a while and retry */
1658 UDELAY(map, chip, adr, 1000000/HZ);
1660 /* Did we succeed? */
1661 if (!chip_good(map, adr, map_word_ff(map))) {
1662 /* reset on all failures. */
1663 map_write( map, CMD(0xF0), chip->start );
1664 /* FIXME - should have reset delay before continuing */
1669 chip->state = FL_READY;
1670 put_chip(map, chip, adr);
1671 mutex_unlock(&chip->mutex);
1676 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1678 unsigned long ofs, len;
1684 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1688 instr->state = MTD_ERASE_DONE;
1689 mtd_erase_callback(instr);
1695 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1697 struct map_info *map = mtd->priv;
1698 struct cfi_private *cfi = map->fldrv_priv;
1701 if (instr->addr != 0)
1704 if (instr->len != mtd->size)
1707 ret = do_erase_chip(map, &cfi->chips[0]);
1711 instr->state = MTD_ERASE_DONE;
1712 mtd_erase_callback(instr);
1717 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1718 unsigned long adr, int len, void *thunk)
1720 struct cfi_private *cfi = map->fldrv_priv;
1723 mutex_lock(&chip->mutex);
1724 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1727 chip->state = FL_LOCKING;
1729 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1730 __func__, adr, len);
1732 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1733 cfi->device_type, NULL);
1734 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1735 cfi->device_type, NULL);
1736 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1737 cfi->device_type, NULL);
1738 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1739 cfi->device_type, NULL);
1740 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1741 cfi->device_type, NULL);
1742 map_write(map, CMD(0x40), chip->start + adr);
1744 chip->state = FL_READY;
1745 put_chip(map, chip, adr + chip->start);
1749 mutex_unlock(&chip->mutex);
1753 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1754 unsigned long adr, int len, void *thunk)
1756 struct cfi_private *cfi = map->fldrv_priv;
1759 mutex_lock(&chip->mutex);
1760 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1763 chip->state = FL_UNLOCKING;
1765 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1766 __func__, adr, len);
1768 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1769 cfi->device_type, NULL);
1770 map_write(map, CMD(0x70), adr);
1772 chip->state = FL_READY;
1773 put_chip(map, chip, adr + chip->start);
1777 mutex_unlock(&chip->mutex);
1781 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1783 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1786 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1788 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1792 static void cfi_amdstd_sync (struct mtd_info *mtd)
1794 struct map_info *map = mtd->priv;
1795 struct cfi_private *cfi = map->fldrv_priv;
1797 struct flchip *chip;
1799 DECLARE_WAITQUEUE(wait, current);
1801 for (i=0; !ret && i<cfi->numchips; i++) {
1802 chip = &cfi->chips[i];
1805 mutex_lock(&chip->mutex);
1807 switch(chip->state) {
1811 case FL_JEDEC_QUERY:
1812 chip->oldstate = chip->state;
1813 chip->state = FL_SYNCING;
1814 /* No need to wake_up() on this state change -
1815 * as the whole point is that nobody can do anything
1816 * with the chip now anyway.
1819 mutex_unlock(&chip->mutex);
1823 /* Not an idle state */
1824 set_current_state(TASK_UNINTERRUPTIBLE);
1825 add_wait_queue(&chip->wq, &wait);
1827 mutex_unlock(&chip->mutex);
1831 remove_wait_queue(&chip->wq, &wait);
1837 /* Unlock the chips again */
1839 for (i--; i >=0; i--) {
1840 chip = &cfi->chips[i];
1842 mutex_lock(&chip->mutex);
1844 if (chip->state == FL_SYNCING) {
1845 chip->state = chip->oldstate;
1848 mutex_unlock(&chip->mutex);
1853 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1855 struct map_info *map = mtd->priv;
1856 struct cfi_private *cfi = map->fldrv_priv;
1858 struct flchip *chip;
1861 for (i=0; !ret && i<cfi->numchips; i++) {
1862 chip = &cfi->chips[i];
1864 mutex_lock(&chip->mutex);
1866 switch(chip->state) {
1870 case FL_JEDEC_QUERY:
1871 chip->oldstate = chip->state;
1872 chip->state = FL_PM_SUSPENDED;
1873 /* No need to wake_up() on this state change -
1874 * as the whole point is that nobody can do anything
1875 * with the chip now anyway.
1877 case FL_PM_SUSPENDED:
1884 mutex_unlock(&chip->mutex);
1887 /* Unlock the chips again */
1890 for (i--; i >=0; i--) {
1891 chip = &cfi->chips[i];
1893 mutex_lock(&chip->mutex);
1895 if (chip->state == FL_PM_SUSPENDED) {
1896 chip->state = chip->oldstate;
1899 mutex_unlock(&chip->mutex);
1907 static void cfi_amdstd_resume(struct mtd_info *mtd)
1909 struct map_info *map = mtd->priv;
1910 struct cfi_private *cfi = map->fldrv_priv;
1912 struct flchip *chip;
1914 for (i=0; i<cfi->numchips; i++) {
1916 chip = &cfi->chips[i];
1918 mutex_lock(&chip->mutex);
1920 if (chip->state == FL_PM_SUSPENDED) {
1921 chip->state = FL_READY;
1922 map_write(map, CMD(0xF0), chip->start);
1926 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1928 mutex_unlock(&chip->mutex);
1934 * Ensure that the flash device is put back into read array mode before
1935 * unloading the driver or rebooting. On some systems, rebooting while
1936 * the flash is in query/program/erase mode will prevent the CPU from
1937 * fetching the bootloader code, requiring a hard reset or power cycle.
1939 static int cfi_amdstd_reset(struct mtd_info *mtd)
1941 struct map_info *map = mtd->priv;
1942 struct cfi_private *cfi = map->fldrv_priv;
1944 struct flchip *chip;
1946 for (i = 0; i < cfi->numchips; i++) {
1948 chip = &cfi->chips[i];
1950 mutex_lock(&chip->mutex);
1952 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
1954 map_write(map, CMD(0xF0), chip->start);
1955 chip->state = FL_SHUTDOWN;
1956 put_chip(map, chip, chip->start);
1959 mutex_unlock(&chip->mutex);
1966 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
1969 struct mtd_info *mtd;
1971 mtd = container_of(nb, struct mtd_info, reboot_notifier);
1972 cfi_amdstd_reset(mtd);
1977 static void cfi_amdstd_destroy(struct mtd_info *mtd)
1979 struct map_info *map = mtd->priv;
1980 struct cfi_private *cfi = map->fldrv_priv;
1982 cfi_amdstd_reset(mtd);
1983 unregister_reboot_notifier(&mtd->reboot_notifier);
1984 kfree(cfi->cmdset_priv);
1987 kfree(mtd->eraseregions);
1990 MODULE_LICENSE("GPL");
1991 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1992 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");