2 * linux/drivers/mmc/host/tmio_mmc_pio.c
4 * Copyright (C) 2011 Guennadi Liakhovetski
5 * Copyright (C) 2007 Ian Molton
6 * Copyright (C) 2004 Ian Molton
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Driver for the MMC / SD / SDIO IP found in:
14 * TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
16 * This driver draws mainly on scattered spec sheets, Reverse engineering
17 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
18 * support). (Further 4 bit support from a later datasheet).
21 * Investigate using a workqueue for PIO transfers
24 * Better Power management
25 * Handle MMC errors better
26 * double buffer support
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <linux/highmem.h>
33 #include <linux/interrupt.h>
35 #include <linux/irq.h>
36 #include <linux/mfd/tmio.h>
37 #include <linux/mmc/host.h>
38 #include <linux/mmc/tmio.h>
39 #include <linux/module.h>
40 #include <linux/pagemap.h>
41 #include <linux/platform_device.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/scatterlist.h>
44 #include <linux/workqueue.h>
45 #include <linux/spinlock.h>
49 void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
51 u32 mask = sd_ctrl_read32(host, CTL_IRQ_MASK) & ~(i & TMIO_MASK_IRQ);
52 sd_ctrl_write32(host, CTL_IRQ_MASK, mask);
55 void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
57 u32 mask = sd_ctrl_read32(host, CTL_IRQ_MASK) | (i & TMIO_MASK_IRQ);
58 sd_ctrl_write32(host, CTL_IRQ_MASK, mask);
61 static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
63 sd_ctrl_write32(host, CTL_STATUS, ~i);
66 static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
68 host->sg_len = data->sg_len;
69 host->sg_ptr = data->sg;
70 host->sg_orig = data->sg;
74 static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
76 host->sg_ptr = sg_next(host->sg_ptr);
78 return --host->sg_len;
81 #ifdef CONFIG_MMC_DEBUG
83 #define STATUS_TO_TEXT(a, status, i) \
85 if (status & TMIO_STAT_##a) { \
92 static void pr_debug_status(u32 status)
95 printk(KERN_DEBUG "status: %08x = ", status);
96 STATUS_TO_TEXT(CARD_REMOVE, status, i);
97 STATUS_TO_TEXT(CARD_INSERT, status, i);
98 STATUS_TO_TEXT(SIGSTATE, status, i);
99 STATUS_TO_TEXT(WRPROTECT, status, i);
100 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
101 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
102 STATUS_TO_TEXT(SIGSTATE_A, status, i);
103 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
104 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
105 STATUS_TO_TEXT(ILL_FUNC, status, i);
106 STATUS_TO_TEXT(CMD_BUSY, status, i);
107 STATUS_TO_TEXT(CMDRESPEND, status, i);
108 STATUS_TO_TEXT(DATAEND, status, i);
109 STATUS_TO_TEXT(CRCFAIL, status, i);
110 STATUS_TO_TEXT(DATATIMEOUT, status, i);
111 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
112 STATUS_TO_TEXT(RXOVERFLOW, status, i);
113 STATUS_TO_TEXT(TXUNDERRUN, status, i);
114 STATUS_TO_TEXT(RXRDY, status, i);
115 STATUS_TO_TEXT(TXRQ, status, i);
116 STATUS_TO_TEXT(ILL_ACCESS, status, i);
121 #define pr_debug_status(s) do { } while (0)
124 static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
126 struct tmio_mmc_host *host = mmc_priv(mmc);
129 host->sdio_irq_enabled = 1;
130 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
131 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK,
132 (TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ));
134 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, TMIO_SDIO_MASK_ALL);
135 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
136 host->sdio_irq_enabled = 0;
140 static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
145 for (clock = host->mmc->f_min, clk = 0x80000080;
146 new_clock >= (clock<<1); clk >>= 1)
151 if (host->set_clk_div)
152 host->set_clk_div(host->pdev, (clk>>22) & 1);
154 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
157 static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
159 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
161 /* implicit BUG_ON(!res) */
162 if (resource_size(res) > 0x100) {
163 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
167 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
168 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
172 static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
174 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
176 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
177 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
180 /* implicit BUG_ON(!res) */
181 if (resource_size(res) > 0x100) {
182 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
187 static void tmio_mmc_reset(struct tmio_mmc_host *host)
189 struct resource *res = platform_get_resource(host->pdev, IORESOURCE_MEM, 0);
191 /* FIXME - should we set stop clock reg here */
192 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
193 /* implicit BUG_ON(!res) */
194 if (resource_size(res) > 0x100)
195 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
197 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
198 if (resource_size(res) > 0x100)
199 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
203 static void tmio_mmc_reset_work(struct work_struct *work)
205 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
206 delayed_reset_work.work);
207 struct mmc_request *mrq;
210 spin_lock_irqsave(&host->lock, flags);
214 * is request already finished? Since we use a non-blocking
215 * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
216 * us, so, have to check for IS_ERR(host->mrq)
218 if (IS_ERR_OR_NULL(mrq)
219 || time_is_after_jiffies(host->last_req_ts +
220 msecs_to_jiffies(2000))) {
221 spin_unlock_irqrestore(&host->lock, flags);
225 dev_warn(&host->pdev->dev,
226 "timeout waiting for hardware interrupt (CMD%u)\n",
230 host->data->error = -ETIMEDOUT;
232 host->cmd->error = -ETIMEDOUT;
234 mrq->cmd->error = -ETIMEDOUT;
238 host->force_pio = false;
240 spin_unlock_irqrestore(&host->lock, flags);
242 tmio_mmc_reset(host);
244 /* Ready for new calls */
247 mmc_request_done(host->mmc, mrq);
250 /* called with host->lock held, interrupts disabled */
251 static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
253 struct mmc_request *mrq = host->mrq;
260 host->force_pio = false;
262 cancel_delayed_work(&host->delayed_reset_work);
266 /* FIXME: mmc_request_done() can schedule! */
267 mmc_request_done(host->mmc, mrq);
270 /* These are the bitmasks the tmio chip requires to implement the MMC response
271 * types. Note that R1 and R6 are the same in this scheme. */
272 #define APP_CMD 0x0040
273 #define RESP_NONE 0x0300
274 #define RESP_R1 0x0400
275 #define RESP_R1B 0x0500
276 #define RESP_R2 0x0600
277 #define RESP_R3 0x0700
278 #define DATA_PRESENT 0x0800
279 #define TRANSFER_READ 0x1000
280 #define TRANSFER_MULTI 0x2000
281 #define SECURITY_CMD 0x4000
283 static int tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
285 struct mmc_data *data = host->data;
288 /* Command 12 is handled by hardware */
289 if (cmd->opcode == 12 && !cmd->arg) {
290 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
294 switch (mmc_resp_type(cmd)) {
295 case MMC_RSP_NONE: c |= RESP_NONE; break;
296 case MMC_RSP_R1: c |= RESP_R1; break;
297 case MMC_RSP_R1B: c |= RESP_R1B; break;
298 case MMC_RSP_R2: c |= RESP_R2; break;
299 case MMC_RSP_R3: c |= RESP_R3; break;
301 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
307 /* FIXME - this seems to be ok commented out but the spec suggest this bit
308 * should be set when issuing app commands.
309 * if(cmd->flags & MMC_FLAG_ACMD)
314 if (data->blocks > 1) {
315 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
318 if (data->flags & MMC_DATA_READ)
322 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_CMD);
324 /* Fire off the command */
325 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
326 sd_ctrl_write16(host, CTL_SD_CMD, c);
332 * This chip always returns (at least?) as much data as you ask for.
333 * I'm unsure what happens if you ask for less than a block. This should be
334 * looked into to ensure that a funny length read doesn't hose the controller.
336 static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
338 struct mmc_data *data = host->data;
344 if ((host->chan_tx || host->chan_rx) && !host->force_pio) {
345 pr_err("PIO IRQ in DMA mode!\n");
348 pr_debug("Spurious PIO IRQ\n");
352 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
353 buf = (unsigned short *)(sg_virt + host->sg_off);
355 count = host->sg_ptr->length - host->sg_off;
356 if (count > data->blksz)
359 pr_debug("count: %08x offset: %08x flags %08x\n",
360 count, host->sg_off, data->flags);
362 /* Transfer the data */
363 if (data->flags & MMC_DATA_READ)
364 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
366 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
368 host->sg_off += count;
370 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
372 if (host->sg_off == host->sg_ptr->length)
373 tmio_mmc_next_sg(host);
378 static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
380 if (host->sg_ptr == &host->bounce_sg) {
382 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
383 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
384 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
388 /* needs to be called with host->lock held */
389 void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
391 struct mmc_data *data = host->data;
392 struct mmc_command *stop;
397 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
402 /* FIXME - return correct transfer count on errors */
404 data->bytes_xfered = data->blocks * data->blksz;
406 data->bytes_xfered = 0;
408 pr_debug("Completed data request\n");
411 * FIXME: other drivers allow an optional stop command of any given type
412 * which we dont do, as the chip can auto generate them.
413 * Perhaps we can be smarter about when to use auto CMD12 and
414 * only issue the auto request when we know this is the desired
415 * stop command, allowing fallback to the stop command the
416 * upper layers expect. For now, we do what works.
419 if (data->flags & MMC_DATA_READ) {
420 if (host->chan_rx && !host->force_pio)
421 tmio_mmc_check_bounce_buffer(host);
422 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
425 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
430 if (stop->opcode == 12 && !stop->arg)
431 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
436 tmio_mmc_finish_request(host);
439 static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
441 struct mmc_data *data;
442 spin_lock(&host->lock);
448 if (host->chan_tx && (data->flags & MMC_DATA_WRITE) && !host->force_pio) {
450 * Has all data been written out yet? Testing on SuperH showed,
451 * that in most cases the first interrupt comes already with the
452 * BUSY status bit clear, but on some operations, like mount or
453 * in the beginning of a write / sync / umount, there is one
454 * DATAEND interrupt with the BUSY bit set, in this cases
455 * waiting for one more interrupt fixes the problem.
457 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
458 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
459 tasklet_schedule(&host->dma_complete);
461 } else if (host->chan_rx && (data->flags & MMC_DATA_READ) && !host->force_pio) {
462 tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
463 tasklet_schedule(&host->dma_complete);
465 tmio_mmc_do_data_irq(host);
466 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
469 spin_unlock(&host->lock);
472 static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
475 struct mmc_command *cmd = host->cmd;
478 spin_lock(&host->lock);
481 pr_debug("Spurious CMD irq\n");
487 /* This controller is sicker than the PXA one. Not only do we need to
488 * drop the top 8 bits of the first response word, we also need to
489 * modify the order of the response for short response command types.
492 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
493 cmd->resp[i] = sd_ctrl_read32(host, addr);
495 if (cmd->flags & MMC_RSP_136) {
496 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
497 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
498 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
500 } else if (cmd->flags & MMC_RSP_R3) {
501 cmd->resp[0] = cmd->resp[3];
504 if (stat & TMIO_STAT_CMDTIMEOUT)
505 cmd->error = -ETIMEDOUT;
506 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
507 cmd->error = -EILSEQ;
509 /* If there is data to handle we enable data IRQs here, and
510 * we will ultimatley finish the request in the data_end handler.
511 * If theres no data or we encountered an error, finish now.
513 if (host->data && !cmd->error) {
514 if (host->data->flags & MMC_DATA_READ) {
515 if (host->force_pio || !host->chan_rx)
516 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
518 tasklet_schedule(&host->dma_issue);
520 if (host->force_pio || !host->chan_tx)
521 tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
523 tasklet_schedule(&host->dma_issue);
526 tmio_mmc_finish_request(host);
530 spin_unlock(&host->lock);
533 irqreturn_t tmio_mmc_irq(int irq, void *devid)
535 struct tmio_mmc_host *host = devid;
536 struct tmio_mmc_data *pdata = host->pdata;
537 unsigned int ireg, irq_mask, status;
538 unsigned int sdio_ireg, sdio_irq_mask, sdio_status;
540 pr_debug("MMC IRQ begin\n");
542 status = sd_ctrl_read32(host, CTL_STATUS);
543 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
544 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
547 if (!ireg && pdata->flags & TMIO_MMC_SDIO_IRQ) {
548 sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
549 sdio_irq_mask = sd_ctrl_read16(host, CTL_SDIO_IRQ_MASK);
550 sdio_ireg = sdio_status & TMIO_SDIO_MASK_ALL & ~sdio_irq_mask;
552 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status & ~TMIO_SDIO_MASK_ALL);
554 if (sdio_ireg && !host->sdio_irq_enabled) {
555 pr_warning("tmio_mmc: Spurious SDIO IRQ, disabling! 0x%04x 0x%04x 0x%04x\n",
556 sdio_status, sdio_irq_mask, sdio_ireg);
557 tmio_mmc_enable_sdio_irq(host->mmc, 0);
561 if (host->mmc->caps & MMC_CAP_SDIO_IRQ &&
562 sdio_ireg & TMIO_SDIO_STAT_IOIRQ)
563 mmc_signal_sdio_irq(host->mmc);
569 pr_debug_status(status);
570 pr_debug_status(ireg);
572 /* Card insert / remove attempts */
573 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
574 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
575 TMIO_STAT_CARD_REMOVE);
576 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
580 /* CRC and other errors */
581 /* if (ireg & TMIO_STAT_ERR_IRQ)
582 * handled |= tmio_error_irq(host, irq, stat);
585 /* Command completion */
586 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
587 tmio_mmc_ack_mmc_irqs(host,
588 TMIO_STAT_CMDRESPEND |
589 TMIO_STAT_CMDTIMEOUT);
590 tmio_mmc_cmd_irq(host, status);
595 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
596 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
597 tmio_mmc_pio_irq(host);
601 /* Data transfer completion */
602 if (ireg & TMIO_STAT_DATAEND) {
603 tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
604 tmio_mmc_data_irq(host);
608 pr_warning("tmio_mmc: Spurious irq, disabling! "
609 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
610 pr_debug_status(status);
611 tmio_mmc_disable_mmc_irqs(host, status & ~irq_mask);
616 EXPORT_SYMBOL(tmio_mmc_irq);
618 static int tmio_mmc_start_data(struct tmio_mmc_host *host,
619 struct mmc_data *data)
621 struct tmio_mmc_data *pdata = host->pdata;
623 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
624 data->blksz, data->blocks);
626 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
627 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
628 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
630 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
631 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
632 mmc_hostname(host->mmc), data->blksz);
637 tmio_mmc_init_sg(host, data);
640 /* Set transfer length / blocksize */
641 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
642 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
644 tmio_mmc_start_dma(host, data);
649 /* Process requests from the MMC layer */
650 static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
652 struct tmio_mmc_host *host = mmc_priv(mmc);
656 spin_lock_irqsave(&host->lock, flags);
659 pr_debug("request not null\n");
660 if (IS_ERR(host->mrq)) {
661 spin_unlock_irqrestore(&host->lock, flags);
662 mrq->cmd->error = -EAGAIN;
663 mmc_request_done(mmc, mrq);
668 host->last_req_ts = jiffies;
672 spin_unlock_irqrestore(&host->lock, flags);
675 ret = tmio_mmc_start_data(host, mrq->data);
680 ret = tmio_mmc_start_command(host, mrq->cmd);
682 schedule_delayed_work(&host->delayed_reset_work,
683 msecs_to_jiffies(2000));
688 host->force_pio = false;
690 mrq->cmd->error = ret;
691 mmc_request_done(mmc, mrq);
694 /* Set MMC clock / power.
695 * Note: This controller uses a simple divider scheme therefore it cannot
696 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
697 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
700 static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
702 struct tmio_mmc_host *host = mmc_priv(mmc);
703 struct tmio_mmc_data *pdata = host->pdata;
706 spin_lock_irqsave(&host->lock, flags);
708 if (IS_ERR(host->mrq)) {
709 dev_dbg(&host->pdev->dev,
710 "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
711 current->comm, task_pid_nr(current),
712 ios->clock, ios->power_mode);
713 host->mrq = ERR_PTR(-EINTR);
715 dev_dbg(&host->pdev->dev,
716 "%s.%d: CMD%u active since %lu, now %lu!\n",
717 current->comm, task_pid_nr(current),
718 host->mrq->cmd->opcode, host->last_req_ts, jiffies);
720 spin_unlock_irqrestore(&host->lock, flags);
724 host->mrq = ERR_PTR(-EBUSY);
726 spin_unlock_irqrestore(&host->lock, flags);
729 tmio_mmc_set_clock(host, ios->clock);
731 /* Power sequence - OFF -> UP -> ON */
732 if (ios->power_mode == MMC_POWER_UP) {
733 if ((pdata->flags & TMIO_MMC_HAS_COLD_CD) && !pdata->power) {
734 pm_runtime_get_sync(&host->pdev->dev);
737 /* power up SD bus */
739 host->set_pwr(host->pdev, 1);
740 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
741 /* power down SD bus */
742 if (ios->power_mode == MMC_POWER_OFF) {
744 host->set_pwr(host->pdev, 0);
745 if ((pdata->flags & TMIO_MMC_HAS_COLD_CD) &&
747 pdata->power = false;
748 pm_runtime_put(&host->pdev->dev);
751 tmio_mmc_clk_stop(host);
753 /* start bus clock */
754 tmio_mmc_clk_start(host);
757 switch (ios->bus_width) {
758 case MMC_BUS_WIDTH_1:
759 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
761 case MMC_BUS_WIDTH_4:
762 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
766 /* Let things settle. delay taken from winCE driver */
768 if (PTR_ERR(host->mrq) == -EINTR)
769 dev_dbg(&host->pdev->dev,
770 "%s.%d: IOS interrupted: clk %u, mode %u",
771 current->comm, task_pid_nr(current),
772 ios->clock, ios->power_mode);
776 static int tmio_mmc_get_ro(struct mmc_host *mmc)
778 struct tmio_mmc_host *host = mmc_priv(mmc);
779 struct tmio_mmc_data *pdata = host->pdata;
781 return !((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
782 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT));
785 static int tmio_mmc_get_cd(struct mmc_host *mmc)
787 struct tmio_mmc_host *host = mmc_priv(mmc);
788 struct tmio_mmc_data *pdata = host->pdata;
793 return pdata->get_cd(host->pdev);
796 static const struct mmc_host_ops tmio_mmc_ops = {
797 .request = tmio_mmc_request,
798 .set_ios = tmio_mmc_set_ios,
799 .get_ro = tmio_mmc_get_ro,
800 .get_cd = tmio_mmc_get_cd,
801 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
804 int __devinit tmio_mmc_host_probe(struct tmio_mmc_host **host,
805 struct platform_device *pdev,
806 struct tmio_mmc_data *pdata)
808 struct tmio_mmc_host *_host;
809 struct mmc_host *mmc;
810 struct resource *res_ctl;
812 u32 irq_mask = TMIO_MASK_CMD;
814 res_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
822 pdata->dev = &pdev->dev;
823 _host = mmc_priv(mmc);
824 _host->pdata = pdata;
827 platform_set_drvdata(pdev, mmc);
829 _host->set_pwr = pdata->set_pwr;
830 _host->set_clk_div = pdata->set_clk_div;
832 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
833 _host->bus_shift = resource_size(res_ctl) >> 10;
835 _host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
841 mmc->ops = &tmio_mmc_ops;
842 mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
843 mmc->f_max = pdata->hclk;
844 mmc->f_min = mmc->f_max / 512;
846 mmc->max_blk_size = 512;
847 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
849 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
850 mmc->max_seg_size = mmc->max_req_size;
852 mmc->ocr_avail = pdata->ocr_mask;
854 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
856 pdata->power = false;
857 pm_runtime_enable(&pdev->dev);
858 ret = pm_runtime_resume(&pdev->dev);
862 tmio_mmc_clk_stop(_host);
863 tmio_mmc_reset(_host);
865 tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
866 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
867 tmio_mmc_enable_sdio_irq(mmc, 0);
869 spin_lock_init(&_host->lock);
871 /* Init delayed work for request timeouts */
872 INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
874 /* See if we also get DMA */
875 tmio_mmc_request_dma(_host, pdata);
877 /* We have to keep the device powered for its card detection to work */
878 if (!(pdata->flags & TMIO_MMC_HAS_COLD_CD))
879 pm_runtime_get_noresume(&pdev->dev);
883 /* Unmask the IRQs we want to know about */
885 irq_mask |= TMIO_MASK_READOP;
887 irq_mask |= TMIO_MASK_WRITEOP;
889 tmio_mmc_enable_mmc_irqs(_host, irq_mask);
896 pm_runtime_disable(&pdev->dev);
903 EXPORT_SYMBOL(tmio_mmc_host_probe);
905 void tmio_mmc_host_remove(struct tmio_mmc_host *host)
907 struct platform_device *pdev = host->pdev;
910 * We don't have to manipulate pdata->power here: if there is a card in
911 * the slot, the runtime PM is active and our .runtime_resume() will not
912 * be run. If there is no card in the slot and the platform can suspend
913 * the controller, the runtime PM is suspended and pdata->power == false,
914 * so, our .runtime_resume() will not try to detect a card in the slot.
916 if (host->pdata->flags & TMIO_MMC_HAS_COLD_CD)
917 pm_runtime_get_sync(&pdev->dev);
919 mmc_remove_host(host->mmc);
920 cancel_delayed_work_sync(&host->delayed_reset_work);
921 tmio_mmc_release_dma(host);
923 pm_runtime_put_sync(&pdev->dev);
924 pm_runtime_disable(&pdev->dev);
927 mmc_free_host(host->mmc);
929 EXPORT_SYMBOL(tmio_mmc_host_remove);
932 int tmio_mmc_host_suspend(struct device *dev)
934 struct mmc_host *mmc = dev_get_drvdata(dev);
935 struct tmio_mmc_host *host = mmc_priv(mmc);
936 int ret = mmc_suspend_host(mmc);
939 tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
941 host->pm_error = pm_runtime_put_sync(dev);
945 EXPORT_SYMBOL(tmio_mmc_host_suspend);
947 int tmio_mmc_host_resume(struct device *dev)
949 struct mmc_host *mmc = dev_get_drvdata(dev);
950 struct tmio_mmc_host *host = mmc_priv(mmc);
952 /* The MMC core will perform the complete set up */
953 host->pdata->power = false;
956 pm_runtime_get_sync(dev);
958 tmio_mmc_reset(mmc_priv(mmc));
959 tmio_mmc_request_dma(host, host->pdata);
961 return mmc_resume_host(mmc);
963 EXPORT_SYMBOL(tmio_mmc_host_resume);
965 #endif /* CONFIG_PM */
967 int tmio_mmc_host_runtime_suspend(struct device *dev)
971 EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
973 int tmio_mmc_host_runtime_resume(struct device *dev)
975 struct mmc_host *mmc = dev_get_drvdata(dev);
976 struct tmio_mmc_host *host = mmc_priv(mmc);
977 struct tmio_mmc_data *pdata = host->pdata;
979 tmio_mmc_reset(host);
982 /* Only entered after a card-insert interrupt */
983 tmio_mmc_set_ios(mmc, &mmc->ios);
984 mmc_detect_change(mmc, msecs_to_jiffies(100));
989 EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
991 MODULE_LICENSE("GPL v2");