2 * linux/drivers/mmc/tmio_mmc.c
4 * Copyright (C) 2004 Ian Molton
5 * Copyright (C) 2007 Ian Molton
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Driver for the MMC / SD / SDIO cell found in:
13 * TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
15 * This driver draws mainly on scattered spec sheets, Reverse engineering
16 * of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
17 * support). (Further 4 bit support from a later datasheet).
20 * Investigate using a workqueue for PIO transfers
23 * Better Power management
24 * Handle MMC errors better
25 * double buffer support
29 #include <linux/delay.h>
30 #include <linux/device.h>
31 #include <linux/dmaengine.h>
32 #include <linux/highmem.h>
33 #include <linux/interrupt.h>
35 #include <linux/irq.h>
36 #include <linux/mfd/core.h>
37 #include <linux/mfd/tmio.h>
38 #include <linux/mmc/host.h>
39 #include <linux/module.h>
40 #include <linux/pagemap.h>
41 #include <linux/scatterlist.h>
42 #include <linux/workqueue.h>
43 #include <linux/spinlock.h>
45 #define CTL_SD_CMD 0x00
46 #define CTL_ARG_REG 0x04
47 #define CTL_STOP_INTERNAL_ACTION 0x08
48 #define CTL_XFER_BLK_COUNT 0xa
49 #define CTL_RESPONSE 0x0c
50 #define CTL_STATUS 0x1c
51 #define CTL_IRQ_MASK 0x20
52 #define CTL_SD_CARD_CLK_CTL 0x24
53 #define CTL_SD_XFER_LEN 0x26
54 #define CTL_SD_MEM_CARD_OPT 0x28
55 #define CTL_SD_ERROR_DETAIL_STATUS 0x2c
56 #define CTL_SD_DATA_PORT 0x30
57 #define CTL_TRANSACTION_CTL 0x34
58 #define CTL_SDIO_STATUS 0x36
59 #define CTL_SDIO_IRQ_MASK 0x38
60 #define CTL_RESET_SD 0xe0
61 #define CTL_SDIO_REGS 0x100
62 #define CTL_CLK_AND_WAIT_CTL 0x138
63 #define CTL_RESET_SDIO 0x1e0
65 /* Definitions for values the CTRL_STATUS register can take. */
66 #define TMIO_STAT_CMDRESPEND 0x00000001
67 #define TMIO_STAT_DATAEND 0x00000004
68 #define TMIO_STAT_CARD_REMOVE 0x00000008
69 #define TMIO_STAT_CARD_INSERT 0x00000010
70 #define TMIO_STAT_SIGSTATE 0x00000020
71 #define TMIO_STAT_WRPROTECT 0x00000080
72 #define TMIO_STAT_CARD_REMOVE_A 0x00000100
73 #define TMIO_STAT_CARD_INSERT_A 0x00000200
74 #define TMIO_STAT_SIGSTATE_A 0x00000400
75 #define TMIO_STAT_CMD_IDX_ERR 0x00010000
76 #define TMIO_STAT_CRCFAIL 0x00020000
77 #define TMIO_STAT_STOPBIT_ERR 0x00040000
78 #define TMIO_STAT_DATATIMEOUT 0x00080000
79 #define TMIO_STAT_RXOVERFLOW 0x00100000
80 #define TMIO_STAT_TXUNDERRUN 0x00200000
81 #define TMIO_STAT_CMDTIMEOUT 0x00400000
82 #define TMIO_STAT_RXRDY 0x01000000
83 #define TMIO_STAT_TXRQ 0x02000000
84 #define TMIO_STAT_ILL_FUNC 0x20000000
85 #define TMIO_STAT_CMD_BUSY 0x40000000
86 #define TMIO_STAT_ILL_ACCESS 0x80000000
88 /* Definitions for values the CTRL_SDIO_STATUS register can take. */
89 #define TMIO_SDIO_STAT_IOIRQ 0x0001
90 #define TMIO_SDIO_STAT_EXPUB52 0x4000
91 #define TMIO_SDIO_STAT_EXWT 0x8000
92 #define TMIO_SDIO_MASK_ALL 0xc007
94 /* Define some IRQ masks */
95 /* This is the mask used at reset by the chip */
96 #define TMIO_MASK_ALL 0x837f031d
97 #define TMIO_MASK_READOP (TMIO_STAT_RXRDY | TMIO_STAT_DATAEND)
98 #define TMIO_MASK_WRITEOP (TMIO_STAT_TXRQ | TMIO_STAT_DATAEND)
99 #define TMIO_MASK_CMD (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT | \
100 TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT)
101 #define TMIO_MASK_IRQ (TMIO_MASK_READOP | TMIO_MASK_WRITEOP | TMIO_MASK_CMD)
103 #define enable_mmc_irqs(host, i) \
106 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
107 mask &= ~((i) & TMIO_MASK_IRQ); \
108 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
111 #define disable_mmc_irqs(host, i) \
114 mask = sd_ctrl_read32((host), CTL_IRQ_MASK); \
115 mask |= ((i) & TMIO_MASK_IRQ); \
116 sd_ctrl_write32((host), CTL_IRQ_MASK, mask); \
119 #define ack_mmc_irqs(host, i) \
121 sd_ctrl_write32((host), CTL_STATUS, ~(i)); \
124 /* This is arbitrary, just noone needed any higher alignment yet */
127 struct tmio_mmc_host {
129 unsigned long bus_shift;
130 struct mmc_command *cmd;
131 struct mmc_request *mrq;
132 struct mmc_data *data;
133 struct mmc_host *mmc;
135 unsigned int sdio_irq_enabled;
137 /* Callbacks for clock / power control */
138 void (*set_pwr)(struct platform_device *host, int state);
139 void (*set_clk_div)(struct platform_device *host, int state);
141 /* pio related stuff */
142 struct scatterlist *sg_ptr;
143 struct scatterlist *sg_orig;
147 struct platform_device *pdev;
150 struct dma_chan *chan_rx;
151 struct dma_chan *chan_tx;
152 struct tasklet_struct dma_complete;
153 struct tasklet_struct dma_issue;
154 #ifdef CONFIG_TMIO_MMC_DMA
155 u8 bounce_buf[PAGE_CACHE_SIZE] __attribute__((aligned(MAX_ALIGN)));
156 struct scatterlist bounce_sg;
159 /* Track lost interrupts */
160 struct delayed_work delayed_reset_work;
162 unsigned long last_req_ts;
165 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host);
167 static u16 sd_ctrl_read16(struct tmio_mmc_host *host, int addr)
169 return readw(host->ctl + (addr << host->bus_shift));
172 static void sd_ctrl_read16_rep(struct tmio_mmc_host *host, int addr,
175 readsw(host->ctl + (addr << host->bus_shift), buf, count);
178 static u32 sd_ctrl_read32(struct tmio_mmc_host *host, int addr)
180 return readw(host->ctl + (addr << host->bus_shift)) |
181 readw(host->ctl + ((addr + 2) << host->bus_shift)) << 16;
184 static void sd_ctrl_write16(struct tmio_mmc_host *host, int addr, u16 val)
186 writew(val, host->ctl + (addr << host->bus_shift));
189 static void sd_ctrl_write16_rep(struct tmio_mmc_host *host, int addr,
192 writesw(host->ctl + (addr << host->bus_shift), buf, count);
195 static void sd_ctrl_write32(struct tmio_mmc_host *host, int addr, u32 val)
197 writew(val, host->ctl + (addr << host->bus_shift));
198 writew(val >> 16, host->ctl + ((addr + 2) << host->bus_shift));
201 static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
203 host->sg_len = data->sg_len;
204 host->sg_ptr = data->sg;
205 host->sg_orig = data->sg;
209 static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
211 host->sg_ptr = sg_next(host->sg_ptr);
213 return --host->sg_len;
216 static char *tmio_mmc_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
218 local_irq_save(*flags);
219 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
222 static void tmio_mmc_kunmap_atomic(struct scatterlist *sg, unsigned long *flags, void *virt)
224 kunmap_atomic(virt - sg->offset, KM_BIO_SRC_IRQ);
225 local_irq_restore(*flags);
228 #ifdef CONFIG_MMC_DEBUG
230 #define STATUS_TO_TEXT(a, status, i) \
232 if (status & TMIO_STAT_##a) { \
239 void pr_debug_status(u32 status)
242 printk(KERN_DEBUG "status: %08x = ", status);
243 STATUS_TO_TEXT(CARD_REMOVE, status, i);
244 STATUS_TO_TEXT(CARD_INSERT, status, i);
245 STATUS_TO_TEXT(SIGSTATE, status, i);
246 STATUS_TO_TEXT(WRPROTECT, status, i);
247 STATUS_TO_TEXT(CARD_REMOVE_A, status, i);
248 STATUS_TO_TEXT(CARD_INSERT_A, status, i);
249 STATUS_TO_TEXT(SIGSTATE_A, status, i);
250 STATUS_TO_TEXT(CMD_IDX_ERR, status, i);
251 STATUS_TO_TEXT(STOPBIT_ERR, status, i);
252 STATUS_TO_TEXT(ILL_FUNC, status, i);
253 STATUS_TO_TEXT(CMD_BUSY, status, i);
254 STATUS_TO_TEXT(CMDRESPEND, status, i);
255 STATUS_TO_TEXT(DATAEND, status, i);
256 STATUS_TO_TEXT(CRCFAIL, status, i);
257 STATUS_TO_TEXT(DATATIMEOUT, status, i);
258 STATUS_TO_TEXT(CMDTIMEOUT, status, i);
259 STATUS_TO_TEXT(RXOVERFLOW, status, i);
260 STATUS_TO_TEXT(TXUNDERRUN, status, i);
261 STATUS_TO_TEXT(RXRDY, status, i);
262 STATUS_TO_TEXT(TXRQ, status, i);
263 STATUS_TO_TEXT(ILL_ACCESS, status, i);
268 #define pr_debug_status(s) do { } while (0)
271 static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
273 struct tmio_mmc_host *host = mmc_priv(mmc);
276 host->sdio_irq_enabled = 1;
277 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
278 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK,
279 (TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ));
281 sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, TMIO_SDIO_MASK_ALL);
282 sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
283 host->sdio_irq_enabled = 0;
287 static void tmio_mmc_set_clock(struct tmio_mmc_host *host, int new_clock)
292 for (clock = host->mmc->f_min, clk = 0x80000080;
293 new_clock >= (clock<<1); clk >>= 1)
298 if (host->set_clk_div)
299 host->set_clk_div(host->pdev, (clk>>22) & 1);
301 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & 0x1ff);
304 static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
306 struct mfd_cell *cell = host->pdev->dev.platform_data;
307 struct tmio_mmc_data *pdata = cell->driver_data;
310 * Testing on sh-mobile showed that SDIO IRQs are unmasked when
311 * CTL_CLK_AND_WAIT_CTL gets written, so we have to disable the
312 * device IRQ here and restore the SDIO IRQ mask before
313 * re-enabling the device IRQ.
315 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
316 disable_irq(host->irq);
317 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
319 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
320 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
321 enable_irq(host->irq);
323 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~0x0100 &
324 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
328 static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
330 struct mfd_cell *cell = host->pdev->dev.platform_data;
331 struct tmio_mmc_data *pdata = cell->driver_data;
333 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, 0x0100 |
334 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
336 /* see comment in tmio_mmc_clk_stop above */
337 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
338 disable_irq(host->irq);
339 sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
341 if (pdata->flags & TMIO_MMC_SDIO_IRQ) {
342 tmio_mmc_enable_sdio_irq(host->mmc, host->sdio_irq_enabled);
343 enable_irq(host->irq);
347 static void reset(struct tmio_mmc_host *host)
349 /* FIXME - should we set stop clock reg here */
350 sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
351 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0000);
353 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
354 sd_ctrl_write16(host, CTL_RESET_SDIO, 0x0001);
358 static void tmio_mmc_reset_work(struct work_struct *work)
360 struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
361 delayed_reset_work.work);
362 struct mmc_request *mrq;
365 spin_lock_irqsave(&host->lock, flags);
368 /* request already finished */
370 || time_is_after_jiffies(host->last_req_ts +
371 msecs_to_jiffies(2000))) {
372 spin_unlock_irqrestore(&host->lock, flags);
376 dev_warn(&host->pdev->dev,
377 "timeout waiting for hardware interrupt (CMD%u)\n",
381 host->data->error = -ETIMEDOUT;
383 host->cmd->error = -ETIMEDOUT;
385 mrq->cmd->error = -ETIMEDOUT;
391 spin_unlock_irqrestore(&host->lock, flags);
395 mmc_request_done(host->mmc, mrq);
399 tmio_mmc_finish_request(struct tmio_mmc_host *host)
401 struct mmc_request *mrq = host->mrq;
410 cancel_delayed_work(&host->delayed_reset_work);
412 mmc_request_done(host->mmc, mrq);
415 /* These are the bitmasks the tmio chip requires to implement the MMC response
416 * types. Note that R1 and R6 are the same in this scheme. */
417 #define APP_CMD 0x0040
418 #define RESP_NONE 0x0300
419 #define RESP_R1 0x0400
420 #define RESP_R1B 0x0500
421 #define RESP_R2 0x0600
422 #define RESP_R3 0x0700
423 #define DATA_PRESENT 0x0800
424 #define TRANSFER_READ 0x1000
425 #define TRANSFER_MULTI 0x2000
426 #define SECURITY_CMD 0x4000
429 tmio_mmc_start_command(struct tmio_mmc_host *host, struct mmc_command *cmd)
431 struct mmc_data *data = host->data;
434 /* Command 12 is handled by hardware */
435 if (cmd->opcode == 12 && !cmd->arg) {
436 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x001);
440 switch (mmc_resp_type(cmd)) {
441 case MMC_RSP_NONE: c |= RESP_NONE; break;
442 case MMC_RSP_R1: c |= RESP_R1; break;
443 case MMC_RSP_R1B: c |= RESP_R1B; break;
444 case MMC_RSP_R2: c |= RESP_R2; break;
445 case MMC_RSP_R3: c |= RESP_R3; break;
447 pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
453 /* FIXME - this seems to be ok commented out but the spec suggest this bit
454 * should be set when issuing app commands.
455 * if(cmd->flags & MMC_FLAG_ACMD)
460 if (data->blocks > 1) {
461 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x100);
464 if (data->flags & MMC_DATA_READ)
468 enable_mmc_irqs(host, TMIO_MASK_CMD);
470 /* Fire off the command */
471 sd_ctrl_write32(host, CTL_ARG_REG, cmd->arg);
472 sd_ctrl_write16(host, CTL_SD_CMD, c);
478 * This chip always returns (at least?) as much data as you ask for.
479 * I'm unsure what happens if you ask for less than a block. This should be
480 * looked into to ensure that a funny length read doesnt hose the controller.
482 static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
484 struct mmc_data *data = host->data;
491 pr_debug("Spurious PIO IRQ\n");
495 sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
496 buf = (unsigned short *)(sg_virt + host->sg_off);
498 count = host->sg_ptr->length - host->sg_off;
499 if (count > data->blksz)
502 pr_debug("count: %08x offset: %08x flags %08x\n",
503 count, host->sg_off, data->flags);
505 /* Transfer the data */
506 if (data->flags & MMC_DATA_READ)
507 sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
509 sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
511 host->sg_off += count;
513 tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
515 if (host->sg_off == host->sg_ptr->length)
516 tmio_mmc_next_sg(host);
521 /* needs to be called with host->lock held */
522 static void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
524 struct mmc_data *data = host->data;
525 struct mmc_command *stop;
530 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
535 /* FIXME - return correct transfer count on errors */
537 data->bytes_xfered = data->blocks * data->blksz;
539 data->bytes_xfered = 0;
541 pr_debug("Completed data request\n");
544 * FIXME: other drivers allow an optional stop command of any given type
545 * which we dont do, as the chip can auto generate them.
546 * Perhaps we can be smarter about when to use auto CMD12 and
547 * only issue the auto request when we know this is the desired
548 * stop command, allowing fallback to the stop command the
549 * upper layers expect. For now, we do what works.
552 if (data->flags & MMC_DATA_READ) {
554 disable_mmc_irqs(host, TMIO_MASK_READOP);
556 tmio_check_bounce_buffer(host);
557 dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
561 disable_mmc_irqs(host, TMIO_MASK_WRITEOP);
562 dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
567 if (stop->opcode == 12 && !stop->arg)
568 sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0x000);
573 tmio_mmc_finish_request(host);
576 static void tmio_mmc_data_irq(struct tmio_mmc_host *host)
578 struct mmc_data *data;
579 spin_lock(&host->lock);
585 if (host->chan_tx && (data->flags & MMC_DATA_WRITE)) {
587 * Has all data been written out yet? Testing on SuperH showed,
588 * that in most cases the first interrupt comes already with the
589 * BUSY status bit clear, but on some operations, like mount or
590 * in the beginning of a write / sync / umount, there is one
591 * DATAEND interrupt with the BUSY bit set, in this cases
592 * waiting for one more interrupt fixes the problem.
594 if (!(sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_CMD_BUSY)) {
595 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
596 tasklet_schedule(&host->dma_complete);
598 } else if (host->chan_rx && (data->flags & MMC_DATA_READ)) {
599 disable_mmc_irqs(host, TMIO_STAT_DATAEND);
600 tasklet_schedule(&host->dma_complete);
602 tmio_mmc_do_data_irq(host);
605 spin_unlock(&host->lock);
608 static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host,
611 struct mmc_command *cmd = host->cmd;
614 spin_lock(&host->lock);
617 pr_debug("Spurious CMD irq\n");
623 /* This controller is sicker than the PXA one. Not only do we need to
624 * drop the top 8 bits of the first response word, we also need to
625 * modify the order of the response for short response command types.
628 for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
629 cmd->resp[i] = sd_ctrl_read32(host, addr);
631 if (cmd->flags & MMC_RSP_136) {
632 cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
633 cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
634 cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
636 } else if (cmd->flags & MMC_RSP_R3) {
637 cmd->resp[0] = cmd->resp[3];
640 if (stat & TMIO_STAT_CMDTIMEOUT)
641 cmd->error = -ETIMEDOUT;
642 else if (stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC)
643 cmd->error = -EILSEQ;
645 /* If there is data to handle we enable data IRQs here, and
646 * we will ultimatley finish the request in the data_end handler.
647 * If theres no data or we encountered an error, finish now.
649 if (host->data && !cmd->error) {
650 if (host->data->flags & MMC_DATA_READ) {
652 enable_mmc_irqs(host, TMIO_MASK_READOP);
655 enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
657 tasklet_schedule(&host->dma_issue);
660 tmio_mmc_finish_request(host);
664 spin_unlock(&host->lock);
669 static irqreturn_t tmio_mmc_irq(int irq, void *devid)
671 struct tmio_mmc_host *host = devid;
672 struct mfd_cell *cell = host->pdev->dev.platform_data;
673 struct tmio_mmc_data *pdata = cell->driver_data;
674 unsigned int ireg, irq_mask, status;
675 unsigned int sdio_ireg, sdio_irq_mask, sdio_status;
677 pr_debug("MMC IRQ begin\n");
679 status = sd_ctrl_read32(host, CTL_STATUS);
680 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
681 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
684 if (!ireg && pdata->flags & TMIO_MMC_SDIO_IRQ) {
685 sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
686 sdio_irq_mask = sd_ctrl_read16(host, CTL_SDIO_IRQ_MASK);
687 sdio_ireg = sdio_status & TMIO_SDIO_MASK_ALL & ~sdio_irq_mask;
689 sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status & ~TMIO_SDIO_MASK_ALL);
691 if (sdio_ireg && !host->sdio_irq_enabled) {
692 pr_warning("tmio_mmc: Spurious SDIO IRQ, disabling! 0x%04x 0x%04x 0x%04x\n",
693 sdio_status, sdio_irq_mask, sdio_ireg);
694 tmio_mmc_enable_sdio_irq(host->mmc, 0);
698 if (host->mmc->caps & MMC_CAP_SDIO_IRQ &&
699 sdio_ireg & TMIO_SDIO_STAT_IOIRQ)
700 mmc_signal_sdio_irq(host->mmc);
706 pr_debug_status(status);
707 pr_debug_status(ireg);
710 disable_mmc_irqs(host, status & ~irq_mask);
712 pr_warning("tmio_mmc: Spurious irq, disabling! "
713 "0x%08x 0x%08x 0x%08x\n", status, irq_mask, ireg);
714 pr_debug_status(status);
720 /* Card insert / remove attempts */
721 if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
722 ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
723 TMIO_STAT_CARD_REMOVE);
724 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
727 /* CRC and other errors */
728 /* if (ireg & TMIO_STAT_ERR_IRQ)
729 * handled |= tmio_error_irq(host, irq, stat);
732 /* Command completion */
733 if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
735 TMIO_STAT_CMDRESPEND |
736 TMIO_STAT_CMDTIMEOUT);
737 tmio_mmc_cmd_irq(host, status);
741 if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
742 ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
743 tmio_mmc_pio_irq(host);
746 /* Data transfer completion */
747 if (ireg & TMIO_STAT_DATAEND) {
748 ack_mmc_irqs(host, TMIO_STAT_DATAEND);
749 tmio_mmc_data_irq(host);
752 /* Check status - keep going until we've handled it all */
753 status = sd_ctrl_read32(host, CTL_STATUS);
754 irq_mask = sd_ctrl_read32(host, CTL_IRQ_MASK);
755 ireg = status & TMIO_MASK_IRQ & ~irq_mask;
757 pr_debug("Status at end of loop: %08x\n", status);
758 pr_debug_status(status);
760 pr_debug("MMC IRQ end\n");
766 #ifdef CONFIG_TMIO_MMC_DMA
767 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
769 if (host->sg_ptr == &host->bounce_sg) {
771 void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
772 memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
773 tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
777 static void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable)
779 #if defined(CONFIG_SUPERH) || defined(CONFIG_ARCH_SHMOBILE)
780 /* Switch DMA mode on or off - SuperH specific? */
781 sd_ctrl_write16(host, 0xd8, enable ? 2 : 0);
785 static void tmio_dma_complete(void *arg)
787 struct tmio_mmc_host *host = arg;
789 dev_dbg(&host->pdev->dev, "Command completed\n");
792 dev_warn(&host->pdev->dev, "NULL data in DMA completion!\n");
794 enable_mmc_irqs(host, TMIO_STAT_DATAEND);
797 static void tmio_mmc_start_dma_rx(struct tmio_mmc_host *host)
799 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
800 struct dma_async_tx_descriptor *desc = NULL;
801 struct dma_chan *chan = host->chan_rx;
802 struct mfd_cell *cell = host->pdev->dev.platform_data;
803 struct tmio_mmc_data *pdata = cell->driver_data;
806 bool aligned = true, multiple = true;
807 unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
809 for_each_sg(sg, sg_tmp, host->sg_len, i) {
810 if (sg_tmp->offset & align)
812 if (sg_tmp->length & align) {
818 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
819 align >= MAX_ALIGN)) || !multiple) {
824 /* The only sg element can be unaligned, use our bounce buffer then */
826 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
827 host->sg_ptr = &host->bounce_sg;
831 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_FROM_DEVICE);
833 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
834 DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
837 desc->callback = tmio_dma_complete;
838 desc->callback_param = host;
839 cookie = dmaengine_submit(desc);
840 dma_async_issue_pending(chan);
842 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
843 __func__, host->sg_len, ret, cookie, host->mrq);
847 /* DMA failed, fall back to PIO */
850 host->chan_rx = NULL;
851 dma_release_channel(chan);
852 /* Free the Tx channel too */
853 chan = host->chan_tx;
855 host->chan_tx = NULL;
856 dma_release_channel(chan);
858 dev_warn(&host->pdev->dev,
859 "DMA failed: %d, falling back to PIO\n", ret);
860 tmio_mmc_enable_dma(host, false);
863 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
864 desc, cookie, host->sg_len);
867 static void tmio_mmc_start_dma_tx(struct tmio_mmc_host *host)
869 struct scatterlist *sg = host->sg_ptr, *sg_tmp;
870 struct dma_async_tx_descriptor *desc = NULL;
871 struct dma_chan *chan = host->chan_tx;
872 struct mfd_cell *cell = host->pdev->dev.platform_data;
873 struct tmio_mmc_data *pdata = cell->driver_data;
876 bool aligned = true, multiple = true;
877 unsigned int align = (1 << pdata->dma->alignment_shift) - 1;
879 for_each_sg(sg, sg_tmp, host->sg_len, i) {
880 if (sg_tmp->offset & align)
882 if (sg_tmp->length & align) {
888 if ((!aligned && (host->sg_len > 1 || sg->length > PAGE_CACHE_SIZE ||
889 align >= MAX_ALIGN)) || !multiple) {
894 /* The only sg element can be unaligned, use our bounce buffer then */
897 void *sg_vaddr = tmio_mmc_kmap_atomic(sg, &flags);
898 sg_init_one(&host->bounce_sg, host->bounce_buf, sg->length);
899 memcpy(host->bounce_buf, sg_vaddr, host->bounce_sg.length);
900 tmio_mmc_kunmap_atomic(sg, &flags, sg_vaddr);
901 host->sg_ptr = &host->bounce_sg;
905 ret = dma_map_sg(chan->device->dev, sg, host->sg_len, DMA_TO_DEVICE);
907 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
908 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
911 desc->callback = tmio_dma_complete;
912 desc->callback_param = host;
913 cookie = dmaengine_submit(desc);
915 dev_dbg(&host->pdev->dev, "%s(): mapped %d -> %d, cookie %d, rq %p\n",
916 __func__, host->sg_len, ret, cookie, host->mrq);
920 /* DMA failed, fall back to PIO */
923 host->chan_tx = NULL;
924 dma_release_channel(chan);
925 /* Free the Rx channel too */
926 chan = host->chan_rx;
928 host->chan_rx = NULL;
929 dma_release_channel(chan);
931 dev_warn(&host->pdev->dev,
932 "DMA failed: %d, falling back to PIO\n", ret);
933 tmio_mmc_enable_dma(host, false);
936 dev_dbg(&host->pdev->dev, "%s(): desc %p, cookie %d\n", __func__,
940 static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
941 struct mmc_data *data)
943 if (data->flags & MMC_DATA_READ) {
945 tmio_mmc_start_dma_rx(host);
948 tmio_mmc_start_dma_tx(host);
952 static void tmio_issue_tasklet_fn(unsigned long priv)
954 struct tmio_mmc_host *host = (struct tmio_mmc_host *)priv;
955 struct dma_chan *chan = host->chan_tx;
957 dma_async_issue_pending(chan);
960 static void tmio_tasklet_fn(unsigned long arg)
962 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
965 spin_lock_irqsave(&host->lock, flags);
970 if (host->data->flags & MMC_DATA_READ)
971 dma_unmap_sg(host->chan_rx->device->dev,
972 host->sg_ptr, host->sg_len,
975 dma_unmap_sg(host->chan_tx->device->dev,
976 host->sg_ptr, host->sg_len,
979 tmio_mmc_do_data_irq(host);
981 spin_unlock_irqrestore(&host->lock, flags);
984 /* It might be necessary to make filter MFD specific */
985 static bool tmio_mmc_filter(struct dma_chan *chan, void *arg)
987 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
992 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
993 struct tmio_mmc_data *pdata)
995 /* We can only either use DMA for both Tx and Rx or not use it at all */
1000 dma_cap_set(DMA_SLAVE, mask);
1002 host->chan_tx = dma_request_channel(mask, tmio_mmc_filter,
1003 pdata->dma->chan_priv_tx);
1004 dev_dbg(&host->pdev->dev, "%s: TX: got channel %p\n", __func__,
1010 host->chan_rx = dma_request_channel(mask, tmio_mmc_filter,
1011 pdata->dma->chan_priv_rx);
1012 dev_dbg(&host->pdev->dev, "%s: RX: got channel %p\n", __func__,
1015 if (!host->chan_rx) {
1016 dma_release_channel(host->chan_tx);
1017 host->chan_tx = NULL;
1021 tasklet_init(&host->dma_complete, tmio_tasklet_fn, (unsigned long)host);
1022 tasklet_init(&host->dma_issue, tmio_issue_tasklet_fn, (unsigned long)host);
1024 tmio_mmc_enable_dma(host, true);
1028 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
1030 if (host->chan_tx) {
1031 struct dma_chan *chan = host->chan_tx;
1032 host->chan_tx = NULL;
1033 dma_release_channel(chan);
1035 if (host->chan_rx) {
1036 struct dma_chan *chan = host->chan_rx;
1037 host->chan_rx = NULL;
1038 dma_release_channel(chan);
1042 static void tmio_check_bounce_buffer(struct tmio_mmc_host *host)
1046 static void tmio_mmc_start_dma(struct tmio_mmc_host *host,
1047 struct mmc_data *data)
1051 static void tmio_mmc_request_dma(struct tmio_mmc_host *host,
1052 struct tmio_mmc_data *pdata)
1054 host->chan_tx = NULL;
1055 host->chan_rx = NULL;
1058 static void tmio_mmc_release_dma(struct tmio_mmc_host *host)
1063 static int tmio_mmc_start_data(struct tmio_mmc_host *host,
1064 struct mmc_data *data)
1066 struct mfd_cell *cell = host->pdev->dev.platform_data;
1067 struct tmio_mmc_data *pdata = cell->driver_data;
1069 pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
1070 data->blksz, data->blocks);
1072 /* Some hardware cannot perform 2 byte requests in 4 bit mode */
1073 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1074 int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
1076 if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
1077 pr_err("%s: %d byte block unsupported in 4 bit mode\n",
1078 mmc_hostname(host->mmc), data->blksz);
1083 tmio_mmc_init_sg(host, data);
1086 /* Set transfer length / blocksize */
1087 sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
1088 sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
1090 tmio_mmc_start_dma(host, data);
1095 /* Process requests from the MMC layer */
1096 static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1098 struct tmio_mmc_host *host = mmc_priv(mmc);
1102 pr_debug("request not null\n");
1104 host->last_req_ts = jiffies;
1109 ret = tmio_mmc_start_data(host, mrq->data);
1114 ret = tmio_mmc_start_command(host, mrq->cmd);
1116 schedule_delayed_work(&host->delayed_reset_work,
1117 msecs_to_jiffies(2000));
1123 mrq->cmd->error = ret;
1124 mmc_request_done(mmc, mrq);
1127 /* Set MMC clock / power.
1128 * Note: This controller uses a simple divider scheme therefore it cannot
1129 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
1130 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
1133 static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1135 struct tmio_mmc_host *host = mmc_priv(mmc);
1138 tmio_mmc_set_clock(host, ios->clock);
1140 /* Power sequence - OFF -> ON -> UP */
1141 switch (ios->power_mode) {
1142 case MMC_POWER_OFF: /* power down SD bus */
1144 host->set_pwr(host->pdev, 0);
1145 tmio_mmc_clk_stop(host);
1147 case MMC_POWER_ON: /* power up SD bus */
1149 host->set_pwr(host->pdev, 1);
1151 case MMC_POWER_UP: /* start bus clock */
1152 tmio_mmc_clk_start(host);
1156 switch (ios->bus_width) {
1157 case MMC_BUS_WIDTH_1:
1158 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x80e0);
1160 case MMC_BUS_WIDTH_4:
1161 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, 0x00e0);
1165 /* Let things settle. delay taken from winCE driver */
1169 static int tmio_mmc_get_ro(struct mmc_host *mmc)
1171 struct tmio_mmc_host *host = mmc_priv(mmc);
1172 struct mfd_cell *cell = host->pdev->dev.platform_data;
1173 struct tmio_mmc_data *pdata = cell->driver_data;
1175 return ((pdata->flags & TMIO_MMC_WRPROTECT_DISABLE) ||
1176 (sd_ctrl_read32(host, CTL_STATUS) & TMIO_STAT_WRPROTECT)) ? 0 : 1;
1179 static int tmio_mmc_get_cd(struct mmc_host *mmc)
1181 struct tmio_mmc_host *host = mmc_priv(mmc);
1182 struct mfd_cell *cell = host->pdev->dev.platform_data;
1183 struct tmio_mmc_data *pdata = cell->driver_data;
1188 return pdata->get_cd(host->pdev);
1191 static const struct mmc_host_ops tmio_mmc_ops = {
1192 .request = tmio_mmc_request,
1193 .set_ios = tmio_mmc_set_ios,
1194 .get_ro = tmio_mmc_get_ro,
1195 .get_cd = tmio_mmc_get_cd,
1196 .enable_sdio_irq = tmio_mmc_enable_sdio_irq,
1200 static int tmio_mmc_suspend(struct platform_device *dev, pm_message_t state)
1202 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1203 struct mmc_host *mmc = platform_get_drvdata(dev);
1206 ret = mmc_suspend_host(mmc);
1208 /* Tell MFD core it can disable us now.*/
1209 if (!ret && cell->disable)
1215 static int tmio_mmc_resume(struct platform_device *dev)
1217 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1218 struct mmc_host *mmc = platform_get_drvdata(dev);
1221 /* Tell the MFD core we are ready to be enabled */
1223 ret = cell->resume(dev);
1228 mmc_resume_host(mmc);
1234 #define tmio_mmc_suspend NULL
1235 #define tmio_mmc_resume NULL
1238 static int __devinit tmio_mmc_probe(struct platform_device *dev)
1240 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1241 struct tmio_mmc_data *pdata;
1242 struct resource *res_ctl;
1243 struct tmio_mmc_host *host;
1244 struct mmc_host *mmc;
1246 u32 irq_mask = TMIO_MASK_CMD;
1248 if (dev->num_resources != 2)
1251 res_ctl = platform_get_resource(dev, IORESOURCE_MEM, 0);
1255 pdata = cell->driver_data;
1256 if (!pdata || !pdata->hclk)
1261 mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &dev->dev);
1265 host = mmc_priv(mmc);
1268 platform_set_drvdata(dev, mmc);
1270 host->set_pwr = pdata->set_pwr;
1271 host->set_clk_div = pdata->set_clk_div;
1273 /* SD control register space size is 0x200, 0x400 for bus_shift=1 */
1274 host->bus_shift = resource_size(res_ctl) >> 10;
1276 host->ctl = ioremap(res_ctl->start, resource_size(res_ctl));
1280 mmc->ops = &tmio_mmc_ops;
1281 mmc->caps = MMC_CAP_4_BIT_DATA | pdata->capabilities;
1282 mmc->f_max = pdata->hclk;
1283 mmc->f_min = mmc->f_max / 512;
1285 mmc->max_blk_size = 512;
1286 mmc->max_blk_count = (PAGE_CACHE_SIZE / mmc->max_blk_size) *
1288 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1289 mmc->max_seg_size = mmc->max_req_size;
1290 if (pdata->ocr_mask)
1291 mmc->ocr_avail = pdata->ocr_mask;
1293 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1295 /* Tell the MFD core we are ready to be enabled */
1297 ret = cell->enable(dev);
1302 tmio_mmc_clk_stop(host);
1305 ret = platform_get_irq(dev, 0);
1311 disable_mmc_irqs(host, TMIO_MASK_ALL);
1312 if (pdata->flags & TMIO_MMC_SDIO_IRQ)
1313 tmio_mmc_enable_sdio_irq(mmc, 0);
1315 ret = request_irq(host->irq, tmio_mmc_irq, IRQF_DISABLED |
1316 IRQF_TRIGGER_FALLING, dev_name(&dev->dev), host);
1320 spin_lock_init(&host->lock);
1322 /* Init delayed work for request timeouts */
1323 INIT_DELAYED_WORK(&host->delayed_reset_work, tmio_mmc_reset_work);
1325 /* See if we also get DMA */
1326 tmio_mmc_request_dma(host, pdata);
1330 pr_info("%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
1331 (unsigned long)host->ctl, host->irq);
1333 /* Unmask the IRQs we want to know about */
1335 irq_mask |= TMIO_MASK_READOP;
1337 irq_mask |= TMIO_MASK_WRITEOP;
1338 enable_mmc_irqs(host, irq_mask);
1353 static int __devexit tmio_mmc_remove(struct platform_device *dev)
1355 struct mfd_cell *cell = (struct mfd_cell *)dev->dev.platform_data;
1356 struct mmc_host *mmc = platform_get_drvdata(dev);
1358 platform_set_drvdata(dev, NULL);
1361 struct tmio_mmc_host *host = mmc_priv(mmc);
1362 mmc_remove_host(mmc);
1363 cancel_delayed_work_sync(&host->delayed_reset_work);
1364 tmio_mmc_release_dma(host);
1365 free_irq(host->irq, host);
1375 /* ------------------- device registration ----------------------- */
1377 static struct platform_driver tmio_mmc_driver = {
1380 .owner = THIS_MODULE,
1382 .probe = tmio_mmc_probe,
1383 .remove = __devexit_p(tmio_mmc_remove),
1384 .suspend = tmio_mmc_suspend,
1385 .resume = tmio_mmc_resume,
1389 static int __init tmio_mmc_init(void)
1391 return platform_driver_register(&tmio_mmc_driver);
1394 static void __exit tmio_mmc_exit(void)
1396 platform_driver_unregister(&tmio_mmc_driver);
1399 module_init(tmio_mmc_init);
1400 module_exit(tmio_mmc_exit);
1402 MODULE_DESCRIPTION("Toshiba TMIO SD/MMC driver");
1403 MODULE_AUTHOR("Ian Molton <spyro@f2s.com>");
1404 MODULE_LICENSE("GPL v2");
1405 MODULE_ALIAS("platform:tmio-mmc");