drivers/mmc/host/sh_mmcif.c

   1 /*
   2  * MMCIF eMMC driver.
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Yusuke Goda <yusuke.goda.sx@renesas.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  *
  12  * TODO
  13  *  1. DMA
  14  *  2. Power management
  15  *  3. Handle MMC errors better
  16  *
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/mmc/card.h>
  25 #include <linux/mmc/core.h>
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/mmc.h>
  28 #include <linux/mmc/sdio.h>
  29 #include <linux/mmc/sh_mmcif.h>
  30 #include <linux/pagemap.h>
  31 #include <linux/platform_device.h>
  32
  33 #define DRIVER_NAME     "sh_mmcif"
  34 #define DRIVER_VERSION  "2010-04-28"
  35
  36 /* CE_CMD_SET */
  37 #define CMD_MASK                0x3f000000
  38 #define CMD_SET_RTYP_NO         ((0 << 23) | (0 << 22))
  39 #define CMD_SET_RTYP_6B         ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
  40 #define CMD_SET_RTYP_17B        ((1 << 23) | (0 << 22)) /* R2 */
  41 #define CMD_SET_RBSY            (1 << 21) /* R1b */
  42 #define CMD_SET_CCSEN           (1 << 20)
  43 #define CMD_SET_WDAT            (1 << 19) /* 1: on data, 0: no data */
  44 #define CMD_SET_DWEN            (1 << 18) /* 1: write, 0: read */
  45 #define CMD_SET_CMLTE           (1 << 17) /* 1: multi block trans, 0: single */
  46 #define CMD_SET_CMD12EN         (1 << 16) /* 1: CMD12 auto issue */
  47 #define CMD_SET_RIDXC_INDEX     ((0 << 15) | (0 << 14)) /* index check */
  48 #define CMD_SET_RIDXC_BITS      ((0 << 15) | (1 << 14)) /* check bits check */
  49 #define CMD_SET_RIDXC_NO        ((1 << 15) | (0 << 14)) /* no check */
  50 #define CMD_SET_CRC7C           ((0 << 13) | (0 << 12)) /* CRC7 check*/
  51 #define CMD_SET_CRC7C_BITS      ((0 << 13) | (1 << 12)) /* check bits check*/
  52 #define CMD_SET_CRC7C_INTERNAL  ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
  53 #define CMD_SET_CRC16C          (1 << 10) /* 0: CRC16 check*/
  54 #define CMD_SET_CRCSTE          (1 << 8) /* 1: not receive CRC status */
  55 #define CMD_SET_TBIT            (1 << 7) /* 1: tran mission bit "Low" */
  56 #define CMD_SET_OPDM            (1 << 6) /* 1: open/drain */
  57 #define CMD_SET_CCSH            (1 << 5)
  58 #define CMD_SET_DATW_1          ((0 << 1) | (0 << 0)) /* 1bit */
  59 #define CMD_SET_DATW_4          ((0 << 1) | (1 << 0)) /* 4bit */
  60 #define CMD_SET_DATW_8          ((1 << 1) | (0 << 0)) /* 8bit */
  61
  62 /* CE_CMD_CTRL */
  63 #define CMD_CTRL_BREAK          (1 << 0)
  64
  65 /* CE_BLOCK_SET */
  66 #define BLOCK_SIZE_MASK         0x0000ffff
  67
  68 /* CE_INT */
  69 #define INT_CCSDE               (1 << 29)
  70 #define INT_CMD12DRE            (1 << 26)
  71 #define INT_CMD12RBE            (1 << 25)
  72 #define INT_CMD12CRE            (1 << 24)
  73 #define INT_DTRANE              (1 << 23)
  74 #define INT_BUFRE               (1 << 22)
  75 #define INT_BUFWEN              (1 << 21)
  76 #define INT_BUFREN              (1 << 20)
  77 #define INT_CCSRCV              (1 << 19)
  78 #define INT_RBSYE               (1 << 17)
  79 #define INT_CRSPE               (1 << 16)
  80 #define INT_CMDVIO              (1 << 15)
  81 #define INT_BUFVIO              (1 << 14)
  82 #define INT_WDATERR             (1 << 11)
  83 #define INT_RDATERR             (1 << 10)
  84 #define INT_RIDXERR             (1 << 9)
  85 #define INT_RSPERR              (1 << 8)
  86 #define INT_CCSTO               (1 << 5)
  87 #define INT_CRCSTO              (1 << 4)
  88 #define INT_WDATTO              (1 << 3)
  89 #define INT_RDATTO              (1 << 2)
  90 #define INT_RBSYTO              (1 << 1)
  91 #define INT_RSPTO               (1 << 0)
  92 #define INT_ERR_STS             (INT_CMDVIO | INT_BUFVIO | INT_WDATERR |  \
  93                                  INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
  94                                  INT_CCSTO | INT_CRCSTO | INT_WDATTO |    \
  95                                  INT_RDATTO | INT_RBSYTO | INT_RSPTO)
  96
  97 /* CE_INT_MASK */
  98 #define MASK_ALL                0x00000000
  99 #define MASK_MCCSDE             (1 << 29)
 100 #define MASK_MCMD12DRE          (1 << 26)
 101 #define MASK_MCMD12RBE          (1 << 25)
 102 #define MASK_MCMD12CRE          (1 << 24)
 103 #define MASK_MDTRANE            (1 << 23)
 104 #define MASK_MBUFRE             (1 << 22)
 105 #define MASK_MBUFWEN            (1 << 21)
 106 #define MASK_MBUFREN            (1 << 20)
 107 #define MASK_MCCSRCV            (1 << 19)
 108 #define MASK_MRBSYE             (1 << 17)
 109 #define MASK_MCRSPE             (1 << 16)
 110 #define MASK_MCMDVIO            (1 << 15)
 111 #define MASK_MBUFVIO            (1 << 14)
 112 #define MASK_MWDATERR           (1 << 11)
 113 #define MASK_MRDATERR           (1 << 10)
 114 #define MASK_MRIDXERR           (1 << 9)
 115 #define MASK_MRSPERR            (1 << 8)
 116 #define MASK_MCCSTO             (1 << 5)
 117 #define MASK_MCRCSTO            (1 << 4)
 118 #define MASK_MWDATTO            (1 << 3)
 119 #define MASK_MRDATTO            (1 << 2)
 120 #define MASK_MRBSYTO            (1 << 1)
 121 #define MASK_MRSPTO             (1 << 0)
 122
 123 /* CE_HOST_STS1 */
 124 #define STS1_CMDSEQ             (1 << 31)
 125
 126 /* CE_HOST_STS2 */
 127 #define STS2_CRCSTE             (1 << 31)
 128 #define STS2_CRC16E             (1 << 30)
 129 #define STS2_AC12CRCE           (1 << 29)
 130 #define STS2_RSPCRC7E           (1 << 28)
 131 #define STS2_CRCSTEBE           (1 << 27)
 132 #define STS2_RDATEBE            (1 << 26)
 133 #define STS2_AC12REBE           (1 << 25)
 134 #define STS2_RSPEBE             (1 << 24)
 135 #define STS2_AC12IDXE           (1 << 23)
 136 #define STS2_RSPIDXE            (1 << 22)
 137 #define STS2_CCSTO              (1 << 15)
 138 #define STS2_RDATTO             (1 << 14)
 139 #define STS2_DATBSYTO           (1 << 13)
 140 #define STS2_CRCSTTO            (1 << 12)
 141 #define STS2_AC12BSYTO          (1 << 11)
 142 #define STS2_RSPBSYTO           (1 << 10)
 143 #define STS2_AC12RSPTO          (1 << 9)
 144 #define STS2_RSPTO              (1 << 8)
 145 #define STS2_CRC_ERR            (STS2_CRCSTE | STS2_CRC16E |            \
 146                                  STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
 147 #define STS2_TIMEOUT_ERR        (STS2_CCSTO | STS2_RDATTO |             \
 148                                  STS2_DATBSYTO | STS2_CRCSTTO |         \
 149                                  STS2_AC12BSYTO | STS2_RSPBSYTO |       \
 150                                  STS2_AC12RSPTO | STS2_RSPTO)
 151
 152 #define CLKDEV_EMMC_DATA        52000000 /* 52MHz */
 153 #define CLKDEV_MMC_DATA         20000000 /* 20MHz */
 154 #define CLKDEV_INIT             400000   /* 400 KHz */
 155
 156 struct sh_mmcif_host {
 157         struct mmc_host *mmc;
 158         struct mmc_data *data;
 159         struct platform_device *pd;
 160         struct clk *hclk;
 161         unsigned int clk;
 162         int bus_width;
 163         bool sd_error;
 164         long timeout;
 165         void __iomem *addr;
 166         struct completion intr_wait;
 167
 168         /* DMA support */
 169         struct dma_chan         *chan_rx;
 170         struct dma_chan         *chan_tx;
 171         struct completion       dma_complete;
 172         bool                    dma_active;
 173 };
 174
 175 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
 176                                         unsigned int reg, u32 val)
 177 {
 178         writel(val | readl(host->addr + reg), host->addr + reg);
 179 }
 180
 181 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
 182                                         unsigned int reg, u32 val)
 183 {
 184         writel(~val & readl(host->addr + reg), host->addr + reg);
 185 }
 186
 187 static void mmcif_dma_complete(void *arg)
 188 {
 189         struct sh_mmcif_host *host = arg;
 190         dev_dbg(&host->pd->dev, "Command completed\n");
 191
 192         if (WARN(!host->data, "%s: NULL data in DMA completion!\n",
 193                  dev_name(&host->pd->dev)))
 194                 return;
 195
 196         if (host->data->flags & MMC_DATA_READ)
 197                 dma_unmap_sg(host->chan_rx->device->dev,
 198                              host->data->sg, host->data->sg_len,
 199                              DMA_FROM_DEVICE);
 200         else
 201                 dma_unmap_sg(host->chan_tx->device->dev,
 202                              host->data->sg, host->data->sg_len,
 203                              DMA_TO_DEVICE);
 204
 205         complete(&host->dma_complete);
 206 }
 207
 208 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
 209 {
 210         struct scatterlist *sg = host->data->sg;
 211         struct dma_async_tx_descriptor *desc = NULL;
 212         struct dma_chan *chan = host->chan_rx;
 213         dma_cookie_t cookie = -EINVAL;
 214         int ret;
 215
 216         ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
 217                          DMA_FROM_DEVICE);
 218         if (ret > 0) {
 219                 host->dma_active = true;
 220                 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
 221                         DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 222         }
 223
 224         if (desc) {
 225                 desc->callback = mmcif_dma_complete;
 226                 desc->callback_param = host;
 227                 cookie = dmaengine_submit(desc);
 228                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
 229                 dma_async_issue_pending(chan);
 230         }
 231         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 232                 __func__, host->data->sg_len, ret, cookie);
 233
 234         if (!desc) {
 235                 /* DMA failed, fall back to PIO */
 236                 if (ret >= 0)
 237                         ret = -EIO;
 238                 host->chan_rx = NULL;
 239                 host->dma_active = false;
 240                 dma_release_channel(chan);
 241                 /* Free the Tx channel too */
 242                 chan = host->chan_tx;
 243                 if (chan) {
 244                         host->chan_tx = NULL;
 245                         dma_release_channel(chan);
 246                 }
 247                 dev_warn(&host->pd->dev,
 248                          "DMA failed: %d, falling back to PIO\n", ret);
 249                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 250         }
 251
 252         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
 253                 desc, cookie, host->data->sg_len);
 254 }
 255
 256 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
 257 {
 258         struct scatterlist *sg = host->data->sg;
 259         struct dma_async_tx_descriptor *desc = NULL;
 260         struct dma_chan *chan = host->chan_tx;
 261         dma_cookie_t cookie = -EINVAL;
 262         int ret;
 263
 264         ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len,
 265                          DMA_TO_DEVICE);
 266         if (ret > 0) {
 267                 host->dma_active = true;
 268                 desc = chan->device->device_prep_slave_sg(chan, sg, ret,
 269                         DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 270         }
 271
 272         if (desc) {
 273                 desc->callback = mmcif_dma_complete;
 274                 desc->callback_param = host;
 275                 cookie = dmaengine_submit(desc);
 276                 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
 277                 dma_async_issue_pending(chan);
 278         }
 279         dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n",
 280                 __func__, host->data->sg_len, ret, cookie);
 281
 282         if (!desc) {
 283                 /* DMA failed, fall back to PIO */
 284                 if (ret >= 0)
 285                         ret = -EIO;
 286                 host->chan_tx = NULL;
 287                 host->dma_active = false;
 288                 dma_release_channel(chan);
 289                 /* Free the Rx channel too */
 290                 chan = host->chan_rx;
 291                 if (chan) {
 292                         host->chan_rx = NULL;
 293                         dma_release_channel(chan);
 294                 }
 295                 dev_warn(&host->pd->dev,
 296                          "DMA failed: %d, falling back to PIO\n", ret);
 297                 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 298         }
 299
 300         dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__,
 301                 desc, cookie);
 302 }
 303
 304 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg)
 305 {
 306         dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg);
 307         chan->private = arg;
 308         return true;
 309 }
 310
 311 static void sh_mmcif_request_dma(struct sh_mmcif_host *host,
 312                                  struct sh_mmcif_plat_data *pdata)
 313 {
 314         host->dma_active = false;
 315
 316         /* We can only either use DMA for both Tx and Rx or not use it at all */
 317         if (pdata->dma) {
 318                 dma_cap_mask_t mask;
 319
 320                 dma_cap_zero(mask);
 321                 dma_cap_set(DMA_SLAVE, mask);
 322
 323                 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter,
 324                                                     &pdata->dma->chan_priv_tx);
 325                 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__,
 326                         host->chan_tx);
 327
 328                 if (!host->chan_tx)
 329                         return;
 330
 331                 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter,
 332                                                     &pdata->dma->chan_priv_rx);
 333                 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__,
 334                         host->chan_rx);
 335
 336                 if (!host->chan_rx) {
 337                         dma_release_channel(host->chan_tx);
 338                         host->chan_tx = NULL;
 339                         return;
 340                 }
 341
 342                 init_completion(&host->dma_complete);
 343         }
 344 }
 345
 346 static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
 347 {
 348         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 349         /* Descriptors are freed automatically */
 350         if (host->chan_tx) {
 351                 struct dma_chan *chan = host->chan_tx;
 352                 host->chan_tx = NULL;
 353                 dma_release_channel(chan);
 354         }
 355         if (host->chan_rx) {
 356                 struct dma_chan *chan = host->chan_rx;
 357                 host->chan_rx = NULL;
 358                 dma_release_channel(chan);
 359         }
 360
 361         host->dma_active = false;
 362 }
 363
 364 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
 365 {
 366         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 367
 368         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 369         sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
 370
 371         if (!clk)
 372                 return;
 373         if (p->sup_pclk && clk == host->clk)
 374                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
 375         else
 376                 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
 377                         (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16));
 378
 379         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
 380 }
 381
 382 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
 383 {
 384         u32 tmp;
 385
 386         tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
 387
 388         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
 389         sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
 390         sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
 391                 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
 392         /* byte swap on */
 393         sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
 394 }
 395
 396 static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
 397 {
 398         u32 state1, state2;
 399         int ret, timeout = 10000000;
 400
 401         host->sd_error = false;
 402
 403         state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
 404         state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
 405         dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1);
 406         dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2);
 407
 408         if (state1 & STS1_CMDSEQ) {
 409                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
 410                 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
 411                 while (1) {
 412                         timeout--;
 413                         if (timeout < 0) {
 414                                 dev_err(&host->pd->dev,
 415                                         "Forceed end of command sequence timeout err\n");
 416                                 return -EIO;
 417                         }
 418                         if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
 419                                                                 & STS1_CMDSEQ))
 420                                 break;
 421                         mdelay(1);
 422                 }
 423                 sh_mmcif_sync_reset(host);
 424                 dev_dbg(&host->pd->dev, "Forced end of command sequence\n");
 425                 return -EIO;
 426         }
 427
 428         if (state2 & STS2_CRC_ERR) {
 429                 dev_dbg(&host->pd->dev, ": Happened CRC error\n");
 430                 ret = -EIO;
 431         } else if (state2 & STS2_TIMEOUT_ERR) {
 432                 dev_dbg(&host->pd->dev, ": Happened Timeout error\n");
 433                 ret = -ETIMEDOUT;
 434         } else {
 435                 dev_dbg(&host->pd->dev, ": Happened End/Index error\n");
 436                 ret = -EIO;
 437         }
 438         return ret;
 439 }
 440
 441 static int sh_mmcif_single_read(struct sh_mmcif_host *host,
 442                                         struct mmc_request *mrq)
 443 {
 444         struct mmc_data *data = mrq->data;
 445         long time;
 446         u32 blocksize, i, *p = sg_virt(data->sg);
 447
 448         /* buf read enable */
 449         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 450         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 451                         host->timeout);
 452         if (time <= 0 || host->sd_error)
 453                 return sh_mmcif_error_manage(host);
 454
 455         blocksize = (BLOCK_SIZE_MASK &
 456                         sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
 457         for (i = 0; i < blocksize / 4; i++)
 458                 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
 459
 460         /* buffer read end */
 461         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 462         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 463                         host->timeout);
 464         if (time <= 0 || host->sd_error)
 465                 return sh_mmcif_error_manage(host);
 466
 467         return 0;
 468 }
 469
 470 static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
 471                                         struct mmc_request *mrq)
 472 {
 473         struct mmc_data *data = mrq->data;
 474         long time;
 475         u32 blocksize, i, j, sec, *p;
 476
 477         blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
 478                                                      MMCIF_CE_BLOCK_SET);
 479         for (j = 0; j < data->sg_len; j++) {
 480                 p = sg_virt(data->sg);
 481                 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
 482                         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 483                         /* buf read enable */
 484                         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 485                                 host->timeout);
 486
 487                         if (time <= 0 || host->sd_error)
 488                                 return sh_mmcif_error_manage(host);
 489
 490                         for (i = 0; i < blocksize / 4; i++)
 491                                 *p++ = sh_mmcif_readl(host->addr,
 492                                                       MMCIF_CE_DATA);
 493                 }
 494                 if (j < data->sg_len - 1)
 495                         data->sg++;
 496         }
 497         return 0;
 498 }
 499
 500 static int sh_mmcif_single_write(struct sh_mmcif_host *host,
 501                                         struct mmc_request *mrq)
 502 {
 503         struct mmc_data *data = mrq->data;
 504         long time;
 505         u32 blocksize, i, *p = sg_virt(data->sg);
 506
 507         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 508
 509         /* buf write enable */
 510         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 511                         host->timeout);
 512         if (time <= 0 || host->sd_error)
 513                 return sh_mmcif_error_manage(host);
 514
 515         blocksize = (BLOCK_SIZE_MASK &
 516                         sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3;
 517         for (i = 0; i < blocksize / 4; i++)
 518                 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
 519
 520         /* buffer write end */
 521         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 522
 523         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 524                         host->timeout);
 525         if (time <= 0 || host->sd_error)
 526                 return sh_mmcif_error_manage(host);
 527
 528         return 0;
 529 }
 530
 531 static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
 532                                                 struct mmc_request *mrq)
 533 {
 534         struct mmc_data *data = mrq->data;
 535         long time;
 536         u32 i, sec, j, blocksize, *p;
 537
 538         blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr,
 539                                                      MMCIF_CE_BLOCK_SET);
 540
 541         for (j = 0; j < data->sg_len; j++) {
 542                 p = sg_virt(data->sg);
 543                 for (sec = 0; sec < data->sg->length / blocksize; sec++) {
 544                         sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 545                         /* buf write enable*/
 546                         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 547                                 host->timeout);
 548
 549                         if (time <= 0 || host->sd_error)
 550                                 return sh_mmcif_error_manage(host);
 551
 552                         for (i = 0; i < blocksize / 4; i++)
 553                                 sh_mmcif_writel(host->addr,
 554                                                 MMCIF_CE_DATA, *p++);
 555                 }
 556                 if (j < data->sg_len - 1)
 557                         data->sg++;
 558         }
 559         return 0;
 560 }
 561
 562 static void sh_mmcif_get_response(struct sh_mmcif_host *host,
 563                                                 struct mmc_command *cmd)
 564 {
 565         if (cmd->flags & MMC_RSP_136) {
 566                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
 567                 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
 568                 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
 569                 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 570         } else
 571                 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
 572 }
 573
 574 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
 575                                                 struct mmc_command *cmd)
 576 {
 577         cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
 578 }
 579
 580 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
 581                 struct mmc_request *mrq, struct mmc_command *cmd, u32 opc)
 582 {
 583         u32 tmp = 0;
 584
 585         /* Response Type check */
 586         switch (mmc_resp_type(cmd)) {
 587         case MMC_RSP_NONE:
 588                 tmp |= CMD_SET_RTYP_NO;
 589                 break;
 590         case MMC_RSP_R1:
 591         case MMC_RSP_R1B:
 592         case MMC_RSP_R3:
 593                 tmp |= CMD_SET_RTYP_6B;
 594                 break;
 595         case MMC_RSP_R2:
 596                 tmp |= CMD_SET_RTYP_17B;
 597                 break;
 598         default:
 599                 dev_err(&host->pd->dev, "Unsupported response type.\n");
 600                 break;
 601         }
 602         switch (opc) {
 603         /* RBSY */
 604         case MMC_SWITCH:
 605         case MMC_STOP_TRANSMISSION:
 606         case MMC_SET_WRITE_PROT:
 607         case MMC_CLR_WRITE_PROT:
 608         case MMC_ERASE:
 609         case MMC_GEN_CMD:
 610                 tmp |= CMD_SET_RBSY;
 611                 break;
 612         }
 613         /* WDAT / DATW */
 614         if (host->data) {
 615                 tmp |= CMD_SET_WDAT;
 616                 switch (host->bus_width) {
 617                 case MMC_BUS_WIDTH_1:
 618                         tmp |= CMD_SET_DATW_1;
 619                         break;
 620                 case MMC_BUS_WIDTH_4:
 621                         tmp |= CMD_SET_DATW_4;
 622                         break;
 623                 case MMC_BUS_WIDTH_8:
 624                         tmp |= CMD_SET_DATW_8;
 625                         break;
 626                 default:
 627                         dev_err(&host->pd->dev, "Unsupported bus width.\n");
 628                         break;
 629                 }
 630         }
 631         /* DWEN */
 632         if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
 633                 tmp |= CMD_SET_DWEN;
 634         /* CMLTE/CMD12EN */
 635         if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
 636                 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
 637                 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
 638                                         mrq->data->blocks << 16);
 639         }
 640         /* RIDXC[1:0] check bits */
 641         if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
 642             opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 643                 tmp |= CMD_SET_RIDXC_BITS;
 644         /* RCRC7C[1:0] check bits */
 645         if (opc == MMC_SEND_OP_COND)
 646                 tmp |= CMD_SET_CRC7C_BITS;
 647         /* RCRC7C[1:0] internal CRC7 */
 648         if (opc == MMC_ALL_SEND_CID ||
 649                 opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
 650                 tmp |= CMD_SET_CRC7C_INTERNAL;
 651
 652         return opc = ((opc << 24) | tmp);
 653 }
 654
 655 static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
 656                                 struct mmc_request *mrq, u32 opc)
 657 {
 658         int ret;
 659
 660         switch (opc) {
 661         case MMC_READ_MULTIPLE_BLOCK:
 662                 ret = sh_mmcif_multi_read(host, mrq);
 663                 break;
 664         case MMC_WRITE_MULTIPLE_BLOCK:
 665                 ret = sh_mmcif_multi_write(host, mrq);
 666                 break;
 667         case MMC_WRITE_BLOCK:
 668                 ret = sh_mmcif_single_write(host, mrq);
 669                 break;
 670         case MMC_READ_SINGLE_BLOCK:
 671         case MMC_SEND_EXT_CSD:
 672                 ret = sh_mmcif_single_read(host, mrq);
 673                 break;
 674         default:
 675                 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc);
 676                 ret = -EINVAL;
 677                 break;
 678         }
 679         return ret;
 680 }
 681
 682 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
 683                         struct mmc_request *mrq, struct mmc_command *cmd)
 684 {
 685         long time;
 686         int ret = 0, mask = 0;
 687         u32 opc = cmd->opcode;
 688
 689         switch (opc) {
 690         /* respons busy check */
 691         case MMC_SWITCH:
 692         case MMC_STOP_TRANSMISSION:
 693         case MMC_SET_WRITE_PROT:
 694         case MMC_CLR_WRITE_PROT:
 695         case MMC_ERASE:
 696         case MMC_GEN_CMD:
 697                 mask = MASK_MRBSYE;
 698                 break;
 699         default:
 700                 mask = MASK_MCRSPE;
 701                 break;
 702         }
 703         mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR |
 704                 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR |
 705                 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO |
 706                 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO;
 707
 708         if (host->data) {
 709                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
 710                 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
 711                                 mrq->data->blksz);
 712         }
 713         opc = sh_mmcif_set_cmd(host, mrq, cmd, opc);
 714
 715         sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
 716         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
 717         /* set arg */
 718         sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
 719         /* set cmd */
 720         sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
 721
 722         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 723                 host->timeout);
 724         if (time <= 0) {
 725                 cmd->error = sh_mmcif_error_manage(host);
 726                 return;
 727         }
 728         if (host->sd_error) {
 729                 switch (cmd->opcode) {
 730                 case MMC_ALL_SEND_CID:
 731                 case MMC_SELECT_CARD:
 732                 case MMC_APP_CMD:
 733                         cmd->error = -ETIMEDOUT;
 734                         break;
 735                 default:
 736                         dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n",
 737                                         cmd->opcode);
 738                         cmd->error = sh_mmcif_error_manage(host);
 739                         break;
 740                 }
 741                 host->sd_error = false;
 742                 return;
 743         }
 744         if (!(cmd->flags & MMC_RSP_PRESENT)) {
 745                 cmd->error = 0;
 746                 return;
 747         }
 748         sh_mmcif_get_response(host, cmd);
 749         if (host->data) {
 750                 if (!host->dma_active) {
 751                         ret = sh_mmcif_data_trans(host, mrq, cmd->opcode);
 752                 } else {
 753                         long time =
 754                                 wait_for_completion_interruptible_timeout(&host->dma_complete,
 755                                                                           host->timeout);
 756                         if (!time)
 757                                 ret = -ETIMEDOUT;
 758                         else if (time < 0)
 759                                 ret = time;
 760                         sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
 761                                         BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
 762                         host->dma_active = false;
 763                 }
 764                 if (ret < 0)
 765                         mrq->data->bytes_xfered = 0;
 766                 else
 767                         mrq->data->bytes_xfered =
 768                                 mrq->data->blocks * mrq->data->blksz;
 769         }
 770         cmd->error = ret;
 771 }
 772
 773 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
 774                 struct mmc_request *mrq, struct mmc_command *cmd)
 775 {
 776         long time;
 777
 778         if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK)
 779                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 780         else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK)
 781                 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 782         else {
 783                 dev_err(&host->pd->dev, "unsupported stop cmd\n");
 784                 cmd->error = sh_mmcif_error_manage(host);
 785                 return;
 786         }
 787
 788         time = wait_for_completion_interruptible_timeout(&host->intr_wait,
 789                         host->timeout);
 790         if (time <= 0 || host->sd_error) {
 791                 cmd->error = sh_mmcif_error_manage(host);
 792                 return;
 793         }
 794         sh_mmcif_get_cmd12response(host, cmd);
 795         cmd->error = 0;
 796 }
 797
 798 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
 799 {
 800         struct sh_mmcif_host *host = mmc_priv(mmc);
 801
 802         switch (mrq->cmd->opcode) {
 803         /* MMCIF does not support SD/SDIO command */
 804         case SD_IO_SEND_OP_COND:
 805         case MMC_APP_CMD:
 806                 mrq->cmd->error = -ETIMEDOUT;
 807                 mmc_request_done(mmc, mrq);
 808                 return;
 809         case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
 810                 if (!mrq->data) {
 811                         /* send_if_cond cmd (not support) */
 812                         mrq->cmd->error = -ETIMEDOUT;
 813                         mmc_request_done(mmc, mrq);
 814                         return;
 815                 }
 816                 break;
 817         default:
 818                 break;
 819         }
 820         host->data = mrq->data;
 821         if (mrq->data) {
 822                 if (mrq->data->flags & MMC_DATA_READ) {
 823                         if (host->chan_rx)
 824                                 sh_mmcif_start_dma_rx(host);
 825                 } else {
 826                         if (host->chan_tx)
 827                                 sh_mmcif_start_dma_tx(host);
 828                 }
 829         }
 830         sh_mmcif_start_cmd(host, mrq, mrq->cmd);
 831         host->data = NULL;
 832
 833         if (mrq->cmd->error != 0) {
 834                 mmc_request_done(mmc, mrq);
 835                 return;
 836         }
 837         if (mrq->stop)
 838                 sh_mmcif_stop_cmd(host, mrq, mrq->stop);
 839         mmc_request_done(mmc, mrq);
 840 }
 841
 842 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 843 {
 844         struct sh_mmcif_host *host = mmc_priv(mmc);
 845         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 846
 847         if (ios->power_mode == MMC_POWER_UP) {
 848                 if (p->set_pwr)
 849                         p->set_pwr(host->pd, ios->power_mode);
 850         } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
 851                 /* clock stop */
 852                 sh_mmcif_clock_control(host, 0);
 853                 if (ios->power_mode == MMC_POWER_OFF && p->down_pwr)
 854                         p->down_pwr(host->pd);
 855                 return;
 856         }
 857
 858         if (ios->clock)
 859                 sh_mmcif_clock_control(host, ios->clock);
 860
 861         host->bus_width = ios->bus_width;
 862 }
 863
 864 static int sh_mmcif_get_cd(struct mmc_host *mmc)
 865 {
 866         struct sh_mmcif_host *host = mmc_priv(mmc);
 867         struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
 868
 869         if (!p->get_cd)
 870                 return -ENOSYS;
 871         else
 872                 return p->get_cd(host->pd);
 873 }
 874
 875 static struct mmc_host_ops sh_mmcif_ops = {
 876         .request        = sh_mmcif_request,
 877         .set_ios        = sh_mmcif_set_ios,
 878         .get_cd         = sh_mmcif_get_cd,
 879 };
 880
 881 static void sh_mmcif_detect(struct mmc_host *mmc)
 882 {
 883         mmc_detect_change(mmc, 0);
 884 }
 885
 886 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
 887 {
 888         struct sh_mmcif_host *host = dev_id;
 889         u32 state;
 890         int err = 0;
 891
 892         state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
 893
 894         if (state & INT_RBSYE) {
 895                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
 896                                 ~(INT_RBSYE | INT_CRSPE));
 897                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE);
 898         } else if (state & INT_CRSPE) {
 899                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE);
 900                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE);
 901         } else if (state & INT_BUFREN) {
 902                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN);
 903                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
 904         } else if (state & INT_BUFWEN) {
 905                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN);
 906                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
 907         } else if (state & INT_CMD12DRE) {
 908                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
 909                         ~(INT_CMD12DRE | INT_CMD12RBE |
 910                           INT_CMD12CRE | INT_BUFRE));
 911                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
 912         } else if (state & INT_BUFRE) {
 913                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE);
 914                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
 915         } else if (state & INT_DTRANE) {
 916                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE);
 917                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
 918         } else if (state & INT_CMD12RBE) {
 919                 sh_mmcif_writel(host->addr, MMCIF_CE_INT,
 920                                 ~(INT_CMD12RBE | INT_CMD12CRE));
 921                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
 922         } else if (state & INT_ERR_STS) {
 923                 /* err interrupts */
 924                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
 925                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
 926                 err = 1;
 927         } else {
 928                 dev_dbg(&host->pd->dev, "Not support int\n");
 929                 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
 930                 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
 931                 err = 1;
 932         }
 933         if (err) {
 934                 host->sd_error = true;
 935                 dev_dbg(&host->pd->dev, "int err state = %08x\n", state);
 936         }
 937         if (state & ~(INT_CMD12RBE | INT_CMD12CRE))
 938                 complete(&host->intr_wait);
 939         else
 940                 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state);
 941
 942         return IRQ_HANDLED;
 943 }
 944
 945 static int __devinit sh_mmcif_probe(struct platform_device *pdev)
 946 {
 947         int ret = 0, irq[2];
 948         struct mmc_host *mmc;
 949         struct sh_mmcif_host *host;
 950         struct sh_mmcif_plat_data *pd;
 951         struct resource *res;
 952         void __iomem *reg;
 953         char clk_name[8];
 954
 955         irq[0] = platform_get_irq(pdev, 0);
 956         irq[1] = platform_get_irq(pdev, 1);
 957         if (irq[0] < 0 || irq[1] < 0) {
 958                 dev_err(&pdev->dev, "Get irq error\n");
 959                 return -ENXIO;
 960         }
 961         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 962         if (!res) {
 963                 dev_err(&pdev->dev, "platform_get_resource error.\n");
 964                 return -ENXIO;
 965         }
 966         reg = ioremap(res->start, resource_size(res));
 967         if (!reg) {
 968                 dev_err(&pdev->dev, "ioremap error.\n");
 969                 return -ENOMEM;
 970         }
 971         pd = pdev->dev.platform_data;
 972         if (!pd) {
 973                 dev_err(&pdev->dev, "sh_mmcif plat data error.\n");
 974                 ret = -ENXIO;
 975                 goto clean_up;
 976         }
 977         mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev);
 978         if (!mmc) {
 979                 ret = -ENOMEM;
 980                 goto clean_up;
 981         }
 982         host            = mmc_priv(mmc);
 983         host->mmc       = mmc;
 984         host->addr      = reg;
 985         host->timeout   = 1000;
 986
 987         snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id);
 988         host->hclk = clk_get(&pdev->dev, clk_name);
 989         if (IS_ERR(host->hclk)) {
 990                 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
 991                 ret = PTR_ERR(host->hclk);
 992                 goto clean_up1;
 993         }
 994         clk_enable(host->hclk);
 995         host->clk = clk_get_rate(host->hclk);
 996         host->pd = pdev;
 997
 998         init_completion(&host->intr_wait);
 999
1000         mmc->ops = &sh_mmcif_ops;
1001         mmc->f_max = host->clk;
1002         /* close to 400KHz */
1003         if (mmc->f_max < 51200000)
1004                 mmc->f_min = mmc->f_max / 128;
1005         else if (mmc->f_max < 102400000)
1006                 mmc->f_min = mmc->f_max / 256;
1007         else
1008                 mmc->f_min = mmc->f_max / 512;
1009         if (pd->ocr)
1010                 mmc->ocr_avail = pd->ocr;
1011         mmc->caps = MMC_CAP_MMC_HIGHSPEED;
1012         if (pd->caps)
1013                 mmc->caps |= pd->caps;
1014         mmc->max_segs = 32;
1015         mmc->max_blk_size = 512;
1016         mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs;
1017         mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1018         mmc->max_seg_size = mmc->max_req_size;
1019
1020         sh_mmcif_sync_reset(host);
1021         platform_set_drvdata(pdev, host);
1022
1023         /* See if we also get DMA */
1024         sh_mmcif_request_dma(host, pd);
1025
1026         mmc_add_host(mmc);
1027
1028         ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
1029         if (ret) {
1030                 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
1031                 goto clean_up2;
1032         }
1033         ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
1034         if (ret) {
1035                 free_irq(irq[0], host);
1036                 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
1037                 goto clean_up2;
1038         }
1039
1040         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1041         sh_mmcif_detect(host->mmc);
1042
1043         dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
1044         dev_dbg(&pdev->dev, "chip ver H'%04x\n",
1045                 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
1046         return ret;
1047
1048 clean_up2:
1049         clk_disable(host->hclk);
1050 clean_up1:
1051         mmc_free_host(mmc);
1052 clean_up:
1053         if (reg)
1054                 iounmap(reg);
1055         return ret;
1056 }
1057
1058 static int __devexit sh_mmcif_remove(struct platform_device *pdev)
1059 {
1060         struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1061         int irq[2];
1062
1063         mmc_remove_host(host->mmc);
1064         sh_mmcif_release_dma(host);
1065
1066         if (host->addr)
1067                 iounmap(host->addr);
1068
1069         sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
1070
1071         irq[0] = platform_get_irq(pdev, 0);
1072         irq[1] = platform_get_irq(pdev, 1);
1073
1074         free_irq(irq[0], host);
1075         free_irq(irq[1], host);
1076
1077         platform_set_drvdata(pdev, NULL);
1078
1079         clk_disable(host->hclk);
1080         mmc_free_host(host->mmc);
1081
1082         return 0;
1083 }
1084
1085 static struct platform_driver sh_mmcif_driver = {
1086         .probe          = sh_mmcif_probe,
1087         .remove         = sh_mmcif_remove,
1088         .driver         = {
1089                 .name   = DRIVER_NAME,
1090         },
1091 };
1092
1093 static int __init sh_mmcif_init(void)
1094 {
1095         return platform_driver_register(&sh_mmcif_driver);
1096 }
1097
1098 static void __exit sh_mmcif_exit(void)
1099 {
1100         platform_driver_unregister(&sh_mmcif_driver);
1101 }
1102
1103 module_init(sh_mmcif_init);
1104 module_exit(sh_mmcif_exit);
1105
1106
1107 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1108 MODULE_LICENSE("GPL");
1109 MODULE_ALIAS("platform:" DRIVER_NAME);
1110 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");