2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/workqueue.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/core.h>
32 #include <linux/mmc/mmc.h>
34 #include <linux/semaphore.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/pm_runtime.h>
39 #include <mach/hardware.h>
40 #include <plat/board.h>
44 /* OMAP HSMMC Host Controller Registers */
45 #define OMAP_HSMMC_SYSCONFIG 0x0010
46 #define OMAP_HSMMC_SYSSTATUS 0x0014
47 #define OMAP_HSMMC_CON 0x002C
48 #define OMAP_HSMMC_BLK 0x0104
49 #define OMAP_HSMMC_ARG 0x0108
50 #define OMAP_HSMMC_CMD 0x010C
51 #define OMAP_HSMMC_RSP10 0x0110
52 #define OMAP_HSMMC_RSP32 0x0114
53 #define OMAP_HSMMC_RSP54 0x0118
54 #define OMAP_HSMMC_RSP76 0x011C
55 #define OMAP_HSMMC_DATA 0x0120
56 #define OMAP_HSMMC_HCTL 0x0128
57 #define OMAP_HSMMC_SYSCTL 0x012C
58 #define OMAP_HSMMC_STAT 0x0130
59 #define OMAP_HSMMC_IE 0x0134
60 #define OMAP_HSMMC_ISE 0x0138
61 #define OMAP_HSMMC_CAPA 0x0140
63 #define VS18 (1 << 26)
64 #define VS30 (1 << 25)
65 #define SDVS18 (0x5 << 9)
66 #define SDVS30 (0x6 << 9)
67 #define SDVS33 (0x7 << 9)
68 #define SDVS_MASK 0x00000E00
69 #define SDVSCLR 0xFFFFF1FF
70 #define SDVSDET 0x00000400
77 #define CLKD_MASK 0x0000FFC0
79 #define DTO_MASK 0x000F0000
81 #define INT_EN_MASK 0x307F0033
82 #define BWR_ENABLE (1 << 4)
83 #define BRR_ENABLE (1 << 5)
84 #define DTO_ENABLE (1 << 20)
85 #define INIT_STREAM (1 << 1)
86 #define DP_SELECT (1 << 21)
91 #define FOUR_BIT (1 << 1)
97 #define CMD_TIMEOUT (1 << 16)
98 #define DATA_TIMEOUT (1 << 20)
99 #define CMD_CRC (1 << 17)
100 #define DATA_CRC (1 << 21)
101 #define CARD_ERR (1 << 28)
102 #define STAT_CLEAR 0xFFFFFFFF
103 #define INIT_STREAM_CMD 0x00000000
104 #define DUAL_VOLT_OCR_BIT 7
105 #define SRC (1 << 25)
106 #define SRD (1 << 26)
107 #define SOFTRESET (1 << 1)
108 #define RESETDONE (1 << 0)
111 * FIXME: Most likely all the data using these _DEVID defines should come
112 * from the platform_data, or implemented in controller and slot specific
115 #define OMAP_MMC1_DEVID 0
116 #define OMAP_MMC2_DEVID 1
117 #define OMAP_MMC3_DEVID 2
118 #define OMAP_MMC4_DEVID 3
119 #define OMAP_MMC5_DEVID 4
121 #define MMC_AUTOSUSPEND_DELAY 100
122 #define MMC_TIMEOUT_MS 20
123 #define OMAP_MMC_MASTER_CLOCK 96000000
124 #define OMAP_MMC_MIN_CLOCK 400000
125 #define OMAP_MMC_MAX_CLOCK 52000000
126 #define DRIVER_NAME "omap_hsmmc"
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
133 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
136 * MMC Host controller read/write API's
138 #define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
141 #define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
144 struct omap_hsmmc_next {
145 unsigned int dma_len;
149 struct omap_hsmmc_host {
151 struct mmc_host *mmc;
152 struct mmc_request *mrq;
153 struct mmc_command *cmd;
154 struct mmc_data *data;
158 * vcc == configured supply
159 * vcc_aux == optional
160 * - MMC1, supply for DAT4..DAT7
161 * - MMC2/MMC2, external level shifter voltage supply, for
162 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
164 struct regulator *vcc;
165 struct regulator *vcc_aux;
166 struct work_struct mmc_carddetect_work;
168 resource_size_t mapbase;
169 spinlock_t irq_lock; /* Prevent races with irq handler */
171 unsigned int dma_len;
172 unsigned int dma_sg_idx;
173 unsigned char bus_mode;
174 unsigned char power_mode;
180 int dma_line_tx, dma_line_rx;
191 struct omap_hsmmc_next next_data;
193 struct omap_mmc_platform_data *pdata;
196 static int omap_hsmmc_card_detect(struct device *dev, int slot)
198 struct omap_mmc_platform_data *mmc = dev->platform_data;
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
204 static int omap_hsmmc_get_wp(struct device *dev, int slot)
206 struct omap_mmc_platform_data *mmc = dev->platform_data;
208 /* NOTE: assumes write protect signal is active-high */
209 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
212 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
216 /* NOTE: assumes card detect signal is active-low */
217 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
222 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
224 struct omap_mmc_platform_data *mmc = dev->platform_data;
226 disable_irq(mmc->slots[0].card_detect_irq);
230 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
232 struct omap_mmc_platform_data *mmc = dev->platform_data;
234 enable_irq(mmc->slots[0].card_detect_irq);
240 #define omap_hsmmc_suspend_cdirq NULL
241 #define omap_hsmmc_resume_cdirq NULL
245 #ifdef CONFIG_REGULATOR
247 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
250 struct omap_hsmmc_host *host =
251 platform_get_drvdata(to_platform_device(dev));
254 if (mmc_slot(host).before_set_reg)
255 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
258 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
260 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
262 if (mmc_slot(host).after_set_reg)
263 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
268 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
271 struct omap_hsmmc_host *host =
272 platform_get_drvdata(to_platform_device(dev));
276 * If we don't see a Vcc regulator, assume it's a fixed
277 * voltage always-on regulator.
282 if (mmc_slot(host).before_set_reg)
283 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
286 * Assume Vcc regulator is used only to power the card ... OMAP
287 * VDDS is used to power the pins, optionally with a transceiver to
288 * support cards using voltages other than VDDS (1.8V nominal). When a
289 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
291 * In some cases this regulator won't support enable/disable;
292 * e.g. it's a fixed rail for a WLAN chip.
294 * In other cases vcc_aux switches interface power. Example, for
295 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
296 * chips/cards need an interface voltage rail too.
299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
300 /* Enable interface voltage rail, if needed */
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
304 ret = mmc_regulator_set_ocr(host->mmc,
308 /* Shut down the rail */
310 ret = regulator_disable(host->vcc_aux);
312 /* Then proceed to shut down the local regulator */
313 ret = mmc_regulator_set_ocr(host->mmc,
318 if (mmc_slot(host).after_set_reg)
319 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
324 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
330 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
331 int vdd, int cardsleep)
333 struct omap_hsmmc_host *host =
334 platform_get_drvdata(to_platform_device(dev));
335 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
337 return regulator_set_mode(host->vcc, mode);
340 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
341 int vdd, int cardsleep)
343 struct omap_hsmmc_host *host =
344 platform_get_drvdata(to_platform_device(dev));
348 * If we don't see a Vcc regulator, assume it's a fixed
349 * voltage always-on regulator.
354 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
357 return regulator_set_mode(host->vcc, mode);
360 /* VCC can be turned off if card is asleep */
362 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
364 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
366 err = regulator_set_mode(host->vcc, mode);
370 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
371 return regulator_set_mode(host->vcc_aux, mode);
374 return regulator_disable(host->vcc_aux);
376 return regulator_enable(host->vcc_aux);
379 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
380 int vdd, int cardsleep)
385 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
387 struct regulator *reg;
392 case OMAP_MMC1_DEVID:
393 /* On-chip level shifting via PBIAS0/PBIAS1 */
394 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
395 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
397 case OMAP_MMC2_DEVID:
398 case OMAP_MMC3_DEVID:
399 case OMAP_MMC5_DEVID:
400 /* Off-chip level shifting, or none */
401 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
402 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
404 case OMAP_MMC4_DEVID:
405 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
406 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
408 pr_err("MMC%d configuration not supported!\n", host->id);
412 reg = regulator_get(host->dev, "vmmc");
414 dev_dbg(host->dev, "vmmc regulator missing\n");
416 * HACK: until fixed.c regulator is usable,
417 * we don't require a main regulator
420 if (host->id == OMAP_MMC1_DEVID) {
426 ocr_value = mmc_regulator_get_ocrmask(reg);
427 if (!mmc_slot(host).ocr_mask) {
428 mmc_slot(host).ocr_mask = ocr_value;
430 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
431 pr_err("MMC%d ocrmask %x is not supported\n",
432 host->id, mmc_slot(host).ocr_mask);
433 mmc_slot(host).ocr_mask = 0;
438 /* Allow an aux regulator */
439 reg = regulator_get(host->dev, "vmmc_aux");
440 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
442 /* For eMMC do not power off when not in sleep state */
443 if (mmc_slot(host).no_regulator_off_init)
446 * UGLY HACK: workaround regulator framework bugs.
447 * When the bootloader leaves a supply active, it's
448 * initialized with zero usecount ... and we can't
449 * disable it without first enabling it. Until the
450 * framework is fixed, we need a workaround like this
451 * (which is safe for MMC, but not in general).
453 if (regulator_is_enabled(host->vcc) > 0) {
454 regulator_enable(host->vcc);
455 regulator_disable(host->vcc);
458 if (regulator_is_enabled(reg) > 0) {
459 regulator_enable(reg);
460 regulator_disable(reg);
468 mmc_slot(host).set_power = NULL;
469 mmc_slot(host).set_sleep = NULL;
473 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
475 regulator_put(host->vcc);
476 regulator_put(host->vcc_aux);
477 mmc_slot(host).set_power = NULL;
478 mmc_slot(host).set_sleep = NULL;
481 static inline int omap_hsmmc_have_reg(void)
488 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
493 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
497 static inline int omap_hsmmc_have_reg(void)
504 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
508 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
509 if (pdata->slots[0].cover)
510 pdata->slots[0].get_cover_state =
511 omap_hsmmc_get_cover_state;
513 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
514 pdata->slots[0].card_detect_irq =
515 gpio_to_irq(pdata->slots[0].switch_pin);
516 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
519 ret = gpio_direction_input(pdata->slots[0].switch_pin);
523 pdata->slots[0].switch_pin = -EINVAL;
525 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
526 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
527 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
530 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
534 pdata->slots[0].gpio_wp = -EINVAL;
539 gpio_free(pdata->slots[0].gpio_wp);
541 if (gpio_is_valid(pdata->slots[0].switch_pin))
543 gpio_free(pdata->slots[0].switch_pin);
547 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
549 if (gpio_is_valid(pdata->slots[0].gpio_wp))
550 gpio_free(pdata->slots[0].gpio_wp);
551 if (gpio_is_valid(pdata->slots[0].switch_pin))
552 gpio_free(pdata->slots[0].switch_pin);
556 * Start clock to the card
558 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
560 OMAP_HSMMC_WRITE(host->base, SYSCTL,
561 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
565 * Stop clock to the card
567 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
569 OMAP_HSMMC_WRITE(host->base, SYSCTL,
570 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
571 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
572 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
575 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
576 struct mmc_command *cmd)
578 unsigned int irq_mask;
581 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
583 irq_mask = INT_EN_MASK;
585 /* Disable timeout for erases */
586 if (cmd->opcode == MMC_ERASE)
587 irq_mask &= ~DTO_ENABLE;
589 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
590 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
591 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
594 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
596 OMAP_HSMMC_WRITE(host->base, ISE, 0);
597 OMAP_HSMMC_WRITE(host->base, IE, 0);
598 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
601 /* Calculate divisor for the given clock frequency */
602 static u16 calc_divisor(struct mmc_ios *ios)
607 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
615 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
617 struct mmc_ios *ios = &host->mmc->ios;
618 unsigned long regval;
619 unsigned long timeout;
621 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
623 omap_hsmmc_stop_clock(host);
625 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
626 regval = regval & ~(CLKD_MASK | DTO_MASK);
627 regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
628 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
629 OMAP_HSMMC_WRITE(host->base, SYSCTL,
630 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
632 /* Wait till the ICS bit is set */
633 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
634 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
635 && time_before(jiffies, timeout))
638 omap_hsmmc_start_clock(host);
641 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
643 struct mmc_ios *ios = &host->mmc->ios;
646 con = OMAP_HSMMC_READ(host->base, CON);
647 switch (ios->bus_width) {
648 case MMC_BUS_WIDTH_8:
649 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
651 case MMC_BUS_WIDTH_4:
652 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
653 OMAP_HSMMC_WRITE(host->base, HCTL,
654 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
656 case MMC_BUS_WIDTH_1:
657 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
658 OMAP_HSMMC_WRITE(host->base, HCTL,
659 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
664 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
666 struct mmc_ios *ios = &host->mmc->ios;
669 con = OMAP_HSMMC_READ(host->base, CON);
670 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
671 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
673 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
679 * Restore the MMC host context, if it was lost as result of a
680 * power state change.
682 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
684 struct mmc_ios *ios = &host->mmc->ios;
685 struct omap_mmc_platform_data *pdata = host->pdata;
686 int context_loss = 0;
688 unsigned long timeout;
690 if (pdata->get_context_loss_count) {
691 context_loss = pdata->get_context_loss_count(host->dev);
692 if (context_loss < 0)
696 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
697 context_loss == host->context_loss ? "not " : "");
698 if (host->context_loss == context_loss)
701 /* Wait for hardware reset */
702 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
703 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
704 && time_before(jiffies, timeout))
707 /* Do software reset */
708 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
709 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
710 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
711 && time_before(jiffies, timeout))
714 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
715 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
717 if (host->id == OMAP_MMC1_DEVID) {
718 if (host->power_mode != MMC_POWER_OFF &&
719 (1 << ios->vdd) <= MMC_VDD_23_24)
729 OMAP_HSMMC_WRITE(host->base, HCTL,
730 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
732 OMAP_HSMMC_WRITE(host->base, CAPA,
733 OMAP_HSMMC_READ(host->base, CAPA) | capa);
735 OMAP_HSMMC_WRITE(host->base, HCTL,
736 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
738 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
739 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
740 && time_before(jiffies, timeout))
743 omap_hsmmc_disable_irq(host);
745 /* Do not initialize card-specific things if the power is off */
746 if (host->power_mode == MMC_POWER_OFF)
749 omap_hsmmc_set_bus_width(host);
751 omap_hsmmc_set_clock(host);
753 omap_hsmmc_set_bus_mode(host);
756 host->context_loss = context_loss;
758 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
763 * Save the MMC host context (store the number of power state changes so far).
765 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
767 struct omap_mmc_platform_data *pdata = host->pdata;
770 if (pdata->get_context_loss_count) {
771 context_loss = pdata->get_context_loss_count(host->dev);
772 if (context_loss < 0)
774 host->context_loss = context_loss;
780 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
785 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
792 * Send init stream sequence to card
793 * before sending IDLE command
795 static void send_init_stream(struct omap_hsmmc_host *host)
798 unsigned long timeout;
800 if (host->protect_card)
803 disable_irq(host->irq);
805 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
806 OMAP_HSMMC_WRITE(host->base, CON,
807 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
808 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
810 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
811 while ((reg != CC) && time_before(jiffies, timeout))
812 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
814 OMAP_HSMMC_WRITE(host->base, CON,
815 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
817 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
818 OMAP_HSMMC_READ(host->base, STAT);
820 enable_irq(host->irq);
824 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
828 if (mmc_slot(host).get_cover_state)
829 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
834 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
837 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
838 struct omap_hsmmc_host *host = mmc_priv(mmc);
840 return sprintf(buf, "%s\n",
841 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
844 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
847 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
850 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
851 struct omap_hsmmc_host *host = mmc_priv(mmc);
853 return sprintf(buf, "%s\n", mmc_slot(host).name);
856 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
859 * Configure the response type and send the cmd.
862 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
863 struct mmc_data *data)
865 int cmdreg = 0, resptype = 0, cmdtype = 0;
867 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
868 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
871 omap_hsmmc_enable_irq(host, cmd);
873 host->response_busy = 0;
874 if (cmd->flags & MMC_RSP_PRESENT) {
875 if (cmd->flags & MMC_RSP_136)
877 else if (cmd->flags & MMC_RSP_BUSY) {
879 host->response_busy = 1;
885 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
886 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
887 * a val of 0x3, rest 0x0.
889 if (cmd == host->mrq->stop)
892 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
895 cmdreg |= DP_SELECT | MSBS | BCE;
896 if (data->flags & MMC_DATA_READ)
905 host->req_in_progress = 1;
907 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
908 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
912 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
914 if (data->flags & MMC_DATA_WRITE)
915 return DMA_TO_DEVICE;
917 return DMA_FROM_DEVICE;
920 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
924 spin_lock(&host->irq_lock);
925 host->req_in_progress = 0;
926 dma_ch = host->dma_ch;
927 spin_unlock(&host->irq_lock);
929 omap_hsmmc_disable_irq(host);
930 /* Do not complete the request if DMA is still in progress */
931 if (mrq->data && host->use_dma && dma_ch != -1)
934 mmc_request_done(host->mmc, mrq);
938 * Notify the transfer complete to MMC core
941 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
944 struct mmc_request *mrq = host->mrq;
946 /* TC before CC from CMD6 - don't know why, but it happens */
947 if (host->cmd && host->cmd->opcode == 6 &&
948 host->response_busy) {
949 host->response_busy = 0;
953 omap_hsmmc_request_done(host, mrq);
960 data->bytes_xfered += data->blocks * (data->blksz);
962 data->bytes_xfered = 0;
965 omap_hsmmc_request_done(host, data->mrq);
968 omap_hsmmc_start_command(host, data->stop, NULL);
972 * Notify the core about command completion
975 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
979 if (cmd->flags & MMC_RSP_PRESENT) {
980 if (cmd->flags & MMC_RSP_136) {
981 /* response type 2 */
982 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
983 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
984 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
985 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
987 /* response types 1, 1b, 3, 4, 5, 6 */
988 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
991 if ((host->data == NULL && !host->response_busy) || cmd->error)
992 omap_hsmmc_request_done(host, cmd->mrq);
996 * DMA clean up for command errors
998 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1002 host->data->error = errno;
1004 spin_lock(&host->irq_lock);
1005 dma_ch = host->dma_ch;
1007 spin_unlock(&host->irq_lock);
1009 if (host->use_dma && dma_ch != -1) {
1010 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1012 omap_hsmmc_get_dma_dir(host, host->data));
1013 omap_free_dma(dma_ch);
1019 * Readable error output
1021 #ifdef CONFIG_MMC_DEBUG
1022 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1024 /* --- means reserved bit without definition at documentation */
1025 static const char *omap_hsmmc_status_bits[] = {
1026 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1027 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1028 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1029 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1035 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1038 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1039 if (status & (1 << i)) {
1040 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1044 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1047 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1051 #endif /* CONFIG_MMC_DEBUG */
1054 * MMC controller internal state machines reset
1056 * Used to reset command or data internal state machines, using respectively
1057 * SRC or SRD bit of SYSCTL register
1058 * Can be called from interrupt context
1060 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1063 unsigned long i = 0;
1064 unsigned long limit = (loops_per_jiffy *
1065 msecs_to_jiffies(MMC_TIMEOUT_MS));
1067 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1068 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1071 * OMAP4 ES2 and greater has an updated reset logic.
1072 * Monitor a 0->1 transition first
1074 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1075 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1081 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1085 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1086 dev_err(mmc_dev(host->mmc),
1087 "Timeout waiting on controller reset in %s\n",
1091 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1093 struct mmc_data *data;
1094 int end_cmd = 0, end_trans = 0;
1096 if (!host->req_in_progress) {
1098 OMAP_HSMMC_WRITE(host->base, STAT, status);
1099 /* Flush posted write */
1100 status = OMAP_HSMMC_READ(host->base, STAT);
1101 } while (status & INT_EN_MASK);
1106 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1109 omap_hsmmc_dbg_report_irq(host, status);
1110 if ((status & CMD_TIMEOUT) ||
1111 (status & CMD_CRC)) {
1113 if (status & CMD_TIMEOUT) {
1114 omap_hsmmc_reset_controller_fsm(host,
1116 host->cmd->error = -ETIMEDOUT;
1118 host->cmd->error = -EILSEQ;
1122 if (host->data || host->response_busy) {
1124 omap_hsmmc_dma_cleanup(host,
1126 host->response_busy = 0;
1127 omap_hsmmc_reset_controller_fsm(host, SRD);
1130 if ((status & DATA_TIMEOUT) ||
1131 (status & DATA_CRC)) {
1132 if (host->data || host->response_busy) {
1133 int err = (status & DATA_TIMEOUT) ?
1134 -ETIMEDOUT : -EILSEQ;
1137 omap_hsmmc_dma_cleanup(host, err);
1139 host->mrq->cmd->error = err;
1140 host->response_busy = 0;
1141 omap_hsmmc_reset_controller_fsm(host, SRD);
1145 if (status & CARD_ERR) {
1146 dev_dbg(mmc_dev(host->mmc),
1147 "Ignoring card err CMD%d\n", host->cmd->opcode);
1155 OMAP_HSMMC_WRITE(host->base, STAT, status);
1157 if (end_cmd || ((status & CC) && host->cmd))
1158 omap_hsmmc_cmd_done(host, host->cmd);
1159 if ((end_trans || (status & TC)) && host->mrq)
1160 omap_hsmmc_xfer_done(host, data);
1164 * MMC controller IRQ handler
1166 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1168 struct omap_hsmmc_host *host = dev_id;
1171 status = OMAP_HSMMC_READ(host->base, STAT);
1173 omap_hsmmc_do_irq(host, status);
1174 /* Flush posted write */
1175 status = OMAP_HSMMC_READ(host->base, STAT);
1176 } while (status & INT_EN_MASK);
1181 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1185 OMAP_HSMMC_WRITE(host->base, HCTL,
1186 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1187 for (i = 0; i < loops_per_jiffy; i++) {
1188 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1195 * Switch MMC interface voltage ... only relevant for MMC1.
1197 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1198 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1199 * Some chips, like eMMC ones, use internal transceivers.
1201 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1206 /* Disable the clocks */
1207 pm_runtime_put_sync(host->dev);
1208 if (host->got_dbclk)
1209 clk_disable(host->dbclk);
1211 /* Turn the power off */
1212 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1214 /* Turn the power ON with given VDD 1.8 or 3.0v */
1216 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1218 pm_runtime_get_sync(host->dev);
1219 if (host->got_dbclk)
1220 clk_enable(host->dbclk);
1225 OMAP_HSMMC_WRITE(host->base, HCTL,
1226 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1227 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1230 * If a MMC dual voltage card is detected, the set_ios fn calls
1231 * this fn with VDD bit set for 1.8V. Upon card removal from the
1232 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1234 * Cope with a bit of slop in the range ... per data sheets:
1235 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1236 * but recommended values are 1.71V to 1.89V
1237 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1238 * but recommended values are 2.7V to 3.3V
1240 * Board setup code shouldn't permit anything very out-of-range.
1241 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1242 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1244 if ((1 << vdd) <= MMC_VDD_23_24)
1249 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1250 set_sd_bus_power(host);
1254 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1258 /* Protect the card while the cover is open */
1259 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1261 if (!mmc_slot(host).get_cover_state)
1264 host->reqs_blocked = 0;
1265 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1266 if (host->protect_card) {
1267 printk(KERN_INFO "%s: cover is closed, "
1268 "card is now accessible\n",
1269 mmc_hostname(host->mmc));
1270 host->protect_card = 0;
1273 if (!host->protect_card) {
1274 printk(KERN_INFO "%s: cover is open, "
1275 "card is now inaccessible\n",
1276 mmc_hostname(host->mmc));
1277 host->protect_card = 1;
1283 * Work Item to notify the core about card insertion/removal
1285 static void omap_hsmmc_detect(struct work_struct *work)
1287 struct omap_hsmmc_host *host =
1288 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1289 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1292 if (host->suspended)
1295 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1297 if (slot->card_detect)
1298 carddetect = slot->card_detect(host->dev, host->slot_id);
1300 omap_hsmmc_protect_card(host);
1301 carddetect = -ENOSYS;
1305 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1307 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1311 * ISR for handling card insertion and removal
1313 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1315 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1317 if (host->suspended)
1319 schedule_work(&host->mmc_carddetect_work);
1324 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1325 struct mmc_data *data)
1329 if (data->flags & MMC_DATA_WRITE)
1330 sync_dev = host->dma_line_tx;
1332 sync_dev = host->dma_line_rx;
1336 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1337 struct mmc_data *data,
1338 struct scatterlist *sgl)
1340 int blksz, nblk, dma_ch;
1342 dma_ch = host->dma_ch;
1343 if (data->flags & MMC_DATA_WRITE) {
1344 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1345 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1346 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1347 sg_dma_address(sgl), 0, 0);
1349 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1350 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1351 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1352 sg_dma_address(sgl), 0, 0);
1355 blksz = host->data->blksz;
1356 nblk = sg_dma_len(sgl) / blksz;
1358 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1359 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1360 omap_hsmmc_get_dma_sync_dev(host, data),
1361 !(data->flags & MMC_DATA_WRITE));
1363 omap_start_dma(dma_ch);
1367 * DMA call back function
1369 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1371 struct omap_hsmmc_host *host = cb_data;
1372 struct mmc_data *data;
1373 int dma_ch, req_in_progress;
1375 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1376 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1381 spin_lock(&host->irq_lock);
1382 if (host->dma_ch < 0) {
1383 spin_unlock(&host->irq_lock);
1387 data = host->mrq->data;
1389 if (host->dma_sg_idx < host->dma_len) {
1390 /* Fire up the next transfer. */
1391 omap_hsmmc_config_dma_params(host, data,
1392 data->sg + host->dma_sg_idx);
1393 spin_unlock(&host->irq_lock);
1397 if (!data->host_cookie)
1398 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1399 omap_hsmmc_get_dma_dir(host, data));
1401 req_in_progress = host->req_in_progress;
1402 dma_ch = host->dma_ch;
1404 spin_unlock(&host->irq_lock);
1406 omap_free_dma(dma_ch);
1408 /* If DMA has finished after TC, complete the request */
1409 if (!req_in_progress) {
1410 struct mmc_request *mrq = host->mrq;
1413 mmc_request_done(host->mmc, mrq);
1417 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1418 struct mmc_data *data,
1419 struct omap_hsmmc_next *next)
1423 if (!next && data->host_cookie &&
1424 data->host_cookie != host->next_data.cookie) {
1425 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1426 " host->next_data.cookie %d\n",
1427 __func__, data->host_cookie, host->next_data.cookie);
1428 data->host_cookie = 0;
1431 /* Check if next job is already prepared */
1433 (!next && data->host_cookie != host->next_data.cookie)) {
1434 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1436 omap_hsmmc_get_dma_dir(host, data));
1439 dma_len = host->next_data.dma_len;
1440 host->next_data.dma_len = 0;
1448 next->dma_len = dma_len;
1449 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1451 host->dma_len = dma_len;
1457 * Routine to configure and start DMA for the MMC card
1459 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1460 struct mmc_request *req)
1462 int dma_ch = 0, ret = 0, i;
1463 struct mmc_data *data = req->data;
1465 /* Sanity check: all the SG entries must be aligned by block size. */
1466 for (i = 0; i < data->sg_len; i++) {
1467 struct scatterlist *sgl;
1470 if (sgl->length % data->blksz)
1473 if ((data->blksz % 4) != 0)
1474 /* REVISIT: The MMC buffer increments only when MSB is written.
1475 * Return error for blksz which is non multiple of four.
1479 BUG_ON(host->dma_ch != -1);
1481 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1482 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1484 dev_err(mmc_dev(host->mmc),
1485 "%s: omap_request_dma() failed with %d\n",
1486 mmc_hostname(host->mmc), ret);
1489 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1493 host->dma_ch = dma_ch;
1494 host->dma_sg_idx = 0;
1496 omap_hsmmc_config_dma_params(host, data, data->sg);
1501 static void set_data_timeout(struct omap_hsmmc_host *host,
1502 unsigned int timeout_ns,
1503 unsigned int timeout_clks)
1505 unsigned int timeout, cycle_ns;
1506 uint32_t reg, clkd, dto = 0;
1508 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1509 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1513 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1514 timeout = timeout_ns / cycle_ns;
1515 timeout += timeout_clks;
1517 while ((timeout & 0x80000000) == 0) {
1534 reg |= dto << DTO_SHIFT;
1535 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1539 * Configure block length for MMC/SD cards and initiate the transfer.
1542 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1545 host->data = req->data;
1547 if (req->data == NULL) {
1548 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1550 * Set an arbitrary 100ms data timeout for commands with
1553 if (req->cmd->flags & MMC_RSP_BUSY)
1554 set_data_timeout(host, 100000000U, 0);
1558 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1559 | (req->data->blocks << 16));
1560 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1562 if (host->use_dma) {
1563 ret = omap_hsmmc_start_dma_transfer(host, req);
1565 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1572 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1575 struct omap_hsmmc_host *host = mmc_priv(mmc);
1576 struct mmc_data *data = mrq->data;
1578 if (host->use_dma) {
1579 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1580 omap_hsmmc_get_dma_dir(host, data));
1581 data->host_cookie = 0;
1585 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1588 struct omap_hsmmc_host *host = mmc_priv(mmc);
1590 if (mrq->data->host_cookie) {
1591 mrq->data->host_cookie = 0;
1596 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1598 mrq->data->host_cookie = 0;
1602 * Request function. for read/write operation
1604 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1606 struct omap_hsmmc_host *host = mmc_priv(mmc);
1609 BUG_ON(host->req_in_progress);
1610 BUG_ON(host->dma_ch != -1);
1611 if (host->protect_card) {
1612 if (host->reqs_blocked < 3) {
1614 * Ensure the controller is left in a consistent
1615 * state by resetting the command and data state
1618 omap_hsmmc_reset_controller_fsm(host, SRD);
1619 omap_hsmmc_reset_controller_fsm(host, SRC);
1620 host->reqs_blocked += 1;
1622 req->cmd->error = -EBADF;
1624 req->data->error = -EBADF;
1625 req->cmd->retries = 0;
1626 mmc_request_done(mmc, req);
1628 } else if (host->reqs_blocked)
1629 host->reqs_blocked = 0;
1630 WARN_ON(host->mrq != NULL);
1632 err = omap_hsmmc_prepare_data(host, req);
1634 req->cmd->error = err;
1636 req->data->error = err;
1638 mmc_request_done(mmc, req);
1642 omap_hsmmc_start_command(host, req->cmd, req->data);
1645 /* Routine to configure clock values. Exposed API to core */
1646 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1648 struct omap_hsmmc_host *host = mmc_priv(mmc);
1649 int do_send_init_stream = 0;
1651 pm_runtime_get_sync(host->dev);
1653 if (ios->power_mode != host->power_mode) {
1654 switch (ios->power_mode) {
1656 mmc_slot(host).set_power(host->dev, host->slot_id,
1661 mmc_slot(host).set_power(host->dev, host->slot_id,
1663 host->vdd = ios->vdd;
1666 do_send_init_stream = 1;
1669 host->power_mode = ios->power_mode;
1672 /* FIXME: set registers based only on changes to ios */
1674 omap_hsmmc_set_bus_width(host);
1676 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1677 /* Only MMC1 can interface at 3V without some flavor
1678 * of external transceiver; but they all handle 1.8V.
1680 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1681 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1683 * The mmc_select_voltage fn of the core does
1684 * not seem to set the power_mode to
1685 * MMC_POWER_UP upon recalculating the voltage.
1688 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1689 dev_dbg(mmc_dev(host->mmc),
1690 "Switch operation failed\n");
1694 omap_hsmmc_set_clock(host);
1696 if (do_send_init_stream)
1697 send_init_stream(host);
1699 omap_hsmmc_set_bus_mode(host);
1701 pm_runtime_put_autosuspend(host->dev);
1704 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1706 struct omap_hsmmc_host *host = mmc_priv(mmc);
1708 if (!mmc_slot(host).card_detect)
1710 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1713 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1715 struct omap_hsmmc_host *host = mmc_priv(mmc);
1717 if (!mmc_slot(host).get_ro)
1719 return mmc_slot(host).get_ro(host->dev, 0);
1722 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1724 struct omap_hsmmc_host *host = mmc_priv(mmc);
1726 if (mmc_slot(host).init_card)
1727 mmc_slot(host).init_card(card);
1730 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1732 u32 hctl, capa, value;
1734 /* Only MMC1 supports 3.0V */
1735 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1743 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1744 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1746 value = OMAP_HSMMC_READ(host->base, CAPA);
1747 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1749 /* Set the controller to AUTO IDLE mode */
1750 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1751 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1753 /* Set SD bus power bit */
1754 set_sd_bus_power(host);
1757 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1759 struct omap_hsmmc_host *host = mmc_priv(mmc);
1761 pm_runtime_get_sync(host->dev);
1766 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1768 struct omap_hsmmc_host *host = mmc_priv(mmc);
1770 pm_runtime_mark_last_busy(host->dev);
1771 pm_runtime_put_autosuspend(host->dev);
1776 static const struct mmc_host_ops omap_hsmmc_ops = {
1777 .enable = omap_hsmmc_enable_fclk,
1778 .disable = omap_hsmmc_disable_fclk,
1779 .post_req = omap_hsmmc_post_req,
1780 .pre_req = omap_hsmmc_pre_req,
1781 .request = omap_hsmmc_request,
1782 .set_ios = omap_hsmmc_set_ios,
1783 .get_cd = omap_hsmmc_get_cd,
1784 .get_ro = omap_hsmmc_get_ro,
1785 .init_card = omap_hsmmc_init_card,
1786 /* NYET -- enable_sdio_irq */
1789 #ifdef CONFIG_DEBUG_FS
1791 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1793 struct mmc_host *mmc = s->private;
1794 struct omap_hsmmc_host *host = mmc_priv(mmc);
1795 int context_loss = 0;
1797 if (host->pdata->get_context_loss_count)
1798 context_loss = host->pdata->get_context_loss_count(host->dev);
1800 seq_printf(s, "mmc%d:\n"
1803 " nesting_cnt:\t%d\n"
1804 " ctx_loss:\t%d:%d\n"
1806 mmc->index, mmc->enabled ? 1 : 0,
1807 host->dpm_state, mmc->nesting_cnt,
1808 host->context_loss, context_loss);
1810 if (host->suspended) {
1811 seq_printf(s, "host suspended, can't read registers\n");
1815 pm_runtime_get_sync(host->dev);
1817 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1818 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1819 seq_printf(s, "CON:\t\t0x%08x\n",
1820 OMAP_HSMMC_READ(host->base, CON));
1821 seq_printf(s, "HCTL:\t\t0x%08x\n",
1822 OMAP_HSMMC_READ(host->base, HCTL));
1823 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1824 OMAP_HSMMC_READ(host->base, SYSCTL));
1825 seq_printf(s, "IE:\t\t0x%08x\n",
1826 OMAP_HSMMC_READ(host->base, IE));
1827 seq_printf(s, "ISE:\t\t0x%08x\n",
1828 OMAP_HSMMC_READ(host->base, ISE));
1829 seq_printf(s, "CAPA:\t\t0x%08x\n",
1830 OMAP_HSMMC_READ(host->base, CAPA));
1832 pm_runtime_mark_last_busy(host->dev);
1833 pm_runtime_put_autosuspend(host->dev);
1838 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1840 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1843 static const struct file_operations mmc_regs_fops = {
1844 .open = omap_hsmmc_regs_open,
1846 .llseek = seq_lseek,
1847 .release = single_release,
1850 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1852 if (mmc->debugfs_root)
1853 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1854 mmc, &mmc_regs_fops);
1859 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1865 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1867 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1868 struct mmc_host *mmc;
1869 struct omap_hsmmc_host *host = NULL;
1870 struct resource *res;
1873 if (pdata == NULL) {
1874 dev_err(&pdev->dev, "Platform Data is missing\n");
1878 if (pdata->nr_slots == 0) {
1879 dev_err(&pdev->dev, "No Slots\n");
1883 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1884 irq = platform_get_irq(pdev, 0);
1885 if (res == NULL || irq < 0)
1888 res->start += pdata->reg_offset;
1889 res->end += pdata->reg_offset;
1890 res = request_mem_region(res->start, resource_size(res), pdev->name);
1894 ret = omap_hsmmc_gpio_init(pdata);
1898 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1904 host = mmc_priv(mmc);
1906 host->pdata = pdata;
1907 host->dev = &pdev->dev;
1909 host->dev->dma_mask = &pdata->dma_mask;
1912 host->id = pdev->id;
1914 host->mapbase = res->start;
1915 host->base = ioremap(host->mapbase, SZ_4K);
1916 host->power_mode = MMC_POWER_OFF;
1917 host->next_data.cookie = 1;
1919 platform_set_drvdata(pdev, host);
1920 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1922 mmc->ops = &omap_hsmmc_ops;
1925 * If regulator_disable can only put vcc_aux to sleep then there is
1928 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1929 mmc_slot(host).no_off = 1;
1931 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1932 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1934 spin_lock_init(&host->irq_lock);
1936 host->fclk = clk_get(&pdev->dev, "fck");
1937 if (IS_ERR(host->fclk)) {
1938 ret = PTR_ERR(host->fclk);
1943 omap_hsmmc_context_save(host);
1945 mmc->caps |= MMC_CAP_DISABLE;
1947 pm_runtime_enable(host->dev);
1948 pm_runtime_get_sync(host->dev);
1949 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1950 pm_runtime_use_autosuspend(host->dev);
1952 if (cpu_is_omap2430()) {
1953 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1955 * MMC can still work without debounce clock.
1957 if (IS_ERR(host->dbclk))
1958 dev_warn(mmc_dev(host->mmc),
1959 "Failed to get debounce clock\n");
1961 host->got_dbclk = 1;
1963 if (host->got_dbclk)
1964 if (clk_enable(host->dbclk) != 0)
1965 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1969 /* Since we do only SG emulation, we can have as many segs
1971 mmc->max_segs = 1024;
1973 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1974 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1975 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1976 mmc->max_seg_size = mmc->max_req_size;
1978 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1979 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1981 mmc->caps |= mmc_slot(host).caps;
1982 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1983 mmc->caps |= MMC_CAP_4_BIT_DATA;
1985 if (mmc_slot(host).nonremovable)
1986 mmc->caps |= MMC_CAP_NONREMOVABLE;
1988 omap_hsmmc_conf_bus_power(host);
1990 /* Select DMA lines */
1992 case OMAP_MMC1_DEVID:
1993 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1994 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1996 case OMAP_MMC2_DEVID:
1997 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1998 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2000 case OMAP_MMC3_DEVID:
2001 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2002 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2004 case OMAP_MMC4_DEVID:
2005 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2006 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2008 case OMAP_MMC5_DEVID:
2009 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2010 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2013 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2017 /* Request IRQ for MMC operations */
2018 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2019 mmc_hostname(mmc), host);
2021 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2025 if (pdata->init != NULL) {
2026 if (pdata->init(&pdev->dev) != 0) {
2027 dev_dbg(mmc_dev(host->mmc),
2028 "Unable to configure MMC IRQs\n");
2029 goto err_irq_cd_init;
2033 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2034 ret = omap_hsmmc_reg_get(host);
2040 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2042 /* Request IRQ for card detect */
2043 if ((mmc_slot(host).card_detect_irq)) {
2044 ret = request_irq(mmc_slot(host).card_detect_irq,
2045 omap_hsmmc_cd_handler,
2046 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2048 mmc_hostname(mmc), host);
2050 dev_dbg(mmc_dev(host->mmc),
2051 "Unable to grab MMC CD IRQ\n");
2054 pdata->suspend = omap_hsmmc_suspend_cdirq;
2055 pdata->resume = omap_hsmmc_resume_cdirq;
2058 omap_hsmmc_disable_irq(host);
2060 omap_hsmmc_protect_card(host);
2064 if (mmc_slot(host).name != NULL) {
2065 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2069 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2070 ret = device_create_file(&mmc->class_dev,
2071 &dev_attr_cover_switch);
2076 omap_hsmmc_debugfs(mmc);
2077 pm_runtime_mark_last_busy(host->dev);
2078 pm_runtime_put_autosuspend(host->dev);
2083 mmc_remove_host(mmc);
2084 free_irq(mmc_slot(host).card_detect_irq, host);
2087 omap_hsmmc_reg_put(host);
2089 if (host->pdata->cleanup)
2090 host->pdata->cleanup(&pdev->dev);
2092 free_irq(host->irq, host);
2094 pm_runtime_mark_last_busy(host->dev);
2095 pm_runtime_put_autosuspend(host->dev);
2096 clk_put(host->fclk);
2097 if (host->got_dbclk) {
2098 clk_disable(host->dbclk);
2099 clk_put(host->dbclk);
2102 iounmap(host->base);
2103 platform_set_drvdata(pdev, NULL);
2106 omap_hsmmc_gpio_free(pdata);
2108 release_mem_region(res->start, resource_size(res));
2112 static int omap_hsmmc_remove(struct platform_device *pdev)
2114 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2115 struct resource *res;
2118 pm_runtime_get_sync(host->dev);
2119 mmc_remove_host(host->mmc);
2121 omap_hsmmc_reg_put(host);
2122 if (host->pdata->cleanup)
2123 host->pdata->cleanup(&pdev->dev);
2124 free_irq(host->irq, host);
2125 if (mmc_slot(host).card_detect_irq)
2126 free_irq(mmc_slot(host).card_detect_irq, host);
2127 flush_work_sync(&host->mmc_carddetect_work);
2129 pm_runtime_put_sync(host->dev);
2130 pm_runtime_disable(host->dev);
2131 clk_put(host->fclk);
2132 if (host->got_dbclk) {
2133 clk_disable(host->dbclk);
2134 clk_put(host->dbclk);
2137 mmc_free_host(host->mmc);
2138 iounmap(host->base);
2139 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2142 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2144 release_mem_region(res->start, resource_size(res));
2145 platform_set_drvdata(pdev, NULL);
2151 static int omap_hsmmc_suspend(struct device *dev)
2154 struct platform_device *pdev = to_platform_device(dev);
2155 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2157 if (host && host->suspended)
2161 pm_runtime_get_sync(host->dev);
2162 host->suspended = 1;
2163 if (host->pdata->suspend) {
2164 ret = host->pdata->suspend(&pdev->dev,
2167 dev_dbg(mmc_dev(host->mmc),
2168 "Unable to handle MMC board"
2169 " level suspend\n");
2170 host->suspended = 0;
2174 cancel_work_sync(&host->mmc_carddetect_work);
2175 ret = mmc_suspend_host(host->mmc);
2178 omap_hsmmc_disable_irq(host);
2179 OMAP_HSMMC_WRITE(host->base, HCTL,
2180 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2181 if (host->got_dbclk)
2182 clk_disable(host->dbclk);
2184 host->suspended = 0;
2185 if (host->pdata->resume) {
2186 ret = host->pdata->resume(&pdev->dev,
2189 dev_dbg(mmc_dev(host->mmc),
2190 "Unmask interrupt failed\n");
2193 pm_runtime_put_sync(host->dev);
2198 /* Routine to resume the MMC device */
2199 static int omap_hsmmc_resume(struct device *dev)
2202 struct platform_device *pdev = to_platform_device(dev);
2203 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2205 if (host && !host->suspended)
2209 pm_runtime_get_sync(host->dev);
2211 if (host->got_dbclk)
2212 clk_enable(host->dbclk);
2214 omap_hsmmc_conf_bus_power(host);
2216 if (host->pdata->resume) {
2217 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2219 dev_dbg(mmc_dev(host->mmc),
2220 "Unmask interrupt failed\n");
2223 omap_hsmmc_protect_card(host);
2225 /* Notify the core to resume the host */
2226 ret = mmc_resume_host(host->mmc);
2228 host->suspended = 0;
2230 pm_runtime_mark_last_busy(host->dev);
2231 pm_runtime_put_autosuspend(host->dev);
2239 #define omap_hsmmc_suspend NULL
2240 #define omap_hsmmc_resume NULL
2243 static int omap_hsmmc_runtime_suspend(struct device *dev)
2245 struct omap_hsmmc_host *host;
2247 host = platform_get_drvdata(to_platform_device(dev));
2248 omap_hsmmc_context_save(host);
2249 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2254 static int omap_hsmmc_runtime_resume(struct device *dev)
2256 struct omap_hsmmc_host *host;
2258 host = platform_get_drvdata(to_platform_device(dev));
2259 omap_hsmmc_context_restore(host);
2260 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2265 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2266 .suspend = omap_hsmmc_suspend,
2267 .resume = omap_hsmmc_resume,
2268 .runtime_suspend = omap_hsmmc_runtime_suspend,
2269 .runtime_resume = omap_hsmmc_runtime_resume,
2272 static struct platform_driver omap_hsmmc_driver = {
2273 .remove = omap_hsmmc_remove,
2275 .name = DRIVER_NAME,
2276 .owner = THIS_MODULE,
2277 .pm = &omap_hsmmc_dev_pm_ops,
2281 static int __init omap_hsmmc_init(void)
2283 /* Register the MMC driver */
2284 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2287 static void __exit omap_hsmmc_cleanup(void)
2289 /* Unregister MMC driver */
2290 platform_driver_unregister(&omap_hsmmc_driver);
2293 module_init(omap_hsmmc_init);
2294 module_exit(omap_hsmmc_cleanup);
2296 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2297 MODULE_LICENSE("GPL");
2298 MODULE_ALIAS("platform:" DRIVER_NAME);
2299 MODULE_AUTHOR("Texas Instruments Inc");