2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/highmem.h>
21 #include <linux/log2.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/card.h>
24 #include <linux/amba/bus.h>
25 #include <linux/clk.h>
26 #include <linux/scatterlist.h>
27 #include <linux/gpio.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/amba/mmci.h>
33 #include <asm/div64.h>
35 #include <asm/sizes.h>
39 #define DRIVER_NAME "mmci-pl18x"
41 static unsigned int fmax = 515633;
44 * struct variant_data - MMCI variant-specific quirks
45 * @clkreg: default value for MCICLOCK register
46 * @clkreg_enable: enable value for MMCICLOCK register
47 * @datalength_bits: number of bits in the MMCIDATALENGTH register
48 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
49 * is asserted (likewise for RX)
50 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
51 * is asserted (likewise for RX)
52 * @sdio: variant supports SDIO
53 * @st_clkdiv: true if using a ST-specific clock divider algorithm
54 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register
58 unsigned int clkreg_enable;
59 unsigned int datalength_bits;
60 unsigned int fifosize;
61 unsigned int fifohalfsize;
64 bool blksz_datactrl16;
67 static struct variant_data variant_arm = {
69 .fifohalfsize = 8 * 4,
70 .datalength_bits = 16,
73 static struct variant_data variant_arm_extended_fifo = {
75 .fifohalfsize = 64 * 4,
76 .datalength_bits = 16,
79 static struct variant_data variant_u300 = {
81 .fifohalfsize = 8 * 4,
82 .clkreg_enable = MCI_ST_U300_HWFCEN,
83 .datalength_bits = 16,
87 static struct variant_data variant_ux500 = {
89 .fifohalfsize = 8 * 4,
90 .clkreg = MCI_CLK_ENABLE,
91 .clkreg_enable = MCI_ST_UX500_HWFCEN,
92 .datalength_bits = 24,
97 static struct variant_data variant_ux500v2 = {
99 .fifohalfsize = 8 * 4,
100 .clkreg = MCI_CLK_ENABLE,
101 .clkreg_enable = MCI_ST_UX500_HWFCEN,
102 .datalength_bits = 24,
105 .blksz_datactrl16 = true,
109 * This must be called with host->lock held
111 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
113 struct variant_data *variant = host->variant;
114 u32 clk = variant->clkreg;
117 if (desired >= host->mclk) {
118 clk = MCI_CLK_BYPASS;
119 if (variant->st_clkdiv)
120 clk |= MCI_ST_UX500_NEG_EDGE;
121 host->cclk = host->mclk;
122 } else if (variant->st_clkdiv) {
124 * DB8500 TRM says f = mclk / (clkdiv + 2)
125 * => clkdiv = (mclk / f) - 2
126 * Round the divider up so we don't exceed the max
129 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
132 host->cclk = host->mclk / (clk + 2);
135 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
136 * => clkdiv = mclk / (2 * f) - 1
138 clk = host->mclk / (2 * desired) - 1;
141 host->cclk = host->mclk / (2 * (clk + 1));
144 clk |= variant->clkreg_enable;
145 clk |= MCI_CLK_ENABLE;
146 /* This hasn't proven to be worthwhile */
147 /* clk |= MCI_CLK_PWRSAVE; */
150 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
152 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
153 clk |= MCI_ST_8BIT_BUS;
155 writel(clk, host->base + MMCICLOCK);
159 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
161 writel(0, host->base + MMCICOMMAND);
169 * Need to drop the host lock here; mmc_request_done may call
170 * back into the driver...
172 spin_unlock(&host->lock);
173 mmc_request_done(host->mmc, mrq);
174 spin_lock(&host->lock);
177 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
179 void __iomem *base = host->base;
181 if (host->singleirq) {
182 unsigned int mask0 = readl(base + MMCIMASK0);
184 mask0 &= ~MCI_IRQ1MASK;
187 writel(mask0, base + MMCIMASK0);
190 writel(mask, base + MMCIMASK1);
193 static void mmci_stop_data(struct mmci_host *host)
195 writel(0, host->base + MMCIDATACTRL);
196 mmci_set_mask1(host, 0);
200 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
202 unsigned int flags = SG_MITER_ATOMIC;
204 if (data->flags & MMC_DATA_READ)
205 flags |= SG_MITER_TO_SG;
207 flags |= SG_MITER_FROM_SG;
209 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
213 * All the DMA operation mode stuff goes inside this ifdef.
214 * This assumes that you have a generic DMA device interface,
215 * no custom DMA interfaces are supported.
217 #ifdef CONFIG_DMA_ENGINE
218 static void __devinit mmci_dma_setup(struct mmci_host *host)
220 struct mmci_platform_data *plat = host->plat;
221 const char *rxname, *txname;
224 if (!plat || !plat->dma_filter) {
225 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
229 /* Try to acquire a generic DMA engine slave channel */
231 dma_cap_set(DMA_SLAVE, mask);
234 * If only an RX channel is specified, the driver will
235 * attempt to use it bidirectionally, however if it is
236 * is specified but cannot be located, DMA will be disabled.
238 if (plat->dma_rx_param) {
239 host->dma_rx_channel = dma_request_channel(mask,
242 /* E.g if no DMA hardware is present */
243 if (!host->dma_rx_channel)
244 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
247 if (plat->dma_tx_param) {
248 host->dma_tx_channel = dma_request_channel(mask,
251 if (!host->dma_tx_channel)
252 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
254 host->dma_tx_channel = host->dma_rx_channel;
257 if (host->dma_rx_channel)
258 rxname = dma_chan_name(host->dma_rx_channel);
262 if (host->dma_tx_channel)
263 txname = dma_chan_name(host->dma_tx_channel);
267 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
271 * Limit the maximum segment size in any SG entry according to
272 * the parameters of the DMA engine device.
274 if (host->dma_tx_channel) {
275 struct device *dev = host->dma_tx_channel->device->dev;
276 unsigned int max_seg_size = dma_get_max_seg_size(dev);
278 if (max_seg_size < host->mmc->max_seg_size)
279 host->mmc->max_seg_size = max_seg_size;
281 if (host->dma_rx_channel) {
282 struct device *dev = host->dma_rx_channel->device->dev;
283 unsigned int max_seg_size = dma_get_max_seg_size(dev);
285 if (max_seg_size < host->mmc->max_seg_size)
286 host->mmc->max_seg_size = max_seg_size;
291 * This is used in __devinit or __devexit so inline it
292 * so it can be discarded.
294 static inline void mmci_dma_release(struct mmci_host *host)
296 struct mmci_platform_data *plat = host->plat;
298 if (host->dma_rx_channel)
299 dma_release_channel(host->dma_rx_channel);
300 if (host->dma_tx_channel && plat->dma_tx_param)
301 dma_release_channel(host->dma_tx_channel);
302 host->dma_rx_channel = host->dma_tx_channel = NULL;
305 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
307 struct dma_chan *chan = host->dma_current;
308 enum dma_data_direction dir;
312 /* Wait up to 1ms for the DMA to complete */
314 status = readl(host->base + MMCISTATUS);
315 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
321 * Check to see whether we still have some data left in the FIFO -
322 * this catches DMA controllers which are unable to monitor the
323 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
324 * contiguous buffers. On TX, we'll get a FIFO underrun error.
326 if (status & MCI_RXDATAAVLBLMASK) {
327 dmaengine_terminate_all(chan);
332 if (data->flags & MMC_DATA_WRITE) {
335 dir = DMA_FROM_DEVICE;
338 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
341 * Use of DMA with scatter-gather is impossible.
342 * Give up with DMA and switch back to PIO mode.
344 if (status & MCI_RXDATAAVLBLMASK) {
345 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
346 mmci_dma_release(host);
350 static void mmci_dma_data_error(struct mmci_host *host)
352 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
353 dmaengine_terminate_all(host->dma_current);
356 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
358 struct variant_data *variant = host->variant;
359 struct dma_slave_config conf = {
360 .src_addr = host->phybase + MMCIFIFO,
361 .dst_addr = host->phybase + MMCIFIFO,
362 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
363 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
364 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
365 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
367 struct mmc_data *data = host->data;
368 struct dma_chan *chan;
369 struct dma_device *device;
370 struct dma_async_tx_descriptor *desc;
373 host->dma_current = NULL;
375 if (data->flags & MMC_DATA_READ) {
376 conf.direction = DMA_FROM_DEVICE;
377 chan = host->dma_rx_channel;
379 conf.direction = DMA_TO_DEVICE;
380 chan = host->dma_tx_channel;
383 /* If there's no DMA channel, fall back to PIO */
387 /* If less than or equal to the fifo size, don't bother with DMA */
388 if (host->size <= variant->fifosize)
391 device = chan->device;
392 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction);
396 dmaengine_slave_config(chan, &conf);
397 desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
398 conf.direction, DMA_CTRL_ACK);
402 /* Okay, go for it. */
403 host->dma_current = chan;
405 dev_vdbg(mmc_dev(host->mmc),
406 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
407 data->sg_len, data->blksz, data->blocks, data->flags);
408 dmaengine_submit(desc);
409 dma_async_issue_pending(chan);
411 datactrl |= MCI_DPSM_DMAENABLE;
413 /* Trigger the DMA transfer */
414 writel(datactrl, host->base + MMCIDATACTRL);
417 * Let the MMCI say when the data is ended and it's time
418 * to fire next DMA request. When that happens, MMCI will
419 * call mmci_data_end()
421 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
422 host->base + MMCIMASK0);
426 dmaengine_terminate_all(chan);
427 dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction);
431 /* Blank functions if the DMA engine is not available */
432 static inline void mmci_dma_setup(struct mmci_host *host)
436 static inline void mmci_dma_release(struct mmci_host *host)
440 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
444 static inline void mmci_dma_data_error(struct mmci_host *host)
448 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
454 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
456 struct variant_data *variant = host->variant;
457 unsigned int datactrl, timeout, irqmask;
458 unsigned long long clks;
462 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
463 data->blksz, data->blocks, data->flags);
466 host->size = data->blksz * data->blocks;
467 data->bytes_xfered = 0;
469 clks = (unsigned long long)data->timeout_ns * host->cclk;
470 do_div(clks, 1000000000UL);
472 timeout = data->timeout_clks + (unsigned int)clks;
475 writel(timeout, base + MMCIDATATIMER);
476 writel(host->size, base + MMCIDATALENGTH);
478 blksz_bits = ffs(data->blksz) - 1;
479 BUG_ON(1 << blksz_bits != data->blksz);
481 if (variant->blksz_datactrl16)
482 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
484 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
486 if (data->flags & MMC_DATA_READ)
487 datactrl |= MCI_DPSM_DIRECTION;
490 * Attempt to use DMA operation mode, if this
491 * should fail, fall back to PIO mode
493 if (!mmci_dma_start_data(host, datactrl))
496 /* IRQ mode, map the SG list for CPU reading/writing */
497 mmci_init_sg(host, data);
499 if (data->flags & MMC_DATA_READ) {
500 irqmask = MCI_RXFIFOHALFFULLMASK;
503 * If we have less than the fifo 'half-full' threshold to
504 * transfer, trigger a PIO interrupt as soon as any data
507 if (host->size < variant->fifohalfsize)
508 irqmask |= MCI_RXDATAAVLBLMASK;
511 * We don't actually need to include "FIFO empty" here
512 * since its implicit in "FIFO half empty".
514 irqmask = MCI_TXFIFOHALFEMPTYMASK;
517 /* The ST Micro variants has a special bit to enable SDIO */
518 if (variant->sdio && host->mmc->card)
519 if (mmc_card_sdio(host->mmc->card))
520 datactrl |= MCI_ST_DPSM_SDIOEN;
522 writel(datactrl, base + MMCIDATACTRL);
523 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
524 mmci_set_mask1(host, irqmask);
528 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
530 void __iomem *base = host->base;
532 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
533 cmd->opcode, cmd->arg, cmd->flags);
535 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
536 writel(0, base + MMCICOMMAND);
540 c |= cmd->opcode | MCI_CPSM_ENABLE;
541 if (cmd->flags & MMC_RSP_PRESENT) {
542 if (cmd->flags & MMC_RSP_136)
543 c |= MCI_CPSM_LONGRSP;
544 c |= MCI_CPSM_RESPONSE;
547 c |= MCI_CPSM_INTERRUPT;
551 writel(cmd->arg, base + MMCIARGUMENT);
552 writel(c, base + MMCICOMMAND);
556 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
559 /* First check for errors */
560 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
563 /* Terminate the DMA transfer */
564 if (dma_inprogress(host))
565 mmci_dma_data_error(host);
568 * Calculate how far we are into the transfer. Note that
569 * the data counter gives the number of bytes transferred
570 * on the MMC bus, not on the host side. On reads, this
571 * can be as much as a FIFO-worth of data ahead. This
572 * matters for FIFO overruns only.
574 remain = readl(host->base + MMCIDATACNT);
575 success = data->blksz * data->blocks - remain;
577 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
579 if (status & MCI_DATACRCFAIL) {
580 /* Last block was not successful */
582 data->error = -EILSEQ;
583 } else if (status & MCI_DATATIMEOUT) {
584 data->error = -ETIMEDOUT;
585 } else if (status & MCI_STARTBITERR) {
586 data->error = -ECOMM;
587 } else if (status & MCI_TXUNDERRUN) {
589 } else if (status & MCI_RXOVERRUN) {
590 if (success > host->variant->fifosize)
591 success -= host->variant->fifosize;
596 data->bytes_xfered = round_down(success, data->blksz);
599 if (status & MCI_DATABLOCKEND)
600 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
602 if (status & MCI_DATAEND || data->error) {
603 if (dma_inprogress(host))
604 mmci_dma_unmap(host, data);
605 mmci_stop_data(host);
608 /* The error clause is handled above, success! */
609 data->bytes_xfered = data->blksz * data->blocks;
612 mmci_request_end(host, data->mrq);
614 mmci_start_command(host, data->stop, 0);
620 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
623 void __iomem *base = host->base;
627 if (status & MCI_CMDTIMEOUT) {
628 cmd->error = -ETIMEDOUT;
629 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
630 cmd->error = -EILSEQ;
632 cmd->resp[0] = readl(base + MMCIRESPONSE0);
633 cmd->resp[1] = readl(base + MMCIRESPONSE1);
634 cmd->resp[2] = readl(base + MMCIRESPONSE2);
635 cmd->resp[3] = readl(base + MMCIRESPONSE3);
638 if (!cmd->data || cmd->error) {
640 mmci_stop_data(host);
641 mmci_request_end(host, cmd->mrq);
642 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
643 mmci_start_data(host, cmd->data);
647 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
649 void __iomem *base = host->base;
652 int host_remain = host->size;
655 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
663 readsl(base + MMCIFIFO, ptr, count >> 2);
667 host_remain -= count;
672 status = readl(base + MMCISTATUS);
673 } while (status & MCI_RXDATAAVLBL);
678 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
680 struct variant_data *variant = host->variant;
681 void __iomem *base = host->base;
685 unsigned int count, maxcnt;
687 maxcnt = status & MCI_TXFIFOEMPTY ?
688 variant->fifosize : variant->fifohalfsize;
689 count = min(remain, maxcnt);
692 * The ST Micro variant for SDIO transfer sizes
693 * less then 8 bytes should have clock H/W flow
697 mmc_card_sdio(host->mmc->card)) {
699 writel(readl(host->base + MMCICLOCK) &
700 ~variant->clkreg_enable,
701 host->base + MMCICLOCK);
703 writel(readl(host->base + MMCICLOCK) |
704 variant->clkreg_enable,
705 host->base + MMCICLOCK);
709 * SDIO especially may want to send something that is
710 * not divisible by 4 (as opposed to card sectors
711 * etc), and the FIFO only accept full 32-bit writes.
712 * So compensate by adding +3 on the count, a single
713 * byte become a 32bit write, 7 bytes will be two
716 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
724 status = readl(base + MMCISTATUS);
725 } while (status & MCI_TXFIFOHALFEMPTY);
731 * PIO data transfer IRQ handler.
733 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
735 struct mmci_host *host = dev_id;
736 struct sg_mapping_iter *sg_miter = &host->sg_miter;
737 struct variant_data *variant = host->variant;
738 void __iomem *base = host->base;
742 status = readl(base + MMCISTATUS);
744 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
746 local_irq_save(flags);
749 unsigned int remain, len;
753 * For write, we only need to test the half-empty flag
754 * here - if the FIFO is completely empty, then by
755 * definition it is more than half empty.
757 * For read, check for data available.
759 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
762 if (!sg_miter_next(sg_miter))
765 buffer = sg_miter->addr;
766 remain = sg_miter->length;
769 if (status & MCI_RXACTIVE)
770 len = mmci_pio_read(host, buffer, remain);
771 if (status & MCI_TXACTIVE)
772 len = mmci_pio_write(host, buffer, remain, status);
774 sg_miter->consumed = len;
782 status = readl(base + MMCISTATUS);
785 sg_miter_stop(sg_miter);
787 local_irq_restore(flags);
790 * If we have less than the fifo 'half-full' threshold to transfer,
791 * trigger a PIO interrupt as soon as any data is available.
793 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
794 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
797 * If we run out of data, disable the data IRQs; this
798 * prevents a race where the FIFO becomes empty before
799 * the chip itself has disabled the data path, and
800 * stops us racing with our data end IRQ.
802 if (host->size == 0) {
803 mmci_set_mask1(host, 0);
804 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
811 * Handle completion of command and data transfers.
813 static irqreturn_t mmci_irq(int irq, void *dev_id)
815 struct mmci_host *host = dev_id;
819 spin_lock(&host->lock);
822 struct mmc_command *cmd;
823 struct mmc_data *data;
825 status = readl(host->base + MMCISTATUS);
827 if (host->singleirq) {
828 if (status & readl(host->base + MMCIMASK1))
829 mmci_pio_irq(irq, dev_id);
831 status &= ~MCI_IRQ1MASK;
834 status &= readl(host->base + MMCIMASK0);
835 writel(status, host->base + MMCICLEAR);
837 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
840 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
841 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
842 mmci_data_irq(host, data, status);
845 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
846 mmci_cmd_irq(host, cmd, status);
851 spin_unlock(&host->lock);
853 return IRQ_RETVAL(ret);
856 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
858 struct mmci_host *host = mmc_priv(mmc);
861 WARN_ON(host->mrq != NULL);
863 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
864 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
866 mrq->cmd->error = -EINVAL;
867 mmc_request_done(mmc, mrq);
871 spin_lock_irqsave(&host->lock, flags);
875 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
876 mmci_start_data(host, mrq->data);
878 mmci_start_command(host, mrq->cmd, 0);
880 spin_unlock_irqrestore(&host->lock, flags);
883 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
885 struct mmci_host *host = mmc_priv(mmc);
890 switch (ios->power_mode) {
893 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
897 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
899 dev_err(mmc_dev(mmc), "unable to set OCR\n");
901 * The .set_ios() function in the mmc_host_ops
902 * struct return void, and failing to set the
903 * power should be rare so we print an error
909 if (host->plat->vdd_handler)
910 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
912 /* The ST version does not have this, fall through to POWER_ON */
913 if (host->hw_designer != AMBA_VENDOR_ST) {
922 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
923 if (host->hw_designer != AMBA_VENDOR_ST)
927 * The ST Micro variant use the ROD bit for something
928 * else and only has OD (Open Drain).
934 spin_lock_irqsave(&host->lock, flags);
936 mmci_set_clkreg(host, ios->clock);
938 if (host->pwr != pwr) {
940 writel(pwr, host->base + MMCIPOWER);
943 spin_unlock_irqrestore(&host->lock, flags);
946 static int mmci_get_ro(struct mmc_host *mmc)
948 struct mmci_host *host = mmc_priv(mmc);
950 if (host->gpio_wp == -ENOSYS)
953 return gpio_get_value_cansleep(host->gpio_wp);
956 static int mmci_get_cd(struct mmc_host *mmc)
958 struct mmci_host *host = mmc_priv(mmc);
959 struct mmci_platform_data *plat = host->plat;
962 if (host->gpio_cd == -ENOSYS) {
964 return 1; /* Assume always present */
966 status = plat->status(mmc_dev(host->mmc));
968 status = !!gpio_get_value_cansleep(host->gpio_cd)
972 * Use positive logic throughout - status is zero for no card,
973 * non-zero for card inserted.
978 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
980 struct mmci_host *host = dev_id;
982 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
987 static const struct mmc_host_ops mmci_ops = {
988 .request = mmci_request,
989 .set_ios = mmci_set_ios,
990 .get_ro = mmci_get_ro,
991 .get_cd = mmci_get_cd,
994 static int __devinit mmci_probe(struct amba_device *dev,
995 const struct amba_id *id)
997 struct mmci_platform_data *plat = dev->dev.platform_data;
998 struct variant_data *variant = id->data;
999 struct mmci_host *host;
1000 struct mmc_host *mmc;
1003 /* must have platform data */
1009 ret = amba_request_regions(dev, DRIVER_NAME);
1013 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1019 host = mmc_priv(mmc);
1022 host->gpio_wp = -ENOSYS;
1023 host->gpio_cd = -ENOSYS;
1024 host->gpio_cd_irq = -1;
1026 host->hw_designer = amba_manf(dev);
1027 host->hw_revision = amba_rev(dev);
1028 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1029 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1031 host->clk = clk_get(&dev->dev, NULL);
1032 if (IS_ERR(host->clk)) {
1033 ret = PTR_ERR(host->clk);
1038 ret = clk_enable(host->clk);
1043 host->variant = variant;
1044 host->mclk = clk_get_rate(host->clk);
1046 * According to the spec, mclk is max 100 MHz,
1047 * so we try to adjust the clock down to this,
1050 if (host->mclk > 100000000) {
1051 ret = clk_set_rate(host->clk, 100000000);
1054 host->mclk = clk_get_rate(host->clk);
1055 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1058 host->phybase = dev->res.start;
1059 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1065 mmc->ops = &mmci_ops;
1067 * The ARM and ST versions of the block have slightly different
1068 * clock divider equations which means that the minimum divider
1071 if (variant->st_clkdiv)
1072 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1074 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1076 * If the platform data supplies a maximum operating
1077 * frequency, this takes precedence. Else, we fall back
1078 * to using the module parameter, which has a (low)
1079 * default value in case it is not specified. Either
1080 * value must not exceed the clock rate into the block,
1084 mmc->f_max = min(host->mclk, plat->f_max);
1086 mmc->f_max = min(host->mclk, fmax);
1087 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1089 #ifdef CONFIG_REGULATOR
1090 /* If we're using the regulator framework, try to fetch a regulator */
1091 host->vcc = regulator_get(&dev->dev, "vmmc");
1092 if (IS_ERR(host->vcc))
1095 int mask = mmc_regulator_get_ocrmask(host->vcc);
1098 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
1101 host->mmc->ocr_avail = (u32) mask;
1104 "Provided ocr_mask/setpower will not be used "
1105 "(using regulator instead)\n");
1109 /* Fall back to platform data if no regulator is found */
1110 if (host->vcc == NULL)
1111 mmc->ocr_avail = plat->ocr_mask;
1112 mmc->caps = plat->capabilities;
1117 mmc->max_segs = NR_SG;
1120 * Since only a certain number of bits are valid in the data length
1121 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1124 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1127 * Set the maximum segment size. Since we aren't doing DMA
1128 * (yet) we are only limited by the data length register.
1130 mmc->max_seg_size = mmc->max_req_size;
1133 * Block size can be up to 2048 bytes, but must be a power of two.
1135 mmc->max_blk_size = 2048;
1138 * No limit on the number of blocks transferred.
1140 mmc->max_blk_count = mmc->max_req_size;
1142 spin_lock_init(&host->lock);
1144 writel(0, host->base + MMCIMASK0);
1145 writel(0, host->base + MMCIMASK1);
1146 writel(0xfff, host->base + MMCICLEAR);
1148 if (gpio_is_valid(plat->gpio_cd)) {
1149 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1151 ret = gpio_direction_input(plat->gpio_cd);
1153 host->gpio_cd = plat->gpio_cd;
1154 else if (ret != -ENOSYS)
1158 * A gpio pin that will detect cards when inserted and removed
1159 * will most likely want to trigger on the edges if it is
1160 * 0 when ejected and 1 when inserted (or mutatis mutandis
1161 * for the inverted case) so we request triggers on both
1164 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1166 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1167 DRIVER_NAME " (cd)", host);
1169 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1171 if (gpio_is_valid(plat->gpio_wp)) {
1172 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1174 ret = gpio_direction_input(plat->gpio_wp);
1176 host->gpio_wp = plat->gpio_wp;
1177 else if (ret != -ENOSYS)
1181 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1182 && host->gpio_cd_irq < 0)
1183 mmc->caps |= MMC_CAP_NEEDS_POLL;
1185 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1189 if (dev->irq[1] == NO_IRQ)
1190 host->singleirq = true;
1192 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1193 DRIVER_NAME " (pio)", host);
1198 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1200 amba_set_drvdata(dev, mmc);
1202 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1203 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1204 amba_rev(dev), (unsigned long long)dev->res.start,
1205 dev->irq[0], dev->irq[1]);
1207 mmci_dma_setup(host);
1214 free_irq(dev->irq[0], host);
1216 if (host->gpio_wp != -ENOSYS)
1217 gpio_free(host->gpio_wp);
1219 if (host->gpio_cd_irq >= 0)
1220 free_irq(host->gpio_cd_irq, host);
1221 if (host->gpio_cd != -ENOSYS)
1222 gpio_free(host->gpio_cd);
1224 iounmap(host->base);
1226 clk_disable(host->clk);
1232 amba_release_regions(dev);
1237 static int __devexit mmci_remove(struct amba_device *dev)
1239 struct mmc_host *mmc = amba_get_drvdata(dev);
1241 amba_set_drvdata(dev, NULL);
1244 struct mmci_host *host = mmc_priv(mmc);
1246 mmc_remove_host(mmc);
1248 writel(0, host->base + MMCIMASK0);
1249 writel(0, host->base + MMCIMASK1);
1251 writel(0, host->base + MMCICOMMAND);
1252 writel(0, host->base + MMCIDATACTRL);
1254 mmci_dma_release(host);
1255 free_irq(dev->irq[0], host);
1256 if (!host->singleirq)
1257 free_irq(dev->irq[1], host);
1259 if (host->gpio_wp != -ENOSYS)
1260 gpio_free(host->gpio_wp);
1261 if (host->gpio_cd_irq >= 0)
1262 free_irq(host->gpio_cd_irq, host);
1263 if (host->gpio_cd != -ENOSYS)
1264 gpio_free(host->gpio_cd);
1266 iounmap(host->base);
1267 clk_disable(host->clk);
1271 mmc_regulator_set_ocr(mmc, host->vcc, 0);
1272 regulator_put(host->vcc);
1276 amba_release_regions(dev);
1283 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1285 struct mmc_host *mmc = amba_get_drvdata(dev);
1289 struct mmci_host *host = mmc_priv(mmc);
1291 ret = mmc_suspend_host(mmc);
1293 writel(0, host->base + MMCIMASK0);
1299 static int mmci_resume(struct amba_device *dev)
1301 struct mmc_host *mmc = amba_get_drvdata(dev);
1305 struct mmci_host *host = mmc_priv(mmc);
1307 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1309 ret = mmc_resume_host(mmc);
1315 #define mmci_suspend NULL
1316 #define mmci_resume NULL
1319 static struct amba_id mmci_ids[] = {
1323 .data = &variant_arm,
1328 .data = &variant_arm_extended_fifo,
1333 .data = &variant_arm,
1335 /* ST Micro variants */
1339 .data = &variant_u300,
1344 .data = &variant_u300,
1349 .data = &variant_ux500,
1354 .data = &variant_ux500v2,
1359 static struct amba_driver mmci_driver = {
1361 .name = DRIVER_NAME,
1363 .probe = mmci_probe,
1364 .remove = __devexit_p(mmci_remove),
1365 .suspend = mmci_suspend,
1366 .resume = mmci_resume,
1367 .id_table = mmci_ids,
1370 static int __init mmci_init(void)
1372 return amba_driver_register(&mmci_driver);
1375 static void __exit mmci_exit(void)
1377 amba_driver_unregister(&mmci_driver);
1380 module_init(mmci_init);
1381 module_exit(mmci_exit);
1382 module_param(fmax, uint, 0444);
1384 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1385 MODULE_LICENSE("GPL");