drivers/mmc/host/imxmmc.c

   1 /*
   2  *  linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
   3  *
   4  *  Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
   5  *  Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
   6  *
   7  *  derived from pxamci.c by Russell King
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/ioport.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/blkdev.h>
  21 #include <linux/dma-mapping.h>
  22 #include <linux/mmc/host.h>
  23 #include <linux/mmc/card.h>
  24 #include <linux/delay.h>
  25 #include <linux/clk.h>
  26 #include <linux/io.h>
  27
  28 #include <asm/dma.h>
  29 #include <asm/irq.h>
  30 #include <asm/sizes.h>
  31 #include <mach/mmc.h>
  32 #include <mach/imx-dma.h>
  33
  34 #include "imxmmc.h"
  35
  36 #define DRIVER_NAME "imx-mmc"
  37
  38 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
  39                                  INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
  40                                  INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
  41
  42 struct imxmci_host {
  43         struct mmc_host         *mmc;
  44         spinlock_t              lock;
  45         struct resource         *res;
  46         void __iomem            *base;
  47         int                     irq;
  48         imx_dmach_t             dma;
  49         volatile unsigned int   imask;
  50         unsigned int            power_mode;
  51         unsigned int            present;
  52         struct imxmmc_platform_data *pdata;
  53
  54         struct mmc_request      *req;
  55         struct mmc_command      *cmd;
  56         struct mmc_data         *data;
  57
  58         struct timer_list       timer;
  59         struct tasklet_struct   tasklet;
  60         unsigned int            status_reg;
  61         unsigned long           pending_events;
  62         /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
  63         u16                     *data_ptr;
  64         unsigned int            data_cnt;
  65         atomic_t                stuck_timeout;
  66
  67         unsigned int            dma_nents;
  68         unsigned int            dma_size;
  69         unsigned int            dma_dir;
  70         int                     dma_allocated;
  71
  72         unsigned char           actual_bus_width;
  73
  74         int                     prev_cmd_code;
  75
  76         struct clk              *clk;
  77 };
  78
  79 #define IMXMCI_PEND_IRQ_b       0
  80 #define IMXMCI_PEND_DMA_END_b   1
  81 #define IMXMCI_PEND_DMA_ERR_b   2
  82 #define IMXMCI_PEND_WAIT_RESP_b 3
  83 #define IMXMCI_PEND_DMA_DATA_b  4
  84 #define IMXMCI_PEND_CPU_DATA_b  5
  85 #define IMXMCI_PEND_CARD_XCHG_b 6
  86 #define IMXMCI_PEND_SET_INIT_b  7
  87 #define IMXMCI_PEND_STARTED_b   8
  88
  89 #define IMXMCI_PEND_IRQ_m       (1 << IMXMCI_PEND_IRQ_b)
  90 #define IMXMCI_PEND_DMA_END_m   (1 << IMXMCI_PEND_DMA_END_b)
  91 #define IMXMCI_PEND_DMA_ERR_m   (1 << IMXMCI_PEND_DMA_ERR_b)
  92 #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
  93 #define IMXMCI_PEND_DMA_DATA_m  (1 << IMXMCI_PEND_DMA_DATA_b)
  94 #define IMXMCI_PEND_CPU_DATA_m  (1 << IMXMCI_PEND_CPU_DATA_b)
  95 #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
  96 #define IMXMCI_PEND_SET_INIT_m  (1 << IMXMCI_PEND_SET_INIT_b)
  97 #define IMXMCI_PEND_STARTED_m   (1 << IMXMCI_PEND_STARTED_b)
  98
  99 static void imxmci_stop_clock(struct imxmci_host *host)
 100 {
 101         int i = 0;
 102         u16 reg;
 103
 104         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 105         writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
 106         while (i < 0x1000) {
 107                 if (!(i & 0x7f)) {
 108                         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 109                         writew(reg | STR_STP_CLK_STOP_CLK,
 110                                         host->base + MMC_REG_STR_STP_CLK);
 111                 }
 112
 113                 reg = readw(host->base + MMC_REG_STATUS);
 114                 if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
 115                         /* Check twice before cut */
 116                         reg = readw(host->base + MMC_REG_STATUS);
 117                         if (!(reg & STATUS_CARD_BUS_CLK_RUN))
 118                                 return;
 119                 }
 120
 121                 i++;
 122         }
 123         dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
 124 }
 125
 126 static int imxmci_start_clock(struct imxmci_host *host)
 127 {
 128         unsigned int trials = 0;
 129         unsigned int delay_limit = 128;
 130         unsigned long flags;
 131         u16 reg;
 132
 133         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 134         writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
 135
 136         clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
 137
 138         /*
 139          * Command start of the clock, this usually succeeds in less
 140          * then 6 delay loops, but during card detection (low clockrate)
 141          * it takes up to 5000 delay loops and sometimes fails for the first time
 142          */
 143         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 144         writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
 145
 146         do {
 147                 unsigned int delay = delay_limit;
 148
 149                 while (delay--) {
 150                         reg = readw(host->base + MMC_REG_STATUS);
 151                         if (reg & STATUS_CARD_BUS_CLK_RUN)
 152                                 /* Check twice before cut */
 153                                 reg = readw(host->base + MMC_REG_STATUS);
 154                                 if (reg & STATUS_CARD_BUS_CLK_RUN)
 155                                         return 0;
 156
 157                         if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
 158                                 return 0;
 159                 }
 160
 161                 local_irq_save(flags);
 162                 /*
 163                  * Ensure, that request is not doubled under all possible circumstances.
 164                  * It is possible, that cock running state is missed, because some other
 165                  * IRQ or schedule delays this function execution and the clocks has
 166                  * been already stopped by other means (response processing, SDHC HW)
 167                  */
 168                 if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
 169                         reg = readw(host->base + MMC_REG_STR_STP_CLK);
 170                         writew(reg | STR_STP_CLK_START_CLK,
 171                                         host->base + MMC_REG_STR_STP_CLK);
 172                 }
 173                 local_irq_restore(flags);
 174
 175         } while (++trials < 256);
 176
 177         dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
 178
 179         return -1;
 180 }
 181
 182 static void imxmci_softreset(struct imxmci_host *host)
 183 {
 184         int i;
 185
 186         /* reset sequence */
 187         writew(0x08, host->base + MMC_REG_STR_STP_CLK);
 188         writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
 189
 190         for (i = 0; i < 8; i++)
 191                 writew(0x05, host->base + MMC_REG_STR_STP_CLK);
 192
 193         writew(0xff, host->base + MMC_REG_RES_TO);
 194         writew(512, host->base + MMC_REG_BLK_LEN);
 195         writew(1, host->base + MMC_REG_NOB);
 196 }
 197
 198 static int imxmci_busy_wait_for_status(struct imxmci_host *host,
 199                                        unsigned int *pstat, unsigned int stat_mask,
 200                                        int timeout, const char *where)
 201 {
 202         int loops = 0;
 203
 204         while (!(*pstat & stat_mask)) {
 205                 loops += 2;
 206                 if (loops >= timeout) {
 207                         dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
 208                                 where, *pstat, stat_mask);
 209                         return -1;
 210                 }
 211                 udelay(2);
 212                 *pstat |= readw(host->base + MMC_REG_STATUS);
 213         }
 214         if (!loops)
 215                 return 0;
 216
 217         /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
 218         if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
 219                 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
 220                          loops, where, *pstat, stat_mask);
 221         return loops;
 222 }
 223
 224 static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
 225 {
 226         unsigned int nob = data->blocks;
 227         unsigned int blksz = data->blksz;
 228         unsigned int datasz = nob * blksz;
 229         int i;
 230
 231         if (data->flags & MMC_DATA_STREAM)
 232                 nob = 0xffff;
 233
 234         host->data = data;
 235         data->bytes_xfered = 0;
 236
 237         writew(nob, host->base + MMC_REG_NOB);
 238         writew(blksz, host->base + MMC_REG_BLK_LEN);
 239
 240         /*
 241          * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
 242          * We are in big troubles for non-512 byte transfers according to note in the paragraph
 243          * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
 244          * The situation is even more complex in reality. The SDHC in not able to handle wll
 245          * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
 246          * This is required for SCR read at least.
 247          */
 248         if (datasz < 512) {
 249                 host->dma_size = datasz;
 250                 if (data->flags & MMC_DATA_READ) {
 251                         host->dma_dir = DMA_FROM_DEVICE;
 252
 253                         /* Hack to enable read SCR */
 254                         writew(1, host->base + MMC_REG_NOB);
 255                         writew(512, host->base + MMC_REG_BLK_LEN);
 256                 } else {
 257                         host->dma_dir = DMA_TO_DEVICE;
 258                 }
 259
 260                 /* Convert back to virtual address */
 261                 host->data_ptr = (u16 *)sg_virt(data->sg);
 262                 host->data_cnt = 0;
 263
 264                 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
 265                 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
 266
 267                 return;
 268         }
 269
 270         if (data->flags & MMC_DATA_READ) {
 271                 host->dma_dir = DMA_FROM_DEVICE;
 272                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
 273                                              data->sg_len,  host->dma_dir);
 274
 275                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
 276                                  host->res->start + MMC_REG_BUFFER_ACCESS,
 277                                  DMA_MODE_READ);
 278
 279                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
 280                 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
 281         } else {
 282                 host->dma_dir = DMA_TO_DEVICE;
 283
 284                 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
 285                                              data->sg_len,  host->dma_dir);
 286
 287                 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
 288                                  host->res->start + MMC_REG_BUFFER_ACCESS,
 289                                  DMA_MODE_WRITE);
 290
 291                 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
 292                 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
 293         }
 294
 295 #if 1   /* This code is there only for consistency checking and can be disabled in future */
 296         host->dma_size = 0;
 297         for (i = 0; i < host->dma_nents; i++)
 298                 host->dma_size += data->sg[i].length;
 299
 300         if (datasz > host->dma_size) {
 301                 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
 302                         datasz, host->dma_size);
 303         }
 304 #endif
 305
 306         host->dma_size = datasz;
 307
 308         wmb();
 309
 310         if (host->actual_bus_width == MMC_BUS_WIDTH_4)
 311                 BLR(host->dma) = 0;     /* burst 64 byte read / 64 bytes write */
 312         else
 313                 BLR(host->dma) = 16;    /* burst 16 byte read / 16 bytes write */
 314
 315         RSSR(host->dma) = DMA_REQ_SDHC;
 316
 317         set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
 318         clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
 319
 320         /* start DMA engine for read, write is delayed after initial response */
 321         if (host->dma_dir == DMA_FROM_DEVICE)
 322                 imx_dma_enable(host->dma);
 323 }
 324
 325 static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
 326 {
 327         unsigned long flags;
 328         u32 imask;
 329
 330         WARN_ON(host->cmd != NULL);
 331         host->cmd = cmd;
 332
 333         /* Ensure, that clock are stopped else command programming and start fails */
 334         imxmci_stop_clock(host);
 335
 336         if (cmd->flags & MMC_RSP_BUSY)
 337                 cmdat |= CMD_DAT_CONT_BUSY;
 338
 339         switch (mmc_resp_type(cmd)) {
 340         case MMC_RSP_R1: /* short CRC, OPCODE */
 341         case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
 342                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
 343                 break;
 344         case MMC_RSP_R2: /* long 136 bit + CRC */
 345                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
 346                 break;
 347         case MMC_RSP_R3: /* short */
 348                 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
 349                 break;
 350         default:
 351                 break;
 352         }
 353
 354         if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
 355                 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
 356
 357         if (host->actual_bus_width == MMC_BUS_WIDTH_4)
 358                 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
 359
 360         writew(cmd->opcode, host->base + MMC_REG_CMD);
 361         writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
 362         writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
 363         writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
 364
 365         atomic_set(&host->stuck_timeout, 0);
 366         set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
 367
 368
 369         imask = IMXMCI_INT_MASK_DEFAULT;
 370         imask &= ~INT_MASK_END_CMD_RES;
 371         if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
 372                 /* imask &= ~INT_MASK_BUF_READY; */
 373                 imask &= ~INT_MASK_DATA_TRAN;
 374                 if (cmdat & CMD_DAT_CONT_WRITE)
 375                         imask &= ~INT_MASK_WRITE_OP_DONE;
 376                 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
 377                         imask &= ~INT_MASK_BUF_READY;
 378         }
 379
 380         spin_lock_irqsave(&host->lock, flags);
 381         host->imask = imask;
 382         writew(host->imask, host->base + MMC_REG_INT_MASK);
 383         spin_unlock_irqrestore(&host->lock, flags);
 384
 385         dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
 386                 cmd->opcode, cmd->opcode, imask);
 387
 388         imxmci_start_clock(host);
 389 }
 390
 391 static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
 392 {
 393         unsigned long flags;
 394
 395         spin_lock_irqsave(&host->lock, flags);
 396
 397         host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
 398                                   IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
 399
 400         host->imask = IMXMCI_INT_MASK_DEFAULT;
 401         writew(host->imask, host->base + MMC_REG_INT_MASK);
 402
 403         spin_unlock_irqrestore(&host->lock, flags);
 404
 405         if (req && req->cmd)
 406                 host->prev_cmd_code = req->cmd->opcode;
 407
 408         host->req = NULL;
 409         host->cmd = NULL;
 410         host->data = NULL;
 411         mmc_request_done(host->mmc, req);
 412 }
 413
 414 static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
 415 {
 416         struct mmc_data *data = host->data;
 417         int data_error;
 418
 419         if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
 420                 imx_dma_disable(host->dma);
 421                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
 422                              host->dma_dir);
 423         }
 424
 425         if (stat & STATUS_ERR_MASK) {
 426                 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
 427                 if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
 428                         data->error = -EILSEQ;
 429                 else if (stat & STATUS_TIME_OUT_READ)
 430                         data->error = -ETIMEDOUT;
 431                 else
 432                         data->error = -EIO;
 433         } else {
 434                 data->bytes_xfered = host->dma_size;
 435         }
 436
 437         data_error = data->error;
 438
 439         host->data = NULL;
 440
 441         return data_error;
 442 }
 443
 444 static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
 445 {
 446         struct mmc_command *cmd = host->cmd;
 447         int i;
 448         u32 a, b, c;
 449         struct mmc_data *data = host->data;
 450
 451         if (!cmd)
 452                 return 0;
 453
 454         host->cmd = NULL;
 455
 456         if (stat & STATUS_TIME_OUT_RESP) {
 457                 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
 458                 cmd->error = -ETIMEDOUT;
 459         } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
 460                 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
 461                 cmd->error = -EILSEQ;
 462         }
 463
 464         if (cmd->flags & MMC_RSP_PRESENT) {
 465                 if (cmd->flags & MMC_RSP_136) {
 466                         for (i = 0; i < 4; i++) {
 467                                 a = readw(host->base + MMC_REG_RES_FIFO);
 468                                 b = readw(host->base + MMC_REG_RES_FIFO);
 469                                 cmd->resp[i] = a << 16 | b;
 470                         }
 471                 } else {
 472                         a = readw(host->base + MMC_REG_RES_FIFO);
 473                         b = readw(host->base + MMC_REG_RES_FIFO);
 474                         c = readw(host->base + MMC_REG_RES_FIFO);
 475                         cmd->resp[0] = a << 24 | b << 8 | c >> 8;
 476                 }
 477         }
 478
 479         dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
 480                 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
 481
 482         if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) {
 483                 if (host->req->data->flags & MMC_DATA_WRITE) {
 484
 485                         /* Wait for FIFO to be empty before starting DMA write */
 486
 487                         stat = readw(host->base + MMC_REG_STATUS);
 488                         if (imxmci_busy_wait_for_status(host, &stat,
 489                                                         STATUS_APPL_BUFF_FE,
 490                                                         40, "imxmci_cmd_done DMA WR") < 0) {
 491                                 cmd->error = -EIO;
 492                                 imxmci_finish_data(host, stat);
 493                                 if (host->req)
 494                                         imxmci_finish_request(host, host->req);
 495                                 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
 496                                          stat);
 497                                 return 0;
 498                         }
 499
 500                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
 501                                 imx_dma_enable(host->dma);
 502                 }
 503         } else {
 504                 struct mmc_request *req;
 505                 imxmci_stop_clock(host);
 506                 req = host->req;
 507
 508                 if (data)
 509                         imxmci_finish_data(host, stat);
 510
 511                 if (req)
 512                         imxmci_finish_request(host, req);
 513                 else
 514                         dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
 515         }
 516
 517         return 1;
 518 }
 519
 520 static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
 521 {
 522         struct mmc_data *data = host->data;
 523         int data_error;
 524
 525         if (!data)
 526                 return 0;
 527
 528         data_error = imxmci_finish_data(host, stat);
 529
 530         if (host->req->stop) {
 531                 imxmci_stop_clock(host);
 532                 imxmci_start_cmd(host, host->req->stop, 0);
 533         } else {
 534                 struct mmc_request *req;
 535                 req = host->req;
 536                 if (req)
 537                         imxmci_finish_request(host, req);
 538                 else
 539                         dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
 540         }
 541
 542         return 1;
 543 }
 544
 545 static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
 546 {
 547         int i;
 548         int burst_len;
 549         int trans_done = 0;
 550         unsigned int stat = *pstat;
 551
 552         if (host->actual_bus_width != MMC_BUS_WIDTH_4)
 553                 burst_len = 16;
 554         else
 555                 burst_len = 64;
 556
 557         /* This is unfortunately required */
 558         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
 559                 stat);
 560
 561         udelay(20);     /* required for clocks < 8MHz*/
 562
 563         if (host->dma_dir == DMA_FROM_DEVICE) {
 564                 imxmci_busy_wait_for_status(host, &stat,
 565                                             STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
 566                                             STATUS_TIME_OUT_READ,
 567                                             50, "imxmci_cpu_driven_data read");
 568
 569                 while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
 570                        !(stat & STATUS_TIME_OUT_READ) &&
 571                        (host->data_cnt < 512)) {
 572
 573                         udelay(20);     /* required for clocks < 8MHz*/
 574
 575                         for (i = burst_len; i >= 2 ; i -= 2) {
 576                                 u16 data;
 577                                 data = readw(host->base + MMC_REG_BUFFER_ACCESS);
 578                                 udelay(10);     /* required for clocks < 8MHz*/
 579                                 if (host->data_cnt+2 <= host->dma_size) {
 580                                         *(host->data_ptr++) = data;
 581                                 } else {
 582                                         if (host->data_cnt < host->dma_size)
 583                                                 *(u8 *)(host->data_ptr) = data;
 584                                 }
 585                                 host->data_cnt += 2;
 586                         }
 587
 588                         stat = readw(host->base + MMC_REG_STATUS);
 589
 590                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
 591                                 host->data_cnt, burst_len, stat);
 592                 }
 593
 594                 if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
 595                         trans_done = 1;
 596
 597                 if (host->dma_size & 0x1ff)
 598                         stat &= ~STATUS_CRC_READ_ERR;
 599
 600                 if (stat & STATUS_TIME_OUT_READ) {
 601                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
 602                                 stat);
 603                         trans_done = -1;
 604                 }
 605
 606         } else {
 607                 imxmci_busy_wait_for_status(host, &stat,
 608                                             STATUS_APPL_BUFF_FE,
 609                                             20, "imxmci_cpu_driven_data write");
 610
 611                 while ((stat & STATUS_APPL_BUFF_FE) &&
 612                        (host->data_cnt < host->dma_size)) {
 613                         if (burst_len >= host->dma_size - host->data_cnt) {
 614                                 burst_len = host->dma_size - host->data_cnt;
 615                                 host->data_cnt = host->dma_size;
 616                                 trans_done = 1;
 617                         } else {
 618                                 host->data_cnt += burst_len;
 619                         }
 620
 621                         for (i = burst_len; i > 0 ; i -= 2)
 622                                 writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
 623
 624                         stat = readw(host->base + MMC_REG_STATUS);
 625
 626                         dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
 627                                 burst_len, stat);
 628                 }
 629         }
 630
 631         *pstat = stat;
 632
 633         return trans_done;
 634 }
 635
 636 static void imxmci_dma_irq(int dma, void *devid)
 637 {
 638         struct imxmci_host *host = devid;
 639         u32 stat = readw(host->base + MMC_REG_STATUS);
 640
 641         atomic_set(&host->stuck_timeout, 0);
 642         host->status_reg = stat;
 643         set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
 644         tasklet_schedule(&host->tasklet);
 645 }
 646
 647 static irqreturn_t imxmci_irq(int irq, void *devid)
 648 {
 649         struct imxmci_host *host = devid;
 650         u32 stat = readw(host->base + MMC_REG_STATUS);
 651         int handled = 1;
 652
 653         writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
 654                         host->base + MMC_REG_INT_MASK);
 655
 656         atomic_set(&host->stuck_timeout, 0);
 657         host->status_reg = stat;
 658         set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
 659         set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
 660         tasklet_schedule(&host->tasklet);
 661
 662         return IRQ_RETVAL(handled);;
 663 }
 664
 665 static void imxmci_tasklet_fnc(unsigned long data)
 666 {
 667         struct imxmci_host *host = (struct imxmci_host *)data;
 668         u32 stat;
 669         unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
 670         int timeout = 0;
 671
 672         if (atomic_read(&host->stuck_timeout) > 4) {
 673                 char *what;
 674                 timeout = 1;
 675                 stat = readw(host->base + MMC_REG_STATUS);
 676                 host->status_reg = stat;
 677                 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
 678                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
 679                                 what = "RESP+DMA";
 680                         else
 681                                 what = "RESP";
 682                 else
 683                         if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
 684                                 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
 685                                         what = "DATA";
 686                                 else
 687                                         what = "DMA";
 688                         else
 689                                 what = "???";
 690
 691                 dev_err(mmc_dev(host->mmc),
 692                         "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
 693                         what, stat,
 694                         readw(host->base + MMC_REG_INT_MASK));
 695                 dev_err(mmc_dev(host->mmc),
 696                         "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
 697                         readw(host->base + MMC_REG_CMD_DAT_CONT),
 698                         readw(host->base + MMC_REG_BLK_LEN),
 699                         readw(host->base + MMC_REG_NOB),
 700                         CCR(host->dma));
 701                 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
 702                         host->cmd ? host->cmd->opcode : 0,
 703                         host->prev_cmd_code,
 704                         1 << host->actual_bus_width, host->dma_size);
 705         }
 706
 707         if (!host->present || timeout)
 708                 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
 709                         STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
 710
 711         if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
 712                 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
 713
 714                 stat = readw(host->base + MMC_REG_STATUS);
 715                 /*
 716                  * This is not required in theory, but there is chance to miss some flag
 717                  * which clears automatically by mask write, FreeScale original code keeps
 718                  * stat from IRQ time so do I
 719                  */
 720                 stat |= host->status_reg;
 721
 722                 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
 723                         stat &= ~STATUS_CRC_READ_ERR;
 724
 725                 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
 726                         imxmci_busy_wait_for_status(host, &stat,
 727                                                     STATUS_END_CMD_RESP | STATUS_ERR_MASK,
 728                                                     20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
 729                 }
 730
 731                 if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
 732                         if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
 733                                 imxmci_cmd_done(host, stat);
 734                         if (host->data && (stat & STATUS_ERR_MASK))
 735                                 imxmci_data_done(host, stat);
 736                 }
 737
 738                 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
 739                         stat |= readw(host->base + MMC_REG_STATUS);
 740                         if (imxmci_cpu_driven_data(host, &stat)) {
 741                                 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
 742                                         imxmci_cmd_done(host, stat);
 743                                 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
 744                                                   &host->pending_events);
 745                                 imxmci_data_done(host, stat);
 746                         }
 747                 }
 748         }
 749
 750         if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
 751             !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
 752
 753                 stat = readw(host->base + MMC_REG_STATUS);
 754                 /* Same as above */
 755                 stat |= host->status_reg;
 756
 757                 if (host->dma_dir == DMA_TO_DEVICE)
 758                         data_dir_mask = STATUS_WRITE_OP_DONE;
 759                 else
 760                         data_dir_mask = STATUS_DATA_TRANS_DONE;
 761
 762                 if (stat & data_dir_mask) {
 763                         clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
 764                         imxmci_data_done(host, stat);
 765                 }
 766         }
 767
 768         if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
 769
 770                 if (host->cmd)
 771                         imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
 772
 773                 if (host->data)
 774                         imxmci_data_done(host, STATUS_TIME_OUT_READ |
 775                                          STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
 776
 777                 if (host->req)
 778                         imxmci_finish_request(host, host->req);
 779
 780                 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
 781
 782         }
 783 }
 784
 785 static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
 786 {
 787         struct imxmci_host *host = mmc_priv(mmc);
 788         unsigned int cmdat;
 789
 790         WARN_ON(host->req != NULL);
 791
 792         host->req = req;
 793
 794         cmdat = 0;
 795
 796         if (req->data) {
 797                 imxmci_setup_data(host, req->data);
 798
 799                 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
 800
 801                 if (req->data->flags & MMC_DATA_WRITE)
 802                         cmdat |= CMD_DAT_CONT_WRITE;
 803
 804                 if (req->data->flags & MMC_DATA_STREAM)
 805                         cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
 806         }
 807
 808         imxmci_start_cmd(host, req->cmd, cmdat);
 809 }
 810
 811 #define CLK_RATE 19200000
 812
 813 static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 814 {
 815         struct imxmci_host *host = mmc_priv(mmc);
 816         int prescaler;
 817
 818         if (ios->bus_width == MMC_BUS_WIDTH_4) {
 819                 host->actual_bus_width = MMC_BUS_WIDTH_4;
 820                 imx_gpio_mode(PB11_PF_SD_DAT3);
 821         } else {
 822                 host->actual_bus_width = MMC_BUS_WIDTH_1;
 823                 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
 824         }
 825
 826         if (host->power_mode != ios->power_mode) {
 827                 switch (ios->power_mode) {
 828                 case MMC_POWER_OFF:
 829                         break;
 830                 case MMC_POWER_UP:
 831                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
 832                         break;
 833                 case MMC_POWER_ON:
 834                         break;
 835                 }
 836                 host->power_mode = ios->power_mode;
 837         }
 838
 839         if (ios->clock) {
 840                 unsigned int clk;
 841                 u16 reg;
 842
 843                 /* The prescaler is 5 for PERCLK2 equal to 96MHz
 844                  * then 96MHz / 5 = 19.2 MHz
 845                  */
 846                 clk = clk_get_rate(host->clk);
 847                 prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
 848                 switch (prescaler) {
 849                 case 0:
 850                 case 1: prescaler = 0;
 851                         break;
 852                 case 2: prescaler = 1;
 853                         break;
 854                 case 3: prescaler = 2;
 855                         break;
 856                 case 4: prescaler = 4;
 857                         break;
 858                 default:
 859                 case 5: prescaler = 5;
 860                         break;
 861                 }
 862
 863                 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
 864                         clk, prescaler);
 865
 866                 for (clk = 0; clk < 8; clk++) {
 867                         int x;
 868                         x = CLK_RATE / (1 << clk);
 869                         if (x <= ios->clock)
 870                                 break;
 871                 }
 872
 873                 /* enable controller */
 874                 reg = readw(host->base + MMC_REG_STR_STP_CLK);
 875                 writew(reg | STR_STP_CLK_ENABLE,
 876                                 host->base + MMC_REG_STR_STP_CLK);
 877
 878                 imxmci_stop_clock(host);
 879                 writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
 880                 /*
 881                  * Under my understanding, clock should not be started there, because it would
 882                  * initiate SDHC sequencer and send last or random command into card
 883                  */
 884                 /* imxmci_start_clock(host); */
 885
 886                 dev_dbg(mmc_dev(host->mmc),
 887                         "MMC_CLK_RATE: 0x%08x\n",
 888                         readw(host->base + MMC_REG_CLK_RATE));
 889         } else {
 890                 imxmci_stop_clock(host);
 891         }
 892 }
 893
 894 static int imxmci_get_ro(struct mmc_host *mmc)
 895 {
 896         struct imxmci_host *host = mmc_priv(mmc);
 897
 898         if (host->pdata && host->pdata->get_ro)
 899                 return !!host->pdata->get_ro(mmc_dev(mmc));
 900         /*
 901          * Board doesn't support read only detection; let the mmc core
 902          * decide what to do.
 903          */
 904         return -ENOSYS;
 905 }
 906
 907
 908 static const struct mmc_host_ops imxmci_ops = {
 909         .request        = imxmci_request,
 910         .set_ios        = imxmci_set_ios,
 911         .get_ro         = imxmci_get_ro,
 912 };
 913
 914 static void imxmci_check_status(unsigned long data)
 915 {
 916         struct imxmci_host *host = (struct imxmci_host *)data;
 917
 918         if (host->pdata && host->pdata->card_present &&
 919             host->pdata->card_present(mmc_dev(host->mmc)) != host->present) {
 920                 host->present ^= 1;
 921                 dev_info(mmc_dev(host->mmc), "card %s\n",
 922                       host->present ? "inserted" : "removed");
 923
 924                 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
 925                 tasklet_schedule(&host->tasklet);
 926         }
 927
 928         if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
 929             test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
 930                 atomic_inc(&host->stuck_timeout);
 931                 if (atomic_read(&host->stuck_timeout) > 4)
 932                         tasklet_schedule(&host->tasklet);
 933         } else {
 934                 atomic_set(&host->stuck_timeout, 0);
 935
 936         }
 937
 938         mod_timer(&host->timer, jiffies + (HZ>>1));
 939 }
 940
 941 static int imxmci_probe(struct platform_device *pdev)
 942 {
 943         struct mmc_host *mmc;
 944         struct imxmci_host *host = NULL;
 945         struct resource *r;
 946         int ret = 0, irq;
 947         u16 rev_no;
 948
 949         printk(KERN_INFO "i.MX mmc driver\n");
 950
 951         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 952         irq = platform_get_irq(pdev, 0);
 953         if (!r || irq < 0)
 954                 return -ENXIO;
 955
 956         r = request_mem_region(r->start, resource_size(r), pdev->name);
 957         if (!r)
 958                 return -EBUSY;
 959
 960         mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
 961         if (!mmc) {
 962                 ret = -ENOMEM;
 963                 goto out;
 964         }
 965
 966         mmc->ops = &imxmci_ops;
 967         mmc->f_min = 150000;
 968         mmc->f_max = CLK_RATE/2;
 969         mmc->ocr_avail = MMC_VDD_32_33;
 970         mmc->caps = MMC_CAP_4_BIT_DATA;
 971
 972         /* MMC core transfer sizes tunable parameters */
 973         mmc->max_hw_segs = 64;
 974         mmc->max_phys_segs = 64;
 975         mmc->max_seg_size = 64*512;     /* default PAGE_CACHE_SIZE */
 976         mmc->max_req_size = 64*512;     /* default PAGE_CACHE_SIZE */
 977         mmc->max_blk_size = 2048;
 978         mmc->max_blk_count = 65535;
 979
 980         host = mmc_priv(mmc);
 981         host->base = ioremap(r->start, resource_size(r));
 982         if (!host->base) {
 983                 ret = -ENOMEM;
 984                 goto out;
 985         }
 986
 987         host->mmc = mmc;
 988         host->dma_allocated = 0;
 989         host->pdata = pdev->dev.platform_data;
 990         if (!host->pdata)
 991                 dev_warn(&pdev->dev, "No platform data provided!\n");
 992
 993         spin_lock_init(&host->lock);
 994         host->res = r;
 995         host->irq = irq;
 996
 997         host->clk = clk_get(&pdev->dev, "perclk2");
 998         if (IS_ERR(host->clk)) {
 999                 ret = PTR_ERR(host->clk);
1000                 goto out;
1001         }
1002         clk_enable(host->clk);
1003
1004         imx_gpio_mode(PB8_PF_SD_DAT0);
1005         imx_gpio_mode(PB9_PF_SD_DAT1);
1006         imx_gpio_mode(PB10_PF_SD_DAT2);
1007         /* Configured as GPIO with pull-up to ensure right MCC card mode */
1008         /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
1009         imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
1010         /* imx_gpio_mode(PB11_PF_SD_DAT3); */
1011         imx_gpio_mode(PB12_PF_SD_CLK);
1012         imx_gpio_mode(PB13_PF_SD_CMD);
1013
1014         imxmci_softreset(host);
1015
1016         rev_no = readw(host->base + MMC_REG_REV_NO);
1017         if (rev_no != 0x390) {
1018                 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1019                         readw(host->base + MMC_REG_REV_NO));
1020                 goto out;
1021         }
1022
1023         /* recommended in data sheet */
1024         writew(0x2db4, host->base + MMC_REG_READ_TO);
1025
1026         host->imask = IMXMCI_INT_MASK_DEFAULT;
1027         writew(host->imask, host->base + MMC_REG_INT_MASK);
1028
1029         host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
1030         if(host->dma < 0) {
1031                 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
1032                 ret = -EBUSY;
1033                 goto out;
1034         }
1035         host->dma_allocated = 1;
1036         imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
1037
1038         tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
1039         host->status_reg=0;
1040         host->pending_events=0;
1041
1042         ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1043         if (ret)
1044                 goto out;
1045
1046         if (host->pdata && host->pdata->card_present)
1047                 host->present = host->pdata->card_present(mmc_dev(mmc));
1048         else    /* if there is no way to detect assume that card is present */
1049                 host->present = 1;
1050
1051         init_timer(&host->timer);
1052         host->timer.data = (unsigned long)host;
1053         host->timer.function = imxmci_check_status;
1054         add_timer(&host->timer);
1055         mod_timer(&host->timer, jiffies + (HZ >> 1));
1056
1057         platform_set_drvdata(pdev, mmc);
1058
1059         mmc_add_host(mmc);
1060
1061         return 0;
1062
1063 out:
1064         if (host) {
1065                 if (host->dma_allocated) {
1066                         imx_dma_free(host->dma);
1067                         host->dma_allocated = 0;
1068                 }
1069                 if (host->clk) {
1070                         clk_disable(host->clk);
1071                         clk_put(host->clk);
1072                 }
1073                 if (host->base)
1074                         iounmap(host->base);
1075         }
1076         if (mmc)
1077                 mmc_free_host(mmc);
1078         release_mem_region(r->start, resource_size(r));
1079         return ret;
1080 }
1081
1082 static int imxmci_remove(struct platform_device *pdev)
1083 {
1084         struct mmc_host *mmc = platform_get_drvdata(pdev);
1085
1086         platform_set_drvdata(pdev, NULL);
1087
1088         if (mmc) {
1089                 struct imxmci_host *host = mmc_priv(mmc);
1090
1091                 tasklet_disable(&host->tasklet);
1092
1093                 del_timer_sync(&host->timer);
1094                 mmc_remove_host(mmc);
1095
1096                 free_irq(host->irq, host);
1097                 iounmap(host->base);
1098                 if (host->dma_allocated) {
1099                         imx_dma_free(host->dma);
1100                         host->dma_allocated = 0;
1101                 }
1102
1103                 tasklet_kill(&host->tasklet);
1104
1105                 clk_disable(host->clk);
1106                 clk_put(host->clk);
1107
1108                 release_mem_region(host->res->start, resource_size(host->res));
1109
1110                 mmc_free_host(mmc);
1111         }
1112         return 0;
1113 }
1114
1115 #ifdef CONFIG_PM
1116 static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1117 {
1118         struct mmc_host *mmc = platform_get_drvdata(dev);
1119         int ret = 0;
1120
1121         if (mmc)
1122                 ret = mmc_suspend_host(mmc, state);
1123
1124         return ret;
1125 }
1126
1127 static int imxmci_resume(struct platform_device *dev)
1128 {
1129         struct mmc_host *mmc = platform_get_drvdata(dev);
1130         struct imxmci_host *host;
1131         int ret = 0;
1132
1133         if (mmc) {
1134                 host = mmc_priv(mmc);
1135                 if (host)
1136                         set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1137                 ret = mmc_resume_host(mmc);
1138         }
1139
1140         return ret;
1141 }
1142 #else
1143 #define imxmci_suspend  NULL
1144 #define imxmci_resume   NULL
1145 #endif /* CONFIG_PM */
1146
1147 static struct platform_driver imxmci_driver = {
1148         .probe          = imxmci_probe,
1149         .remove         = imxmci_remove,
1150         .suspend        = imxmci_suspend,
1151         .resume         = imxmci_resume,
1152         .driver         = {
1153                 .name           = DRIVER_NAME,
1154                 .owner          = THIS_MODULE,
1155         }
1156 };
1157
1158 static int __init imxmci_init(void)
1159 {
1160         return platform_driver_register(&imxmci_driver);
1161 }
1162
1163 static void __exit imxmci_exit(void)
1164 {
1165         platform_driver_unregister(&imxmci_driver);
1166 }
1167
1168 module_init(imxmci_init);
1169 module_exit(imxmci_exit);
1170
1171 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1172 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1173 MODULE_LICENSE("GPL");
1174 MODULE_ALIAS("platform:imx-mmc");