drivers/mmc/host/au1xmmc.c

   1 /*
   2  * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
   3  *
   4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   5  *
   6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   7  *  the following copyright notices:
   8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
   9  *     Portions Copyright (C) 2002 Embedix, Inc
  10  *     Copyright 2002 Hewlett-Packard Company
  11
  12  *  2.6 version of this driver inspired by:
  13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14  *     All Rights Reserved.
  15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16  *     All Rights Reserved.
  17  *
  18
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 /* Why is a timer used to detect insert events?
  25  *
  26  * From the AU1100 MMC application guide:
  27  * If the Au1100-based design is intended to support both MultiMediaCards
  28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  30  * In doing so, a MMC card never enters SPI-mode communications,
  31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  32  * (the low to high transition will not occur).
  33  *
  34  * So we use the timer to check the status manually.
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/mm.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/scatterlist.h>
  44
  45 #include <linux/mmc/host.h>
  46 #include <asm/io.h>
  47 #include <asm/mach-au1x00/au1000.h>
  48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  49 #include <asm/mach-au1x00/au1100_mmc.h>
  50
  51 #include <au1xxx.h>
  52 #include "au1xmmc.h"
  53
  54 #define DRIVER_NAME "au1xxx-mmc"
  55
  56 /* Set this to enable special debugging macros */
  57
  58 #ifdef DEBUG
  59 #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
  60 #else
  61 #define DBG(fmt, idx, args...)
  62 #endif
  63
  64 const struct {
  65         u32 iobase;
  66         u32 tx_devid, rx_devid;
  67         u16 bcsrpwr;
  68         u16 bcsrstatus;
  69         u16 wpstatus;
  70 } au1xmmc_card_table[] = {
  71         { SD0_BASE, DSCR_CMD0_SDMS_TX0, DSCR_CMD0_SDMS_RX0,
  72           BCSR_BOARD_SD0PWR, BCSR_INT_SD0INSERT, BCSR_STATUS_SD0WP },
  73 #ifndef CONFIG_MIPS_DB1200
  74         { SD1_BASE, DSCR_CMD0_SDMS_TX1, DSCR_CMD0_SDMS_RX1,
  75           BCSR_BOARD_DS1PWR, BCSR_INT_SD1INSERT, BCSR_STATUS_SD1WP }
  76 #endif
  77 };
  78
  79 #define AU1XMMC_CONTROLLER_COUNT (ARRAY_SIZE(au1xmmc_card_table))
  80
  81 /* This array stores pointers for the hosts (used by the IRQ handler) */
  82 struct au1xmmc_host *au1xmmc_hosts[AU1XMMC_CONTROLLER_COUNT];
  83 static int dma = 1;
  84
  85 #ifdef MODULE
  86 module_param(dma, bool, 0);
  87 MODULE_PARM_DESC(dma, "Use DMA engine for data transfers (0 = disabled)");
  88 #endif
  89
  90 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
  91 {
  92         u32 val = au_readl(HOST_CONFIG(host));
  93         val |= mask;
  94         au_writel(val, HOST_CONFIG(host));
  95         au_sync();
  96 }
  97
  98 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
  99 {
 100         u32 val = au_readl(HOST_CONFIG2(host));
 101
 102         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
 103         au_sync_delay(1);
 104
 105         /* SEND_STOP will turn off clock control - this re-enables it */
 106         val &= ~SD_CONFIG2_DF;
 107
 108         au_writel(val, HOST_CONFIG2(host));
 109         au_sync();
 110 }
 111
 112 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
 113 {
 114         u32 val = au_readl(HOST_CONFIG(host));
 115         val &= ~mask;
 116         au_writel(val, HOST_CONFIG(host));
 117         au_sync();
 118 }
 119
 120 static inline void SEND_STOP(struct au1xmmc_host *host)
 121 {
 122
 123         /* We know the value of CONFIG2, so avoid a read we don't need */
 124         u32 mask = SD_CONFIG2_EN;
 125
 126         WARN_ON(host->status != HOST_S_DATA);
 127         host->status = HOST_S_STOP;
 128
 129         au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
 130         au_sync();
 131
 132         /* Send the stop commmand */
 133         au_writel(STOP_CMD, HOST_CMD(host));
 134 }
 135
 136 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 137 {
 138
 139         u32 val = au1xmmc_card_table[host->id].bcsrpwr;
 140
 141         bcsr->board &= ~val;
 142         if (state) bcsr->board |= val;
 143
 144         au_sync_delay(1);
 145 }
 146
 147 static inline int au1xmmc_card_inserted(struct au1xmmc_host *host)
 148 {
 149         return (bcsr->sig_status & au1xmmc_card_table[host->id].bcsrstatus)
 150                 ? 1 : 0;
 151 }
 152
 153 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 154 {
 155         struct au1xmmc_host *host = mmc_priv(mmc);
 156         return (bcsr->status & au1xmmc_card_table[host->id].wpstatus)
 157                 ? 1 : 0;
 158 }
 159
 160 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 161 {
 162
 163         struct mmc_request *mrq = host->mrq;
 164
 165         host->mrq = NULL;
 166         host->flags &= HOST_F_ACTIVE;
 167
 168         host->dma.len = 0;
 169         host->dma.dir = 0;
 170
 171         host->pio.index  = 0;
 172         host->pio.offset = 0;
 173         host->pio.len = 0;
 174
 175         host->status = HOST_S_IDLE;
 176
 177         bcsr->disk_leds |= (1 << 8);
 178
 179         mmc_request_done(host->mmc, mrq);
 180 }
 181
 182 static void au1xmmc_tasklet_finish(unsigned long param)
 183 {
 184         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 185         au1xmmc_finish_request(host);
 186 }
 187
 188 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 189                                 struct mmc_command *cmd, struct mmc_data *data)
 190 {
 191         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 192
 193         switch (mmc_resp_type(cmd)) {
 194         case MMC_RSP_NONE:
 195                 break;
 196         case MMC_RSP_R1:
 197                 mmccmd |= SD_CMD_RT_1;
 198                 break;
 199         case MMC_RSP_R1B:
 200                 mmccmd |= SD_CMD_RT_1B;
 201                 break;
 202         case MMC_RSP_R2:
 203                 mmccmd |= SD_CMD_RT_2;
 204                 break;
 205         case MMC_RSP_R3:
 206                 mmccmd |= SD_CMD_RT_3;
 207                 break;
 208         default:
 209                 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
 210                         mmc_resp_type(cmd));
 211                 return -EINVAL;
 212         }
 213
 214         if (data) {
 215                 if (data->flags & MMC_DATA_READ) {
 216                         if (data->blocks > 1)
 217                                 mmccmd |= SD_CMD_CT_4;
 218                         else
 219                                 mmccmd |= SD_CMD_CT_2;
 220                 } else if (data->flags & MMC_DATA_WRITE) {
 221                         if (data->blocks > 1)
 222                                 mmccmd |= SD_CMD_CT_3;
 223                         else
 224                                 mmccmd |= SD_CMD_CT_1;
 225                 }
 226         }
 227
 228         au_writel(cmd->arg, HOST_CMDARG(host));
 229         au_sync();
 230
 231         if (wait)
 232                 IRQ_OFF(host, SD_CONFIG_CR);
 233
 234         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 235         au_sync();
 236
 237         /* Wait for the command to go on the line */
 238
 239         while(1) {
 240                 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
 241                         break;
 242         }
 243
 244         /* Wait for the command to come back */
 245
 246         if (wait) {
 247                 u32 status = au_readl(HOST_STATUS(host));
 248
 249                 while(!(status & SD_STATUS_CR))
 250                         status = au_readl(HOST_STATUS(host));
 251
 252                 /* Clear the CR status */
 253                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
 254
 255                 IRQ_ON(host, SD_CONFIG_CR);
 256         }
 257
 258         return 0;
 259 }
 260
 261 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 262 {
 263
 264         struct mmc_request *mrq = host->mrq;
 265         struct mmc_data *data;
 266         u32 crc;
 267
 268         WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
 269
 270         if (host->mrq == NULL)
 271                 return;
 272
 273         data = mrq->cmd->data;
 274
 275         if (status == 0)
 276                 status = au_readl(HOST_STATUS(host));
 277
 278         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 279
 280         while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 281                 status = au_readl(HOST_STATUS(host));
 282
 283         data->error = 0;
 284         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 285
 286         /* Process any errors */
 287
 288         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 289         if (host->flags & HOST_F_XMIT)
 290                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 291
 292         if (crc)
 293                 data->error = -EILSEQ;
 294
 295         /* Clear the CRC bits */
 296         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 297
 298         data->bytes_xfered = 0;
 299
 300         if (!data->error) {
 301                 if (host->flags & HOST_F_DMA) {
 302                         u32 chan = DMA_CHANNEL(host);
 303
 304                         chan_tab_t *c = *((chan_tab_t **) chan);
 305                         au1x_dma_chan_t *cp = c->chan_ptr;
 306                         data->bytes_xfered = cp->ddma_bytecnt;
 307                 }
 308                 else
 309                         data->bytes_xfered =
 310                                 (data->blocks * data->blksz) -
 311                                 host->pio.len;
 312         }
 313
 314         au1xmmc_finish_request(host);
 315 }
 316
 317 static void au1xmmc_tasklet_data(unsigned long param)
 318 {
 319         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 320
 321         u32 status = au_readl(HOST_STATUS(host));
 322         au1xmmc_data_complete(host, status);
 323 }
 324
 325 #define AU1XMMC_MAX_TRANSFER 8
 326
 327 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 328 {
 329
 330         struct mmc_data *data = 0;
 331         int sg_len, max, count = 0;
 332         unsigned char *sg_ptr;
 333         u32 status = 0;
 334         struct scatterlist *sg;
 335
 336         data = host->mrq->data;
 337
 338         if (!(host->flags & HOST_F_XMIT))
 339                 return;
 340
 341         /* This is the pointer to the data buffer */
 342         sg = &data->sg[host->pio.index];
 343         sg_ptr = sg_virt(sg) + host->pio.offset;
 344
 345         /* This is the space left inside the buffer */
 346         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 347
 348         /* Check to if we need less then the size of the sg_buffer */
 349
 350         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 351         if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
 352
 353         for(count = 0; count < max; count++ ) {
 354                 unsigned char val;
 355
 356                 status = au_readl(HOST_STATUS(host));
 357
 358                 if (!(status & SD_STATUS_TH))
 359                         break;
 360
 361                 val = *sg_ptr++;
 362
 363                 au_writel((unsigned long) val, HOST_TXPORT(host));
 364                 au_sync();
 365         }
 366
 367         host->pio.len -= count;
 368         host->pio.offset += count;
 369
 370         if (count == sg_len) {
 371                 host->pio.index++;
 372                 host->pio.offset = 0;
 373         }
 374
 375         if (host->pio.len == 0) {
 376                 IRQ_OFF(host, SD_CONFIG_TH);
 377
 378                 if (host->flags & HOST_F_STOP)
 379                         SEND_STOP(host);
 380
 381                 tasklet_schedule(&host->data_task);
 382         }
 383 }
 384
 385 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 386 {
 387
 388         struct mmc_data *data = 0;
 389         int sg_len = 0, max = 0, count = 0;
 390         unsigned char *sg_ptr = 0;
 391         u32 status = 0;
 392         struct scatterlist *sg;
 393
 394         data = host->mrq->data;
 395
 396         if (!(host->flags & HOST_F_RECV))
 397                 return;
 398
 399         max = host->pio.len;
 400
 401         if (host->pio.index < host->dma.len) {
 402                 sg = &data->sg[host->pio.index];
 403                 sg_ptr = sg_virt(sg) + host->pio.offset;
 404
 405                 /* This is the space left inside the buffer */
 406                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 407
 408                 /* Check to if we need less then the size of the sg_buffer */
 409                 if (sg_len < max) max = sg_len;
 410         }
 411
 412         if (max > AU1XMMC_MAX_TRANSFER)
 413                 max = AU1XMMC_MAX_TRANSFER;
 414
 415         for(count = 0; count < max; count++ ) {
 416                 u32 val;
 417                 status = au_readl(HOST_STATUS(host));
 418
 419                 if (!(status & SD_STATUS_NE))
 420                         break;
 421
 422                 if (status & SD_STATUS_RC) {
 423                         DBG("RX CRC Error [%d + %d].\n", host->id,
 424                                         host->pio.len, count);
 425                         break;
 426                 }
 427
 428                 if (status & SD_STATUS_RO) {
 429                         DBG("RX Overrun [%d + %d]\n", host->id,
 430                                         host->pio.len, count);
 431                         break;
 432                 }
 433                 else if (status & SD_STATUS_RU) {
 434                         DBG("RX Underrun [%d + %d]\n", host->id,
 435                                         host->pio.len,  count);
 436                         break;
 437                 }
 438
 439                 val = au_readl(HOST_RXPORT(host));
 440
 441                 if (sg_ptr)
 442                         *sg_ptr++ = (unsigned char) (val & 0xFF);
 443         }
 444
 445         host->pio.len -= count;
 446         host->pio.offset += count;
 447
 448         if (sg_len && count == sg_len) {
 449                 host->pio.index++;
 450                 host->pio.offset = 0;
 451         }
 452
 453         if (host->pio.len == 0) {
 454                 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
 455                 IRQ_OFF(host, SD_CONFIG_NE);
 456
 457                 if (host->flags & HOST_F_STOP)
 458                         SEND_STOP(host);
 459
 460                 tasklet_schedule(&host->data_task);
 461         }
 462 }
 463
 464 /* static void au1xmmc_cmd_complete
 465    This is called when a command has been completed - grab the response
 466    and check for errors.  Then start the data transfer if it is indicated.
 467 */
 468
 469 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 470 {
 471
 472         struct mmc_request *mrq = host->mrq;
 473         struct mmc_command *cmd;
 474         int trans;
 475
 476         if (!host->mrq)
 477                 return;
 478
 479         cmd = mrq->cmd;
 480         cmd->error = 0;
 481
 482         if (cmd->flags & MMC_RSP_PRESENT) {
 483                 if (cmd->flags & MMC_RSP_136) {
 484                         u32 r[4];
 485                         int i;
 486
 487                         r[0] = au_readl(host->iobase + SD_RESP3);
 488                         r[1] = au_readl(host->iobase + SD_RESP2);
 489                         r[2] = au_readl(host->iobase + SD_RESP1);
 490                         r[3] = au_readl(host->iobase + SD_RESP0);
 491
 492                         /* The CRC is omitted from the response, so really
 493                          * we only got 120 bytes, but the engine expects
 494                          * 128 bits, so we have to shift things up
 495                          */
 496
 497                         for(i = 0; i < 4; i++) {
 498                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 499                                 if (i != 3)
 500                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 501                         }
 502                 } else {
 503                         /* Techincally, we should be getting all 48 bits of
 504                          * the response (SD_RESP1 + SD_RESP2), but because
 505                          * our response omits the CRC, our data ends up
 506                          * being shifted 8 bits to the right.  In this case,
 507                          * that means that the OSR data starts at bit 31,
 508                          * so we can just read RESP0 and return that
 509                          */
 510                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
 511                 }
 512         }
 513
 514         /* Figure out errors */
 515
 516         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 517                 cmd->error = -EILSEQ;
 518
 519         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 520
 521         if (!trans || cmd->error) {
 522
 523                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
 524                 tasklet_schedule(&host->finish_task);
 525                 return;
 526         }
 527
 528         host->status = HOST_S_DATA;
 529
 530         if (host->flags & HOST_F_DMA) {
 531                 u32 channel = DMA_CHANNEL(host);
 532
 533                 /* Start the DMA as soon as the buffer gets something in it */
 534
 535                 if (host->flags & HOST_F_RECV) {
 536                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 537
 538                         while((status & mask) != mask)
 539                                 status = au_readl(HOST_STATUS(host));
 540                 }
 541
 542                 au1xxx_dbdma_start(channel);
 543         }
 544 }
 545
 546 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 547 {
 548
 549         unsigned int pbus = get_au1x00_speed();
 550         unsigned int divisor;
 551         u32 config;
 552
 553         /* From databook:
 554            divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
 555         */
 556
 557         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
 558         pbus /= 2;
 559
 560         divisor = ((pbus / rate) / 2) - 1;
 561
 562         config = au_readl(HOST_CONFIG(host));
 563
 564         config &= ~(SD_CONFIG_DIV);
 565         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 566
 567         au_writel(config, HOST_CONFIG(host));
 568         au_sync();
 569 }
 570
 571 static int
 572 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
 573 {
 574
 575         int datalen = data->blocks * data->blksz;
 576
 577         if (dma != 0)
 578                 host->flags |= HOST_F_DMA;
 579
 580         if (data->flags & MMC_DATA_READ)
 581                 host->flags |= HOST_F_RECV;
 582         else
 583                 host->flags |= HOST_F_XMIT;
 584
 585         if (host->mrq->stop)
 586                 host->flags |= HOST_F_STOP;
 587
 588         host->dma.dir = DMA_BIDIRECTIONAL;
 589
 590         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 591                                    data->sg_len, host->dma.dir);
 592
 593         if (host->dma.len == 0)
 594                 return -ETIMEDOUT;
 595
 596         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
 597
 598         if (host->flags & HOST_F_DMA) {
 599                 int i;
 600                 u32 channel = DMA_CHANNEL(host);
 601
 602                 au1xxx_dbdma_stop(channel);
 603
 604                 for(i = 0; i < host->dma.len; i++) {
 605                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 606                         struct scatterlist *sg = &data->sg[i];
 607                         int sg_len = sg->length;
 608
 609                         int len = (datalen > sg_len) ? sg_len : datalen;
 610
 611                         if (i == host->dma.len - 1)
 612                                 flags = DDMA_FLAGS_IE;
 613
 614                         if (host->flags & HOST_F_XMIT){
 615                                 ret = au1xxx_dbdma_put_source_flags(channel,
 616                                         (void *) sg_virt(sg), len, flags);
 617                         }
 618                         else {
 619                                 ret = au1xxx_dbdma_put_dest_flags(channel,
 620                                         (void *) sg_virt(sg),
 621                                         len, flags);
 622                         }
 623
 624                         if (!ret)
 625                                 goto dataerr;
 626
 627                         datalen -= len;
 628                 }
 629         }
 630         else {
 631                 host->pio.index = 0;
 632                 host->pio.offset = 0;
 633                 host->pio.len = datalen;
 634
 635                 if (host->flags & HOST_F_XMIT)
 636                         IRQ_ON(host, SD_CONFIG_TH);
 637                 else
 638                         IRQ_ON(host, SD_CONFIG_NE);
 639                         //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
 640         }
 641
 642         return 0;
 643
 644  dataerr:
 645         dma_unmap_sg(mmc_dev(host->mmc),data->sg,data->sg_len,host->dma.dir);
 646         return -ETIMEDOUT;
 647 }
 648
 649 /* static void au1xmmc_request
 650    This actually starts a command or data transaction
 651 */
 652
 653 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 654 {
 655
 656         struct au1xmmc_host *host = mmc_priv(mmc);
 657         unsigned int flags = 0;
 658         int ret = 0;
 659
 660         WARN_ON(irqs_disabled());
 661         WARN_ON(host->status != HOST_S_IDLE);
 662
 663         host->mrq = mrq;
 664         host->status = HOST_S_CMD;
 665
 666         bcsr->disk_leds &= ~(1 << 8);
 667
 668         if (mrq->data) {
 669                 FLUSH_FIFO(host);
 670                 flags = mrq->data->flags;
 671                 ret = au1xmmc_prepare_data(host, mrq->data);
 672         }
 673
 674         if (!ret)
 675                 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
 676
 677         if (ret) {
 678                 mrq->cmd->error = ret;
 679                 au1xmmc_finish_request(host);
 680         }
 681 }
 682
 683 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 684 {
 685
 686         /* Apply the clock */
 687         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 688         au_sync_delay(1);
 689
 690         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 691         au_sync_delay(5);
 692
 693         au_writel(~0, HOST_STATUS(host));
 694         au_sync();
 695
 696         au_writel(0, HOST_BLKSIZE(host));
 697         au_writel(0x001fffff, HOST_TIMEOUT(host));
 698         au_sync();
 699
 700         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 701         au_sync();
 702
 703         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 704         au_sync_delay(1);
 705
 706         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 707         au_sync();
 708
 709         /* Configure interrupts */
 710         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 711         au_sync();
 712 }
 713
 714
 715 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
 716 {
 717         struct au1xmmc_host *host = mmc_priv(mmc);
 718
 719         if (ios->power_mode == MMC_POWER_OFF)
 720                 au1xmmc_set_power(host, 0);
 721         else if (ios->power_mode == MMC_POWER_ON) {
 722                 au1xmmc_set_power(host, 1);
 723         }
 724
 725         if (ios->clock && ios->clock != host->clock) {
 726                 au1xmmc_set_clock(host, ios->clock);
 727                 host->clock = ios->clock;
 728         }
 729 }
 730
 731 static void au1xmmc_dma_callback(int irq, void *dev_id)
 732 {
 733         struct au1xmmc_host *host = (struct au1xmmc_host *) dev_id;
 734
 735         /* Avoid spurious interrupts */
 736
 737         if (!host->mrq)
 738                 return;
 739
 740         if (host->flags & HOST_F_STOP)
 741                 SEND_STOP(host);
 742
 743         tasklet_schedule(&host->data_task);
 744 }
 745
 746 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 747 #define STATUS_DATA_IN  (SD_STATUS_NE)
 748 #define STATUS_DATA_OUT (SD_STATUS_TH)
 749
 750 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 751 {
 752
 753         u32 status;
 754         int i, ret = 0;
 755
 756         disable_irq(AU1100_SD_IRQ);
 757
 758         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
 759                 struct au1xmmc_host * host = au1xmmc_hosts[i];
 760                 u32 handled = 1;
 761
 762                 status = au_readl(HOST_STATUS(host));
 763
 764                 if (host->mrq && (status & STATUS_TIMEOUT)) {
 765                         if (status & SD_STATUS_RAT)
 766                                 host->mrq->cmd->error = -ETIMEDOUT;
 767
 768                         else if (status & SD_STATUS_DT)
 769                                 host->mrq->data->error = -ETIMEDOUT;
 770
 771                         /* In PIO mode, interrupts might still be enabled */
 772                         IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 773
 774                         //IRQ_OFF(host, SD_CONFIG_TH|SD_CONFIG_RA|SD_CONFIG_RF);
 775                         tasklet_schedule(&host->finish_task);
 776                 }
 777 #if 0
 778                 else if (status & SD_STATUS_DD) {
 779
 780                         /* Sometimes we get a DD before a NE in PIO mode */
 781
 782                         if (!(host->flags & HOST_F_DMA) &&
 783                                         (status & SD_STATUS_NE))
 784                                 au1xmmc_receive_pio(host);
 785                         else {
 786                                 au1xmmc_data_complete(host, status);
 787                                 //tasklet_schedule(&host->data_task);
 788                         }
 789                 }
 790 #endif
 791                 else if (status & (SD_STATUS_CR)) {
 792                         if (host->status == HOST_S_CMD)
 793                                 au1xmmc_cmd_complete(host,status);
 794                 }
 795                 else if (!(host->flags & HOST_F_DMA)) {
 796                         if ((host->flags & HOST_F_XMIT) &&
 797                             (status & STATUS_DATA_OUT))
 798                                 au1xmmc_send_pio(host);
 799                         else if ((host->flags & HOST_F_RECV) &&
 800                             (status & STATUS_DATA_IN))
 801                                 au1xmmc_receive_pio(host);
 802                 }
 803                 else if (status & 0x203FBC70) {
 804                         DBG("Unhandled status %8.8x\n", host->id, status);
 805                         handled = 0;
 806                 }
 807
 808                 au_writel(status, HOST_STATUS(host));
 809                 au_sync();
 810
 811                 ret |= handled;
 812         }
 813
 814         enable_irq(AU1100_SD_IRQ);
 815         return ret;
 816 }
 817
 818 static void au1xmmc_poll_event(unsigned long arg)
 819 {
 820         struct au1xmmc_host *host = (struct au1xmmc_host *) arg;
 821
 822         int card = au1xmmc_card_inserted(host);
 823         int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
 824
 825         if (card != controller) {
 826                 host->flags &= ~HOST_F_ACTIVE;
 827                 if (card) host->flags |= HOST_F_ACTIVE;
 828                 mmc_detect_change(host->mmc, 0);
 829         }
 830
 831         if (host->mrq != NULL) {
 832                 u32 status = au_readl(HOST_STATUS(host));
 833                 DBG("PENDING - %8.8x\n", host->id, status);
 834         }
 835
 836         mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
 837 }
 838
 839 static dbdev_tab_t au1xmmc_mem_dbdev =
 840 {
 841         DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 8, 0x00000000, 0, 0
 842 };
 843
 844 static void au1xmmc_init_dma(struct au1xmmc_host *host)
 845 {
 846
 847         u32 rxchan, txchan;
 848
 849         int txid = au1xmmc_card_table[host->id].tx_devid;
 850         int rxid = au1xmmc_card_table[host->id].rx_devid;
 851
 852         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
 853            of 8 bits.  And since devices are shared, we need to create
 854            our own to avoid freaking out other devices
 855         */
 856
 857         int memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
 858
 859         txchan = au1xxx_dbdma_chan_alloc(memid, txid,
 860                                          au1xmmc_dma_callback, (void *) host);
 861
 862         rxchan = au1xxx_dbdma_chan_alloc(rxid, memid,
 863                                          au1xmmc_dma_callback, (void *) host);
 864
 865         au1xxx_dbdma_set_devwidth(txchan, 8);
 866         au1xxx_dbdma_set_devwidth(rxchan, 8);
 867
 868         au1xxx_dbdma_ring_alloc(txchan, AU1XMMC_DESCRIPTOR_COUNT);
 869         au1xxx_dbdma_ring_alloc(rxchan, AU1XMMC_DESCRIPTOR_COUNT);
 870
 871         host->tx_chan = txchan;
 872         host->rx_chan = rxchan;
 873 }
 874
 875 static const struct mmc_host_ops au1xmmc_ops = {
 876         .request        = au1xmmc_request,
 877         .set_ios        = au1xmmc_set_ios,
 878         .get_ro         = au1xmmc_card_readonly,
 879 };
 880
 881 static int __devinit au1xmmc_probe(struct platform_device *pdev)
 882 {
 883
 884         int i, ret = 0;
 885
 886         /* THe interrupt is shared among all controllers */
 887         ret = request_irq(AU1100_SD_IRQ, au1xmmc_irq, IRQF_DISABLED, "MMC", 0);
 888
 889         if (ret) {
 890                 printk(DRIVER_NAME "ERROR: Couldn't get int %d: %d\n",
 891                                 AU1100_SD_IRQ, ret);
 892                 return -ENXIO;
 893         }
 894
 895         disable_irq(AU1100_SD_IRQ);
 896
 897         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
 898                 struct mmc_host *mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 899                 struct au1xmmc_host *host = 0;
 900
 901                 if (!mmc) {
 902                         printk(DRIVER_NAME "ERROR: no mem for host %d\n", i);
 903                         au1xmmc_hosts[i] = 0;
 904                         continue;
 905                 }
 906
 907                 mmc->ops = &au1xmmc_ops;
 908
 909                 mmc->f_min =   450000;
 910                 mmc->f_max = 24000000;
 911
 912                 mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
 913                 mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
 914
 915                 mmc->max_blk_size = 2048;
 916                 mmc->max_blk_count = 512;
 917
 918                 mmc->ocr_avail = AU1XMMC_OCR;
 919
 920                 host = mmc_priv(mmc);
 921                 host->mmc = mmc;
 922
 923                 host->id = i;
 924                 host->iobase = au1xmmc_card_table[host->id].iobase;
 925                 host->clock = 0;
 926                 host->power_mode = MMC_POWER_OFF;
 927
 928                 host->flags = au1xmmc_card_inserted(host) ? HOST_F_ACTIVE : 0;
 929                 host->status = HOST_S_IDLE;
 930
 931                 init_timer(&host->timer);
 932
 933                 host->timer.function = au1xmmc_poll_event;
 934                 host->timer.data = (unsigned long) host;
 935                 host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
 936
 937                 tasklet_init(&host->data_task, au1xmmc_tasklet_data,
 938                                 (unsigned long) host);
 939
 940                 tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
 941                                 (unsigned long) host);
 942
 943                 spin_lock_init(&host->lock);
 944
 945                 if (dma != 0)
 946                         au1xmmc_init_dma(host);
 947
 948                 au1xmmc_reset_controller(host);
 949
 950                 mmc_add_host(mmc);
 951                 au1xmmc_hosts[i] = host;
 952
 953                 add_timer(&host->timer);
 954
 955                 printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X (mode=%s)\n",
 956                        host->id, host->iobase, dma ? "dma" : "pio");
 957         }
 958
 959         enable_irq(AU1100_SD_IRQ);
 960
 961         return 0;
 962 }
 963
 964 static int __devexit au1xmmc_remove(struct platform_device *pdev)
 965 {
 966
 967         int i;
 968
 969         disable_irq(AU1100_SD_IRQ);
 970
 971         for(i = 0; i < AU1XMMC_CONTROLLER_COUNT; i++) {
 972                 struct au1xmmc_host *host = au1xmmc_hosts[i];
 973                 if (!host) continue;
 974
 975                 tasklet_kill(&host->data_task);
 976                 tasklet_kill(&host->finish_task);
 977
 978                 del_timer_sync(&host->timer);
 979                 au1xmmc_set_power(host, 0);
 980
 981                 mmc_remove_host(host->mmc);
 982
 983                 au1xxx_dbdma_chan_free(host->tx_chan);
 984                 au1xxx_dbdma_chan_free(host->rx_chan);
 985
 986                 au_writel(0x0, HOST_ENABLE(host));
 987                 au_sync();
 988         }
 989
 990         free_irq(AU1100_SD_IRQ, 0);
 991         return 0;
 992 }
 993
 994 static struct platform_driver au1xmmc_driver = {
 995         .probe         = au1xmmc_probe,
 996         .remove        = au1xmmc_remove,
 997         .suspend       = NULL,
 998         .resume        = NULL,
 999         .driver        = {
1000                 .name  = DRIVER_NAME,
1001         },
1002 };
1003
1004 static int __init au1xmmc_init(void)
1005 {
1006         return platform_driver_register(&au1xmmc_driver);
1007 }
1008
1009 static void __exit au1xmmc_exit(void)
1010 {
1011         platform_driver_unregister(&au1xmmc_driver);
1012 }
1013
1014 module_init(au1xmmc_init);
1015 module_exit(au1xmmc_exit);
1016
1017 #ifdef MODULE
1018 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1019 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1020 MODULE_LICENSE("GPL");
1021 #endif
1022