drivers/mmc/host/au1xmmc.c

   1 /*
   2  * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
   3  *
   4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   5  *
   6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   7  *  the following copyright notices:
   8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
   9  *     Portions Copyright (C) 2002 Embedix, Inc
  10  *     Copyright 2002 Hewlett-Packard Company
  11
  12  *  2.6 version of this driver inspired by:
  13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14  *     All Rights Reserved.
  15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16  *     All Rights Reserved.
  17  *
  18
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 /* Why don't we use the SD controllers' carddetect feature?
  25  *
  26  * From the AU1100 MMC application guide:
  27  * If the Au1100-based design is intended to support both MultiMediaCards
  28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  30  * In doing so, a MMC card never enters SPI-mode communications,
  31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  32  * (the low to high transition will not occur).
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/init.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/mm.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/scatterlist.h>
  42 #include <linux/leds.h>
  43 #include <linux/mmc/host.h>
  44
  45 #include <asm/io.h>
  46 #include <asm/mach-au1x00/au1000.h>
  47 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  48 #include <asm/mach-au1x00/au1100_mmc.h>
  49
  50 #define DRIVER_NAME "au1xxx-mmc"
  51
  52 /* Set this to enable special debugging macros */
  53 /* #define DEBUG */
  54
  55 #ifdef DEBUG
  56 #define DBG(fmt, idx, args...)  \
  57         printk(KERN_DEBUG "au1xmmc(%d): DEBUG: " fmt, idx, ##args)
  58 #else
  59 #define DBG(fmt, idx, args...) do {} while (0)
  60 #endif
  61
  62 /* Hardware definitions */
  63 #define AU1XMMC_DESCRIPTOR_COUNT 1
  64 #define AU1XMMC_DESCRIPTOR_SIZE  2048
  65
  66 #define AU1XMMC_OCR (MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | \
  67                      MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 | \
  68                      MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36)
  69
  70 /* This gives us a hard value for the stop command that we can write directly
  71  * to the command register.
  72  */
  73 #define STOP_CMD        \
  74         (SD_CMD_RT_1B | SD_CMD_CT_7 | (0xC << SD_CMD_CI_SHIFT) | SD_CMD_GO)
  75
  76 /* This is the set of interrupts that we configure by default. */
  77 #define AU1XMMC_INTERRUPTS                              \
  78         (SD_CONFIG_SC | SD_CONFIG_DT | SD_CONFIG_RAT |  \
  79          SD_CONFIG_CR | SD_CONFIG_I)
  80
  81 /* The poll event (looking for insert/remove events runs twice a second. */
  82 #define AU1XMMC_DETECT_TIMEOUT (HZ/2)
  83
  84 struct au1xmmc_host {
  85         struct mmc_host *mmc;
  86         struct mmc_request *mrq;
  87
  88         u32 flags;
  89         u32 iobase;
  90         u32 clock;
  91         u32 bus_width;
  92         u32 power_mode;
  93
  94         int status;
  95
  96         struct {
  97                 int len;
  98                 int dir;
  99         } dma;
 100
 101         struct {
 102                 int index;
 103                 int offset;
 104                 int len;
 105         } pio;
 106
 107         u32 tx_chan;
 108         u32 rx_chan;
 109
 110         int irq;
 111
 112         struct tasklet_struct finish_task;
 113         struct tasklet_struct data_task;
 114         struct au1xmmc_platform_data *platdata;
 115         struct platform_device *pdev;
 116         struct resource *ioarea;
 117 };
 118
 119 /* Status flags used by the host structure */
 120 #define HOST_F_XMIT     0x0001
 121 #define HOST_F_RECV     0x0002
 122 #define HOST_F_DMA      0x0010
 123 #define HOST_F_ACTIVE   0x0100
 124 #define HOST_F_STOP     0x1000
 125
 126 #define HOST_S_IDLE     0x0001
 127 #define HOST_S_CMD      0x0002
 128 #define HOST_S_DATA     0x0003
 129 #define HOST_S_STOP     0x0004
 130
 131 /* Easy access macros */
 132 #define HOST_STATUS(h)  ((h)->iobase + SD_STATUS)
 133 #define HOST_CONFIG(h)  ((h)->iobase + SD_CONFIG)
 134 #define HOST_ENABLE(h)  ((h)->iobase + SD_ENABLE)
 135 #define HOST_TXPORT(h)  ((h)->iobase + SD_TXPORT)
 136 #define HOST_RXPORT(h)  ((h)->iobase + SD_RXPORT)
 137 #define HOST_CMDARG(h)  ((h)->iobase + SD_CMDARG)
 138 #define HOST_BLKSIZE(h) ((h)->iobase + SD_BLKSIZE)
 139 #define HOST_CMD(h)     ((h)->iobase + SD_CMD)
 140 #define HOST_CONFIG2(h) ((h)->iobase + SD_CONFIG2)
 141 #define HOST_TIMEOUT(h) ((h)->iobase + SD_TIMEOUT)
 142 #define HOST_DEBUG(h)   ((h)->iobase + SD_DEBUG)
 143
 144 #define DMA_CHANNEL(h)  \
 145         (((h)->flags & HOST_F_XMIT) ? (h)->tx_chan : (h)->rx_chan)
 146
 147 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
 148 {
 149         u32 val = au_readl(HOST_CONFIG(host));
 150         val |= mask;
 151         au_writel(val, HOST_CONFIG(host));
 152         au_sync();
 153 }
 154
 155 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
 156 {
 157         u32 val = au_readl(HOST_CONFIG2(host));
 158
 159         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
 160         au_sync_delay(1);
 161
 162         /* SEND_STOP will turn off clock control - this re-enables it */
 163         val &= ~SD_CONFIG2_DF;
 164
 165         au_writel(val, HOST_CONFIG2(host));
 166         au_sync();
 167 }
 168
 169 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
 170 {
 171         u32 val = au_readl(HOST_CONFIG(host));
 172         val &= ~mask;
 173         au_writel(val, HOST_CONFIG(host));
 174         au_sync();
 175 }
 176
 177 static inline void SEND_STOP(struct au1xmmc_host *host)
 178 {
 179         u32 config2;
 180
 181         WARN_ON(host->status != HOST_S_DATA);
 182         host->status = HOST_S_STOP;
 183
 184         config2 = au_readl(HOST_CONFIG2(host));
 185         au_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host));
 186         au_sync();
 187
 188         /* Send the stop commmand */
 189         au_writel(STOP_CMD, HOST_CMD(host));
 190 }
 191
 192 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 193 {
 194         if (host->platdata && host->platdata->set_power)
 195                 host->platdata->set_power(host->mmc, state);
 196 }
 197
 198 static int au1xmmc_card_inserted(struct mmc_host *mmc)
 199 {
 200         struct au1xmmc_host *host = mmc_priv(mmc);
 201
 202         if (host->platdata && host->platdata->card_inserted)
 203                 return !!host->platdata->card_inserted(host->mmc);
 204
 205         return -ENOSYS;
 206 }
 207
 208 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 209 {
 210         struct au1xmmc_host *host = mmc_priv(mmc);
 211
 212         if (host->platdata && host->platdata->card_readonly)
 213                 return !!host->platdata->card_readonly(mmc);
 214
 215         return -ENOSYS;
 216 }
 217
 218 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 219 {
 220         struct mmc_request *mrq = host->mrq;
 221
 222         host->mrq = NULL;
 223         host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
 224
 225         host->dma.len = 0;
 226         host->dma.dir = 0;
 227
 228         host->pio.index  = 0;
 229         host->pio.offset = 0;
 230         host->pio.len = 0;
 231
 232         host->status = HOST_S_IDLE;
 233
 234         mmc_request_done(host->mmc, mrq);
 235 }
 236
 237 static void au1xmmc_tasklet_finish(unsigned long param)
 238 {
 239         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 240         au1xmmc_finish_request(host);
 241 }
 242
 243 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 244                                 struct mmc_command *cmd, struct mmc_data *data)
 245 {
 246         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 247
 248         switch (mmc_resp_type(cmd)) {
 249         case MMC_RSP_NONE:
 250                 break;
 251         case MMC_RSP_R1:
 252                 mmccmd |= SD_CMD_RT_1;
 253                 break;
 254         case MMC_RSP_R1B:
 255                 mmccmd |= SD_CMD_RT_1B;
 256                 break;
 257         case MMC_RSP_R2:
 258                 mmccmd |= SD_CMD_RT_2;
 259                 break;
 260         case MMC_RSP_R3:
 261                 mmccmd |= SD_CMD_RT_3;
 262                 break;
 263         default:
 264                 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
 265                         mmc_resp_type(cmd));
 266                 return -EINVAL;
 267         }
 268
 269         if (data) {
 270                 if (data->flags & MMC_DATA_READ) {
 271                         if (data->blocks > 1)
 272                                 mmccmd |= SD_CMD_CT_4;
 273                         else
 274                                 mmccmd |= SD_CMD_CT_2;
 275                 } else if (data->flags & MMC_DATA_WRITE) {
 276                         if (data->blocks > 1)
 277                                 mmccmd |= SD_CMD_CT_3;
 278                         else
 279                                 mmccmd |= SD_CMD_CT_1;
 280                 }
 281         }
 282
 283         au_writel(cmd->arg, HOST_CMDARG(host));
 284         au_sync();
 285
 286         if (wait)
 287                 IRQ_OFF(host, SD_CONFIG_CR);
 288
 289         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 290         au_sync();
 291
 292         /* Wait for the command to go on the line */
 293         while (au_readl(HOST_CMD(host)) & SD_CMD_GO)
 294                 /* nop */;
 295
 296         /* Wait for the command to come back */
 297         if (wait) {
 298                 u32 status = au_readl(HOST_STATUS(host));
 299
 300                 while (!(status & SD_STATUS_CR))
 301                         status = au_readl(HOST_STATUS(host));
 302
 303                 /* Clear the CR status */
 304                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
 305
 306                 IRQ_ON(host, SD_CONFIG_CR);
 307         }
 308
 309         return 0;
 310 }
 311
 312 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 313 {
 314         struct mmc_request *mrq = host->mrq;
 315         struct mmc_data *data;
 316         u32 crc;
 317
 318         WARN_ON((host->status != HOST_S_DATA) && (host->status != HOST_S_STOP));
 319
 320         if (host->mrq == NULL)
 321                 return;
 322
 323         data = mrq->cmd->data;
 324
 325         if (status == 0)
 326                 status = au_readl(HOST_STATUS(host));
 327
 328         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 329         while ((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 330                 status = au_readl(HOST_STATUS(host));
 331
 332         data->error = 0;
 333         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 334
 335         /* Process any errors */
 336         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 337         if (host->flags & HOST_F_XMIT)
 338                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 339
 340         if (crc)
 341                 data->error = -EILSEQ;
 342
 343         /* Clear the CRC bits */
 344         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 345
 346         data->bytes_xfered = 0;
 347
 348         if (!data->error) {
 349                 if (host->flags & HOST_F_DMA) {
 350 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 351                         u32 chan = DMA_CHANNEL(host);
 352
 353                         chan_tab_t *c = *((chan_tab_t **)chan);
 354                         au1x_dma_chan_t *cp = c->chan_ptr;
 355                         data->bytes_xfered = cp->ddma_bytecnt;
 356 #endif
 357                 } else
 358                         data->bytes_xfered =
 359                                 (data->blocks * data->blksz) - host->pio.len;
 360         }
 361
 362         au1xmmc_finish_request(host);
 363 }
 364
 365 static void au1xmmc_tasklet_data(unsigned long param)
 366 {
 367         struct au1xmmc_host *host = (struct au1xmmc_host *)param;
 368
 369         u32 status = au_readl(HOST_STATUS(host));
 370         au1xmmc_data_complete(host, status);
 371 }
 372
 373 #define AU1XMMC_MAX_TRANSFER 8
 374
 375 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 376 {
 377         struct mmc_data *data;
 378         int sg_len, max, count;
 379         unsigned char *sg_ptr, val;
 380         u32 status;
 381         struct scatterlist *sg;
 382
 383         data = host->mrq->data;
 384
 385         if (!(host->flags & HOST_F_XMIT))
 386                 return;
 387
 388         /* This is the pointer to the data buffer */
 389         sg = &data->sg[host->pio.index];
 390         sg_ptr = sg_virt(sg) + host->pio.offset;
 391
 392         /* This is the space left inside the buffer */
 393         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 394
 395         /* Check if we need less than the size of the sg_buffer */
 396         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 397         if (max > AU1XMMC_MAX_TRANSFER)
 398                 max = AU1XMMC_MAX_TRANSFER;
 399
 400         for (count = 0; count < max; count++) {
 401                 status = au_readl(HOST_STATUS(host));
 402
 403                 if (!(status & SD_STATUS_TH))
 404                         break;
 405
 406                 val = *sg_ptr++;
 407
 408                 au_writel((unsigned long)val, HOST_TXPORT(host));
 409                 au_sync();
 410         }
 411
 412         host->pio.len -= count;
 413         host->pio.offset += count;
 414
 415         if (count == sg_len) {
 416                 host->pio.index++;
 417                 host->pio.offset = 0;
 418         }
 419
 420         if (host->pio.len == 0) {
 421                 IRQ_OFF(host, SD_CONFIG_TH);
 422
 423                 if (host->flags & HOST_F_STOP)
 424                         SEND_STOP(host);
 425
 426                 tasklet_schedule(&host->data_task);
 427         }
 428 }
 429
 430 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 431 {
 432         struct mmc_data *data;
 433         int max, count, sg_len = 0;
 434         unsigned char *sg_ptr = NULL;
 435         u32 status, val;
 436         struct scatterlist *sg;
 437
 438         data = host->mrq->data;
 439
 440         if (!(host->flags & HOST_F_RECV))
 441                 return;
 442
 443         max = host->pio.len;
 444
 445         if (host->pio.index < host->dma.len) {
 446                 sg = &data->sg[host->pio.index];
 447                 sg_ptr = sg_virt(sg) + host->pio.offset;
 448
 449                 /* This is the space left inside the buffer */
 450                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 451
 452                 /* Check if we need less than the size of the sg_buffer */
 453                 if (sg_len < max)
 454                         max = sg_len;
 455         }
 456
 457         if (max > AU1XMMC_MAX_TRANSFER)
 458                 max = AU1XMMC_MAX_TRANSFER;
 459
 460         for (count = 0; count < max; count++) {
 461                 status = au_readl(HOST_STATUS(host));
 462
 463                 if (!(status & SD_STATUS_NE))
 464                         break;
 465
 466                 if (status & SD_STATUS_RC) {
 467                         DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
 468                                         host->pio.len, count);
 469                         break;
 470                 }
 471
 472                 if (status & SD_STATUS_RO) {
 473                         DBG("RX Overrun [%d + %d]\n", host->pdev->id,
 474                                         host->pio.len, count);
 475                         break;
 476                 }
 477                 else if (status & SD_STATUS_RU) {
 478                         DBG("RX Underrun [%d + %d]\n", host->pdev->id,
 479                                         host->pio.len,  count);
 480                         break;
 481                 }
 482
 483                 val = au_readl(HOST_RXPORT(host));
 484
 485                 if (sg_ptr)
 486                         *sg_ptr++ = (unsigned char)(val & 0xFF);
 487         }
 488
 489         host->pio.len -= count;
 490         host->pio.offset += count;
 491
 492         if (sg_len && count == sg_len) {
 493                 host->pio.index++;
 494                 host->pio.offset = 0;
 495         }
 496
 497         if (host->pio.len == 0) {
 498                 /* IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 499                 IRQ_OFF(host, SD_CONFIG_NE);
 500
 501                 if (host->flags & HOST_F_STOP)
 502                         SEND_STOP(host);
 503
 504                 tasklet_schedule(&host->data_task);
 505         }
 506 }
 507
 508 /* This is called when a command has been completed - grab the response
 509  * and check for errors.  Then start the data transfer if it is indicated.
 510  */
 511 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 512 {
 513         struct mmc_request *mrq = host->mrq;
 514         struct mmc_command *cmd;
 515         u32 r[4];
 516         int i, trans;
 517
 518         if (!host->mrq)
 519                 return;
 520
 521         cmd = mrq->cmd;
 522         cmd->error = 0;
 523
 524         if (cmd->flags & MMC_RSP_PRESENT) {
 525                 if (cmd->flags & MMC_RSP_136) {
 526                         r[0] = au_readl(host->iobase + SD_RESP3);
 527                         r[1] = au_readl(host->iobase + SD_RESP2);
 528                         r[2] = au_readl(host->iobase + SD_RESP1);
 529                         r[3] = au_readl(host->iobase + SD_RESP0);
 530
 531                         /* The CRC is omitted from the response, so really
 532                          * we only got 120 bytes, but the engine expects
 533                          * 128 bits, so we have to shift things up.
 534                          */
 535                         for (i = 0; i < 4; i++) {
 536                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 537                                 if (i != 3)
 538                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 539                         }
 540                 } else {
 541                         /* Techincally, we should be getting all 48 bits of
 542                          * the response (SD_RESP1 + SD_RESP2), but because
 543                          * our response omits the CRC, our data ends up
 544                          * being shifted 8 bits to the right.  In this case,
 545                          * that means that the OSR data starts at bit 31,
 546                          * so we can just read RESP0 and return that.
 547                          */
 548                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
 549                 }
 550         }
 551
 552         /* Figure out errors */
 553         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 554                 cmd->error = -EILSEQ;
 555
 556         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 557
 558         if (!trans || cmd->error) {
 559                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF);
 560                 tasklet_schedule(&host->finish_task);
 561                 return;
 562         }
 563
 564         host->status = HOST_S_DATA;
 565
 566         if (host->flags & HOST_F_DMA) {
 567 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 568                 u32 channel = DMA_CHANNEL(host);
 569
 570                 /* Start the DMA as soon as the buffer gets something in it */
 571
 572                 if (host->flags & HOST_F_RECV) {
 573                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 574
 575                         while((status & mask) != mask)
 576                                 status = au_readl(HOST_STATUS(host));
 577                 }
 578
 579                 au1xxx_dbdma_start(channel);
 580 #endif
 581         }
 582 }
 583
 584 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 585 {
 586         unsigned int pbus = get_au1x00_speed();
 587         unsigned int divisor;
 588         u32 config;
 589
 590         /* From databook:
 591          * divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
 592          */
 593         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
 594         pbus /= 2;
 595         divisor = ((pbus / rate) / 2) - 1;
 596
 597         config = au_readl(HOST_CONFIG(host));
 598
 599         config &= ~(SD_CONFIG_DIV);
 600         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 601
 602         au_writel(config, HOST_CONFIG(host));
 603         au_sync();
 604 }
 605
 606 static int au1xmmc_prepare_data(struct au1xmmc_host *host,
 607                                 struct mmc_data *data)
 608 {
 609         int datalen = data->blocks * data->blksz;
 610
 611         if (data->flags & MMC_DATA_READ)
 612                 host->flags |= HOST_F_RECV;
 613         else
 614                 host->flags |= HOST_F_XMIT;
 615
 616         if (host->mrq->stop)
 617                 host->flags |= HOST_F_STOP;
 618
 619         host->dma.dir = DMA_BIDIRECTIONAL;
 620
 621         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 622                                    data->sg_len, host->dma.dir);
 623
 624         if (host->dma.len == 0)
 625                 return -ETIMEDOUT;
 626
 627         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
 628
 629         if (host->flags & HOST_F_DMA) {
 630 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 631                 int i;
 632                 u32 channel = DMA_CHANNEL(host);
 633
 634                 au1xxx_dbdma_stop(channel);
 635
 636                 for (i = 0; i < host->dma.len; i++) {
 637                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 638                         struct scatterlist *sg = &data->sg[i];
 639                         int sg_len = sg->length;
 640
 641                         int len = (datalen > sg_len) ? sg_len : datalen;
 642
 643                         if (i == host->dma.len - 1)
 644                                 flags = DDMA_FLAGS_IE;
 645
 646                         if (host->flags & HOST_F_XMIT) {
 647                                 ret = au1xxx_dbdma_put_source_flags(channel,
 648                                         (void *)sg_virt(sg), len, flags);
 649                         } else {
 650                                 ret = au1xxx_dbdma_put_dest_flags(channel,
 651                                         (void *)sg_virt(sg), len, flags);
 652                         }
 653
 654                         if (!ret)
 655                                 goto dataerr;
 656
 657                         datalen -= len;
 658                 }
 659 #endif
 660         } else {
 661                 host->pio.index = 0;
 662                 host->pio.offset = 0;
 663                 host->pio.len = datalen;
 664
 665                 if (host->flags & HOST_F_XMIT)
 666                         IRQ_ON(host, SD_CONFIG_TH);
 667                 else
 668                         IRQ_ON(host, SD_CONFIG_NE);
 669                         /* IRQ_ON(host, SD_CONFIG_RA | SD_CONFIG_RF); */
 670         }
 671
 672         return 0;
 673
 674 dataerr:
 675         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 676                         host->dma.dir);
 677         return -ETIMEDOUT;
 678 }
 679
 680 /* This actually starts a command or data transaction */
 681 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 682 {
 683         struct au1xmmc_host *host = mmc_priv(mmc);
 684         int ret = 0;
 685
 686         WARN_ON(irqs_disabled());
 687         WARN_ON(host->status != HOST_S_IDLE);
 688
 689         host->mrq = mrq;
 690         host->status = HOST_S_CMD;
 691
 692         /* fail request immediately if no card is present */
 693         if (0 == au1xmmc_card_inserted(mmc)) {
 694                 mrq->cmd->error = -ENOMEDIUM;
 695                 au1xmmc_finish_request(host);
 696                 return;
 697         }
 698
 699         if (mrq->data) {
 700                 FLUSH_FIFO(host);
 701                 ret = au1xmmc_prepare_data(host, mrq->data);
 702         }
 703
 704         if (!ret)
 705                 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
 706
 707         if (ret) {
 708                 mrq->cmd->error = ret;
 709                 au1xmmc_finish_request(host);
 710         }
 711 }
 712
 713 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 714 {
 715         /* Apply the clock */
 716         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 717         au_sync_delay(1);
 718
 719         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 720         au_sync_delay(5);
 721
 722         au_writel(~0, HOST_STATUS(host));
 723         au_sync();
 724
 725         au_writel(0, HOST_BLKSIZE(host));
 726         au_writel(0x001fffff, HOST_TIMEOUT(host));
 727         au_sync();
 728
 729         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 730         au_sync();
 731
 732         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 733         au_sync_delay(1);
 734
 735         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 736         au_sync();
 737
 738         /* Configure interrupts */
 739         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 740         au_sync();
 741 }
 742
 743
 744 static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 745 {
 746         struct au1xmmc_host *host = mmc_priv(mmc);
 747         u32 config2;
 748
 749         if (ios->power_mode == MMC_POWER_OFF)
 750                 au1xmmc_set_power(host, 0);
 751         else if (ios->power_mode == MMC_POWER_ON) {
 752                 au1xmmc_set_power(host, 1);
 753         }
 754
 755         if (ios->clock && ios->clock != host->clock) {
 756                 au1xmmc_set_clock(host, ios->clock);
 757                 host->clock = ios->clock;
 758         }
 759
 760         config2 = au_readl(HOST_CONFIG2(host));
 761         switch (ios->bus_width) {
 762         case MMC_BUS_WIDTH_4:
 763                 config2 |= SD_CONFIG2_WB;
 764                 break;
 765         case MMC_BUS_WIDTH_1:
 766                 config2 &= ~SD_CONFIG2_WB;
 767                 break;
 768         }
 769         au_writel(config2, HOST_CONFIG2(host));
 770         au_sync();
 771 }
 772
 773 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 774 #define STATUS_DATA_IN  (SD_STATUS_NE)
 775 #define STATUS_DATA_OUT (SD_STATUS_TH)
 776
 777 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 778 {
 779         struct au1xmmc_host *host = dev_id;
 780         u32 status;
 781
 782         status = au_readl(HOST_STATUS(host));
 783
 784         if (!(status & SD_STATUS_I))
 785                 return IRQ_NONE;        /* not ours */
 786
 787         if (status & SD_STATUS_SI)      /* SDIO */
 788                 mmc_signal_sdio_irq(host->mmc);
 789
 790         if (host->mrq && (status & STATUS_TIMEOUT)) {
 791                 if (status & SD_STATUS_RAT)
 792                         host->mrq->cmd->error = -ETIMEDOUT;
 793                 else if (status & SD_STATUS_DT)
 794                         host->mrq->data->error = -ETIMEDOUT;
 795
 796                 /* In PIO mode, interrupts might still be enabled */
 797                 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 798
 799                 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
 800                 tasklet_schedule(&host->finish_task);
 801         }
 802 #if 0
 803         else if (status & SD_STATUS_DD) {
 804                 /* Sometimes we get a DD before a NE in PIO mode */
 805                 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
 806                         au1xmmc_receive_pio(host);
 807                 else {
 808                         au1xmmc_data_complete(host, status);
 809                         /* tasklet_schedule(&host->data_task); */
 810                 }
 811         }
 812 #endif
 813         else if (status & SD_STATUS_CR) {
 814                 if (host->status == HOST_S_CMD)
 815                         au1xmmc_cmd_complete(host, status);
 816
 817         } else if (!(host->flags & HOST_F_DMA)) {
 818                 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
 819                         au1xmmc_send_pio(host);
 820                 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
 821                         au1xmmc_receive_pio(host);
 822
 823         } else if (status & 0x203F3C70) {
 824                         DBG("Unhandled status %8.8x\n", host->pdev->id,
 825                                 status);
 826         }
 827
 828         au_writel(status, HOST_STATUS(host));
 829         au_sync();
 830
 831         return IRQ_HANDLED;
 832 }
 833
 834 #ifdef CONFIG_SOC_AU1200
 835 /* 8bit memory DMA device */
 836 static dbdev_tab_t au1xmmc_mem_dbdev = {
 837         .dev_id         = DSCR_CMD0_ALWAYS,
 838         .dev_flags      = DEV_FLAGS_ANYUSE,
 839         .dev_tsize      = 0,
 840         .dev_devwidth   = 8,
 841         .dev_physaddr   = 0x00000000,
 842         .dev_intlevel   = 0,
 843         .dev_intpolarity = 0,
 844 };
 845 static int memid;
 846
 847 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
 848 {
 849         struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
 850
 851         /* Avoid spurious interrupts */
 852         if (!host->mrq)
 853                 return;
 854
 855         if (host->flags & HOST_F_STOP)
 856                 SEND_STOP(host);
 857
 858         tasklet_schedule(&host->data_task);
 859 }
 860
 861 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
 862 {
 863         struct resource *res;
 864         int txid, rxid;
 865
 866         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
 867         if (!res)
 868                 return -ENODEV;
 869         txid = res->start;
 870
 871         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
 872         if (!res)
 873                 return -ENODEV;
 874         rxid = res->start;
 875
 876         if (!memid)
 877                 return -ENODEV;
 878
 879         host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
 880                                 au1xmmc_dbdma_callback, (void *)host);
 881         if (!host->tx_chan) {
 882                 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
 883                 return -ENODEV;
 884         }
 885
 886         host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
 887                                 au1xmmc_dbdma_callback, (void *)host);
 888         if (!host->rx_chan) {
 889                 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
 890                 au1xxx_dbdma_chan_free(host->tx_chan);
 891                 return -ENODEV;
 892         }
 893
 894         au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
 895         au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
 896
 897         au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 898         au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 899
 900         /* DBDMA is good to go */
 901         host->flags |= HOST_F_DMA;
 902
 903         return 0;
 904 }
 905
 906 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
 907 {
 908         if (host->flags & HOST_F_DMA) {
 909                 host->flags &= ~HOST_F_DMA;
 910                 au1xxx_dbdma_chan_free(host->tx_chan);
 911                 au1xxx_dbdma_chan_free(host->rx_chan);
 912         }
 913 }
 914 #endif
 915
 916 static void au1xmmc_enable_sdio_irq(struct mmc_host *mmc, int en)
 917 {
 918         struct au1xmmc_host *host = mmc_priv(mmc);
 919
 920         if (en)
 921                 IRQ_ON(host, SD_CONFIG_SI);
 922         else
 923                 IRQ_OFF(host, SD_CONFIG_SI);
 924 }
 925
 926 static const struct mmc_host_ops au1xmmc_ops = {
 927         .request        = au1xmmc_request,
 928         .set_ios        = au1xmmc_set_ios,
 929         .get_ro         = au1xmmc_card_readonly,
 930         .get_cd         = au1xmmc_card_inserted,
 931         .enable_sdio_irq = au1xmmc_enable_sdio_irq,
 932 };
 933
 934 static int __devinit au1xmmc_probe(struct platform_device *pdev)
 935 {
 936         struct mmc_host *mmc;
 937         struct au1xmmc_host *host;
 938         struct resource *r;
 939         int ret;
 940
 941         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 942         if (!mmc) {
 943                 dev_err(&pdev->dev, "no memory for mmc_host\n");
 944                 ret = -ENOMEM;
 945                 goto out0;
 946         }
 947
 948         host = mmc_priv(mmc);
 949         host->mmc = mmc;
 950         host->platdata = pdev->dev.platform_data;
 951         host->pdev = pdev;
 952
 953         ret = -ENODEV;
 954         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 955         if (!r) {
 956                 dev_err(&pdev->dev, "no mmio defined\n");
 957                 goto out1;
 958         }
 959
 960         host->ioarea = request_mem_region(r->start, r->end - r->start + 1,
 961                                            pdev->name);
 962         if (!host->ioarea) {
 963                 dev_err(&pdev->dev, "mmio already in use\n");
 964                 goto out1;
 965         }
 966
 967         host->iobase = (unsigned long)ioremap(r->start, 0x3c);
 968         if (!host->iobase) {
 969                 dev_err(&pdev->dev, "cannot remap mmio\n");
 970                 goto out2;
 971         }
 972
 973         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 974         if (!r) {
 975                 dev_err(&pdev->dev, "no IRQ defined\n");
 976                 goto out3;
 977         }
 978
 979         host->irq = r->start;
 980         /* IRQ is shared among both SD controllers */
 981         ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
 982                           DRIVER_NAME, host);
 983         if (ret) {
 984                 dev_err(&pdev->dev, "cannot grab IRQ\n");
 985                 goto out3;
 986         }
 987
 988         mmc->ops = &au1xmmc_ops;
 989
 990         mmc->f_min =   450000;
 991         mmc->f_max = 24000000;
 992
 993         mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
 994         mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
 995
 996         mmc->max_blk_size = 2048;
 997         mmc->max_blk_count = 512;
 998
 999         mmc->ocr_avail = AU1XMMC_OCR;
1000         mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1001
1002         host->status = HOST_S_IDLE;
1003
1004         /* board-specific carddetect setup, if any */
1005         if (host->platdata && host->platdata->cd_setup) {
1006                 ret = host->platdata->cd_setup(mmc, 1);
1007                 if (ret) {
1008                         dev_warn(&pdev->dev, "board CD setup failed\n");
1009                         mmc->caps |= MMC_CAP_NEEDS_POLL;
1010                 }
1011         } else
1012                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1013
1014         tasklet_init(&host->data_task, au1xmmc_tasklet_data,
1015                         (unsigned long)host);
1016
1017         tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
1018                         (unsigned long)host);
1019
1020 #ifdef CONFIG_SOC_AU1200
1021         ret = au1xmmc_dbdma_init(host);
1022         if (ret)
1023                 printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n");
1024 #endif
1025
1026 #ifdef CONFIG_LEDS_CLASS
1027         if (host->platdata && host->platdata->led) {
1028                 struct led_classdev *led = host->platdata->led;
1029                 led->name = mmc_hostname(mmc);
1030                 led->brightness = LED_OFF;
1031                 led->default_trigger = mmc_hostname(mmc);
1032                 ret = led_classdev_register(mmc_dev(mmc), led);
1033                 if (ret)
1034                         goto out5;
1035         }
1036 #endif
1037
1038         au1xmmc_reset_controller(host);
1039
1040         ret = mmc_add_host(mmc);
1041         if (ret) {
1042                 dev_err(&pdev->dev, "cannot add mmc host\n");
1043                 goto out6;
1044         }
1045
1046         platform_set_drvdata(pdev, host);
1047
1048         printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1049                 " (mode=%s)\n", pdev->id, host->iobase,
1050                 host->flags & HOST_F_DMA ? "dma" : "pio");
1051
1052         return 0;       /* all ok */
1053
1054 out6:
1055 #ifdef CONFIG_LEDS_CLASS
1056         if (host->platdata && host->platdata->led)
1057                 led_classdev_unregister(host->platdata->led);
1058 out5:
1059 #endif
1060         au_writel(0, HOST_ENABLE(host));
1061         au_writel(0, HOST_CONFIG(host));
1062         au_writel(0, HOST_CONFIG2(host));
1063         au_sync();
1064
1065 #ifdef CONFIG_SOC_AU1200
1066         au1xmmc_dbdma_shutdown(host);
1067 #endif
1068
1069         tasklet_kill(&host->data_task);
1070         tasklet_kill(&host->finish_task);
1071
1072         if (host->platdata && host->platdata->cd_setup &&
1073             !(mmc->caps & MMC_CAP_NEEDS_POLL))
1074                 host->platdata->cd_setup(mmc, 0);
1075
1076         free_irq(host->irq, host);
1077 out3:
1078         iounmap((void *)host->iobase);
1079 out2:
1080         release_resource(host->ioarea);
1081         kfree(host->ioarea);
1082 out1:
1083         mmc_free_host(mmc);
1084 out0:
1085         return ret;
1086 }
1087
1088 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1089 {
1090         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1091
1092         if (host) {
1093                 mmc_remove_host(host->mmc);
1094
1095 #ifdef CONFIG_LEDS_CLASS
1096                 if (host->platdata && host->platdata->led)
1097                         led_classdev_unregister(host->platdata->led);
1098 #endif
1099
1100                 if (host->platdata && host->platdata->cd_setup &&
1101                     !(host->mmc->caps & MMC_CAP_NEEDS_POLL))
1102                         host->platdata->cd_setup(host->mmc, 0);
1103
1104                 au_writel(0, HOST_ENABLE(host));
1105                 au_writel(0, HOST_CONFIG(host));
1106                 au_writel(0, HOST_CONFIG2(host));
1107                 au_sync();
1108
1109                 tasklet_kill(&host->data_task);
1110                 tasklet_kill(&host->finish_task);
1111
1112 #ifdef CONFIG_SOC_AU1200
1113                 au1xmmc_dbdma_shutdown(host);
1114 #endif
1115                 au1xmmc_set_power(host, 0);
1116
1117                 free_irq(host->irq, host);
1118                 iounmap((void *)host->iobase);
1119                 release_resource(host->ioarea);
1120                 kfree(host->ioarea);
1121
1122                 mmc_free_host(host->mmc);
1123                 platform_set_drvdata(pdev, NULL);
1124         }
1125         return 0;
1126 }
1127
1128 #ifdef CONFIG_PM
1129 static int au1xmmc_suspend(struct platform_device *pdev, pm_message_t state)
1130 {
1131         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1132         int ret;
1133
1134         ret = mmc_suspend_host(host->mmc, state);
1135         if (ret)
1136                 return ret;
1137
1138         au_writel(0, HOST_CONFIG2(host));
1139         au_writel(0, HOST_CONFIG(host));
1140         au_writel(0xffffffff, HOST_STATUS(host));
1141         au_writel(0, HOST_ENABLE(host));
1142         au_sync();
1143
1144         return 0;
1145 }
1146
1147 static int au1xmmc_resume(struct platform_device *pdev)
1148 {
1149         struct au1xmmc_host *host = platform_get_drvdata(pdev);
1150
1151         au1xmmc_reset_controller(host);
1152
1153         return mmc_resume_host(host->mmc);
1154 }
1155 #else
1156 #define au1xmmc_suspend NULL
1157 #define au1xmmc_resume NULL
1158 #endif
1159
1160 static struct platform_driver au1xmmc_driver = {
1161         .probe         = au1xmmc_probe,
1162         .remove        = au1xmmc_remove,
1163         .suspend       = au1xmmc_suspend,
1164         .resume        = au1xmmc_resume,
1165         .driver        = {
1166                 .name  = DRIVER_NAME,
1167                 .owner = THIS_MODULE,
1168         },
1169 };
1170
1171 static int __init au1xmmc_init(void)
1172 {
1173 #ifdef CONFIG_SOC_AU1200
1174         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1175          * of 8 bits.  And since devices are shared, we need to create
1176          * our own to avoid freaking out other devices.
1177          */
1178         memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1179         if (!memid)
1180                 printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n");
1181 #endif
1182         return platform_driver_register(&au1xmmc_driver);
1183 }
1184
1185 static void __exit au1xmmc_exit(void)
1186 {
1187 #ifdef CONFIG_SOC_AU1200
1188         if (memid)
1189                 au1xxx_ddma_del_device(memid);
1190 #endif
1191         platform_driver_unregister(&au1xmmc_driver);
1192 }
1193
1194 module_init(au1xmmc_init);
1195 module_exit(au1xmmc_exit);
1196
1197 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1198 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1199 MODULE_LICENSE("GPL");
1200 MODULE_ALIAS("platform:au1xxx-mmc");