2 * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver
4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
6 * Copyright (C) 2006 Malcolm Noyes
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 This is the AT91 MCI driver that has been tested with both MMC cards
15 and SD-cards. Boards that support write protect are now supported.
16 The CCAT91SBC001 board does not support SD cards.
18 The three entry points are at91_mci_request, at91_mci_set_ios
22 This configures the device to put it into the correct mode and clock speed
26 MCI request processes the commands sent in the mmc_request structure. This
27 can consist of a processing command and a stop command in the case of
28 multiple block transfers.
30 There are three main types of request, commands, reads and writes.
32 Commands are straight forward. The command is submitted to the controller and
33 the request function returns. When the controller generates an interrupt to indicate
34 the command is finished, the response to the command are read and the mmc_request_done
35 function called to end the request.
37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
38 controller to manage the transfers.
40 A read is done from the controller directly to the scatterlist passed in from the request.
41 Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
42 swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug.
44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
46 A write is slightly different in that the bytes to write are read from the scatterlist
47 into a dma memory buffer (this is in case the source buffer should be read only). The
48 entire write buffer is then done from this single dma memory buffer.
50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
53 Gets the status of the write protect pin, if available.
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/init.h>
59 #include <linux/ioport.h>
60 #include <linux/platform_device.h>
61 #include <linux/interrupt.h>
62 #include <linux/blkdev.h>
63 #include <linux/delay.h>
64 #include <linux/err.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/clk.h>
67 #include <linux/atmel_pdc.h>
69 #include <linux/mmc/host.h>
75 #include <asm/mach/mmc.h>
76 #include <asm/arch/board.h>
77 #include <asm/arch/cpu.h>
78 #include <asm/arch/at91_mci.h>
80 #define DRIVER_NAME "at91_mci"
82 #define FL_SENT_COMMAND (1 << 0)
83 #define FL_SENT_STOP (1 << 1)
85 #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
86 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
87 | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
89 #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg))
90 #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
94 * Low level type for this driver
99 struct mmc_command *cmd;
100 struct mmc_request *request;
102 void __iomem *baseaddr;
105 struct at91_mmc_data *board;
111 * Flag indicating when the command has been sent. This is used to
112 * work out whether or not to send the stop
115 /* flag for current bus settings */
118 /* DMA buffer used for transmitting */
119 unsigned int* buffer;
120 dma_addr_t physical_address;
121 unsigned int total_length;
123 /* Latest in the scatterlist that has been enabled for transfer, but not freed */
126 /* Latest in the scatterlist that has been enabled for transfer */
129 /* Timer for timeouts */
130 struct timer_list timer;
134 * Reset the controller and restore most of the state
136 static void at91_reset_host(struct at91mci_host *host)
144 local_irq_save(flags);
145 imr = at91_mci_read(host, AT91_MCI_IMR);
147 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
149 /* save current state */
150 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
151 sdcr = at91_mci_read(host, AT91_MCI_SDCR);
152 dtor = at91_mci_read(host, AT91_MCI_DTOR);
154 /* reset the controller */
155 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
158 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
159 at91_mci_write(host, AT91_MCI_MR, mr);
160 at91_mci_write(host, AT91_MCI_SDCR, sdcr);
161 at91_mci_write(host, AT91_MCI_DTOR, dtor);
162 at91_mci_write(host, AT91_MCI_IER, imr);
164 /* make sure sdio interrupts will fire */
165 at91_mci_read(host, AT91_MCI_SR);
167 local_irq_restore(flags);
170 static void at91_timeout_timer(unsigned long data)
172 struct at91mci_host *host;
174 host = (struct at91mci_host *)data;
177 dev_err(host->mmc->parent, "Timeout waiting end of packet\n");
179 if (host->cmd && host->cmd->data) {
180 host->cmd->data->error = -ETIMEDOUT;
183 host->cmd->error = -ETIMEDOUT;
185 host->request->cmd->error = -ETIMEDOUT;
188 at91_reset_host(host);
189 mmc_request_done(host->mmc, host->request);
194 * Copy from sg to a dma block - used for transfers
196 static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
198 unsigned int len, i, size;
199 unsigned *dmabuf = host->buffer;
201 size = host->total_length;
205 * Just loop through all entries. Size might not
206 * be the entire list though so make sure that
207 * we do not transfer too much.
209 for (i = 0; i < len; i++) {
210 struct scatterlist *sg;
212 unsigned int *sgbuffer;
216 sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
217 amount = min(size, sg->length);
220 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
223 for (index = 0; index < (amount / 4); index++)
224 *dmabuf++ = swab32(sgbuffer[index]);
227 memcpy(dmabuf, sgbuffer, amount);
229 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
236 * Check that we didn't get a request to transfer
237 * more data than can fit into the SG list.
245 static void at91_mci_pre_dma_read(struct at91mci_host *host)
248 struct scatterlist *sg;
249 struct mmc_command *cmd;
250 struct mmc_data *data;
252 pr_debug("pre dma read\n");
256 pr_debug("no command\n");
262 pr_debug("no data\n");
266 for (i = 0; i < 2; i++) {
267 /* nothing left to transfer */
268 if (host->transfer_index >= data->sg_len) {
269 pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index);
273 /* Check to see if this needs filling */
275 if (at91_mci_read(host, ATMEL_PDC_RCR) != 0) {
276 pr_debug("Transfer active in current\n");
281 if (at91_mci_read(host, ATMEL_PDC_RNCR) != 0) {
282 pr_debug("Transfer active in next\n");
287 /* Setup the next transfer */
288 pr_debug("Using transfer index %d\n", host->transfer_index);
290 sg = &data->sg[host->transfer_index++];
291 pr_debug("sg = %p\n", sg);
293 sg->dma_address = dma_map_page(NULL, sg_page(sg), sg->offset, sg->length, DMA_FROM_DEVICE);
295 pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
298 at91_mci_write(host, ATMEL_PDC_RPR, sg->dma_address);
299 at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ? sg->length : sg->length / 4);
302 at91_mci_write(host, ATMEL_PDC_RNPR, sg->dma_address);
303 at91_mci_write(host, ATMEL_PDC_RNCR, (data->blksz & 0x3) ? sg->length : sg->length / 4);
307 pr_debug("pre dma read done\n");
311 * Handle after a dma read
313 static void at91_mci_post_dma_read(struct at91mci_host *host)
315 struct mmc_command *cmd;
316 struct mmc_data *data;
318 pr_debug("post dma read\n");
322 pr_debug("no command\n");
328 pr_debug("no data\n");
332 while (host->in_use_index < host->transfer_index) {
333 struct scatterlist *sg;
335 pr_debug("finishing index %d\n", host->in_use_index);
337 sg = &data->sg[host->in_use_index++];
339 pr_debug("Unmapping page %08X\n", sg->dma_address);
341 dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE);
343 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
344 unsigned int *buffer;
347 /* Swap the contents of the buffer */
348 buffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
349 pr_debug("buffer = %p, length = %d\n", buffer, sg->length);
351 for (index = 0; index < (sg->length / 4); index++)
352 buffer[index] = swab32(buffer[index]);
354 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
357 flush_dcache_page(sg_page(sg));
359 data->bytes_xfered += sg->length;
362 /* Is there another transfer to trigger? */
363 if (host->transfer_index < data->sg_len)
364 at91_mci_pre_dma_read(host);
366 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
367 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
370 pr_debug("post dma read done\n");
374 * Handle transmitted data
376 static void at91_mci_handle_transmitted(struct at91mci_host *host)
378 struct mmc_command *cmd;
379 struct mmc_data *data;
381 pr_debug("Handling the transmit\n");
383 /* Disable the transfer */
384 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
386 /* Now wait for cmd ready */
387 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
395 if (cmd->data->blocks > 1) {
396 pr_debug("multiple write : wait for BLKE...\n");
397 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE);
399 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
403 * Update bytes tranfered count during a write operation
405 static void at91_mci_update_bytes_xfered(struct at91mci_host *host)
407 struct mmc_data *data;
409 /* always deal with the effective request (and not the current cmd) */
411 if (host->request->cmd && host->request->cmd->error != 0)
414 if (host->request->data) {
415 data = host->request->data;
416 if (data->flags & MMC_DATA_WRITE) {
417 /* card is in IDLE mode now */
418 pr_debug("-> bytes_xfered %d, total_length = %d\n",
419 data->bytes_xfered, host->total_length);
420 data->bytes_xfered = host->total_length;
426 /*Handle after command sent ready*/
427 static int at91_mci_handle_cmdrdy(struct at91mci_host *host)
431 else if (!host->cmd->data) {
432 if (host->flags & FL_SENT_STOP) {
433 /*After multi block write, we must wait for NOTBUSY*/
434 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
436 } else if (host->cmd->data->flags & MMC_DATA_WRITE) {
437 /*After sendding multi-block-write command, start DMA transfer*/
438 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
439 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
442 /* command not completed, have to wait */
448 * Enable the controller
450 static void at91_mci_enable(struct at91mci_host *host)
454 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
455 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
456 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
457 mr = AT91_MCI_PDCMODE | 0x34a;
459 if (cpu_is_at91sam9260() || cpu_is_at91sam9263())
460 mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
462 at91_mci_write(host, AT91_MCI_MR, mr);
464 /* use Slot A or B (only one at same time) */
465 at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b);
469 * Disable the controller
471 static void at91_mci_disable(struct at91mci_host *host)
473 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
479 static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
481 unsigned int cmdr, mr;
482 unsigned int block_length;
483 struct mmc_data *data = cmd->data;
486 unsigned int ier = 0;
490 /* Needed for leaving busy state before CMD1 */
491 if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
492 pr_debug("Clearing timeout\n");
493 at91_mci_write(host, AT91_MCI_ARGR, 0);
494 at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
495 while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
497 pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
503 if (mmc_resp_type(cmd) == MMC_RSP_NONE)
504 cmdr |= AT91_MCI_RSPTYP_NONE;
506 /* if a response is expected then allow maximum response latancy */
507 cmdr |= AT91_MCI_MAXLAT;
508 /* set 136 bit response for R2, 48 bit response otherwise */
509 if (mmc_resp_type(cmd) == MMC_RSP_R2)
510 cmdr |= AT91_MCI_RSPTYP_136;
512 cmdr |= AT91_MCI_RSPTYP_48;
517 if ( cpu_is_at91rm9200() && (data->blksz & 0x3) ) {
518 pr_debug("Unsupported block size\n");
519 cmd->error = -EINVAL;
520 mmc_request_done(host->mmc, host->request);
524 block_length = data->blksz;
525 blocks = data->blocks;
527 /* always set data start - also set direction flag for read */
528 if (data->flags & MMC_DATA_READ)
529 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
530 else if (data->flags & MMC_DATA_WRITE)
531 cmdr |= AT91_MCI_TRCMD_START;
533 if (data->flags & MMC_DATA_STREAM)
534 cmdr |= AT91_MCI_TRTYP_STREAM;
535 if (data->blocks > 1)
536 cmdr |= AT91_MCI_TRTYP_MULTIPLE;
543 if (host->flags & FL_SENT_STOP)
544 cmdr |= AT91_MCI_TRCMD_STOP;
546 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
547 cmdr |= AT91_MCI_OPDCMD;
550 * Set the arguments and send the command
552 pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
553 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
556 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS);
557 at91_mci_write(host, ATMEL_PDC_RPR, 0);
558 at91_mci_write(host, ATMEL_PDC_RCR, 0);
559 at91_mci_write(host, ATMEL_PDC_RNPR, 0);
560 at91_mci_write(host, ATMEL_PDC_RNCR, 0);
561 at91_mci_write(host, ATMEL_PDC_TPR, 0);
562 at91_mci_write(host, ATMEL_PDC_TCR, 0);
563 at91_mci_write(host, ATMEL_PDC_TNPR, 0);
564 at91_mci_write(host, ATMEL_PDC_TNCR, 0);
565 ier = AT91_MCI_CMDRDY;
567 /* zero block length and PDC mode */
568 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
569 mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0;
570 mr |= (block_length << 16);
571 mr |= AT91_MCI_PDCMODE;
572 at91_mci_write(host, AT91_MCI_MR, mr);
574 if (!cpu_is_at91rm9200())
575 at91_mci_write(host, AT91_MCI_BLKR,
576 AT91_MCI_BLKR_BCNT(blocks) |
577 AT91_MCI_BLKR_BLKLEN(block_length));
580 * Disable the PDC controller
582 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
584 if (cmdr & AT91_MCI_TRCMD_START) {
585 data->bytes_xfered = 0;
586 host->transfer_index = 0;
587 host->in_use_index = 0;
588 if (cmdr & AT91_MCI_TRDIR) {
593 host->total_length = 0;
595 at91_mci_pre_dma_read(host);
596 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
602 host->total_length = block_length * blocks;
603 host->buffer = dma_alloc_coherent(NULL,
605 &host->physical_address, GFP_KERNEL);
607 at91_mci_sg_to_dma(host, data);
609 pr_debug("Transmitting %d bytes\n", host->total_length);
611 at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
612 at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ?
613 host->total_length : host->total_length / 4);
615 ier = AT91_MCI_CMDRDY;
621 * Send the command and then enable the PDC - not the other way round as
622 * the data sheet says
625 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
626 at91_mci_write(host, AT91_MCI_CMDR, cmdr);
628 if (cmdr & AT91_MCI_TRCMD_START) {
629 if (cmdr & AT91_MCI_TRDIR)
630 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
633 /* Enable selected interrupts */
634 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
638 * Process the next step in the request
640 static void at91_mci_process_next(struct at91mci_host *host)
642 if (!(host->flags & FL_SENT_COMMAND)) {
643 host->flags |= FL_SENT_COMMAND;
644 at91_mci_send_command(host, host->request->cmd);
646 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
647 host->flags |= FL_SENT_STOP;
648 at91_mci_send_command(host, host->request->stop);
650 del_timer(&host->timer);
651 /* the at91rm9200 mci controller hangs after some transfers,
652 * and the workaround is to reset it after each transfer.
654 if (cpu_is_at91rm9200())
655 at91_reset_host(host);
656 mmc_request_done(host->mmc, host->request);
661 * Handle a command that has been completed
663 static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status)
665 struct mmc_command *cmd = host->cmd;
666 struct mmc_data *data = cmd->data;
668 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
670 cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
671 cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
672 cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
673 cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
676 dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
680 pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n",
681 status, at91_mci_read(host, AT91_MCI_SR),
682 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
684 if (status & AT91_MCI_ERRORS) {
685 if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) {
689 if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) {
691 if (status & AT91_MCI_DTOE)
692 data->error = -ETIMEDOUT;
693 else if (status & AT91_MCI_DCRCE)
694 data->error = -EILSEQ;
697 if (status & AT91_MCI_RTOE)
698 cmd->error = -ETIMEDOUT;
699 else if (status & AT91_MCI_RCRCE)
700 cmd->error = -EILSEQ;
705 pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n",
706 cmd->error, data ? data->error : 0,
707 cmd->opcode, cmd->retries);
713 at91_mci_process_next(host);
717 * Handle an MMC request
719 static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
721 struct at91mci_host *host = mmc_priv(mmc);
725 mod_timer(&host->timer, jiffies + HZ);
727 at91_mci_process_next(host);
733 static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
736 struct at91mci_host *host = mmc_priv(mmc);
737 unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
739 host->bus_mode = ios->bus_mode;
741 if (ios->clock == 0) {
742 /* Disable the MCI controller */
743 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
747 /* Enable the MCI controller */
748 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
750 if ((at91_master_clock % (ios->clock * 2)) == 0)
751 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
753 clkdiv = (at91_master_clock / ios->clock) / 2;
755 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
756 at91_master_clock / (2 * (clkdiv + 1)));
758 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
759 pr_debug("MMC: Setting controller bus width to 4\n");
760 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
763 pr_debug("MMC: Setting controller bus width to 1\n");
764 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
767 /* Set the clock divider */
768 at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
770 /* maybe switch power to the card */
771 if (host->board->vcc_pin) {
772 switch (ios->power_mode) {
774 gpio_set_value(host->board->vcc_pin, 0);
777 gpio_set_value(host->board->vcc_pin, 1);
788 * Handle an interrupt
790 static irqreturn_t at91_mci_irq(int irq, void *devid)
792 struct at91mci_host *host = devid;
794 unsigned int int_status, int_mask;
796 int_status = at91_mci_read(host, AT91_MCI_SR);
797 int_mask = at91_mci_read(host, AT91_MCI_IMR);
799 pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
800 int_status & int_mask);
802 int_status = int_status & int_mask;
804 if (int_status & AT91_MCI_ERRORS) {
807 if (int_status & AT91_MCI_UNRE)
808 pr_debug("MMC: Underrun error\n");
809 if (int_status & AT91_MCI_OVRE)
810 pr_debug("MMC: Overrun error\n");
811 if (int_status & AT91_MCI_DTOE)
812 pr_debug("MMC: Data timeout\n");
813 if (int_status & AT91_MCI_DCRCE)
814 pr_debug("MMC: CRC error in data\n");
815 if (int_status & AT91_MCI_RTOE)
816 pr_debug("MMC: Response timeout\n");
817 if (int_status & AT91_MCI_RENDE)
818 pr_debug("MMC: Response end bit error\n");
819 if (int_status & AT91_MCI_RCRCE)
820 pr_debug("MMC: Response CRC error\n");
821 if (int_status & AT91_MCI_RDIRE)
822 pr_debug("MMC: Response direction error\n");
823 if (int_status & AT91_MCI_RINDE)
824 pr_debug("MMC: Response index error\n");
826 /* Only continue processing if no errors */
828 if (int_status & AT91_MCI_TXBUFE) {
829 pr_debug("TX buffer empty\n");
830 at91_mci_handle_transmitted(host);
833 if (int_status & AT91_MCI_ENDRX) {
835 at91_mci_post_dma_read(host);
838 if (int_status & AT91_MCI_RXBUFF) {
839 pr_debug("RX buffer full\n");
840 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
841 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
845 if (int_status & AT91_MCI_ENDTX)
846 pr_debug("Transmit has ended\n");
848 if (int_status & AT91_MCI_NOTBUSY) {
849 pr_debug("Card is ready\n");
850 at91_mci_update_bytes_xfered(host);
854 if (int_status & AT91_MCI_DTIP)
855 pr_debug("Data transfer in progress\n");
857 if (int_status & AT91_MCI_BLKE) {
858 pr_debug("Block transfer has ended\n");
859 if (host->request->data && host->request->data->blocks > 1) {
860 /* multi block write : complete multi write
861 * command and send stop */
864 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
868 if (int_status & AT91_MCI_SDIOIRQA)
869 mmc_signal_sdio_irq(host->mmc);
871 if (int_status & AT91_MCI_SDIOIRQB)
872 mmc_signal_sdio_irq(host->mmc);
874 if (int_status & AT91_MCI_TXRDY)
875 pr_debug("Ready to transmit\n");
877 if (int_status & AT91_MCI_RXRDY)
878 pr_debug("Ready to receive\n");
880 if (int_status & AT91_MCI_CMDRDY) {
881 pr_debug("Command ready\n");
882 completed = at91_mci_handle_cmdrdy(host);
887 pr_debug("Completed command\n");
888 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
889 at91_mci_completed_command(host, int_status);
891 at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
896 static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
898 struct at91mci_host *host = _host;
899 int present = !gpio_get_value(irq_to_gpio(irq));
902 * we expect this irq on both insert and remove,
903 * and use a short delay to debounce.
905 if (present != host->present) {
906 host->present = present;
907 pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
908 present ? "insert" : "remove");
910 pr_debug("****** Resetting SD-card bus width ******\n");
911 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
913 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
918 static int at91_mci_get_ro(struct mmc_host *mmc)
920 struct at91mci_host *host = mmc_priv(mmc);
922 if (host->board->wp_pin)
923 return !!gpio_get_value(host->board->wp_pin);
925 * Board doesn't support read only detection; let the mmc core
931 static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable)
933 struct at91mci_host *host = mmc_priv(mmc);
935 pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc),
936 host->board->slot_b ? 'B':'A', enable ? "enable" : "disable");
937 at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR,
938 host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA);
942 static const struct mmc_host_ops at91_mci_ops = {
943 .request = at91_mci_request,
944 .set_ios = at91_mci_set_ios,
945 .get_ro = at91_mci_get_ro,
946 .enable_sdio_irq = at91_mci_enable_sdio_irq,
950 * Probe for the device
952 static int __init at91_mci_probe(struct platform_device *pdev)
954 struct mmc_host *mmc;
955 struct at91mci_host *host;
956 struct resource *res;
959 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
963 if (!request_mem_region(res->start, res->end - res->start + 1, DRIVER_NAME))
966 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
969 dev_dbg(&pdev->dev, "couldn't allocate mmc host\n");
973 mmc->ops = &at91_mci_ops;
975 mmc->f_max = 25000000;
976 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
977 mmc->caps = MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
979 mmc->max_blk_size = 4095;
980 mmc->max_blk_count = mmc->max_req_size;
982 host = mmc_priv(mmc);
986 host->board = pdev->dev.platform_data;
987 if (host->board->wire4) {
988 if (cpu_is_at91sam9260() || cpu_is_at91sam9263())
989 mmc->caps |= MMC_CAP_4_BIT_DATA;
991 dev_warn(&pdev->dev, "4 wire bus mode not supported"
992 " - using 1 wire\n");
996 * Reserve GPIOs ... board init code makes sure these pins are set
997 * up as GPIOs with the right direction (input, except for vcc)
999 if (host->board->det_pin) {
1000 ret = gpio_request(host->board->det_pin, "mmc_detect");
1002 dev_dbg(&pdev->dev, "couldn't claim card detect pin\n");
1006 if (host->board->wp_pin) {
1007 ret = gpio_request(host->board->wp_pin, "mmc_wp");
1009 dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n");
1013 if (host->board->vcc_pin) {
1014 ret = gpio_request(host->board->vcc_pin, "mmc_vcc");
1016 dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n");
1024 host->mci_clk = clk_get(&pdev->dev, "mci_clk");
1025 if (IS_ERR(host->mci_clk)) {
1027 dev_dbg(&pdev->dev, "no mci_clk?\n");
1034 host->baseaddr = ioremap(res->start, res->end - res->start + 1);
1035 if (!host->baseaddr) {
1043 clk_enable(host->mci_clk); /* Enable the peripheral clock */
1044 at91_mci_disable(host);
1045 at91_mci_enable(host);
1048 * Allocate the MCI interrupt
1050 host->irq = platform_get_irq(pdev, 0);
1051 ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED,
1052 mmc_hostname(mmc), host);
1054 dev_dbg(&pdev->dev, "request MCI interrupt failed\n");
1058 platform_set_drvdata(pdev, mmc);
1061 * Add host to MMC layer
1063 if (host->board->det_pin) {
1064 host->present = !gpio_get_value(host->board->det_pin);
1071 setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host);
1074 * monitor card insertion/removal if we can
1076 if (host->board->det_pin) {
1077 ret = request_irq(gpio_to_irq(host->board->det_pin),
1078 at91_mmc_det_irq, 0, mmc_hostname(mmc), host);
1080 dev_warn(&pdev->dev, "request MMC detect irq failed\n");
1082 device_init_wakeup(&pdev->dev, 1);
1085 pr_debug("Added MCI driver\n");
1090 clk_disable(host->mci_clk);
1091 iounmap(host->baseaddr);
1093 clk_put(host->mci_clk);
1095 if (host->board->vcc_pin)
1096 gpio_free(host->board->vcc_pin);
1098 if (host->board->wp_pin)
1099 gpio_free(host->board->wp_pin);
1101 if (host->board->det_pin)
1102 gpio_free(host->board->det_pin);
1106 release_mem_region(res->start, res->end - res->start + 1);
1107 dev_err(&pdev->dev, "probe failed, err %d\n", ret);
1114 static int __exit at91_mci_remove(struct platform_device *pdev)
1116 struct mmc_host *mmc = platform_get_drvdata(pdev);
1117 struct at91mci_host *host;
1118 struct resource *res;
1123 host = mmc_priv(mmc);
1125 if (host->board->det_pin) {
1126 if (device_can_wakeup(&pdev->dev))
1127 free_irq(gpio_to_irq(host->board->det_pin), host);
1128 device_init_wakeup(&pdev->dev, 0);
1129 gpio_free(host->board->det_pin);
1132 at91_mci_disable(host);
1133 del_timer_sync(&host->timer);
1134 mmc_remove_host(mmc);
1135 free_irq(host->irq, host);
1137 clk_disable(host->mci_clk); /* Disable the peripheral clock */
1138 clk_put(host->mci_clk);
1140 if (host->board->vcc_pin)
1141 gpio_free(host->board->vcc_pin);
1142 if (host->board->wp_pin)
1143 gpio_free(host->board->wp_pin);
1145 iounmap(host->baseaddr);
1146 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1147 release_mem_region(res->start, res->end - res->start + 1);
1150 platform_set_drvdata(pdev, NULL);
1151 pr_debug("MCI Removed\n");
1157 static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
1159 struct mmc_host *mmc = platform_get_drvdata(pdev);
1160 struct at91mci_host *host = mmc_priv(mmc);
1163 if (host->board->det_pin && device_may_wakeup(&pdev->dev))
1164 enable_irq_wake(host->board->det_pin);
1167 ret = mmc_suspend_host(mmc, state);
1172 static int at91_mci_resume(struct platform_device *pdev)
1174 struct mmc_host *mmc = platform_get_drvdata(pdev);
1175 struct at91mci_host *host = mmc_priv(mmc);
1178 if (host->board->det_pin && device_may_wakeup(&pdev->dev))
1179 disable_irq_wake(host->board->det_pin);
1182 ret = mmc_resume_host(mmc);
1187 #define at91_mci_suspend NULL
1188 #define at91_mci_resume NULL
1191 static struct platform_driver at91_mci_driver = {
1192 .remove = __exit_p(at91_mci_remove),
1193 .suspend = at91_mci_suspend,
1194 .resume = at91_mci_resume,
1196 .name = DRIVER_NAME,
1197 .owner = THIS_MODULE,
1201 static int __init at91_mci_init(void)
1203 return platform_driver_probe(&at91_mci_driver, at91_mci_probe);
1206 static void __exit at91_mci_exit(void)
1208 platform_driver_unregister(&at91_mci_driver);
1211 module_init(at91_mci_init);
1212 module_exit(at91_mci_exit);
1214 MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
1215 MODULE_AUTHOR("Nick Randell");
1216 MODULE_LICENSE("GPL");
1217 MODULE_ALIAS("platform:at91_mci");