2 * linux/drivers/mmc/at91_mci.c - ATMEL AT91RM9200 MCI Driver
4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
6 * Copyright (C) 2006 Malcolm Noyes
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 This is the AT91RM9200 MCI driver that has been tested with both MMC cards
15 and SD-cards. Boards that support write protect are now supported.
16 The CCAT91SBC001 board does not support SD cards.
18 The three entry points are at91_mci_request, at91_mci_set_ios
22 This configures the device to put it into the correct mode and clock speed
26 MCI request processes the commands sent in the mmc_request structure. This
27 can consist of a processing command and a stop command in the case of
28 multiple block transfers.
30 There are three main types of request, commands, reads and writes.
32 Commands are straight forward. The command is submitted to the controller and
33 the request function returns. When the controller generates an interrupt to indicate
34 the command is finished, the response to the command are read and the mmc_request_done
35 function called to end the request.
37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
38 controller to manage the transfers.
40 A read is done from the controller directly to the scatterlist passed in from the request.
41 Due to a bug in the controller, when a read is completed, all the words are byte
42 swapped in the scatterlist buffers.
44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
46 A write is slightly different in that the bytes to write are read from the scatterlist
47 into a dma memory buffer (this is in case the source buffer should be read only). The
48 entire write buffer is then done from this single dma memory buffer.
50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
53 Gets the status of the write protect pin, if available.
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/init.h>
59 #include <linux/ioport.h>
60 #include <linux/platform_device.h>
61 #include <linux/interrupt.h>
62 #include <linux/blkdev.h>
63 #include <linux/delay.h>
64 #include <linux/err.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/clk.h>
68 #include <linux/mmc/host.h>
69 #include <linux/mmc/protocol.h>
73 #include <asm/mach/mmc.h>
74 #include <asm/arch/board.h>
75 #include <asm/arch/gpio.h>
76 #include <asm/arch/at91_mci.h>
77 #include <asm/arch/at91_pdc.h>
79 #define DRIVER_NAME "at91_mci"
83 static struct clk *mci_clk;
85 #define FL_SENT_COMMAND (1 << 0)
86 #define FL_SENT_STOP (1 << 1)
90 #define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg))
91 #define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
95 * Low level type for this driver
100 struct mmc_command *cmd;
101 struct mmc_request *request;
103 void __iomem *baseaddr;
105 struct at91_mmc_data *board;
109 * Flag indicating when the command has been sent. This is used to
110 * work out whether or not to send the stop
113 /* flag for current bus settings */
116 /* DMA buffer used for transmitting */
117 unsigned int* buffer;
118 dma_addr_t physical_address;
119 unsigned int total_length;
121 /* Latest in the scatterlist that has been enabled for transfer, but not freed */
124 /* Latest in the scatterlist that has been enabled for transfer */
129 * Copy from sg to a dma block - used for transfers
131 static inline void at91mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
133 unsigned int len, i, size;
134 unsigned *dmabuf = host->buffer;
136 size = host->total_length;
140 * Just loop through all entries. Size might not
141 * be the entire list though so make sure that
142 * we do not transfer too much.
144 for (i = 0; i < len; i++) {
145 struct scatterlist *sg;
148 unsigned int *sgbuffer;
152 sgbuffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
153 amount = min(size, sg->length);
157 for (index = 0; index < amount; index++)
158 *dmabuf++ = swab32(sgbuffer[index]);
160 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
167 * Check that we didn't get a request to transfer
168 * more data than can fit into the SG list.
176 static void at91mci_pre_dma_read(struct at91mci_host *host)
179 struct scatterlist *sg;
180 struct mmc_command *cmd;
181 struct mmc_data *data;
183 pr_debug("pre dma read\n");
187 pr_debug("no command\n");
193 pr_debug("no data\n");
197 for (i = 0; i < 2; i++) {
198 /* nothing left to transfer */
199 if (host->transfer_index >= data->sg_len) {
200 pr_debug("Nothing left to transfer (index = %d)\n", host->transfer_index);
204 /* Check to see if this needs filling */
206 if (at91_mci_read(host, AT91_PDC_RCR) != 0) {
207 pr_debug("Transfer active in current\n");
212 if (at91_mci_read(host, AT91_PDC_RNCR) != 0) {
213 pr_debug("Transfer active in next\n");
218 /* Setup the next transfer */
219 pr_debug("Using transfer index %d\n", host->transfer_index);
221 sg = &data->sg[host->transfer_index++];
222 pr_debug("sg = %p\n", sg);
224 sg->dma_address = dma_map_page(NULL, sg->page, sg->offset, sg->length, DMA_FROM_DEVICE);
226 pr_debug("dma address = %08X, length = %d\n", sg->dma_address, sg->length);
229 at91_mci_write(host, AT91_PDC_RPR, sg->dma_address);
230 at91_mci_write(host, AT91_PDC_RCR, sg->length / 4);
233 at91_mci_write(host, AT91_PDC_RNPR, sg->dma_address);
234 at91_mci_write(host, AT91_PDC_RNCR, sg->length / 4);
238 pr_debug("pre dma read done\n");
242 * Handle after a dma read
244 static void at91mci_post_dma_read(struct at91mci_host *host)
246 struct mmc_command *cmd;
247 struct mmc_data *data;
249 pr_debug("post dma read\n");
253 pr_debug("no command\n");
259 pr_debug("no data\n");
263 while (host->in_use_index < host->transfer_index) {
264 unsigned int *buffer;
268 struct scatterlist *sg;
270 pr_debug("finishing index %d\n", host->in_use_index);
272 sg = &data->sg[host->in_use_index++];
274 pr_debug("Unmapping page %08X\n", sg->dma_address);
276 dma_unmap_page(NULL, sg->dma_address, sg->length, DMA_FROM_DEVICE);
278 /* Swap the contents of the buffer */
279 buffer = kmap_atomic(sg->page, KM_BIO_SRC_IRQ) + sg->offset;
280 pr_debug("buffer = %p, length = %d\n", buffer, sg->length);
282 data->bytes_xfered += sg->length;
284 len = sg->length / 4;
286 for (index = 0; index < len; index++) {
287 buffer[index] = swab32(buffer[index]);
289 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
290 flush_dcache_page(sg->page);
293 /* Is there another transfer to trigger? */
294 if (host->transfer_index < data->sg_len)
295 at91mci_pre_dma_read(host);
297 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
298 at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
301 pr_debug("post dma read done\n");
305 * Handle transmitted data
307 static void at91_mci_handle_transmitted(struct at91mci_host *host)
309 struct mmc_command *cmd;
310 struct mmc_data *data;
312 pr_debug("Handling the transmit\n");
314 /* Disable the transfer */
315 at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
317 /* Now wait for cmd ready */
318 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
319 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
327 data->bytes_xfered = host->total_length;
331 * Enable the controller
333 static void at91_mci_enable(struct at91mci_host *host)
335 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
336 at91_mci_write(host, AT91_MCI_IDR, 0xFFFFFFFF);
337 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
338 at91_mci_write(host, AT91_MCI_MR, 0x834A);
339 at91_mci_write(host, AT91_MCI_SDCR, 0x0);
343 * Disable the controller
345 static void at91_mci_disable(struct at91mci_host *host)
347 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
352 * return the interrupts to enable
354 static unsigned int at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
356 unsigned int cmdr, mr;
357 unsigned int block_length;
358 struct mmc_data *data = cmd->data;
361 unsigned int ier = 0;
365 /* Not sure if this is needed */
367 if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
368 pr_debug("Clearing timeout\n");
369 at91_mci_write(host, AT91_MCI_ARGR, 0);
370 at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
371 while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
373 pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
379 if (mmc_resp_type(cmd) == MMC_RSP_NONE)
380 cmdr |= AT91_MCI_RSPTYP_NONE;
382 /* if a response is expected then allow maximum response latancy */
383 cmdr |= AT91_MCI_MAXLAT;
384 /* set 136 bit response for R2, 48 bit response otherwise */
385 if (mmc_resp_type(cmd) == MMC_RSP_R2)
386 cmdr |= AT91_MCI_RSPTYP_136;
388 cmdr |= AT91_MCI_RSPTYP_48;
392 block_length = data->blksz;
393 blocks = data->blocks;
395 /* always set data start - also set direction flag for read */
396 if (data->flags & MMC_DATA_READ)
397 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
398 else if (data->flags & MMC_DATA_WRITE)
399 cmdr |= AT91_MCI_TRCMD_START;
401 if (data->flags & MMC_DATA_STREAM)
402 cmdr |= AT91_MCI_TRTYP_STREAM;
403 if (data->flags & MMC_DATA_MULTI)
404 cmdr |= AT91_MCI_TRTYP_MULTIPLE;
411 if (cmd->opcode == MMC_STOP_TRANSMISSION)
412 cmdr |= AT91_MCI_TRCMD_STOP;
414 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
415 cmdr |= AT91_MCI_OPDCMD;
418 * Set the arguments and send the command
420 pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08lX)\n",
421 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
424 at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
425 at91_mci_write(host, AT91_PDC_RPR, 0);
426 at91_mci_write(host, AT91_PDC_RCR, 0);
427 at91_mci_write(host, AT91_PDC_RNPR, 0);
428 at91_mci_write(host, AT91_PDC_RNCR, 0);
429 at91_mci_write(host, AT91_PDC_TPR, 0);
430 at91_mci_write(host, AT91_PDC_TCR, 0);
431 at91_mci_write(host, AT91_PDC_TNPR, 0);
432 at91_mci_write(host, AT91_PDC_TNCR, 0);
434 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
435 at91_mci_write(host, AT91_MCI_CMDR, cmdr);
436 return AT91_MCI_CMDRDY;
439 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff; /* zero block length and PDC mode */
440 at91_mci_write(host, AT91_MCI_MR, mr | (block_length << 16) | AT91_MCI_PDCMODE);
443 * Disable the PDC controller
445 at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
447 if (cmdr & AT91_MCI_TRCMD_START) {
448 data->bytes_xfered = 0;
449 host->transfer_index = 0;
450 host->in_use_index = 0;
451 if (cmdr & AT91_MCI_TRDIR) {
456 host->total_length = 0;
458 at91mci_pre_dma_read(host);
459 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
465 host->total_length = block_length * blocks;
466 host->buffer = dma_alloc_coherent(NULL,
468 &host->physical_address, GFP_KERNEL);
470 at91mci_sg_to_dma(host, data);
472 pr_debug("Transmitting %d bytes\n", host->total_length);
474 at91_mci_write(host, AT91_PDC_TPR, host->physical_address);
475 at91_mci_write(host, AT91_PDC_TCR, host->total_length / 4);
476 ier = AT91_MCI_TXBUFE;
481 * Send the command and then enable the PDC - not the other way round as
482 * the data sheet says
485 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
486 at91_mci_write(host, AT91_MCI_CMDR, cmdr);
488 if (cmdr & AT91_MCI_TRCMD_START) {
489 if (cmdr & AT91_MCI_TRDIR)
490 at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_RXTEN);
492 at91_mci_write(host, AT91_PDC_PTCR, AT91_PDC_TXTEN);
498 * Wait for a command to complete
500 static void at91mci_process_command(struct at91mci_host *host, struct mmc_command *cmd)
504 ier = at91_mci_send_command(host, cmd);
506 pr_debug("setting ier to %08X\n", ier);
508 /* Stop on errors or the required value */
509 at91_mci_write(host, AT91_MCI_IER, 0xffff0000 | ier);
513 * Process the next step in the request
515 static void at91mci_process_next(struct at91mci_host *host)
517 if (!(host->flags & FL_SENT_COMMAND)) {
518 host->flags |= FL_SENT_COMMAND;
519 at91mci_process_command(host, host->request->cmd);
521 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
522 host->flags |= FL_SENT_STOP;
523 at91mci_process_command(host, host->request->stop);
526 mmc_request_done(host->mmc, host->request);
530 * Handle a command that has been completed
532 static void at91mci_completed_command(struct at91mci_host *host)
534 struct mmc_command *cmd = host->cmd;
537 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
539 cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
540 cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
541 cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
542 cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
545 dma_free_coherent(NULL, host->total_length, host->buffer, host->physical_address);
549 status = at91_mci_read(host, AT91_MCI_SR);
551 pr_debug("Status = %08X [%08X %08X %08X %08X]\n",
552 status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
554 if (status & (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE |
555 AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE |
556 AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)) {
557 if ((status & AT91_MCI_RCRCE) &&
558 ((cmd->opcode == MMC_SEND_OP_COND) || (cmd->opcode == SD_APP_OP_COND))) {
559 cmd->error = MMC_ERR_NONE;
562 if (status & (AT91_MCI_RTOE | AT91_MCI_DTOE))
563 cmd->error = MMC_ERR_TIMEOUT;
564 else if (status & (AT91_MCI_RCRCE | AT91_MCI_DCRCE))
565 cmd->error = MMC_ERR_BADCRC;
566 else if (status & (AT91_MCI_OVRE | AT91_MCI_UNRE))
567 cmd->error = MMC_ERR_FIFO;
569 cmd->error = MMC_ERR_FAILED;
571 pr_debug("Error detected and set to %d (cmd = %d, retries = %d)\n",
572 cmd->error, cmd->opcode, cmd->retries);
576 cmd->error = MMC_ERR_NONE;
578 at91mci_process_next(host);
582 * Handle an MMC request
584 static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
586 struct at91mci_host *host = mmc_priv(mmc);
590 at91mci_process_next(host);
596 static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
599 struct at91mci_host *host = mmc_priv(mmc);
600 unsigned long at91_master_clock = clk_get_rate(mci_clk);
602 host->bus_mode = ios->bus_mode;
604 if (ios->clock == 0) {
605 /* Disable the MCI controller */
606 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
610 /* Enable the MCI controller */
611 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
613 if ((at91_master_clock % (ios->clock * 2)) == 0)
614 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
616 clkdiv = (at91_master_clock / ios->clock) / 2;
618 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
619 at91_master_clock / (2 * (clkdiv + 1)));
621 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
622 pr_debug("MMC: Setting controller bus width to 4\n");
623 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
626 pr_debug("MMC: Setting controller bus width to 1\n");
627 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
630 /* Set the clock divider */
631 at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
633 /* maybe switch power to the card */
634 if (host->board->vcc_pin) {
635 switch (ios->power_mode) {
637 at91_set_gpio_output(host->board->vcc_pin, 0);
641 at91_set_gpio_output(host->board->vcc_pin, 1);
648 * Handle an interrupt
650 static irqreturn_t at91_mci_irq(int irq, void *devid)
652 struct at91mci_host *host = devid;
655 unsigned int int_status;
657 int_status = at91_mci_read(host, AT91_MCI_SR);
658 pr_debug("MCI irq: status = %08X, %08lX, %08lX\n", int_status, at91_mci_read(host, AT91_MCI_IMR),
659 int_status & at91_mci_read(host, AT91_MCI_IMR));
661 if ((int_status & at91_mci_read(host, AT91_MCI_IMR)) & 0xffff0000)
664 int_status &= at91_mci_read(host, AT91_MCI_IMR);
666 if (int_status & AT91_MCI_UNRE)
667 pr_debug("MMC: Underrun error\n");
668 if (int_status & AT91_MCI_OVRE)
669 pr_debug("MMC: Overrun error\n");
670 if (int_status & AT91_MCI_DTOE)
671 pr_debug("MMC: Data timeout\n");
672 if (int_status & AT91_MCI_DCRCE)
673 pr_debug("MMC: CRC error in data\n");
674 if (int_status & AT91_MCI_RTOE)
675 pr_debug("MMC: Response timeout\n");
676 if (int_status & AT91_MCI_RENDE)
677 pr_debug("MMC: Response end bit error\n");
678 if (int_status & AT91_MCI_RCRCE)
679 pr_debug("MMC: Response CRC error\n");
680 if (int_status & AT91_MCI_RDIRE)
681 pr_debug("MMC: Response direction error\n");
682 if (int_status & AT91_MCI_RINDE)
683 pr_debug("MMC: Response index error\n");
685 /* Only continue processing if no errors */
687 if (int_status & AT91_MCI_TXBUFE) {
688 pr_debug("TX buffer empty\n");
689 at91_mci_handle_transmitted(host);
692 if (int_status & AT91_MCI_RXBUFF) {
693 pr_debug("RX buffer full\n");
694 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);
697 if (int_status & AT91_MCI_ENDTX) {
698 pr_debug("Transmit has ended\n");
701 if (int_status & AT91_MCI_ENDRX) {
702 pr_debug("Receive has ended\n");
703 at91mci_post_dma_read(host);
706 if (int_status & AT91_MCI_NOTBUSY) {
707 pr_debug("Card is ready\n");
708 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_CMDRDY);
711 if (int_status & AT91_MCI_DTIP) {
712 pr_debug("Data transfer in progress\n");
715 if (int_status & AT91_MCI_BLKE) {
716 pr_debug("Block transfer has ended\n");
719 if (int_status & AT91_MCI_TXRDY) {
720 pr_debug("Ready to transmit\n");
723 if (int_status & AT91_MCI_RXRDY) {
724 pr_debug("Ready to receive\n");
727 if (int_status & AT91_MCI_CMDRDY) {
728 pr_debug("Command ready\n");
732 at91_mci_write(host, AT91_MCI_IDR, int_status);
735 pr_debug("Completed command\n");
736 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
737 at91mci_completed_command(host);
743 static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
745 struct at91mci_host *host = _host;
746 int present = !at91_get_gpio_value(irq);
749 * we expect this irq on both insert and remove,
750 * and use a short delay to debounce.
752 if (present != host->present) {
753 host->present = present;
754 pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
755 present ? "insert" : "remove");
757 pr_debug("****** Resetting SD-card bus width ******\n");
758 at91_mci_write(host, AT91_MCI_SDCR, 0);
760 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
765 int at91_mci_get_ro(struct mmc_host *mmc)
768 struct at91mci_host *host = mmc_priv(mmc);
770 if (host->board->wp_pin) {
771 read_only = at91_get_gpio_value(host->board->wp_pin);
772 printk(KERN_WARNING "%s: card is %s\n", mmc_hostname(mmc),
773 (read_only ? "read-only" : "read-write") );
776 printk(KERN_WARNING "%s: host does not support reading read-only "
777 "switch. Assuming write-enable.\n", mmc_hostname(mmc));
782 static const struct mmc_host_ops at91_mci_ops = {
783 .request = at91_mci_request,
784 .set_ios = at91_mci_set_ios,
785 .get_ro = at91_mci_get_ro,
789 * Probe for the device
791 static int at91_mci_probe(struct platform_device *pdev)
793 struct mmc_host *mmc;
794 struct at91mci_host *host;
797 pr_debug("Probe MCI devices\n");
799 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
801 pr_debug("Failed to allocate mmc host\n");
805 mmc->ops = &at91_mci_ops;
807 mmc->f_max = 25000000;
808 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
809 mmc->caps = MMC_CAP_BYTEBLOCK;
811 host = mmc_priv(mmc);
815 host->board = pdev->dev.platform_data;
816 if (host->board->wire4) {
818 mmc->caps |= MMC_CAP_4_BIT_DATA;
820 printk("MMC: 4 wire bus mode not supported by this driver - using 1 wire\n");
827 mci_clk = clk_get(&pdev->dev, "mci_clk");
828 if (IS_ERR(mci_clk)) {
829 printk(KERN_ERR "AT91 MMC: no clock defined.\n");
833 clk_enable(mci_clk); /* Enable the peripheral clock */
835 host->baseaddr = (void __iomem *)AT91_VA_BASE_MCI;
840 at91_mci_disable(host);
841 at91_mci_enable(host);
844 * Allocate the MCI interrupt
846 ret = request_irq(AT91RM9200_ID_MCI, at91_mci_irq, IRQF_SHARED, DRIVER_NAME, host);
848 printk(KERN_ERR "Failed to request MCI interrupt\n");
849 clk_disable(mci_clk);
855 platform_set_drvdata(pdev, mmc);
858 * Add host to MMC layer
860 if (host->board->det_pin)
861 host->present = !at91_get_gpio_value(host->board->det_pin);
868 * monitor card insertion/removal if we can
870 if (host->board->det_pin) {
871 ret = request_irq(host->board->det_pin, at91_mmc_det_irq,
872 0, DRIVER_NAME, host);
874 printk(KERN_ERR "couldn't allocate MMC detect irq\n");
877 pr_debug(KERN_INFO "Added MCI driver\n");
885 static int at91_mci_remove(struct platform_device *pdev)
887 struct mmc_host *mmc = platform_get_drvdata(pdev);
888 struct at91mci_host *host;
893 host = mmc_priv(mmc);
895 if (host->present != -1) {
896 free_irq(host->board->det_pin, host);
897 cancel_delayed_work(&host->mmc->detect);
900 mmc_remove_host(mmc);
901 at91_mci_disable(host);
902 free_irq(AT91RM9200_ID_MCI, host);
905 clk_disable(mci_clk); /* Disable the peripheral clock */
908 platform_set_drvdata(pdev, NULL);
910 pr_debug("MCI Removed\n");
916 static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
918 struct mmc_host *mmc = platform_get_drvdata(pdev);
922 ret = mmc_suspend_host(mmc, state);
927 static int at91_mci_resume(struct platform_device *pdev)
929 struct mmc_host *mmc = platform_get_drvdata(pdev);
933 ret = mmc_resume_host(mmc);
938 #define at91_mci_suspend NULL
939 #define at91_mci_resume NULL
942 static struct platform_driver at91_mci_driver = {
943 .probe = at91_mci_probe,
944 .remove = at91_mci_remove,
945 .suspend = at91_mci_suspend,
946 .resume = at91_mci_resume,
949 .owner = THIS_MODULE,
953 static int __init at91_mci_init(void)
955 return platform_driver_register(&at91_mci_driver);
958 static void __exit at91_mci_exit(void)
960 platform_driver_unregister(&at91_mci_driver);
963 module_init(at91_mci_init);
964 module_exit(at91_mci_exit);
966 MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
967 MODULE_AUTHOR("Nick Randell");
968 MODULE_LICENSE("GPL");