2 * Copyright 2009 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
5 * loosely based on an earlier driver that has
6 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
8 * This program is free software; you can redistribute it and/or modify it under
9 * the terms of the GNU General Public License version 2 as published by the
10 * Free Software Foundation.
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/spi/spi.h>
15 #include <linux/mfd/core.h>
16 #include <linux/mfd/mc13783-private.h>
18 #define MC13783_IRQSTAT0 0
19 #define MC13783_IRQSTAT0_ADCDONEI (1 << 0)
20 #define MC13783_IRQSTAT0_ADCBISDONEI (1 << 1)
21 #define MC13783_IRQSTAT0_TSI (1 << 2)
22 #define MC13783_IRQSTAT0_WHIGHI (1 << 3)
23 #define MC13783_IRQSTAT0_WLOWI (1 << 4)
24 #define MC13783_IRQSTAT0_CHGDETI (1 << 6)
25 #define MC13783_IRQSTAT0_CHGOVI (1 << 7)
26 #define MC13783_IRQSTAT0_CHGREVI (1 << 8)
27 #define MC13783_IRQSTAT0_CHGSHORTI (1 << 9)
28 #define MC13783_IRQSTAT0_CCCVI (1 << 10)
29 #define MC13783_IRQSTAT0_CHGCURRI (1 << 11)
30 #define MC13783_IRQSTAT0_BPONI (1 << 12)
31 #define MC13783_IRQSTAT0_LOBATLI (1 << 13)
32 #define MC13783_IRQSTAT0_LOBATHI (1 << 14)
33 #define MC13783_IRQSTAT0_UDPI (1 << 15)
34 #define MC13783_IRQSTAT0_USBI (1 << 16)
35 #define MC13783_IRQSTAT0_IDI (1 << 19)
36 #define MC13783_IRQSTAT0_SE1I (1 << 21)
37 #define MC13783_IRQSTAT0_CKDETI (1 << 22)
38 #define MC13783_IRQSTAT0_UDMI (1 << 23)
40 #define MC13783_IRQMASK0 1
41 #define MC13783_IRQMASK0_ADCDONEM MC13783_IRQSTAT0_ADCDONEI
42 #define MC13783_IRQMASK0_ADCBISDONEM MC13783_IRQSTAT0_ADCBISDONEI
43 #define MC13783_IRQMASK0_TSM MC13783_IRQSTAT0_TSI
44 #define MC13783_IRQMASK0_WHIGHM MC13783_IRQSTAT0_WHIGHI
45 #define MC13783_IRQMASK0_WLOWM MC13783_IRQSTAT0_WLOWI
46 #define MC13783_IRQMASK0_CHGDETM MC13783_IRQSTAT0_CHGDETI
47 #define MC13783_IRQMASK0_CHGOVM MC13783_IRQSTAT0_CHGOVI
48 #define MC13783_IRQMASK0_CHGREVM MC13783_IRQSTAT0_CHGREVI
49 #define MC13783_IRQMASK0_CHGSHORTM MC13783_IRQSTAT0_CHGSHORTI
50 #define MC13783_IRQMASK0_CCCVM MC13783_IRQSTAT0_CCCVI
51 #define MC13783_IRQMASK0_CHGCURRM MC13783_IRQSTAT0_CHGCURRI
52 #define MC13783_IRQMASK0_BPONM MC13783_IRQSTAT0_BPONI
53 #define MC13783_IRQMASK0_LOBATLM MC13783_IRQSTAT0_LOBATLI
54 #define MC13783_IRQMASK0_LOBATHM MC13783_IRQSTAT0_LOBATHI
55 #define MC13783_IRQMASK0_UDPM MC13783_IRQSTAT0_UDPI
56 #define MC13783_IRQMASK0_USBM MC13783_IRQSTAT0_USBI
57 #define MC13783_IRQMASK0_IDM MC13783_IRQSTAT0_IDI
58 #define MC13783_IRQMASK0_SE1M MC13783_IRQSTAT0_SE1I
59 #define MC13783_IRQMASK0_CKDETM MC13783_IRQSTAT0_CKDETI
60 #define MC13783_IRQMASK0_UDMM MC13783_IRQSTAT0_UDMI
62 #define MC13783_IRQSTAT1 3
63 #define MC13783_IRQSTAT1_1HZI (1 << 0)
64 #define MC13783_IRQSTAT1_TODAI (1 << 1)
65 #define MC13783_IRQSTAT1_ONOFD1I (1 << 3)
66 #define MC13783_IRQSTAT1_ONOFD2I (1 << 4)
67 #define MC13783_IRQSTAT1_ONOFD3I (1 << 5)
68 #define MC13783_IRQSTAT1_SYSRSTI (1 << 6)
69 #define MC13783_IRQSTAT1_RTCRSTI (1 << 7)
70 #define MC13783_IRQSTAT1_PCI (1 << 8)
71 #define MC13783_IRQSTAT1_WARMI (1 << 9)
72 #define MC13783_IRQSTAT1_MEMHLDI (1 << 10)
73 #define MC13783_IRQSTAT1_PWRRDYI (1 << 11)
74 #define MC13783_IRQSTAT1_THWARNLI (1 << 12)
75 #define MC13783_IRQSTAT1_THWARNHI (1 << 13)
76 #define MC13783_IRQSTAT1_CLKI (1 << 14)
77 #define MC13783_IRQSTAT1_SEMAFI (1 << 15)
78 #define MC13783_IRQSTAT1_MC2BI (1 << 17)
79 #define MC13783_IRQSTAT1_HSDETI (1 << 18)
80 #define MC13783_IRQSTAT1_HSLI (1 << 19)
81 #define MC13783_IRQSTAT1_ALSPTHI (1 << 20)
82 #define MC13783_IRQSTAT1_AHSSHORTI (1 << 21)
84 #define MC13783_IRQMASK1 4
85 #define MC13783_IRQMASK1_1HZM MC13783_IRQSTAT1_1HZI
86 #define MC13783_IRQMASK1_TODAM MC13783_IRQSTAT1_TODAI
87 #define MC13783_IRQMASK1_ONOFD1M MC13783_IRQSTAT1_ONOFD1I
88 #define MC13783_IRQMASK1_ONOFD2M MC13783_IRQSTAT1_ONOFD2I
89 #define MC13783_IRQMASK1_ONOFD3M MC13783_IRQSTAT1_ONOFD3I
90 #define MC13783_IRQMASK1_SYSRSTM MC13783_IRQSTAT1_SYSRSTI
91 #define MC13783_IRQMASK1_RTCRSTM MC13783_IRQSTAT1_RTCRSTI
92 #define MC13783_IRQMASK1_PCM MC13783_IRQSTAT1_PCI
93 #define MC13783_IRQMASK1_WARMM MC13783_IRQSTAT1_WARMI
94 #define MC13783_IRQMASK1_MEMHLDM MC13783_IRQSTAT1_MEMHLDI
95 #define MC13783_IRQMASK1_PWRRDYM MC13783_IRQSTAT1_PWRRDYI
96 #define MC13783_IRQMASK1_THWARNLM MC13783_IRQSTAT1_THWARNLI
97 #define MC13783_IRQMASK1_THWARNHM MC13783_IRQSTAT1_THWARNHI
98 #define MC13783_IRQMASK1_CLKM MC13783_IRQSTAT1_CLKI
99 #define MC13783_IRQMASK1_SEMAFM MC13783_IRQSTAT1_SEMAFI
100 #define MC13783_IRQMASK1_MC2BM MC13783_IRQSTAT1_MC2BI
101 #define MC13783_IRQMASK1_HSDETM MC13783_IRQSTAT1_HSDETI
102 #define MC13783_IRQMASK1_HSLM MC13783_IRQSTAT1_HSLI
103 #define MC13783_IRQMASK1_ALSPTHM MC13783_IRQSTAT1_ALSPTHI
104 #define MC13783_IRQMASK1_AHSSHORTM MC13783_IRQSTAT1_AHSSHORTI
106 #define MC13783_ADC1 44
107 #define MC13783_ADC1_ADEN (1 << 0)
108 #define MC13783_ADC1_RAND (1 << 1)
109 #define MC13783_ADC1_ADSEL (1 << 3)
110 #define MC13783_ADC1_ASC (1 << 20)
111 #define MC13783_ADC1_ADTRIGIGN (1 << 21)
113 #define MC13783_NUMREGS 0x3f
115 void mc13783_lock(struct mc13783 *mc13783)
117 if (!mutex_trylock(&mc13783->lock)) {
118 dev_dbg(&mc13783->spidev->dev, "wait for %s from %pf\n",
119 __func__, __builtin_return_address(0));
121 mutex_lock(&mc13783->lock);
123 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
124 __func__, __builtin_return_address(0));
126 EXPORT_SYMBOL(mc13783_lock);
128 void mc13783_unlock(struct mc13783 *mc13783)
130 dev_dbg(&mc13783->spidev->dev, "%s from %pf\n",
131 __func__, __builtin_return_address(0));
132 mutex_unlock(&mc13783->lock);
134 EXPORT_SYMBOL(mc13783_unlock);
136 #define MC13783_REGOFFSET_SHIFT 25
137 int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val)
139 struct spi_transfer t;
140 struct spi_message m;
143 BUG_ON(!mutex_is_locked(&mc13783->lock));
145 if (offset > MC13783_NUMREGS)
148 *val = offset << MC13783_REGOFFSET_SHIFT;
150 memset(&t, 0, sizeof(t));
156 spi_message_init(&m);
157 spi_message_add_tail(&t, &m);
159 ret = spi_sync(mc13783->spidev, &m);
161 /* error in message.status implies error return from spi_sync */
162 BUG_ON(!ret && m.status);
169 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
173 EXPORT_SYMBOL(mc13783_reg_read);
175 int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val)
178 struct spi_transfer t;
179 struct spi_message m;
182 BUG_ON(!mutex_is_locked(&mc13783->lock));
184 dev_vdbg(&mc13783->spidev->dev, "[0x%02x] <- 0x%06x\n", offset, val);
186 if (offset > MC13783_NUMREGS || val > 0xffffff)
189 buf = 1 << 31 | offset << MC13783_REGOFFSET_SHIFT | val;
191 memset(&t, 0, sizeof(t));
197 spi_message_init(&m);
198 spi_message_add_tail(&t, &m);
200 ret = spi_sync(mc13783->spidev, &m);
202 BUG_ON(!ret && m.status);
209 EXPORT_SYMBOL(mc13783_reg_write);
211 int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
219 ret = mc13783_reg_read(mc13783, offset, &valread);
223 valread = (valread & ~mask) | val;
225 return mc13783_reg_write(mc13783, offset, valread);
227 EXPORT_SYMBOL(mc13783_reg_rmw);
229 int mc13783_get_flags(struct mc13783 *mc13783)
231 return mc13783->flags;
233 EXPORT_SYMBOL(mc13783_get_flags);
235 int mc13783_irq_mask(struct mc13783 *mc13783, int irq)
238 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
239 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
242 if (irq < 0 || irq >= MC13783_NUM_IRQ)
245 ret = mc13783_reg_read(mc13783, offmask, &mask);
253 return mc13783_reg_write(mc13783, offmask, mask | irqbit);
255 EXPORT_SYMBOL(mc13783_irq_mask);
257 int mc13783_irq_unmask(struct mc13783 *mc13783, int irq)
260 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
261 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
264 if (irq < 0 || irq >= MC13783_NUM_IRQ)
267 ret = mc13783_reg_read(mc13783, offmask, &mask);
271 if (!(mask & irqbit))
272 /* already unmasked */
275 return mc13783_reg_write(mc13783, offmask, mask & ~irqbit);
277 EXPORT_SYMBOL(mc13783_irq_unmask);
279 int mc13783_irq_status(struct mc13783 *mc13783, int irq,
280 int *enabled, int *pending)
283 unsigned int offmask = irq < 24 ? MC13783_IRQMASK0 : MC13783_IRQMASK1;
284 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
285 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
287 if (irq < 0 || irq >= MC13783_NUM_IRQ)
293 ret = mc13783_reg_read(mc13783, offmask, &mask);
297 *enabled = mask & irqbit;
303 ret = mc13783_reg_read(mc13783, offstat, &stat);
307 *pending = stat & irqbit;
312 EXPORT_SYMBOL(mc13783_irq_status);
314 int mc13783_irq_ack(struct mc13783 *mc13783, int irq)
316 unsigned int offstat = irq < 24 ? MC13783_IRQSTAT0 : MC13783_IRQSTAT1;
317 unsigned int val = 1 << (irq < 24 ? irq : irq - 24);
319 BUG_ON(irq < 0 || irq >= MC13783_NUM_IRQ);
321 return mc13783_reg_write(mc13783, offstat, val);
323 EXPORT_SYMBOL(mc13783_irq_ack);
325 int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
326 irq_handler_t handler, const char *name, void *dev)
328 BUG_ON(!mutex_is_locked(&mc13783->lock));
331 if (irq < 0 || irq >= MC13783_NUM_IRQ)
334 if (mc13783->irqhandler[irq])
337 mc13783->irqhandler[irq] = handler;
338 mc13783->irqdata[irq] = dev;
342 EXPORT_SYMBOL(mc13783_irq_request_nounmask);
344 int mc13783_irq_request(struct mc13783 *mc13783, int irq,
345 irq_handler_t handler, const char *name, void *dev)
349 ret = mc13783_irq_request_nounmask(mc13783, irq, handler, name, dev);
353 ret = mc13783_irq_unmask(mc13783, irq);
355 mc13783->irqhandler[irq] = NULL;
356 mc13783->irqdata[irq] = NULL;
362 EXPORT_SYMBOL(mc13783_irq_request);
364 int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev)
367 BUG_ON(!mutex_is_locked(&mc13783->lock));
369 if (irq < 0 || irq >= MC13783_NUM_IRQ || !mc13783->irqhandler[irq] ||
370 mc13783->irqdata[irq] != dev)
373 ret = mc13783_irq_mask(mc13783, irq);
377 mc13783->irqhandler[irq] = NULL;
378 mc13783->irqdata[irq] = NULL;
382 EXPORT_SYMBOL(mc13783_irq_free);
384 static inline irqreturn_t mc13783_irqhandler(struct mc13783 *mc13783, int irq)
386 return mc13783->irqhandler[irq](irq, mc13783->irqdata[irq]);
390 * returns: number of handled irqs or negative error
391 * locking: holds mc13783->lock
393 static int mc13783_irq_handle(struct mc13783 *mc13783,
394 unsigned int offstat, unsigned int offmask, int baseirq)
397 int ret = mc13783_reg_read(mc13783, offstat, &stat);
403 ret = mc13783_reg_read(mc13783, offmask, &mask);
407 while (stat & ~mask) {
408 int irq = __ffs(stat & ~mask);
412 if (likely(mc13783->irqhandler[baseirq + irq])) {
415 handled = mc13783_irqhandler(mc13783, baseirq + irq);
416 if (handled == IRQ_HANDLED)
419 dev_err(&mc13783->spidev->dev,
420 "BUG: irq %u but no handler\n",
425 ret = mc13783_reg_write(mc13783, offmask, mask);
432 static irqreturn_t mc13783_irq_thread(int irq, void *data)
434 struct mc13783 *mc13783 = data;
438 mc13783_lock(mc13783);
440 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT0,
441 MC13783_IRQMASK0, MC13783_IRQ_ADCDONE);
445 ret = mc13783_irq_handle(mc13783, MC13783_IRQSTAT1,
446 MC13783_IRQMASK1, MC13783_IRQ_1HZ);
450 mc13783_unlock(mc13783);
452 return IRQ_RETVAL(handled);
455 #define MC13783_ADC1_CHAN0_SHIFT 5
456 #define MC13783_ADC1_CHAN1_SHIFT 8
458 struct mc13783_adcdone_data {
459 struct mc13783 *mc13783;
460 struct completion done;
463 static irqreturn_t mc13783_handler_adcdone(int irq, void *data)
465 struct mc13783_adcdone_data *adcdone_data = data;
467 mc13783_irq_ack(adcdone_data->mc13783, irq);
469 complete_all(&adcdone_data->done);
474 #define MC13783_ADC_WORKING (1 << 16)
476 int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
477 unsigned int channel, unsigned int *sample)
479 u32 adc0, adc1, old_adc0;
481 struct mc13783_adcdone_data adcdone_data = {
484 init_completion(&adcdone_data.done);
486 dev_dbg(&mc13783->spidev->dev, "%s\n", __func__);
488 mc13783_lock(mc13783);
490 if (mc13783->flags & MC13783_ADC_WORKING) {
495 mc13783->flags |= MC13783_ADC_WORKING;
497 mc13783_reg_read(mc13783, MC13783_ADC0, &old_adc0);
499 adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
500 adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN | MC13783_ADC1_ASC;
503 adc1 |= MC13783_ADC1_ADSEL;
506 case MC13783_ADC_MODE_TS:
507 adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_TSMOD0 |
509 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
512 case MC13783_ADC_MODE_SINGLE_CHAN:
513 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
514 adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
515 adc1 |= MC13783_ADC1_RAND;
518 case MC13783_ADC_MODE_MULT_CHAN:
519 adc0 |= old_adc0 & MC13783_ADC0_TSMOD_MASK;
520 adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
524 mc13783_unlock(mc13783);
528 dev_dbg(&mc13783->spidev->dev, "%s: request irq\n", __func__);
529 mc13783_irq_request(mc13783, MC13783_IRQ_ADCDONE,
530 mc13783_handler_adcdone, __func__, &adcdone_data);
531 mc13783_irq_ack(mc13783, MC13783_IRQ_ADCDONE);
533 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, adc0);
534 mc13783_reg_write(mc13783, MC13783_REG_ADC_1, adc1);
536 mc13783_unlock(mc13783);
538 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
543 mc13783_lock(mc13783);
545 mc13783_irq_free(mc13783, MC13783_IRQ_ADCDONE, &adcdone_data);
548 for (i = 0; i < 4; ++i) {
549 ret = mc13783_reg_read(mc13783,
550 MC13783_REG_ADC_2, &sample[i]);
555 if (mode == MC13783_ADC_MODE_TS)
557 mc13783_reg_write(mc13783, MC13783_REG_ADC_0, old_adc0);
559 mc13783->flags &= ~MC13783_ADC_WORKING;
561 mc13783_unlock(mc13783);
565 EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
567 static int mc13783_add_subdevice_pdata(struct mc13783 *mc13783,
568 const char *name, void *pdata, size_t pdata_size)
570 struct mfd_cell cell = {
572 .platform_data = pdata,
573 .data_size = pdata_size,
576 return mfd_add_devices(&mc13783->spidev->dev, -1, &cell, 1, NULL, 0);
579 static int mc13783_add_subdevice(struct mc13783 *mc13783, const char *name)
581 return mc13783_add_subdevice_pdata(mc13783, name, NULL, 0);
584 static int mc13783_check_revision(struct mc13783 *mc13783)
586 u32 rev_id, rev1, rev2, finid, icid;
588 mc13783_reg_read(mc13783, MC13783_REG_REVISION, &rev_id);
590 rev1 = (rev_id & 0x018) >> 3;
591 rev2 = (rev_id & 0x007);
592 icid = (rev_id & 0x01C0) >> 6;
593 finid = (rev_id & 0x01E00) >> 9;
595 /* Ver 0.2 is actually 3.2a. Report as 3.2 */
596 if ((rev1 == 0) && (rev2 == 2))
599 if (rev1 == 0 || icid != 2) {
600 dev_err(&mc13783->spidev->dev, "No MC13783 detected.\n");
604 dev_info(&mc13783->spidev->dev,
605 "MC13783 Rev %d.%d FinVer %x detected\n",
611 static int mc13783_probe(struct spi_device *spi)
613 struct mc13783 *mc13783;
614 struct mc13783_platform_data *pdata = dev_get_platdata(&spi->dev);
617 mc13783 = kzalloc(sizeof(*mc13783), GFP_KERNEL);
621 dev_set_drvdata(&spi->dev, mc13783);
622 spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
623 spi->bits_per_word = 32;
626 mc13783->spidev = spi;
628 mutex_init(&mc13783->lock);
629 mc13783_lock(mc13783);
631 ret = mc13783_check_revision(mc13783);
636 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK0, 0x00ffffff);
640 ret = mc13783_reg_write(mc13783, MC13783_IRQMASK1, 0x00ffffff);
644 ret = request_threaded_irq(spi->irq, NULL, mc13783_irq_thread,
645 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, "mc13783", mc13783);
650 mutex_unlock(&mc13783->lock);
651 dev_set_drvdata(&spi->dev, NULL);
656 /* This should go away (BEGIN) */
658 mc13783->flags = pdata->flags;
659 mc13783->regulators = pdata->regulators;
660 mc13783->num_regulators = pdata->num_regulators;
662 /* This should go away (END) */
664 mc13783_unlock(mc13783);
666 if (pdata->flags & MC13783_USE_ADC)
667 mc13783_add_subdevice(mc13783, "mc13783-adc");
669 if (pdata->flags & MC13783_USE_CODEC)
670 mc13783_add_subdevice(mc13783, "mc13783-codec");
672 if (pdata->flags & MC13783_USE_REGULATOR) {
673 struct mc13783_regulator_platform_data regulator_pdata = {
674 .num_regulators = pdata->num_regulators,
675 .regulators = pdata->regulators,
678 mc13783_add_subdevice_pdata(mc13783, "mc13783-regulator",
679 ®ulator_pdata, sizeof(regulator_pdata));
682 if (pdata->flags & MC13783_USE_RTC)
683 mc13783_add_subdevice(mc13783, "mc13783-rtc");
685 if (pdata->flags & MC13783_USE_TOUCHSCREEN)
686 mc13783_add_subdevice(mc13783, "mc13783-ts");
688 if (pdata->flags & MC13783_USE_LED)
689 mc13783_add_subdevice_pdata(mc13783, "mc13783-led",
690 pdata->leds, sizeof(*pdata->leds));
695 static int __devexit mc13783_remove(struct spi_device *spi)
697 struct mc13783 *mc13783 = dev_get_drvdata(&spi->dev);
699 free_irq(mc13783->spidev->irq, mc13783);
701 mfd_remove_devices(&spi->dev);
706 static struct spi_driver mc13783_driver = {
709 .bus = &spi_bus_type,
710 .owner = THIS_MODULE,
712 .probe = mc13783_probe,
713 .remove = __devexit_p(mc13783_remove),
716 static int __init mc13783_init(void)
718 return spi_register_driver(&mc13783_driver);
720 subsys_initcall(mc13783_init);
722 static void __exit mc13783_exit(void)
724 spi_unregister_driver(&mc13783_driver);
726 module_exit(mc13783_exit);
728 MODULE_DESCRIPTION("Core driver for Freescale MC13783 PMIC");
729 MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
730 MODULE_LICENSE("GPL v2");