4 * Compaq ASIC3 support.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
12 * Copyright 2007-2008 OpenedHand Ltd.
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
19 #include <linux/kernel.h>
20 #include <linux/irq.h>
21 #include <linux/gpio.h>
23 #include <linux/spinlock.h>
24 #include <linux/platform_device.h>
26 #include <linux/mfd/asic3.h>
49 #define INIT_CDEX(_name, _rate) \
50 [ASIC3_CLOCK_##_name] = { \
51 .cdex = CLOCK_CDEX_##_name, \
55 struct asic3_clk asic3_clk_init[] __initdata = {
57 INIT_CDEX(OWM, 5000000),
63 INIT_CDEX(SD_HOST, 24576000),
64 INIT_CDEX(SD_BUS, 12288000),
66 INIT_CDEX(EX0, 32768),
67 INIT_CDEX(EX1, 24576000),
71 void __iomem *mapping;
72 unsigned int bus_shift;
74 unsigned int irq_base;
77 struct gpio_chip gpio;
80 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
83 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
85 static inline void asic3_write_register(struct asic3 *asic,
86 unsigned int reg, u32 value)
88 iowrite16(value, asic->mapping +
89 (reg >> asic->bus_shift));
92 static inline u32 asic3_read_register(struct asic3 *asic,
95 return ioread16(asic->mapping +
96 (reg >> asic->bus_shift));
99 void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
104 spin_lock_irqsave(&asic->lock, flags);
105 val = asic3_read_register(asic, reg);
110 asic3_write_register(asic, reg, val);
111 spin_unlock_irqrestore(&asic->lock, flags);
115 #define MAX_ASIC_ISR_LOOPS 20
116 #define ASIC3_GPIO_BASE_INCR \
117 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
119 static void asic3_irq_flip_edge(struct asic3 *asic,
125 spin_lock_irqsave(&asic->lock, flags);
126 edge = asic3_read_register(asic,
127 base + ASIC3_GPIO_EDGE_TRIGGER);
129 asic3_write_register(asic,
130 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
131 spin_unlock_irqrestore(&asic->lock, flags);
134 static void asic3_irq_demux(unsigned int irq, struct irq_desc *desc)
140 desc->chip->ack(irq);
142 asic = desc->handler_data;
144 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
148 spin_lock_irqsave(&asic->lock, flags);
149 status = asic3_read_register(asic,
150 ASIC3_OFFSET(INTR, P_INT_STAT));
151 spin_unlock_irqrestore(&asic->lock, flags);
153 /* Check all ten register bits */
154 if ((status & 0x3ff) == 0)
157 /* Handle GPIO IRQs */
158 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
159 if (status & (1 << bank)) {
160 unsigned long base, istat;
162 base = ASIC3_GPIO_A_BASE
163 + bank * ASIC3_GPIO_BASE_INCR;
165 spin_lock_irqsave(&asic->lock, flags);
166 istat = asic3_read_register(asic,
168 ASIC3_GPIO_INT_STATUS);
169 /* Clearing IntStatus */
170 asic3_write_register(asic,
172 ASIC3_GPIO_INT_STATUS, 0);
173 spin_unlock_irqrestore(&asic->lock, flags);
175 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
182 irqnr = asic->irq_base +
183 (ASIC3_GPIOS_PER_BANK * bank)
185 desc = irq_to_desc(irqnr);
186 desc->handle_irq(irqnr, desc);
187 if (asic->irq_bothedge[bank] & bit)
188 asic3_irq_flip_edge(asic, base,
194 /* Handle remaining IRQs in the status register */
195 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
196 /* They start at bit 4 and go up */
197 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4))) {
198 desc = irq_to_desc(asic->irq_base + i);
199 desc->handle_irq(asic->irq_base + i,
205 if (iter >= MAX_ASIC_ISR_LOOPS)
206 dev_err(asic->dev, "interrupt processing overrun\n");
209 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
213 n = (irq - asic->irq_base) >> 4;
215 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
218 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
220 return (irq - asic->irq_base) & 0xf;
223 static void asic3_mask_gpio_irq(unsigned int irq)
225 struct asic3 *asic = get_irq_chip_data(irq);
226 u32 val, bank, index;
229 bank = asic3_irq_to_bank(asic, irq);
230 index = asic3_irq_to_index(asic, irq);
232 spin_lock_irqsave(&asic->lock, flags);
233 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
235 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
236 spin_unlock_irqrestore(&asic->lock, flags);
239 static void asic3_mask_irq(unsigned int irq)
241 struct asic3 *asic = get_irq_chip_data(irq);
245 spin_lock_irqsave(&asic->lock, flags);
246 regval = asic3_read_register(asic,
248 ASIC3_INTR_INT_MASK);
250 regval &= ~(ASIC3_INTMASK_MASK0 <<
251 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
253 asic3_write_register(asic,
257 spin_unlock_irqrestore(&asic->lock, flags);
260 static void asic3_unmask_gpio_irq(unsigned int irq)
262 struct asic3 *asic = get_irq_chip_data(irq);
263 u32 val, bank, index;
266 bank = asic3_irq_to_bank(asic, irq);
267 index = asic3_irq_to_index(asic, irq);
269 spin_lock_irqsave(&asic->lock, flags);
270 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
271 val &= ~(1 << index);
272 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
273 spin_unlock_irqrestore(&asic->lock, flags);
276 static void asic3_unmask_irq(unsigned int irq)
278 struct asic3 *asic = get_irq_chip_data(irq);
282 spin_lock_irqsave(&asic->lock, flags);
283 regval = asic3_read_register(asic,
285 ASIC3_INTR_INT_MASK);
287 regval |= (ASIC3_INTMASK_MASK0 <<
288 (irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
290 asic3_write_register(asic,
294 spin_unlock_irqrestore(&asic->lock, flags);
297 static int asic3_gpio_irq_type(unsigned int irq, unsigned int type)
299 struct asic3 *asic = get_irq_chip_data(irq);
301 u16 trigger, level, edge, bit;
304 bank = asic3_irq_to_bank(asic, irq);
305 index = asic3_irq_to_index(asic, irq);
308 spin_lock_irqsave(&asic->lock, flags);
309 level = asic3_read_register(asic,
310 bank + ASIC3_GPIO_LEVEL_TRIGGER);
311 edge = asic3_read_register(asic,
312 bank + ASIC3_GPIO_EDGE_TRIGGER);
313 trigger = asic3_read_register(asic,
314 bank + ASIC3_GPIO_TRIGGER_TYPE);
315 asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit;
317 if (type == IRQ_TYPE_EDGE_RISING) {
320 } else if (type == IRQ_TYPE_EDGE_FALLING) {
323 } else if (type == IRQ_TYPE_EDGE_BOTH) {
325 if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base))
329 asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit;
330 } else if (type == IRQ_TYPE_LEVEL_LOW) {
333 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
338 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
339 * be careful to not unmask them if mask was also called.
340 * Probably need internal state for mask.
342 dev_notice(asic->dev, "irq type not changed\n");
344 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
346 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
348 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
350 spin_unlock_irqrestore(&asic->lock, flags);
354 static struct irq_chip asic3_gpio_irq_chip = {
355 .name = "ASIC3-GPIO",
356 .ack = asic3_mask_gpio_irq,
357 .mask = asic3_mask_gpio_irq,
358 .unmask = asic3_unmask_gpio_irq,
359 .set_type = asic3_gpio_irq_type,
362 static struct irq_chip asic3_irq_chip = {
364 .ack = asic3_mask_irq,
365 .mask = asic3_mask_irq,
366 .unmask = asic3_unmask_irq,
369 static int __init asic3_irq_probe(struct platform_device *pdev)
371 struct asic3 *asic = platform_get_drvdata(pdev);
372 unsigned long clksel = 0;
373 unsigned int irq, irq_base;
376 ret = platform_get_irq(pdev, 0);
381 /* turn on clock to IRQ controller */
382 clksel |= CLOCK_SEL_CX;
383 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
386 irq_base = asic->irq_base;
388 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
389 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
390 set_irq_chip(irq, &asic3_gpio_irq_chip);
392 set_irq_chip(irq, &asic3_irq_chip);
394 set_irq_chip_data(irq, asic);
395 set_irq_handler(irq, handle_level_irq);
396 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
399 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
400 ASIC3_INTMASK_GINTMASK);
402 set_irq_chained_handler(asic->irq_nr, asic3_irq_demux);
403 set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
404 set_irq_data(asic->irq_nr, asic);
409 static void asic3_irq_remove(struct platform_device *pdev)
411 struct asic3 *asic = platform_get_drvdata(pdev);
412 unsigned int irq, irq_base;
414 irq_base = asic->irq_base;
416 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
417 set_irq_flags(irq, 0);
418 set_irq_handler(irq, NULL);
419 set_irq_chip(irq, NULL);
420 set_irq_chip_data(irq, NULL);
422 set_irq_chained_handler(asic->irq_nr, NULL);
426 static int asic3_gpio_direction(struct gpio_chip *chip,
427 unsigned offset, int out)
429 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
430 unsigned int gpio_base;
434 asic = container_of(chip, struct asic3, gpio);
435 gpio_base = ASIC3_GPIO_TO_BASE(offset);
437 if (gpio_base > ASIC3_GPIO_D_BASE) {
438 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
443 spin_lock_irqsave(&asic->lock, flags);
445 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
447 /* Input is 0, Output is 1 */
453 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
455 spin_unlock_irqrestore(&asic->lock, flags);
461 static int asic3_gpio_direction_input(struct gpio_chip *chip,
464 return asic3_gpio_direction(chip, offset, 0);
467 static int asic3_gpio_direction_output(struct gpio_chip *chip,
468 unsigned offset, int value)
470 return asic3_gpio_direction(chip, offset, 1);
473 static int asic3_gpio_get(struct gpio_chip *chip,
476 unsigned int gpio_base;
477 u32 mask = ASIC3_GPIO_TO_MASK(offset);
480 asic = container_of(chip, struct asic3, gpio);
481 gpio_base = ASIC3_GPIO_TO_BASE(offset);
483 if (gpio_base > ASIC3_GPIO_D_BASE) {
484 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
489 return asic3_read_register(asic, gpio_base + ASIC3_GPIO_STATUS) & mask;
492 static void asic3_gpio_set(struct gpio_chip *chip,
493 unsigned offset, int value)
496 unsigned int gpio_base;
500 asic = container_of(chip, struct asic3, gpio);
501 gpio_base = ASIC3_GPIO_TO_BASE(offset);
503 if (gpio_base > ASIC3_GPIO_D_BASE) {
504 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
509 mask = ASIC3_GPIO_TO_MASK(offset);
511 spin_lock_irqsave(&asic->lock, flags);
513 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
520 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
522 spin_unlock_irqrestore(&asic->lock, flags);
527 static __init int asic3_gpio_probe(struct platform_device *pdev,
528 u16 *gpio_config, int num)
530 struct asic3 *asic = platform_get_drvdata(pdev);
531 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
532 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
533 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
536 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
537 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
538 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
540 /* Enable all GPIOs */
541 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
542 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
543 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
544 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
546 for (i = 0; i < num; i++) {
547 u8 alt, pin, dir, init, bank_num, bit_num;
548 u16 config = gpio_config[i];
550 pin = ASIC3_CONFIG_GPIO_PIN(config);
551 alt = ASIC3_CONFIG_GPIO_ALT(config);
552 dir = ASIC3_CONFIG_GPIO_DIR(config);
553 init = ASIC3_CONFIG_GPIO_INIT(config);
555 bank_num = ASIC3_GPIO_TO_BANK(pin);
556 bit_num = ASIC3_GPIO_TO_BIT(pin);
558 alt_reg[bank_num] |= (alt << bit_num);
559 out_reg[bank_num] |= (init << bit_num);
560 dir_reg[bank_num] |= (dir << bit_num);
563 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
564 asic3_write_register(asic,
565 ASIC3_BANK_TO_BASE(i) +
566 ASIC3_GPIO_DIRECTION,
568 asic3_write_register(asic,
569 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
571 asic3_write_register(asic,
572 ASIC3_BANK_TO_BASE(i) +
573 ASIC3_GPIO_ALT_FUNCTION,
577 return gpiochip_add(&asic->gpio);
580 static int asic3_gpio_remove(struct platform_device *pdev)
582 struct asic3 *asic = platform_get_drvdata(pdev);
584 return gpiochip_remove(&asic->gpio);
587 static int asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
592 spin_lock_irqsave(&asic->lock, flags);
593 if (clk->enabled++ == 0) {
594 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
596 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
598 spin_unlock_irqrestore(&asic->lock, flags);
603 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
608 WARN_ON(clk->enabled == 0);
610 spin_lock_irqsave(&asic->lock, flags);
611 if (--clk->enabled == 0) {
612 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
614 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
616 spin_unlock_irqrestore(&asic->lock, flags);
620 static int __init asic3_probe(struct platform_device *pdev)
622 struct asic3_platform_data *pdata = pdev->dev.platform_data;
624 struct resource *mem;
625 unsigned long clksel;
629 asic = kzalloc(sizeof(struct asic3), GFP_KERNEL);
631 printk(KERN_ERR "kzalloc failed\n");
635 spin_lock_init(&asic->lock);
636 platform_set_drvdata(pdev, asic);
637 asic->dev = &pdev->dev;
639 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
642 dev_err(asic->dev, "no MEM resource\n");
646 map_size = mem->end - mem->start + 1;
647 asic->mapping = ioremap(mem->start, map_size);
648 if (!asic->mapping) {
650 dev_err(asic->dev, "Couldn't ioremap\n");
654 asic->irq_base = pdata->irq_base;
656 /* calculate bus shift from mem resource */
657 asic->bus_shift = 2 - (map_size >> 12);
660 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
662 ret = asic3_irq_probe(pdev);
664 dev_err(asic->dev, "Couldn't probe IRQs\n");
668 asic->gpio.base = pdata->gpio_base;
669 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
670 asic->gpio.get = asic3_gpio_get;
671 asic->gpio.set = asic3_gpio_set;
672 asic->gpio.direction_input = asic3_gpio_direction_input;
673 asic->gpio.direction_output = asic3_gpio_direction_output;
675 ret = asic3_gpio_probe(pdev,
677 pdata->gpio_config_num);
679 dev_err(asic->dev, "GPIO probe failed\n");
683 /* Making a per-device copy is only needed for the
684 * theoretical case of multiple ASIC3s on one board:
686 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
688 dev_info(asic->dev, "ASIC3 Core driver\n");
693 asic3_irq_remove(pdev);
696 iounmap(asic->mapping);
704 static int asic3_remove(struct platform_device *pdev)
707 struct asic3 *asic = platform_get_drvdata(pdev);
709 ret = asic3_gpio_remove(pdev);
712 asic3_irq_remove(pdev);
714 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
716 iounmap(asic->mapping);
723 static void asic3_shutdown(struct platform_device *pdev)
727 static struct platform_driver asic3_device_driver = {
731 .remove = __devexit_p(asic3_remove),
732 .shutdown = asic3_shutdown,
735 static int __init asic3_init(void)
738 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
742 subsys_initcall(asic3_init);