2 * Copyright (c) 2010 Samsung Electronics
4 * Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 #include <linux/types.h>
15 #include <media/videobuf-core.h>
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-mem2mem.h>
18 #include <linux/videodev2.h>
19 #include "regs-fimc.h"
21 #define err(fmt, args...) \
22 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
25 #define dbg(fmt, args...) \
26 printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
28 #define dbg(fmt, args...)
31 #define NUM_FIMC_CLOCKS 2
32 #define MODULE_NAME "s5p-fimc"
33 #define FIMC_MAX_DEVS 3
34 #define FIMC_MAX_OUT_BUFS 4
35 #define SCALER_MAX_HRATIO 64
36 #define SCALER_MAX_VRATIO 64
44 #define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
45 #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
67 S5P_FIMC_YCBCR444_LOCAL,
68 S5P_FIMC_MAX_COLOR = S5P_FIMC_YCBCR444_LOCAL,
69 S5P_FIMC_COLOR_MASK = 0x0F,
72 /* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats. */
73 #define S5P_FIMC_OUT_CRYCBY S5P_CIOCTRL_ORDER422_CRYCBY
74 #define S5P_FIMC_OUT_CBYCRY S5P_CIOCTRL_ORDER422_YCRYCB
75 #define S5P_FIMC_OUT_YCRYCB S5P_CIOCTRL_ORDER422_CBYCRY
76 #define S5P_FIMC_OUT_YCBYCR S5P_CIOCTRL_ORDER422_YCBYCR
78 /* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats. */
79 #define S5P_FIMC_IN_CRYCBY S5P_MSCTRL_ORDER422_CRYCBY
80 #define S5P_FIMC_IN_CBYCRY S5P_MSCTRL_ORDER422_YCRYCB
81 #define S5P_FIMC_IN_YCRYCB S5P_MSCTRL_ORDER422_CBYCRY
82 #define S5P_FIMC_IN_YCBYCR S5P_MSCTRL_ORDER422_YCBYCR
84 /* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
85 #define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
87 /* The embedded image effect selection */
88 #define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
89 #define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
90 #define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
91 #define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
92 #define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
93 #define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
95 /* The hardware context state. */
96 #define FIMC_PARAMS (1 << 0)
97 #define FIMC_SRC_ADDR (1 << 1)
98 #define FIMC_DST_ADDR (1 << 2)
99 #define FIMC_SRC_FMT (1 << 3)
100 #define FIMC_DST_FMT (1 << 4)
102 /* Image conversion flags */
103 #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
104 #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
105 #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
106 #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
107 #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
108 #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
109 /* YCbCr data dynamic range for RGB-YUV color conversion. Y/Cb/Cr: (0 ~ 255) */
110 #define FIMC_COLOR_RANGE_WIDE (0 << 3)
111 /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
112 #define FIMC_COLOR_RANGE_NARROW (1 << 3)
115 #define FLIP_X_AXIS 1
116 #define FLIP_Y_AXIS 2
117 #define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
120 * struct fimc_fmt - the driver's internal color format data
121 * @name: format description
122 * @fourcc: the fourcc code for this format
123 * @color: the corresponding fimc_color_fmt
124 * @depth: number of bits per pixel
125 * @buff_cnt: number of physically non-contiguous data planes
126 * @planes_cnt: number of physically contiguous data planes
138 * struct fimc_dma_offset - pixel offset information for DMA
139 * @y_h: y value horizontal offset
140 * @y_v: y value vertical offset
141 * @cb_h: cb value horizontal offset
142 * @cb_v: cb value vertical offset
143 * @cr_h: cr value horizontal offset
144 * @cr_v: cr value vertical offset
146 struct fimc_dma_offset {
156 * struct fimc_effect - the configuration data for the "Arbitrary" image effect
158 * @pat_cb: cr value when type is "arbitrary"
159 * @pat_cr: cr value when type is "arbitrary"
168 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
170 * @enabled: the flag set when the scaler is used
171 * @hfactor: horizontal shift factor
172 * @vfactor: vertical shift factor
173 * @pre_hratio: horizontal ratio of the prescaler
174 * @pre_vratio: vertical ratio of the prescaler
175 * @pre_dst_width: the prescaler's destination width
176 * @pre_dst_height: the prescaler's destination height
177 * @scaleup_h: flag indicating scaling up horizontally
178 * @scaleup_v: flag indicating scaling up vertically
179 * @main_hratio: the main scaler's horizontal ratio
180 * @main_vratio: the main scaler's vertical ratio
181 * @real_width: source width - offset
182 * @real_height: source height - offset
183 * @copy_mode: flag set if one-to-one mode is used, i.e. no scaling
184 * and color format conversion
204 * struct fimc_addr - the FIMC physical address set for DMA
206 * @y: luminance plane physical address
207 * @cb: Cb plane physical address
208 * @cr: Cr plane physical address
217 * struct fimc_vid_buffer - the driver's video buffer
218 * @vb: v4l videobuf buffer
220 struct fimc_vid_buffer {
221 struct videobuf_buffer vb;
225 * struct fimc_frame - input/output frame format properties
227 * @f_width: image full width (virtual screen size)
228 * @f_height: image full height (virtual screen size)
229 * @o_width: original image width as set by S_FMT
230 * @o_height: original image height as set by S_FMT
231 * @offs_h: image horizontal pixel offset
232 * @offs_v: image vertical pixel offset
233 * @width: image pixel width
234 * @height: image pixel weight
235 * @paddr: image frame buffer physical addresses
236 * @buf_cnt: number of buffers depending on a color format
237 * @size: image size in bytes
238 * @color: color format
239 * @dma_offset: DMA offset in bytes
251 struct fimc_addr paddr;
252 struct fimc_dma_offset dma_offset;
253 struct fimc_fmt *fmt;
257 * struct fimc_m2m_device - v4l2 memory-to-memory device data
258 * @vfd: the video device node for v4l2 m2m mode
259 * @v4l2_dev: v4l2 device for m2m mode
260 * @m2m_dev: v4l2 memory-to-memory device data
261 * @ctx: hardware context data
262 * @refcnt: the reference counter
264 struct fimc_m2m_device {
265 struct video_device *vfd;
266 struct v4l2_device v4l2_dev;
267 struct v4l2_m2m_dev *m2m_dev;
268 struct fimc_ctx *ctx;
273 * struct samsung_fimc_variant - camera interface variant information
275 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
276 * @has_inp_rot: set if has input rotator
277 * @has_out_rot: set if has output rotator
278 * @min_inp_pixsize: minimum input pixel size
279 * @min_out_pixsize: minimum output pixel size
280 * @scaler_en_w: maximum input pixel width when the scaler is enabled
281 * @scaler_dis_w: maximum input pixel width when the scaler is disabled
282 * @in_rot_en_h: maximum input width when the input rotator is used
283 * @in_rot_dis_w: maximum input width when the input rotator is used
284 * @out_rot_en_w: maximum output width for the output rotator enabled
285 * @out_rot_dis_w: maximum output width for the output rotator enabled
287 struct samsung_fimc_variant {
288 unsigned int pix_hoff:1;
289 unsigned int has_inp_rot:1;
290 unsigned int has_out_rot:1;
303 * struct samsung_fimc_driverdata - per-device type driver data for init time.
305 * @variant: the variant information for this driver.
306 * @dev_cnt: number of fimc sub-devices available in SoC
308 struct samsung_fimc_driverdata {
309 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
316 * struct fimc_subdev - abstraction for a FIMC entity
318 * @slock: the spinlock protecting this data structure
319 * @lock: the mutex protecting this data structure
320 * @pdev: pointer to the FIMC platform device
321 * @id: FIMC device index (0..2)
322 * @clock[]: the clocks required for FIMC operation
323 * @regs: the mapped hardware registers
324 * @regs_res: the resource claimed for IO registers
325 * @irq: interrupt number of the FIMC subdevice
326 * @irqlock: spinlock protecting videbuffer queue
327 * @m2m: memory-to-memory V4L2 device information
328 * @state: the FIMC device state flags
333 struct platform_device *pdev;
334 struct samsung_fimc_variant *variant;
336 struct clk *clock[NUM_FIMC_CLOCKS];
338 struct resource *regs_res;
341 struct workqueue_struct *work_queue;
342 struct fimc_m2m_device m2m;
347 * fimc_ctx - the device context data
349 * @lock: mutex protecting this data structure
350 * @s_frame: source frame properties
351 * @d_frame: destination frame properties
352 * @out_order_1p: output 1-plane YCBCR order
353 * @out_order_2p: output 2-plane YCBCR order
354 * @in_order_1p input 1-plane YCBCR order
355 * @in_order_2p: input 2-plane YCBCR order
356 * @in_path: input mode (DMA or camera)
357 * @out_path: output mode (DMA or FIFO)
358 * @scaler: image scaler properties
359 * @effect: image effect
360 * @rotation: image clockwise rotation in degrees
361 * @flip: image flip mode
362 * @flags: an additional flags for image conversion
363 * @state: flags to keep track of user configuration
364 * @fimc_dev: the FIMC device this context applies to
365 * @m2m_ctx: memory-to-memory device context
369 struct fimc_frame s_frame;
370 struct fimc_frame d_frame;
375 enum fimc_datapath in_path;
376 enum fimc_datapath out_path;
377 struct fimc_scaler scaler;
378 struct fimc_effect effect;
383 struct fimc_dev *fimc_dev;
384 struct v4l2_m2m_ctx *m2m_ctx;
388 static inline int tiled_fmt(struct fimc_fmt *fmt)
393 static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
395 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
396 cfg |= S5P_CIGCTRL_IRQ_CLR;
397 writel(cfg, dev->regs + S5P_CIGCTRL);
400 static inline void fimc_hw_start_scaler(struct fimc_dev *dev)
402 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
403 cfg |= S5P_CISCCTRL_SCALERSTART;
404 writel(cfg, dev->regs + S5P_CISCCTRL);
407 static inline void fimc_hw_stop_scaler(struct fimc_dev *dev)
409 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
410 cfg &= ~S5P_CISCCTRL_SCALERSTART;
411 writel(cfg, dev->regs + S5P_CISCCTRL);
414 static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
416 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
417 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
418 writel(cfg, dev->regs + S5P_CIIMGCPT);
421 static inline void fimc_hw_start_in_dma(struct fimc_dev *dev)
423 u32 cfg = readl(dev->regs + S5P_MSCTRL);
424 cfg |= S5P_MSCTRL_ENVID;
425 writel(cfg, dev->regs + S5P_MSCTRL);
428 static inline void fimc_hw_stop_in_dma(struct fimc_dev *dev)
430 u32 cfg = readl(dev->regs + S5P_MSCTRL);
431 cfg &= ~S5P_MSCTRL_ENVID;
432 writel(cfg, dev->regs + S5P_MSCTRL);
435 static inline struct fimc_frame *ctx_m2m_get_frame(struct fimc_ctx *ctx,
436 enum v4l2_buf_type type)
438 struct fimc_frame *frame;
440 if (V4L2_BUF_TYPE_VIDEO_OUTPUT == type) {
441 frame = &ctx->s_frame;
442 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == type) {
443 frame = &ctx->d_frame;
445 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
446 "Wrong buffer/video queue type (%d)\n", type);
447 return ERR_PTR(-EINVAL);
453 /* -----------------------------------------------------*/
455 void fimc_hw_reset(struct fimc_dev *dev);
456 void fimc_hw_set_rotation(struct fimc_ctx *ctx);
457 void fimc_hw_set_target_format(struct fimc_ctx *ctx);
458 void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
459 void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable);
460 void fimc_hw_en_irq(struct fimc_dev *dev, int enable);
461 void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
462 void fimc_hw_set_scaler(struct fimc_ctx *ctx);
463 void fimc_hw_en_capture(struct fimc_ctx *ctx);
464 void fimc_hw_set_effect(struct fimc_ctx *ctx);
465 void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
466 void fimc_hw_set_input_path(struct fimc_ctx *ctx);
467 void fimc_hw_set_output_path(struct fimc_ctx *ctx);
468 void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
469 void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
471 #endif /* FIMC_CORE_H_ */