drivers/media/video/omap3isp/ispreg.h

   1 /*
   2  * ispreg.h
   3  *
   4  * TI OMAP3 ISP - Registers definitions
   5  *
   6  * Copyright (C) 2010 Nokia Corporation
   7  * Copyright (C) 2009 Texas Instruments, Inc
   8  *
   9  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10  *           Sakari Ailus <sakari.ailus@iki.fi>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  24  * 02110-1301 USA
  25  */
  26
  27 #ifndef OMAP3_ISP_REG_H
  28 #define OMAP3_ISP_REG_H
  29
  30 #include <plat/omap34xx.h>
  31
  32
  33 #define CM_CAM_MCLK_HZ                  172800000       /* Hz */
  34
  35 /* ISP Submodules offset */
  36
  37 #define OMAP3ISP_REG_BASE               OMAP3430_ISP_BASE
  38 #define OMAP3ISP_REG(offset)            (OMAP3ISP_REG_BASE + (offset))
  39
  40 #define OMAP3ISP_CCP2_REG_OFFSET        0x0400
  41 #define OMAP3ISP_CCP2_REG_BASE          (OMAP3ISP_REG_BASE +            \
  42                                          OMAP3ISP_CCP2_REG_OFFSET)
  43 #define OMAP3ISP_CCP2_REG(offset)       (OMAP3ISP_CCP2_REG_BASE + (offset))
  44
  45 #define OMAP3ISP_CCDC_REG_OFFSET        0x0600
  46 #define OMAP3ISP_CCDC_REG_BASE          (OMAP3ISP_REG_BASE +            \
  47                                          OMAP3ISP_CCDC_REG_OFFSET)
  48 #define OMAP3ISP_CCDC_REG(offset)       (OMAP3ISP_CCDC_REG_BASE + (offset))
  49
  50 #define OMAP3ISP_HIST_REG_OFFSET        0x0A00
  51 #define OMAP3ISP_HIST_REG_BASE          (OMAP3ISP_REG_BASE +            \
  52                                          OMAP3ISP_HIST_REG_OFFSET)
  53 #define OMAP3ISP_HIST_REG(offset)       (OMAP3ISP_HIST_REG_BASE + (offset))
  54
  55 #define OMAP3ISP_H3A_REG_OFFSET         0x0C00
  56 #define OMAP3ISP_H3A_REG_BASE           (OMAP3ISP_REG_BASE +            \
  57                                          OMAP3ISP_H3A_REG_OFFSET)
  58 #define OMAP3ISP_H3A_REG(offset)        (OMAP3ISP_H3A_REG_BASE + (offset))
  59
  60 #define OMAP3ISP_PREV_REG_OFFSET        0x0E00
  61 #define OMAP3ISP_PREV_REG_BASE          (OMAP3ISP_REG_BASE +            \
  62                                          OMAP3ISP_PREV_REG_OFFSET)
  63 #define OMAP3ISP_PREV_REG(offset)       (OMAP3ISP_PREV_REG_BASE + (offset))
  64
  65 #define OMAP3ISP_RESZ_REG_OFFSET        0x1000
  66 #define OMAP3ISP_RESZ_REG_BASE          (OMAP3ISP_REG_BASE +            \
  67                                          OMAP3ISP_RESZ_REG_OFFSET)
  68 #define OMAP3ISP_RESZ_REG(offset)       (OMAP3ISP_RESZ_REG_BASE + (offset))
  69
  70 #define OMAP3ISP_SBL_REG_OFFSET         0x1200
  71 #define OMAP3ISP_SBL_REG_BASE           (OMAP3ISP_REG_BASE +            \
  72                                          OMAP3ISP_SBL_REG_OFFSET)
  73 #define OMAP3ISP_SBL_REG(offset)        (OMAP3ISP_SBL_REG_BASE + (offset))
  74
  75 #define OMAP3ISP_CSI2A_REGS1_REG_OFFSET 0x1800
  76 #define OMAP3ISP_CSI2A_REGS1_REG_BASE   (OMAP3ISP_REG_BASE +            \
  77                                          OMAP3ISP_CSI2A_REGS1_REG_OFFSET)
  78 #define OMAP3ISP_CSI2A_REGS1_REG(offset)                                \
  79                                 (OMAP3ISP_CSI2A_REGS1_REG_BASE + (offset))
  80
  81 #define OMAP3ISP_CSIPHY2_REG_OFFSET     0x1970
  82 #define OMAP3ISP_CSIPHY2_REG_BASE       (OMAP3ISP_REG_BASE +    \
  83                                          OMAP3ISP_CSIPHY2_REG_OFFSET)
  84 #define OMAP3ISP_CSIPHY2_REG(offset)    (OMAP3ISP_CSIPHY2_REG_BASE + (offset))
  85
  86 #define OMAP3ISP_CSI2A_REGS2_REG_OFFSET 0x19C0
  87 #define OMAP3ISP_CSI2A_REGS2_REG_BASE   (OMAP3ISP_REG_BASE +            \
  88                                          OMAP3ISP_CSI2A_REGS2_REG_OFFSET)
  89 #define OMAP3ISP_CSI2A_REGS2_REG(offset)                                \
  90                                 (OMAP3ISP_CSI2A_REGS2_REG_BASE + (offset))
  91
  92 #define OMAP3ISP_CSI2C_REGS1_REG_OFFSET 0x1C00
  93 #define OMAP3ISP_CSI2C_REGS1_REG_BASE   (OMAP3ISP_REG_BASE +            \
  94                                          OMAP3ISP_CSI2C_REGS1_REG_OFFSET)
  95 #define OMAP3ISP_CSI2C_REGS1_REG(offset)                                \
  96                                 (OMAP3ISP_CSI2C_REGS1_REG_BASE + (offset))
  97
  98 #define OMAP3ISP_CSIPHY1_REG_OFFSET     0x1D70
  99 #define OMAP3ISP_CSIPHY1_REG_BASE       (OMAP3ISP_REG_BASE +    \
 100                                          OMAP3ISP_CSIPHY1_REG_OFFSET)
 101 #define OMAP3ISP_CSIPHY1_REG(offset)    (OMAP3ISP_CSIPHY1_REG_BASE + (offset))
 102
 103 #define OMAP3ISP_CSI2C_REGS2_REG_OFFSET 0x1DC0
 104 #define OMAP3ISP_CSI2C_REGS2_REG_BASE   (OMAP3ISP_REG_BASE +            \
 105                                          OMAP3ISP_CSI2C_REGS2_REG_OFFSET)
 106 #define OMAP3ISP_CSI2C_REGS2_REG(offset)                                \
 107                                 (OMAP3ISP_CSI2C_REGS2_REG_BASE + (offset))
 108
 109 /* ISP module register offset */
 110
 111 #define ISP_REVISION                    (0x000)
 112 #define ISP_SYSCONFIG                   (0x004)
 113 #define ISP_SYSSTATUS                   (0x008)
 114 #define ISP_IRQ0ENABLE                  (0x00C)
 115 #define ISP_IRQ0STATUS                  (0x010)
 116 #define ISP_IRQ1ENABLE                  (0x014)
 117 #define ISP_IRQ1STATUS                  (0x018)
 118 #define ISP_TCTRL_GRESET_LENGTH         (0x030)
 119 #define ISP_TCTRL_PSTRB_REPLAY          (0x034)
 120 #define ISP_CTRL                        (0x040)
 121 #define ISP_SECURE                      (0x044)
 122 #define ISP_TCTRL_CTRL                  (0x050)
 123 #define ISP_TCTRL_FRAME                 (0x054)
 124 #define ISP_TCTRL_PSTRB_DELAY           (0x058)
 125 #define ISP_TCTRL_STRB_DELAY            (0x05C)
 126 #define ISP_TCTRL_SHUT_DELAY            (0x060)
 127 #define ISP_TCTRL_PSTRB_LENGTH          (0x064)
 128 #define ISP_TCTRL_STRB_LENGTH           (0x068)
 129 #define ISP_TCTRL_SHUT_LENGTH           (0x06C)
 130 #define ISP_PING_PONG_ADDR              (0x070)
 131 #define ISP_PING_PONG_MEM_RANGE         (0x074)
 132 #define ISP_PING_PONG_BUF_SIZE          (0x078)
 133
 134 /* CCP2 receiver registers */
 135
 136 #define ISPCCP2_REVISION                (0x000)
 137 #define ISPCCP2_SYSCONFIG               (0x004)
 138 #define ISPCCP2_SYSCONFIG_SOFT_RESET    (1 << 1)
 139 #define ISPCCP2_SYSCONFIG_AUTO_IDLE             0x1
 140 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT   12
 141 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_FORCE   \
 142         (0x0 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
 143 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_NO      \
 144         (0x1 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
 145 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SMART   \
 146         (0x2 << ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
 147 #define ISPCCP2_SYSSTATUS               (0x008)
 148 #define ISPCCP2_SYSSTATUS_RESET_DONE    (1 << 0)
 149 #define ISPCCP2_LC01_IRQENABLE          (0x00C)
 150 #define ISPCCP2_LC01_IRQSTATUS          (0x010)
 151 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ       (1 << 11)
 152 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ       (1 << 10)
 153 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ       (1 << 9)
 154 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ       (1 << 8)
 155 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ    (1 << 7)
 156 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ (1 << 5)
 157 #define ISPCCP2_LC01_IRQSTATUS_LC0_CRC_IRQ      (1 << 4)
 158 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSP_IRQ      (1 << 3)
 159 #define ISPCCP2_LC01_IRQSTATUS_LC0_FW_IRQ       (1 << 2)
 160 #define ISPCCP2_LC01_IRQSTATUS_LC0_FSC_IRQ      (1 << 1)
 161 #define ISPCCP2_LC01_IRQSTATUS_LC0_SSC_IRQ      (1 << 0)
 162
 163 #define ISPCCP2_LC23_IRQENABLE          (0x014)
 164 #define ISPCCP2_LC23_IRQSTATUS          (0x018)
 165 #define ISPCCP2_LCM_IRQENABLE           (0x02C)
 166 #define ISPCCP2_LCM_IRQSTATUS_EOF_IRQ           (1 << 0)
 167 #define ISPCCP2_LCM_IRQSTATUS_OCPERROR_IRQ      (1 << 1)
 168 #define ISPCCP2_LCM_IRQSTATUS           (0x030)
 169 #define ISPCCP2_CTRL                    (0x040)
 170 #define ISPCCP2_CTRL_IF_EN              (1 << 0)
 171 #define ISPCCP2_CTRL_PHY_SEL            (1 << 1)
 172 #define ISPCCP2_CTRL_PHY_SEL_CLOCK      (0 << 1)
 173 #define ISPCCP2_CTRL_PHY_SEL_STROBE     (1 << 1)
 174 #define ISPCCP2_CTRL_PHY_SEL_MASK       0x1
 175 #define ISPCCP2_CTRL_PHY_SEL_SHIFT      1
 176 #define ISPCCP2_CTRL_IO_OUT_SEL         (1 << 2)
 177 #define ISPCCP2_CTRL_MODE               (1 << 4)
 178 #define ISPCCP2_CTRL_VP_CLK_FORCE_ON    (1 << 9)
 179 #define ISPCCP2_CTRL_INV                (1 << 10)
 180 #define ISPCCP2_CTRL_INV_MASK           0x1
 181 #define ISPCCP2_CTRL_INV_SHIFT          10
 182 #define ISPCCP2_CTRL_VP_ONLY_EN         (1 << 11)
 183 #define ISPCCP2_CTRL_VP_CLK_POL         (1 << 12)
 184 #define ISPCCP2_CTRL_VPCLK_DIV_SHIFT    15
 185 #define ISPCCP2_CTRL_VPCLK_DIV_MASK     0x1ffff /* [31:15] */
 186 #define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT  8 /* 3430 bits */
 187 #define ISPCCP2_CTRL_VP_OUT_CTRL_MASK   0x3 /* 3430 bits */
 188 #define ISPCCP2_DBG                     (0x044)
 189 #define ISPCCP2_GNQ                     (0x048)
 190 #define ISPCCP2_LCx_CTRL(x)                     ((0x050)+0x30*(x))
 191 #define ISPCCP2_LCx_CTRL_CHAN_EN                (1 << 0)
 192 #define ISPCCP2_LCx_CTRL_CRC_EN                 (1 << 19)
 193 #define ISPCCP2_LCx_CTRL_CRC_MASK               0x1
 194 #define ISPCCP2_LCx_CTRL_CRC_SHIFT              2
 195 #define ISPCCP2_LCx_CTRL_CRC_SHIFT_15_0         19
 196 #define ISPCCP2_LCx_CTRL_REGION_EN              (1 << 1)
 197 #define ISPCCP2_LCx_CTRL_REGION_MASK            0x1
 198 #define ISPCCP2_LCx_CTRL_REGION_SHIFT           1
 199 #define ISPCCP2_LCx_CTRL_FORMAT_MASK_15_0       0x3f
 200 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT_15_0      0x2
 201 #define ISPCCP2_LCx_CTRL_FORMAT_MASK            0x1f
 202 #define ISPCCP2_LCx_CTRL_FORMAT_SHIFT           0x3
 203 #define ISPCCP2_LCx_CODE(x)             ((0x054)+0x30*(x))
 204 #define ISPCCP2_LCx_STAT_START(x)       ((0x058)+0x30*(x))
 205 #define ISPCCP2_LCx_STAT_SIZE(x)        ((0x05C)+0x30*(x))
 206 #define ISPCCP2_LCx_SOF_ADDR(x)         ((0x060)+0x30*(x))
 207 #define ISPCCP2_LCx_EOF_ADDR(x)         ((0x064)+0x30*(x))
 208 #define ISPCCP2_LCx_DAT_START(x)        ((0x068)+0x30*(x))
 209 #define ISPCCP2_LCx_DAT_SIZE(x)         ((0x06C)+0x30*(x))
 210 #define ISPCCP2_LCx_DAT_MASK            0xFFF
 211 #define ISPCCP2_LCx_DAT_SHIFT           16
 212 #define ISPCCP2_LCx_DAT_PING_ADDR(x)    ((0x070)+0x30*(x))
 213 #define ISPCCP2_LCx_DAT_PONG_ADDR(x)    ((0x074)+0x30*(x))
 214 #define ISPCCP2_LCx_DAT_OFST(x)         ((0x078)+0x30*(x))
 215 #define ISPCCP2_LCM_CTRL                (0x1D0)
 216 #define ISPCCP2_LCM_CTRL_CHAN_EN               (1 << 0)
 217 #define ISPCCP2_LCM_CTRL_DST_PORT              (1 << 2)
 218 #define ISPCCP2_LCM_CTRL_DST_PORT_SHIFT         2
 219 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_SHIFT    3
 220 #define ISPCCP2_LCM_CTRL_READ_THROTTLE_MASK     0x11
 221 #define ISPCCP2_LCM_CTRL_BURST_SIZE_SHIFT       5
 222 #define ISPCCP2_LCM_CTRL_BURST_SIZE_MASK        0x7
 223 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_SHIFT       16
 224 #define ISPCCP2_LCM_CTRL_SRC_FORMAT_MASK        0x7
 225 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_SHIFT      20
 226 #define ISPCCP2_LCM_CTRL_SRC_DECOMPR_MASK       0x3
 227 #define ISPCCP2_LCM_CTRL_SRC_DPCM_PRED          (1 << 22)
 228 #define ISPCCP2_LCM_CTRL_SRC_PACK               (1 << 23)
 229 #define ISPCCP2_LCM_CTRL_DST_FORMAT_SHIFT       24
 230 #define ISPCCP2_LCM_CTRL_DST_FORMAT_MASK        0x7
 231 #define ISPCCP2_LCM_VSIZE               (0x1D4)
 232 #define ISPCCP2_LCM_VSIZE_SHIFT         16
 233 #define ISPCCP2_LCM_HSIZE               (0x1D8)
 234 #define ISPCCP2_LCM_HSIZE_SHIFT         16
 235 #define ISPCCP2_LCM_PREFETCH            (0x1DC)
 236 #define ISPCCP2_LCM_PREFETCH_SHIFT      3
 237 #define ISPCCP2_LCM_SRC_ADDR            (0x1E0)
 238 #define ISPCCP2_LCM_SRC_OFST            (0x1E4)
 239 #define ISPCCP2_LCM_DST_ADDR            (0x1E8)
 240 #define ISPCCP2_LCM_DST_OFST            (0x1EC)
 241
 242 /* CCDC module register offset */
 243
 244 #define ISPCCDC_PID                     (0x000)
 245 #define ISPCCDC_PCR                     (0x004)
 246 #define ISPCCDC_SYN_MODE                (0x008)
 247 #define ISPCCDC_HD_VD_WID               (0x00C)
 248 #define ISPCCDC_PIX_LINES               (0x010)
 249 #define ISPCCDC_HORZ_INFO               (0x014)
 250 #define ISPCCDC_VERT_START              (0x018)
 251 #define ISPCCDC_VERT_LINES              (0x01C)
 252 #define ISPCCDC_CULLING                 (0x020)
 253 #define ISPCCDC_HSIZE_OFF               (0x024)
 254 #define ISPCCDC_SDOFST                  (0x028)
 255 #define ISPCCDC_SDR_ADDR                (0x02C)
 256 #define ISPCCDC_CLAMP                   (0x030)
 257 #define ISPCCDC_DCSUB                   (0x034)
 258 #define ISPCCDC_COLPTN                  (0x038)
 259 #define ISPCCDC_BLKCMP                  (0x03C)
 260 #define ISPCCDC_FPC                     (0x040)
 261 #define ISPCCDC_FPC_ADDR                (0x044)
 262 #define ISPCCDC_VDINT                   (0x048)
 263 #define ISPCCDC_ALAW                    (0x04C)
 264 #define ISPCCDC_REC656IF                (0x050)
 265 #define ISPCCDC_CFG                     (0x054)
 266 #define ISPCCDC_FMTCFG                  (0x058)
 267 #define ISPCCDC_FMT_HORZ                (0x05C)
 268 #define ISPCCDC_FMT_VERT                (0x060)
 269 #define ISPCCDC_FMT_ADDR0               (0x064)
 270 #define ISPCCDC_FMT_ADDR1               (0x068)
 271 #define ISPCCDC_FMT_ADDR2               (0x06C)
 272 #define ISPCCDC_FMT_ADDR3               (0x070)
 273 #define ISPCCDC_FMT_ADDR4               (0x074)
 274 #define ISPCCDC_FMT_ADDR5               (0x078)
 275 #define ISPCCDC_FMT_ADDR6               (0x07C)
 276 #define ISPCCDC_FMT_ADDR7               (0x080)
 277 #define ISPCCDC_PRGEVEN0                (0x084)
 278 #define ISPCCDC_PRGEVEN1                (0x088)
 279 #define ISPCCDC_PRGODD0                 (0x08C)
 280 #define ISPCCDC_PRGODD1                 (0x090)
 281 #define ISPCCDC_VP_OUT                  (0x094)
 282
 283 #define ISPCCDC_LSC_CONFIG              (0x098)
 284 #define ISPCCDC_LSC_INITIAL             (0x09C)
 285 #define ISPCCDC_LSC_TABLE_BASE          (0x0A0)
 286 #define ISPCCDC_LSC_TABLE_OFFSET        (0x0A4)
 287
 288 /* SBL */
 289 #define ISPSBL_PCR                      0x4
 290 #define ISPSBL_PCR_H3A_AEAWB_WBL_OVF    (1 << 16)
 291 #define ISPSBL_PCR_H3A_AF_WBL_OVF       (1 << 17)
 292 #define ISPSBL_PCR_RSZ4_WBL_OVF         (1 << 18)
 293 #define ISPSBL_PCR_RSZ3_WBL_OVF         (1 << 19)
 294 #define ISPSBL_PCR_RSZ2_WBL_OVF         (1 << 20)
 295 #define ISPSBL_PCR_RSZ1_WBL_OVF         (1 << 21)
 296 #define ISPSBL_PCR_PRV_WBL_OVF          (1 << 22)
 297 #define ISPSBL_PCR_CCDC_WBL_OVF         (1 << 23)
 298 #define ISPSBL_PCR_CCDCPRV_2_RSZ_OVF    (1 << 24)
 299 #define ISPSBL_PCR_CSIA_WBL_OVF         (1 << 25)
 300 #define ISPSBL_PCR_CSIB_WBL_OVF         (1 << 26)
 301 #define ISPSBL_CCDC_WR_0                (0x028)
 302 #define ISPSBL_CCDC_WR_0_DATA_READY     (1 << 21)
 303 #define ISPSBL_CCDC_WR_1                (0x02C)
 304 #define ISPSBL_CCDC_WR_2                (0x030)
 305 #define ISPSBL_CCDC_WR_3                (0x034)
 306
 307 #define ISPSBL_SDR_REQ_EXP              0xF8
 308 #define ISPSBL_SDR_REQ_HIST_EXP_SHIFT   0
 309 #define ISPSBL_SDR_REQ_HIST_EXP_MASK    (0x3FF)
 310 #define ISPSBL_SDR_REQ_RSZ_EXP_SHIFT    10
 311 #define ISPSBL_SDR_REQ_RSZ_EXP_MASK     (0x3FF << ISPSBL_SDR_REQ_RSZ_EXP_SHIFT)
 312 #define ISPSBL_SDR_REQ_PRV_EXP_SHIFT    20
 313 #define ISPSBL_SDR_REQ_PRV_EXP_MASK     (0x3FF << ISPSBL_SDR_REQ_PRV_EXP_SHIFT)
 314
 315 /* Histogram registers */
 316 #define ISPHIST_PID                     (0x000)
 317 #define ISPHIST_PCR                     (0x004)
 318 #define ISPHIST_CNT                     (0x008)
 319 #define ISPHIST_WB_GAIN                 (0x00C)
 320 #define ISPHIST_R0_HORZ                 (0x010)
 321 #define ISPHIST_R0_VERT                 (0x014)
 322 #define ISPHIST_R1_HORZ                 (0x018)
 323 #define ISPHIST_R1_VERT                 (0x01C)
 324 #define ISPHIST_R2_HORZ                 (0x020)
 325 #define ISPHIST_R2_VERT                 (0x024)
 326 #define ISPHIST_R3_HORZ                 (0x028)
 327 #define ISPHIST_R3_VERT                 (0x02C)
 328 #define ISPHIST_ADDR                    (0x030)
 329 #define ISPHIST_DATA                    (0x034)
 330 #define ISPHIST_RADD                    (0x038)
 331 #define ISPHIST_RADD_OFF                (0x03C)
 332 #define ISPHIST_H_V_INFO                (0x040)
 333
 334 /* H3A module registers */
 335 #define ISPH3A_PID                      (0x000)
 336 #define ISPH3A_PCR                      (0x004)
 337 #define ISPH3A_AEWWIN1                  (0x04C)
 338 #define ISPH3A_AEWINSTART               (0x050)
 339 #define ISPH3A_AEWINBLK                 (0x054)
 340 #define ISPH3A_AEWSUBWIN                (0x058)
 341 #define ISPH3A_AEWBUFST                 (0x05C)
 342 #define ISPH3A_AFPAX1                   (0x008)
 343 #define ISPH3A_AFPAX2                   (0x00C)
 344 #define ISPH3A_AFPAXSTART               (0x010)
 345 #define ISPH3A_AFIIRSH                  (0x014)
 346 #define ISPH3A_AFBUFST                  (0x018)
 347 #define ISPH3A_AFCOEF010                (0x01C)
 348 #define ISPH3A_AFCOEF032                (0x020)
 349 #define ISPH3A_AFCOEF054                (0x024)
 350 #define ISPH3A_AFCOEF076                (0x028)
 351 #define ISPH3A_AFCOEF098                (0x02C)
 352 #define ISPH3A_AFCOEF0010               (0x030)
 353 #define ISPH3A_AFCOEF110                (0x034)
 354 #define ISPH3A_AFCOEF132                (0x038)
 355 #define ISPH3A_AFCOEF154                (0x03C)
 356 #define ISPH3A_AFCOEF176                (0x040)
 357 #define ISPH3A_AFCOEF198                (0x044)
 358 #define ISPH3A_AFCOEF1010               (0x048)
 359
 360 #define ISPPRV_PCR                      (0x004)
 361 #define ISPPRV_HORZ_INFO                (0x008)
 362 #define ISPPRV_VERT_INFO                (0x00C)
 363 #define ISPPRV_RSDR_ADDR                (0x010)
 364 #define ISPPRV_RADR_OFFSET              (0x014)
 365 #define ISPPRV_DSDR_ADDR                (0x018)
 366 #define ISPPRV_DRKF_OFFSET              (0x01C)
 367 #define ISPPRV_WSDR_ADDR                (0x020)
 368 #define ISPPRV_WADD_OFFSET              (0x024)
 369 #define ISPPRV_AVE                      (0x028)
 370 #define ISPPRV_HMED                     (0x02C)
 371 #define ISPPRV_NF                       (0x030)
 372 #define ISPPRV_WB_DGAIN                 (0x034)
 373 #define ISPPRV_WBGAIN                   (0x038)
 374 #define ISPPRV_WBSEL                    (0x03C)
 375 #define ISPPRV_CFA                      (0x040)
 376 #define ISPPRV_BLKADJOFF                (0x044)
 377 #define ISPPRV_RGB_MAT1                 (0x048)
 378 #define ISPPRV_RGB_MAT2                 (0x04C)
 379 #define ISPPRV_RGB_MAT3                 (0x050)
 380 #define ISPPRV_RGB_MAT4                 (0x054)
 381 #define ISPPRV_RGB_MAT5                 (0x058)
 382 #define ISPPRV_RGB_OFF1                 (0x05C)
 383 #define ISPPRV_RGB_OFF2                 (0x060)
 384 #define ISPPRV_CSC0                     (0x064)
 385 #define ISPPRV_CSC1                     (0x068)
 386 #define ISPPRV_CSC2                     (0x06C)
 387 #define ISPPRV_CSC_OFFSET               (0x070)
 388 #define ISPPRV_CNT_BRT                  (0x074)
 389 #define ISPPRV_CSUP                     (0x078)
 390 #define ISPPRV_SETUP_YC                 (0x07C)
 391 #define ISPPRV_SET_TBL_ADDR             (0x080)
 392 #define ISPPRV_SET_TBL_DATA             (0x084)
 393 #define ISPPRV_CDC_THR0                 (0x090)
 394 #define ISPPRV_CDC_THR1                 (ISPPRV_CDC_THR0 + (0x4))
 395 #define ISPPRV_CDC_THR2                 (ISPPRV_CDC_THR0 + (0x4) * 2)
 396 #define ISPPRV_CDC_THR3                 (ISPPRV_CDC_THR0 + (0x4) * 3)
 397
 398 #define ISPPRV_REDGAMMA_TABLE_ADDR      0x0000
 399 #define ISPPRV_GREENGAMMA_TABLE_ADDR    0x0400
 400 #define ISPPRV_BLUEGAMMA_TABLE_ADDR     0x0800
 401 #define ISPPRV_NF_TABLE_ADDR            0x0C00
 402 #define ISPPRV_YENH_TABLE_ADDR          0x1000
 403 #define ISPPRV_CFA_TABLE_ADDR           0x1400
 404
 405 #define ISPPRV_MAXOUTPUT_WIDTH          1280
 406 #define ISPPRV_MAXOUTPUT_WIDTH_ES2      3300
 407 #define ISPPRV_MAXOUTPUT_WIDTH_3630     4096
 408 #define ISPRSZ_MIN_OUTPUT               64
 409 #define ISPRSZ_MAX_OUTPUT               3312
 410
 411 /* Resizer module register offset */
 412 #define ISPRSZ_PID                      (0x000)
 413 #define ISPRSZ_PCR                      (0x004)
 414 #define ISPRSZ_CNT                      (0x008)
 415 #define ISPRSZ_OUT_SIZE                 (0x00C)
 416 #define ISPRSZ_IN_START                 (0x010)
 417 #define ISPRSZ_IN_SIZE                  (0x014)
 418 #define ISPRSZ_SDR_INADD                (0x018)
 419 #define ISPRSZ_SDR_INOFF                (0x01C)
 420 #define ISPRSZ_SDR_OUTADD               (0x020)
 421 #define ISPRSZ_SDR_OUTOFF               (0x024)
 422 #define ISPRSZ_HFILT10                  (0x028)
 423 #define ISPRSZ_HFILT32                  (0x02C)
 424 #define ISPRSZ_HFILT54                  (0x030)
 425 #define ISPRSZ_HFILT76                  (0x034)
 426 #define ISPRSZ_HFILT98                  (0x038)
 427 #define ISPRSZ_HFILT1110                (0x03C)
 428 #define ISPRSZ_HFILT1312                (0x040)
 429 #define ISPRSZ_HFILT1514                (0x044)
 430 #define ISPRSZ_HFILT1716                (0x048)
 431 #define ISPRSZ_HFILT1918                (0x04C)
 432 #define ISPRSZ_HFILT2120                (0x050)
 433 #define ISPRSZ_HFILT2322                (0x054)
 434 #define ISPRSZ_HFILT2524                (0x058)
 435 #define ISPRSZ_HFILT2726                (0x05C)
 436 #define ISPRSZ_HFILT2928                (0x060)
 437 #define ISPRSZ_HFILT3130                (0x064)
 438 #define ISPRSZ_VFILT10                  (0x068)
 439 #define ISPRSZ_VFILT32                  (0x06C)
 440 #define ISPRSZ_VFILT54                  (0x070)
 441 #define ISPRSZ_VFILT76                  (0x074)
 442 #define ISPRSZ_VFILT98                  (0x078)
 443 #define ISPRSZ_VFILT1110                (0x07C)
 444 #define ISPRSZ_VFILT1312                (0x080)
 445 #define ISPRSZ_VFILT1514                (0x084)
 446 #define ISPRSZ_VFILT1716                (0x088)
 447 #define ISPRSZ_VFILT1918                (0x08C)
 448 #define ISPRSZ_VFILT2120                (0x090)
 449 #define ISPRSZ_VFILT2322                (0x094)
 450 #define ISPRSZ_VFILT2524                (0x098)
 451 #define ISPRSZ_VFILT2726                (0x09C)
 452 #define ISPRSZ_VFILT2928                (0x0A0)
 453 #define ISPRSZ_VFILT3130                (0x0A4)
 454 #define ISPRSZ_YENH                     (0x0A8)
 455
 456 #define ISP_INT_CLR                     0xFF113F11
 457 #define ISPPRV_PCR_EN                   1
 458 #define ISPPRV_PCR_BUSY                 (1 << 1)
 459 #define ISPPRV_PCR_SOURCE               (1 << 2)
 460 #define ISPPRV_PCR_ONESHOT              (1 << 3)
 461 #define ISPPRV_PCR_WIDTH                (1 << 4)
 462 #define ISPPRV_PCR_INVALAW              (1 << 5)
 463 #define ISPPRV_PCR_DRKFEN               (1 << 6)
 464 #define ISPPRV_PCR_DRKFCAP              (1 << 7)
 465 #define ISPPRV_PCR_HMEDEN               (1 << 8)
 466 #define ISPPRV_PCR_NFEN                 (1 << 9)
 467 #define ISPPRV_PCR_CFAEN                (1 << 10)
 468 #define ISPPRV_PCR_CFAFMT_SHIFT         11
 469 #define ISPPRV_PCR_CFAFMT_MASK          0x7800
 470 #define ISPPRV_PCR_CFAFMT_BAYER         (0 << 11)
 471 #define ISPPRV_PCR_CFAFMT_SONYVGA       (1 << 11)
 472 #define ISPPRV_PCR_CFAFMT_RGBFOVEON     (2 << 11)
 473 #define ISPPRV_PCR_CFAFMT_DNSPL         (3 << 11)
 474 #define ISPPRV_PCR_CFAFMT_HONEYCOMB     (4 << 11)
 475 #define ISPPRV_PCR_CFAFMT_RRGGBBFOVEON  (5 << 11)
 476 #define ISPPRV_PCR_YNENHEN              (1 << 15)
 477 #define ISPPRV_PCR_SUPEN                (1 << 16)
 478 #define ISPPRV_PCR_YCPOS_SHIFT          17
 479 #define ISPPRV_PCR_YCPOS_YCrYCb         (0 << 17)
 480 #define ISPPRV_PCR_YCPOS_YCbYCr         (1 << 17)
 481 #define ISPPRV_PCR_YCPOS_CbYCrY         (2 << 17)
 482 #define ISPPRV_PCR_YCPOS_CrYCbY         (3 << 17)
 483 #define ISPPRV_PCR_RSZPORT              (1 << 19)
 484 #define ISPPRV_PCR_SDRPORT              (1 << 20)
 485 #define ISPPRV_PCR_SCOMP_EN             (1 << 21)
 486 #define ISPPRV_PCR_SCOMP_SFT_SHIFT      (22)
 487 #define ISPPRV_PCR_SCOMP_SFT_MASK       (7 << 22)
 488 #define ISPPRV_PCR_GAMMA_BYPASS         (1 << 26)
 489 #define ISPPRV_PCR_DCOREN               (1 << 27)
 490 #define ISPPRV_PCR_DCCOUP               (1 << 28)
 491 #define ISPPRV_PCR_DRK_FAIL             (1 << 31)
 492
 493 #define ISPPRV_HORZ_INFO_EPH_SHIFT      0
 494 #define ISPPRV_HORZ_INFO_EPH_MASK       0x3fff
 495 #define ISPPRV_HORZ_INFO_SPH_SHIFT      16
 496 #define ISPPRV_HORZ_INFO_SPH_MASK       0x3fff0
 497
 498 #define ISPPRV_VERT_INFO_ELV_SHIFT      0
 499 #define ISPPRV_VERT_INFO_ELV_MASK       0x3fff
 500 #define ISPPRV_VERT_INFO_SLV_SHIFT      16
 501 #define ISPPRV_VERT_INFO_SLV_MASK       0x3fff0
 502
 503 #define ISPPRV_AVE_EVENDIST_SHIFT       2
 504 #define ISPPRV_AVE_EVENDIST_1           0x0
 505 #define ISPPRV_AVE_EVENDIST_2           0x1
 506 #define ISPPRV_AVE_EVENDIST_3           0x2
 507 #define ISPPRV_AVE_EVENDIST_4           0x3
 508 #define ISPPRV_AVE_ODDDIST_SHIFT        4
 509 #define ISPPRV_AVE_ODDDIST_1            0x0
 510 #define ISPPRV_AVE_ODDDIST_2            0x1
 511 #define ISPPRV_AVE_ODDDIST_3            0x2
 512 #define ISPPRV_AVE_ODDDIST_4            0x3
 513
 514 #define ISPPRV_HMED_THRESHOLD_SHIFT     0
 515 #define ISPPRV_HMED_EVENDIST            (1 << 8)
 516 #define ISPPRV_HMED_ODDDIST             (1 << 9)
 517
 518 #define ISPPRV_WBGAIN_COEF0_SHIFT       0
 519 #define ISPPRV_WBGAIN_COEF1_SHIFT       8
 520 #define ISPPRV_WBGAIN_COEF2_SHIFT       16
 521 #define ISPPRV_WBGAIN_COEF3_SHIFT       24
 522
 523 #define ISPPRV_WBSEL_COEF0              0x0
 524 #define ISPPRV_WBSEL_COEF1              0x1
 525 #define ISPPRV_WBSEL_COEF2              0x2
 526 #define ISPPRV_WBSEL_COEF3              0x3
 527
 528 #define ISPPRV_WBSEL_N0_0_SHIFT         0
 529 #define ISPPRV_WBSEL_N0_1_SHIFT         2
 530 #define ISPPRV_WBSEL_N0_2_SHIFT         4
 531 #define ISPPRV_WBSEL_N0_3_SHIFT         6
 532 #define ISPPRV_WBSEL_N1_0_SHIFT         8
 533 #define ISPPRV_WBSEL_N1_1_SHIFT         10
 534 #define ISPPRV_WBSEL_N1_2_SHIFT         12
 535 #define ISPPRV_WBSEL_N1_3_SHIFT         14
 536 #define ISPPRV_WBSEL_N2_0_SHIFT         16
 537 #define ISPPRV_WBSEL_N2_1_SHIFT         18
 538 #define ISPPRV_WBSEL_N2_2_SHIFT         20
 539 #define ISPPRV_WBSEL_N2_3_SHIFT         22
 540 #define ISPPRV_WBSEL_N3_0_SHIFT         24
 541 #define ISPPRV_WBSEL_N3_1_SHIFT         26
 542 #define ISPPRV_WBSEL_N3_2_SHIFT         28
 543 #define ISPPRV_WBSEL_N3_3_SHIFT         30
 544
 545 #define ISPPRV_CFA_GRADTH_HOR_SHIFT     0
 546 #define ISPPRV_CFA_GRADTH_VER_SHIFT     8
 547
 548 #define ISPPRV_BLKADJOFF_B_SHIFT        0
 549 #define ISPPRV_BLKADJOFF_G_SHIFT        8
 550 #define ISPPRV_BLKADJOFF_R_SHIFT        16
 551
 552 #define ISPPRV_RGB_MAT1_MTX_RR_SHIFT    0
 553 #define ISPPRV_RGB_MAT1_MTX_GR_SHIFT    16
 554
 555 #define ISPPRV_RGB_MAT2_MTX_BR_SHIFT    0
 556 #define ISPPRV_RGB_MAT2_MTX_RG_SHIFT    16
 557
 558 #define ISPPRV_RGB_MAT3_MTX_GG_SHIFT    0
 559 #define ISPPRV_RGB_MAT3_MTX_BG_SHIFT    16
 560
 561 #define ISPPRV_RGB_MAT4_MTX_RB_SHIFT    0
 562 #define ISPPRV_RGB_MAT4_MTX_GB_SHIFT    16
 563
 564 #define ISPPRV_RGB_MAT5_MTX_BB_SHIFT    0
 565
 566 #define ISPPRV_RGB_OFF1_MTX_OFFG_SHIFT  0
 567 #define ISPPRV_RGB_OFF1_MTX_OFFR_SHIFT  16
 568
 569 #define ISPPRV_RGB_OFF2_MTX_OFFB_SHIFT  0
 570
 571 #define ISPPRV_CSC0_RY_SHIFT            0
 572 #define ISPPRV_CSC0_GY_SHIFT            10
 573 #define ISPPRV_CSC0_BY_SHIFT            20
 574
 575 #define ISPPRV_CSC1_RCB_SHIFT           0
 576 #define ISPPRV_CSC1_GCB_SHIFT           10
 577 #define ISPPRV_CSC1_BCB_SHIFT           20
 578
 579 #define ISPPRV_CSC2_RCR_SHIFT           0
 580 #define ISPPRV_CSC2_GCR_SHIFT           10
 581 #define ISPPRV_CSC2_BCR_SHIFT           20
 582
 583 #define ISPPRV_CSC_OFFSET_CR_SHIFT      0
 584 #define ISPPRV_CSC_OFFSET_CB_SHIFT      8
 585 #define ISPPRV_CSC_OFFSET_Y_SHIFT       16
 586
 587 #define ISPPRV_CNT_BRT_BRT_SHIFT        0
 588 #define ISPPRV_CNT_BRT_CNT_SHIFT        8
 589
 590 #define ISPPRV_CONTRAST_MAX             0x10
 591 #define ISPPRV_CONTRAST_MIN             0xFF
 592 #define ISPPRV_BRIGHT_MIN               0x00
 593 #define ISPPRV_BRIGHT_MAX               0xFF
 594
 595 #define ISPPRV_CSUP_CSUPG_SHIFT         0
 596 #define ISPPRV_CSUP_THRES_SHIFT         8
 597 #define ISPPRV_CSUP_HPYF_SHIFT          16
 598
 599 #define ISPPRV_SETUP_YC_MINC_SHIFT      0
 600 #define ISPPRV_SETUP_YC_MAXC_SHIFT      8
 601 #define ISPPRV_SETUP_YC_MINY_SHIFT      16
 602 #define ISPPRV_SETUP_YC_MAXY_SHIFT      24
 603 #define ISPPRV_YC_MAX                   0xFF
 604 #define ISPPRV_YC_MIN                   0x0
 605
 606 /* Define bit fields within selected registers */
 607 #define ISP_REVISION_SHIFT                      0
 608
 609 #define ISP_SYSCONFIG_AUTOIDLE                  (1 << 0)
 610 #define ISP_SYSCONFIG_SOFTRESET                 (1 << 1)
 611 #define ISP_SYSCONFIG_MIDLEMODE_SHIFT           12
 612 #define ISP_SYSCONFIG_MIDLEMODE_FORCESTANDBY    0x0
 613 #define ISP_SYSCONFIG_MIDLEMODE_NOSTANBY        0x1
 614 #define ISP_SYSCONFIG_MIDLEMODE_SMARTSTANDBY    0x2
 615
 616 #define ISP_SYSSTATUS_RESETDONE                 0
 617
 618 #define IRQ0ENABLE_CSIA_IRQ                     (1 << 0)
 619 #define IRQ0ENABLE_CSIC_IRQ                     (1 << 1)
 620 #define IRQ0ENABLE_CCP2_LCM_IRQ                 (1 << 3)
 621 #define IRQ0ENABLE_CCP2_LC0_IRQ                 (1 << 4)
 622 #define IRQ0ENABLE_CCP2_LC1_IRQ                 (1 << 5)
 623 #define IRQ0ENABLE_CCP2_LC2_IRQ                 (1 << 6)
 624 #define IRQ0ENABLE_CCP2_LC3_IRQ                 (1 << 7)
 625 #define IRQ0ENABLE_CSIB_IRQ                     (IRQ0ENABLE_CCP2_LCM_IRQ | \
 626                                                 IRQ0ENABLE_CCP2_LC0_IRQ | \
 627                                                 IRQ0ENABLE_CCP2_LC1_IRQ | \
 628                                                 IRQ0ENABLE_CCP2_LC2_IRQ | \
 629                                                 IRQ0ENABLE_CCP2_LC3_IRQ)
 630
 631 #define IRQ0ENABLE_CCDC_VD0_IRQ                 (1 << 8)
 632 #define IRQ0ENABLE_CCDC_VD1_IRQ                 (1 << 9)
 633 #define IRQ0ENABLE_CCDC_VD2_IRQ                 (1 << 10)
 634 #define IRQ0ENABLE_CCDC_ERR_IRQ                 (1 << 11)
 635 #define IRQ0ENABLE_H3A_AF_DONE_IRQ              (1 << 12)
 636 #define IRQ0ENABLE_H3A_AWB_DONE_IRQ             (1 << 13)
 637 #define IRQ0ENABLE_HIST_DONE_IRQ                (1 << 16)
 638 #define IRQ0ENABLE_CCDC_LSC_DONE_IRQ            (1 << 17)
 639 #define IRQ0ENABLE_CCDC_LSC_PREF_COMP_IRQ       (1 << 18)
 640 #define IRQ0ENABLE_CCDC_LSC_PREF_ERR_IRQ        (1 << 19)
 641 #define IRQ0ENABLE_PRV_DONE_IRQ                 (1 << 20)
 642 #define IRQ0ENABLE_RSZ_DONE_IRQ                 (1 << 24)
 643 #define IRQ0ENABLE_OVF_IRQ                      (1 << 25)
 644 #define IRQ0ENABLE_PING_IRQ                     (1 << 26)
 645 #define IRQ0ENABLE_PONG_IRQ                     (1 << 27)
 646 #define IRQ0ENABLE_MMU_ERR_IRQ                  (1 << 28)
 647 #define IRQ0ENABLE_OCP_ERR_IRQ                  (1 << 29)
 648 #define IRQ0ENABLE_SEC_ERR_IRQ                  (1 << 30)
 649 #define IRQ0ENABLE_HS_VS_IRQ                    (1 << 31)
 650
 651 #define IRQ0STATUS_CSIA_IRQ                     (1 << 0)
 652 #define IRQ0STATUS_CSI2C_IRQ                    (1 << 1)
 653 #define IRQ0STATUS_CCP2_LCM_IRQ                 (1 << 3)
 654 #define IRQ0STATUS_CCP2_LC0_IRQ                 (1 << 4)
 655 #define IRQ0STATUS_CSIB_IRQ                     (IRQ0STATUS_CCP2_LCM_IRQ | \
 656                                                 IRQ0STATUS_CCP2_LC0_IRQ)
 657
 658 #define IRQ0STATUS_CSIB_LC1_IRQ                 (1 << 5)
 659 #define IRQ0STATUS_CSIB_LC2_IRQ                 (1 << 6)
 660 #define IRQ0STATUS_CSIB_LC3_IRQ                 (1 << 7)
 661 #define IRQ0STATUS_CCDC_VD0_IRQ                 (1 << 8)
 662 #define IRQ0STATUS_CCDC_VD1_IRQ                 (1 << 9)
 663 #define IRQ0STATUS_CCDC_VD2_IRQ                 (1 << 10)
 664 #define IRQ0STATUS_CCDC_ERR_IRQ                 (1 << 11)
 665 #define IRQ0STATUS_H3A_AF_DONE_IRQ              (1 << 12)
 666 #define IRQ0STATUS_H3A_AWB_DONE_IRQ             (1 << 13)
 667 #define IRQ0STATUS_HIST_DONE_IRQ                (1 << 16)
 668 #define IRQ0STATUS_CCDC_LSC_DONE_IRQ            (1 << 17)
 669 #define IRQ0STATUS_CCDC_LSC_PREF_COMP_IRQ       (1 << 18)
 670 #define IRQ0STATUS_CCDC_LSC_PREF_ERR_IRQ        (1 << 19)
 671 #define IRQ0STATUS_PRV_DONE_IRQ                 (1 << 20)
 672 #define IRQ0STATUS_RSZ_DONE_IRQ                 (1 << 24)
 673 #define IRQ0STATUS_OVF_IRQ                      (1 << 25)
 674 #define IRQ0STATUS_PING_IRQ                     (1 << 26)
 675 #define IRQ0STATUS_PONG_IRQ                     (1 << 27)
 676 #define IRQ0STATUS_MMU_ERR_IRQ                  (1 << 28)
 677 #define IRQ0STATUS_OCP_ERR_IRQ                  (1 << 29)
 678 #define IRQ0STATUS_SEC_ERR_IRQ                  (1 << 30)
 679 #define IRQ0STATUS_HS_VS_IRQ                    (1 << 31)
 680
 681 #define TCTRL_GRESET_LEN                        0
 682
 683 #define TCTRL_PSTRB_REPLAY_DELAY                0
 684 #define TCTRL_PSTRB_REPLAY_COUNTER_SHIFT        25
 685
 686 #define ISPCTRL_PAR_SER_CLK_SEL_PARALLEL        0x0
 687 #define ISPCTRL_PAR_SER_CLK_SEL_CSIA            0x1
 688 #define ISPCTRL_PAR_SER_CLK_SEL_CSIB            0x2
 689 #define ISPCTRL_PAR_SER_CLK_SEL_CSIC            0x3
 690 #define ISPCTRL_PAR_SER_CLK_SEL_MASK            0x3
 691
 692 #define ISPCTRL_PAR_BRIDGE_SHIFT                2
 693 #define ISPCTRL_PAR_BRIDGE_DISABLE              (0x0 << 2)
 694 #define ISPCTRL_PAR_BRIDGE_LENDIAN              (0x2 << 2)
 695 #define ISPCTRL_PAR_BRIDGE_BENDIAN              (0x3 << 2)
 696 #define ISPCTRL_PAR_BRIDGE_MASK                 (0x3 << 2)
 697
 698 #define ISPCTRL_PAR_CLK_POL_SHIFT               4
 699 #define ISPCTRL_PAR_CLK_POL_INV                 (1 << 4)
 700 #define ISPCTRL_PING_PONG_EN                    (1 << 5)
 701 #define ISPCTRL_SHIFT_SHIFT                     6
 702 #define ISPCTRL_SHIFT_0                         (0x0 << 6)
 703 #define ISPCTRL_SHIFT_2                         (0x1 << 6)
 704 #define ISPCTRL_SHIFT_4                         (0x2 << 6)
 705 #define ISPCTRL_SHIFT_MASK                      (0x3 << 6)
 706
 707 #define ISPCTRL_CCDC_CLK_EN                     (1 << 8)
 708 #define ISPCTRL_SCMP_CLK_EN                     (1 << 9)
 709 #define ISPCTRL_H3A_CLK_EN                      (1 << 10)
 710 #define ISPCTRL_HIST_CLK_EN                     (1 << 11)
 711 #define ISPCTRL_PREV_CLK_EN                     (1 << 12)
 712 #define ISPCTRL_RSZ_CLK_EN                      (1 << 13)
 713 #define ISPCTRL_SYNC_DETECT_SHIFT               14
 714 #define ISPCTRL_SYNC_DETECT_HSFALL      (0x0 << ISPCTRL_SYNC_DETECT_SHIFT)
 715 #define ISPCTRL_SYNC_DETECT_HSRISE      (0x1 << ISPCTRL_SYNC_DETECT_SHIFT)
 716 #define ISPCTRL_SYNC_DETECT_VSFALL      (0x2 << ISPCTRL_SYNC_DETECT_SHIFT)
 717 #define ISPCTRL_SYNC_DETECT_VSRISE      (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
 718 #define ISPCTRL_SYNC_DETECT_MASK        (0x3 << ISPCTRL_SYNC_DETECT_SHIFT)
 719
 720 #define ISPCTRL_CCDC_RAM_EN             (1 << 16)
 721 #define ISPCTRL_PREV_RAM_EN             (1 << 17)
 722 #define ISPCTRL_SBL_RD_RAM_EN           (1 << 18)
 723 #define ISPCTRL_SBL_WR1_RAM_EN          (1 << 19)
 724 #define ISPCTRL_SBL_WR0_RAM_EN          (1 << 20)
 725 #define ISPCTRL_SBL_AUTOIDLE            (1 << 21)
 726 #define ISPCTRL_SBL_SHARED_WPORTC       (1 << 26)
 727 #define ISPCTRL_SBL_SHARED_RPORTA       (1 << 27)
 728 #define ISPCTRL_SBL_SHARED_RPORTB       (1 << 28)
 729 #define ISPCTRL_JPEG_FLUSH              (1 << 30)
 730 #define ISPCTRL_CCDC_FLUSH              (1 << 31)
 731
 732 #define ISPSECURE_SECUREMODE            0
 733
 734 #define ISPTCTRL_CTRL_DIV_LOW           0x0
 735 #define ISPTCTRL_CTRL_DIV_HIGH          0x1
 736 #define ISPTCTRL_CTRL_DIV_BYPASS        0x1F
 737
 738 #define ISPTCTRL_CTRL_DIVA_SHIFT        0
 739 #define ISPTCTRL_CTRL_DIVA_MASK         (0x1F << ISPTCTRL_CTRL_DIVA_SHIFT)
 740
 741 #define ISPTCTRL_CTRL_DIVB_SHIFT        5
 742 #define ISPTCTRL_CTRL_DIVB_MASK         (0x1F << ISPTCTRL_CTRL_DIVB_SHIFT)
 743
 744 #define ISPTCTRL_CTRL_DIVC_SHIFT        10
 745 #define ISPTCTRL_CTRL_DIVC_NOCLOCK      (0x0 << 10)
 746
 747 #define ISPTCTRL_CTRL_SHUTEN            (1 << 21)
 748 #define ISPTCTRL_CTRL_PSTRBEN           (1 << 22)
 749 #define ISPTCTRL_CTRL_STRBEN            (1 << 23)
 750 #define ISPTCTRL_CTRL_SHUTPOL           (1 << 24)
 751 #define ISPTCTRL_CTRL_STRBPSTRBPOL      (1 << 26)
 752
 753 #define ISPTCTRL_CTRL_INSEL_SHIFT       27
 754 #define ISPTCTRL_CTRL_INSEL_PARALLEL    (0x0 << 27)
 755 #define ISPTCTRL_CTRL_INSEL_CSIA        (0x1 << 27)
 756 #define ISPTCTRL_CTRL_INSEL_CSIB        (0x2 << 27)
 757
 758 #define ISPTCTRL_CTRL_GRESETEn          (1 << 29)
 759 #define ISPTCTRL_CTRL_GRESETPOL         (1 << 30)
 760 #define ISPTCTRL_CTRL_GRESETDIR         (1 << 31)
 761
 762 #define ISPTCTRL_FRAME_SHUT_SHIFT               0
 763 #define ISPTCTRL_FRAME_PSTRB_SHIFT              6
 764 #define ISPTCTRL_FRAME_STRB_SHIFT               12
 765
 766 #define ISPCCDC_PID_PREV_SHIFT                  0
 767 #define ISPCCDC_PID_CID_SHIFT                   8
 768 #define ISPCCDC_PID_TID_SHIFT                   16
 769
 770 #define ISPCCDC_PCR_EN                          1
 771 #define ISPCCDC_PCR_BUSY                        (1 << 1)
 772
 773 #define ISPCCDC_SYN_MODE_VDHDOUT                0x1
 774 #define ISPCCDC_SYN_MODE_FLDOUT                 (1 << 1)
 775 #define ISPCCDC_SYN_MODE_VDPOL                  (1 << 2)
 776 #define ISPCCDC_SYN_MODE_HDPOL                  (1 << 3)
 777 #define ISPCCDC_SYN_MODE_FLDPOL                 (1 << 4)
 778 #define ISPCCDC_SYN_MODE_EXWEN                  (1 << 5)
 779 #define ISPCCDC_SYN_MODE_DATAPOL                (1 << 6)
 780 #define ISPCCDC_SYN_MODE_FLDMODE                (1 << 7)
 781 #define ISPCCDC_SYN_MODE_DATSIZ_MASK            (0x7 << 8)
 782 #define ISPCCDC_SYN_MODE_DATSIZ_8_16            (0x0 << 8)
 783 #define ISPCCDC_SYN_MODE_DATSIZ_12              (0x4 << 8)
 784 #define ISPCCDC_SYN_MODE_DATSIZ_11              (0x5 << 8)
 785 #define ISPCCDC_SYN_MODE_DATSIZ_10              (0x6 << 8)
 786 #define ISPCCDC_SYN_MODE_DATSIZ_8               (0x7 << 8)
 787 #define ISPCCDC_SYN_MODE_PACK8                  (1 << 11)
 788 #define ISPCCDC_SYN_MODE_INPMOD_MASK            (3 << 12)
 789 #define ISPCCDC_SYN_MODE_INPMOD_RAW             (0 << 12)
 790 #define ISPCCDC_SYN_MODE_INPMOD_YCBCR16         (1 << 12)
 791 #define ISPCCDC_SYN_MODE_INPMOD_YCBCR8          (2 << 12)
 792 #define ISPCCDC_SYN_MODE_LPF                    (1 << 14)
 793 #define ISPCCDC_SYN_MODE_FLDSTAT                (1 << 15)
 794 #define ISPCCDC_SYN_MODE_VDHDEN                 (1 << 16)
 795 #define ISPCCDC_SYN_MODE_WEN                    (1 << 17)
 796 #define ISPCCDC_SYN_MODE_VP2SDR                 (1 << 18)
 797 #define ISPCCDC_SYN_MODE_SDR2RSZ                (1 << 19)
 798
 799 #define ISPCCDC_HD_VD_WID_VDW_SHIFT             0
 800 #define ISPCCDC_HD_VD_WID_HDW_SHIFT             16
 801
 802 #define ISPCCDC_PIX_LINES_HLPRF_SHIFT           0
 803 #define ISPCCDC_PIX_LINES_PPLN_SHIFT            16
 804
 805 #define ISPCCDC_HORZ_INFO_NPH_SHIFT             0
 806 #define ISPCCDC_HORZ_INFO_NPH_MASK              0x00007fff
 807 #define ISPCCDC_HORZ_INFO_SPH_SHIFT             16
 808 #define ISPCCDC_HORZ_INFO_SPH_MASK              0x7fff0000
 809
 810 #define ISPCCDC_VERT_START_SLV1_SHIFT           0
 811 #define ISPCCDC_VERT_START_SLV0_SHIFT           16
 812 #define ISPCCDC_VERT_START_SLV0_MASK            0x7fff0000
 813
 814 #define ISPCCDC_VERT_LINES_NLV_SHIFT            0
 815 #define ISPCCDC_VERT_LINES_NLV_MASK             0x00007fff
 816
 817 #define ISPCCDC_CULLING_CULV_SHIFT              0
 818 #define ISPCCDC_CULLING_CULHODD_SHIFT           16
 819 #define ISPCCDC_CULLING_CULHEVN_SHIFT           24
 820
 821 #define ISPCCDC_HSIZE_OFF_SHIFT                 0
 822
 823 #define ISPCCDC_SDOFST_FINV                     (1 << 14)
 824 #define ISPCCDC_SDOFST_FOFST_1L                 0
 825 #define ISPCCDC_SDOFST_FOFST_4L                 (3 << 12)
 826 #define ISPCCDC_SDOFST_LOFST3_SHIFT             0
 827 #define ISPCCDC_SDOFST_LOFST2_SHIFT             3
 828 #define ISPCCDC_SDOFST_LOFST1_SHIFT             6
 829 #define ISPCCDC_SDOFST_LOFST0_SHIFT             9
 830 #define EVENEVEN                                1
 831 #define ODDEVEN                                 2
 832 #define EVENODD                                 3
 833 #define ODDODD                                  4
 834
 835 #define ISPCCDC_CLAMP_OBGAIN_SHIFT              0
 836 #define ISPCCDC_CLAMP_OBST_SHIFT                10
 837 #define ISPCCDC_CLAMP_OBSLN_SHIFT               25
 838 #define ISPCCDC_CLAMP_OBSLEN_SHIFT              28
 839 #define ISPCCDC_CLAMP_CLAMPEN                   (1 << 31)
 840
 841 #define ISPCCDC_COLPTN_R_Ye                     0x0
 842 #define ISPCCDC_COLPTN_Gr_Cy                    0x1
 843 #define ISPCCDC_COLPTN_Gb_G                     0x2
 844 #define ISPCCDC_COLPTN_B_Mg                     0x3
 845 #define ISPCCDC_COLPTN_CP0PLC0_SHIFT            0
 846 #define ISPCCDC_COLPTN_CP0PLC1_SHIFT            2
 847 #define ISPCCDC_COLPTN_CP0PLC2_SHIFT            4
 848 #define ISPCCDC_COLPTN_CP0PLC3_SHIFT            6
 849 #define ISPCCDC_COLPTN_CP1PLC0_SHIFT            8
 850 #define ISPCCDC_COLPTN_CP1PLC1_SHIFT            10
 851 #define ISPCCDC_COLPTN_CP1PLC2_SHIFT            12
 852 #define ISPCCDC_COLPTN_CP1PLC3_SHIFT            14
 853 #define ISPCCDC_COLPTN_CP2PLC0_SHIFT            16
 854 #define ISPCCDC_COLPTN_CP2PLC1_SHIFT            18
 855 #define ISPCCDC_COLPTN_CP2PLC2_SHIFT            20
 856 #define ISPCCDC_COLPTN_CP2PLC3_SHIFT            22
 857 #define ISPCCDC_COLPTN_CP3PLC0_SHIFT            24
 858 #define ISPCCDC_COLPTN_CP3PLC1_SHIFT            26
 859 #define ISPCCDC_COLPTN_CP3PLC2_SHIFT            28
 860 #define ISPCCDC_COLPTN_CP3PLC3_SHIFT            30
 861
 862 #define ISPCCDC_BLKCMP_B_MG_SHIFT               0
 863 #define ISPCCDC_BLKCMP_GB_G_SHIFT               8
 864 #define ISPCCDC_BLKCMP_GR_CY_SHIFT              16
 865 #define ISPCCDC_BLKCMP_R_YE_SHIFT               24
 866
 867 #define ISPCCDC_FPC_FPNUM_SHIFT                 0
 868 #define ISPCCDC_FPC_FPCEN                       (1 << 15)
 869 #define ISPCCDC_FPC_FPERR                       (1 << 16)
 870
 871 #define ISPCCDC_VDINT_1_SHIFT                   0
 872 #define ISPCCDC_VDINT_1_MASK                    0x00007fff
 873 #define ISPCCDC_VDINT_0_SHIFT                   16
 874 #define ISPCCDC_VDINT_0_MASK                    0x7fff0000
 875
 876 #define ISPCCDC_ALAW_GWDI_12_3                  (0x3 << 0)
 877 #define ISPCCDC_ALAW_GWDI_11_2                  (0x4 << 0)
 878 #define ISPCCDC_ALAW_GWDI_10_1                  (0x5 << 0)
 879 #define ISPCCDC_ALAW_GWDI_9_0                   (0x6 << 0)
 880 #define ISPCCDC_ALAW_CCDTBL                     (1 << 3)
 881
 882 #define ISPCCDC_REC656IF_R656ON                 1
 883 #define ISPCCDC_REC656IF_ECCFVH                 (1 << 1)
 884
 885 #define ISPCCDC_CFG_BW656                       (1 << 5)
 886 #define ISPCCDC_CFG_FIDMD_SHIFT                 6
 887 #define ISPCCDC_CFG_WENLOG                      (1 << 8)
 888 #define ISPCCDC_CFG_WENLOG_AND                  (0 << 8)
 889 #define ISPCCDC_CFG_WENLOG_OR                   (1 << 8)
 890 #define ISPCCDC_CFG_Y8POS                       (1 << 11)
 891 #define ISPCCDC_CFG_BSWD                        (1 << 12)
 892 #define ISPCCDC_CFG_MSBINVI                     (1 << 13)
 893 #define ISPCCDC_CFG_VDLC                        (1 << 15)
 894
 895 #define ISPCCDC_FMTCFG_FMTEN                    0x1
 896 #define ISPCCDC_FMTCFG_LNALT                    (1 << 1)
 897 #define ISPCCDC_FMTCFG_LNUM_SHIFT               2
 898 #define ISPCCDC_FMTCFG_PLEN_ODD_SHIFT           4
 899 #define ISPCCDC_FMTCFG_PLEN_EVEN_SHIFT          8
 900 #define ISPCCDC_FMTCFG_VPIN_MASK                0x00007000
 901 #define ISPCCDC_FMTCFG_VPIN_12_3                (0x3 << 12)
 902 #define ISPCCDC_FMTCFG_VPIN_11_2                (0x4 << 12)
 903 #define ISPCCDC_FMTCFG_VPIN_10_1                (0x5 << 12)
 904 #define ISPCCDC_FMTCFG_VPIN_9_0                 (0x6 << 12)
 905 #define ISPCCDC_FMTCFG_VPEN                     (1 << 15)
 906
 907 #define ISPCCDC_FMTCFG_VPIF_FRQ_MASK            0x003f0000
 908 #define ISPCCDC_FMTCFG_VPIF_FRQ_SHIFT           16
 909 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY2             (0x0 << 16)
 910 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY3             (0x1 << 16)
 911 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY4             (0x2 << 16)
 912 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY5             (0x3 << 16)
 913 #define ISPCCDC_FMTCFG_VPIF_FRQ_BY6             (0x4 << 16)
 914
 915 #define ISPCCDC_FMT_HORZ_FMTLNH_SHIFT           0
 916 #define ISPCCDC_FMT_HORZ_FMTSPH_SHIFT           16
 917
 918 #define ISPCCDC_FMT_VERT_FMTLNV_SHIFT           0
 919 #define ISPCCDC_FMT_VERT_FMTSLV_SHIFT           16
 920
 921 #define ISPCCDC_FMT_HORZ_FMTSPH_MASK            0x1fff0000
 922 #define ISPCCDC_FMT_HORZ_FMTLNH_MASK            0x00001fff
 923
 924 #define ISPCCDC_FMT_VERT_FMTSLV_MASK            0x1fff0000
 925 #define ISPCCDC_FMT_VERT_FMTLNV_MASK            0x00001fff
 926
 927 #define ISPCCDC_VP_OUT_HORZ_ST_SHIFT            0
 928 #define ISPCCDC_VP_OUT_HORZ_NUM_SHIFT           4
 929 #define ISPCCDC_VP_OUT_VERT_NUM_SHIFT           17
 930
 931 #define ISPRSZ_PID_PREV_SHIFT                   0
 932 #define ISPRSZ_PID_CID_SHIFT                    8
 933 #define ISPRSZ_PID_TID_SHIFT                    16
 934
 935 #define ISPRSZ_PCR_ENABLE                       (1 << 0)
 936 #define ISPRSZ_PCR_BUSY                         (1 << 1)
 937 #define ISPRSZ_PCR_ONESHOT                      (1 << 2)
 938
 939 #define ISPRSZ_CNT_HRSZ_SHIFT                   0
 940 #define ISPRSZ_CNT_HRSZ_MASK                    \
 941         (0x3FF << ISPRSZ_CNT_HRSZ_SHIFT)
 942 #define ISPRSZ_CNT_VRSZ_SHIFT                   10
 943 #define ISPRSZ_CNT_VRSZ_MASK                    \
 944         (0x3FF << ISPRSZ_CNT_VRSZ_SHIFT)
 945 #define ISPRSZ_CNT_HSTPH_SHIFT                  20
 946 #define ISPRSZ_CNT_HSTPH_MASK                   (0x7 << ISPRSZ_CNT_HSTPH_SHIFT)
 947 #define ISPRSZ_CNT_VSTPH_SHIFT                  23
 948 #define ISPRSZ_CNT_VSTPH_MASK                   (0x7 << ISPRSZ_CNT_VSTPH_SHIFT)
 949 #define ISPRSZ_CNT_YCPOS                        (1 << 26)
 950 #define ISPRSZ_CNT_INPTYP                       (1 << 27)
 951 #define ISPRSZ_CNT_INPSRC                       (1 << 28)
 952 #define ISPRSZ_CNT_CBILIN                       (1 << 29)
 953
 954 #define ISPRSZ_OUT_SIZE_HORZ_SHIFT              0
 955 #define ISPRSZ_OUT_SIZE_HORZ_MASK               \
 956         (0xFFF << ISPRSZ_OUT_SIZE_HORZ_SHIFT)
 957 #define ISPRSZ_OUT_SIZE_VERT_SHIFT              16
 958 #define ISPRSZ_OUT_SIZE_VERT_MASK               \
 959         (0xFFF << ISPRSZ_OUT_SIZE_VERT_SHIFT)
 960
 961 #define ISPRSZ_IN_START_HORZ_ST_SHIFT           0
 962 #define ISPRSZ_IN_START_HORZ_ST_MASK            \
 963         (0x1FFF << ISPRSZ_IN_START_HORZ_ST_SHIFT)
 964 #define ISPRSZ_IN_START_VERT_ST_SHIFT           16
 965 #define ISPRSZ_IN_START_VERT_ST_MASK            \
 966         (0x1FFF << ISPRSZ_IN_START_VERT_ST_SHIFT)
 967
 968 #define ISPRSZ_IN_SIZE_HORZ_SHIFT               0
 969 #define ISPRSZ_IN_SIZE_HORZ_MASK                \
 970         (0x1FFF << ISPRSZ_IN_SIZE_HORZ_SHIFT)
 971 #define ISPRSZ_IN_SIZE_VERT_SHIFT               16
 972 #define ISPRSZ_IN_SIZE_VERT_MASK                \
 973         (0x1FFF << ISPRSZ_IN_SIZE_VERT_SHIFT)
 974
 975 #define ISPRSZ_SDR_INADD_ADDR_SHIFT             0
 976 #define ISPRSZ_SDR_INADD_ADDR_MASK              0xFFFFFFFF
 977
 978 #define ISPRSZ_SDR_INOFF_OFFSET_SHIFT           0
 979 #define ISPRSZ_SDR_INOFF_OFFSET_MASK            \
 980         (0xFFFF << ISPRSZ_SDR_INOFF_OFFSET_SHIFT)
 981
 982 #define ISPRSZ_SDR_OUTADD_ADDR_SHIFT            0
 983 #define ISPRSZ_SDR_OUTADD_ADDR_MASK             0xFFFFFFFF
 984
 985
 986 #define ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT          0
 987 #define ISPRSZ_SDR_OUTOFF_OFFSET_MASK           \
 988         (0xFFFF << ISPRSZ_SDR_OUTOFF_OFFSET_SHIFT)
 989
 990 #define ISPRSZ_HFILT_COEF0_SHIFT                0
 991 #define ISPRSZ_HFILT_COEF0_MASK                 \
 992         (0x3FF << ISPRSZ_HFILT_COEF0_SHIFT)
 993 #define ISPRSZ_HFILT_COEF1_SHIFT                16
 994 #define ISPRSZ_HFILT_COEF1_MASK                 \
 995         (0x3FF << ISPRSZ_HFILT_COEF1_SHIFT)
 996
 997 #define ISPRSZ_HFILT32_COEF2_SHIFT              0
 998 #define ISPRSZ_HFILT32_COEF2_MASK               0x3FF
 999 #define ISPRSZ_HFILT32_COEF3_SHIFT              16
1000 #define ISPRSZ_HFILT32_COEF3_MASK               0x3FF0000
1001
1002 #define ISPRSZ_HFILT54_COEF4_SHIFT              0
1003 #define ISPRSZ_HFILT54_COEF4_MASK               0x3FF
1004 #define ISPRSZ_HFILT54_COEF5_SHIFT              16
1005 #define ISPRSZ_HFILT54_COEF5_MASK               0x3FF0000
1006
1007 #define ISPRSZ_HFILT76_COEFF6_SHIFT             0
1008 #define ISPRSZ_HFILT76_COEFF6_MASK              0x3FF
1009 #define ISPRSZ_HFILT76_COEFF7_SHIFT             16
1010 #define ISPRSZ_HFILT76_COEFF7_MASK              0x3FF0000
1011
1012 #define ISPRSZ_HFILT98_COEFF8_SHIFT             0
1013 #define ISPRSZ_HFILT98_COEFF8_MASK              0x3FF
1014 #define ISPRSZ_HFILT98_COEFF9_SHIFT             16
1015 #define ISPRSZ_HFILT98_COEFF9_MASK              0x3FF0000
1016
1017 #define ISPRSZ_HFILT1110_COEF10_SHIFT           0
1018 #define ISPRSZ_HFILT1110_COEF10_MASK            0x3FF
1019 #define ISPRSZ_HFILT1110_COEF11_SHIFT           16
1020 #define ISPRSZ_HFILT1110_COEF11_MASK            0x3FF0000
1021
1022 #define ISPRSZ_HFILT1312_COEFF12_SHIFT          0
1023 #define ISPRSZ_HFILT1312_COEFF12_MASK           0x3FF
1024 #define ISPRSZ_HFILT1312_COEFF13_SHIFT          16
1025 #define ISPRSZ_HFILT1312_COEFF13_MASK           0x3FF0000
1026
1027 #define ISPRSZ_HFILT1514_COEFF14_SHIFT          0
1028 #define ISPRSZ_HFILT1514_COEFF14_MASK           0x3FF
1029 #define ISPRSZ_HFILT1514_COEFF15_SHIFT          16
1030 #define ISPRSZ_HFILT1514_COEFF15_MASK           0x3FF0000
1031
1032 #define ISPRSZ_HFILT1716_COEF16_SHIFT           0
1033 #define ISPRSZ_HFILT1716_COEF16_MASK            0x3FF
1034 #define ISPRSZ_HFILT1716_COEF17_SHIFT           16
1035 #define ISPRSZ_HFILT1716_COEF17_MASK            0x3FF0000
1036
1037 #define ISPRSZ_HFILT1918_COEF18_SHIFT           0
1038 #define ISPRSZ_HFILT1918_COEF18_MASK            0x3FF
1039 #define ISPRSZ_HFILT1918_COEF19_SHIFT           16
1040 #define ISPRSZ_HFILT1918_COEF19_MASK            0x3FF0000
1041
1042 #define ISPRSZ_HFILT2120_COEF20_SHIFT           0
1043 #define ISPRSZ_HFILT2120_COEF20_MASK            0x3FF
1044 #define ISPRSZ_HFILT2120_COEF21_SHIFT           16
1045 #define ISPRSZ_HFILT2120_COEF21_MASK            0x3FF0000
1046
1047 #define ISPRSZ_HFILT2322_COEF22_SHIFT           0
1048 #define ISPRSZ_HFILT2322_COEF22_MASK            0x3FF
1049 #define ISPRSZ_HFILT2322_COEF23_SHIFT           16
1050 #define ISPRSZ_HFILT2322_COEF23_MASK            0x3FF0000
1051
1052 #define ISPRSZ_HFILT2524_COEF24_SHIFT           0
1053 #define ISPRSZ_HFILT2524_COEF24_MASK            0x3FF
1054 #define ISPRSZ_HFILT2524_COEF25_SHIFT           16
1055 #define ISPRSZ_HFILT2524_COEF25_MASK            0x3FF0000
1056
1057 #define ISPRSZ_HFILT2726_COEF26_SHIFT           0
1058 #define ISPRSZ_HFILT2726_COEF26_MASK            0x3FF
1059 #define ISPRSZ_HFILT2726_COEF27_SHIFT           16
1060 #define ISPRSZ_HFILT2726_COEF27_MASK            0x3FF0000
1061
1062 #define ISPRSZ_HFILT2928_COEF28_SHIFT           0
1063 #define ISPRSZ_HFILT2928_COEF28_MASK            0x3FF
1064 #define ISPRSZ_HFILT2928_COEF29_SHIFT           16
1065 #define ISPRSZ_HFILT2928_COEF29_MASK            0x3FF0000
1066
1067 #define ISPRSZ_HFILT3130_COEF30_SHIFT           0
1068 #define ISPRSZ_HFILT3130_COEF30_MASK            0x3FF
1069 #define ISPRSZ_HFILT3130_COEF31_SHIFT           16
1070 #define ISPRSZ_HFILT3130_COEF31_MASK            0x3FF0000
1071
1072 #define ISPRSZ_VFILT_COEF0_SHIFT                0
1073 #define ISPRSZ_VFILT_COEF0_MASK                 \
1074         (0x3FF << ISPRSZ_VFILT_COEF0_SHIFT)
1075 #define ISPRSZ_VFILT_COEF1_SHIFT                16
1076 #define ISPRSZ_VFILT_COEF1_MASK                 \
1077         (0x3FF << ISPRSZ_VFILT_COEF1_SHIFT)
1078
1079 #define ISPRSZ_VFILT10_COEF0_SHIFT              0
1080 #define ISPRSZ_VFILT10_COEF0_MASK               0x3FF
1081 #define ISPRSZ_VFILT10_COEF1_SHIFT              16
1082 #define ISPRSZ_VFILT10_COEF1_MASK               0x3FF0000
1083
1084 #define ISPRSZ_VFILT32_COEF2_SHIFT              0
1085 #define ISPRSZ_VFILT32_COEF2_MASK               0x3FF
1086 #define ISPRSZ_VFILT32_COEF3_SHIFT              16
1087 #define ISPRSZ_VFILT32_COEF3_MASK               0x3FF0000
1088
1089 #define ISPRSZ_VFILT54_COEF4_SHIFT              0
1090 #define ISPRSZ_VFILT54_COEF4_MASK               0x3FF
1091 #define ISPRSZ_VFILT54_COEF5_SHIFT              16
1092 #define ISPRSZ_VFILT54_COEF5_MASK               0x3FF0000
1093
1094 #define ISPRSZ_VFILT76_COEFF6_SHIFT             0
1095 #define ISPRSZ_VFILT76_COEFF6_MASK              0x3FF
1096 #define ISPRSZ_VFILT76_COEFF7_SHIFT             16
1097 #define ISPRSZ_VFILT76_COEFF7_MASK              0x3FF0000
1098
1099 #define ISPRSZ_VFILT98_COEFF8_SHIFT             0
1100 #define ISPRSZ_VFILT98_COEFF8_MASK              0x3FF
1101 #define ISPRSZ_VFILT98_COEFF9_SHIFT             16
1102 #define ISPRSZ_VFILT98_COEFF9_MASK              0x3FF0000
1103
1104 #define ISPRSZ_VFILT1110_COEF10_SHIFT           0
1105 #define ISPRSZ_VFILT1110_COEF10_MASK            0x3FF
1106 #define ISPRSZ_VFILT1110_COEF11_SHIFT           16
1107 #define ISPRSZ_VFILT1110_COEF11_MASK            0x3FF0000
1108
1109 #define ISPRSZ_VFILT1312_COEFF12_SHIFT          0
1110 #define ISPRSZ_VFILT1312_COEFF12_MASK           0x3FF
1111 #define ISPRSZ_VFILT1312_COEFF13_SHIFT          16
1112 #define ISPRSZ_VFILT1312_COEFF13_MASK           0x3FF0000
1113
1114 #define ISPRSZ_VFILT1514_COEFF14_SHIFT          0
1115 #define ISPRSZ_VFILT1514_COEFF14_MASK           0x3FF
1116 #define ISPRSZ_VFILT1514_COEFF15_SHIFT          16
1117 #define ISPRSZ_VFILT1514_COEFF15_MASK           0x3FF0000
1118
1119 #define ISPRSZ_VFILT1716_COEF16_SHIFT           0
1120 #define ISPRSZ_VFILT1716_COEF16_MASK            0x3FF
1121 #define ISPRSZ_VFILT1716_COEF17_SHIFT           16
1122 #define ISPRSZ_VFILT1716_COEF17_MASK            0x3FF0000
1123
1124 #define ISPRSZ_VFILT1918_COEF18_SHIFT           0
1125 #define ISPRSZ_VFILT1918_COEF18_MASK            0x3FF
1126 #define ISPRSZ_VFILT1918_COEF19_SHIFT           16
1127 #define ISPRSZ_VFILT1918_COEF19_MASK            0x3FF0000
1128
1129 #define ISPRSZ_VFILT2120_COEF20_SHIFT           0
1130 #define ISPRSZ_VFILT2120_COEF20_MASK            0x3FF
1131 #define ISPRSZ_VFILT2120_COEF21_SHIFT           16
1132 #define ISPRSZ_VFILT2120_COEF21_MASK            0x3FF0000
1133
1134 #define ISPRSZ_VFILT2322_COEF22_SHIFT           0
1135 #define ISPRSZ_VFILT2322_COEF22_MASK            0x3FF
1136 #define ISPRSZ_VFILT2322_COEF23_SHIFT           16
1137 #define ISPRSZ_VFILT2322_COEF23_MASK            0x3FF0000
1138
1139 #define ISPRSZ_VFILT2524_COEF24_SHIFT           0
1140 #define ISPRSZ_VFILT2524_COEF24_MASK            0x3FF
1141 #define ISPRSZ_VFILT2524_COEF25_SHIFT           16
1142 #define ISPRSZ_VFILT2524_COEF25_MASK            0x3FF0000
1143
1144 #define ISPRSZ_VFILT2726_COEF26_SHIFT           0
1145 #define ISPRSZ_VFILT2726_COEF26_MASK            0x3FF
1146 #define ISPRSZ_VFILT2726_COEF27_SHIFT           16
1147 #define ISPRSZ_VFILT2726_COEF27_MASK            0x3FF0000
1148
1149 #define ISPRSZ_VFILT2928_COEF28_SHIFT           0
1150 #define ISPRSZ_VFILT2928_COEF28_MASK            0x3FF
1151 #define ISPRSZ_VFILT2928_COEF29_SHIFT           16
1152 #define ISPRSZ_VFILT2928_COEF29_MASK            0x3FF0000
1153
1154 #define ISPRSZ_VFILT3130_COEF30_SHIFT           0
1155 #define ISPRSZ_VFILT3130_COEF30_MASK            0x3FF
1156 #define ISPRSZ_VFILT3130_COEF31_SHIFT           16
1157 #define ISPRSZ_VFILT3130_COEF31_MASK            0x3FF0000
1158
1159 #define ISPRSZ_YENH_CORE_SHIFT                  0
1160 #define ISPRSZ_YENH_CORE_MASK                   \
1161         (0xFF << ISPRSZ_YENH_CORE_SHIFT)
1162 #define ISPRSZ_YENH_SLOP_SHIFT                  8
1163 #define ISPRSZ_YENH_SLOP_MASK                   \
1164         (0xF << ISPRSZ_YENH_SLOP_SHIFT)
1165 #define ISPRSZ_YENH_GAIN_SHIFT                  12
1166 #define ISPRSZ_YENH_GAIN_MASK                   \
1167         (0xF << ISPRSZ_YENH_GAIN_SHIFT)
1168 #define ISPRSZ_YENH_ALGO_SHIFT                  16
1169 #define ISPRSZ_YENH_ALGO_MASK                   \
1170         (0x3 << ISPRSZ_YENH_ALGO_SHIFT)
1171
1172 #define ISPH3A_PCR_AEW_ALAW_EN_SHIFT            1
1173 #define ISPH3A_PCR_AF_MED_TH_SHIFT              3
1174 #define ISPH3A_PCR_AF_RGBPOS_SHIFT              11
1175 #define ISPH3A_PCR_AEW_AVE2LMT_SHIFT            22
1176 #define ISPH3A_PCR_AEW_AVE2LMT_MASK             0xFFC00000
1177 #define ISPH3A_PCR_BUSYAF                       (1 << 15)
1178 #define ISPH3A_PCR_BUSYAEAWB                    (1 << 18)
1179
1180 #define ISPH3A_AEWWIN1_WINHC_SHIFT              0
1181 #define ISPH3A_AEWWIN1_WINHC_MASK               0x3F
1182 #define ISPH3A_AEWWIN1_WINVC_SHIFT              6
1183 #define ISPH3A_AEWWIN1_WINVC_MASK               0x1FC0
1184 #define ISPH3A_AEWWIN1_WINW_SHIFT               13
1185 #define ISPH3A_AEWWIN1_WINW_MASK                0xFE000
1186 #define ISPH3A_AEWWIN1_WINH_SHIFT               24
1187 #define ISPH3A_AEWWIN1_WINH_MASK                0x7F000000
1188
1189 #define ISPH3A_AEWINSTART_WINSH_SHIFT           0
1190 #define ISPH3A_AEWINSTART_WINSH_MASK            0x0FFF
1191 #define ISPH3A_AEWINSTART_WINSV_SHIFT           16
1192 #define ISPH3A_AEWINSTART_WINSV_MASK            0x0FFF0000
1193
1194 #define ISPH3A_AEWINBLK_WINH_SHIFT              0
1195 #define ISPH3A_AEWINBLK_WINH_MASK               0x7F
1196 #define ISPH3A_AEWINBLK_WINSV_SHIFT             16
1197 #define ISPH3A_AEWINBLK_WINSV_MASK              0x0FFF0000
1198
1199 #define ISPH3A_AEWSUBWIN_AEWINCH_SHIFT          0
1200 #define ISPH3A_AEWSUBWIN_AEWINCH_MASK           0x0F
1201 #define ISPH3A_AEWSUBWIN_AEWINCV_SHIFT          8
1202 #define ISPH3A_AEWSUBWIN_AEWINCV_MASK           0x0F00
1203
1204 #define ISPHIST_PCR_ENABLE_SHIFT        0
1205 #define ISPHIST_PCR_ENABLE_MASK         0x01
1206 #define ISPHIST_PCR_ENABLE              (1 << ISPHIST_PCR_ENABLE_SHIFT)
1207 #define ISPHIST_PCR_BUSY                0x02
1208
1209 #define ISPHIST_CNT_DATASIZE_SHIFT      8
1210 #define ISPHIST_CNT_DATASIZE_MASK       0x0100
1211 #define ISPHIST_CNT_CLEAR_SHIFT         7
1212 #define ISPHIST_CNT_CLEAR_MASK          0x080
1213 #define ISPHIST_CNT_CLEAR               (1 << ISPHIST_CNT_CLEAR_SHIFT)
1214 #define ISPHIST_CNT_CFA_SHIFT           6
1215 #define ISPHIST_CNT_CFA_MASK            0x040
1216 #define ISPHIST_CNT_BINS_SHIFT          4
1217 #define ISPHIST_CNT_BINS_MASK           0x030
1218 #define ISPHIST_CNT_SOURCE_SHIFT        3
1219 #define ISPHIST_CNT_SOURCE_MASK         0x08
1220 #define ISPHIST_CNT_SHIFT_SHIFT         0
1221 #define ISPHIST_CNT_SHIFT_MASK          0x07
1222
1223 #define ISPHIST_WB_GAIN_WG00_SHIFT      24
1224 #define ISPHIST_WB_GAIN_WG00_MASK       0xFF000000
1225 #define ISPHIST_WB_GAIN_WG01_SHIFT      16
1226 #define ISPHIST_WB_GAIN_WG01_MASK       0xFF0000
1227 #define ISPHIST_WB_GAIN_WG02_SHIFT      8
1228 #define ISPHIST_WB_GAIN_WG02_MASK       0xFF00
1229 #define ISPHIST_WB_GAIN_WG03_SHIFT      0
1230 #define ISPHIST_WB_GAIN_WG03_MASK       0xFF
1231
1232 #define ISPHIST_REG_START_END_MASK              0x3FFF
1233 #define ISPHIST_REG_START_SHIFT                 16
1234 #define ISPHIST_REG_END_SHIFT                   0
1235 #define ISPHIST_REG_START_MASK                  (ISPHIST_REG_START_END_MASK << \
1236                                                  ISPHIST_REG_START_SHIFT)
1237 #define ISPHIST_REG_END_MASK                    (ISPHIST_REG_START_END_MASK << \
1238                                                  ISPHIST_REG_END_SHIFT)
1239
1240 #define ISPHIST_REG_MASK                        (ISPHIST_REG_START_MASK | \
1241                                                  ISPHIST_REG_END_MASK)
1242
1243 #define ISPHIST_ADDR_SHIFT                      0
1244 #define ISPHIST_ADDR_MASK                       0x3FF
1245
1246 #define ISPHIST_DATA_SHIFT                      0
1247 #define ISPHIST_DATA_MASK                       0xFFFFF
1248
1249 #define ISPHIST_RADD_SHIFT                      0
1250 #define ISPHIST_RADD_MASK                       0xFFFFFFFF
1251
1252 #define ISPHIST_RADD_OFF_SHIFT                  0
1253 #define ISPHIST_RADD_OFF_MASK                   0xFFFF
1254
1255 #define ISPHIST_HV_INFO_HSIZE_SHIFT             16
1256 #define ISPHIST_HV_INFO_HSIZE_MASK              0x3FFF0000
1257 #define ISPHIST_HV_INFO_VSIZE_SHIFT             0
1258 #define ISPHIST_HV_INFO_VSIZE_MASK              0x3FFF
1259
1260 #define ISPHIST_HV_INFO_MASK                    0x3FFF3FFF
1261
1262 #define ISPCCDC_LSC_ENABLE                      1
1263 #define ISPCCDC_LSC_BUSY                        (1 << 7)
1264 #define ISPCCDC_LSC_GAIN_MODE_N_MASK            0x700
1265 #define ISPCCDC_LSC_GAIN_MODE_N_SHIFT           8
1266 #define ISPCCDC_LSC_GAIN_MODE_M_MASK            0x3800
1267 #define ISPCCDC_LSC_GAIN_MODE_M_SHIFT           12
1268 #define ISPCCDC_LSC_GAIN_FORMAT_MASK            0xE
1269 #define ISPCCDC_LSC_GAIN_FORMAT_SHIFT           1
1270 #define ISPCCDC_LSC_AFTER_REFORMATTER_MASK      (1<<6)
1271
1272 #define ISPCCDC_LSC_INITIAL_X_MASK              0x3F
1273 #define ISPCCDC_LSC_INITIAL_X_SHIFT             0
1274 #define ISPCCDC_LSC_INITIAL_Y_MASK              0x3F0000
1275 #define ISPCCDC_LSC_INITIAL_Y_SHIFT             16
1276
1277 /* -----------------------------------------------------------------------------
1278  * CSI2 receiver registers (ES2.0)
1279  */
1280
1281 #define ISPCSI2_REVISION                        (0x000)
1282 #define ISPCSI2_SYSCONFIG                       (0x010)
1283 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT   12
1284 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK    \
1285         (0x3 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1286 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_FORCE   \
1287         (0x0 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1288 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO      \
1289         (0x1 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1290 #define ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART   \
1291         (0x2 << ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SHIFT)
1292 #define ISPCSI2_SYSCONFIG_SOFT_RESET            (1 << 1)
1293 #define ISPCSI2_SYSCONFIG_AUTO_IDLE             (1 << 0)
1294
1295 #define ISPCSI2_SYSSTATUS                       (0x014)
1296 #define ISPCSI2_SYSSTATUS_RESET_DONE            (1 << 0)
1297
1298 #define ISPCSI2_IRQSTATUS                       (0x018)
1299 #define ISPCSI2_IRQSTATUS_OCP_ERR_IRQ           (1 << 14)
1300 #define ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ      (1 << 13)
1301 #define ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ    (1 << 12)
1302 #define ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ (1 << 11)
1303 #define ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ    (1 << 10)
1304 #define ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ    (1 << 9)
1305 #define ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ          (1 << 8)
1306 #define ISPCSI2_IRQSTATUS_CONTEXT(n)            (1 << (n))
1307
1308 #define ISPCSI2_IRQENABLE                       (0x01c)
1309 #define ISPCSI2_CTRL                            (0x040)
1310 #define ISPCSI2_CTRL_VP_CLK_EN                  (1 << 15)
1311 #define ISPCSI2_CTRL_VP_ONLY_EN                 (1 << 11)
1312 #define ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT          8
1313 #define ISPCSI2_CTRL_VP_OUT_CTRL_MASK           \
1314         (3 << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT)
1315 #define ISPCSI2_CTRL_DBG_EN                     (1 << 7)
1316 #define ISPCSI2_CTRL_BURST_SIZE_SHIFT           5
1317 #define ISPCSI2_CTRL_BURST_SIZE_MASK            \
1318         (3 << ISPCSI2_CTRL_BURST_SIZE_SHIFT)
1319 #define ISPCSI2_CTRL_FRAME                      (1 << 3)
1320 #define ISPCSI2_CTRL_ECC_EN                     (1 << 2)
1321 #define ISPCSI2_CTRL_SECURE                     (1 << 1)
1322 #define ISPCSI2_CTRL_IF_EN                      (1 << 0)
1323
1324 #define ISPCSI2_DBG_H                           (0x044)
1325 #define ISPCSI2_GNQ                             (0x048)
1326 #define ISPCSI2_PHY_CFG                         (0x050)
1327 #define ISPCSI2_PHY_CFG_RESET_CTRL              (1 << 30)
1328 #define ISPCSI2_PHY_CFG_RESET_DONE              (1 << 29)
1329 #define ISPCSI2_PHY_CFG_PWR_CMD_SHIFT           27
1330 #define ISPCSI2_PHY_CFG_PWR_CMD_MASK            \
1331         (0x3 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1332 #define ISPCSI2_PHY_CFG_PWR_CMD_OFF             \
1333         (0x0 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1334 #define ISPCSI2_PHY_CFG_PWR_CMD_ON              \
1335         (0x1 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1336 #define ISPCSI2_PHY_CFG_PWR_CMD_ULPW            \
1337         (0x2 << ISPCSI2_PHY_CFG_PWR_CMD_SHIFT)
1338 #define ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT        25
1339 #define ISPCSI2_PHY_CFG_PWR_STATUS_MASK         \
1340         (0x3 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1341 #define ISPCSI2_PHY_CFG_PWR_STATUS_OFF          \
1342         (0x0 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1343 #define ISPCSI2_PHY_CFG_PWR_STATUS_ON           \
1344         (0x1 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1345 #define ISPCSI2_PHY_CFG_PWR_STATUS_ULPW         \
1346         (0x2 << ISPCSI2_PHY_CFG_PWR_STATUS_SHIFT)
1347 #define ISPCSI2_PHY_CFG_PWR_AUTO                (1 << 24)
1348
1349 #define ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n)       (3 + ((n) * 4))
1350 #define ISPCSI2_PHY_CFG_DATA_POL_MASK(n)        \
1351         (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1352 #define ISPCSI2_PHY_CFG_DATA_POL_PN(n)          \
1353         (0x0 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1354 #define ISPCSI2_PHY_CFG_DATA_POL_NP(n)          \
1355         (0x1 << ISPCSI2_PHY_CFG_DATA_POL_SHIFT(n))
1356
1357 #define ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n)  ((n) * 4)
1358 #define ISPCSI2_PHY_CFG_DATA_POSITION_MASK(n)   \
1359         (0x7 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1360 #define ISPCSI2_PHY_CFG_DATA_POSITION_NC(n)     \
1361         (0x0 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1362 #define ISPCSI2_PHY_CFG_DATA_POSITION_1(n)      \
1363         (0x1 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1364 #define ISPCSI2_PHY_CFG_DATA_POSITION_2(n)      \
1365         (0x2 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1366 #define ISPCSI2_PHY_CFG_DATA_POSITION_3(n)      \
1367         (0x3 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1368 #define ISPCSI2_PHY_CFG_DATA_POSITION_4(n)      \
1369         (0x4 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1370 #define ISPCSI2_PHY_CFG_DATA_POSITION_5(n)      \
1371         (0x5 << ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(n))
1372
1373 #define ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT         3
1374 #define ISPCSI2_PHY_CFG_CLOCK_POL_MASK          \
1375         (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1376 #define ISPCSI2_PHY_CFG_CLOCK_POL_PN            \
1377         (0x0 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1378 #define ISPCSI2_PHY_CFG_CLOCK_POL_NP            \
1379         (0x1 << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT)
1380
1381 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT    0
1382 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK     \
1383         (0x7 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1384 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_1        \
1385         (0x1 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1386 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_2        \
1387         (0x2 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1388 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_3        \
1389         (0x3 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1390 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_4        \
1391         (0x4 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1392 #define ISPCSI2_PHY_CFG_CLOCK_POSITION_5        \
1393         (0x5 << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT)
1394
1395 #define ISPCSI2_PHY_IRQSTATUS                   (0x054)
1396 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMEXIT  (1 << 26)
1397 #define ISPCSI2_PHY_IRQSTATUS_STATEALLULPMENTER (1 << 25)
1398 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM5        (1 << 24)
1399 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM4        (1 << 23)
1400 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM3        (1 << 22)
1401 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM2        (1 << 21)
1402 #define ISPCSI2_PHY_IRQSTATUS_STATEULPM1        (1 << 20)
1403 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL5       (1 << 19)
1404 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL4       (1 << 18)
1405 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL3       (1 << 17)
1406 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL2       (1 << 16)
1407 #define ISPCSI2_PHY_IRQSTATUS_ERRCONTROL1       (1 << 15)
1408 #define ISPCSI2_PHY_IRQSTATUS_ERRESC5           (1 << 14)
1409 #define ISPCSI2_PHY_IRQSTATUS_ERRESC4           (1 << 13)
1410 #define ISPCSI2_PHY_IRQSTATUS_ERRESC3           (1 << 12)
1411 #define ISPCSI2_PHY_IRQSTATUS_ERRESC2           (1 << 11)
1412 #define ISPCSI2_PHY_IRQSTATUS_ERRESC1           (1 << 10)
1413 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS5     (1 << 9)
1414 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS4     (1 << 8)
1415 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS3     (1 << 7)
1416 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS2     (1 << 6)
1417 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTSYNCHS1     (1 << 5)
1418 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS5         (1 << 4)
1419 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS4         (1 << 3)
1420 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS3         (1 << 2)
1421 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS2         (1 << 1)
1422 #define ISPCSI2_PHY_IRQSTATUS_ERRSOTHS1         1
1423
1424 #define ISPCSI2_SHORT_PACKET                    (0x05c)
1425 #define ISPCSI2_PHY_IRQENABLE                   (0x060)
1426 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT  (1 << 26)
1427 #define ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER (1 << 25)
1428 #define ISPCSI2_PHY_IRQENABLE_STATEULPM5        (1 << 24)
1429 #define ISPCSI2_PHY_IRQENABLE_STATEULPM4        (1 << 23)
1430 #define ISPCSI2_PHY_IRQENABLE_STATEULPM3        (1 << 22)
1431 #define ISPCSI2_PHY_IRQENABLE_STATEULPM2        (1 << 21)
1432 #define ISPCSI2_PHY_IRQENABLE_STATEULPM1        (1 << 20)
1433 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL5       (1 << 19)
1434 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL4       (1 << 18)
1435 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL3       (1 << 17)
1436 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL2       (1 << 16)
1437 #define ISPCSI2_PHY_IRQENABLE_ERRCONTROL1       (1 << 15)
1438 #define ISPCSI2_PHY_IRQENABLE_ERRESC5           (1 << 14)
1439 #define ISPCSI2_PHY_IRQENABLE_ERRESC4           (1 << 13)
1440 #define ISPCSI2_PHY_IRQENABLE_ERRESC3           (1 << 12)
1441 #define ISPCSI2_PHY_IRQENABLE_ERRESC2           (1 << 11)
1442 #define ISPCSI2_PHY_IRQENABLE_ERRESC1           (1 << 10)
1443 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5     (1 << 9)
1444 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4     (1 << 8)
1445 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3     (1 << 7)
1446 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2     (1 << 6)
1447 #define ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1     (1 << 5)
1448 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS5         (1 << 4)
1449 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS4         (1 << 3)
1450 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS3         (1 << 2)
1451 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS2         (1 << 1)
1452 #define ISPCSI2_PHY_IRQENABLE_ERRSOTHS1         (1 << 0)
1453
1454 #define ISPCSI2_DBG_P                           (0x068)
1455 #define ISPCSI2_TIMING                          (0x06c)
1456 #define ISPCSI2_TIMING_FORCE_RX_MODE_IO(n)      (1 << ((16 * ((n) - 1)) + 15))
1457 #define ISPCSI2_TIMING_STOP_STATE_X16_IO(n)     (1 << ((16 * ((n) - 1)) + 14))
1458 #define ISPCSI2_TIMING_STOP_STATE_X4_IO(n)      (1 << ((16 * ((n) - 1)) + 13))
1459 #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n)   (16 * ((n) - 1))
1460 #define ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(n)    \
1461         (0x1fff << ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(n))
1462
1463 #define ISPCSI2_CTX_CTRL1(n)                    ((0x070) + 0x20 * (n))
1464 #define ISPCSI2_CTX_CTRL1_COUNT_SHIFT           8
1465 #define ISPCSI2_CTX_CTRL1_COUNT_MASK            \
1466         (0xff << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
1467 #define ISPCSI2_CTX_CTRL1_EOF_EN                (1 << 7)
1468 #define ISPCSI2_CTX_CTRL1_EOL_EN                (1 << 6)
1469 #define ISPCSI2_CTX_CTRL1_CS_EN                 (1 << 5)
1470 #define ISPCSI2_CTX_CTRL1_COUNT_UNLOCK          (1 << 4)
1471 #define ISPCSI2_CTX_CTRL1_PING_PONG             (1 << 3)
1472 #define ISPCSI2_CTX_CTRL1_CTX_EN                (1 << 0)
1473
1474 #define ISPCSI2_CTX_CTRL2(n)                    ((0x074) + 0x20 * (n))
1475 #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT    13
1476 #define ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK     \
1477         (0x3 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT)
1478 #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT      11
1479 #define ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK       \
1480         (0x3 << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT)
1481 #define ISPCSI2_CTX_CTRL2_DPCM_PRED             (1 << 10)
1482 #define ISPCSI2_CTX_CTRL2_FORMAT_SHIFT          0
1483 #define ISPCSI2_CTX_CTRL2_FORMAT_MASK           \
1484         (0x3ff << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT)
1485 #define ISPCSI2_CTX_CTRL2_FRAME_SHIFT           16
1486 #define ISPCSI2_CTX_CTRL2_FRAME_MASK            \
1487         (0xffff << ISPCSI2_CTX_CTRL2_FRAME_SHIFT)
1488
1489 #define ISPCSI2_CTX_DAT_OFST(n)                 ((0x078) + 0x20 * (n))
1490 #define ISPCSI2_CTX_DAT_OFST_OFST_SHIFT         0
1491 #define ISPCSI2_CTX_DAT_OFST_OFST_MASK          \
1492         (0x1ffe0 << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT)
1493
1494 #define ISPCSI2_CTX_DAT_PING_ADDR(n)            ((0x07c) + 0x20 * (n))
1495 #define ISPCSI2_CTX_DAT_PONG_ADDR(n)            ((0x080) + 0x20 * (n))
1496 #define ISPCSI2_CTX_IRQENABLE(n)                ((0x084) + 0x20 * (n))
1497 #define ISPCSI2_CTX_IRQENABLE_ECC_CORRECTION_IRQ        (1 << 8)
1498 #define ISPCSI2_CTX_IRQENABLE_LINE_NUMBER_IRQ   (1 << 7)
1499 #define ISPCSI2_CTX_IRQENABLE_FRAME_NUMBER_IRQ  (1 << 6)
1500 #define ISPCSI2_CTX_IRQENABLE_CS_IRQ            (1 << 5)
1501 #define ISPCSI2_CTX_IRQENABLE_LE_IRQ            (1 << 3)
1502 #define ISPCSI2_CTX_IRQENABLE_LS_IRQ            (1 << 2)
1503 #define ISPCSI2_CTX_IRQENABLE_FE_IRQ            (1 << 1)
1504 #define ISPCSI2_CTX_IRQENABLE_FS_IRQ            (1 << 0)
1505
1506 #define ISPCSI2_CTX_IRQSTATUS(n)                ((0x088) + 0x20 * (n))
1507 #define ISPCSI2_CTX_IRQSTATUS_ECC_CORRECTION_IRQ        (1 << 8)
1508 #define ISPCSI2_CTX_IRQSTATUS_LINE_NUMBER_IRQ   (1 << 7)
1509 #define ISPCSI2_CTX_IRQSTATUS_FRAME_NUMBER_IRQ  (1 << 6)
1510 #define ISPCSI2_CTX_IRQSTATUS_CS_IRQ            (1 << 5)
1511 #define ISPCSI2_CTX_IRQSTATUS_LE_IRQ            (1 << 3)
1512 #define ISPCSI2_CTX_IRQSTATUS_LS_IRQ            (1 << 2)
1513 #define ISPCSI2_CTX_IRQSTATUS_FE_IRQ            (1 << 1)
1514 #define ISPCSI2_CTX_IRQSTATUS_FS_IRQ            (1 << 0)
1515
1516 #define ISPCSI2_CTX_CTRL3(n)                    ((0x08c) + 0x20 * (n))
1517 #define ISPCSI2_CTX_CTRL3_ALPHA_SHIFT           5
1518 #define ISPCSI2_CTX_CTRL3_ALPHA_MASK            \
1519         (0x3fff << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT)
1520
1521 /* This instance is for OMAP3630 only */
1522 #define ISPCSI2_CTX_TRANSCODEH(n)               (0x000 + 0x8 * (n))
1523 #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT     16
1524 #define ISPCSI2_CTX_TRANSCODEH_HCOUNT_MASK      \
1525         (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1526 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_SHIFT      0
1527 #define ISPCSI2_CTX_TRANSCODEH_HSKIP_MASK       \
1528         (0x1fff << ISPCSI2_CTX_TRANSCODEH_HCOUNT_SHIFT)
1529 #define ISPCSI2_CTX_TRANSCODEV(n)               (0x004 + 0x8 * (n))
1530 #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT     16
1531 #define ISPCSI2_CTX_TRANSCODEV_VCOUNT_MASK      \
1532         (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1533 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_SHIFT      0
1534 #define ISPCSI2_CTX_TRANSCODEV_VSKIP_MASK       \
1535         (0x1fff << ISPCSI2_CTX_TRANSCODEV_VCOUNT_SHIFT)
1536
1537 /* -----------------------------------------------------------------------------
1538  * CSI PHY registers
1539  */
1540
1541 #define ISPCSIPHY_REG0                          (0x000)
1542 #define ISPCSIPHY_REG0_THS_TERM_SHIFT           8
1543 #define ISPCSIPHY_REG0_THS_TERM_MASK            \
1544         (0xff << ISPCSIPHY_REG0_THS_TERM_SHIFT)
1545 #define ISPCSIPHY_REG0_THS_SETTLE_SHIFT         0
1546 #define ISPCSIPHY_REG0_THS_SETTLE_MASK          \
1547         (0xff << ISPCSIPHY_REG0_THS_SETTLE_SHIFT)
1548
1549 #define ISPCSIPHY_REG1                                  (0x004)
1550 #define ISPCSIPHY_REG1_RESET_DONE_CTRLCLK               (1 << 29)
1551 /* This field is for OMAP3630 only */
1552 #define ISPCSIPHY_REG1_CLOCK_MISS_DETECTOR_STATUS       (1 << 25)
1553 #define ISPCSIPHY_REG1_TCLK_TERM_SHIFT                  18
1554 #define ISPCSIPHY_REG1_TCLK_TERM_MASK                   \
1555         (0x7f << ISPCSIPHY_REG1_TCLK_TERM_SHIFT)
1556 #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_SHIFT       10
1557 #define ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN_MASK        \
1558         (0xff << ISPCSIPHY_REG1_DPHY_HS_SYNC_PATTERN)
1559 /* This field is for OMAP3430 only */
1560 #define ISPCSIPHY_REG1_TCLK_MISS_SHIFT                  8
1561 #define ISPCSIPHY_REG1_TCLK_MISS_MASK                   \
1562         (0x3 << ISPCSIPHY_REG1_TCLK_MISS_SHIFT)
1563 /* This field is for OMAP3630 only */
1564 #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT         8
1565 #define ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_MASK          \
1566         (0x3 << ISPCSIPHY_REG1_CTRLCLK_DIV_FACTOR_SHIFT)
1567 #define ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT                0
1568 #define ISPCSIPHY_REG1_TCLK_SETTLE_MASK                 \
1569         (0xff << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT)
1570
1571 /* This register is for OMAP3630 only */
1572 #define ISPCSIPHY_REG2                                  (0x008)
1573 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT     30
1574 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK      \
1575         (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC0_SHIFT)
1576 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT     28
1577 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK      \
1578         (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC1_SHIFT)
1579 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT     26
1580 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK      \
1581         (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC2_SHIFT)
1582 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT     24
1583 #define ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK      \
1584         (0x3 << ISPCSIPHY_REG2_TRIGGER_CMD_RXTRIGESC3_SHIFT)
1585 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT          0
1586 #define ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_MASK           \
1587         (0x7fffff << ISPCSIPHY_REG2_CCP2_SYNC_PATTERN_SHIFT)
1588
1589 #endif  /* OMAP3_ISP_REG_H */