2 $Id: cx88-reg.h,v 1.8 2005/07/07 13:58:38 mchehab Exp $
4 cx88x-hw.h - CX2388x register offsets
6 Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
8 2002 Yurij Sysoev <yurij@naturesoft.net>
9 2003 Gerd Knorr <kraxel@bytesex.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 /* ---------------------------------------------------------------------- */
30 /* PCI IDs and config space */
32 #ifndef PCI_VENDOR_ID_CONEXANT
33 # define PCI_VENDOR_ID_CONEXANT 0x14F1
35 #ifndef PCI_DEVICE_ID_CX2300_VID
36 # define PCI_DEVICE_ID_CX2300_VID 0x8800
39 #define CX88X_DEVCTRL 0x40
40 #define CX88X_EN_TBFX 0x02
41 #define CX88X_EN_VSFX 0x04
44 /* ---------------------------------------------------------------------- */
45 /* DMA Controller registers */
47 #define MO_PDMA_STHRSH 0x200000 // Source threshold
48 #define MO_PDMA_STADRS 0x200004 // Source target address
49 #define MO_PDMA_SIADRS 0x200008 // Source internal address
50 #define MO_PDMA_SCNTRL 0x20000C // Source control
51 #define MO_PDMA_DTHRSH 0x200010 // Destination threshold
52 #define MO_PDMA_DTADRS 0x200014 // Destination target address
53 #define MO_PDMA_DIADRS 0x200018 // Destination internal address
54 #define MO_PDMA_DCNTRL 0x20001C // Destination control
55 #define MO_LD_SSID 0x200030 // Load subsystem ID
56 #define MO_DEV_CNTRL2 0x200034 // Device control
57 #define MO_PCI_INTMSK 0x200040 // PCI interrupt mask
58 #define MO_PCI_INTSTAT 0x200044 // PCI interrupt status
59 #define MO_PCI_INTMSTAT 0x200048 // PCI interrupt masked status
60 #define MO_VID_INTMSK 0x200050 // Video interrupt mask
61 #define MO_VID_INTSTAT 0x200054 // Video interrupt status
62 #define MO_VID_INTMSTAT 0x200058 // Video interrupt masked status
63 #define MO_VID_INTSSTAT 0x20005C // Video interrupt set status
64 #define MO_AUD_INTMSK 0x200060 // Audio interrupt mask
65 #define MO_AUD_INTSTAT 0x200064 // Audio interrupt status
66 #define MO_AUD_INTMSTAT 0x200068 // Audio interrupt masked status
67 #define MO_AUD_INTSSTAT 0x20006C // Audio interrupt set status
68 #define MO_TS_INTMSK 0x200070 // Transport stream interrupt mask
69 #define MO_TS_INTSTAT 0x200074 // Transport stream interrupt status
70 #define MO_TS_INTMSTAT 0x200078 // Transport stream interrupt mask status
71 #define MO_TS_INTSSTAT 0x20007C // Transport stream interrupt set status
72 #define MO_VIP_INTMSK 0x200080 // VIP interrupt mask
73 #define MO_VIP_INTSTAT 0x200084 // VIP interrupt status
74 #define MO_VIP_INTMSTAT 0x200088 // VIP interrupt masked status
75 #define MO_VIP_INTSSTAT 0x20008C // VIP interrupt set status
76 #define MO_GPHST_INTMSK 0x200090 // Host interrupt mask
77 #define MO_GPHST_INTSTAT 0x200094 // Host interrupt status
78 #define MO_GPHST_INTMSTAT 0x200098 // Host interrupt masked status
79 #define MO_GPHST_INTSSTAT 0x20009C // Host interrupt set status
81 // DMA Channels 1-6 belong to SPIPE
82 #define MO_DMA7_PTR1 0x300018 // {24}RW* DMA Current Ptr : Ch#7
83 #define MO_DMA8_PTR1 0x30001C // {24}RW* DMA Current Ptr : Ch#8
85 // DMA Channels 9-20 belong to SPIPE
86 #define MO_DMA21_PTR1 0x300080 // {24}R0* DMA Current Ptr : Ch#21
87 #define MO_DMA22_PTR1 0x300084 // {24}R0* DMA Current Ptr : Ch#22
88 #define MO_DMA23_PTR1 0x300088 // {24}R0* DMA Current Ptr : Ch#23
89 #define MO_DMA24_PTR1 0x30008C // {24}R0* DMA Current Ptr : Ch#24
90 #define MO_DMA25_PTR1 0x300090 // {24}R0* DMA Current Ptr : Ch#25
91 #define MO_DMA26_PTR1 0x300094 // {24}R0* DMA Current Ptr : Ch#26
92 #define MO_DMA27_PTR1 0x300098 // {24}R0* DMA Current Ptr : Ch#27
93 #define MO_DMA28_PTR1 0x30009C // {24}R0* DMA Current Ptr : Ch#28
94 #define MO_DMA29_PTR1 0x3000A0 // {24}R0* DMA Current Ptr : Ch#29
95 #define MO_DMA30_PTR1 0x3000A4 // {24}R0* DMA Current Ptr : Ch#30
96 #define MO_DMA31_PTR1 0x3000A8 // {24}R0* DMA Current Ptr : Ch#31
97 #define MO_DMA32_PTR1 0x3000AC // {24}R0* DMA Current Ptr : Ch#32
99 #define MO_DMA21_PTR2 0x3000C0 // {24}RW* DMA Tab Ptr : Ch#21
100 #define MO_DMA22_PTR2 0x3000C4 // {24}RW* DMA Tab Ptr : Ch#22
101 #define MO_DMA23_PTR2 0x3000C8 // {24}RW* DMA Tab Ptr : Ch#23
102 #define MO_DMA24_PTR2 0x3000CC // {24}RW* DMA Tab Ptr : Ch#24
103 #define MO_DMA25_PTR2 0x3000D0 // {24}RW* DMA Tab Ptr : Ch#25
104 #define MO_DMA26_PTR2 0x3000D4 // {24}RW* DMA Tab Ptr : Ch#26
105 #define MO_DMA27_PTR2 0x3000D8 // {24}RW* DMA Tab Ptr : Ch#27
106 #define MO_DMA28_PTR2 0x3000DC // {24}RW* DMA Tab Ptr : Ch#28
107 #define MO_DMA29_PTR2 0x3000E0 // {24}RW* DMA Tab Ptr : Ch#29
108 #define MO_DMA30_PTR2 0x3000E4 // {24}RW* DMA Tab Ptr : Ch#30
109 #define MO_DMA31_PTR2 0x3000E8 // {24}RW* DMA Tab Ptr : Ch#31
110 #define MO_DMA32_PTR2 0x3000EC // {24}RW* DMA Tab Ptr : Ch#32
112 #define MO_DMA21_CNT1 0x300100 // {11}RW* DMA Buffer Size : Ch#21
113 #define MO_DMA22_CNT1 0x300104 // {11}RW* DMA Buffer Size : Ch#22
114 #define MO_DMA23_CNT1 0x300108 // {11}RW* DMA Buffer Size : Ch#23
115 #define MO_DMA24_CNT1 0x30010C // {11}RW* DMA Buffer Size : Ch#24
116 #define MO_DMA25_CNT1 0x300110 // {11}RW* DMA Buffer Size : Ch#25
117 #define MO_DMA26_CNT1 0x300114 // {11}RW* DMA Buffer Size : Ch#26
118 #define MO_DMA27_CNT1 0x300118 // {11}RW* DMA Buffer Size : Ch#27
119 #define MO_DMA28_CNT1 0x30011C // {11}RW* DMA Buffer Size : Ch#28
120 #define MO_DMA29_CNT1 0x300120 // {11}RW* DMA Buffer Size : Ch#29
121 #define MO_DMA30_CNT1 0x300124 // {11}RW* DMA Buffer Size : Ch#30
122 #define MO_DMA31_CNT1 0x300128 // {11}RW* DMA Buffer Size : Ch#31
123 #define MO_DMA32_CNT1 0x30012C // {11}RW* DMA Buffer Size : Ch#32
125 #define MO_DMA21_CNT2 0x300140 // {11}RW* DMA Table Size : Ch#21
126 #define MO_DMA22_CNT2 0x300144 // {11}RW* DMA Table Size : Ch#22
127 #define MO_DMA23_CNT2 0x300148 // {11}RW* DMA Table Size : Ch#23
128 #define MO_DMA24_CNT2 0x30014C // {11}RW* DMA Table Size : Ch#24
129 #define MO_DMA25_CNT2 0x300150 // {11}RW* DMA Table Size : Ch#25
130 #define MO_DMA26_CNT2 0x300154 // {11}RW* DMA Table Size : Ch#26
131 #define MO_DMA27_CNT2 0x300158 // {11}RW* DMA Table Size : Ch#27
132 #define MO_DMA28_CNT2 0x30015C // {11}RW* DMA Table Size : Ch#28
133 #define MO_DMA29_CNT2 0x300160 // {11}RW* DMA Table Size : Ch#29
134 #define MO_DMA30_CNT2 0x300164 // {11}RW* DMA Table Size : Ch#30
135 #define MO_DMA31_CNT2 0x300168 // {11}RW* DMA Table Size : Ch#31
136 #define MO_DMA32_CNT2 0x30016C // {11}RW* DMA Table Size : Ch#32
139 /* ---------------------------------------------------------------------- */
140 /* Video registers */
142 #define MO_VIDY_DMA 0x310000 // {64}RWp Video Y
143 #define MO_VIDU_DMA 0x310008 // {64}RWp Video U
144 #define MO_VIDV_DMA 0x310010 // {64}RWp Video V
145 #define MO_VBI_DMA 0x310018 // {64}RWp VBI (Vertical blanking interval)
147 #define MO_DEVICE_STATUS 0x310100
148 #define MO_INPUT_FORMAT 0x310104
149 #define MO_AGC_BURST 0x31010c
150 #define MO_CONTR_BRIGHT 0x310110
151 #define MO_UV_SATURATION 0x310114
152 #define MO_HUE 0x310118
153 #define MO_HTOTAL 0x310120
154 #define MO_HDELAY_EVEN 0x310124
155 #define MO_HDELAY_ODD 0x310128
156 #define MO_VDELAY_ODD 0x31012c
157 #define MO_VDELAY_EVEN 0x310130
158 #define MO_HACTIVE_EVEN 0x31013c
159 #define MO_HACTIVE_ODD 0x310140
160 #define MO_VACTIVE_EVEN 0x310144
161 #define MO_VACTIVE_ODD 0x310148
162 #define MO_HSCALE_EVEN 0x31014c
163 #define MO_HSCALE_ODD 0x310150
164 #define MO_VSCALE_EVEN 0x310154
165 #define MO_FILTER_EVEN 0x31015c
166 #define MO_VSCALE_ODD 0x310158
167 #define MO_FILTER_ODD 0x310160
168 #define MO_OUTPUT_FORMAT 0x310164
170 #define MO_PLL_REG 0x310168 // PLL register
171 #define MO_PLL_ADJ_CTRL 0x31016c // PLL adjust control register
172 #define MO_SCONV_REG 0x310170 // sample rate conversion register
173 #define MO_SCONV_FIFO 0x310174 // sample rate conversion fifo
174 #define MO_SUB_STEP 0x310178 // subcarrier step size
175 #define MO_SUB_STEP_DR 0x31017c // subcarrier step size for DR line
177 #define MO_CAPTURE_CTRL 0x310180 // capture control
178 #define MO_COLOR_CTRL 0x310184
179 #define MO_VBI_PACKET 0x310188 // vbi packet size / delay
180 #define MO_FIELD_COUNT 0x310190 // field counter
181 #define MO_VIP_CONFIG 0x310194
182 #define MO_VBOS_CONTROL 0x3101a8
184 #define MO_AGC_BACK_VBI 0x310200
185 #define MO_AGC_SYNC_TIP1 0x310208
187 #define MO_VIDY_GPCNT 0x31C020 // {16}RO Video Y general purpose counter
188 #define MO_VIDU_GPCNT 0x31C024 // {16}RO Video U general purpose counter
189 #define MO_VIDV_GPCNT 0x31C028 // {16}RO Video V general purpose counter
190 #define MO_VBI_GPCNT 0x31C02C // {16}RO VBI general purpose counter
191 #define MO_VIDY_GPCNTRL 0x31C030 // {2}WO Video Y general purpose control
192 #define MO_VIDU_GPCNTRL 0x31C034 // {2}WO Video U general purpose control
193 #define MO_VIDV_GPCNTRL 0x31C038 // {2}WO Video V general purpose control
194 #define MO_VBI_GPCNTRL 0x31C03C // {2}WO VBI general purpose counter
195 #define MO_VID_DMACNTRL 0x31C040 // {8}RW Video DMA control
196 #define MO_VID_XFR_STAT 0x31C044 // {1}RO Video transfer status
199 /* ---------------------------------------------------------------------- */
200 /* audio registers */
202 #define MO_AUDD_DMA 0x320000 // {64}RWp Audio downstream
203 #define MO_AUDU_DMA 0x320008 // {64}RWp Audio upstream
204 #define MO_AUDR_DMA 0x320010 // {64}RWp Audio RDS (downstream)
205 #define MO_AUDD_GPCNT 0x32C020 // {16}RO Audio down general purpose counter
206 #define MO_AUDU_GPCNT 0x32C024 // {16}RO Audio up general purpose counter
207 #define MO_AUDR_GPCNT 0x32C028 // {16}RO Audio RDS general purpose counter
208 #define MO_AUDD_GPCNTRL 0x32C030 // {2}WO Audio down general purpose control
209 #define MO_AUDU_GPCNTRL 0x32C034 // {2}WO Audio up general purpose control
210 #define MO_AUDR_GPCNTRL 0x32C038 // {2}WO Audio RDS general purpose control
211 #define MO_AUD_DMACNTRL 0x32C040 // {6}RW Audio DMA control
212 #define MO_AUD_XFR_STAT 0x32C044 // {1}RO Audio transfer status
213 #define MO_AUDD_LNGTH 0x32C048 // {12}RW Audio down line length
214 #define MO_AUDR_LNGTH 0x32C04C // {12}RW Audio RDS line length
216 #define AUD_INIT 0x320100
217 #define AUD_INIT_LD 0x320104
218 #define AUD_SOFT_RESET 0x320108
219 #define AUD_I2SINPUTCNTL 0x320120
220 #define AUD_BAUDRATE 0x320124
221 #define AUD_I2SOUTPUTCNTL 0x320128
222 #define AAGC_HYST 0x320134
223 #define AAGC_GAIN 0x320138
224 #define AAGC_DEF 0x32013c
225 #define AUD_IIR1_0_SEL 0x320150
226 #define AUD_IIR1_0_SHIFT 0x320154
227 #define AUD_IIR1_1_SEL 0x320158
228 #define AUD_IIR1_1_SHIFT 0x32015c
229 #define AUD_IIR1_2_SEL 0x320160
230 #define AUD_IIR1_2_SHIFT 0x320164
231 #define AUD_IIR1_3_SEL 0x320168
232 #define AUD_IIR1_3_SHIFT 0x32016c
233 #define AUD_IIR1_4_SEL 0x320170
234 #define AUD_IIR1_4_SHIFT 0x32017c
235 #define AUD_IIR1_5_SEL 0x320180
236 #define AUD_IIR1_5_SHIFT 0x320184
237 #define AUD_IIR2_0_SEL 0x320190
238 #define AUD_IIR2_0_SHIFT 0x320194
239 #define AUD_IIR2_1_SEL 0x320198
240 #define AUD_IIR2_1_SHIFT 0x32019c
241 #define AUD_IIR2_2_SEL 0x3201a0
242 #define AUD_IIR2_2_SHIFT 0x3201a4
243 #define AUD_IIR2_3_SEL 0x3201a8
244 #define AUD_IIR2_3_SHIFT 0x3201ac
245 #define AUD_IIR3_0_SEL 0x3201c0
246 #define AUD_IIR3_0_SHIFT 0x3201c4
247 #define AUD_IIR3_1_SEL 0x3201c8
248 #define AUD_IIR3_1_SHIFT 0x3201cc
249 #define AUD_IIR3_2_SEL 0x3201d0
250 #define AUD_IIR3_2_SHIFT 0x3201d4
251 #define AUD_IIR4_0_SEL 0x3201e0
252 #define AUD_IIR4_0_SHIFT 0x3201e4
253 #define AUD_IIR4_1_SEL 0x3201e8
254 #define AUD_IIR4_1_SHIFT 0x3201ec
255 #define AUD_IIR4_2_SEL 0x3201f0
256 #define AUD_IIR4_2_SHIFT 0x3201f4
257 #define AUD_IIR4_0_CA0 0x320200
258 #define AUD_IIR4_0_CA1 0x320204
259 #define AUD_IIR4_0_CA2 0x320208
260 #define AUD_IIR4_0_CB0 0x32020c
261 #define AUD_IIR4_0_CB1 0x320210
262 #define AUD_IIR4_1_CA0 0x320214
263 #define AUD_IIR4_1_CA1 0x320218
264 #define AUD_IIR4_1_CA2 0x32021c
265 #define AUD_IIR4_1_CB0 0x320220
266 #define AUD_IIR4_1_CB1 0x320224
267 #define AUD_IIR4_2_CA0 0x320228
268 #define AUD_IIR4_2_CA1 0x32022c
269 #define AUD_IIR4_2_CA2 0x320230
270 #define AUD_IIR4_2_CB0 0x320234
271 #define AUD_IIR4_2_CB1 0x320238
272 #define AUD_HP_MD_IIR4_1 0x320250
273 #define AUD_HP_PROG_IIR4_1 0x320254
274 #define AUD_FM_MODE_ENABLE 0x320258
275 #define AUD_POLY0_DDS_CONSTANT 0x320270
276 #define AUD_DN0_FREQ 0x320274
277 #define AUD_DN1_FREQ 0x320278
278 #define AUD_DN1_FREQ_SHIFT 0x32027c
279 #define AUD_DN1_AFC 0x320280
280 #define AUD_DN1_SRC_SEL 0x320284
281 #define AUD_DN1_SHFT 0x320288
282 #define AUD_DN2_FREQ 0x32028c
283 #define AUD_DN2_FREQ_SHIFT 0x320290
284 #define AUD_DN2_AFC 0x320294
285 #define AUD_DN2_SRC_SEL 0x320298
286 #define AUD_DN2_SHFT 0x32029c
287 #define AUD_CRDC0_SRC_SEL 0x320300
288 #define AUD_CRDC0_SHIFT 0x320304
289 #define AUD_CORDIC_SHIFT_0 0x320308
290 #define AUD_CRDC1_SRC_SEL 0x32030c
291 #define AUD_CRDC1_SHIFT 0x320310
292 #define AUD_CORDIC_SHIFT_1 0x320314
293 #define AUD_DCOC_0_SRC 0x320320
294 #define AUD_DCOC0_SHIFT 0x320324
295 #define AUD_DCOC_0_SHIFT_IN0 0x320328
296 #define AUD_DCOC_0_SHIFT_IN1 0x32032c
297 #define AUD_DCOC_1_SRC 0x320330
298 #define AUD_DCOC1_SHIFT 0x320334
299 #define AUD_DCOC_1_SHIFT_IN0 0x320338
300 #define AUD_DCOC_1_SHIFT_IN1 0x32033c
301 #define AUD_DCOC_2_SRC 0x320340
302 #define AUD_DCOC2_SHIFT 0x320344
303 #define AUD_DCOC_2_SHIFT_IN0 0x320348
304 #define AUD_DCOC_2_SHIFT_IN1 0x32034c
305 #define AUD_DCOC_PASS_IN 0x320350
306 #define AUD_PDET_SRC 0x320370
307 #define AUD_PDET_SHIFT 0x320374
308 #define AUD_PILOT_BQD_1_K0 0x320380
309 #define AUD_PILOT_BQD_1_K1 0x320384
310 #define AUD_PILOT_BQD_1_K2 0x320388
311 #define AUD_PILOT_BQD_1_K3 0x32038c
312 #define AUD_PILOT_BQD_1_K4 0x320390
313 #define AUD_PILOT_BQD_2_K0 0x320394
314 #define AUD_PILOT_BQD_2_K1 0x320398
315 #define AUD_PILOT_BQD_2_K2 0x32039c
316 #define AUD_PILOT_BQD_2_K3 0x3203a0
317 #define AUD_PILOT_BQD_2_K4 0x3203a4
318 #define AUD_THR_FR 0x3203c0
319 #define AUD_X_PROG 0x3203c4
320 #define AUD_Y_PROG 0x3203c8
321 #define AUD_HARMONIC_MULT 0x3203cc
322 #define AUD_C1_UP_THR 0x3203d0
323 #define AUD_C1_LO_THR 0x3203d4
324 #define AUD_C2_UP_THR 0x3203d8
325 #define AUD_C2_LO_THR 0x3203dc
326 #define AUD_PLL_EN 0x320400
327 #define AUD_PLL_SRC 0x320404
328 #define AUD_PLL_SHIFT 0x320408
329 #define AUD_PLL_IF_SEL 0x32040c
330 #define AUD_PLL_IF_SHIFT 0x320410
331 #define AUD_BIQUAD_PLL_K0 0x320414
332 #define AUD_BIQUAD_PLL_K1 0x320418
333 #define AUD_BIQUAD_PLL_K2 0x32041c
334 #define AUD_BIQUAD_PLL_K3 0x320420
335 #define AUD_BIQUAD_PLL_K4 0x320424
336 #define AUD_DEEMPH0_SRC_SEL 0x320440
337 #define AUD_DEEMPH0_SHIFT 0x320444
338 #define AUD_DEEMPH0_G0 0x320448
339 #define AUD_DEEMPH0_A0 0x32044c
340 #define AUD_DEEMPH0_B0 0x320450
341 #define AUD_DEEMPH0_A1 0x320454
342 #define AUD_DEEMPH0_B1 0x320458
343 #define AUD_DEEMPH1_SRC_SEL 0x32045c
344 #define AUD_DEEMPH1_SHIFT 0x320460
345 #define AUD_DEEMPH1_G0 0x320464
346 #define AUD_DEEMPH1_A0 0x320468
347 #define AUD_DEEMPH1_B0 0x32046c
348 #define AUD_DEEMPH1_A1 0x320470
349 #define AUD_DEEMPH1_B1 0x320474
350 #define AUD_OUT0_SEL 0x320490
351 #define AUD_OUT0_SHIFT 0x320494
352 #define AUD_OUT1_SEL 0x320498
353 #define AUD_OUT1_SHIFT 0x32049c
354 #define AUD_RDSI_SEL 0x3204a0
355 #define AUD_RDSI_SHIFT 0x3204a4
356 #define AUD_RDSQ_SEL 0x3204a8
357 #define AUD_RDSQ_SHIFT 0x3204ac
358 #define AUD_DBX_IN_GAIN 0x320500
359 #define AUD_DBX_WBE_GAIN 0x320504
360 #define AUD_DBX_SE_GAIN 0x320508
361 #define AUD_DBX_RMS_WBE 0x32050c
362 #define AUD_DBX_RMS_SE 0x320510
363 #define AUD_DBX_SE_BYPASS 0x320514
364 #define AUD_FAWDETCTL 0x320530
365 #define AUD_FAWDETWINCTL 0x320534
366 #define AUD_DEEMPHGAIN_R 0x320538
367 #define AUD_DEEMPHNUMER1_R 0x32053c
368 #define AUD_DEEMPHNUMER2_R 0x320540
369 #define AUD_DEEMPHDENOM1_R 0x320544
370 #define AUD_DEEMPHDENOM2_R 0x320548
371 #define AUD_ERRLOGPERIOD_R 0x32054c
372 #define AUD_ERRINTRPTTHSHLD1_R 0x320550
373 #define AUD_ERRINTRPTTHSHLD2_R 0x320554
374 #define AUD_ERRINTRPTTHSHLD3_R 0x320558
375 #define AUD_NICAM_STATUS1 0x32055c
376 #define AUD_NICAM_STATUS2 0x320560
377 #define AUD_ERRLOG1 0x320564
378 #define AUD_ERRLOG2 0x320568
379 #define AUD_ERRLOG3 0x32056c
380 #define AUD_DAC_BYPASS_L 0x320580
381 #define AUD_DAC_BYPASS_R 0x320584
382 #define AUD_DAC_BYPASS_CTL 0x320588
383 #define AUD_CTL 0x32058c
384 #define AUD_STATUS 0x320590
385 #define AUD_VOL_CTL 0x320594
386 #define AUD_BAL_CTL 0x320598
387 #define AUD_START_TIMER 0x3205b0
388 #define AUD_MODE_CHG_TIMER 0x3205b4
389 #define AUD_POLYPH80SCALEFAC 0x3205b8
390 #define AUD_DMD_RA_DDS 0x3205bc
391 #define AUD_I2S_RA_DDS 0x3205c0
392 #define AUD_RATE_THRES_DMD 0x3205d0
393 #define AUD_RATE_THRES_I2S 0x3205d4
394 #define AUD_RATE_ADJ1 0x3205d8
395 #define AUD_RATE_ADJ2 0x3205dc
396 #define AUD_RATE_ADJ3 0x3205e0
397 #define AUD_RATE_ADJ4 0x3205e4
398 #define AUD_RATE_ADJ5 0x3205e8
399 #define AUD_APB_IN_RATE_ADJ 0x3205ec
400 #define AUD_I2SCNTL 0x3205ec
401 #define AUD_PHASE_FIX_CTL 0x3205f0
402 #define AUD_PLL_PRESCALE 0x320600
403 #define AUD_PLL_DDS 0x320604
404 #define AUD_PLL_INT 0x320608
405 #define AUD_PLL_FRAC 0x32060c
406 #define AUD_PLL_JTAG 0x320620
407 #define AUD_PLL_SPMP 0x320624
408 #define AUD_AFE_12DB_EN 0x320628
410 // Audio QAM Register Addresses
411 #define AUD_PDF_DDS_CNST_BYTE2 0x320d01
412 #define AUD_PDF_DDS_CNST_BYTE1 0x320d02
413 #define AUD_PDF_DDS_CNST_BYTE0 0x320d03
414 #define AUD_PHACC_FREQ_8MSB 0x320d2a
415 #define AUD_PHACC_FREQ_8LSB 0x320d2b
416 #define AUD_QAM_MODE 0x320d04
419 /* ---------------------------------------------------------------------- */
420 /* transport stream registers */
422 #define MO_TS_DMA 0x330000 // {64}RWp Transport stream downstream
423 #define MO_TS_GPCNT 0x33C020 // {16}RO TS general purpose counter
424 #define MO_TS_GPCNTRL 0x33C030 // {2}WO TS general purpose control
425 #define MO_TS_DMACNTRL 0x33C040 // {6}RW TS DMA control
426 #define MO_TS_XFR_STAT 0x33C044 // {1}RO TS transfer status
427 #define MO_TS_LNGTH 0x33C048 // {12}RW TS line length
429 #define TS_HW_SOP_CNTRL 0x33C04C
430 #define TS_GEN_CNTRL 0x33C050
431 #define TS_BD_PKT_STAT 0x33C054
432 #define TS_SOP_STAT 0x33C058
433 #define TS_FIFO_OVFL_STAT 0x33C05C
434 #define TS_VALERR_CNTRL 0x33C060
437 /* ---------------------------------------------------------------------- */
440 #define MO_VIPD_DMA 0x340000 // {64}RWp VIP downstream
441 #define MO_VIPU_DMA 0x340008 // {64}RWp VIP upstream
442 #define MO_VIPD_GPCNT 0x34C020 // {16}RO VIP down general purpose counter
443 #define MO_VIPU_GPCNT 0x34C024 // {16}RO VIP up general purpose counter
444 #define MO_VIPD_GPCNTRL 0x34C030 // {2}WO VIP down general purpose control
445 #define MO_VIPU_GPCNTRL 0x34C034 // {2}WO VIP up general purpose control
446 #define MO_VIP_DMACNTRL 0x34C040 // {6}RW VIP DMA control
447 #define MO_VIP_XFR_STAT 0x34C044 // {1}RO VIP transfer status
448 #define MO_VIP_CFG 0x340048 // VIP configuration
449 #define MO_VIPU_CNTRL 0x34004C // VIP upstream control #1
450 #define MO_VIPD_CNTRL 0x340050 // VIP downstream control #2
451 #define MO_VIPD_LNGTH 0x340054 // VIP downstream line length
452 #define MO_VIP_BRSTLN 0x340058 // VIP burst length
453 #define MO_VIP_INTCNTRL 0x34C05C // VIP Interrupt Control
454 #define MO_VIP_XFTERM 0x340060 // VIP transfer terminate
457 /* ---------------------------------------------------------------------- */
460 #define MO_M2M_DMA 0x350000 // {64}RWp Mem2Mem DMA Bfr
461 #define MO_GP0_IO 0x350010 // {32}RW* GPIOoutput enablesdata I/O
462 #define MO_GP1_IO 0x350014 // {32}RW* GPIOoutput enablesdata I/O
463 #define MO_GP2_IO 0x350018 // {32}RW* GPIOoutput enablesdata I/O
464 #define MO_GP3_IO 0x35001C // {32}RW* GPIO Mode/Ctrloutput enables
465 #define MO_GPIO 0x350020 // {32}RW* GPIO I2C Ctrldata I/O
466 #define MO_GPOE 0x350024 // {32}RW GPIO I2C Ctrloutput enables
467 #define MO_GP_ISM 0x350028 // {16}WO GPIO Intr Sens/Pol
469 #define MO_PLL_B 0x35C008 // {32}RW* PLL Control for ASB bus clks
470 #define MO_M2M_CNT 0x35C024 // {32}RW Mem2Mem DMA Cnt
471 #define MO_M2M_XSUM 0x35C028 // {32}RO M2M XOR-Checksum
472 #define MO_CRC 0x35C02C // {16}RW CRC16 init/result
473 #define MO_CRC_D 0x35C030 // {32}WO CRC16 new data in
474 #define MO_TM_CNT_LDW 0x35C034 // {32}RO Timer : Counter low dword
475 #define MO_TM_CNT_UW 0x35C038 // {16}RO Timer : Counter high word
476 #define MO_TM_LMT_LDW 0x35C03C // {32}RW Timer : Limit low dword
477 #define MO_TM_LMT_UW 0x35C040 // {32}RW Timer : Limit high word
478 #define MO_PINMUX_IO 0x35C044 // {8}RW Pin Mux Control
479 #define MO_TSTSEL_IO 0x35C048 // {2}RW Pin Mux Control
480 #define MO_AFECFG_IO 0x35C04C // AFE configuration reg
481 #define MO_DDS_IO 0x35C050 // DDS Increment reg
482 #define MO_DDSCFG_IO 0x35C054 // DDS Configuration reg
483 #define MO_SAMPLE_IO 0x35C058 // IRIn sample reg
484 #define MO_SRST_IO 0x35C05C // Output system reset reg
486 #define MO_INT1_MSK 0x35C060 // DMA RISC interrupt mask
487 #define MO_INT1_STAT 0x35C064 // DMA RISC interrupt status
488 #define MO_INT1_MSTAT 0x35C068 // DMA RISC interrupt masked status
491 /* ---------------------------------------------------------------------- */
492 /* i2c bus registers */
494 #define MO_I2C 0x368000 // I2C data/control
495 #define MO_I2C_DIV (0xf<<4)
496 #define MO_I2C_SYNC (1<<3)
497 #define MO_I2C_W3B (1<<2)
498 #define MO_I2C_SCL (1<<1)
499 #define MO_I2C_SDA (1<<0)
502 /* ---------------------------------------------------------------------- */
503 /* general purpose host registers */
504 /* FIXME: tyops? s/0x35/0x38/ ?? */
506 #define MO_GPHSTD_DMA 0x350000 // {64}RWp Host downstream
507 #define MO_GPHSTU_DMA 0x350008 // {64}RWp Host upstream
508 #define MO_GPHSTU_CNTRL 0x380048 // Host upstream control #1
509 #define MO_GPHSTD_CNTRL 0x38004C // Host downstream control #2
510 #define MO_GPHSTD_LNGTH 0x380050 // Host downstream line length
511 #define MO_GPHST_WSC 0x380054 // Host wait state control
512 #define MO_GPHST_XFR 0x380058 // Host transfer control
513 #define MO_GPHST_WDTH 0x38005C // Host interface width
514 #define MO_GPHST_HDSHK 0x380060 // Host peripheral handshake
515 #define MO_GPHST_MUX16 0x380064 // Host muxed 16-bit transfer parameters
516 #define MO_GPHST_MODE 0x380068 // Host mode select
518 #define MO_GPHSTD_GPCNT 0x35C020 // Host down general purpose counter
519 #define MO_GPHSTU_GPCNT 0x35C024 // Host up general purpose counter
520 #define MO_GPHSTD_GPCNTRL 0x38C030 // Host down general purpose control
521 #define MO_GPHSTU_GPCNTRL 0x38C034 // Host up general purpose control
522 #define MO_GPHST_DMACNTRL 0x38C040 // Host DMA control
523 #define MO_GPHST_XFR_STAT 0x38C044 // Host transfer status
524 #define MO_GPHST_SOFT_RST 0x38C06C // Host software reset
527 /* ---------------------------------------------------------------------- */
528 /* RISC instructions */
530 #define RISC_SYNC 0x80000000
531 #define RISC_SYNC_ODD 0x80000000
532 #define RISC_SYNC_EVEN 0x80000200
533 #define RISC_RESYNC 0x80008000
534 #define RISC_RESYNC_ODD 0x80008000
535 #define RISC_RESYNC_EVEN 0x80008200
536 #define RISC_WRITE 0x10000000
537 #define RISC_WRITEC 0x50000000
538 #define RISC_READ 0x90000000
539 #define RISC_READC 0xA0000000
540 #define RISC_JUMP 0x70000000
541 #define RISC_SKIP 0x20000000
542 #define RISC_WRITERM 0xB0000000
543 #define RISC_WRITECM 0xC0000000
544 #define RISC_WRITECR 0xD0000000
545 #define RISC_IMM 0x00000001
547 #define RISC_SOL 0x08000000
548 #define RISC_EOL 0x04000000
550 #define RISC_IRQ2 0x02000000
551 #define RISC_IRQ1 0x01000000
553 #define RISC_CNT_NONE 0x00000000
554 #define RISC_CNT_INC 0x00010000
555 #define RISC_CNT_RSVR 0x00020000
556 #define RISC_CNT_RESET 0x00030000
557 #define RISC_JMP_SRP 0x01
560 /* ---------------------------------------------------------------------- */
561 /* various constants */
563 #define SEL_BTSC 0x01
564 #define SEL_EIAJ 0x02
567 #define SEL_NICAM 0x10
568 #define SEL_FMRADIO 0x20
571 #define EN_BTSC_FORCE_MONO 0
572 #define EN_BTSC_FORCE_STEREO 1
573 #define EN_BTSC_FORCE_SAP 2
574 #define EN_BTSC_AUTO_STEREO 3
575 #define EN_BTSC_AUTO_SAP 4
577 #define EN_A2_FORCE_MONO1 8
578 #define EN_A2_FORCE_MONO2 9
579 #define EN_A2_FORCE_STEREO 10
580 #define EN_A2_AUTO_MONO2 11
581 #define EN_A2_AUTO_STEREO 12
583 #define EN_EIAJ_FORCE_MONO1 16
584 #define EN_EIAJ_FORCE_MONO2 17
585 #define EN_EIAJ_FORCE_STEREO 18
586 #define EN_EIAJ_AUTO_MONO2 19
587 #define EN_EIAJ_AUTO_STEREO 20
589 #define EN_NICAM_FORCE_MONO1 32
590 #define EN_NICAM_FORCE_MONO2 33
591 #define EN_NICAM_FORCE_STEREO 34
592 #define EN_NICAM_AUTO_MONO2 35
593 #define EN_NICAM_AUTO_STEREO 36
595 #define EN_FMRADIO_FORCE_MONO 24
596 #define EN_FMRADIO_FORCE_STEREO 25
597 #define EN_FMRADIO_AUTO_STEREO 26
599 #define EN_NICAM_AUTO_FALLBACK 0x00000040
600 #define EN_FMRADIO_EN_RDS 0x00000200
601 #define EN_NICAM_TRY_AGAIN_BIT 0x00000400
602 #define EN_DAC_ENABLE 0x00001000
603 #define EN_I2SOUT_ENABLE 0x00002000
604 #define EN_I2SIN_STR2DAC 0x00004000
605 #define EN_I2SIN_ENABLE 0x00008000
607 #define EN_DMTRX_SUMDIFF (0 << 7)
608 #define EN_DMTRX_SUMR (1 << 7)
609 #define EN_DMTRX_LR (2 << 7)
610 #define EN_DMTRX_MONO (3 << 7)
611 #define EN_DMTRX_BYPASS (1 << 11)
614 #define VID_CAPTURE_CONTROL 0x310180
616 #define CX23880_CAP_CTL_CAPTURE_VBI_ODD (1<<3)
617 #define CX23880_CAP_CTL_CAPTURE_VBI_EVEN (1<<2)
618 #define CX23880_CAP_CTL_CAPTURE_ODD (1<<1)
619 #define CX23880_CAP_CTL_CAPTURE_EVEN (1<<0)
621 #define VideoInputMux0 0x0
622 #define VideoInputMux1 0x1
623 #define VideoInputMux2 0x2
624 #define VideoInputMux3 0x3
625 #define VideoInputTuner 0x0
626 #define VideoInputComposite 0x1
627 #define VideoInputSVideo 0x2
628 #define VideoInputOther 0x3
634 #define VideoFormatAuto 0x0
635 #define VideoFormatNTSC 0x1
636 #define VideoFormatNTSCJapan 0x2
637 #define VideoFormatNTSC443 0x3
638 #define VideoFormatPAL 0x4
639 #define VideoFormatPALB 0x4
640 #define VideoFormatPALD 0x4
641 #define VideoFormatPALG 0x4
642 #define VideoFormatPALH 0x4
643 #define VideoFormatPALI 0x4
644 #define VideoFormatPALBDGHI 0x4
645 #define VideoFormatPALM 0x5
646 #define VideoFormatPALN 0x6
647 #define VideoFormatPALNC 0x7
648 #define VideoFormatPAL60 0x8
649 #define VideoFormatSECAM 0x9
651 #define VideoFormatAuto27MHz 0x10
652 #define VideoFormatNTSC27MHz 0x11
653 #define VideoFormatNTSCJapan27MHz 0x12
654 #define VideoFormatNTSC44327MHz 0x13
655 #define VideoFormatPAL27MHz 0x14
656 #define VideoFormatPALB27MHz 0x14
657 #define VideoFormatPALD27MHz 0x14
658 #define VideoFormatPALG27MHz 0x14
659 #define VideoFormatPALH27MHz 0x14
660 #define VideoFormatPALI27MHz 0x14
661 #define VideoFormatPALBDGHI27MHz 0x14
662 #define VideoFormatPALM27MHz 0x15
663 #define VideoFormatPALN27MHz 0x16
664 #define VideoFormatPALNC27MHz 0x17
665 #define VideoFormatPAL6027MHz 0x18
666 #define VideoFormatSECAM27MHz 0x19
668 #define NominalUSECAM 0x87
669 #define NominalVSECAM 0x85
670 #define NominalUNTSC 0xFE
671 #define NominalVNTSC 0xB4
673 #define NominalContrast 0xD8
675 #define HFilterAutoFormat 0x0
676 #define HFilterCIF 0x1
677 #define HFilterQCIF 0x2
678 #define HFilterICON 0x3
680 #define VFilter2TapInterpolate 0
681 #define VFilter3TapInterpolate 1
682 #define VFilter4TapInterpolate 2
683 #define VFilter5TapInterpolate 3
684 #define VFilter2TapNoInterpolate 4
685 #define VFilter3TapNoInterpolate 5
686 #define VFilter4TapNoInterpolate 6
687 #define VFilter5TapNoInterpolate 7
689 #define ColorFormatRGB32 0x0000
690 #define ColorFormatRGB24 0x0011
691 #define ColorFormatRGB16 0x0022
692 #define ColorFormatRGB15 0x0033
693 #define ColorFormatYUY2 0x0044
694 #define ColorFormatBTYUV 0x0055
695 #define ColorFormatY8 0x0066
696 #define ColorFormatRGB8 0x0077
697 #define ColorFormatPL422 0x0088
698 #define ColorFormatPL411 0x0099
699 #define ColorFormatYUV12 0x00AA
700 #define ColorFormatYUV9 0x00BB
701 #define ColorFormatRAW 0x00EE
702 #define ColorFormatBSWAP 0x0300
703 #define ColorFormatWSWAP 0x0c00
704 #define ColorFormatEvenMask 0x050f
705 #define ColorFormatOddMask 0x0af0
706 #define ColorFormatGamma 0x1000
708 #define Interlaced 0x1
709 #define NonInterlaced 0x0
711 #define FieldEven 0x1
714 #define TGReadWriteMode 0x0
715 #define TGEnableMode 0x1
717 #define DV_CbAlign 0x0
718 #define DV_Y0Align 0x1
719 #define DV_CrAlign 0x2
720 #define DV_Y1Align 0x3
722 #define DVF_Analog 0x0
723 #define DVF_CCIR656 0x1
724 #define DVF_ByteStream 0x2
725 #define DVF_ExtVSYNC 0x4
726 #define DVF_ExtField 0x5
728 #define CHANNEL_VID_Y 0x1
729 #define CHANNEL_VID_U 0x2
730 #define CHANNEL_VID_V 0x3
731 #define CHANNEL_VID_VBI 0x4
732 #define CHANNEL_AUD_DN 0x5
733 #define CHANNEL_AUD_UP 0x6
734 #define CHANNEL_AUD_RDS_DN 0x7
735 #define CHANNEL_MPEG_DN 0x8
736 #define CHANNEL_VIP_DN 0x9
737 #define CHANNEL_VIP_UP 0xA
738 #define CHANNEL_HOST_DN 0xB
739 #define CHANNEL_HOST_UP 0xC
740 #define CHANNEL_FIRST 0x1
741 #define CHANNEL_LAST 0xC
743 #define GP_COUNT_CONTROL_NONE 0x0
744 #define GP_COUNT_CONTROL_INC 0x1
745 #define GP_COUNT_CONTROL_RESERVED 0x2
746 #define GP_COUNT_CONTROL_RESET 0x3
748 #define PLL_PRESCALE_BY_2 2
749 #define PLL_PRESCALE_BY_3 3
750 #define PLL_PRESCALE_BY_4 4
751 #define PLL_PRESCALE_BY_5 5
753 #define HLNotchFilter4xFsc 0
754 #define HLNotchFilterSquare 1
755 #define HLNotchFilter135NTSC 2
756 #define HLNotchFilter135PAL 3
758 #define NTSC_8x_SUB_CARRIER 28.63636E6
759 #define PAL_8x_SUB_CARRIER 35.46895E6
761 // Default analog settings
762 #define DEFAULT_HUE_NTSC 0x00
763 #define DEFAULT_BRIGHTNESS_NTSC 0x00
764 #define DEFAULT_CONTRAST_NTSC 0x39
765 #define DEFAULT_SAT_U_NTSC 0x7F
766 #define DEFAULT_SAT_V_NTSC 0x5A
775 SOURCE_COMPVIASVIDEO,
779 #endif /* _CX88_REG_H_ */
git.openpandora.org / pandora-kernel.git / blob