drivers/media/video/cx25821/cx25821-core.c

   1 /*
   2  *  Driver for the Conexant CX25821 PCIe bridge
   3  *
   4  *  Copyright (C) 2009 Conexant Systems Inc.
   5  *  Authors  <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
   6  *  Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the Free Software
  21  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  25
  26 #include <linux/i2c.h>
  27 #include <linux/slab.h>
  28 #include "cx25821.h"
  29 #include "cx25821-sram.h"
  30 #include "cx25821-video.h"
  31
  32 MODULE_DESCRIPTION("Driver for Athena cards");
  33 MODULE_AUTHOR("Shu Lin - Hiep Huynh");
  34 MODULE_LICENSE("GPL");
  35
  36 static unsigned int debug;
  37 module_param(debug, int, 0644);
  38 MODULE_PARM_DESC(debug, "enable debug messages");
  39
  40 static unsigned int card[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET };
  41 module_param_array(card, int, NULL, 0444);
  42 MODULE_PARM_DESC(card, "card type");
  43
  44 static unsigned int cx25821_devcount;
  45
  46 DEFINE_MUTEX(cx25821_devlist_mutex);
  47 EXPORT_SYMBOL(cx25821_devlist_mutex);
  48 LIST_HEAD(cx25821_devlist);
  49 EXPORT_SYMBOL(cx25821_devlist);
  50
  51 struct sram_channel cx25821_sram_channels[] = {
  52         [SRAM_CH00] = {
  53                 .i = SRAM_CH00,
  54                 .name = "VID A",
  55                 .cmds_start = VID_A_DOWN_CMDS,
  56                 .ctrl_start = VID_A_IQ,
  57                 .cdt = VID_A_CDT,
  58                 .fifo_start = VID_A_DOWN_CLUSTER_1,
  59                 .fifo_size = (VID_CLUSTER_SIZE << 2),
  60                 .ptr1_reg = DMA1_PTR1,
  61                 .ptr2_reg = DMA1_PTR2,
  62                 .cnt1_reg = DMA1_CNT1,
  63                 .cnt2_reg = DMA1_CNT2,
  64                 .int_msk = VID_A_INT_MSK,
  65                 .int_stat = VID_A_INT_STAT,
  66                 .int_mstat = VID_A_INT_MSTAT,
  67                 .dma_ctl = VID_DST_A_DMA_CTL,
  68                 .gpcnt_ctl = VID_DST_A_GPCNT_CTL,
  69                 .gpcnt = VID_DST_A_GPCNT,
  70                 .vip_ctl = VID_DST_A_VIP_CTL,
  71                 .pix_frmt = VID_DST_A_PIX_FRMT,
  72         },
  73
  74         [SRAM_CH01] = {
  75                 .i = SRAM_CH01,
  76                 .name = "VID B",
  77                 .cmds_start = VID_B_DOWN_CMDS,
  78                 .ctrl_start = VID_B_IQ,
  79                 .cdt = VID_B_CDT,
  80                 .fifo_start = VID_B_DOWN_CLUSTER_1,
  81                 .fifo_size = (VID_CLUSTER_SIZE << 2),
  82                 .ptr1_reg = DMA2_PTR1,
  83                 .ptr2_reg = DMA2_PTR2,
  84                 .cnt1_reg = DMA2_CNT1,
  85                 .cnt2_reg = DMA2_CNT2,
  86                 .int_msk = VID_B_INT_MSK,
  87                 .int_stat = VID_B_INT_STAT,
  88                 .int_mstat = VID_B_INT_MSTAT,
  89                 .dma_ctl = VID_DST_B_DMA_CTL,
  90                 .gpcnt_ctl = VID_DST_B_GPCNT_CTL,
  91                 .gpcnt = VID_DST_B_GPCNT,
  92                 .vip_ctl = VID_DST_B_VIP_CTL,
  93                 .pix_frmt = VID_DST_B_PIX_FRMT,
  94         },
  95
  96         [SRAM_CH02] = {
  97                 .i = SRAM_CH02,
  98                 .name = "VID C",
  99                 .cmds_start = VID_C_DOWN_CMDS,
 100                 .ctrl_start = VID_C_IQ,
 101                 .cdt = VID_C_CDT,
 102                 .fifo_start = VID_C_DOWN_CLUSTER_1,
 103                 .fifo_size = (VID_CLUSTER_SIZE << 2),
 104                 .ptr1_reg = DMA3_PTR1,
 105                 .ptr2_reg = DMA3_PTR2,
 106                 .cnt1_reg = DMA3_CNT1,
 107                 .cnt2_reg = DMA3_CNT2,
 108                 .int_msk = VID_C_INT_MSK,
 109                 .int_stat = VID_C_INT_STAT,
 110                 .int_mstat = VID_C_INT_MSTAT,
 111                 .dma_ctl = VID_DST_C_DMA_CTL,
 112                 .gpcnt_ctl = VID_DST_C_GPCNT_CTL,
 113                 .gpcnt = VID_DST_C_GPCNT,
 114                 .vip_ctl = VID_DST_C_VIP_CTL,
 115                 .pix_frmt = VID_DST_C_PIX_FRMT,
 116         },
 117
 118         [SRAM_CH03] = {
 119                 .i = SRAM_CH03,
 120                 .name = "VID D",
 121                 .cmds_start = VID_D_DOWN_CMDS,
 122                 .ctrl_start = VID_D_IQ,
 123                 .cdt = VID_D_CDT,
 124                 .fifo_start = VID_D_DOWN_CLUSTER_1,
 125                 .fifo_size = (VID_CLUSTER_SIZE << 2),
 126                 .ptr1_reg = DMA4_PTR1,
 127                 .ptr2_reg = DMA4_PTR2,
 128                 .cnt1_reg = DMA4_CNT1,
 129                 .cnt2_reg = DMA4_CNT2,
 130                 .int_msk = VID_D_INT_MSK,
 131                 .int_stat = VID_D_INT_STAT,
 132                 .int_mstat = VID_D_INT_MSTAT,
 133                 .dma_ctl = VID_DST_D_DMA_CTL,
 134                 .gpcnt_ctl = VID_DST_D_GPCNT_CTL,
 135                 .gpcnt = VID_DST_D_GPCNT,
 136                 .vip_ctl = VID_DST_D_VIP_CTL,
 137                 .pix_frmt = VID_DST_D_PIX_FRMT,
 138         },
 139
 140         [SRAM_CH04] = {
 141                 .i = SRAM_CH04,
 142                 .name = "VID E",
 143                 .cmds_start = VID_E_DOWN_CMDS,
 144                 .ctrl_start = VID_E_IQ,
 145                 .cdt = VID_E_CDT,
 146                 .fifo_start = VID_E_DOWN_CLUSTER_1,
 147                 .fifo_size = (VID_CLUSTER_SIZE << 2),
 148                 .ptr1_reg = DMA5_PTR1,
 149                 .ptr2_reg = DMA5_PTR2,
 150                 .cnt1_reg = DMA5_CNT1,
 151                 .cnt2_reg = DMA5_CNT2,
 152                 .int_msk = VID_E_INT_MSK,
 153                 .int_stat = VID_E_INT_STAT,
 154                 .int_mstat = VID_E_INT_MSTAT,
 155                 .dma_ctl = VID_DST_E_DMA_CTL,
 156                 .gpcnt_ctl = VID_DST_E_GPCNT_CTL,
 157                 .gpcnt = VID_DST_E_GPCNT,
 158                 .vip_ctl = VID_DST_E_VIP_CTL,
 159                 .pix_frmt = VID_DST_E_PIX_FRMT,
 160         },
 161
 162         [SRAM_CH05] = {
 163                 .i = SRAM_CH05,
 164                 .name = "VID F",
 165                 .cmds_start = VID_F_DOWN_CMDS,
 166                 .ctrl_start = VID_F_IQ,
 167                 .cdt = VID_F_CDT,
 168                 .fifo_start = VID_F_DOWN_CLUSTER_1,
 169                 .fifo_size = (VID_CLUSTER_SIZE << 2),
 170                 .ptr1_reg = DMA6_PTR1,
 171                 .ptr2_reg = DMA6_PTR2,
 172                 .cnt1_reg = DMA6_CNT1,
 173                 .cnt2_reg = DMA6_CNT2,
 174                 .int_msk = VID_F_INT_MSK,
 175                 .int_stat = VID_F_INT_STAT,
 176                 .int_mstat = VID_F_INT_MSTAT,
 177                 .dma_ctl = VID_DST_F_DMA_CTL,
 178                 .gpcnt_ctl = VID_DST_F_GPCNT_CTL,
 179                 .gpcnt = VID_DST_F_GPCNT,
 180                 .vip_ctl = VID_DST_F_VIP_CTL,
 181                 .pix_frmt = VID_DST_F_PIX_FRMT,
 182         },
 183
 184         [SRAM_CH06] = {
 185                 .i = SRAM_CH06,
 186                 .name = "VID G",
 187                 .cmds_start = VID_G_DOWN_CMDS,
 188                 .ctrl_start = VID_G_IQ,
 189                 .cdt = VID_G_CDT,
 190                 .fifo_start = VID_G_DOWN_CLUSTER_1,
 191                 .fifo_size = (VID_CLUSTER_SIZE << 2),
 192                 .ptr1_reg = DMA7_PTR1,
 193                 .ptr2_reg = DMA7_PTR2,
 194                 .cnt1_reg = DMA7_CNT1,
 195                 .cnt2_reg = DMA7_CNT2,
 196                 .int_msk = VID_G_INT_MSK,
 197                 .int_stat = VID_G_INT_STAT,
 198                 .int_mstat = VID_G_INT_MSTAT,
 199                 .dma_ctl = VID_DST_G_DMA_CTL,
 200                 .gpcnt_ctl = VID_DST_G_GPCNT_CTL,
 201                 .gpcnt = VID_DST_G_GPCNT,
 202                 .vip_ctl = VID_DST_G_VIP_CTL,
 203                 .pix_frmt = VID_DST_G_PIX_FRMT,
 204         },
 205
 206         [SRAM_CH07] = {
 207                 .i = SRAM_CH07,
 208                 .name = "VID H",
 209                 .cmds_start = VID_H_DOWN_CMDS,
 210                 .ctrl_start = VID_H_IQ,
 211                 .cdt = VID_H_CDT,
 212                 .fifo_start = VID_H_DOWN_CLUSTER_1,
 213                 .fifo_size = (VID_CLUSTER_SIZE << 2),
 214                 .ptr1_reg = DMA8_PTR1,
 215                 .ptr2_reg = DMA8_PTR2,
 216                 .cnt1_reg = DMA8_CNT1,
 217                 .cnt2_reg = DMA8_CNT2,
 218                 .int_msk = VID_H_INT_MSK,
 219                 .int_stat = VID_H_INT_STAT,
 220                 .int_mstat = VID_H_INT_MSTAT,
 221                 .dma_ctl = VID_DST_H_DMA_CTL,
 222                 .gpcnt_ctl = VID_DST_H_GPCNT_CTL,
 223                 .gpcnt = VID_DST_H_GPCNT,
 224                 .vip_ctl = VID_DST_H_VIP_CTL,
 225                 .pix_frmt = VID_DST_H_PIX_FRMT,
 226         },
 227
 228         [SRAM_CH08] = {
 229                 .name = "audio from",
 230                 .cmds_start = AUD_A_DOWN_CMDS,
 231                 .ctrl_start = AUD_A_IQ,
 232                 .cdt = AUD_A_CDT,
 233                 .fifo_start = AUD_A_DOWN_CLUSTER_1,
 234                 .fifo_size = AUDIO_CLUSTER_SIZE * 3,
 235                 .ptr1_reg = DMA17_PTR1,
 236                 .ptr2_reg = DMA17_PTR2,
 237                 .cnt1_reg = DMA17_CNT1,
 238                 .cnt2_reg = DMA17_CNT2,
 239         },
 240
 241         [SRAM_CH09] = {
 242                 .i = SRAM_CH09,
 243                 .name = "VID Upstream I",
 244                 .cmds_start = VID_I_UP_CMDS,
 245                 .ctrl_start = VID_I_IQ,
 246                 .cdt = VID_I_CDT,
 247                 .fifo_start = VID_I_UP_CLUSTER_1,
 248                 .fifo_size = (VID_CLUSTER_SIZE << 2),
 249                 .ptr1_reg = DMA15_PTR1,
 250                 .ptr2_reg = DMA15_PTR2,
 251                 .cnt1_reg = DMA15_CNT1,
 252                 .cnt2_reg = DMA15_CNT2,
 253                 .int_msk = VID_I_INT_MSK,
 254                 .int_stat = VID_I_INT_STAT,
 255                 .int_mstat = VID_I_INT_MSTAT,
 256                 .dma_ctl = VID_SRC_I_DMA_CTL,
 257                 .gpcnt_ctl = VID_SRC_I_GPCNT_CTL,
 258                 .gpcnt = VID_SRC_I_GPCNT,
 259
 260                 .vid_fmt_ctl = VID_SRC_I_FMT_CTL,
 261                 .vid_active_ctl1 = VID_SRC_I_ACTIVE_CTL1,
 262                 .vid_active_ctl2 = VID_SRC_I_ACTIVE_CTL2,
 263                 .vid_cdt_size = VID_SRC_I_CDT_SZ,
 264                 .irq_bit = 8,
 265         },
 266
 267         [SRAM_CH10] = {
 268                 .i = SRAM_CH10,
 269                 .name = "VID Upstream J",
 270                 .cmds_start = VID_J_UP_CMDS,
 271                 .ctrl_start = VID_J_IQ,
 272                 .cdt = VID_J_CDT,
 273                 .fifo_start = VID_J_UP_CLUSTER_1,
 274                 .fifo_size = (VID_CLUSTER_SIZE << 2),
 275                 .ptr1_reg = DMA16_PTR1,
 276                 .ptr2_reg = DMA16_PTR2,
 277                 .cnt1_reg = DMA16_CNT1,
 278                 .cnt2_reg = DMA16_CNT2,
 279                 .int_msk = VID_J_INT_MSK,
 280                 .int_stat = VID_J_INT_STAT,
 281                 .int_mstat = VID_J_INT_MSTAT,
 282                 .dma_ctl = VID_SRC_J_DMA_CTL,
 283                 .gpcnt_ctl = VID_SRC_J_GPCNT_CTL,
 284                 .gpcnt = VID_SRC_J_GPCNT,
 285
 286                 .vid_fmt_ctl = VID_SRC_J_FMT_CTL,
 287                 .vid_active_ctl1 = VID_SRC_J_ACTIVE_CTL1,
 288                 .vid_active_ctl2 = VID_SRC_J_ACTIVE_CTL2,
 289                 .vid_cdt_size = VID_SRC_J_CDT_SZ,
 290                 .irq_bit = 9,
 291         },
 292
 293         [SRAM_CH11] = {
 294                 .i = SRAM_CH11,
 295                 .name = "Audio Upstream Channel B",
 296                 .cmds_start = AUD_B_UP_CMDS,
 297                 .ctrl_start = AUD_B_IQ,
 298                 .cdt = AUD_B_CDT,
 299                 .fifo_start = AUD_B_UP_CLUSTER_1,
 300                 .fifo_size = (AUDIO_CLUSTER_SIZE * 3),
 301                 .ptr1_reg = DMA22_PTR1,
 302                 .ptr2_reg = DMA22_PTR2,
 303                 .cnt1_reg = DMA22_CNT1,
 304                 .cnt2_reg = DMA22_CNT2,
 305                 .int_msk = AUD_B_INT_MSK,
 306                 .int_stat = AUD_B_INT_STAT,
 307                 .int_mstat = AUD_B_INT_MSTAT,
 308                 .dma_ctl = AUD_INT_DMA_CTL,
 309                 .gpcnt_ctl = AUD_B_GPCNT_CTL,
 310                 .gpcnt = AUD_B_GPCNT,
 311                 .aud_length = AUD_B_LNGTH,
 312                 .aud_cfg = AUD_B_CFG,
 313                 .fld_aud_fifo_en = FLD_AUD_SRC_B_FIFO_EN,
 314                 .fld_aud_risc_en = FLD_AUD_SRC_B_RISC_EN,
 315                 .irq_bit = 11,
 316         },
 317 };
 318 EXPORT_SYMBOL(cx25821_sram_channels);
 319
 320 struct sram_channel *channel0 = &cx25821_sram_channels[SRAM_CH00];
 321 struct sram_channel *channel1 = &cx25821_sram_channels[SRAM_CH01];
 322 struct sram_channel *channel2 = &cx25821_sram_channels[SRAM_CH02];
 323 struct sram_channel *channel3 = &cx25821_sram_channels[SRAM_CH03];
 324 struct sram_channel *channel4 = &cx25821_sram_channels[SRAM_CH04];
 325 struct sram_channel *channel5 = &cx25821_sram_channels[SRAM_CH05];
 326 struct sram_channel *channel6 = &cx25821_sram_channels[SRAM_CH06];
 327 struct sram_channel *channel7 = &cx25821_sram_channels[SRAM_CH07];
 328 struct sram_channel *channel9 = &cx25821_sram_channels[SRAM_CH09];
 329 struct sram_channel *channel10 = &cx25821_sram_channels[SRAM_CH10];
 330 struct sram_channel *channel11 = &cx25821_sram_channels[SRAM_CH11];
 331
 332 struct cx25821_dmaqueue mpegq;
 333
 334 static int cx25821_risc_decode(u32 risc)
 335 {
 336         static const char * const instr[16] = {
 337                 [RISC_SYNC >> 28] = "sync",
 338                 [RISC_WRITE >> 28] = "write",
 339                 [RISC_WRITEC >> 28] = "writec",
 340                 [RISC_READ >> 28] = "read",
 341                 [RISC_READC >> 28] = "readc",
 342                 [RISC_JUMP >> 28] = "jump",
 343                 [RISC_SKIP >> 28] = "skip",
 344                 [RISC_WRITERM >> 28] = "writerm",
 345                 [RISC_WRITECM >> 28] = "writecm",
 346                 [RISC_WRITECR >> 28] = "writecr",
 347         };
 348         static const int incr[16] = {
 349                 [RISC_WRITE >> 28] = 3,
 350                 [RISC_JUMP >> 28] = 3,
 351                 [RISC_SKIP >> 28] = 1,
 352                 [RISC_SYNC >> 28] = 1,
 353                 [RISC_WRITERM >> 28] = 3,
 354                 [RISC_WRITECM >> 28] = 3,
 355                 [RISC_WRITECR >> 28] = 4,
 356         };
 357         static const char * const bits[] = {
 358                 "12", "13", "14", "resync",
 359                 "cnt0", "cnt1", "18", "19",
 360                 "20", "21", "22", "23",
 361                 "irq1", "irq2", "eol", "sol",
 362         };
 363         int i;
 364
 365         pr_cont("0x%08x [ %s",
 366                 risc, instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 367         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) {
 368                 if (risc & (1 << (i + 12)))
 369                         pr_cont(" %s", bits[i]);
 370         }
 371         pr_cont(" count=%d ]\n", risc & 0xfff);
 372         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 373 }
 374
 375 static inline int i2c_slave_did_ack(struct i2c_adapter *i2c_adap)
 376 {
 377         struct cx25821_i2c *bus = i2c_adap->algo_data;
 378         struct cx25821_dev *dev = bus->dev;
 379         return cx_read(bus->reg_stat) & 0x01;
 380 }
 381
 382 void cx_i2c_read_print(struct cx25821_dev *dev, u32 reg, const char *reg_string)
 383 {
 384         int tmp = 0;
 385         u32 value = 0;
 386
 387         value = cx25821_i2c_read(&dev->i2c_bus[0], reg, &tmp);
 388 }
 389
 390 static void cx25821_registers_init(struct cx25821_dev *dev)
 391 {
 392         u32 tmp;
 393
 394         /* enable RUN_RISC in Pecos */
 395         cx_write(DEV_CNTRL2, 0x20);
 396
 397         /* Set the master PCI interrupt masks to enable video, audio, MBIF,
 398          * and GPIO interrupts
 399          * I2C interrupt masking is handled by the I2C objects themselves. */
 400         cx_write(PCI_INT_MSK, 0x2001FFFF);
 401
 402         tmp = cx_read(RDR_TLCTL0);
 403         tmp &= ~FLD_CFG_RCB_CK_EN;      /* Clear the RCB_CK_EN bit */
 404         cx_write(RDR_TLCTL0, tmp);
 405
 406         /* PLL-A setting for the Audio Master Clock */
 407         cx_write(PLL_A_INT_FRAC, 0x9807A58B);
 408
 409         /* PLL_A_POST = 0x1C, PLL_A_OUT_TO_PIN = 0x1 */
 410         cx_write(PLL_A_POST_STAT_BIST, 0x8000019C);
 411
 412         /* clear reset bit [31] */
 413         tmp = cx_read(PLL_A_INT_FRAC);
 414         cx_write(PLL_A_INT_FRAC, tmp & 0x7FFFFFFF);
 415
 416         /* PLL-B setting for Mobilygen Host Bus Interface */
 417         cx_write(PLL_B_INT_FRAC, 0x9883A86F);
 418
 419         /* PLL_B_POST = 0xD, PLL_B_OUT_TO_PIN = 0x0 */
 420         cx_write(PLL_B_POST_STAT_BIST, 0x8000018D);
 421
 422         /* clear reset bit [31] */
 423         tmp = cx_read(PLL_B_INT_FRAC);
 424         cx_write(PLL_B_INT_FRAC, tmp & 0x7FFFFFFF);
 425
 426         /* PLL-C setting for video upstream channel */
 427         cx_write(PLL_C_INT_FRAC, 0x96A0EA3F);
 428
 429         /* PLL_C_POST = 0x3, PLL_C_OUT_TO_PIN = 0x0 */
 430         cx_write(PLL_C_POST_STAT_BIST, 0x80000103);
 431
 432         /* clear reset bit [31] */
 433         tmp = cx_read(PLL_C_INT_FRAC);
 434         cx_write(PLL_C_INT_FRAC, tmp & 0x7FFFFFFF);
 435
 436         /* PLL-D setting for audio upstream channel */
 437         cx_write(PLL_D_INT_FRAC, 0x98757F5B);
 438
 439         /* PLL_D_POST = 0x13, PLL_D_OUT_TO_PIN = 0x0 */
 440         cx_write(PLL_D_POST_STAT_BIST, 0x80000113);
 441
 442         /* clear reset bit [31] */
 443         tmp = cx_read(PLL_D_INT_FRAC);
 444         cx_write(PLL_D_INT_FRAC, tmp & 0x7FFFFFFF);
 445
 446         /* This selects the PLL C clock source for the video upstream channel
 447          * I and J */
 448         tmp = cx_read(VID_CH_CLK_SEL);
 449         cx_write(VID_CH_CLK_SEL, (tmp & 0x00FFFFFF) | 0x24000000);
 450
 451         /* 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for
 452          * channel A-C
 453          * select 656/VIP DST for downstream Channel A - C */
 454         tmp = cx_read(VID_CH_MODE_SEL);
 455         /* cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF); */
 456         cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
 457
 458         /* enables 656 port I and J as output */
 459         tmp = cx_read(CLK_RST);
 460         /* use external ALT_PLL_REF pin as its reference clock instead */
 461         tmp |= FLD_USE_ALT_PLL_REF;
 462         cx_write(CLK_RST, tmp & ~(FLD_VID_I_CLK_NOE | FLD_VID_J_CLK_NOE));
 463
 464         mdelay(100);
 465 }
 466
 467 int cx25821_sram_channel_setup(struct cx25821_dev *dev,
 468                                struct sram_channel *ch,
 469                                unsigned int bpl, u32 risc)
 470 {
 471         unsigned int i, lines;
 472         u32 cdt;
 473
 474         if (ch->cmds_start == 0) {
 475                 cx_write(ch->ptr1_reg, 0);
 476                 cx_write(ch->ptr2_reg, 0);
 477                 cx_write(ch->cnt2_reg, 0);
 478                 cx_write(ch->cnt1_reg, 0);
 479                 return 0;
 480         }
 481
 482         bpl = (bpl + 7) & ~7;   /* alignment */
 483         cdt = ch->cdt;
 484         lines = ch->fifo_size / bpl;
 485
 486         if (lines > 4)
 487                 lines = 4;
 488
 489         BUG_ON(lines < 2);
 490
 491         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 492         cx_write(8 + 4, 8);
 493         cx_write(8 + 8, 0);
 494
 495         /* write CDT */
 496         for (i = 0; i < lines; i++) {
 497                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
 498                 cx_write(cdt + 16 * i + 4, 0);
 499                 cx_write(cdt + 16 * i + 8, 0);
 500                 cx_write(cdt + 16 * i + 12, 0);
 501         }
 502
 503         /* init the first cdt buffer */
 504         for (i = 0; i < 128; i++)
 505                 cx_write(ch->fifo_start + 4 * i, i);
 506
 507         /* write CMDS */
 508         if (ch->jumponly)
 509                 cx_write(ch->cmds_start + 0, 8);
 510         else
 511                 cx_write(ch->cmds_start + 0, risc);
 512
 513         cx_write(ch->cmds_start + 4, 0);        /* 64 bits 63-32 */
 514         cx_write(ch->cmds_start + 8, cdt);
 515         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
 516         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 517
 518         if (ch->jumponly)
 519                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
 520         else
 521                 cx_write(ch->cmds_start + 20, 64 >> 2);
 522
 523         for (i = 24; i < 80; i += 4)
 524                 cx_write(ch->cmds_start + i, 0);
 525
 526         /* fill registers */
 527         cx_write(ch->ptr1_reg, ch->fifo_start);
 528         cx_write(ch->ptr2_reg, cdt);
 529         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
 530         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
 531
 532         return 0;
 533 }
 534 EXPORT_SYMBOL(cx25821_sram_channel_setup);
 535
 536 int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
 537                                      struct sram_channel *ch,
 538                                      unsigned int bpl, u32 risc)
 539 {
 540         unsigned int i, lines;
 541         u32 cdt;
 542
 543         if (ch->cmds_start == 0) {
 544                 cx_write(ch->ptr1_reg, 0);
 545                 cx_write(ch->ptr2_reg, 0);
 546                 cx_write(ch->cnt2_reg, 0);
 547                 cx_write(ch->cnt1_reg, 0);
 548                 return 0;
 549         }
 550
 551         bpl = (bpl + 7) & ~7;   /* alignment */
 552         cdt = ch->cdt;
 553         lines = ch->fifo_size / bpl;
 554
 555         if (lines > 3)
 556                 lines = 3;      /* for AUDIO */
 557
 558         BUG_ON(lines < 2);
 559
 560         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 561         cx_write(8 + 4, 8);
 562         cx_write(8 + 8, 0);
 563
 564         /* write CDT */
 565         for (i = 0; i < lines; i++) {
 566                 cx_write(cdt + 16 * i, ch->fifo_start + bpl * i);
 567                 cx_write(cdt + 16 * i + 4, 0);
 568                 cx_write(cdt + 16 * i + 8, 0);
 569                 cx_write(cdt + 16 * i + 12, 0);
 570         }
 571
 572         /* write CMDS */
 573         if (ch->jumponly)
 574                 cx_write(ch->cmds_start + 0, 8);
 575         else
 576                 cx_write(ch->cmds_start + 0, risc);
 577
 578         cx_write(ch->cmds_start + 4, 0);        /* 64 bits 63-32 */
 579         cx_write(ch->cmds_start + 8, cdt);
 580         cx_write(ch->cmds_start + 12, (lines * 16) >> 3);
 581         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 582
 583         /* IQ size */
 584         if (ch->jumponly)
 585                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
 586         else
 587                 cx_write(ch->cmds_start + 20, 64 >> 2);
 588
 589         /* zero out */
 590         for (i = 24; i < 80; i += 4)
 591                 cx_write(ch->cmds_start + i, 0);
 592
 593         /* fill registers */
 594         cx_write(ch->ptr1_reg, ch->fifo_start);
 595         cx_write(ch->ptr2_reg, cdt);
 596         cx_write(ch->cnt2_reg, (lines * 16) >> 3);
 597         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
 598
 599         return 0;
 600 }
 601 EXPORT_SYMBOL(cx25821_sram_channel_setup_audio);
 602
 603 void cx25821_sram_channel_dump(struct cx25821_dev *dev, struct sram_channel *ch)
 604 {
 605         static char *name[] = {
 606                 "init risc lo",
 607                 "init risc hi",
 608                 "cdt base",
 609                 "cdt size",
 610                 "iq base",
 611                 "iq size",
 612                 "risc pc lo",
 613                 "risc pc hi",
 614                 "iq wr ptr",
 615                 "iq rd ptr",
 616                 "cdt current",
 617                 "pci target lo",
 618                 "pci target hi",
 619                 "line / byte",
 620         };
 621         u32 risc;
 622         unsigned int i, j, n;
 623
 624         pr_warn("%s: %s - dma channel status dump\n", dev->name, ch->name);
 625         for (i = 0; i < ARRAY_SIZE(name); i++)
 626                 pr_warn("cmds + 0x%2x:   %-15s: 0x%08x\n",
 627                         i * 4, name[i], cx_read(ch->cmds_start + 4 * i));
 628
 629         j = i * 4;
 630         for (i = 0; i < 4;) {
 631                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 632                 pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
 633                 i += cx25821_risc_decode(risc);
 634         }
 635
 636         for (i = 0; i < (64 >> 2); i += n) {
 637                 risc = cx_read(ch->ctrl_start + 4 * i);
 638                 /* No consideration for bits 63-32 */
 639
 640                 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
 641                         i * 4, ch->ctrl_start + 4 * i, i);
 642                 n = cx25821_risc_decode(risc);
 643                 for (j = 1; j < n; j++) {
 644                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 645                         pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
 646                                 4 * (i + j), i + j, risc, j);
 647                 }
 648         }
 649
 650         pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
 651                 ch->fifo_start, ch->fifo_start + ch->fifo_size);
 652         pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
 653                 ch->ctrl_start, ch->ctrl_start + 6 * 16);
 654         pr_warn("        :   ptr1_reg: 0x%08x\n",
 655                 cx_read(ch->ptr1_reg));
 656         pr_warn("        :   ptr2_reg: 0x%08x\n",
 657                 cx_read(ch->ptr2_reg));
 658         pr_warn("        :   cnt1_reg: 0x%08x\n",
 659                 cx_read(ch->cnt1_reg));
 660         pr_warn("        :   cnt2_reg: 0x%08x\n",
 661                 cx_read(ch->cnt2_reg));
 662 }
 663 EXPORT_SYMBOL(cx25821_sram_channel_dump);
 664
 665 void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
 666                                      struct sram_channel *ch)
 667 {
 668         static const char * const name[] = {
 669                 "init risc lo",
 670                 "init risc hi",
 671                 "cdt base",
 672                 "cdt size",
 673                 "iq base",
 674                 "iq size",
 675                 "risc pc lo",
 676                 "risc pc hi",
 677                 "iq wr ptr",
 678                 "iq rd ptr",
 679                 "cdt current",
 680                 "pci target lo",
 681                 "pci target hi",
 682                 "line / byte",
 683         };
 684
 685         u32 risc, value, tmp;
 686         unsigned int i, j, n;
 687
 688         pr_info("\n%s: %s - dma Audio channel status dump\n",
 689                 dev->name, ch->name);
 690
 691         for (i = 0; i < ARRAY_SIZE(name); i++)
 692                 pr_info("%s: cmds + 0x%2x:   %-15s: 0x%08x\n",
 693                         dev->name, i * 4, name[i],
 694                         cx_read(ch->cmds_start + 4 * i));
 695
 696         j = i * 4;
 697         for (i = 0; i < 4;) {
 698                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 699                 pr_warn("cmds + 0x%2x:   risc%d: ", j + i * 4, i);
 700                 i += cx25821_risc_decode(risc);
 701         }
 702
 703         for (i = 0; i < (64 >> 2); i += n) {
 704                 risc = cx_read(ch->ctrl_start + 4 * i);
 705                 /* No consideration for bits 63-32 */
 706
 707                 pr_warn("ctrl + 0x%2x (0x%08x): iq %x: ",
 708                         i * 4, ch->ctrl_start + 4 * i, i);
 709                 n = cx25821_risc_decode(risc);
 710
 711                 for (j = 1; j < n; j++) {
 712                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 713                         pr_warn("ctrl + 0x%2x :   iq %x: 0x%08x [ arg #%d ]\n",
 714                                 4 * (i + j), i + j, risc, j);
 715                 }
 716         }
 717
 718         pr_warn("        :   fifo: 0x%08x -> 0x%x\n",
 719                 ch->fifo_start, ch->fifo_start + ch->fifo_size);
 720         pr_warn("        :   ctrl: 0x%08x -> 0x%x\n",
 721                 ch->ctrl_start, ch->ctrl_start + 6 * 16);
 722         pr_warn("        :   ptr1_reg: 0x%08x\n",
 723                 cx_read(ch->ptr1_reg));
 724         pr_warn("        :   ptr2_reg: 0x%08x\n",
 725                 cx_read(ch->ptr2_reg));
 726         pr_warn("        :   cnt1_reg: 0x%08x\n",
 727                 cx_read(ch->cnt1_reg));
 728         pr_warn("        :   cnt2_reg: 0x%08x\n",
 729                 cx_read(ch->cnt2_reg));
 730
 731         for (i = 0; i < 4; i++) {
 732                 risc = cx_read(ch->cmds_start + 56 + (i * 4));
 733                 pr_warn("instruction %d = 0x%x\n", i, risc);
 734         }
 735
 736         /* read data from the first cdt buffer */
 737         risc = cx_read(AUD_A_CDT);
 738         pr_warn("\nread cdt loc=0x%x\n", risc);
 739         for (i = 0; i < 8; i++) {
 740                 n = cx_read(risc + i * 4);
 741                 pr_cont("0x%x ", n);
 742         }
 743         pr_cont("\n\n");
 744
 745         value = cx_read(CLK_RST);
 746         CX25821_INFO(" CLK_RST = 0x%x\n\n", value);
 747
 748         value = cx_read(PLL_A_POST_STAT_BIST);
 749         CX25821_INFO(" PLL_A_POST_STAT_BIST = 0x%x\n\n", value);
 750         value = cx_read(PLL_A_INT_FRAC);
 751         CX25821_INFO(" PLL_A_INT_FRAC = 0x%x\n\n", value);
 752
 753         value = cx_read(PLL_B_POST_STAT_BIST);
 754         CX25821_INFO(" PLL_B_POST_STAT_BIST = 0x%x\n\n", value);
 755         value = cx_read(PLL_B_INT_FRAC);
 756         CX25821_INFO(" PLL_B_INT_FRAC = 0x%x\n\n", value);
 757
 758         value = cx_read(PLL_C_POST_STAT_BIST);
 759         CX25821_INFO(" PLL_C_POST_STAT_BIST = 0x%x\n\n", value);
 760         value = cx_read(PLL_C_INT_FRAC);
 761         CX25821_INFO(" PLL_C_INT_FRAC = 0x%x\n\n", value);
 762
 763         value = cx_read(PLL_D_POST_STAT_BIST);
 764         CX25821_INFO(" PLL_D_POST_STAT_BIST = 0x%x\n\n", value);
 765         value = cx_read(PLL_D_INT_FRAC);
 766         CX25821_INFO(" PLL_D_INT_FRAC = 0x%x\n\n", value);
 767
 768         value = cx25821_i2c_read(&dev->i2c_bus[0], AFE_AB_DIAG_CTRL, &tmp);
 769         CX25821_INFO(" AFE_AB_DIAG_CTRL (0x10900090) = 0x%x\n\n", value);
 770 }
 771 EXPORT_SYMBOL(cx25821_sram_channel_dump_audio);
 772
 773 static void cx25821_shutdown(struct cx25821_dev *dev)
 774 {
 775         int i;
 776
 777         /* disable RISC controller */
 778         cx_write(DEV_CNTRL2, 0);
 779
 780         /* Disable Video A/B activity */
 781         for (i = 0; i < VID_CHANNEL_NUM; i++) {
 782                 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
 783                 cx_write(dev->channels[i].sram_channels->int_msk, 0);
 784         }
 785
 786         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
 787                 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
 788                 cx_write(dev->channels[i].sram_channels->dma_ctl, 0);
 789                 cx_write(dev->channels[i].sram_channels->int_msk, 0);
 790         }
 791
 792         /* Disable Audio activity */
 793         cx_write(AUD_INT_DMA_CTL, 0);
 794
 795         /* Disable Serial port */
 796         cx_write(UART_CTL, 0);
 797
 798         /* Disable Interrupts */
 799         cx_write(PCI_INT_MSK, 0);
 800         cx_write(AUD_A_INT_MSK, 0);
 801 }
 802
 803 void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel_select,
 804                               u32 format)
 805 {
 806         if (channel_select <= 7 && channel_select >= 0) {
 807                 cx_write(dev->channels[channel_select].
 808                         sram_channels->pix_frmt, format);
 809                 dev->channels[channel_select].pixel_formats = format;
 810         }
 811 }
 812
 813 static void cx25821_set_vip_mode(struct cx25821_dev *dev,
 814                                  struct sram_channel *ch)
 815 {
 816         cx_write(ch->pix_frmt, PIXEL_FRMT_422);
 817         cx_write(ch->vip_ctl, PIXEL_ENGINE_VIP1);
 818 }
 819
 820 static void cx25821_initialize(struct cx25821_dev *dev)
 821 {
 822         int i;
 823
 824         dprintk(1, "%s()\n", __func__);
 825
 826         cx25821_shutdown(dev);
 827         cx_write(PCI_INT_STAT, 0xffffffff);
 828
 829         for (i = 0; i < VID_CHANNEL_NUM; i++)
 830                 cx_write(dev->channels[i].sram_channels->int_stat, 0xffffffff);
 831
 832         cx_write(AUD_A_INT_STAT, 0xffffffff);
 833         cx_write(AUD_B_INT_STAT, 0xffffffff);
 834         cx_write(AUD_C_INT_STAT, 0xffffffff);
 835         cx_write(AUD_D_INT_STAT, 0xffffffff);
 836         cx_write(AUD_E_INT_STAT, 0xffffffff);
 837
 838         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 839         cx_write(PAD_CTRL, 0x12);       /* for I2C */
 840         cx25821_registers_init(dev);    /* init Pecos registers */
 841         mdelay(100);
 842
 843         for (i = 0; i < VID_CHANNEL_NUM; i++) {
 844                 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
 845                 cx25821_sram_channel_setup(dev, dev->channels[i].sram_channels,
 846                                                 1440, 0);
 847                 dev->channels[i].pixel_formats = PIXEL_FRMT_422;
 848                 dev->channels[i].use_cif_resolution = FALSE;
 849         }
 850
 851         /* Probably only affect Downstream */
 852         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
 853                 i <= VID_UPSTREAM_SRAM_CHANNEL_J; i++) {
 854                 cx25821_set_vip_mode(dev, dev->channels[i].sram_channels);
 855         }
 856
 857         cx25821_sram_channel_setup_audio(dev,
 858                                 dev->channels[SRAM_CH08].sram_channels,
 859                                 128, 0);
 860
 861         cx25821_gpio_init(dev);
 862 }
 863
 864 static int cx25821_get_resources(struct cx25821_dev *dev)
 865 {
 866         if (request_mem_region
 867             (pci_resource_start(dev->pci, 0), pci_resource_len(dev->pci, 0),
 868              dev->name))
 869                 return 0;
 870
 871         pr_err("%s: can't get MMIO memory @ 0x%llx\n",
 872                dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
 873
 874         return -EBUSY;
 875 }
 876
 877 static void cx25821_dev_checkrevision(struct cx25821_dev *dev)
 878 {
 879         dev->hwrevision = cx_read(RDR_CFG2) & 0xff;
 880
 881         pr_info("%s(): Hardware revision = 0x%02x\n",
 882                 __func__, dev->hwrevision);
 883 }
 884
 885 static void cx25821_iounmap(struct cx25821_dev *dev)
 886 {
 887         if (dev == NULL)
 888                 return;
 889
 890         /* Releasing IO memory */
 891         if (dev->lmmio != NULL) {
 892                 CX25821_INFO("Releasing lmmio.\n");
 893                 iounmap(dev->lmmio);
 894                 dev->lmmio = NULL;
 895         }
 896 }
 897
 898 static int cx25821_dev_setup(struct cx25821_dev *dev)
 899 {
 900         int io_size = 0, i;
 901
 902         pr_info("\n***********************************\n");
 903         pr_info("cx25821 set up\n");
 904         pr_info("***********************************\n\n");
 905
 906         mutex_init(&dev->lock);
 907
 908         atomic_inc(&dev->refcount);
 909
 910         dev->nr = ++cx25821_devcount;
 911         sprintf(dev->name, "cx25821[%d]", dev->nr);
 912
 913         mutex_lock(&cx25821_devlist_mutex);
 914         list_add_tail(&dev->devlist, &cx25821_devlist);
 915         mutex_unlock(&cx25821_devlist_mutex);
 916
 917         if (dev->pci->device != 0x8210) {
 918                 pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n",
 919                         __func__, dev->pci->device);
 920                 return -1;
 921         } else {
 922                 pr_info("Athena Hardware device = 0x%02x\n", dev->pci->device);
 923         }
 924
 925         /* Apply a sensible clock frequency for the PCIe bridge */
 926         dev->clk_freq = 28000000;
 927         for (i = 0; i < MAX_VID_CHANNEL_NUM; i++)
 928                 dev->channels[i].sram_channels = &cx25821_sram_channels[i];
 929
 930         if (dev->nr > 1)
 931                 CX25821_INFO("dev->nr > 1!");
 932
 933         /* board config */
 934         dev->board = 1;         /* card[dev->nr]; */
 935         dev->_max_num_decoders = MAX_DECODERS;
 936
 937         dev->pci_bus = dev->pci->bus->number;
 938         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 939         dev->pci_irqmask = 0x001f00;
 940
 941         /* External Master 1 Bus */
 942         dev->i2c_bus[0].nr = 0;
 943         dev->i2c_bus[0].dev = dev;
 944         dev->i2c_bus[0].reg_stat = I2C1_STAT;
 945         dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
 946         dev->i2c_bus[0].reg_addr = I2C1_ADDR;
 947         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 948         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 949         dev->i2c_bus[0].i2c_period = (0x07 << 24);      /* 1.95MHz */
 950
 951         if (cx25821_get_resources(dev) < 0) {
 952                 pr_err("%s: No more PCIe resources for subsystem: %04x:%04x\n",
 953                        dev->name, dev->pci->subsystem_vendor,
 954                        dev->pci->subsystem_device);
 955
 956                 cx25821_devcount--;
 957                 return -EBUSY;
 958         }
 959
 960         /* PCIe stuff */
 961         dev->base_io_addr = pci_resource_start(dev->pci, 0);
 962         io_size = pci_resource_len(dev->pci, 0);
 963
 964         if (!dev->base_io_addr) {
 965                 CX25821_ERR("No PCI Memory resources, exiting!\n");
 966                 return -ENODEV;
 967         }
 968
 969         dev->lmmio = ioremap(dev->base_io_addr, pci_resource_len(dev->pci, 0));
 970
 971         if (!dev->lmmio) {
 972                 CX25821_ERR
 973                     ("ioremap failed, maybe increasing __VMALLOC_RESERVE in page.h\n");
 974                 cx25821_iounmap(dev);
 975                 return -ENOMEM;
 976         }
 977
 978         dev->bmmio = (u8 __iomem *) dev->lmmio;
 979
 980         pr_info("%s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 981                 dev->name, dev->pci->subsystem_vendor,
 982                 dev->pci->subsystem_device, cx25821_boards[dev->board].name,
 983                 dev->board, card[dev->nr] == dev->board ?
 984                 "insmod option" : "autodetected");
 985
 986         /* init hardware */
 987         cx25821_initialize(dev);
 988
 989         cx25821_i2c_register(&dev->i2c_bus[0]);
 990 /*  cx25821_i2c_register(&dev->i2c_bus[1]);
 991  *  cx25821_i2c_register(&dev->i2c_bus[2]); */
 992
 993         CX25821_INFO("i2c register! bus->i2c_rc = %d\n",
 994                      dev->i2c_bus[0].i2c_rc);
 995
 996         cx25821_card_setup(dev);
 997
 998         if (medusa_video_init(dev) < 0)
 999                 CX25821_ERR("%s(): Failed to initialize medusa!\n", __func__);
1000
1001         cx25821_video_register(dev);
1002
1003         /* register IOCTL device */
1004         dev->ioctl_dev =
1005            cx25821_vdev_init(dev, dev->pci, &cx25821_videoioctl_template,
1006                               "video");
1007
1008         if (video_register_device
1009             (dev->ioctl_dev, VFL_TYPE_GRABBER, VIDEO_IOCTL_CH) < 0) {
1010                 cx25821_videoioctl_unregister(dev);
1011                 pr_err("%s(): Failed to register video adapter for IOCTL, so unregistering videoioctl device\n",
1012                        __func__);
1013         }
1014
1015         cx25821_dev_checkrevision(dev);
1016         CX25821_INFO("setup done!\n");
1017
1018         return 0;
1019 }
1020
1021 void cx25821_start_upstream_video_ch1(struct cx25821_dev *dev,
1022                                       struct upstream_user_struct *up_data)
1023 {
1024         dev->_isNTSC = !strcmp(dev->vid_stdname, "NTSC") ? 1 : 0;
1025
1026         dev->tvnorm = !dev->_isNTSC ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1027         medusa_set_videostandard(dev);
1028
1029         cx25821_vidupstream_init_ch1(dev, dev->channel_select,
1030                                      dev->pixel_format);
1031 }
1032
1033 void cx25821_start_upstream_video_ch2(struct cx25821_dev *dev,
1034                                       struct upstream_user_struct *up_data)
1035 {
1036         dev->_isNTSC_ch2 = !strcmp(dev->vid_stdname_ch2, "NTSC") ? 1 : 0;
1037
1038         dev->tvnorm = !dev->_isNTSC_ch2 ? V4L2_STD_PAL_BG : V4L2_STD_NTSC_M;
1039         medusa_set_videostandard(dev);
1040
1041         cx25821_vidupstream_init_ch2(dev, dev->channel_select_ch2,
1042                                      dev->pixel_format_ch2);
1043 }
1044
1045 void cx25821_start_upstream_audio(struct cx25821_dev *dev,
1046                                   struct upstream_user_struct *up_data)
1047 {
1048         cx25821_audio_upstream_init(dev, AUDIO_UPSTREAM_SRAM_CHANNEL_B);
1049 }
1050
1051 void cx25821_dev_unregister(struct cx25821_dev *dev)
1052 {
1053         int i;
1054
1055         if (!dev->base_io_addr)
1056                 return;
1057
1058         cx25821_free_mem_upstream_ch1(dev);
1059         cx25821_free_mem_upstream_ch2(dev);
1060         cx25821_free_mem_upstream_audio(dev);
1061
1062         release_mem_region(dev->base_io_addr, pci_resource_len(dev->pci, 0));
1063
1064         if (!atomic_dec_and_test(&dev->refcount))
1065                 return;
1066
1067         for (i = 0; i < VID_CHANNEL_NUM; i++)
1068                 cx25821_video_unregister(dev, i);
1069
1070         for (i = VID_UPSTREAM_SRAM_CHANNEL_I;
1071              i <= AUDIO_UPSTREAM_SRAM_CHANNEL_B; i++) {
1072                 cx25821_video_unregister(dev, i);
1073         }
1074
1075         cx25821_videoioctl_unregister(dev);
1076
1077         cx25821_i2c_unregister(&dev->i2c_bus[0]);
1078         cx25821_iounmap(dev);
1079 }
1080 EXPORT_SYMBOL(cx25821_dev_unregister);
1081
1082 static __le32 *cx25821_risc_field(__le32 * rp, struct scatterlist *sglist,
1083                                   unsigned int offset, u32 sync_line,
1084                                   unsigned int bpl, unsigned int padding,
1085                                   unsigned int lines)
1086 {
1087         struct scatterlist *sg;
1088         unsigned int line, todo;
1089
1090         /* sync instruction */
1091         if (sync_line != NO_SYNC_LINE)
1092                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1093
1094         /* scan lines */
1095         sg = sglist;
1096         for (line = 0; line < lines; line++) {
1097                 while (offset && offset >= sg_dma_len(sg)) {
1098                         offset -= sg_dma_len(sg);
1099                         sg++;
1100                 }
1101                 if (bpl <= sg_dma_len(sg) - offset) {
1102                         /* fits into current chunk */
1103                         *(rp++) =
1104                             cpu_to_le32(RISC_WRITE | RISC_SOL | RISC_EOL | bpl);
1105                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1106                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1107                         offset += bpl;
1108                 } else {
1109                         /* scanline needs to be split */
1110                         todo = bpl;
1111                         *(rp++) =
1112                             cpu_to_le32(RISC_WRITE | RISC_SOL |
1113                                         (sg_dma_len(sg) - offset));
1114                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1115                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1116                         todo -= (sg_dma_len(sg) - offset);
1117                         offset = 0;
1118                         sg++;
1119                         while (todo > sg_dma_len(sg)) {
1120                                 *(rp++) =
1121                                     cpu_to_le32(RISC_WRITE | sg_dma_len(sg));
1122                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1123                                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1124                                 todo -= sg_dma_len(sg);
1125                                 sg++;
1126                         }
1127                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1128                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1129                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1130                         offset += todo;
1131                 }
1132
1133                 offset += padding;
1134         }
1135
1136         return rp;
1137 }
1138
1139 int cx25821_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1140                         struct scatterlist *sglist, unsigned int top_offset,
1141                         unsigned int bottom_offset, unsigned int bpl,
1142                         unsigned int padding, unsigned int lines)
1143 {
1144         u32 instructions;
1145         u32 fields;
1146         __le32 *rp;
1147         int rc;
1148
1149         fields = 0;
1150         if (UNSET != top_offset)
1151                 fields++;
1152         if (UNSET != bottom_offset)
1153                 fields++;
1154
1155         /* estimate risc mem: worst case is one write per page border +
1156            one write per scan line + syncs + jump (all 2 dwords).  Padding
1157            can cause next bpl to start close to a page border.  First DMA
1158            region may be smaller than PAGE_SIZE */
1159         /* write and jump need and extra dword */
1160         instructions =
1161             fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
1162         instructions += 2;
1163         rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1164
1165         if (rc < 0)
1166                 return rc;
1167
1168         /* write risc instructions */
1169         rp = risc->cpu;
1170
1171         if (UNSET != top_offset) {
1172                 rp = cx25821_risc_field(rp, sglist, top_offset, 0, bpl, padding,
1173                                         lines);
1174         }
1175
1176         if (UNSET != bottom_offset) {
1177                 rp = cx25821_risc_field(rp, sglist, bottom_offset, 0x200, bpl,
1178                                         padding, lines);
1179         }
1180
1181         /* save pointer to jmp instruction address */
1182         risc->jmp = rp;
1183         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1184
1185         return 0;
1186 }
1187
1188 static __le32 *cx25821_risc_field_audio(__le32 * rp, struct scatterlist *sglist,
1189                                         unsigned int offset, u32 sync_line,
1190                                         unsigned int bpl, unsigned int padding,
1191                                         unsigned int lines, unsigned int lpi)
1192 {
1193         struct scatterlist *sg;
1194         unsigned int line, todo, sol;
1195
1196         /* sync instruction */
1197         if (sync_line != NO_SYNC_LINE)
1198                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1199
1200         /* scan lines */
1201         sg = sglist;
1202         for (line = 0; line < lines; line++) {
1203                 while (offset && offset >= sg_dma_len(sg)) {
1204                         offset -= sg_dma_len(sg);
1205                         sg++;
1206                 }
1207
1208                 if (lpi && line > 0 && !(line % lpi))
1209                         sol = RISC_SOL | RISC_IRQ1 | RISC_CNT_INC;
1210                 else
1211                         sol = RISC_SOL;
1212
1213                 if (bpl <= sg_dma_len(sg) - offset) {
1214                         /* fits into current chunk */
1215                         *(rp++) =
1216                             cpu_to_le32(RISC_WRITE | sol | RISC_EOL | bpl);
1217                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1218                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1219                         offset += bpl;
1220                 } else {
1221                         /* scanline needs to be split */
1222                         todo = bpl;
1223                         *(rp++) = cpu_to_le32(RISC_WRITE | sol |
1224                                               (sg_dma_len(sg) - offset));
1225                         *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
1226                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1227                         todo -= (sg_dma_len(sg) - offset);
1228                         offset = 0;
1229                         sg++;
1230                         while (todo > sg_dma_len(sg)) {
1231                                 *(rp++) = cpu_to_le32(RISC_WRITE |
1232                                                       sg_dma_len(sg));
1233                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1234                                 *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1235                                 todo -= sg_dma_len(sg);
1236                                 sg++;
1237                         }
1238                         *(rp++) = cpu_to_le32(RISC_WRITE | RISC_EOL | todo);
1239                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1240                         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1241                         offset += todo;
1242                 }
1243                 offset += padding;
1244         }
1245
1246         return rp;
1247 }
1248
1249 int cx25821_risc_databuffer_audio(struct pci_dev *pci,
1250                                   struct btcx_riscmem *risc,
1251                                   struct scatterlist *sglist,
1252                                   unsigned int bpl,
1253                                   unsigned int lines, unsigned int lpi)
1254 {
1255         u32 instructions;
1256         __le32 *rp;
1257         int rc;
1258
1259         /* estimate risc mem: worst case is one write per page border +
1260            one write per scan line + syncs + jump (all 2 dwords).  Here
1261            there is no padding and no sync.  First DMA region may be smaller
1262            than PAGE_SIZE */
1263         /* Jump and write need an extra dword */
1264         instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1265         instructions += 1;
1266
1267         rc = btcx_riscmem_alloc(pci, risc, instructions * 12);
1268         if (rc < 0)
1269                 return rc;
1270
1271         /* write risc instructions */
1272         rp = risc->cpu;
1273         rp = cx25821_risc_field_audio(rp, sglist, 0, NO_SYNC_LINE, bpl, 0,
1274                                       lines, lpi);
1275
1276         /* save pointer to jmp instruction address */
1277         risc->jmp = rp;
1278         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1279         return 0;
1280 }
1281 EXPORT_SYMBOL(cx25821_risc_databuffer_audio);
1282
1283 int cx25821_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1284                          u32 reg, u32 mask, u32 value)
1285 {
1286         __le32 *rp;
1287         int rc;
1288
1289         rc = btcx_riscmem_alloc(pci, risc, 4 * 16);
1290
1291         if (rc < 0)
1292                 return rc;
1293
1294         /* write risc instructions */
1295         rp = risc->cpu;
1296
1297         *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ1);
1298         *(rp++) = cpu_to_le32(reg);
1299         *(rp++) = cpu_to_le32(value);
1300         *(rp++) = cpu_to_le32(mask);
1301         *(rp++) = cpu_to_le32(RISC_JUMP);
1302         *(rp++) = cpu_to_le32(risc->dma);
1303         *(rp++) = cpu_to_le32(0);       /* bits 63-32 */
1304         return 0;
1305 }
1306
1307 void cx25821_free_buffer(struct videobuf_queue *q, struct cx25821_buffer *buf)
1308 {
1309         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1310
1311         BUG_ON(in_interrupt());
1312         videobuf_waiton(q, &buf->vb, 0, 0);
1313         videobuf_dma_unmap(q->dev, dma);
1314         videobuf_dma_free(dma);
1315         btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1316         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1317 }
1318
1319 static irqreturn_t cx25821_irq(int irq, void *dev_id)
1320 {
1321         struct cx25821_dev *dev = dev_id;
1322         u32 pci_status, pci_mask;
1323         u32 vid_status;
1324         int i, handled = 0;
1325         u32 mask[8] = { 1, 2, 4, 8, 16, 32, 64, 128 };
1326
1327         pci_status = cx_read(PCI_INT_STAT);
1328         pci_mask = cx_read(PCI_INT_MSK);
1329
1330         if (pci_status == 0)
1331                 goto out;
1332
1333         for (i = 0; i < VID_CHANNEL_NUM; i++) {
1334                 if (pci_status & mask[i]) {
1335                         vid_status = cx_read(dev->channels[i].
1336                                 sram_channels->int_stat);
1337
1338                         if (vid_status)
1339                                 handled +=
1340                                 cx25821_video_irq(dev, i, vid_status);
1341
1342                         cx_write(PCI_INT_STAT, mask[i]);
1343                 }
1344         }
1345
1346 out:
1347         return IRQ_RETVAL(handled);
1348 }
1349
1350 void cx25821_print_irqbits(char *name, char *tag, char **strings,
1351                            int len, u32 bits, u32 mask)
1352 {
1353         unsigned int i;
1354
1355         printk(KERN_DEBUG pr_fmt("%s: %s [0x%x]"), name, tag, bits);
1356
1357         for (i = 0; i < len; i++) {
1358                 if (!(bits & (1 << i)))
1359                         continue;
1360                 if (strings[i])
1361                         pr_cont(" %s", strings[i]);
1362                 else
1363                         pr_cont(" %d", i);
1364                 if (!(mask & (1 << i)))
1365                         continue;
1366                 pr_cont("*");
1367         }
1368         pr_cont("\n");
1369 }
1370 EXPORT_SYMBOL(cx25821_print_irqbits);
1371
1372 struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci)
1373 {
1374         struct cx25821_dev *dev = pci_get_drvdata(pci);
1375         return dev;
1376 }
1377 EXPORT_SYMBOL(cx25821_dev_get);
1378
1379 static int __devinit cx25821_initdev(struct pci_dev *pci_dev,
1380                                      const struct pci_device_id *pci_id)
1381 {
1382         struct cx25821_dev *dev;
1383         int err = 0;
1384
1385         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1386         if (NULL == dev)
1387                 return -ENOMEM;
1388
1389         err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
1390         if (err < 0)
1391                 goto fail_free;
1392
1393         /* pci init */
1394         dev->pci = pci_dev;
1395         if (pci_enable_device(pci_dev)) {
1396                 err = -EIO;
1397
1398                 pr_info("pci enable failed!\n");
1399
1400                 goto fail_unregister_device;
1401         }
1402
1403         pr_info("Athena pci enable !\n");
1404
1405         err = cx25821_dev_setup(dev);
1406         if (err) {
1407                 if (err == -EBUSY)
1408                         goto fail_unregister_device;
1409                 else
1410                         goto fail_unregister_pci;
1411         }
1412
1413         /* print pci info */
1414         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1415         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1416         pr_info("%s/0: found at %s, rev: %d, irq: %d, latency: %d, mmio: 0x%llx\n",
1417                 dev->name, pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1418                 dev->pci_lat, (unsigned long long)dev->base_io_addr);
1419
1420         pci_set_master(pci_dev);
1421         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1422                 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1423                 err = -EIO;
1424                 goto fail_irq;
1425         }
1426
1427         err =
1428             request_irq(pci_dev->irq, cx25821_irq, IRQF_SHARED,
1429                         dev->name, dev);
1430
1431         if (err < 0) {
1432                 pr_err("%s: can't get IRQ %d\n", dev->name, pci_dev->irq);
1433                 goto fail_irq;
1434         }
1435
1436         return 0;
1437
1438 fail_irq:
1439         pr_info("cx25821_initdev() can't get IRQ !\n");
1440         cx25821_dev_unregister(dev);
1441
1442 fail_unregister_pci:
1443         pci_disable_device(pci_dev);
1444 fail_unregister_device:
1445         v4l2_device_unregister(&dev->v4l2_dev);
1446
1447 fail_free:
1448         kfree(dev);
1449         return err;
1450 }
1451
1452 static void __devexit cx25821_finidev(struct pci_dev *pci_dev)
1453 {
1454         struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
1455         struct cx25821_dev *dev = get_cx25821(v4l2_dev);
1456
1457         cx25821_shutdown(dev);
1458         pci_disable_device(pci_dev);
1459
1460         /* unregister stuff */
1461         if (pci_dev->irq)
1462                 free_irq(pci_dev->irq, dev);
1463
1464         mutex_lock(&cx25821_devlist_mutex);
1465         list_del(&dev->devlist);
1466         mutex_unlock(&cx25821_devlist_mutex);
1467
1468         cx25821_dev_unregister(dev);
1469         v4l2_device_unregister(v4l2_dev);
1470         kfree(dev);
1471 }
1472
1473 static DEFINE_PCI_DEVICE_TABLE(cx25821_pci_tbl) = {
1474         {
1475                 /* CX25821 Athena */
1476                 .vendor = 0x14f1,
1477                 .device = 0x8210,
1478                 .subvendor = 0x14f1,
1479                 .subdevice = 0x0920,
1480         },
1481         {
1482                 /* --- end of list --- */
1483         }
1484 };
1485
1486 MODULE_DEVICE_TABLE(pci, cx25821_pci_tbl);
1487
1488 static struct pci_driver cx25821_pci_driver = {
1489         .name = "cx25821",
1490         .id_table = cx25821_pci_tbl,
1491         .probe = cx25821_initdev,
1492         .remove = __devexit_p(cx25821_finidev),
1493         /* TODO */
1494         .suspend = NULL,
1495         .resume = NULL,
1496 };
1497
1498 static int __init cx25821_init(void)
1499 {
1500         pr_info("driver version %d.%d.%d loaded\n",
1501                 (CX25821_VERSION_CODE >> 16) & 0xff,
1502                 (CX25821_VERSION_CODE >> 8) & 0xff,
1503                 CX25821_VERSION_CODE & 0xff);
1504         return pci_register_driver(&cx25821_pci_driver);
1505 }
1506
1507 static void __exit cx25821_fini(void)
1508 {
1509         pci_unregister_driver(&cx25821_pci_driver);
1510 }
1511
1512
1513 module_init(cx25821_init);
1514 module_exit(cx25821_fini);