drivers/media/video/cx23885/cx23885-core.c

   1 /*
   2  *  Driver for the Conexant CX23885 PCIe bridge
   3  *
   4  *  Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *
  15  *  GNU General Public License for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License
  18  *  along with this program; if not, write to the Free Software
  19  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/module.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/kmod.h>
  27 #include <linux/kernel.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/delay.h>
  31 #include <asm/div64.h>
  32
  33 #include "cx23885.h"
  34 #include "cimax2.h"
  35 #include "cx23888-ir.h"
  36 #include "cx23885-ir.h"
  37 #include "cx23885-av.h"
  38 #include "cx23885-input.h"
  39
  40 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
  41 MODULE_AUTHOR("Steven Toth <stoth@linuxtv.org>");
  42 MODULE_LICENSE("GPL");
  43
  44 static unsigned int debug;
  45 module_param(debug, int, 0644);
  46 MODULE_PARM_DESC(debug, "enable debug messages");
  47
  48 static unsigned int card[]  = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
  49 module_param_array(card,  int, NULL, 0444);
  50 MODULE_PARM_DESC(card, "card type");
  51
  52 #define dprintk(level, fmt, arg...)\
  53         do { if (debug >= level)\
  54                 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  55         } while (0)
  56
  57 static unsigned int cx23885_devcount;
  58
  59 #define NO_SYNC_LINE (-1U)
  60
  61 /* FIXME, these allocations will change when
  62  * analog arrives. The be reviewed.
  63  * CX23887 Assumptions
  64  * 1 line = 16 bytes of CDT
  65  * cmds size = 80
  66  * cdt size = 16 * linesize
  67  * iqsize = 64
  68  * maxlines = 6
  69  *
  70  * Address Space:
  71  * 0x00000000 0x00008fff FIFO clusters
  72  * 0x00010000 0x000104af Channel Management Data Structures
  73  * 0x000104b0 0x000104ff Free
  74  * 0x00010500 0x000108bf 15 channels * iqsize
  75  * 0x000108c0 0x000108ff Free
  76  * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
  77  *                       15 channels * (iqsize + (maxlines * linesize))
  78  * 0x00010ea0 0x00010xxx Free
  79  */
  80
  81 static struct sram_channel cx23885_sram_channels[] = {
  82         [SRAM_CH01] = {
  83                 .name           = "VID A",
  84                 .cmds_start     = 0x10000,
  85                 .ctrl_start     = 0x10380,
  86                 .cdt            = 0x104c0,
  87                 .fifo_start     = 0x40,
  88                 .fifo_size      = 0x2800,
  89                 .ptr1_reg       = DMA1_PTR1,
  90                 .ptr2_reg       = DMA1_PTR2,
  91                 .cnt1_reg       = DMA1_CNT1,
  92                 .cnt2_reg       = DMA1_CNT2,
  93         },
  94         [SRAM_CH02] = {
  95                 .name           = "ch2",
  96                 .cmds_start     = 0x0,
  97                 .ctrl_start     = 0x0,
  98                 .cdt            = 0x0,
  99                 .fifo_start     = 0x0,
 100                 .fifo_size      = 0x0,
 101                 .ptr1_reg       = DMA2_PTR1,
 102                 .ptr2_reg       = DMA2_PTR2,
 103                 .cnt1_reg       = DMA2_CNT1,
 104                 .cnt2_reg       = DMA2_CNT2,
 105         },
 106         [SRAM_CH03] = {
 107                 .name           = "TS1 B",
 108                 .cmds_start     = 0x100A0,
 109                 .ctrl_start     = 0x10400,
 110                 .cdt            = 0x10580,
 111                 .fifo_start     = 0x5000,
 112                 .fifo_size      = 0x1000,
 113                 .ptr1_reg       = DMA3_PTR1,
 114                 .ptr2_reg       = DMA3_PTR2,
 115                 .cnt1_reg       = DMA3_CNT1,
 116                 .cnt2_reg       = DMA3_CNT2,
 117         },
 118         [SRAM_CH04] = {
 119                 .name           = "ch4",
 120                 .cmds_start     = 0x0,
 121                 .ctrl_start     = 0x0,
 122                 .cdt            = 0x0,
 123                 .fifo_start     = 0x0,
 124                 .fifo_size      = 0x0,
 125                 .ptr1_reg       = DMA4_PTR1,
 126                 .ptr2_reg       = DMA4_PTR2,
 127                 .cnt1_reg       = DMA4_CNT1,
 128                 .cnt2_reg       = DMA4_CNT2,
 129         },
 130         [SRAM_CH05] = {
 131                 .name           = "ch5",
 132                 .cmds_start     = 0x0,
 133                 .ctrl_start     = 0x0,
 134                 .cdt            = 0x0,
 135                 .fifo_start     = 0x0,
 136                 .fifo_size      = 0x0,
 137                 .ptr1_reg       = DMA5_PTR1,
 138                 .ptr2_reg       = DMA5_PTR2,
 139                 .cnt1_reg       = DMA5_CNT1,
 140                 .cnt2_reg       = DMA5_CNT2,
 141         },
 142         [SRAM_CH06] = {
 143                 .name           = "TS2 C",
 144                 .cmds_start     = 0x10140,
 145                 .ctrl_start     = 0x10440,
 146                 .cdt            = 0x105e0,
 147                 .fifo_start     = 0x6000,
 148                 .fifo_size      = 0x1000,
 149                 .ptr1_reg       = DMA5_PTR1,
 150                 .ptr2_reg       = DMA5_PTR2,
 151                 .cnt1_reg       = DMA5_CNT1,
 152                 .cnt2_reg       = DMA5_CNT2,
 153         },
 154         [SRAM_CH07] = {
 155                 .name           = "ch7",
 156                 .cmds_start     = 0x0,
 157                 .ctrl_start     = 0x0,
 158                 .cdt            = 0x0,
 159                 .fifo_start     = 0x0,
 160                 .fifo_size      = 0x0,
 161                 .ptr1_reg       = DMA6_PTR1,
 162                 .ptr2_reg       = DMA6_PTR2,
 163                 .cnt1_reg       = DMA6_CNT1,
 164                 .cnt2_reg       = DMA6_CNT2,
 165         },
 166         [SRAM_CH08] = {
 167                 .name           = "ch8",
 168                 .cmds_start     = 0x0,
 169                 .ctrl_start     = 0x0,
 170                 .cdt            = 0x0,
 171                 .fifo_start     = 0x0,
 172                 .fifo_size      = 0x0,
 173                 .ptr1_reg       = DMA7_PTR1,
 174                 .ptr2_reg       = DMA7_PTR2,
 175                 .cnt1_reg       = DMA7_CNT1,
 176                 .cnt2_reg       = DMA7_CNT2,
 177         },
 178         [SRAM_CH09] = {
 179                 .name           = "ch9",
 180                 .cmds_start     = 0x0,
 181                 .ctrl_start     = 0x0,
 182                 .cdt            = 0x0,
 183                 .fifo_start     = 0x0,
 184                 .fifo_size      = 0x0,
 185                 .ptr1_reg       = DMA8_PTR1,
 186                 .ptr2_reg       = DMA8_PTR2,
 187                 .cnt1_reg       = DMA8_CNT1,
 188                 .cnt2_reg       = DMA8_CNT2,
 189         },
 190 };
 191
 192 static struct sram_channel cx23887_sram_channels[] = {
 193         [SRAM_CH01] = {
 194                 .name           = "VID A",
 195                 .cmds_start     = 0x10000,
 196                 .ctrl_start     = 0x105b0,
 197                 .cdt            = 0x107b0,
 198                 .fifo_start     = 0x40,
 199                 .fifo_size      = 0x2800,
 200                 .ptr1_reg       = DMA1_PTR1,
 201                 .ptr2_reg       = DMA1_PTR2,
 202                 .cnt1_reg       = DMA1_CNT1,
 203                 .cnt2_reg       = DMA1_CNT2,
 204         },
 205         [SRAM_CH02] = {
 206                 .name           = "ch2",
 207                 .cmds_start     = 0x0,
 208                 .ctrl_start     = 0x0,
 209                 .cdt            = 0x0,
 210                 .fifo_start     = 0x0,
 211                 .fifo_size      = 0x0,
 212                 .ptr1_reg       = DMA2_PTR1,
 213                 .ptr2_reg       = DMA2_PTR2,
 214                 .cnt1_reg       = DMA2_CNT1,
 215                 .cnt2_reg       = DMA2_CNT2,
 216         },
 217         [SRAM_CH03] = {
 218                 .name           = "TS1 B",
 219                 .cmds_start     = 0x100A0,
 220                 .ctrl_start     = 0x10630,
 221                 .cdt            = 0x10870,
 222                 .fifo_start     = 0x5000,
 223                 .fifo_size      = 0x1000,
 224                 .ptr1_reg       = DMA3_PTR1,
 225                 .ptr2_reg       = DMA3_PTR2,
 226                 .cnt1_reg       = DMA3_CNT1,
 227                 .cnt2_reg       = DMA3_CNT2,
 228         },
 229         [SRAM_CH04] = {
 230                 .name           = "ch4",
 231                 .cmds_start     = 0x0,
 232                 .ctrl_start     = 0x0,
 233                 .cdt            = 0x0,
 234                 .fifo_start     = 0x0,
 235                 .fifo_size      = 0x0,
 236                 .ptr1_reg       = DMA4_PTR1,
 237                 .ptr2_reg       = DMA4_PTR2,
 238                 .cnt1_reg       = DMA4_CNT1,
 239                 .cnt2_reg       = DMA4_CNT2,
 240         },
 241         [SRAM_CH05] = {
 242                 .name           = "ch5",
 243                 .cmds_start     = 0x0,
 244                 .ctrl_start     = 0x0,
 245                 .cdt            = 0x0,
 246                 .fifo_start     = 0x0,
 247                 .fifo_size      = 0x0,
 248                 .ptr1_reg       = DMA5_PTR1,
 249                 .ptr2_reg       = DMA5_PTR2,
 250                 .cnt1_reg       = DMA5_CNT1,
 251                 .cnt2_reg       = DMA5_CNT2,
 252         },
 253         [SRAM_CH06] = {
 254                 .name           = "TS2 C",
 255                 .cmds_start     = 0x10140,
 256                 .ctrl_start     = 0x10670,
 257                 .cdt            = 0x108d0,
 258                 .fifo_start     = 0x6000,
 259                 .fifo_size      = 0x1000,
 260                 .ptr1_reg       = DMA5_PTR1,
 261                 .ptr2_reg       = DMA5_PTR2,
 262                 .cnt1_reg       = DMA5_CNT1,
 263                 .cnt2_reg       = DMA5_CNT2,
 264         },
 265         [SRAM_CH07] = {
 266                 .name           = "ch7",
 267                 .cmds_start     = 0x0,
 268                 .ctrl_start     = 0x0,
 269                 .cdt            = 0x0,
 270                 .fifo_start     = 0x0,
 271                 .fifo_size      = 0x0,
 272                 .ptr1_reg       = DMA6_PTR1,
 273                 .ptr2_reg       = DMA6_PTR2,
 274                 .cnt1_reg       = DMA6_CNT1,
 275                 .cnt2_reg       = DMA6_CNT2,
 276         },
 277         [SRAM_CH08] = {
 278                 .name           = "ch8",
 279                 .cmds_start     = 0x0,
 280                 .ctrl_start     = 0x0,
 281                 .cdt            = 0x0,
 282                 .fifo_start     = 0x0,
 283                 .fifo_size      = 0x0,
 284                 .ptr1_reg       = DMA7_PTR1,
 285                 .ptr2_reg       = DMA7_PTR2,
 286                 .cnt1_reg       = DMA7_CNT1,
 287                 .cnt2_reg       = DMA7_CNT2,
 288         },
 289         [SRAM_CH09] = {
 290                 .name           = "ch9",
 291                 .cmds_start     = 0x0,
 292                 .ctrl_start     = 0x0,
 293                 .cdt            = 0x0,
 294                 .fifo_start     = 0x0,
 295                 .fifo_size      = 0x0,
 296                 .ptr1_reg       = DMA8_PTR1,
 297                 .ptr2_reg       = DMA8_PTR2,
 298                 .cnt1_reg       = DMA8_CNT1,
 299                 .cnt2_reg       = DMA8_CNT2,
 300         },
 301 };
 302
 303 void cx23885_irq_add(struct cx23885_dev *dev, u32 mask)
 304 {
 305         unsigned long flags;
 306         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 307
 308         dev->pci_irqmask |= mask;
 309
 310         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 311 }
 312
 313 void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask)
 314 {
 315         unsigned long flags;
 316         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 317
 318         dev->pci_irqmask |= mask;
 319         cx_set(PCI_INT_MSK, mask);
 320
 321         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 322 }
 323
 324 void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask)
 325 {
 326         u32 v;
 327         unsigned long flags;
 328         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 329
 330         v = mask & dev->pci_irqmask;
 331         if (v)
 332                 cx_set(PCI_INT_MSK, v);
 333
 334         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 335 }
 336
 337 static inline void cx23885_irq_enable_all(struct cx23885_dev *dev)
 338 {
 339         cx23885_irq_enable(dev, 0xffffffff);
 340 }
 341
 342 void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask)
 343 {
 344         unsigned long flags;
 345         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 346
 347         cx_clear(PCI_INT_MSK, mask);
 348
 349         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 350 }
 351
 352 static inline void cx23885_irq_disable_all(struct cx23885_dev *dev)
 353 {
 354         cx23885_irq_disable(dev, 0xffffffff);
 355 }
 356
 357 void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask)
 358 {
 359         unsigned long flags;
 360         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 361
 362         dev->pci_irqmask &= ~mask;
 363         cx_clear(PCI_INT_MSK, mask);
 364
 365         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 366 }
 367
 368 static u32 cx23885_irq_get_mask(struct cx23885_dev *dev)
 369 {
 370         u32 v;
 371         unsigned long flags;
 372         spin_lock_irqsave(&dev->pci_irqmask_lock, flags);
 373
 374         v = cx_read(PCI_INT_MSK);
 375
 376         spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags);
 377         return v;
 378 }
 379
 380 static int cx23885_risc_decode(u32 risc)
 381 {
 382         static char *instr[16] = {
 383                 [RISC_SYNC    >> 28] = "sync",
 384                 [RISC_WRITE   >> 28] = "write",
 385                 [RISC_WRITEC  >> 28] = "writec",
 386                 [RISC_READ    >> 28] = "read",
 387                 [RISC_READC   >> 28] = "readc",
 388                 [RISC_JUMP    >> 28] = "jump",
 389                 [RISC_SKIP    >> 28] = "skip",
 390                 [RISC_WRITERM >> 28] = "writerm",
 391                 [RISC_WRITECM >> 28] = "writecm",
 392                 [RISC_WRITECR >> 28] = "writecr",
 393         };
 394         static int incr[16] = {
 395                 [RISC_WRITE   >> 28] = 3,
 396                 [RISC_JUMP    >> 28] = 3,
 397                 [RISC_SKIP    >> 28] = 1,
 398                 [RISC_SYNC    >> 28] = 1,
 399                 [RISC_WRITERM >> 28] = 3,
 400                 [RISC_WRITECM >> 28] = 3,
 401                 [RISC_WRITECR >> 28] = 4,
 402         };
 403         static char *bits[] = {
 404                 "12",   "13",   "14",   "resync",
 405                 "cnt0", "cnt1", "18",   "19",
 406                 "20",   "21",   "22",   "23",
 407                 "irq1", "irq2", "eol",  "sol",
 408         };
 409         int i;
 410
 411         printk("0x%08x [ %s", risc,
 412                instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
 413         for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
 414                 if (risc & (1 << (i + 12)))
 415                         printk(" %s", bits[i]);
 416         printk(" count=%d ]\n", risc & 0xfff);
 417         return incr[risc >> 28] ? incr[risc >> 28] : 1;
 418 }
 419
 420 void cx23885_wakeup(struct cx23885_tsport *port,
 421                            struct cx23885_dmaqueue *q, u32 count)
 422 {
 423         struct cx23885_dev *dev = port->dev;
 424         struct cx23885_buffer *buf;
 425         int bc;
 426
 427         for (bc = 0;; bc++) {
 428                 if (list_empty(&q->active))
 429                         break;
 430                 buf = list_entry(q->active.next,
 431                                  struct cx23885_buffer, vb.queue);
 432
 433                 /* count comes from the hw and is is 16bit wide --
 434                  * this trick handles wrap-arounds correctly for
 435                  * up to 32767 buffers in flight... */
 436                 if ((s16) (count - buf->count) < 0)
 437                         break;
 438
 439                 do_gettimeofday(&buf->vb.ts);
 440                 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
 441                         count, buf->count);
 442                 buf->vb.state = VIDEOBUF_DONE;
 443                 list_del(&buf->vb.queue);
 444                 wake_up(&buf->vb.done);
 445         }
 446         if (list_empty(&q->active))
 447                 del_timer(&q->timeout);
 448         else
 449                 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
 450         if (bc != 1)
 451                 printk(KERN_WARNING "%s: %d buffers handled (should be 1)\n",
 452                        __func__, bc);
 453 }
 454
 455 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
 456                                       struct sram_channel *ch,
 457                                       unsigned int bpl, u32 risc)
 458 {
 459         unsigned int i, lines;
 460         u32 cdt;
 461
 462         if (ch->cmds_start == 0) {
 463                 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
 464                         ch->name);
 465                 cx_write(ch->ptr1_reg, 0);
 466                 cx_write(ch->ptr2_reg, 0);
 467                 cx_write(ch->cnt2_reg, 0);
 468                 cx_write(ch->cnt1_reg, 0);
 469                 return 0;
 470         } else {
 471                 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
 472                         ch->name);
 473         }
 474
 475         bpl   = (bpl + 7) & ~7; /* alignment */
 476         cdt   = ch->cdt;
 477         lines = ch->fifo_size / bpl;
 478         if (lines > 6)
 479                 lines = 6;
 480         BUG_ON(lines < 2);
 481
 482         cx_write(8 + 0, RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 483         cx_write(8 + 4, 8);
 484         cx_write(8 + 8, 0);
 485
 486         /* write CDT */
 487         for (i = 0; i < lines; i++) {
 488                 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
 489                         ch->fifo_start + bpl*i);
 490                 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
 491                 cx_write(cdt + 16*i +  4, 0);
 492                 cx_write(cdt + 16*i +  8, 0);
 493                 cx_write(cdt + 16*i + 12, 0);
 494         }
 495
 496         /* write CMDS */
 497         if (ch->jumponly)
 498                 cx_write(ch->cmds_start + 0, 8);
 499         else
 500                 cx_write(ch->cmds_start + 0, risc);
 501         cx_write(ch->cmds_start +  4, 0); /* 64 bits 63-32 */
 502         cx_write(ch->cmds_start +  8, cdt);
 503         cx_write(ch->cmds_start + 12, (lines*16) >> 3);
 504         cx_write(ch->cmds_start + 16, ch->ctrl_start);
 505         if (ch->jumponly)
 506                 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2));
 507         else
 508                 cx_write(ch->cmds_start + 20, 64 >> 2);
 509         for (i = 24; i < 80; i += 4)
 510                 cx_write(ch->cmds_start + i, 0);
 511
 512         /* fill registers */
 513         cx_write(ch->ptr1_reg, ch->fifo_start);
 514         cx_write(ch->ptr2_reg, cdt);
 515         cx_write(ch->cnt2_reg, (lines*16) >> 3);
 516         cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
 517
 518         dprintk(2, "[bridge %d] sram setup %s: bpl=%d lines=%d\n",
 519                 dev->bridge,
 520                 ch->name,
 521                 bpl,
 522                 lines);
 523
 524         return 0;
 525 }
 526
 527 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
 528                                       struct sram_channel *ch)
 529 {
 530         static char *name[] = {
 531                 "init risc lo",
 532                 "init risc hi",
 533                 "cdt base",
 534                 "cdt size",
 535                 "iq base",
 536                 "iq size",
 537                 "risc pc lo",
 538                 "risc pc hi",
 539                 "iq wr ptr",
 540                 "iq rd ptr",
 541                 "cdt current",
 542                 "pci target lo",
 543                 "pci target hi",
 544                 "line / byte",
 545         };
 546         u32 risc;
 547         unsigned int i, j, n;
 548
 549         printk(KERN_WARNING "%s: %s - dma channel status dump\n",
 550                dev->name, ch->name);
 551         for (i = 0; i < ARRAY_SIZE(name); i++)
 552                 printk(KERN_WARNING "%s:   cmds: %-15s: 0x%08x\n",
 553                        dev->name, name[i],
 554                        cx_read(ch->cmds_start + 4*i));
 555
 556         for (i = 0; i < 4; i++) {
 557                 risc = cx_read(ch->cmds_start + 4 * (i + 14));
 558                 printk(KERN_WARNING "%s:   risc%d: ", dev->name, i);
 559                 cx23885_risc_decode(risc);
 560         }
 561         for (i = 0; i < (64 >> 2); i += n) {
 562                 risc = cx_read(ch->ctrl_start + 4 * i);
 563                 /* No consideration for bits 63-32 */
 564
 565                 printk(KERN_WARNING "%s:   (0x%08x) iq %x: ", dev->name,
 566                        ch->ctrl_start + 4 * i, i);
 567                 n = cx23885_risc_decode(risc);
 568                 for (j = 1; j < n; j++) {
 569                         risc = cx_read(ch->ctrl_start + 4 * (i + j));
 570                         printk(KERN_WARNING "%s:   iq %x: 0x%08x [ arg #%d ]\n",
 571                                dev->name, i+j, risc, j);
 572                 }
 573         }
 574
 575         printk(KERN_WARNING "%s: fifo: 0x%08x -> 0x%x\n",
 576                dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
 577         printk(KERN_WARNING "%s: ctrl: 0x%08x -> 0x%x\n",
 578                dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
 579         printk(KERN_WARNING "%s:   ptr1_reg: 0x%08x\n",
 580                dev->name, cx_read(ch->ptr1_reg));
 581         printk(KERN_WARNING "%s:   ptr2_reg: 0x%08x\n",
 582                dev->name, cx_read(ch->ptr2_reg));
 583         printk(KERN_WARNING "%s:   cnt1_reg: 0x%08x\n",
 584                dev->name, cx_read(ch->cnt1_reg));
 585         printk(KERN_WARNING "%s:   cnt2_reg: 0x%08x\n",
 586                dev->name, cx_read(ch->cnt2_reg));
 587 }
 588
 589 static void cx23885_risc_disasm(struct cx23885_tsport *port,
 590                                 struct btcx_riscmem *risc)
 591 {
 592         struct cx23885_dev *dev = port->dev;
 593         unsigned int i, j, n;
 594
 595         printk(KERN_INFO "%s: risc disasm: %p [dma=0x%08lx]\n",
 596                dev->name, risc->cpu, (unsigned long)risc->dma);
 597         for (i = 0; i < (risc->size >> 2); i += n) {
 598                 printk(KERN_INFO "%s:   %04d: ", dev->name, i);
 599                 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i]));
 600                 for (j = 1; j < n; j++)
 601                         printk(KERN_INFO "%s:   %04d: 0x%08x [ arg #%d ]\n",
 602                                dev->name, i + j, risc->cpu[i + j], j);
 603                 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP))
 604                         break;
 605         }
 606 }
 607
 608 static void cx23885_shutdown(struct cx23885_dev *dev)
 609 {
 610         /* disable RISC controller */
 611         cx_write(DEV_CNTRL2, 0);
 612
 613         /* Disable all IR activity */
 614         cx_write(IR_CNTRL_REG, 0);
 615
 616         /* Disable Video A/B activity */
 617         cx_write(VID_A_DMA_CTL, 0);
 618         cx_write(VID_B_DMA_CTL, 0);
 619         cx_write(VID_C_DMA_CTL, 0);
 620
 621         /* Disable Audio activity */
 622         cx_write(AUD_INT_DMA_CTL, 0);
 623         cx_write(AUD_EXT_DMA_CTL, 0);
 624
 625         /* Disable Serial port */
 626         cx_write(UART_CTL, 0);
 627
 628         /* Disable Interrupts */
 629         cx23885_irq_disable_all(dev);
 630         cx_write(VID_A_INT_MSK, 0);
 631         cx_write(VID_B_INT_MSK, 0);
 632         cx_write(VID_C_INT_MSK, 0);
 633         cx_write(AUDIO_INT_INT_MSK, 0);
 634         cx_write(AUDIO_EXT_INT_MSK, 0);
 635
 636 }
 637
 638 static void cx23885_reset(struct cx23885_dev *dev)
 639 {
 640         dprintk(1, "%s()\n", __func__);
 641
 642         cx23885_shutdown(dev);
 643
 644         cx_write(PCI_INT_STAT, 0xffffffff);
 645         cx_write(VID_A_INT_STAT, 0xffffffff);
 646         cx_write(VID_B_INT_STAT, 0xffffffff);
 647         cx_write(VID_C_INT_STAT, 0xffffffff);
 648         cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
 649         cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
 650         cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
 651         cx_write(PAD_CTRL, 0x00500300);
 652
 653         mdelay(100);
 654
 655         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
 656                 720*4, 0);
 657         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
 658         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
 659                 188*4, 0);
 660         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
 661         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
 662         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
 663                 188*4, 0);
 664         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
 665         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
 666         cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
 667
 668         cx23885_gpio_setup(dev);
 669 }
 670
 671
 672 static int cx23885_pci_quirks(struct cx23885_dev *dev)
 673 {
 674         dprintk(1, "%s()\n", __func__);
 675
 676         /* The cx23885 bridge has a weird bug which causes NMI to be asserted
 677          * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
 678          * occur on the cx23887 bridge.
 679          */
 680         if (dev->bridge == CX23885_BRIDGE_885)
 681                 cx_clear(RDR_TLCTL0, 1 << 4);
 682
 683         return 0;
 684 }
 685
 686 static int get_resources(struct cx23885_dev *dev)
 687 {
 688         if (request_mem_region(pci_resource_start(dev->pci, 0),
 689                                pci_resource_len(dev->pci, 0),
 690                                dev->name))
 691                 return 0;
 692
 693         printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
 694                 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0));
 695
 696         return -EBUSY;
 697 }
 698
 699 static void cx23885_timeout(unsigned long data);
 700 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
 701                                 u32 reg, u32 mask, u32 value);
 702
 703 static int cx23885_init_tsport(struct cx23885_dev *dev,
 704         struct cx23885_tsport *port, int portno)
 705 {
 706         dprintk(1, "%s(portno=%d)\n", __func__, portno);
 707
 708         /* Transport bus init dma queue  - Common settings */
 709         port->dma_ctl_val        = 0x11; /* Enable RISC controller and Fifo */
 710         port->ts_int_msk_val     = 0x1111; /* TS port bits for RISC */
 711         port->vld_misc_val       = 0x0;
 712         port->hw_sop_ctrl_val    = (0x47 << 16 | 188 << 4);
 713
 714         spin_lock_init(&port->slock);
 715         port->dev = dev;
 716         port->nr = portno;
 717
 718         INIT_LIST_HEAD(&port->mpegq.active);
 719         INIT_LIST_HEAD(&port->mpegq.queued);
 720         port->mpegq.timeout.function = cx23885_timeout;
 721         port->mpegq.timeout.data = (unsigned long)port;
 722         init_timer(&port->mpegq.timeout);
 723
 724         mutex_init(&port->frontends.lock);
 725         INIT_LIST_HEAD(&port->frontends.felist);
 726         port->frontends.active_fe_id = 0;
 727
 728         /* This should be hardcoded allow a single frontend
 729          * attachment to this tsport, keeping the -dvb.c
 730          * code clean and safe.
 731          */
 732         if (!port->num_frontends)
 733                 port->num_frontends = 1;
 734
 735         switch (portno) {
 736         case 1:
 737                 port->reg_gpcnt          = VID_B_GPCNT;
 738                 port->reg_gpcnt_ctl      = VID_B_GPCNT_CTL;
 739                 port->reg_dma_ctl        = VID_B_DMA_CTL;
 740                 port->reg_lngth          = VID_B_LNGTH;
 741                 port->reg_hw_sop_ctrl    = VID_B_HW_SOP_CTL;
 742                 port->reg_gen_ctrl       = VID_B_GEN_CTL;
 743                 port->reg_bd_pkt_status  = VID_B_BD_PKT_STATUS;
 744                 port->reg_sop_status     = VID_B_SOP_STATUS;
 745                 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
 746                 port->reg_vld_misc       = VID_B_VLD_MISC;
 747                 port->reg_ts_clk_en      = VID_B_TS_CLK_EN;
 748                 port->reg_src_sel        = VID_B_SRC_SEL;
 749                 port->reg_ts_int_msk     = VID_B_INT_MSK;
 750                 port->reg_ts_int_stat    = VID_B_INT_STAT;
 751                 port->sram_chno          = SRAM_CH03; /* VID_B */
 752                 port->pci_irqmask        = 0x02; /* VID_B bit1 */
 753                 break;
 754         case 2:
 755                 port->reg_gpcnt          = VID_C_GPCNT;
 756                 port->reg_gpcnt_ctl      = VID_C_GPCNT_CTL;
 757                 port->reg_dma_ctl        = VID_C_DMA_CTL;
 758                 port->reg_lngth          = VID_C_LNGTH;
 759                 port->reg_hw_sop_ctrl    = VID_C_HW_SOP_CTL;
 760                 port->reg_gen_ctrl       = VID_C_GEN_CTL;
 761                 port->reg_bd_pkt_status  = VID_C_BD_PKT_STATUS;
 762                 port->reg_sop_status     = VID_C_SOP_STATUS;
 763                 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
 764                 port->reg_vld_misc       = VID_C_VLD_MISC;
 765                 port->reg_ts_clk_en      = VID_C_TS_CLK_EN;
 766                 port->reg_src_sel        = 0;
 767                 port->reg_ts_int_msk     = VID_C_INT_MSK;
 768                 port->reg_ts_int_stat    = VID_C_INT_STAT;
 769                 port->sram_chno          = SRAM_CH06; /* VID_C */
 770                 port->pci_irqmask        = 0x04; /* VID_C bit2 */
 771                 break;
 772         default:
 773                 BUG();
 774         }
 775
 776         cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
 777                      port->reg_dma_ctl, port->dma_ctl_val, 0x00);
 778
 779         return 0;
 780 }
 781
 782 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
 783 {
 784         switch (cx_read(RDR_CFG2) & 0xff) {
 785         case 0x00:
 786                 /* cx23885 */
 787                 dev->hwrevision = 0xa0;
 788                 break;
 789         case 0x01:
 790                 /* CX23885-12Z */
 791                 dev->hwrevision = 0xa1;
 792                 break;
 793         case 0x02:
 794                 /* CX23885-13Z/14Z */
 795                 dev->hwrevision = 0xb0;
 796                 break;
 797         case 0x03:
 798                 if (dev->pci->device == 0x8880) {
 799                         /* CX23888-21Z/22Z */
 800                         dev->hwrevision = 0xc0;
 801                 } else {
 802                         /* CX23885-14Z */
 803                         dev->hwrevision = 0xa4;
 804                 }
 805                 break;
 806         case 0x04:
 807                 if (dev->pci->device == 0x8880) {
 808                         /* CX23888-31Z */
 809                         dev->hwrevision = 0xd0;
 810                 } else {
 811                         /* CX23885-15Z, CX23888-31Z */
 812                         dev->hwrevision = 0xa5;
 813                 }
 814                 break;
 815         case 0x0e:
 816                 /* CX23887-15Z */
 817                 dev->hwrevision = 0xc0;
 818         case 0x0f:
 819                 /* CX23887-14Z */
 820                 dev->hwrevision = 0xb1;
 821                 break;
 822         default:
 823                 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
 824                         __func__, dev->hwrevision);
 825         }
 826         if (dev->hwrevision)
 827                 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
 828                         __func__, dev->hwrevision);
 829         else
 830                 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
 831                         __func__, dev->hwrevision);
 832 }
 833
 834 /* Find the first v4l2_subdev member of the group id in hw */
 835 struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw)
 836 {
 837         struct v4l2_subdev *result = NULL;
 838         struct v4l2_subdev *sd;
 839
 840         spin_lock(&dev->v4l2_dev.lock);
 841         v4l2_device_for_each_subdev(sd, &dev->v4l2_dev) {
 842                 if (sd->grp_id == hw) {
 843                         result = sd;
 844                         break;
 845                 }
 846         }
 847         spin_unlock(&dev->v4l2_dev.lock);
 848         return result;
 849 }
 850
 851 static int cx23885_dev_setup(struct cx23885_dev *dev)
 852 {
 853         int i;
 854
 855         spin_lock_init(&dev->pci_irqmask_lock);
 856
 857         mutex_init(&dev->lock);
 858         mutex_init(&dev->gpio_lock);
 859
 860         atomic_inc(&dev->refcount);
 861
 862         dev->nr = cx23885_devcount++;
 863         sprintf(dev->name, "cx23885[%d]", dev->nr);
 864
 865         /* Configure the internal memory */
 866         if (dev->pci->device == 0x8880) {
 867                 /* Could be 887 or 888, assume a default */
 868                 dev->bridge = CX23885_BRIDGE_887;
 869                 /* Apply a sensible clock frequency for the PCIe bridge */
 870                 dev->clk_freq = 25000000;
 871                 dev->sram_channels = cx23887_sram_channels;
 872         } else
 873         if (dev->pci->device == 0x8852) {
 874                 dev->bridge = CX23885_BRIDGE_885;
 875                 /* Apply a sensible clock frequency for the PCIe bridge */
 876                 dev->clk_freq = 28000000;
 877                 dev->sram_channels = cx23885_sram_channels;
 878         } else
 879                 BUG();
 880
 881         dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
 882                 __func__, dev->bridge);
 883
 884         /* board config */
 885         dev->board = UNSET;
 886         if (card[dev->nr] < cx23885_bcount)
 887                 dev->board = card[dev->nr];
 888         for (i = 0; UNSET == dev->board  &&  i < cx23885_idcount; i++)
 889                 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
 890                     dev->pci->subsystem_device == cx23885_subids[i].subdevice)
 891                         dev->board = cx23885_subids[i].card;
 892         if (UNSET == dev->board) {
 893                 dev->board = CX23885_BOARD_UNKNOWN;
 894                 cx23885_card_list(dev);
 895         }
 896
 897         /* If the user specific a clk freq override, apply it */
 898         if (cx23885_boards[dev->board].clk_freq > 0)
 899                 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
 900
 901         dev->pci_bus  = dev->pci->bus->number;
 902         dev->pci_slot = PCI_SLOT(dev->pci->devfn);
 903         cx23885_irq_add(dev, 0x001f00);
 904         if (cx23885_boards[dev->board].cimax > 0)
 905                 cx23885_irq_add(dev, 0x01800000); /* for CiMaxes */
 906
 907         /* External Master 1 Bus */
 908         dev->i2c_bus[0].nr = 0;
 909         dev->i2c_bus[0].dev = dev;
 910         dev->i2c_bus[0].reg_stat  = I2C1_STAT;
 911         dev->i2c_bus[0].reg_ctrl  = I2C1_CTRL;
 912         dev->i2c_bus[0].reg_addr  = I2C1_ADDR;
 913         dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
 914         dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
 915         dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
 916
 917         /* External Master 2 Bus */
 918         dev->i2c_bus[1].nr = 1;
 919         dev->i2c_bus[1].dev = dev;
 920         dev->i2c_bus[1].reg_stat  = I2C2_STAT;
 921         dev->i2c_bus[1].reg_ctrl  = I2C2_CTRL;
 922         dev->i2c_bus[1].reg_addr  = I2C2_ADDR;
 923         dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
 924         dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
 925         dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
 926
 927         /* Internal Master 3 Bus */
 928         dev->i2c_bus[2].nr = 2;
 929         dev->i2c_bus[2].dev = dev;
 930         dev->i2c_bus[2].reg_stat  = I2C3_STAT;
 931         dev->i2c_bus[2].reg_ctrl  = I2C3_CTRL;
 932         dev->i2c_bus[2].reg_addr  = I2C3_ADDR;
 933         dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
 934         dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
 935         dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
 936
 937         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
 938                 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
 939                 cx23885_init_tsport(dev, &dev->ts1, 1);
 940
 941         if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
 942                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 943                 cx23885_init_tsport(dev, &dev->ts2, 2);
 944
 945         if (get_resources(dev) < 0) {
 946                 printk(KERN_ERR "CORE %s No more PCIe resources for "
 947                        "subsystem: %04x:%04x\n",
 948                        dev->name, dev->pci->subsystem_vendor,
 949                        dev->pci->subsystem_device);
 950
 951                 cx23885_devcount--;
 952                 return -ENODEV;
 953         }
 954
 955         /* PCIe stuff */
 956         dev->lmmio = ioremap(pci_resource_start(dev->pci, 0),
 957                              pci_resource_len(dev->pci, 0));
 958
 959         dev->bmmio = (u8 __iomem *)dev->lmmio;
 960
 961         printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
 962                dev->name, dev->pci->subsystem_vendor,
 963                dev->pci->subsystem_device, cx23885_boards[dev->board].name,
 964                dev->board, card[dev->nr] == dev->board ?
 965                "insmod option" : "autodetected");
 966
 967         cx23885_pci_quirks(dev);
 968
 969         /* Assume some sensible defaults */
 970         dev->tuner_type = cx23885_boards[dev->board].tuner_type;
 971         dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
 972         dev->radio_type = cx23885_boards[dev->board].radio_type;
 973         dev->radio_addr = cx23885_boards[dev->board].radio_addr;
 974
 975         dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
 976                 __func__, dev->tuner_type, dev->tuner_addr);
 977         dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
 978                 __func__, dev->radio_type, dev->radio_addr);
 979
 980         /* The cx23417 encoder has GPIO's that need to be initialised
 981          * before DVB, so that demodulators and tuners are out of
 982          * reset before DVB uses them.
 983          */
 984         if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) ||
 985                 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
 986                         cx23885_mc417_init(dev);
 987
 988         /* init hardware */
 989         cx23885_reset(dev);
 990
 991         cx23885_i2c_register(&dev->i2c_bus[0]);
 992         cx23885_i2c_register(&dev->i2c_bus[1]);
 993         cx23885_i2c_register(&dev->i2c_bus[2]);
 994         cx23885_card_setup(dev);
 995         call_all(dev, core, s_power, 0);
 996         cx23885_ir_init(dev);
 997
 998         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
 999                 if (cx23885_video_register(dev) < 0) {
1000                         printk(KERN_ERR "%s() Failed to register analog "
1001                                 "video adapters on VID_A\n", __func__);
1002                 }
1003         }
1004
1005         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1006                 if (cx23885_dvb_register(&dev->ts1) < 0) {
1007                         printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
1008                                __func__);
1009                 }
1010         } else
1011         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1012                 if (cx23885_417_register(dev) < 0) {
1013                         printk(KERN_ERR
1014                                 "%s() Failed to register 417 on VID_B\n",
1015                                __func__);
1016                 }
1017         }
1018
1019         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1020                 if (cx23885_dvb_register(&dev->ts2) < 0) {
1021                         printk(KERN_ERR
1022                                 "%s() Failed to register dvb on VID_C\n",
1023                                __func__);
1024                 }
1025         } else
1026         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
1027                 if (cx23885_417_register(dev) < 0) {
1028                         printk(KERN_ERR
1029                                 "%s() Failed to register 417 on VID_C\n",
1030                                __func__);
1031                 }
1032         }
1033
1034         cx23885_dev_checkrevision(dev);
1035
1036         return 0;
1037 }
1038
1039 static void cx23885_dev_unregister(struct cx23885_dev *dev)
1040 {
1041         release_mem_region(pci_resource_start(dev->pci, 0),
1042                            pci_resource_len(dev->pci, 0));
1043
1044         if (!atomic_dec_and_test(&dev->refcount))
1045                 return;
1046
1047         if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
1048                 cx23885_video_unregister(dev);
1049
1050         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1051                 cx23885_dvb_unregister(&dev->ts1);
1052
1053         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1054                 cx23885_417_unregister(dev);
1055
1056         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1057                 cx23885_dvb_unregister(&dev->ts2);
1058
1059         if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1060                 cx23885_417_unregister(dev);
1061
1062         cx23885_i2c_unregister(&dev->i2c_bus[2]);
1063         cx23885_i2c_unregister(&dev->i2c_bus[1]);
1064         cx23885_i2c_unregister(&dev->i2c_bus[0]);
1065
1066         iounmap(dev->lmmio);
1067 }
1068
1069 static __le32 *cx23885_risc_field(__le32 *rp, struct scatterlist *sglist,
1070                                unsigned int offset, u32 sync_line,
1071                                unsigned int bpl, unsigned int padding,
1072                                unsigned int lines)
1073 {
1074         struct scatterlist *sg;
1075         unsigned int line, todo;
1076
1077         /* sync instruction */
1078         if (sync_line != NO_SYNC_LINE)
1079                 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
1080
1081         /* scan lines */
1082         sg = sglist;
1083         for (line = 0; line < lines; line++) {
1084                 while (offset && offset >= sg_dma_len(sg)) {
1085                         offset -= sg_dma_len(sg);
1086                         sg++;
1087                 }
1088                 if (bpl <= sg_dma_len(sg)-offset) {
1089                         /* fits into current chunk */
1090                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
1091                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1092                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1093                         offset += bpl;
1094                 } else {
1095                         /* scanline needs to be split */
1096                         todo = bpl;
1097                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_SOL|
1098                                             (sg_dma_len(sg)-offset));
1099                         *(rp++) = cpu_to_le32(sg_dma_address(sg)+offset);
1100                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1101                         todo -= (sg_dma_len(sg)-offset);
1102                         offset = 0;
1103                         sg++;
1104                         while (todo > sg_dma_len(sg)) {
1105                                 *(rp++) = cpu_to_le32(RISC_WRITE|
1106                                                     sg_dma_len(sg));
1107                                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
1108                                 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1109                                 todo -= sg_dma_len(sg);
1110                                 sg++;
1111                         }
1112                         *(rp++) = cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
1113                         *(rp++) = cpu_to_le32(sg_dma_address(sg));
1114                         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1115                         offset += todo;
1116                 }
1117                 offset += padding;
1118         }
1119
1120         return rp;
1121 }
1122
1123 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
1124                         struct scatterlist *sglist, unsigned int top_offset,
1125                         unsigned int bottom_offset, unsigned int bpl,
1126                         unsigned int padding, unsigned int lines)
1127 {
1128         u32 instructions, fields;
1129         __le32 *rp;
1130         int rc;
1131
1132         fields = 0;
1133         if (UNSET != top_offset)
1134                 fields++;
1135         if (UNSET != bottom_offset)
1136                 fields++;
1137
1138         /* estimate risc mem: worst case is one write per page border +
1139            one write per scan line + syncs + jump (all 2 dwords).  Padding
1140            can cause next bpl to start close to a page border.  First DMA
1141            region may be smaller than PAGE_SIZE */
1142         /* write and jump need and extra dword */
1143         instructions  = fields * (1 + ((bpl + padding) * lines)
1144                 / PAGE_SIZE + lines);
1145         instructions += 2;
1146         rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1147         if (rc < 0)
1148                 return rc;
1149
1150         /* write risc instructions */
1151         rp = risc->cpu;
1152         if (UNSET != top_offset)
1153                 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1154                                         bpl, padding, lines);
1155         if (UNSET != bottom_offset)
1156                 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1157                                         bpl, padding, lines);
1158
1159         /* save pointer to jmp instruction address */
1160         risc->jmp = rp;
1161         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1162         return 0;
1163 }
1164
1165 static int cx23885_risc_databuffer(struct pci_dev *pci,
1166                                    struct btcx_riscmem *risc,
1167                                    struct scatterlist *sglist,
1168                                    unsigned int bpl,
1169                                    unsigned int lines)
1170 {
1171         u32 instructions;
1172         __le32 *rp;
1173         int rc;
1174
1175         /* estimate risc mem: worst case is one write per page border +
1176            one write per scan line + syncs + jump (all 2 dwords).  Here
1177            there is no padding and no sync.  First DMA region may be smaller
1178            than PAGE_SIZE */
1179         /* Jump and write need an extra dword */
1180         instructions  = 1 + (bpl * lines) / PAGE_SIZE + lines;
1181         instructions += 1;
1182
1183         rc = btcx_riscmem_alloc(pci, risc, instructions*12);
1184         if (rc < 0)
1185                 return rc;
1186
1187         /* write risc instructions */
1188         rp = risc->cpu;
1189         rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1190
1191         /* save pointer to jmp instruction address */
1192         risc->jmp = rp;
1193         BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size);
1194         return 0;
1195 }
1196
1197 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1198                                 u32 reg, u32 mask, u32 value)
1199 {
1200         __le32 *rp;
1201         int rc;
1202
1203         rc = btcx_riscmem_alloc(pci, risc, 4*16);
1204         if (rc < 0)
1205                 return rc;
1206
1207         /* write risc instructions */
1208         rp = risc->cpu;
1209         *(rp++) = cpu_to_le32(RISC_WRITECR  | RISC_IRQ2);
1210         *(rp++) = cpu_to_le32(reg);
1211         *(rp++) = cpu_to_le32(value);
1212         *(rp++) = cpu_to_le32(mask);
1213         *(rp++) = cpu_to_le32(RISC_JUMP);
1214         *(rp++) = cpu_to_le32(risc->dma);
1215         *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1216         return 0;
1217 }
1218
1219 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1220 {
1221         struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1222
1223         BUG_ON(in_interrupt());
1224         videobuf_waiton(&buf->vb, 0, 0);
1225         videobuf_dma_unmap(q->dev, dma);
1226         videobuf_dma_free(dma);
1227         btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
1228         buf->vb.state = VIDEOBUF_NEEDS_INIT;
1229 }
1230
1231 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1232 {
1233         struct cx23885_dev *dev = port->dev;
1234
1235         dprintk(1, "%s() Register Dump\n", __func__);
1236         dprintk(1, "%s() DEV_CNTRL2               0x%08X\n", __func__,
1237                 cx_read(DEV_CNTRL2));
1238         dprintk(1, "%s() PCI_INT_MSK              0x%08X\n", __func__,
1239                 cx23885_irq_get_mask(dev));
1240         dprintk(1, "%s() AUD_INT_INT_MSK          0x%08X\n", __func__,
1241                 cx_read(AUDIO_INT_INT_MSK));
1242         dprintk(1, "%s() AUD_INT_DMA_CTL          0x%08X\n", __func__,
1243                 cx_read(AUD_INT_DMA_CTL));
1244         dprintk(1, "%s() AUD_EXT_INT_MSK          0x%08X\n", __func__,
1245                 cx_read(AUDIO_EXT_INT_MSK));
1246         dprintk(1, "%s() AUD_EXT_DMA_CTL          0x%08X\n", __func__,
1247                 cx_read(AUD_EXT_DMA_CTL));
1248         dprintk(1, "%s() PAD_CTRL                 0x%08X\n", __func__,
1249                 cx_read(PAD_CTRL));
1250         dprintk(1, "%s() ALT_PIN_OUT_SEL          0x%08X\n", __func__,
1251                 cx_read(ALT_PIN_OUT_SEL));
1252         dprintk(1, "%s() GPIO2                    0x%08X\n", __func__,
1253                 cx_read(GPIO2));
1254         dprintk(1, "%s() gpcnt(0x%08X)          0x%08X\n", __func__,
1255                 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1256         dprintk(1, "%s() gpcnt_ctl(0x%08X)      0x%08x\n", __func__,
1257                 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1258         dprintk(1, "%s() dma_ctl(0x%08X)        0x%08x\n", __func__,
1259                 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1260         if (port->reg_src_sel)
1261                 dprintk(1, "%s() src_sel(0x%08X)        0x%08x\n", __func__,
1262                         port->reg_src_sel, cx_read(port->reg_src_sel));
1263         dprintk(1, "%s() lngth(0x%08X)          0x%08x\n", __func__,
1264                 port->reg_lngth, cx_read(port->reg_lngth));
1265         dprintk(1, "%s() hw_sop_ctrl(0x%08X)    0x%08x\n", __func__,
1266                 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1267         dprintk(1, "%s() gen_ctrl(0x%08X)       0x%08x\n", __func__,
1268                 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1269         dprintk(1, "%s() bd_pkt_status(0x%08X)  0x%08x\n", __func__,
1270                 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1271         dprintk(1, "%s() sop_status(0x%08X)     0x%08x\n", __func__,
1272                 port->reg_sop_status, cx_read(port->reg_sop_status));
1273         dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1274                 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1275         dprintk(1, "%s() vld_misc(0x%08X)       0x%08x\n", __func__,
1276                 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1277         dprintk(1, "%s() ts_clk_en(0x%08X)      0x%08x\n", __func__,
1278                 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1279         dprintk(1, "%s() ts_int_msk(0x%08X)     0x%08x\n", __func__,
1280                 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1281 }
1282
1283 static int cx23885_start_dma(struct cx23885_tsport *port,
1284                              struct cx23885_dmaqueue *q,
1285                              struct cx23885_buffer   *buf)
1286 {
1287         struct cx23885_dev *dev = port->dev;
1288         u32 reg;
1289
1290         dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1291                 buf->vb.width, buf->vb.height, buf->vb.field);
1292
1293         /* Stop the fifo and risc engine for this port */
1294         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1295
1296         /* setup fifo + format */
1297         cx23885_sram_channel_setup(dev,
1298                                    &dev->sram_channels[port->sram_chno],
1299                                    port->ts_packet_size, buf->risc.dma);
1300         if (debug > 5) {
1301                 cx23885_sram_channel_dump(dev,
1302                         &dev->sram_channels[port->sram_chno]);
1303                 cx23885_risc_disasm(port, &buf->risc);
1304         }
1305
1306         /* write TS length to chip */
1307         cx_write(port->reg_lngth, buf->vb.width);
1308
1309         if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1310                 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) {
1311                 printk("%s() Unsupported .portb/c (0x%08x)/(0x%08x)\n",
1312                         __func__,
1313                         cx23885_boards[dev->board].portb,
1314                         cx23885_boards[dev->board].portc);
1315                 return -EINVAL;
1316         }
1317
1318         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1319                 cx23885_av_clk(dev, 0);
1320
1321         udelay(100);
1322
1323         /* If the port supports SRC SELECT, configure it */
1324         if (port->reg_src_sel)
1325                 cx_write(port->reg_src_sel, port->src_sel_val);
1326
1327         cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1328         cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1329         cx_write(port->reg_vld_misc, port->vld_misc_val);
1330         cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1331         udelay(100);
1332
1333         /* NOTE: this is 2 (reserved) for portb, does it matter? */
1334         /* reset counter to zero */
1335         cx_write(port->reg_gpcnt_ctl, 3);
1336         q->count = 1;
1337
1338         /* Set VIDB pins to input */
1339         if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
1340                 reg = cx_read(PAD_CTRL);
1341                 reg &= ~0x3; /* Clear TS1_OE & TS1_SOP_OE */
1342                 cx_write(PAD_CTRL, reg);
1343         }
1344
1345         /* Set VIDC pins to input */
1346         if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
1347                 reg = cx_read(PAD_CTRL);
1348                 reg &= ~0x4; /* Clear TS2_SOP_OE */
1349                 cx_write(PAD_CTRL, reg);
1350         }
1351
1352         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1353
1354                 reg = cx_read(PAD_CTRL);
1355                 reg = reg & ~0x1;    /* Clear TS1_OE */
1356
1357                 /* FIXME, bit 2 writing here is questionable */
1358                 /* set TS1_SOP_OE and TS1_OE_HI */
1359                 reg = reg | 0xa;
1360                 cx_write(PAD_CTRL, reg);
1361
1362                 /* FIXME and these two registers should be documented. */
1363                 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1364                 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1365         }
1366
1367         switch (dev->bridge) {
1368         case CX23885_BRIDGE_885:
1369         case CX23885_BRIDGE_887:
1370         case CX23885_BRIDGE_888:
1371                 /* enable irqs */
1372                 dprintk(1, "%s() enabling TS int's and DMA\n", __func__);
1373                 cx_set(port->reg_ts_int_msk,  port->ts_int_msk_val);
1374                 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1375                 cx23885_irq_add(dev, port->pci_irqmask);
1376                 cx23885_irq_enable_all(dev);
1377                 break;
1378         default:
1379                 BUG();
1380         }
1381
1382         cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1383
1384         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1385                 cx23885_av_clk(dev, 1);
1386
1387         if (debug > 4)
1388                 cx23885_tsport_reg_dump(port);
1389
1390         return 0;
1391 }
1392
1393 static int cx23885_stop_dma(struct cx23885_tsport *port)
1394 {
1395         struct cx23885_dev *dev = port->dev;
1396         u32 reg;
1397
1398         dprintk(1, "%s()\n", __func__);
1399
1400         /* Stop interrupts and DMA */
1401         cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1402         cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1403
1404         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
1405
1406                 reg = cx_read(PAD_CTRL);
1407
1408                 /* Set TS1_OE */
1409                 reg = reg | 0x1;
1410
1411                 /* clear TS1_SOP_OE and TS1_OE_HI */
1412                 reg = reg & ~0xa;
1413                 cx_write(PAD_CTRL, reg);
1414                 cx_write(port->reg_src_sel, 0);
1415                 cx_write(port->reg_gen_ctrl, 8);
1416
1417         }
1418
1419         if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1420                 cx23885_av_clk(dev, 0);
1421
1422         return 0;
1423 }
1424
1425 int cx23885_restart_queue(struct cx23885_tsport *port,
1426                                 struct cx23885_dmaqueue *q)
1427 {
1428         struct cx23885_dev *dev = port->dev;
1429         struct cx23885_buffer *buf;
1430
1431         dprintk(5, "%s()\n", __func__);
1432         if (list_empty(&q->active)) {
1433                 struct cx23885_buffer *prev;
1434                 prev = NULL;
1435
1436                 dprintk(5, "%s() queue is empty\n", __func__);
1437
1438                 for (;;) {
1439                         if (list_empty(&q->queued))
1440                                 return 0;
1441                         buf = list_entry(q->queued.next, struct cx23885_buffer,
1442                                          vb.queue);
1443                         if (NULL == prev) {
1444                                 list_del(&buf->vb.queue);
1445                                 list_add_tail(&buf->vb.queue, &q->active);
1446                                 cx23885_start_dma(port, q, buf);
1447                                 buf->vb.state = VIDEOBUF_ACTIVE;
1448                                 buf->count    = q->count++;
1449                                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1450                                 dprintk(5, "[%p/%d] restart_queue - f/active\n",
1451                                         buf, buf->vb.i);
1452
1453                         } else if (prev->vb.width  == buf->vb.width  &&
1454                                    prev->vb.height == buf->vb.height &&
1455                                    prev->fmt       == buf->fmt) {
1456                                 list_del(&buf->vb.queue);
1457                                 list_add_tail(&buf->vb.queue, &q->active);
1458                                 buf->vb.state = VIDEOBUF_ACTIVE;
1459                                 buf->count    = q->count++;
1460                                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1461                                 /* 64 bit bits 63-32 */
1462                                 prev->risc.jmp[2] = cpu_to_le32(0);
1463                                 dprintk(5, "[%p/%d] restart_queue - m/active\n",
1464                                         buf, buf->vb.i);
1465                         } else {
1466                                 return 0;
1467                         }
1468                         prev = buf;
1469                 }
1470                 return 0;
1471         }
1472
1473         buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1474         dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1475                 buf, buf->vb.i);
1476         cx23885_start_dma(port, q, buf);
1477         list_for_each_entry(buf, &q->active, vb.queue)
1478                 buf->count = q->count++;
1479         mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1480         return 0;
1481 }
1482
1483 /* ------------------------------------------------------------------ */
1484
1485 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1486                         struct cx23885_buffer *buf, enum v4l2_field field)
1487 {
1488         struct cx23885_dev *dev = port->dev;
1489         int size = port->ts_packet_size * port->ts_packet_count;
1490         int rc;
1491
1492         dprintk(1, "%s: %p\n", __func__, buf);
1493         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
1494                 return -EINVAL;
1495
1496         if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1497                 buf->vb.width  = port->ts_packet_size;
1498                 buf->vb.height = port->ts_packet_count;
1499                 buf->vb.size   = size;
1500                 buf->vb.field  = field /*V4L2_FIELD_TOP*/;
1501
1502                 rc = videobuf_iolock(q, &buf->vb, NULL);
1503                 if (0 != rc)
1504                         goto fail;
1505                 cx23885_risc_databuffer(dev->pci, &buf->risc,
1506                                         videobuf_to_dma(&buf->vb)->sglist,
1507                                         buf->vb.width, buf->vb.height);
1508         }
1509         buf->vb.state = VIDEOBUF_PREPARED;
1510         return 0;
1511
1512  fail:
1513         cx23885_free_buffer(q, buf);
1514         return rc;
1515 }
1516
1517 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1518 {
1519         struct cx23885_buffer    *prev;
1520         struct cx23885_dev *dev = port->dev;
1521         struct cx23885_dmaqueue  *cx88q = &port->mpegq;
1522
1523         /* add jump to stopper */
1524         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1525         buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1526         buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1527
1528         if (list_empty(&cx88q->active)) {
1529                 dprintk(1, "queue is empty - first active\n");
1530                 list_add_tail(&buf->vb.queue, &cx88q->active);
1531                 cx23885_start_dma(port, cx88q, buf);
1532                 buf->vb.state = VIDEOBUF_ACTIVE;
1533                 buf->count    = cx88q->count++;
1534                 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1535                 dprintk(1, "[%p/%d] %s - first active\n",
1536                         buf, buf->vb.i, __func__);
1537         } else {
1538                 dprintk(1, "queue is not empty - append to active\n");
1539                 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1540                                   vb.queue);
1541                 list_add_tail(&buf->vb.queue, &cx88q->active);
1542                 buf->vb.state = VIDEOBUF_ACTIVE;
1543                 buf->count    = cx88q->count++;
1544                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1545                 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1546                 dprintk(1, "[%p/%d] %s - append to active\n",
1547                          buf, buf->vb.i, __func__);
1548         }
1549 }
1550
1551 /* ----------------------------------------------------------- */
1552
1553 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1554                               int restart)
1555 {
1556         struct cx23885_dev *dev = port->dev;
1557         struct cx23885_dmaqueue *q = &port->mpegq;
1558         struct cx23885_buffer *buf;
1559         unsigned long flags;
1560
1561         spin_lock_irqsave(&port->slock, flags);
1562         while (!list_empty(&q->active)) {
1563                 buf = list_entry(q->active.next, struct cx23885_buffer,
1564                                  vb.queue);
1565                 list_del(&buf->vb.queue);
1566                 buf->vb.state = VIDEOBUF_ERROR;
1567                 wake_up(&buf->vb.done);
1568                 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1569                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1570         }
1571         if (restart) {
1572                 dprintk(1, "restarting queue\n");
1573                 cx23885_restart_queue(port, q);
1574         }
1575         spin_unlock_irqrestore(&port->slock, flags);
1576 }
1577
1578 void cx23885_cancel_buffers(struct cx23885_tsport *port)
1579 {
1580         struct cx23885_dev *dev = port->dev;
1581         struct cx23885_dmaqueue *q = &port->mpegq;
1582
1583         dprintk(1, "%s()\n", __func__);
1584         del_timer_sync(&q->timeout);
1585         cx23885_stop_dma(port);
1586         do_cancel_buffers(port, "cancel", 0);
1587 }
1588
1589 static void cx23885_timeout(unsigned long data)
1590 {
1591         struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1592         struct cx23885_dev *dev = port->dev;
1593
1594         dprintk(1, "%s()\n", __func__);
1595
1596         if (debug > 5)
1597                 cx23885_sram_channel_dump(dev,
1598                         &dev->sram_channels[port->sram_chno]);
1599
1600         cx23885_stop_dma(port);
1601         do_cancel_buffers(port, "timeout", 1);
1602 }
1603
1604 int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1605 {
1606         /* FIXME: port1 assumption here. */
1607         struct cx23885_tsport *port = &dev->ts1;
1608         int count = 0;
1609         int handled = 0;
1610
1611         if (status == 0)
1612                 return handled;
1613
1614         count = cx_read(port->reg_gpcnt);
1615         dprintk(7, "status: 0x%08x  mask: 0x%08x count: 0x%x\n",
1616                 status, cx_read(port->reg_ts_int_msk), count);
1617
1618         if ((status & VID_B_MSK_BAD_PKT)         ||
1619                 (status & VID_B_MSK_OPC_ERR)     ||
1620                 (status & VID_B_MSK_VBI_OPC_ERR) ||
1621                 (status & VID_B_MSK_SYNC)        ||
1622                 (status & VID_B_MSK_VBI_SYNC)    ||
1623                 (status & VID_B_MSK_OF)          ||
1624                 (status & VID_B_MSK_VBI_OF)) {
1625                 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1626                         "= 0x%x\n", dev->name, status);
1627                 if (status & VID_B_MSK_BAD_PKT)
1628                         dprintk(1, "        VID_B_MSK_BAD_PKT\n");
1629                 if (status & VID_B_MSK_OPC_ERR)
1630                         dprintk(1, "        VID_B_MSK_OPC_ERR\n");
1631                 if (status & VID_B_MSK_VBI_OPC_ERR)
1632                         dprintk(1, "        VID_B_MSK_VBI_OPC_ERR\n");
1633                 if (status & VID_B_MSK_SYNC)
1634                         dprintk(1, "        VID_B_MSK_SYNC\n");
1635                 if (status & VID_B_MSK_VBI_SYNC)
1636                         dprintk(1, "        VID_B_MSK_VBI_SYNC\n");
1637                 if (status & VID_B_MSK_OF)
1638                         dprintk(1, "        VID_B_MSK_OF\n");
1639                 if (status & VID_B_MSK_VBI_OF)
1640                         dprintk(1, "        VID_B_MSK_VBI_OF\n");
1641
1642                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1643                 cx23885_sram_channel_dump(dev,
1644                         &dev->sram_channels[port->sram_chno]);
1645                 cx23885_417_check_encoder(dev);
1646         } else if (status & VID_B_MSK_RISCI1) {
1647                 dprintk(7, "        VID_B_MSK_RISCI1\n");
1648                 spin_lock(&port->slock);
1649                 cx23885_wakeup(port, &port->mpegq, count);
1650                 spin_unlock(&port->slock);
1651         } else if (status & VID_B_MSK_RISCI2) {
1652                 dprintk(7, "        VID_B_MSK_RISCI2\n");
1653                 spin_lock(&port->slock);
1654                 cx23885_restart_queue(port, &port->mpegq);
1655                 spin_unlock(&port->slock);
1656         }
1657         if (status) {
1658                 cx_write(port->reg_ts_int_stat, status);
1659                 handled = 1;
1660         }
1661
1662         return handled;
1663 }
1664
1665 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1666 {
1667         struct cx23885_dev *dev = port->dev;
1668         int handled = 0;
1669         u32 count;
1670
1671         if ((status & VID_BC_MSK_OPC_ERR) ||
1672                 (status & VID_BC_MSK_BAD_PKT) ||
1673                 (status & VID_BC_MSK_SYNC) ||
1674                 (status & VID_BC_MSK_OF)) {
1675
1676                 if (status & VID_BC_MSK_OPC_ERR)
1677                         dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n",
1678                                 VID_BC_MSK_OPC_ERR);
1679
1680                 if (status & VID_BC_MSK_BAD_PKT)
1681                         dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n",
1682                                 VID_BC_MSK_BAD_PKT);
1683
1684                 if (status & VID_BC_MSK_SYNC)
1685                         dprintk(7, " (VID_BC_MSK_SYNC    0x%08x)\n",
1686                                 VID_BC_MSK_SYNC);
1687
1688                 if (status & VID_BC_MSK_OF)
1689                         dprintk(7, " (VID_BC_MSK_OF      0x%08x)\n",
1690                                 VID_BC_MSK_OF);
1691
1692                 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1693
1694                 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1695                 cx23885_sram_channel_dump(dev,
1696                         &dev->sram_channels[port->sram_chno]);
1697
1698         } else if (status & VID_BC_MSK_RISCI1) {
1699
1700                 dprintk(7, " (RISCI1            0x%08x)\n", VID_BC_MSK_RISCI1);
1701
1702                 spin_lock(&port->slock);
1703                 count = cx_read(port->reg_gpcnt);
1704                 cx23885_wakeup(port, &port->mpegq, count);
1705                 spin_unlock(&port->slock);
1706
1707         } else if (status & VID_BC_MSK_RISCI2) {
1708
1709                 dprintk(7, " (RISCI2            0x%08x)\n", VID_BC_MSK_RISCI2);
1710
1711                 spin_lock(&port->slock);
1712                 cx23885_restart_queue(port, &port->mpegq);
1713                 spin_unlock(&port->slock);
1714
1715         }
1716         if (status) {
1717                 cx_write(port->reg_ts_int_stat, status);
1718                 handled = 1;
1719         }
1720
1721         return handled;
1722 }
1723
1724 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1725 {
1726         struct cx23885_dev *dev = dev_id;
1727         struct cx23885_tsport *ts1 = &dev->ts1;
1728         struct cx23885_tsport *ts2 = &dev->ts2;
1729         u32 pci_status, pci_mask;
1730         u32 vida_status, vida_mask;
1731         u32 ts1_status, ts1_mask;
1732         u32 ts2_status, ts2_mask;
1733         int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1734         bool subdev_handled;
1735
1736         pci_status = cx_read(PCI_INT_STAT);
1737         pci_mask = cx23885_irq_get_mask(dev);
1738         vida_status = cx_read(VID_A_INT_STAT);
1739         vida_mask = cx_read(VID_A_INT_MSK);
1740         ts1_status = cx_read(VID_B_INT_STAT);
1741         ts1_mask = cx_read(VID_B_INT_MSK);
1742         ts2_status = cx_read(VID_C_INT_STAT);
1743         ts2_mask = cx_read(VID_C_INT_MSK);
1744
1745         if ((pci_status == 0) && (ts2_status == 0) && (ts1_status == 0))
1746                 goto out;
1747
1748         vida_count = cx_read(VID_A_GPCNT);
1749         ts1_count = cx_read(ts1->reg_gpcnt);
1750         ts2_count = cx_read(ts2->reg_gpcnt);
1751         dprintk(7, "pci_status: 0x%08x  pci_mask: 0x%08x\n",
1752                 pci_status, pci_mask);
1753         dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1754                 vida_status, vida_mask, vida_count);
1755         dprintk(7, "ts1_status: 0x%08x  ts1_mask: 0x%08x count: 0x%x\n",
1756                 ts1_status, ts1_mask, ts1_count);
1757         dprintk(7, "ts2_status: 0x%08x  ts2_mask: 0x%08x count: 0x%x\n",
1758                 ts2_status, ts2_mask, ts2_count);
1759
1760         if (pci_status & (PCI_MSK_RISC_RD | PCI_MSK_RISC_WR |
1761                           PCI_MSK_AL_RD   | PCI_MSK_AL_WR   | PCI_MSK_APB_DMA |
1762                           PCI_MSK_VID_C   | PCI_MSK_VID_B   | PCI_MSK_VID_A   |
1763                           PCI_MSK_AUD_INT | PCI_MSK_AUD_EXT |
1764                           PCI_MSK_GPIO0   | PCI_MSK_GPIO1   |
1765                           PCI_MSK_AV_CORE | PCI_MSK_IR)) {
1766
1767                 if (pci_status & PCI_MSK_RISC_RD)
1768                         dprintk(7, " (PCI_MSK_RISC_RD   0x%08x)\n",
1769                                 PCI_MSK_RISC_RD);
1770
1771                 if (pci_status & PCI_MSK_RISC_WR)
1772                         dprintk(7, " (PCI_MSK_RISC_WR   0x%08x)\n",
1773                                 PCI_MSK_RISC_WR);
1774
1775                 if (pci_status & PCI_MSK_AL_RD)
1776                         dprintk(7, " (PCI_MSK_AL_RD     0x%08x)\n",
1777                                 PCI_MSK_AL_RD);
1778
1779                 if (pci_status & PCI_MSK_AL_WR)
1780                         dprintk(7, " (PCI_MSK_AL_WR     0x%08x)\n",
1781                                 PCI_MSK_AL_WR);
1782
1783                 if (pci_status & PCI_MSK_APB_DMA)
1784                         dprintk(7, " (PCI_MSK_APB_DMA   0x%08x)\n",
1785                                 PCI_MSK_APB_DMA);
1786
1787                 if (pci_status & PCI_MSK_VID_C)
1788                         dprintk(7, " (PCI_MSK_VID_C     0x%08x)\n",
1789                                 PCI_MSK_VID_C);
1790
1791                 if (pci_status & PCI_MSK_VID_B)
1792                         dprintk(7, " (PCI_MSK_VID_B     0x%08x)\n",
1793                                 PCI_MSK_VID_B);
1794
1795                 if (pci_status & PCI_MSK_VID_A)
1796                         dprintk(7, " (PCI_MSK_VID_A     0x%08x)\n",
1797                                 PCI_MSK_VID_A);
1798
1799                 if (pci_status & PCI_MSK_AUD_INT)
1800                         dprintk(7, " (PCI_MSK_AUD_INT   0x%08x)\n",
1801                                 PCI_MSK_AUD_INT);
1802
1803                 if (pci_status & PCI_MSK_AUD_EXT)
1804                         dprintk(7, " (PCI_MSK_AUD_EXT   0x%08x)\n",
1805                                 PCI_MSK_AUD_EXT);
1806
1807                 if (pci_status & PCI_MSK_GPIO0)
1808                         dprintk(7, " (PCI_MSK_GPIO0     0x%08x)\n",
1809                                 PCI_MSK_GPIO0);
1810
1811                 if (pci_status & PCI_MSK_GPIO1)
1812                         dprintk(7, " (PCI_MSK_GPIO1     0x%08x)\n",
1813                                 PCI_MSK_GPIO1);
1814
1815                 if (pci_status & PCI_MSK_AV_CORE)
1816                         dprintk(7, " (PCI_MSK_AV_CORE   0x%08x)\n",
1817                                 PCI_MSK_AV_CORE);
1818
1819                 if (pci_status & PCI_MSK_IR)
1820                         dprintk(7, " (PCI_MSK_IR        0x%08x)\n",
1821                                 PCI_MSK_IR);
1822         }
1823
1824         if (cx23885_boards[dev->board].cimax > 0 &&
1825                 ((pci_status & PCI_MSK_GPIO0) ||
1826                         (pci_status & PCI_MSK_GPIO1))) {
1827
1828                 if (cx23885_boards[dev->board].cimax > 0)
1829                         handled += netup_ci_slot_status(dev, pci_status);
1830
1831         }
1832
1833         if (ts1_status) {
1834                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1835                         handled += cx23885_irq_ts(ts1, ts1_status);
1836                 else
1837                 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1838                         handled += cx23885_irq_417(dev, ts1_status);
1839         }
1840
1841         if (ts2_status) {
1842                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1843                         handled += cx23885_irq_ts(ts2, ts2_status);
1844                 else
1845                 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1846                         handled += cx23885_irq_417(dev, ts2_status);
1847         }
1848
1849         if (vida_status)
1850                 handled += cx23885_video_irq(dev, vida_status);
1851
1852         if (pci_status & PCI_MSK_IR) {
1853                 subdev_handled = false;
1854                 v4l2_subdev_call(dev->sd_ir, core, interrupt_service_routine,
1855                                  pci_status, &subdev_handled);
1856                 if (subdev_handled)
1857                         handled++;
1858         }
1859
1860         if ((pci_status & pci_mask) & PCI_MSK_AV_CORE) {
1861                 cx23885_irq_disable(dev, PCI_MSK_AV_CORE);
1862                 if (!schedule_work(&dev->cx25840_work))
1863                         printk(KERN_ERR "%s: failed to set up deferred work for"
1864                                " AV Core/IR interrupt. Interrupt is disabled"
1865                                " and won't be re-enabled\n", dev->name);
1866                 handled++;
1867         }
1868
1869         if (handled)
1870                 cx_write(PCI_INT_STAT, pci_status);
1871 out:
1872         return IRQ_RETVAL(handled);
1873 }
1874
1875 static void cx23885_v4l2_dev_notify(struct v4l2_subdev *sd,
1876                                     unsigned int notification, void *arg)
1877 {
1878         struct cx23885_dev *dev;
1879
1880         if (sd == NULL)
1881                 return;
1882
1883         dev = to_cx23885(sd->v4l2_dev);
1884
1885         switch (notification) {
1886         case V4L2_SUBDEV_IR_RX_NOTIFY: /* Possibly called in an IRQ context */
1887                 if (sd == dev->sd_ir)
1888                         cx23885_ir_rx_v4l2_dev_notify(sd, *(u32 *)arg);
1889                 break;
1890         case V4L2_SUBDEV_IR_TX_NOTIFY: /* Possibly called in an IRQ context */
1891                 if (sd == dev->sd_ir)
1892                         cx23885_ir_tx_v4l2_dev_notify(sd, *(u32 *)arg);
1893                 break;
1894         }
1895 }
1896
1897 static void cx23885_v4l2_dev_notify_init(struct cx23885_dev *dev)
1898 {
1899         INIT_WORK(&dev->cx25840_work, cx23885_av_work_handler);
1900         INIT_WORK(&dev->ir_rx_work, cx23885_ir_rx_work_handler);
1901         INIT_WORK(&dev->ir_tx_work, cx23885_ir_tx_work_handler);
1902         dev->v4l2_dev.notify = cx23885_v4l2_dev_notify;
1903 }
1904
1905 static inline int encoder_on_portb(struct cx23885_dev *dev)
1906 {
1907         return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER;
1908 }
1909
1910 static inline int encoder_on_portc(struct cx23885_dev *dev)
1911 {
1912         return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER;
1913 }
1914
1915 /* Mask represents 32 different GPIOs, GPIO's are split into multiple
1916  * registers depending on the board configuration (and whether the
1917  * 417 encoder (wi it's own GPIO's) are present. Each GPIO bit will
1918  * be pushed into the correct hardware register, regardless of the
1919  * physical location. Certain registers are shared so we sanity check
1920  * and report errors if we think we're tampering with a GPIo that might
1921  * be assigned to the encoder (and used for the host bus).
1922  *
1923  * GPIO  2 thru  0 - On the cx23885 bridge
1924  * GPIO 18 thru  3 - On the cx23417 host bus interface
1925  * GPIO 23 thru 19 - On the cx25840 a/v core
1926  */
1927 void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask)
1928 {
1929         if (mask & 0x7)
1930                 cx_set(GP0_IO, mask & 0x7);
1931
1932         if (mask & 0x0007fff8) {
1933                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1934                         printk(KERN_ERR
1935                                 "%s: Setting GPIO on encoder ports\n",
1936                                 dev->name);
1937                 cx_set(MC417_RWD, (mask & 0x0007fff8) >> 3);
1938         }
1939
1940         /* TODO: 23-19 */
1941         if (mask & 0x00f80000)
1942                 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1943 }
1944
1945 void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask)
1946 {
1947         if (mask & 0x00000007)
1948                 cx_clear(GP0_IO, mask & 0x7);
1949
1950         if (mask & 0x0007fff8) {
1951                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1952                         printk(KERN_ERR
1953                                 "%s: Clearing GPIO moving on encoder ports\n",
1954                                 dev->name);
1955                 cx_clear(MC417_RWD, (mask & 0x7fff8) >> 3);
1956         }
1957
1958         /* TODO: 23-19 */
1959         if (mask & 0x00f80000)
1960                 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1961 }
1962
1963 u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask)
1964 {
1965         if (mask & 0x00000007)
1966                 return (cx_read(GP0_IO) >> 8) & mask & 0x7;
1967
1968         if (mask & 0x0007fff8) {
1969                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1970                         printk(KERN_ERR
1971                                 "%s: Reading GPIO moving on encoder ports\n",
1972                                 dev->name);
1973                 return (cx_read(MC417_RWD) & ((mask & 0x7fff8) >> 3)) << 3;
1974         }
1975
1976         /* TODO: 23-19 */
1977         if (mask & 0x00f80000)
1978                 printk(KERN_INFO "%s: Unsupported\n", dev->name);
1979
1980         return 0;
1981 }
1982
1983 void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput)
1984 {
1985         if ((mask & 0x00000007) && asoutput)
1986                 cx_set(GP0_IO, (mask & 0x7) << 16);
1987         else if ((mask & 0x00000007) && !asoutput)
1988                 cx_clear(GP0_IO, (mask & 0x7) << 16);
1989
1990         if (mask & 0x0007fff8) {
1991                 if (encoder_on_portb(dev) || encoder_on_portc(dev))
1992                         printk(KERN_ERR
1993                                 "%s: Enabling GPIO on encoder ports\n",
1994                                 dev->name);
1995         }
1996
1997         /* MC417_OEN is active low for output, write 1 for an input */
1998         if ((mask & 0x0007fff8) && asoutput)
1999                 cx_clear(MC417_OEN, (mask & 0x7fff8) >> 3);
2000
2001         else if ((mask & 0x0007fff8) && !asoutput)
2002                 cx_set(MC417_OEN, (mask & 0x7fff8) >> 3);
2003
2004         /* TODO: 23-19 */
2005 }
2006
2007 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
2008                                      const struct pci_device_id *pci_id)
2009 {
2010         struct cx23885_dev *dev;
2011         int err;
2012
2013         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2014         if (NULL == dev)
2015                 return -ENOMEM;
2016
2017         err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev);
2018         if (err < 0)
2019                 goto fail_free;
2020
2021         /* Prepare to handle notifications from subdevices */
2022         cx23885_v4l2_dev_notify_init(dev);
2023
2024         /* pci init */
2025         dev->pci = pci_dev;
2026         if (pci_enable_device(pci_dev)) {
2027                 err = -EIO;
2028                 goto fail_unreg;
2029         }
2030
2031         if (cx23885_dev_setup(dev) < 0) {
2032                 err = -EINVAL;
2033                 goto fail_unreg;
2034         }
2035
2036         /* print pci info */
2037         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
2038         pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER,  &dev->pci_lat);
2039         printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
2040                "latency: %d, mmio: 0x%llx\n", dev->name,
2041                pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
2042                dev->pci_lat,
2043                 (unsigned long long)pci_resource_start(pci_dev, 0));
2044
2045         pci_set_master(pci_dev);
2046         if (!pci_dma_supported(pci_dev, 0xffffffff)) {
2047                 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
2048                 err = -EIO;
2049                 goto fail_irq;
2050         }
2051
2052         if (!pci_enable_msi(pci_dev))
2053                 err = request_irq(pci_dev->irq, cx23885_irq,
2054                                   IRQF_DISABLED, dev->name, dev);
2055         else
2056                 err = request_irq(pci_dev->irq, cx23885_irq,
2057                                   IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
2058         if (err < 0) {
2059                 printk(KERN_ERR "%s: can't get IRQ %d\n",
2060                        dev->name, pci_dev->irq);
2061                 goto fail_irq;
2062         }
2063
2064         switch (dev->board) {
2065         case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2066                 cx23885_irq_add_enable(dev, 0x01800000); /* for NetUP */
2067                 break;
2068         }
2069
2070         /*
2071          * The CX2388[58] IR controller can start firing interrupts when
2072          * enabled, so these have to take place after the cx23885_irq() handler
2073          * is hooked up by the call to request_irq() above.
2074          */
2075         cx23885_ir_pci_int_enable(dev);
2076         cx23885_input_init(dev);
2077
2078         return 0;
2079
2080 fail_irq:
2081         cx23885_dev_unregister(dev);
2082 fail_unreg:
2083         v4l2_device_unregister(&dev->v4l2_dev);
2084 fail_free:
2085         kfree(dev);
2086         return err;
2087 }
2088
2089 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
2090 {
2091         struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
2092         struct cx23885_dev *dev = to_cx23885(v4l2_dev);
2093
2094         cx23885_input_fini(dev);
2095         cx23885_ir_fini(dev);
2096
2097         cx23885_shutdown(dev);
2098
2099         pci_disable_device(pci_dev);
2100
2101         /* unregister stuff */
2102         free_irq(pci_dev->irq, dev);
2103         pci_disable_msi(pci_dev);
2104
2105         cx23885_dev_unregister(dev);
2106         v4l2_device_unregister(v4l2_dev);
2107         kfree(dev);
2108 }
2109
2110 static struct pci_device_id cx23885_pci_tbl[] = {
2111         {
2112                 /* CX23885 */
2113                 .vendor       = 0x14f1,
2114                 .device       = 0x8852,
2115                 .subvendor    = PCI_ANY_ID,
2116                 .subdevice    = PCI_ANY_ID,
2117         }, {
2118                 /* CX23887 Rev 2 */
2119                 .vendor       = 0x14f1,
2120                 .device       = 0x8880,
2121                 .subvendor    = PCI_ANY_ID,
2122                 .subdevice    = PCI_ANY_ID,
2123         }, {
2124                 /* --- end of list --- */
2125         }
2126 };
2127 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
2128
2129 static struct pci_driver cx23885_pci_driver = {
2130         .name     = "cx23885",
2131         .id_table = cx23885_pci_tbl,
2132         .probe    = cx23885_initdev,
2133         .remove   = __devexit_p(cx23885_finidev),
2134         /* TODO */
2135         .suspend  = NULL,
2136         .resume   = NULL,
2137 };
2138
2139 static int __init cx23885_init(void)
2140 {
2141         printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
2142                (CX23885_VERSION_CODE >> 16) & 0xff,
2143                (CX23885_VERSION_CODE >>  8) & 0xff,
2144                CX23885_VERSION_CODE & 0xff);
2145 #ifdef SNAPSHOT
2146         printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
2147                SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
2148 #endif
2149         return pci_register_driver(&cx23885_pci_driver);
2150 }
2151
2152 static void __exit cx23885_fini(void)
2153 {
2154         pci_unregister_driver(&cx23885_pci_driver);
2155 }
2156
2157 module_init(cx23885_init);
2158 module_exit(cx23885_fini);
2159
2160 /* ----------------------------------------------------------- */