drivers/media/video/cx231xx/cx231xx-avcore.c

   1 /*
   2    cx231xx_avcore.c - driver for Conexant Cx23100/101/102
   3                       USB video capture devices
   4
   5    Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   6
   7    This program contains the specific code to control the avdecoder chip and
   8    other related usb control functions for cx231xx based chipset.
   9
  10    This program is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 2 of the License, or
  13    (at your option) any later version.
  14
  15    This program is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this program; if not, write to the Free Software
  22    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/list.h>
  27 #include <linux/module.h>
  28 #include <linux/kernel.h>
  29 #include <linux/bitmap.h>
  30 #include <linux/usb.h>
  31 #include <linux/i2c.h>
  32 #include <linux/version.h>
  33 #include <linux/mm.h>
  34 #include <linux/mutex.h>
  35
  36 #include <media/v4l2-common.h>
  37 #include <media/v4l2-ioctl.h>
  38 #include <media/v4l2-chip-ident.h>
  39
  40 #include "cx231xx.h"
  41
  42 /******************************************************************************
  43                         -: BLOCK ARRANGEMENT :-
  44         I2S block ----------------------|
  45         [I2S audio]                     |
  46                                         |
  47         Analog Front End --> Direct IF -|-> Cx25840 --> Audio
  48         [video & audio]                 |   [Audio]
  49                                         |
  50                                         |-> Cx25840 --> Video
  51                                             [Video]
  52
  53 *******************************************************************************/
  54
  55 /******************************************************************************
  56  *                    A F E - B L O C K    C O N T R O L   functions          *
  57  *                              [ANALOG FRONT END]                            *
  58  ******************************************************************************/
  59 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
  60 {
  61         return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
  62                                         saddr, 2, data, 1);
  63 }
  64
  65 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
  66 {
  67         int status;
  68         u32 temp = 0;
  69
  70         status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
  71                                         saddr, 2, &temp, 1);
  72         *data = (u8) temp;
  73         return status;
  74 }
  75
  76 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
  77 {
  78         int status = 0;
  79         u8 temp = 0;
  80         u8 afe_power_status = 0;
  81         int i = 0;
  82
  83         /* super block initialize */
  84         temp = (u8) (ref_count & 0xff);
  85         status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
  86         if (status < 0)
  87                 return status;
  88
  89         status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
  90         if (status < 0)
  91                 return status;
  92
  93         temp = (u8) ((ref_count & 0x300) >> 8);
  94         temp |= 0x40;
  95         status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
  96         if (status < 0)
  97                 return status;
  98
  99         status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
 100         if (status < 0)
 101                 return status;
 102
 103         /* enable pll     */
 104         while (afe_power_status != 0x18) {
 105                 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
 106                 if (status < 0) {
 107                         cx231xx_info(
 108                         ": Init Super Block failed in send cmd\n");
 109                         break;
 110                 }
 111
 112                 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
 113                 afe_power_status &= 0xff;
 114                 if (status < 0) {
 115                         cx231xx_info(
 116                         ": Init Super Block failed in receive cmd\n");
 117                         break;
 118                 }
 119                 i++;
 120                 if (i == 10) {
 121                         cx231xx_info(
 122                         ": Init Super Block force break in loop !!!!\n");
 123                         status = -1;
 124                         break;
 125                 }
 126         }
 127
 128         if (status < 0)
 129                 return status;
 130
 131         /* start tuning filter */
 132         status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
 133         if (status < 0)
 134                 return status;
 135
 136         msleep(5);
 137
 138         /* exit tuning */
 139         status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
 140
 141         return status;
 142 }
 143
 144 int cx231xx_afe_init_channels(struct cx231xx *dev)
 145 {
 146         int status = 0;
 147
 148         /* power up all 3 channels, clear pd_buffer */
 149         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
 150         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
 151         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
 152
 153         /* Enable quantizer calibration */
 154         status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
 155
 156         /* channel initialize, force modulator (fb) reset */
 157         status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
 158         status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
 159         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
 160
 161         /* start quantilizer calibration  */
 162         status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
 163         status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
 164         status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
 165         msleep(5);
 166
 167         /* exit modulator (fb) reset */
 168         status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
 169         status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
 170         status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
 171
 172         /* enable the pre_clamp in each channel for single-ended input */
 173         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
 174         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
 175         status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
 176
 177         /* use diode instead of resistor, so set term_en to 0, res_en to 0  */
 178         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 179                                    ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
 180         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 181                                    ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
 182         status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 183                                    ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
 184
 185         /* dynamic element matching off */
 186         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
 187         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
 188         status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
 189
 190         return status;
 191 }
 192
 193 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
 194 {
 195         u8 c_value = 0;
 196         int status = 0;
 197
 198         status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
 199         c_value &= (~(0x50));
 200         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
 201
 202         return status;
 203 }
 204
 205 /*
 206         The Analog Front End in Cx231xx has 3 channels. These
 207         channels are used to share between different inputs
 208         like tuner, s-video and composite inputs.
 209
 210         channel 1 ----- pin 1  to pin4(in reg is 1-4)
 211         channel 2 ----- pin 5  to pin8(in reg is 5-8)
 212         channel 3 ----- pin 9 to pin 12(in reg is 9-11)
 213 */
 214 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
 215 {
 216         u8 ch1_setting = (u8) input_mux;
 217         u8 ch2_setting = (u8) (input_mux >> 8);
 218         u8 ch3_setting = (u8) (input_mux >> 16);
 219         int status = 0;
 220         u8 value = 0;
 221
 222         if (ch1_setting != 0) {
 223                 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
 224                 value &= (!INPUT_SEL_MASK);
 225                 value |= (ch1_setting - 1) << 4;
 226                 value &= 0xff;
 227                 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
 228         }
 229
 230         if (ch2_setting != 0) {
 231                 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
 232                 value &= (!INPUT_SEL_MASK);
 233                 value |= (ch2_setting - 1) << 4;
 234                 value &= 0xff;
 235                 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
 236         }
 237
 238         /* For ch3_setting, the value to put in the register is
 239            7 less than the input number */
 240         if (ch3_setting != 0) {
 241                 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
 242                 value &= (!INPUT_SEL_MASK);
 243                 value |= (ch3_setting - 1) << 4;
 244                 value &= 0xff;
 245                 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
 246         }
 247
 248         return status;
 249 }
 250
 251 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
 252 {
 253         int status = 0;
 254
 255         /*
 256         * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
 257         * Currently, only baseband works.
 258         */
 259
 260         switch (mode) {
 261         case AFE_MODE_LOW_IF:
 262                 /* SetupAFEforLowIF();  */
 263                 break;
 264         case AFE_MODE_BASEBAND:
 265                 status = cx231xx_afe_setup_AFE_for_baseband(dev);
 266                 break;
 267         case AFE_MODE_EU_HI_IF:
 268                 /* SetupAFEforEuHiIF(); */
 269                 break;
 270         case AFE_MODE_US_HI_IF:
 271                 /* SetupAFEforUsHiIF(); */
 272                 break;
 273         case AFE_MODE_JAPAN_HI_IF:
 274                 /* SetupAFEforJapanHiIF(); */
 275                 break;
 276         }
 277
 278         if ((mode != dev->afe_mode) &&
 279                 (dev->video_input == CX231XX_VMUX_TELEVISION))
 280                 status = cx231xx_afe_adjust_ref_count(dev,
 281                                                      CX231XX_VMUX_TELEVISION);
 282
 283         dev->afe_mode = mode;
 284
 285         return status;
 286 }
 287
 288 int cx231xx_afe_update_power_control(struct cx231xx *dev,
 289                                         enum AV_MODE avmode)
 290 {
 291         u8 afe_power_status = 0;
 292         int status = 0;
 293
 294         switch (dev->model) {
 295         case CX231XX_BOARD_CNXT_RDE_250:
 296         case CX231XX_BOARD_CNXT_RDU_250:
 297                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 298                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 299                                                 FLD_PWRDN_ENABLE_PLL)) {
 300                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 301                                                         FLD_PWRDN_TUNING_BIAS |
 302                                                         FLD_PWRDN_ENABLE_PLL);
 303                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 304                                                         &afe_power_status);
 305                                 if (status < 0)
 306                                         break;
 307                         }
 308
 309                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 310                                                         0x00);
 311                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 312                                                         0x00);
 313                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 314                                                         0x00);
 315                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 316                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 317                                                         0x70);
 318                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 319                                                         0x70);
 320                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 321                                                         0x70);
 322
 323                         status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 324                                                   &afe_power_status);
 325                         afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 326                                                 FLD_PWRDN_PD_BIAS |
 327                                                 FLD_PWRDN_PD_TUNECK;
 328                         status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 329                                                    afe_power_status);
 330                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 331                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 332                                                 FLD_PWRDN_ENABLE_PLL)) {
 333                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 334                                                         FLD_PWRDN_TUNING_BIAS |
 335                                                         FLD_PWRDN_ENABLE_PLL);
 336                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 337                                                         &afe_power_status);
 338                                 if (status < 0)
 339                                         break;
 340                         }
 341
 342                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 343                                                 0x00);
 344                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 345                                                 0x00);
 346                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 347                                                 0x00);
 348                 } else {
 349                         cx231xx_info("Invalid AV mode input\n");
 350                         status = -1;
 351                 }
 352                 break;
 353         default:
 354                 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 355                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 356                                                 FLD_PWRDN_ENABLE_PLL)) {
 357                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 358                                                         FLD_PWRDN_TUNING_BIAS |
 359                                                         FLD_PWRDN_ENABLE_PLL);
 360                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 361                                                         &afe_power_status);
 362                                 if (status < 0)
 363                                         break;
 364                         }
 365
 366                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 367                                                         0x40);
 368                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 369                                                         0x40);
 370                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 371                                                         0x00);
 372                 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 373                         status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 374                                                         0x70);
 375                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 376                                                         0x70);
 377                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 378                                                         0x70);
 379
 380                         status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 381                                                        &afe_power_status);
 382                         afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 383                                                 FLD_PWRDN_PD_BIAS |
 384                                                 FLD_PWRDN_PD_TUNECK;
 385                         status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 386                                                         afe_power_status);
 387                 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 388                         while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 389                                                 FLD_PWRDN_ENABLE_PLL)) {
 390                                 status = afe_write_byte(dev, SUP_BLK_PWRDN,
 391                                                         FLD_PWRDN_TUNING_BIAS |
 392                                                         FLD_PWRDN_ENABLE_PLL);
 393                                 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 394                                                         &afe_power_status);
 395                                 if (status < 0)
 396                                         break;
 397                         }
 398
 399                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 400                                                         0x00);
 401                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 402                                                         0x00);
 403                         status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 404                                                         0x40);
 405                 } else {
 406                         cx231xx_info("Invalid AV mode input\n");
 407                         status = -1;
 408                 }
 409         }                       /* switch  */
 410
 411         return status;
 412 }
 413
 414 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
 415 {
 416         u8 input_mode = 0;
 417         u8 ntf_mode = 0;
 418         int status = 0;
 419
 420         dev->video_input = video_input;
 421
 422         if (video_input == CX231XX_VMUX_TELEVISION) {
 423                 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
 424                 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
 425                                         &ntf_mode);
 426         } else {
 427                 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
 428                 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
 429                                         &ntf_mode);
 430         }
 431
 432         input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
 433
 434         switch (input_mode) {
 435         case SINGLE_ENDED:
 436                 dev->afe_ref_count = 0x23C;
 437                 break;
 438         case LOW_IF:
 439                 dev->afe_ref_count = 0x24C;
 440                 break;
 441         case EU_IF:
 442                 dev->afe_ref_count = 0x258;
 443                 break;
 444         case US_IF:
 445                 dev->afe_ref_count = 0x260;
 446                 break;
 447         default:
 448                 break;
 449         }
 450
 451         status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
 452
 453         return status;
 454 }
 455
 456 /******************************************************************************
 457  *     V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions    *
 458  ******************************************************************************/
 459 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
 460 {
 461         return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 462                                         saddr, 2, data, 1);
 463 }
 464
 465 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
 466 {
 467         int status;
 468         u32 temp = 0;
 469
 470         status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 471                                         saddr, 2, &temp, 1);
 472         *data = (u8) temp;
 473         return status;
 474 }
 475
 476 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
 477 {
 478         return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 479                                         saddr, 2, data, 4);
 480 }
 481
 482 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
 483 {
 484         return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 485                                         saddr, 2, data, 4);
 486 }
 487
 488 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
 489 {
 490         int status = 0;
 491
 492         switch (INPUT(input)->type) {
 493         case CX231XX_VMUX_COMPOSITE1:
 494         case CX231XX_VMUX_SVIDEO:
 495                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 496                     (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
 497                         /* External AV */
 498                         status = cx231xx_set_power_mode(dev,
 499                                         POLARIS_AVMODE_ENXTERNAL_AV);
 500                         if (status < 0) {
 501                                 cx231xx_errdev("%s: set_power_mode : Failed to"
 502                                                 " set Power - errCode [%d]!\n",
 503                                                 __func__, status);
 504                                 return status;
 505                         }
 506                 }
 507                 status = cx231xx_set_decoder_video_input(dev,
 508                                                          INPUT(input)->type,
 509                                                          INPUT(input)->vmux);
 510                 break;
 511         case CX231XX_VMUX_TELEVISION:
 512         case CX231XX_VMUX_CABLE:
 513                 if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 514                     (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
 515                         /* Tuner */
 516                         status = cx231xx_set_power_mode(dev,
 517                                                 POLARIS_AVMODE_ANALOGT_TV);
 518                         if (status < 0) {
 519                                 cx231xx_errdev("%s: set_power_mode:Failed"
 520                                         " to set Power - errCode [%d]!\n",
 521                                         __func__, status);
 522                                 return status;
 523                         }
 524                 }
 525                 status = cx231xx_set_decoder_video_input(dev,
 526                                                         CX231XX_VMUX_COMPOSITE1,
 527                                                         INPUT(input)->vmux);
 528                 break;
 529         default:
 530                 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
 531                      __func__, INPUT(input)->type);
 532                 break;
 533         }
 534
 535         /* save the selection */
 536         dev->video_input = input;
 537
 538         return status;
 539 }
 540
 541 int cx231xx_set_decoder_video_input(struct cx231xx *dev,
 542                                 u8 pin_type, u8 input)
 543 {
 544         int status = 0;
 545         u32 value = 0;
 546
 547         if (pin_type != dev->video_input) {
 548                 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
 549                 if (status < 0) {
 550                         cx231xx_errdev("%s: adjust_ref_count :Failed to set"
 551                                 "AFE input mux - errCode [%d]!\n",
 552                                 __func__, status);
 553                         return status;
 554                 }
 555         }
 556
 557         /* call afe block to set video inputs */
 558         status = cx231xx_afe_set_input_mux(dev, input);
 559         if (status < 0) {
 560                 cx231xx_errdev("%s: set_input_mux :Failed to set"
 561                                 " AFE input mux - errCode [%d]!\n",
 562                                 __func__, status);
 563                 return status;
 564         }
 565
 566         switch (pin_type) {
 567         case CX231XX_VMUX_COMPOSITE1:
 568                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 569                 value |= (0 << 13) | (1 << 4);
 570                 value &= ~(1 << 5);
 571
 572                 /* set [24:23] [22:15] to 0  */
 573                 value &= (~(0x1ff8000));
 574                 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
 575                 value |= 0x1000000;
 576                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 577
 578                 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 579                 value |= (1 << 7);
 580                 status = vid_blk_write_word(dev, OUT_CTRL1, value);
 581
 582                 /* Set vip 1.1 output mode */
 583                 status = cx231xx_read_modify_write_i2c_dword(dev,
 584                                                         VID_BLK_I2C_ADDRESS,
 585                                                         OUT_CTRL1,
 586                                                         FLD_OUT_MODE,
 587                                                         OUT_MODE_VIP11);
 588
 589                 /* Tell DIF object to go to baseband mode  */
 590                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 591                 if (status < 0) {
 592                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 593                                                    " mode- errCode [%d]!\n",
 594                                 __func__, status);
 595                         return status;
 596                 }
 597
 598                 /* Read the DFE_CTRL1 register */
 599                 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 600
 601                 /* enable the VBI_GATE_EN */
 602                 value |= FLD_VBI_GATE_EN;
 603
 604                 /* Enable the auto-VGA enable */
 605                 value |= FLD_VGA_AUTO_EN;
 606
 607                 /* Write it back */
 608                 status = vid_blk_write_word(dev, DFE_CTRL1, value);
 609
 610                 /* Disable auto config of registers */
 611                 status = cx231xx_read_modify_write_i2c_dword(dev,
 612                                         VID_BLK_I2C_ADDRESS,
 613                                         MODE_CTRL, FLD_ACFG_DIS,
 614                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 615
 616                 /* Set CVBS input mode */
 617                 status = cx231xx_read_modify_write_i2c_dword(dev,
 618                         VID_BLK_I2C_ADDRESS,
 619                         MODE_CTRL, FLD_INPUT_MODE,
 620                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
 621                 break;
 622         case CX231XX_VMUX_SVIDEO:
 623                 /* Disable the use of  DIF */
 624
 625                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 626
 627                 /* set [24:23] [22:15] to 0 */
 628                 value &= (~(0x1ff8000));
 629                 /* set FUNC_MODE[24:23] = 2
 630                 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
 631                 value |= 0x1000010;
 632                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 633
 634                 /* Tell DIF object to go to baseband mode */
 635                 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 636                 if (status < 0) {
 637                         cx231xx_errdev("%s: cx231xx_dif set to By pass"
 638                                                    " mode- errCode [%d]!\n",
 639                                 __func__, status);
 640                         return status;
 641                 }
 642
 643                 /* Read the DFE_CTRL1 register */
 644                 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 645
 646                 /* enable the VBI_GATE_EN */
 647                 value |= FLD_VBI_GATE_EN;
 648
 649                 /* Enable the auto-VGA enable */
 650                 value |= FLD_VGA_AUTO_EN;
 651
 652                 /* Write it back */
 653                 status = vid_blk_write_word(dev, DFE_CTRL1, value);
 654
 655                 /* Disable auto config of registers  */
 656                 status =  cx231xx_read_modify_write_i2c_dword(dev,
 657                                         VID_BLK_I2C_ADDRESS,
 658                                         MODE_CTRL, FLD_ACFG_DIS,
 659                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 660
 661                 /* Set YC input mode */
 662                 status = cx231xx_read_modify_write_i2c_dword(dev,
 663                         VID_BLK_I2C_ADDRESS,
 664                         MODE_CTRL,
 665                         FLD_INPUT_MODE,
 666                         cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
 667
 668                 /* Chroma to ADC2 */
 669                 status = vid_blk_read_word(dev, AFE_CTRL, &value);
 670                 value |= FLD_CHROMA_IN_SEL;     /* set the chroma in select */
 671
 672                 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
 673                    This sets them to use video
 674                    rather than audio.  Only one of the two will be in use. */
 675                 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
 676
 677                 status = vid_blk_write_word(dev, AFE_CTRL, value);
 678
 679                 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
 680                 break;
 681         case CX231XX_VMUX_TELEVISION:
 682         case CX231XX_VMUX_CABLE:
 683         default:
 684                 switch (dev->model) {
 685                 case CX231XX_BOARD_CNXT_RDE_250:
 686                 case CX231XX_BOARD_CNXT_RDU_250:
 687                         /* Disable the use of  DIF   */
 688
 689                         status = vid_blk_read_word(dev, AFE_CTRL, &value);
 690                         value |= (0 << 13) | (1 << 4);
 691                         value &= ~(1 << 5);
 692
 693                         /* set [24:23] [22:15] to 0 */
 694                         value &= (~(0x1FF8000));
 695                         /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
 696                         value |= 0x1000000;
 697                         status = vid_blk_write_word(dev, AFE_CTRL, value);
 698
 699                         status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 700                         value |= (1 << 7);
 701                         status = vid_blk_write_word(dev, OUT_CTRL1, value);
 702
 703                         /* Set vip 1.1 output mode */
 704                         status = cx231xx_read_modify_write_i2c_dword(dev,
 705                                                         VID_BLK_I2C_ADDRESS,
 706                                                         OUT_CTRL1, FLD_OUT_MODE,
 707                                                         OUT_MODE_VIP11);
 708
 709                         /* Tell DIF object to go to baseband mode */
 710                         status = cx231xx_dif_set_standard(dev,
 711                                                           DIF_USE_BASEBAND);
 712                         if (status < 0) {
 713                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 714                                                 " mode- errCode [%d]!\n",
 715                                                 __func__, status);
 716                                 return status;
 717                         }
 718
 719                         /* Read the DFE_CTRL1 register */
 720                         status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 721
 722                         /* enable the VBI_GATE_EN */
 723                         value |= FLD_VBI_GATE_EN;
 724
 725                         /* Enable the auto-VGA enable */
 726                         value |= FLD_VGA_AUTO_EN;
 727
 728                         /* Write it back */
 729                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 730
 731                         /* Disable auto config of registers */
 732                         status = cx231xx_read_modify_write_i2c_dword(dev,
 733                                         VID_BLK_I2C_ADDRESS,
 734                                         MODE_CTRL, FLD_ACFG_DIS,
 735                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 736
 737                         /* Set CVBS input mode */
 738                         status = cx231xx_read_modify_write_i2c_dword(dev,
 739                                 VID_BLK_I2C_ADDRESS,
 740                                 MODE_CTRL, FLD_INPUT_MODE,
 741                                 cx231xx_set_field(FLD_INPUT_MODE,
 742                                                 INPUT_MODE_CVBS_0));
 743                         break;
 744                 default:
 745                         /* Enable the DIF for the tuner */
 746
 747                         /* Reinitialize the DIF */
 748                         status = cx231xx_dif_set_standard(dev, dev->norm);
 749                         if (status < 0) {
 750                                 cx231xx_errdev("%s: cx231xx_dif set to By pass"
 751                                                 " mode- errCode [%d]!\n",
 752                                                 __func__, status);
 753                                 return status;
 754                         }
 755
 756                         /* Make sure bypass is cleared */
 757                         status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
 758
 759                         /* Clear the bypass bit */
 760                         value &= ~FLD_DIF_DIF_BYPASS;
 761
 762                         /* Enable the use of the DIF block */
 763                         status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
 764
 765                         /* Read the DFE_CTRL1 register */
 766                         status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 767
 768                         /* Disable the VBI_GATE_EN */
 769                         value &= ~FLD_VBI_GATE_EN;
 770
 771                         /* Enable the auto-VGA enable, AGC, and
 772                            set the skip count to 2 */
 773                         value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
 774
 775                         /* Write it back */
 776                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 777
 778                         /* Wait until AGC locks up */
 779                         msleep(1);
 780
 781                         /* Disable the auto-VGA enable AGC */
 782                         value &= ~(FLD_VGA_AUTO_EN);
 783
 784                         /* Write it back */
 785                         status = vid_blk_write_word(dev, DFE_CTRL1, value);
 786
 787                         /* Enable Polaris B0 AGC output */
 788                         status = vid_blk_read_word(dev, PIN_CTRL, &value);
 789                         value |= (FLD_OEF_AGC_RF) |
 790                                  (FLD_OEF_AGC_IFVGA) |
 791                                  (FLD_OEF_AGC_IF);
 792                         status = vid_blk_write_word(dev, PIN_CTRL, value);
 793
 794                         /* Set vip 1.1 output mode */
 795                         status = cx231xx_read_modify_write_i2c_dword(dev,
 796                                                 VID_BLK_I2C_ADDRESS,
 797                                                 OUT_CTRL1, FLD_OUT_MODE,
 798                                                 OUT_MODE_VIP11);
 799
 800                         /* Disable auto config of registers */
 801                         status = cx231xx_read_modify_write_i2c_dword(dev,
 802                                         VID_BLK_I2C_ADDRESS,
 803                                         MODE_CTRL, FLD_ACFG_DIS,
 804                                         cx231xx_set_field(FLD_ACFG_DIS, 1));
 805
 806                         /* Set CVBS input mode */
 807                         status = cx231xx_read_modify_write_i2c_dword(dev,
 808                                 VID_BLK_I2C_ADDRESS,
 809                                 MODE_CTRL, FLD_INPUT_MODE,
 810                                 cx231xx_set_field(FLD_INPUT_MODE,
 811                                                 INPUT_MODE_CVBS_0));
 812
 813                         /* Set some bits in AFE_CTRL so that channel 2 or 3
 814                          * is ready to receive audio */
 815                         /* Clear clamp for channels 2 and 3      (bit 16-17) */
 816                         /* Clear droop comp                      (bit 19-20) */
 817                         /* Set VGA_SEL (for audio control)       (bit 7-8) */
 818                         status = vid_blk_read_word(dev, AFE_CTRL, &value);
 819
 820                         value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
 821
 822                         status = vid_blk_write_word(dev, AFE_CTRL, value);
 823                         break;
 824
 825                 }
 826                 break;
 827         }
 828
 829         /* Set raw VBI mode */
 830         status = cx231xx_read_modify_write_i2c_dword(dev,
 831                                 VID_BLK_I2C_ADDRESS,
 832                                 OUT_CTRL1, FLD_VBIHACTRAW_EN,
 833                                 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
 834
 835         status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 836         if (value & 0x02) {
 837                 value |= (1 << 19);
 838                 status = vid_blk_write_word(dev, OUT_CTRL1, value);
 839         }
 840
 841         return status;
 842 }
 843
 844 /*
 845  * Handle any video-mode specific overrides that are different
 846  * on a per video standards basis after touching the MODE_CTRL
 847  * register which resets many values for autodetect
 848  */
 849 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
 850 {
 851         int status = 0;
 852
 853         cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
 854                      (unsigned int)dev->norm);
 855
 856         /* Change the DFE_CTRL3 bp_percent to fix flagging */
 857         status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
 858
 859         if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
 860                 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
 861
 862                 /* Move the close caption lines out of active video,
 863                    adjust the active video start point */
 864                 status = cx231xx_read_modify_write_i2c_dword(dev,
 865                                                         VID_BLK_I2C_ADDRESS,
 866                                                         VERT_TIM_CTRL,
 867                                                         FLD_VBLANK_CNT, 0x18);
 868                 status = cx231xx_read_modify_write_i2c_dword(dev,
 869                                                         VID_BLK_I2C_ADDRESS,
 870                                                         VERT_TIM_CTRL,
 871                                                         FLD_VACTIVE_CNT,
 872                                                         0x1E6000);
 873                 status = cx231xx_read_modify_write_i2c_dword(dev,
 874                                                         VID_BLK_I2C_ADDRESS,
 875                                                         VERT_TIM_CTRL,
 876                                                         FLD_V656BLANK_CNT,
 877                                                         0x1E000000);
 878
 879                 status = cx231xx_read_modify_write_i2c_dword(dev,
 880                                                         VID_BLK_I2C_ADDRESS,
 881                                                         HORIZ_TIM_CTRL,
 882                                                         FLD_HBLANK_CNT,
 883                                                         cx231xx_set_field
 884                                                         (FLD_HBLANK_CNT, 0x79));
 885         } else if (dev->norm & V4L2_STD_SECAM) {
 886                 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
 887                 status =  cx231xx_read_modify_write_i2c_dword(dev,
 888                                                         VID_BLK_I2C_ADDRESS,
 889                                                         VERT_TIM_CTRL,
 890                                                         FLD_VBLANK_CNT, 0x24);
 891                 /* Adjust the active video horizontal start point */
 892                 status = cx231xx_read_modify_write_i2c_dword(dev,
 893                                                         VID_BLK_I2C_ADDRESS,
 894                                                         HORIZ_TIM_CTRL,
 895                                                         FLD_HBLANK_CNT,
 896                                                         cx231xx_set_field
 897                                                         (FLD_HBLANK_CNT, 0x85));
 898         } else {
 899                 cx231xx_info("do_mode_ctrl_overrides PAL\n");
 900                 status = cx231xx_read_modify_write_i2c_dword(dev,
 901                                                         VID_BLK_I2C_ADDRESS,
 902                                                         VERT_TIM_CTRL,
 903                                                         FLD_VBLANK_CNT, 0x24);
 904                 /* Adjust the active video horizontal start point */
 905                 status = cx231xx_read_modify_write_i2c_dword(dev,
 906                                                         VID_BLK_I2C_ADDRESS,
 907                                                         HORIZ_TIM_CTRL,
 908                                                         FLD_HBLANK_CNT,
 909                                                         cx231xx_set_field
 910                                                         (FLD_HBLANK_CNT, 0x85));
 911         }
 912
 913         return status;
 914 }
 915
 916 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
 917 {
 918         int status = 0;
 919         enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
 920
 921         switch (INPUT(input)->amux) {
 922         case CX231XX_AMUX_VIDEO:
 923                 ainput = AUDIO_INPUT_TUNER_TV;
 924                 break;
 925         case CX231XX_AMUX_LINE_IN:
 926                 status = cx231xx_i2s_blk_set_audio_input(dev, input);
 927                 ainput = AUDIO_INPUT_LINE;
 928                 break;
 929         default:
 930                 break;
 931         }
 932
 933         status = cx231xx_set_audio_decoder_input(dev, ainput);
 934
 935         return status;
 936 }
 937
 938 int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
 939                                     enum AUDIO_INPUT audio_input)
 940 {
 941         u32 dwval;
 942         int status;
 943         u8 gen_ctrl;
 944         u32 value = 0;
 945
 946         /* Put it in soft reset   */
 947         status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
 948         gen_ctrl |= 1;
 949         status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
 950
 951         switch (audio_input) {
 952         case AUDIO_INPUT_LINE:
 953                 /* setup AUD_IO control from Merlin paralle output */
 954                 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
 955                                           AUD_CHAN_SRC_PARALLEL);
 956                 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
 957
 958                 /* setup input to Merlin, SRC2 connect to AC97
 959                    bypass upsample-by-2, slave mode, sony mode, left justify
 960                    adr 091c, dat 01000000 */
 961                 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
 962
 963                 status = vid_blk_write_word(dev, AC97_CTL,
 964                                            (dwval | FLD_AC97_UP2X_BYPASS));
 965
 966                 /* select the parallel1 and SRC3 */
 967                 status = vid_blk_write_word(dev, BAND_OUT_SEL,
 968                                 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
 969                                 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
 970                                 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
 971
 972                 /* unmute all, AC97 in, independence mode
 973                    adr 08d0, data 0x00063073 */
 974                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
 975
 976                 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
 977                 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
 978                 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
 979                                            (dwval | FLD_PATH1_AVC_THRESHOLD));
 980
 981                 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
 982                 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
 983                 status = vid_blk_write_word(dev, PATH1_SC_CTL,
 984                                            (dwval | FLD_PATH1_SC_THRESHOLD));
 985                 break;
 986
 987         case AUDIO_INPUT_TUNER_TV:
 988         default:
 989
 990                 /* Setup SRC sources and clocks */
 991                 status = vid_blk_write_word(dev, BAND_OUT_SEL,
 992                         cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)         |
 993                         cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)        |
 994                         cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)         |
 995                         cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)        |
 996                         cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)         |
 997                         cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)        |
 998                         cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)         |
 999                         cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)        |
1000                         cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1001                         cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)        |
1002                         cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)         |
1003                         cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)   |
1004                         cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1005
1006                 /* Setup the AUD_IO control */
1007                 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1008                         cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)  |
1009                         cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)   |
1010                         cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1011                         cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1012                         cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1013
1014                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1015
1016                 /* setAudioStandard(_audio_standard); */
1017
1018                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1019                 switch (dev->model) {
1020                 case CX231XX_BOARD_CNXT_RDE_250:
1021                 case CX231XX_BOARD_CNXT_RDU_250:
1022                         status = cx231xx_read_modify_write_i2c_dword(dev,
1023                                         VID_BLK_I2C_ADDRESS,
1024                                         CHIP_CTRL,
1025                                         FLD_SIF_EN,
1026                                         cx231xx_set_field(FLD_SIF_EN, 1));
1027                         break;
1028                 default:
1029                         break;
1030                 }
1031                 break;
1032
1033         case AUDIO_INPUT_TUNER_FM:
1034                 /*  use SIF for FM radio
1035                    setupFM();
1036                    setAudioStandard(_audio_standard);
1037                  */
1038                 break;
1039
1040         case AUDIO_INPUT_MUTE:
1041                 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1042                 break;
1043         }
1044
1045         /* Take it out of soft reset */
1046         status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1047         gen_ctrl &= ~1;
1048         status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1049
1050         return status;
1051 }
1052
1053 /* Set resolution of the video */
1054 int cx231xx_resolution_set(struct cx231xx *dev)
1055 {
1056         int width, height;
1057         u32 hscale, vscale;
1058         int status = 0;
1059
1060         width = dev->width;
1061         height = dev->height;
1062
1063         get_scale(dev, width, height, &hscale, &vscale);
1064
1065         /* set horzontal scale */
1066         status = vid_blk_write_word(dev, HSCALE_CTRL, hscale);
1067
1068         /* set vertical scale */
1069         status = vid_blk_write_word(dev, VSCALE_CTRL, vscale);
1070
1071         return status;
1072 }
1073
1074 /******************************************************************************
1075  *                    C H I P Specific  C O N T R O L   functions             *
1076  ******************************************************************************/
1077 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1078 {
1079         u32 value;
1080         int status = 0;
1081
1082         status = vid_blk_read_word(dev, PIN_CTRL, &value);
1083         value |= (~dev->board.ctl_pin_status_mask);
1084         status = vid_blk_write_word(dev, PIN_CTRL, value);
1085
1086         return status;
1087 }
1088
1089 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1090                                               u8 analog_or_digital)
1091 {
1092         int status = 0;
1093
1094         /* first set the direction to output */
1095         status = cx231xx_set_gpio_direction(dev,
1096                                             dev->board.
1097                                             agc_analog_digital_select_gpio, 1);
1098
1099         /* 0 - demod ; 1 - Analog mode */
1100         status = cx231xx_set_gpio_value(dev,
1101                                    dev->board.agc_analog_digital_select_gpio,
1102                                    analog_or_digital);
1103
1104         return status;
1105 }
1106
1107 int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1108 {
1109         u8 value[4] = { 0, 0, 0, 0 };
1110         int status = 0;
1111
1112         cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1113
1114         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1115                                        PWR_CTL_EN, value, 4);
1116         if (status < 0)
1117                 return status;
1118
1119         if (I2CIndex == I2C_1) {
1120                 if (value[0] & I2C_DEMOD_EN) {
1121                         value[0] &= ~I2C_DEMOD_EN;
1122                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1123                                                    PWR_CTL_EN, value, 4);
1124                 }
1125         } else {
1126                 if (!(value[0] & I2C_DEMOD_EN)) {
1127                         value[0] |= I2C_DEMOD_EN;
1128                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1129                                                    PWR_CTL_EN, value, 4);
1130                 }
1131         }
1132
1133         return status;
1134
1135 }
1136
1137 /******************************************************************************
1138  *                 D I F - B L O C K    C O N T R O L   functions             *
1139  ******************************************************************************/
1140 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1141                                           u32 function_mode, u32 standard)
1142 {
1143         int status = 0;
1144
1145         if (mode == V4L2_TUNER_RADIO) {
1146                 /* C2HH */
1147                 /* lo if big signal */
1148                 status = cx231xx_reg_mask_write(dev,
1149                                 VID_BLK_I2C_ADDRESS, 32,
1150                                 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1151                 /* FUNC_MODE = DIF */
1152                 status = cx231xx_reg_mask_write(dev,
1153                                 VID_BLK_I2C_ADDRESS, 32,
1154                                 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1155                 /* IF_MODE */
1156                 status = cx231xx_reg_mask_write(dev,
1157                                 VID_BLK_I2C_ADDRESS, 32,
1158                                 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1159                 /* no inv */
1160                 status = cx231xx_reg_mask_write(dev,
1161                                 VID_BLK_I2C_ADDRESS, 32,
1162                                 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1163         } else if (standard != DIF_USE_BASEBAND) {
1164                 if (standard & V4L2_STD_MN) {
1165                         /* lo if big signal */
1166                         status = cx231xx_reg_mask_write(dev,
1167                                         VID_BLK_I2C_ADDRESS, 32,
1168                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1169                         /* FUNC_MODE = DIF */
1170                         status = cx231xx_reg_mask_write(dev,
1171                                         VID_BLK_I2C_ADDRESS, 32,
1172                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1173                                         function_mode);
1174                         /* IF_MODE */
1175                         status = cx231xx_reg_mask_write(dev,
1176                                         VID_BLK_I2C_ADDRESS, 32,
1177                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1178                         /* no inv */
1179                         status = cx231xx_reg_mask_write(dev,
1180                                         VID_BLK_I2C_ADDRESS, 32,
1181                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1182                         /* 0x124, AUD_CHAN1_SRC = 0x3 */
1183                         status = cx231xx_reg_mask_write(dev,
1184                                         VID_BLK_I2C_ADDRESS, 32,
1185                                         AUD_IO_CTRL, 0, 31, 0x00000003);
1186                 } else if ((standard == V4L2_STD_PAL_I) |
1187                         (standard & V4L2_STD_SECAM)) {
1188                         /* C2HH setup */
1189                         /* lo if big signal */
1190                         status = cx231xx_reg_mask_write(dev,
1191                                         VID_BLK_I2C_ADDRESS, 32,
1192                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1193                         /* FUNC_MODE = DIF */
1194                         status = cx231xx_reg_mask_write(dev,
1195                                         VID_BLK_I2C_ADDRESS, 32,
1196                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1197                                         function_mode);
1198                         /* IF_MODE */
1199                         status = cx231xx_reg_mask_write(dev,
1200                                         VID_BLK_I2C_ADDRESS, 32,
1201                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1202                         /* no inv */
1203                         status = cx231xx_reg_mask_write(dev,
1204                                         VID_BLK_I2C_ADDRESS, 32,
1205                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1206                 } else {
1207                         /* default PAL BG */
1208                         /* C2HH setup */
1209                         /* lo if big signal */
1210                         status = cx231xx_reg_mask_write(dev,
1211                                         VID_BLK_I2C_ADDRESS, 32,
1212                                         AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1213                         /* FUNC_MODE = DIF */
1214                         status = cx231xx_reg_mask_write(dev,
1215                                         VID_BLK_I2C_ADDRESS, 32,
1216                                         AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1217                                         function_mode);
1218                         /* IF_MODE */
1219                         status = cx231xx_reg_mask_write(dev,
1220                                         VID_BLK_I2C_ADDRESS, 32,
1221                                         AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1222                         /* no inv */
1223                         status = cx231xx_reg_mask_write(dev,
1224                                         VID_BLK_I2C_ADDRESS, 32,
1225                                         AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1226                 }
1227         }
1228
1229         return status;
1230 }
1231
1232 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1233 {
1234         int status = 0;
1235         u32 dif_misc_ctrl_value = 0;
1236         u32 func_mode = 0;
1237
1238         cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1239
1240         status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1241         if (standard != DIF_USE_BASEBAND)
1242                 dev->norm = standard;
1243
1244         switch (dev->model) {
1245         case CX231XX_BOARD_CNXT_RDE_250:
1246         case CX231XX_BOARD_CNXT_RDU_250:
1247                 func_mode = 0x03;
1248                 break;
1249         default:
1250                 func_mode = 0x01;
1251         }
1252
1253         status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1254                                                   func_mode, standard);
1255
1256         if (standard == DIF_USE_BASEBAND) {     /* base band */
1257                 /* There is a different SRC_PHASE_INC value
1258                    for baseband vs. DIF */
1259                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1260                 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1261                                                 &dif_misc_ctrl_value);
1262                 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1263                 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1264                                                 dif_misc_ctrl_value);
1265         } else if (standard & V4L2_STD_PAL_D) {
1266                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1267                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1268                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1269                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1270                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1271                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1272                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1273                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1274                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1275                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1276                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1277                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1278                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1279                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1280                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1281                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1282                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1283                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1284                                            0x26001700);
1285                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1286                                            DIF_AGC_RF_CURRENT, 0, 31,
1287                                            0x00002660);
1288                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1289                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1290                                            0x72500800);
1291                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1292                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1293                                            0x27000100);
1294                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1295                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1296                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1297                                            DIF_COMP_FLT_CTRL, 0, 31,
1298                                            0x00000000);
1299                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1300                                            DIF_SRC_PHASE_INC, 0, 31,
1301                                            0x1befbf06);
1302                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1303                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1304                                            0x000035e8);
1305                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1306                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1307                 /* Save the Spec Inversion value */
1308                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1309                 dif_misc_ctrl_value |= 0x3a023F11;
1310         } else if (standard & V4L2_STD_PAL_I) {
1311                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1312                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1313                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1314                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1315                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1316                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1317                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1318                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1319                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1320                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1321                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1322                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1323                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1324                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1325                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1326                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1327                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1328                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1329                                            0x26001700);
1330                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1331                                            DIF_AGC_RF_CURRENT, 0, 31,
1332                                            0x00002660);
1333                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1334                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1335                                            0x72500800);
1336                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1337                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1338                                            0x27000100);
1339                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1340                                            DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1341                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1342                                            DIF_COMP_FLT_CTRL, 0, 31,
1343                                            0x00000000);
1344                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1345                                            DIF_SRC_PHASE_INC, 0, 31,
1346                                            0x1befbf06);
1347                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1348                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1349                                            0x000035e8);
1350                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1351                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1352                 /* Save the Spec Inversion value */
1353                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1354                 dif_misc_ctrl_value |= 0x3a033F11;
1355         } else if (standard & V4L2_STD_PAL_M) {
1356                 /* improved Low Frequency Phase Noise */
1357                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1358                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1359                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1360                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1361                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1362                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1363                                                 0x26001700);
1364                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1365                                                 0x00002660);
1366                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1367                                                 0x72500800);
1368                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1369                                                 0x27000100);
1370                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1371                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1372                                                 0x009f50c1);
1373                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1374                                                 0x1befbf06);
1375                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1376                                                 0x000035e8);
1377                 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1378                                                 0x00000000);
1379                 /* Save the Spec Inversion value */
1380                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1381                 dif_misc_ctrl_value |= 0x3A0A3F10;
1382         } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1383                 /* improved Low Frequency Phase Noise */
1384                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1385                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1386                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1387                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1388                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1389                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1390                                                 0x26001700);
1391                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1392                                                 0x00002660);
1393                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1394                                                 0x72500800);
1395                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1396                                                 0x27000100);
1397                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1398                                                 0x012c405d);
1399                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1400                                                 0x009f50c1);
1401                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1402                                                 0x1befbf06);
1403                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1404                                                 0x000035e8);
1405                 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1406                                                 0x00000000);
1407                 /* Save the Spec Inversion value */
1408                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1409                 dif_misc_ctrl_value = 0x3A093F10;
1410         } else if (standard &
1411                   (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1412                    V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1413
1414                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1415                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1416                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1417                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1418                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1419                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1420                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1421                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1422                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1423                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1424                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1425                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1426                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1427                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1428                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1429                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1430                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1431                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1432                                            0x26001700);
1433                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1434                                            DIF_AGC_RF_CURRENT, 0, 31,
1435                                            0x00002660);
1436                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1437                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1438                                            0x27000100);
1439                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1440                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1441                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1442                                            DIF_COMP_FLT_CTRL, 0, 31,
1443                                            0x00000000);
1444                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1445                                            DIF_SRC_PHASE_INC, 0, 31,
1446                                            0x1befbf06);
1447                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1448                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1449                                            0x000035e8);
1450                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1451                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1452                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1453                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1454                                            0xf4000000);
1455
1456                 /* Save the Spec Inversion value */
1457                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1458                 dif_misc_ctrl_value |= 0x3a023F11;
1459         } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1460                 /* Is it SECAM_L1? */
1461                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1462                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1463                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1464                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1465                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1466                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1467                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1468                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1469                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1470                                            DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1471                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1472                                            DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1473                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1474                                            DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1475                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1476                                            DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1477                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1478                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1479                                            0x26001700);
1480                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1481                                            DIF_AGC_RF_CURRENT, 0, 31,
1482                                            0x00002660);
1483                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1484                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1485                                            0x27000100);
1486                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1487                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1488                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1489                                            DIF_COMP_FLT_CTRL, 0, 31,
1490                                            0x00000000);
1491                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1492                                            DIF_SRC_PHASE_INC, 0, 31,
1493                                            0x1befbf06);
1494                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1495                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1496                                            0x000035e8);
1497                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1498                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1499                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1500                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1501                                            0xf2560000);
1502
1503                 /* Save the Spec Inversion value */
1504                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1505                 dif_misc_ctrl_value |= 0x3a023F11;
1506
1507         } else if (standard & V4L2_STD_NTSC_M) {
1508                 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1509                    V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
1510
1511                 /* For NTSC the centre frequency of video coming out of
1512                    sidewinder is around 7.1MHz or 3.6MHz depending on the
1513                    spectral inversion. so for a non spectrally inverted channel
1514                    the pll freq word is 0x03420c49
1515                  */
1516
1517                 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
1518                 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
1519                 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
1520                 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1521                 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
1522                 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1523                                                 0x26001700);
1524                 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1525                                                 0x00002660);
1526                 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1527                                                 0x04000800);
1528                 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1529                                                 0x27000100);
1530                 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
1531
1532                 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1533                                                 0x009f50c1);
1534                 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1535                                                 0x1befbf06);
1536                 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1537                                                 0x000035e8);
1538
1539                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
1540                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
1541                                                 0xC2262600);
1542                 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
1543
1544                 /* Save the Spec Inversion value */
1545                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1546                 dif_misc_ctrl_value |= 0x3a003F10;
1547         } else {
1548                 /* default PAL BG */
1549                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1550                                            DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1551                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1552                                            DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1553                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1554                                            DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1555                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1556                                            DIF_PLL_CTRL3, 0, 31, 0x00008800);
1557                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1558                                            DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1559                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1560                                            DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1561                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1562                                            DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1563                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1564                                            DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1565                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1566                                            DIF_AGC_IF_INT_CURRENT, 0, 31,
1567                                            0x26001700);
1568                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1569                                            DIF_AGC_RF_CURRENT, 0, 31,
1570                                            0x00002660);
1571                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1572                                            DIF_VIDEO_AGC_CTRL, 0, 31,
1573                                            0x72500800);
1574                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1575                                            DIF_VID_AUD_OVERRIDE, 0, 31,
1576                                            0x27000100);
1577                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1578                                            DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1579                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1580                                            DIF_COMP_FLT_CTRL, 0, 31,
1581                                            0x00A653A8);
1582                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1583                                            DIF_SRC_PHASE_INC, 0, 31,
1584                                            0x1befbf06);
1585                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1586                                            DIF_SRC_GAIN_CONTROL, 0, 31,
1587                                            0x000035e8);
1588                 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1589                                            DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1590                 /* Save the Spec Inversion value */
1591                 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1592                 dif_misc_ctrl_value |= 0x3a013F11;
1593         }
1594
1595         /* The AGC values should be the same for all standards,
1596            AUD_SRC_SEL[19] should always be disabled    */
1597         dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
1598
1599         /* It is still possible to get Set Standard calls even when we
1600            are in FM mode.
1601            This is done to override the value for FM. */
1602         if (dev->active_mode == V4L2_TUNER_RADIO)
1603                 dif_misc_ctrl_value = 0x7a080000;
1604
1605         /* Write the calculated value for misc ontrol register      */
1606         status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
1607
1608         return status;
1609 }
1610
1611 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
1612 {
1613         int status = 0;
1614         u32 dwval;
1615
1616         /* Set the RF and IF k_agc values to 3 */
1617         status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1618         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1619         dwval |= 0x33000000;
1620
1621         status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1622
1623         return status;
1624 }
1625
1626 int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1627 {
1628         int status = 0;
1629         u32 dwval;
1630
1631         /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
1632          * SECAM L/B/D standards */
1633         status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1634         dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1635
1636         if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
1637                          V4L2_STD_SECAM_D))
1638                 dwval |= 0x88000000;
1639         else
1640                 dwval |= 0x44000000;
1641
1642         status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1643
1644         return status;
1645 }
1646
1647 /******************************************************************************
1648  *                  I 2 S - B L O C K    C O N T R O L   functions            *
1649  ******************************************************************************/
1650 int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
1651 {
1652         int status = 0;
1653         u32 value;
1654
1655         status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1656                                        CH_PWR_CTRL1, 1, &value, 1);
1657         /* enables clock to delta-sigma and decimation filter */
1658         value |= 0x80;
1659         status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1660                                         CH_PWR_CTRL1, 1, value, 1);
1661         /* power up all channel */
1662         status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1663                                         CH_PWR_CTRL2, 1, 0x00, 1);
1664
1665         return status;
1666 }
1667
1668 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
1669                                         enum AV_MODE avmode)
1670 {
1671         int status = 0;
1672         u32 value = 0;
1673
1674         if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
1675                 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1676                                           CH_PWR_CTRL2, 1, &value, 1);
1677                 value |= 0xfe;
1678                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1679                                                 CH_PWR_CTRL2, 1, value, 1);
1680         } else {
1681                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1682                                                 CH_PWR_CTRL2, 1, 0x00, 1);
1683         }
1684
1685         return status;
1686 }
1687
1688 /* set i2s_blk for audio input types */
1689 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
1690 {
1691         int status = 0;
1692
1693         switch (audio_input) {
1694         case CX231XX_AMUX_LINE_IN:
1695                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1696                                                 CH_PWR_CTRL2, 1, 0x00, 1);
1697                 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1698                                                 CH_PWR_CTRL1, 1, 0x80, 1);
1699                 break;
1700         case CX231XX_AMUX_VIDEO:
1701         default:
1702                 break;
1703         }
1704
1705         dev->ctl_ainput = audio_input;
1706
1707         return status;
1708 }
1709
1710 /******************************************************************************
1711  *                  P O W E R      C O N T R O L   functions                  *
1712  ******************************************************************************/
1713 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1714 {
1715         u8 value[4] = { 0, 0, 0, 0 };
1716         u32 tmp = 0;
1717         int status = 0;
1718
1719         if (dev->power_mode != mode)
1720                 dev->power_mode = mode;
1721         else {
1722                 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
1723                              mode);
1724                 return 0;
1725         }
1726
1727         cx231xx_info(" setPowerMode::mode = %d\n", mode);
1728
1729         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1730                                        4);
1731         if (status < 0)
1732                 return status;
1733
1734         tmp = *((u32 *) value);
1735
1736         switch (mode) {
1737         case POLARIS_AVMODE_ENXTERNAL_AV:
1738
1739                 tmp &= (~PWR_MODE_MASK);
1740
1741                 tmp |= PWR_AV_EN;
1742                 value[0] = (u8) tmp;
1743                 value[1] = (u8) (tmp >> 8);
1744                 value[2] = (u8) (tmp >> 16);
1745                 value[3] = (u8) (tmp >> 24);
1746                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1747                                                 PWR_CTL_EN, value, 4);
1748                 msleep(PWR_SLEEP_INTERVAL);
1749
1750                 tmp |= PWR_ISO_EN;
1751                 value[0] = (u8) tmp;
1752                 value[1] = (u8) (tmp >> 8);
1753                 value[2] = (u8) (tmp >> 16);
1754                 value[3] = (u8) (tmp >> 24);
1755                 status =
1756                     cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1757                                            value, 4);
1758                 msleep(PWR_SLEEP_INTERVAL);
1759
1760                 tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
1761                 value[0] = (u8) tmp;
1762                 value[1] = (u8) (tmp >> 8);
1763                 value[2] = (u8) (tmp >> 16);
1764                 value[3] = (u8) (tmp >> 24);
1765                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1766                                                 PWR_CTL_EN, value, 4);
1767
1768                 /* reset state of xceive tuner */
1769                 dev->xc_fw_load_done = 0;
1770                 break;
1771
1772         case POLARIS_AVMODE_ANALOGT_TV:
1773
1774                 tmp &= (~PWR_DEMOD_EN);
1775                 tmp |= (I2C_DEMOD_EN);
1776                 value[0] = (u8) tmp;
1777                 value[1] = (u8) (tmp >> 8);
1778                 value[2] = (u8) (tmp >> 16);
1779                 value[3] = (u8) (tmp >> 24);
1780                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1781                                                 PWR_CTL_EN, value, 4);
1782                 msleep(PWR_SLEEP_INTERVAL);
1783
1784                 if (!(tmp & PWR_TUNER_EN)) {
1785                         tmp |= (PWR_TUNER_EN);
1786                         value[0] = (u8) tmp;
1787                         value[1] = (u8) (tmp >> 8);
1788                         value[2] = (u8) (tmp >> 16);
1789                         value[3] = (u8) (tmp >> 24);
1790                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1791                                                         PWR_CTL_EN, value, 4);
1792                         msleep(PWR_SLEEP_INTERVAL);
1793                 }
1794
1795                 if (!(tmp & PWR_AV_EN)) {
1796                         tmp |= PWR_AV_EN;
1797                         value[0] = (u8) tmp;
1798                         value[1] = (u8) (tmp >> 8);
1799                         value[2] = (u8) (tmp >> 16);
1800                         value[3] = (u8) (tmp >> 24);
1801                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1802                                                         PWR_CTL_EN, value, 4);
1803                         msleep(PWR_SLEEP_INTERVAL);
1804                 }
1805                 if (!(tmp & PWR_ISO_EN)) {
1806                         tmp |= PWR_ISO_EN;
1807                         value[0] = (u8) tmp;
1808                         value[1] = (u8) (tmp >> 8);
1809                         value[2] = (u8) (tmp >> 16);
1810                         value[3] = (u8) (tmp >> 24);
1811                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1812                                                         PWR_CTL_EN, value, 4);
1813                         msleep(PWR_SLEEP_INTERVAL);
1814                 }
1815
1816                 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
1817                         tmp |= POLARIS_AVMODE_ANALOGT_TV;
1818                         value[0] = (u8) tmp;
1819                         value[1] = (u8) (tmp >> 8);
1820                         value[2] = (u8) (tmp >> 16);
1821                         value[3] = (u8) (tmp >> 24);
1822                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1823                                                         PWR_CTL_EN, value, 4);
1824                         msleep(PWR_SLEEP_INTERVAL);
1825                 }
1826
1827                 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1828                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1829                         /* tuner path to channel 1 from port 3 */
1830                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1831
1832                         if (dev->cx231xx_reset_analog_tuner)
1833                                 dev->cx231xx_reset_analog_tuner(dev);
1834                 }
1835                 break;
1836
1837         case POLARIS_AVMODE_DIGITAL:
1838                 if (!(tmp & PWR_TUNER_EN)) {
1839                         tmp |= (PWR_TUNER_EN);
1840                         value[0] = (u8) tmp;
1841                         value[1] = (u8) (tmp >> 8);
1842                         value[2] = (u8) (tmp >> 16);
1843                         value[3] = (u8) (tmp >> 24);
1844                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1845                                                         PWR_CTL_EN, value, 4);
1846                         msleep(PWR_SLEEP_INTERVAL);
1847                 }
1848                 if (!(tmp & PWR_AV_EN)) {
1849                         tmp |= PWR_AV_EN;
1850                         value[0] = (u8) tmp;
1851                         value[1] = (u8) (tmp >> 8);
1852                         value[2] = (u8) (tmp >> 16);
1853                         value[3] = (u8) (tmp >> 24);
1854                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1855                                                         PWR_CTL_EN, value, 4);
1856                         msleep(PWR_SLEEP_INTERVAL);
1857                 }
1858                 if (!(tmp & PWR_ISO_EN)) {
1859                         tmp |= PWR_ISO_EN;
1860                         value[0] = (u8) tmp;
1861                         value[1] = (u8) (tmp >> 8);
1862                         value[2] = (u8) (tmp >> 16);
1863                         value[3] = (u8) (tmp >> 24);
1864                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1865                                                         PWR_CTL_EN, value, 4);
1866                         msleep(PWR_SLEEP_INTERVAL);
1867                 }
1868
1869                 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
1870                 value[0] = (u8) tmp;
1871                 value[1] = (u8) (tmp >> 8);
1872                 value[2] = (u8) (tmp >> 16);
1873                 value[3] = (u8) (tmp >> 24);
1874                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1875                                                 PWR_CTL_EN, value, 4);
1876                 msleep(PWR_SLEEP_INTERVAL);
1877
1878                 if (!(tmp & PWR_DEMOD_EN)) {
1879                         tmp |= PWR_DEMOD_EN;
1880                         value[0] = (u8) tmp;
1881                         value[1] = (u8) (tmp >> 8);
1882                         value[2] = (u8) (tmp >> 16);
1883                         value[3] = (u8) (tmp >> 24);
1884                         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1885                                                         PWR_CTL_EN, value, 4);
1886                         msleep(PWR_SLEEP_INTERVAL);
1887                 }
1888
1889                 if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1890                     (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1891                         /* tuner path to channel 1 from port 3 */
1892                         cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1893
1894                         if (dev->cx231xx_reset_analog_tuner)
1895                                 dev->cx231xx_reset_analog_tuner(dev);
1896                 }
1897                 break;
1898
1899         default:
1900                 break;
1901         }
1902
1903         msleep(PWR_SLEEP_INTERVAL);
1904
1905         /* For power saving, only enable Pwr_resetout_n
1906            when digital TV is selected. */
1907         if (mode == POLARIS_AVMODE_DIGITAL) {
1908                 tmp |= PWR_RESETOUT_EN;
1909                 value[0] = (u8) tmp;
1910                 value[1] = (u8) (tmp >> 8);
1911                 value[2] = (u8) (tmp >> 16);
1912                 value[3] = (u8) (tmp >> 24);
1913                 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1914                                                 PWR_CTL_EN, value, 4);
1915                 msleep(PWR_SLEEP_INTERVAL);
1916         }
1917
1918         /* update power control for afe */
1919         status = cx231xx_afe_update_power_control(dev, mode);
1920
1921         /* update power control for i2s_blk */
1922         status = cx231xx_i2s_blk_update_power_control(dev, mode);
1923
1924         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1925                                        4);
1926         cx231xx_info(" The data of PWR_CTL_EN register 0x74"
1927                                  "=0x%0x,0x%0x,0x%0x,0x%0x\n",
1928                      value[0], value[1], value[2], value[3]);
1929
1930         return status;
1931 }
1932
1933 int cx231xx_power_suspend(struct cx231xx *dev)
1934 {
1935         u8 value[4] = { 0, 0, 0, 0 };
1936         u32 tmp = 0;
1937         int status = 0;
1938
1939         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1940                                        value, 4);
1941         if (status > 0)
1942                 return status;
1943
1944         tmp = *((u32 *) value);
1945         tmp &= (~PWR_MODE_MASK);
1946
1947         value[0] = (u8) tmp;
1948         value[1] = (u8) (tmp >> 8);
1949         value[2] = (u8) (tmp >> 16);
1950         value[3] = (u8) (tmp >> 24);
1951         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1952                                         value, 4);
1953
1954         return status;
1955 }
1956
1957 /******************************************************************************
1958  *                  S T R E A M    C O N T R O L   functions                  *
1959  ******************************************************************************/
1960 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
1961 {
1962         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1963         u32 tmp = 0;
1964         int status = 0;
1965
1966         cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
1967         status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1968                                        value, 4);
1969         if (status < 0)
1970                 return status;
1971
1972         tmp = *((u32 *) value);
1973         tmp |= ep_mask;
1974         value[0] = (u8) tmp;
1975         value[1] = (u8) (tmp >> 8);
1976         value[2] = (u8) (tmp >> 16);
1977         value[3] = (u8) (tmp >> 24);
1978
1979         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
1980                                         value, 4);
1981
1982         return status;
1983 }
1984
1985 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
1986 {
1987         u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1988         u32 tmp = 0;
1989         int status = 0;
1990
1991         cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
1992         status =
1993             cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
1994         if (status < 0)
1995                 return status;
1996
1997         tmp = *((u32 *) value);
1998         tmp &= (~ep_mask);
1999         value[0] = (u8) tmp;
2000         value[1] = (u8) (tmp >> 8);
2001         value[2] = (u8) (tmp >> 16);
2002         value[3] = (u8) (tmp >> 24);
2003
2004         status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
2005                                         value, 4);
2006
2007         return status;
2008 }
2009
2010 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2011 {
2012         int status = 0;
2013
2014         if (dev->udev->speed == USB_SPEED_HIGH) {
2015                 switch (media_type) {
2016                 case 81: /* audio */
2017                         cx231xx_info("%s: Audio enter HANC\n", __func__);
2018                         status =
2019                             cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2020                         break;
2021
2022                 case 2: /* vbi */
2023                         cx231xx_info("%s: set vanc registers\n", __func__);
2024                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2025                         break;
2026
2027                 case 3: /* sliced cc */
2028                         cx231xx_info("%s: set hanc registers\n", __func__);
2029                         status =
2030                             cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2031                         break;
2032
2033                 case 0: /* video */
2034                         cx231xx_info("%s: set video registers\n", __func__);
2035                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2036                         break;
2037
2038                 case 4: /* ts1 */
2039                         cx231xx_info("%s: set ts1 registers\n", __func__);
2040                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2041                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2042                         break;
2043                 case 6: /* ts1 parallel mode */
2044                         cx231xx_info("%s: set ts1 parrallel mode registers\n",
2045                                      __func__);
2046                         status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2047                         status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2048                         break;
2049                 }
2050         } else {
2051                 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2052         }
2053
2054         return status;
2055 }
2056
2057 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2058 {
2059         int rc;
2060         u32 ep_mask = -1;
2061         struct pcb_config *pcb_config;
2062
2063         /* get EP for media type */
2064         pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2065
2066         if (pcb_config->config_num == 1) {
2067                 switch (media_type) {
2068                 case 0: /* Video */
2069                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2070                         break;
2071                 case 1: /* Audio */
2072                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2073                         break;
2074                 case 2: /* Vbi */
2075                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2076                         break;
2077                 case 3: /* Sliced_cc */
2078                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2079                         break;
2080                 case 4: /* ts1 */
2081                 case 6: /* ts1 parallel mode */
2082                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2083                         break;
2084                 case 5: /* ts2 */
2085                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2086                         break;
2087                 }
2088
2089         } else if (pcb_config->config_num > 1) {
2090                 switch (media_type) {
2091                 case 0: /* Video */
2092                         ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2093                         break;
2094                 case 1: /* Audio */
2095                         ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2096                         break;
2097                 case 2: /* Vbi */
2098                         ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2099                         break;
2100                 case 3: /* Sliced_cc */
2101                         ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2102                         break;
2103                 case 4: /* ts1 */
2104                 case 6: /* ts1 parallel mode */
2105                         ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2106                         break;
2107                 case 5: /* ts2 */
2108                         ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2109                         break;
2110                 }
2111
2112         }
2113
2114         if (start) {
2115                 rc = cx231xx_initialize_stream_xfer(dev, media_type);
2116
2117                 if (rc < 0)
2118                         return rc;
2119
2120                 /* enable video capture */
2121                 if (ep_mask > 0)
2122                         rc = cx231xx_start_stream(dev, ep_mask);
2123         } else {
2124                 /* disable video capture */
2125                 if (ep_mask > 0)
2126                         rc = cx231xx_stop_stream(dev, ep_mask);
2127         }
2128
2129         if (dev->mode == CX231XX_ANALOG_MODE)
2130                 ;/* do any in Analog mode */
2131         else
2132                 ;/* do any in digital mode */
2133
2134         return rc;
2135 }
2136 EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2137
2138 /*****************************************************************************
2139 *                   G P I O   B I T control functions                        *
2140 ******************************************************************************/
2141 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2142 {
2143         int status = 0;
2144
2145         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2146
2147         return status;
2148 }
2149
2150 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2151 {
2152         int status = 0;
2153
2154         status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2155
2156         return status;
2157 }
2158
2159 /*
2160 * cx231xx_set_gpio_direction
2161 *      Sets the direction of the GPIO pin to input or output
2162 *
2163 * Parameters :
2164 *      pin_number : The GPIO Pin number to program the direction for
2165 *                   from 0 to 31
2166 *      pin_value : The Direction of the GPIO Pin under reference.
2167 *                      0 = Input direction
2168 *                      1 = Output direction
2169 */
2170 int cx231xx_set_gpio_direction(struct cx231xx *dev,
2171                                int pin_number, int pin_value)
2172 {
2173         int status = 0;
2174         u32 value = 0;
2175
2176         /* Check for valid pin_number - if 32 , bail out */
2177         if (pin_number >= 32)
2178                 return -EINVAL;
2179
2180         /* input */
2181         if (pin_value == 0)
2182                 value = dev->gpio_dir & (~(1 << pin_number));   /* clear */
2183         else
2184                 value = dev->gpio_dir | (1 << pin_number);
2185
2186         status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2187
2188         /* cache the value for future */
2189         dev->gpio_dir = value;
2190
2191         return status;
2192 }
2193
2194 /*
2195 * cx231xx_set_gpio_value
2196 *      Sets the value of the GPIO pin to Logic high or low. The Pin under
2197 *      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2198 *
2199 * Parameters :
2200 *      pin_number : The GPIO Pin number to program the direction for
2201 *      pin_value : The value of the GPIO Pin under reference.
2202 *                      0 = set it to 0
2203 *                      1 = set it to 1
2204 */
2205 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2206 {
2207         int status = 0;
2208         u32 value = 0;
2209
2210         /* Check for valid pin_number - if 0xFF , bail out */
2211         if (pin_number >= 32)
2212                 return -EINVAL;
2213
2214         /* first do a sanity check - if the Pin is not output, make it output */
2215         if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2216                 /* It was in input mode */
2217                 value = dev->gpio_dir | (1 << pin_number);
2218                 dev->gpio_dir = value;
2219                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2220                                               (u8 *) &dev->gpio_val);
2221                 value = 0;
2222         }
2223
2224         if (pin_value == 0)
2225                 value = dev->gpio_val & (~(1 << pin_number));
2226         else
2227                 value = dev->gpio_val | (1 << pin_number);
2228
2229         /* store the value */
2230         dev->gpio_val = value;
2231
2232         /* toggle bit0 of GP_IO */
2233         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2234
2235         return status;
2236 }
2237
2238 /*****************************************************************************
2239 *                      G P I O I2C related functions                         *
2240 ******************************************************************************/
2241 int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2242 {
2243         int status = 0;
2244
2245         /* set SCL to output 1 ; set SDA to output 1 */
2246         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2247         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2248         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2249         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2250
2251         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2252         if (status < 0)
2253                 return -EINVAL;
2254
2255         /* set SCL to output 1; set SDA to output 0 */
2256         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2257         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2258
2259         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2260         if (status < 0)
2261                 return -EINVAL;
2262
2263         /* set SCL to output 0; set SDA to output 0      */
2264         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2265         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2266
2267         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2268         if (status < 0)
2269                 return -EINVAL;
2270
2271         return status;
2272 }
2273
2274 int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2275 {
2276         int status = 0;
2277
2278         /* set SCL to output 0; set SDA to output 0      */
2279         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2280         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2281
2282         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2283         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2284
2285         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2286         if (status < 0)
2287                 return -EINVAL;
2288
2289         /* set SCL to output 1; set SDA to output 0      */
2290         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2291         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2292
2293         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2294         if (status < 0)
2295                 return -EINVAL;
2296
2297         /* set SCL to input ,release SCL cable control
2298            set SDA to input ,release SDA cable control */
2299         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2300         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2301
2302         status =
2303             cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2304         if (status < 0)
2305                 return -EINVAL;
2306
2307         return status;
2308 }
2309
2310 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2311 {
2312         int status = 0;
2313         u8 i;
2314
2315         /* set SCL to output ; set SDA to output */
2316         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2317         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2318
2319         for (i = 0; i < 8; i++) {
2320                 if (((data << i) & 0x80) == 0) {
2321                         /* set SCL to output 0; set SDA to output 0     */
2322                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2323                         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2324                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2325                                                       (u8 *)&dev->gpio_val);
2326
2327                         /* set SCL to output 1; set SDA to output 0     */
2328                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2329                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2330                                                       (u8 *)&dev->gpio_val);
2331
2332                         /* set SCL to output 0; set SDA to output 0     */
2333                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2334                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2335                                                       (u8 *)&dev->gpio_val);
2336                 } else {
2337                         /* set SCL to output 0; set SDA to output 1     */
2338                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2339                         dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2340                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2341                                                       (u8 *)&dev->gpio_val);
2342
2343                         /* set SCL to output 1; set SDA to output 1     */
2344                         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2345                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2346                                                       (u8 *)&dev->gpio_val);
2347
2348                         /* set SCL to output 0; set SDA to output 1     */
2349                         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2350                         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2351                                                       (u8 *)&dev->gpio_val);
2352                 }
2353         }
2354         return status;
2355 }
2356
2357 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf)
2358 {
2359         u8 value = 0;
2360         int status = 0;
2361         u32 gpio_logic_value = 0;
2362         u8 i;
2363
2364         /* read byte */
2365         for (i = 0; i < 8; i++) {       /* send write I2c addr */
2366
2367                 /* set SCL to output 0; set SDA to input */
2368                 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2369                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2370                                               (u8 *)&dev->gpio_val);
2371
2372                 /* set SCL to output 1; set SDA to input */
2373                 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2374                 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2375                                               (u8 *)&dev->gpio_val);
2376
2377                 /* get SDA data bit */
2378                 gpio_logic_value = dev->gpio_val;
2379                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2380                                               (u8 *)&dev->gpio_val);
2381                 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2382                         value |= (1 << (8 - i - 1));
2383
2384                 dev->gpio_val = gpio_logic_value;
2385         }
2386
2387         /* set SCL to output 0,finish the read latest SCL signal.
2388            !!!set SDA to input, never to modify SDA direction at
2389            the same times */
2390         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2391         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2392
2393         /* store the value */
2394         *buf = value & 0xff;
2395
2396         return status;
2397 }
2398
2399 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2400 {
2401         int status = 0;
2402         u32 gpio_logic_value = 0;
2403         int nCnt = 10;
2404         int nInit = nCnt;
2405
2406         /* clock stretch; set SCL to input; set SDA to input;
2407            get SCL value till SCL = 1 */
2408         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2409         dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2410
2411         gpio_logic_value = dev->gpio_val;
2412         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2413
2414         do {
2415                 msleep(2);
2416                 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2417                                               (u8 *)&dev->gpio_val);
2418                 nCnt--;
2419         } while (((dev->gpio_val &
2420                           (1 << dev->board.tuner_scl_gpio)) == 0) &&
2421                          (nCnt > 0));
2422
2423         if (nCnt == 0)
2424                 cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2425                              nInit * 10);
2426
2427         /* readAck
2428            throuth clock stretch ,slave has given a SCL signal,
2429            so the SDA data can be directly read.  */
2430         status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2431
2432         if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2433                 dev->gpio_val = gpio_logic_value;
2434                 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2435                 status = 0;
2436         } else {
2437                 dev->gpio_val = gpio_logic_value;
2438                 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2439         }
2440
2441         /* read SDA end, set the SCL to output 0, after this operation,
2442            SDA direction can be changed. */
2443         dev->gpio_val = gpio_logic_value;
2444         dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2445         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2446         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2447
2448         return status;
2449 }
2450
2451 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2452 {
2453         int status = 0;
2454
2455         /* set SDA to ouput */
2456         dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2457         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2458
2459         /* set SCL = 0 (output); set SDA = 0 (output) */
2460         dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2461         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2462         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2463
2464         /* set SCL = 1 (output); set SDA = 0 (output) */
2465         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2466         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2467
2468         /* set SCL = 0 (output); set SDA = 0 (output) */
2469         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2470         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2471
2472         /* set SDA to input,and then the slave will read data from SDA. */
2473         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2474         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2475
2476         return status;
2477 }
2478
2479 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2480 {
2481         int status = 0;
2482
2483         /* set scl to output ; set sda to input */
2484         dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2485         dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2486         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2487
2488         /* set scl to output 0; set sda to input */
2489         dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2490         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2491
2492         /* set scl to output 1; set sda to input */
2493         dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2494         status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2495
2496         return status;
2497 }
2498
2499 /*****************************************************************************
2500 *                      G P I O I2C related functions                         *
2501 ******************************************************************************/
2502 /* cx231xx_gpio_i2c_read
2503  * Function to read data from gpio based I2C interface
2504  */
2505 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2506 {
2507         int status = 0;
2508         int i = 0;
2509
2510         /* get the lock */
2511         mutex_lock(&dev->gpio_i2c_lock);
2512
2513         /* start */
2514         status = cx231xx_gpio_i2c_start(dev);
2515
2516         /* write dev_addr */
2517         status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
2518
2519         /* readAck */
2520         status = cx231xx_gpio_i2c_read_ack(dev);
2521
2522         /* read data */
2523         for (i = 0; i < len; i++) {
2524                 /* read data */
2525                 buf[i] = 0;
2526                 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
2527
2528                 if ((i + 1) != len) {
2529                         /* only do write ack if we more length */
2530                         status = cx231xx_gpio_i2c_write_ack(dev);
2531                 }
2532         }
2533
2534         /* write NAK - inform reads are complete */
2535         status = cx231xx_gpio_i2c_write_nak(dev);
2536
2537         /* write end */
2538         status = cx231xx_gpio_i2c_end(dev);
2539
2540         /* release the lock */
2541         mutex_unlock(&dev->gpio_i2c_lock);
2542
2543         return status;
2544 }
2545
2546 /* cx231xx_gpio_i2c_write
2547  * Function to write data to gpio based I2C interface
2548  */
2549 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2550 {
2551         int status = 0;
2552         int i = 0;
2553
2554         /* get the lock */
2555         mutex_lock(&dev->gpio_i2c_lock);
2556
2557         /* start */
2558         status = cx231xx_gpio_i2c_start(dev);
2559
2560         /* write dev_addr */
2561         status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
2562
2563         /* read Ack */
2564         status = cx231xx_gpio_i2c_read_ack(dev);
2565
2566         for (i = 0; i < len; i++) {
2567                 /* Write data */
2568                 status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
2569
2570                 /* read Ack */
2571                 status = cx231xx_gpio_i2c_read_ack(dev);
2572         }
2573
2574         /* write End */
2575         status = cx231xx_gpio_i2c_end(dev);
2576
2577         /* release the lock */
2578         mutex_unlock(&dev->gpio_i2c_lock);
2579
2580         return 0;
2581 }