drivers/media/dvb/ttpci/budget-ci.c

   1 /*
   2  * budget-ci.c: driver for the SAA7146 based Budget DVB cards
   3  *
   4  * Compiled from various sources by Michael Hunold <michael@mihu.de>
   5  *
   6  *     msp430 IR support contributed by Jack Thomasson <jkt@Helius.COM>
   7  *     partially based on the Siemens DVB driver by Ralph+Marcus Metzler
   8  *
   9  * CI interface support (c) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * as published by the Free Software Foundation; either version 2
  14  * of the License, or (at your option) any later version.
  15  *
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  27  *
  28  *
  29  * the project's page is at http://www.linuxtv.org/dvb/
  30  */
  31
  32 #include <linux/module.h>
  33 #include <linux/errno.h>
  34 #include <linux/slab.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/input.h>
  37 #include <linux/spinlock.h>
  38 #include <media/ir-core.h>
  39
  40 #include "budget.h"
  41
  42 #include "dvb_ca_en50221.h"
  43 #include "stv0299.h"
  44 #include "stv0297.h"
  45 #include "tda1004x.h"
  46 #include "stb0899_drv.h"
  47 #include "stb0899_reg.h"
  48 #include "stb0899_cfg.h"
  49 #include "stb6100.h"
  50 #include "stb6100_cfg.h"
  51 #include "lnbp21.h"
  52 #include "bsbe1.h"
  53 #include "bsru6.h"
  54 #include "tda1002x.h"
  55 #include "tda827x.h"
  56
  57 #define MODULE_NAME "budget_ci"
  58
  59 /*
  60  * Regarding DEBIADDR_IR:
  61  * Some CI modules hang if random addresses are read.
  62  * Using address 0x4000 for the IR read means that we
  63  * use the same address as for CI version, which should
  64  * be a safe default.
  65  */
  66 #define DEBIADDR_IR             0x4000
  67 #define DEBIADDR_CICONTROL      0x0000
  68 #define DEBIADDR_CIVERSION      0x4000
  69 #define DEBIADDR_IO             0x1000
  70 #define DEBIADDR_ATTR           0x3000
  71
  72 #define CICONTROL_RESET         0x01
  73 #define CICONTROL_ENABLETS      0x02
  74 #define CICONTROL_CAMDETECT     0x08
  75
  76 #define DEBICICTL               0x00420000
  77 #define DEBICICAM               0x02420000
  78
  79 #define SLOTSTATUS_NONE         1
  80 #define SLOTSTATUS_PRESENT      2
  81 #define SLOTSTATUS_RESET        4
  82 #define SLOTSTATUS_READY        8
  83 #define SLOTSTATUS_OCCUPIED     (SLOTSTATUS_PRESENT|SLOTSTATUS_RESET|SLOTSTATUS_READY)
  84
  85 /* RC5 device wildcard */
  86 #define IR_DEVICE_ANY           255
  87
  88 static int rc5_device = -1;
  89 module_param(rc5_device, int, 0644);
  90 MODULE_PARM_DESC(rc5_device, "only IR commands to given RC5 device (device = 0 - 31, any device = 255, default: autodetect)");
  91
  92 static int ir_debug;
  93 module_param(ir_debug, int, 0644);
  94 MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
  95
  96 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  97
  98 struct budget_ci_ir {
  99         struct input_dev *dev;
 100         struct tasklet_struct msp430_irq_tasklet;
 101         char name[72]; /* 40 + 32 for (struct saa7146_dev).name */
 102         char phys[32];
 103         int rc5_device;
 104         u32 ir_key;
 105         bool have_command;
 106 };
 107
 108 struct budget_ci {
 109         struct budget budget;
 110         struct tasklet_struct ciintf_irq_tasklet;
 111         int slot_status;
 112         int ci_irq;
 113         struct dvb_ca_en50221 ca;
 114         struct budget_ci_ir ir;
 115         u8 tuner_pll_address; /* used for philips_tdm1316l configs */
 116 };
 117
 118 static void msp430_ir_interrupt(unsigned long data)
 119 {
 120         struct budget_ci *budget_ci = (struct budget_ci *) data;
 121         struct input_dev *dev = budget_ci->ir.dev;
 122         u32 command = ttpci_budget_debiread(&budget_ci->budget, DEBINOSWAP, DEBIADDR_IR, 2, 1, 0) >> 8;
 123
 124         /*
 125          * The msp430 chip can generate two different bytes, command and device
 126          *
 127          * type1: X1CCCCCC, C = command bits (0 - 63)
 128          * type2: X0TDDDDD, D = device bits (0 - 31), T = RC5 toggle bit
 129          *
 130          * Each signal from the remote control can generate one or more command
 131          * bytes and one or more device bytes. For the repeated bytes, the
 132          * highest bit (X) is set. The first command byte is always generated
 133          * before the first device byte. Other than that, no specific order
 134          * seems to apply. To make life interesting, bytes can also be lost.
 135          *
 136          * Only when we have a command and device byte, a keypress is
 137          * generated.
 138          */
 139
 140         if (ir_debug)
 141                 printk("budget_ci: received byte 0x%02x\n", command);
 142
 143         /* Remove repeat bit, we use every command */
 144         command = command & 0x7f;
 145
 146         /* Is this a RC5 command byte? */
 147         if (command & 0x40) {
 148                 budget_ci->ir.have_command = true;
 149                 budget_ci->ir.ir_key = command & 0x3f;
 150                 return;
 151         }
 152
 153         /* It's a RC5 device byte */
 154         if (!budget_ci->ir.have_command)
 155                 return;
 156         budget_ci->ir.have_command = false;
 157
 158         /* FIXME: We should generate complete scancodes with device info */
 159         if (budget_ci->ir.rc5_device != IR_DEVICE_ANY &&
 160             budget_ci->ir.rc5_device != (command & 0x1f))
 161                 return;
 162
 163         ir_keydown(dev, budget_ci->ir.ir_key, (command & 0x20) ? 1 : 0);
 164 }
 165
 166 static int msp430_ir_init(struct budget_ci *budget_ci)
 167 {
 168         struct saa7146_dev *saa = budget_ci->budget.dev;
 169         struct input_dev *input_dev = budget_ci->ir.dev;
 170         int error;
 171         char *ir_codes = NULL;
 172
 173
 174         budget_ci->ir.dev = input_dev = input_allocate_device();
 175         if (!input_dev) {
 176                 printk(KERN_ERR "budget_ci: IR interface initialisation failed\n");
 177                 return -ENOMEM;
 178         }
 179
 180         snprintf(budget_ci->ir.name, sizeof(budget_ci->ir.name),
 181                  "Budget-CI dvb ir receiver %s", saa->name);
 182         snprintf(budget_ci->ir.phys, sizeof(budget_ci->ir.phys),
 183                  "pci-%s/ir0", pci_name(saa->pci));
 184
 185         input_dev->name = budget_ci->ir.name;
 186
 187         input_dev->phys = budget_ci->ir.phys;
 188         input_dev->id.bustype = BUS_PCI;
 189         input_dev->id.version = 1;
 190         if (saa->pci->subsystem_vendor) {
 191                 input_dev->id.vendor = saa->pci->subsystem_vendor;
 192                 input_dev->id.product = saa->pci->subsystem_device;
 193         } else {
 194                 input_dev->id.vendor = saa->pci->vendor;
 195                 input_dev->id.product = saa->pci->device;
 196         }
 197         input_dev->dev.parent = &saa->pci->dev;
 198
 199         if (rc5_device < 0)
 200                 budget_ci->ir.rc5_device = IR_DEVICE_ANY;
 201         else
 202                 budget_ci->ir.rc5_device = rc5_device;
 203
 204         /* Select keymap and address */
 205         switch (budget_ci->budget.dev->pci->subsystem_device) {
 206         case 0x100c:
 207         case 0x100f:
 208         case 0x1011:
 209         case 0x1012:
 210                 /* The hauppauge keymap is a superset of these remotes */
 211                 ir_codes = RC_MAP_HAUPPAUGE_NEW;
 212
 213                 if (rc5_device < 0)
 214                         budget_ci->ir.rc5_device = 0x1f;
 215                 break;
 216         case 0x1010:
 217         case 0x1017:
 218         case 0x1019:
 219         case 0x101a:
 220                 /* for the Technotrend 1500 bundled remote */
 221                 ir_codes = RC_MAP_TT_1500;
 222                 break;
 223         default:
 224                 /* unknown remote */
 225                 ir_codes = RC_MAP_BUDGET_CI_OLD;
 226                 break;
 227         }
 228
 229         error = ir_input_register(input_dev, ir_codes, NULL, MODULE_NAME);
 230         if (error) {
 231                 printk(KERN_ERR "budget_ci: could not init driver for IR device (code %d)\n", error);
 232                 return error;
 233         }
 234
 235         /* note: these must be after input_register_device */
 236         input_dev->rep[REP_DELAY] = 400;
 237         input_dev->rep[REP_PERIOD] = 250;
 238
 239         tasklet_init(&budget_ci->ir.msp430_irq_tasklet, msp430_ir_interrupt,
 240                      (unsigned long) budget_ci);
 241
 242         SAA7146_IER_ENABLE(saa, MASK_06);
 243         saa7146_setgpio(saa, 3, SAA7146_GPIO_IRQHI);
 244
 245         return 0;
 246 }
 247
 248 static void msp430_ir_deinit(struct budget_ci *budget_ci)
 249 {
 250         struct saa7146_dev *saa = budget_ci->budget.dev;
 251         struct input_dev *dev = budget_ci->ir.dev;
 252
 253         SAA7146_IER_DISABLE(saa, MASK_06);
 254         saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT);
 255         tasklet_kill(&budget_ci->ir.msp430_irq_tasklet);
 256
 257         ir_input_unregister(dev);
 258 }
 259
 260 static int ciintf_read_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address)
 261 {
 262         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 263
 264         if (slot != 0)
 265                 return -EINVAL;
 266
 267         return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM,
 268                                      DEBIADDR_ATTR | (address & 0xfff), 1, 1, 0);
 269 }
 270
 271 static int ciintf_write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address, u8 value)
 272 {
 273         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 274
 275         if (slot != 0)
 276                 return -EINVAL;
 277
 278         return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM,
 279                                       DEBIADDR_ATTR | (address & 0xfff), 1, value, 1, 0);
 280 }
 281
 282 static int ciintf_read_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address)
 283 {
 284         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 285
 286         if (slot != 0)
 287                 return -EINVAL;
 288
 289         return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM,
 290                                      DEBIADDR_IO | (address & 3), 1, 1, 0);
 291 }
 292
 293 static int ciintf_write_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address, u8 value)
 294 {
 295         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 296
 297         if (slot != 0)
 298                 return -EINVAL;
 299
 300         return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM,
 301                                       DEBIADDR_IO | (address & 3), 1, value, 1, 0);
 302 }
 303
 304 static int ciintf_slot_reset(struct dvb_ca_en50221 *ca, int slot)
 305 {
 306         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 307         struct saa7146_dev *saa = budget_ci->budget.dev;
 308
 309         if (slot != 0)
 310                 return -EINVAL;
 311
 312         if (budget_ci->ci_irq) {
 313                 // trigger on RISING edge during reset so we know when READY is re-asserted
 314                 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
 315         }
 316         budget_ci->slot_status = SLOTSTATUS_RESET;
 317         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0);
 318         msleep(1);
 319         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
 320                                CICONTROL_RESET, 1, 0);
 321
 322         saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI);
 323         ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
 324         return 0;
 325 }
 326
 327 static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
 328 {
 329         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 330         struct saa7146_dev *saa = budget_ci->budget.dev;
 331
 332         if (slot != 0)
 333                 return -EINVAL;
 334
 335         saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI);
 336         ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
 337         return 0;
 338 }
 339
 340 static int ciintf_slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
 341 {
 342         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 343         struct saa7146_dev *saa = budget_ci->budget.dev;
 344         int tmp;
 345
 346         if (slot != 0)
 347                 return -EINVAL;
 348
 349         saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTLO);
 350
 351         tmp = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
 352         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
 353                                tmp | CICONTROL_ENABLETS, 1, 0);
 354
 355         ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTA);
 356         return 0;
 357 }
 358
 359 static void ciintf_interrupt(unsigned long data)
 360 {
 361         struct budget_ci *budget_ci = (struct budget_ci *) data;
 362         struct saa7146_dev *saa = budget_ci->budget.dev;
 363         unsigned int flags;
 364
 365         // ensure we don't get spurious IRQs during initialisation
 366         if (!budget_ci->budget.ci_present)
 367                 return;
 368
 369         // read the CAM status
 370         flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
 371         if (flags & CICONTROL_CAMDETECT) {
 372
 373                 // GPIO should be set to trigger on falling edge if a CAM is present
 374                 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO);
 375
 376                 if (budget_ci->slot_status & SLOTSTATUS_NONE) {
 377                         // CAM insertion IRQ
 378                         budget_ci->slot_status = SLOTSTATUS_PRESENT;
 379                         dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0,
 380                                                      DVB_CA_EN50221_CAMCHANGE_INSERTED);
 381
 382                 } else if (budget_ci->slot_status & SLOTSTATUS_RESET) {
 383                         // CAM ready (reset completed)
 384                         budget_ci->slot_status = SLOTSTATUS_READY;
 385                         dvb_ca_en50221_camready_irq(&budget_ci->ca, 0);
 386
 387                 } else if (budget_ci->slot_status & SLOTSTATUS_READY) {
 388                         // FR/DA IRQ
 389                         dvb_ca_en50221_frda_irq(&budget_ci->ca, 0);
 390                 }
 391         } else {
 392
 393                 // trigger on rising edge if a CAM is not present - when a CAM is inserted, we
 394                 // only want to get the IRQ when it sets READY. If we trigger on the falling edge,
 395                 // the CAM might not actually be ready yet.
 396                 saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
 397
 398                 // generate a CAM removal IRQ if we haven't already
 399                 if (budget_ci->slot_status & SLOTSTATUS_OCCUPIED) {
 400                         // CAM removal IRQ
 401                         budget_ci->slot_status = SLOTSTATUS_NONE;
 402                         dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0,
 403                                                      DVB_CA_EN50221_CAMCHANGE_REMOVED);
 404                 }
 405         }
 406 }
 407
 408 static int ciintf_poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
 409 {
 410         struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
 411         unsigned int flags;
 412
 413         // ensure we don't get spurious IRQs during initialisation
 414         if (!budget_ci->budget.ci_present)
 415                 return -EINVAL;
 416
 417         // read the CAM status
 418         flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
 419         if (flags & CICONTROL_CAMDETECT) {
 420                 // mark it as present if it wasn't before
 421                 if (budget_ci->slot_status & SLOTSTATUS_NONE) {
 422                         budget_ci->slot_status = SLOTSTATUS_PRESENT;
 423                 }
 424
 425                 // during a RESET, we check if we can read from IO memory to see when CAM is ready
 426                 if (budget_ci->slot_status & SLOTSTATUS_RESET) {
 427                         if (ciintf_read_attribute_mem(ca, slot, 0) == 0x1d) {
 428                                 budget_ci->slot_status = SLOTSTATUS_READY;
 429                         }
 430                 }
 431         } else {
 432                 budget_ci->slot_status = SLOTSTATUS_NONE;
 433         }
 434
 435         if (budget_ci->slot_status != SLOTSTATUS_NONE) {
 436                 if (budget_ci->slot_status & SLOTSTATUS_READY) {
 437                         return DVB_CA_EN50221_POLL_CAM_PRESENT | DVB_CA_EN50221_POLL_CAM_READY;
 438                 }
 439                 return DVB_CA_EN50221_POLL_CAM_PRESENT;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int ciintf_init(struct budget_ci *budget_ci)
 446 {
 447         struct saa7146_dev *saa = budget_ci->budget.dev;
 448         int flags;
 449         int result;
 450         int ci_version;
 451         int ca_flags;
 452
 453         memset(&budget_ci->ca, 0, sizeof(struct dvb_ca_en50221));
 454
 455         // enable DEBI pins
 456         saa7146_write(saa, MC1, MASK_27 | MASK_11);
 457
 458         // test if it is there
 459         ci_version = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CIVERSION, 1, 1, 0);
 460         if ((ci_version & 0xa0) != 0xa0) {
 461                 result = -ENODEV;
 462                 goto error;
 463         }
 464
 465         // determine whether a CAM is present or not
 466         flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
 467         budget_ci->slot_status = SLOTSTATUS_NONE;
 468         if (flags & CICONTROL_CAMDETECT)
 469                 budget_ci->slot_status = SLOTSTATUS_PRESENT;
 470
 471         // version 0xa2 of the CI firmware doesn't generate interrupts
 472         if (ci_version == 0xa2) {
 473                 ca_flags = 0;
 474                 budget_ci->ci_irq = 0;
 475         } else {
 476                 ca_flags = DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE |
 477                                 DVB_CA_EN50221_FLAG_IRQ_FR |
 478                                 DVB_CA_EN50221_FLAG_IRQ_DA;
 479                 budget_ci->ci_irq = 1;
 480         }
 481
 482         // register CI interface
 483         budget_ci->ca.owner = THIS_MODULE;
 484         budget_ci->ca.read_attribute_mem = ciintf_read_attribute_mem;
 485         budget_ci->ca.write_attribute_mem = ciintf_write_attribute_mem;
 486         budget_ci->ca.read_cam_control = ciintf_read_cam_control;
 487         budget_ci->ca.write_cam_control = ciintf_write_cam_control;
 488         budget_ci->ca.slot_reset = ciintf_slot_reset;
 489         budget_ci->ca.slot_shutdown = ciintf_slot_shutdown;
 490         budget_ci->ca.slot_ts_enable = ciintf_slot_ts_enable;
 491         budget_ci->ca.poll_slot_status = ciintf_poll_slot_status;
 492         budget_ci->ca.data = budget_ci;
 493         if ((result = dvb_ca_en50221_init(&budget_ci->budget.dvb_adapter,
 494                                           &budget_ci->ca,
 495                                           ca_flags, 1)) != 0) {
 496                 printk("budget_ci: CI interface detected, but initialisation failed.\n");
 497                 goto error;
 498         }
 499
 500         // Setup CI slot IRQ
 501         if (budget_ci->ci_irq) {
 502                 tasklet_init(&budget_ci->ciintf_irq_tasklet, ciintf_interrupt, (unsigned long) budget_ci);
 503                 if (budget_ci->slot_status != SLOTSTATUS_NONE) {
 504                         saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO);
 505                 } else {
 506                         saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
 507                 }
 508                 SAA7146_IER_ENABLE(saa, MASK_03);
 509         }
 510
 511         // enable interface
 512         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
 513                                CICONTROL_RESET, 1, 0);
 514
 515         // success!
 516         printk("budget_ci: CI interface initialised\n");
 517         budget_ci->budget.ci_present = 1;
 518
 519         // forge a fake CI IRQ so the CAM state is setup correctly
 520         if (budget_ci->ci_irq) {
 521                 flags = DVB_CA_EN50221_CAMCHANGE_REMOVED;
 522                 if (budget_ci->slot_status != SLOTSTATUS_NONE)
 523                         flags = DVB_CA_EN50221_CAMCHANGE_INSERTED;
 524                 dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, flags);
 525         }
 526
 527         return 0;
 528
 529 error:
 530         saa7146_write(saa, MC1, MASK_27);
 531         return result;
 532 }
 533
 534 static void ciintf_deinit(struct budget_ci *budget_ci)
 535 {
 536         struct saa7146_dev *saa = budget_ci->budget.dev;
 537
 538         // disable CI interrupts
 539         if (budget_ci->ci_irq) {
 540                 SAA7146_IER_DISABLE(saa, MASK_03);
 541                 saa7146_setgpio(saa, 0, SAA7146_GPIO_INPUT);
 542                 tasklet_kill(&budget_ci->ciintf_irq_tasklet);
 543         }
 544
 545         // reset interface
 546         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0);
 547         msleep(1);
 548         ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
 549                                CICONTROL_RESET, 1, 0);
 550
 551         // disable TS data stream to CI interface
 552         saa7146_setgpio(saa, 1, SAA7146_GPIO_INPUT);
 553
 554         // release the CA device
 555         dvb_ca_en50221_release(&budget_ci->ca);
 556
 557         // disable DEBI pins
 558         saa7146_write(saa, MC1, MASK_27);
 559 }
 560
 561 static void budget_ci_irq(struct saa7146_dev *dev, u32 * isr)
 562 {
 563         struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv;
 564
 565         dprintk(8, "dev: %p, budget_ci: %p\n", dev, budget_ci);
 566
 567         if (*isr & MASK_06)
 568                 tasklet_schedule(&budget_ci->ir.msp430_irq_tasklet);
 569
 570         if (*isr & MASK_10)
 571                 ttpci_budget_irq10_handler(dev, isr);
 572
 573         if ((*isr & MASK_03) && (budget_ci->budget.ci_present) && (budget_ci->ci_irq))
 574                 tasklet_schedule(&budget_ci->ciintf_irq_tasklet);
 575 }
 576
 577 static u8 philips_su1278_tt_inittab[] = {
 578         0x01, 0x0f,
 579         0x02, 0x30,
 580         0x03, 0x00,
 581         0x04, 0x5b,
 582         0x05, 0x85,
 583         0x06, 0x02,
 584         0x07, 0x00,
 585         0x08, 0x02,
 586         0x09, 0x00,
 587         0x0C, 0x01,
 588         0x0D, 0x81,
 589         0x0E, 0x44,
 590         0x0f, 0x14,
 591         0x10, 0x3c,
 592         0x11, 0x84,
 593         0x12, 0xda,
 594         0x13, 0x97,
 595         0x14, 0x95,
 596         0x15, 0xc9,
 597         0x16, 0x19,
 598         0x17, 0x8c,
 599         0x18, 0x59,
 600         0x19, 0xf8,
 601         0x1a, 0xfe,
 602         0x1c, 0x7f,
 603         0x1d, 0x00,
 604         0x1e, 0x00,
 605         0x1f, 0x50,
 606         0x20, 0x00,
 607         0x21, 0x00,
 608         0x22, 0x00,
 609         0x23, 0x00,
 610         0x28, 0x00,
 611         0x29, 0x28,
 612         0x2a, 0x14,
 613         0x2b, 0x0f,
 614         0x2c, 0x09,
 615         0x2d, 0x09,
 616         0x31, 0x1f,
 617         0x32, 0x19,
 618         0x33, 0xfc,
 619         0x34, 0x93,
 620         0xff, 0xff
 621 };
 622
 623 static int philips_su1278_tt_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio)
 624 {
 625         stv0299_writereg(fe, 0x0e, 0x44);
 626         if (srate >= 10000000) {
 627                 stv0299_writereg(fe, 0x13, 0x97);
 628                 stv0299_writereg(fe, 0x14, 0x95);
 629                 stv0299_writereg(fe, 0x15, 0xc9);
 630                 stv0299_writereg(fe, 0x17, 0x8c);
 631                 stv0299_writereg(fe, 0x1a, 0xfe);
 632                 stv0299_writereg(fe, 0x1c, 0x7f);
 633                 stv0299_writereg(fe, 0x2d, 0x09);
 634         } else {
 635                 stv0299_writereg(fe, 0x13, 0x99);
 636                 stv0299_writereg(fe, 0x14, 0x8d);
 637                 stv0299_writereg(fe, 0x15, 0xce);
 638                 stv0299_writereg(fe, 0x17, 0x43);
 639                 stv0299_writereg(fe, 0x1a, 0x1d);
 640                 stv0299_writereg(fe, 0x1c, 0x12);
 641                 stv0299_writereg(fe, 0x2d, 0x05);
 642         }
 643         stv0299_writereg(fe, 0x0e, 0x23);
 644         stv0299_writereg(fe, 0x0f, 0x94);
 645         stv0299_writereg(fe, 0x10, 0x39);
 646         stv0299_writereg(fe, 0x15, 0xc9);
 647
 648         stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
 649         stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
 650         stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
 651
 652         return 0;
 653 }
 654
 655 static int philips_su1278_tt_tuner_set_params(struct dvb_frontend *fe,
 656                                            struct dvb_frontend_parameters *params)
 657 {
 658         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 659         u32 div;
 660         u8 buf[4];
 661         struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = buf,.len = sizeof(buf) };
 662
 663         if ((params->frequency < 950000) || (params->frequency > 2150000))
 664                 return -EINVAL;
 665
 666         div = (params->frequency + (500 - 1)) / 500;    // round correctly
 667         buf[0] = (div >> 8) & 0x7f;
 668         buf[1] = div & 0xff;
 669         buf[2] = 0x80 | ((div & 0x18000) >> 10) | 2;
 670         buf[3] = 0x20;
 671
 672         if (params->u.qpsk.symbol_rate < 4000000)
 673                 buf[3] |= 1;
 674
 675         if (params->frequency < 1250000)
 676                 buf[3] |= 0;
 677         else if (params->frequency < 1550000)
 678                 buf[3] |= 0x40;
 679         else if (params->frequency < 2050000)
 680                 buf[3] |= 0x80;
 681         else if (params->frequency < 2150000)
 682                 buf[3] |= 0xC0;
 683
 684         if (fe->ops.i2c_gate_ctrl)
 685                 fe->ops.i2c_gate_ctrl(fe, 1);
 686         if (i2c_transfer(&budget_ci->budget.i2c_adap, &msg, 1) != 1)
 687                 return -EIO;
 688         return 0;
 689 }
 690
 691 static struct stv0299_config philips_su1278_tt_config = {
 692
 693         .demod_address = 0x68,
 694         .inittab = philips_su1278_tt_inittab,
 695         .mclk = 64000000UL,
 696         .invert = 0,
 697         .skip_reinit = 1,
 698         .lock_output = STV0299_LOCKOUTPUT_1,
 699         .volt13_op0_op1 = STV0299_VOLT13_OP1,
 700         .min_delay_ms = 50,
 701         .set_symbol_rate = philips_su1278_tt_set_symbol_rate,
 702 };
 703
 704
 705
 706 static int philips_tdm1316l_tuner_init(struct dvb_frontend *fe)
 707 {
 708         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 709         static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
 710         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 711         struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = td1316_init,.len =
 712                         sizeof(td1316_init) };
 713
 714         // setup PLL configuration
 715         if (fe->ops.i2c_gate_ctrl)
 716                 fe->ops.i2c_gate_ctrl(fe, 1);
 717         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
 718                 return -EIO;
 719         msleep(1);
 720
 721         // disable the mc44BC374c (do not check for errors)
 722         tuner_msg.addr = 0x65;
 723         tuner_msg.buf = disable_mc44BC374c;
 724         tuner_msg.len = sizeof(disable_mc44BC374c);
 725         if (fe->ops.i2c_gate_ctrl)
 726                 fe->ops.i2c_gate_ctrl(fe, 1);
 727         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) {
 728                 if (fe->ops.i2c_gate_ctrl)
 729                         fe->ops.i2c_gate_ctrl(fe, 1);
 730                 i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1);
 731         }
 732
 733         return 0;
 734 }
 735
 736 static int philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
 737 {
 738         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 739         u8 tuner_buf[4];
 740         struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = tuner_buf,.len = sizeof(tuner_buf) };
 741         int tuner_frequency = 0;
 742         u8 band, cp, filter;
 743
 744         // determine charge pump
 745         tuner_frequency = params->frequency + 36130000;
 746         if (tuner_frequency < 87000000)
 747                 return -EINVAL;
 748         else if (tuner_frequency < 130000000)
 749                 cp = 3;
 750         else if (tuner_frequency < 160000000)
 751                 cp = 5;
 752         else if (tuner_frequency < 200000000)
 753                 cp = 6;
 754         else if (tuner_frequency < 290000000)
 755                 cp = 3;
 756         else if (tuner_frequency < 420000000)
 757                 cp = 5;
 758         else if (tuner_frequency < 480000000)
 759                 cp = 6;
 760         else if (tuner_frequency < 620000000)
 761                 cp = 3;
 762         else if (tuner_frequency < 830000000)
 763                 cp = 5;
 764         else if (tuner_frequency < 895000000)
 765                 cp = 7;
 766         else
 767                 return -EINVAL;
 768
 769         // determine band
 770         if (params->frequency < 49000000)
 771                 return -EINVAL;
 772         else if (params->frequency < 159000000)
 773                 band = 1;
 774         else if (params->frequency < 444000000)
 775                 band = 2;
 776         else if (params->frequency < 861000000)
 777                 band = 4;
 778         else
 779                 return -EINVAL;
 780
 781         // setup PLL filter and TDA9889
 782         switch (params->u.ofdm.bandwidth) {
 783         case BANDWIDTH_6_MHZ:
 784                 tda1004x_writereg(fe, 0x0C, 0x14);
 785                 filter = 0;
 786                 break;
 787
 788         case BANDWIDTH_7_MHZ:
 789                 tda1004x_writereg(fe, 0x0C, 0x80);
 790                 filter = 0;
 791                 break;
 792
 793         case BANDWIDTH_8_MHZ:
 794                 tda1004x_writereg(fe, 0x0C, 0x14);
 795                 filter = 1;
 796                 break;
 797
 798         default:
 799                 return -EINVAL;
 800         }
 801
 802         // calculate divisor
 803         // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
 804         tuner_frequency = (((params->frequency / 1000) * 6) + 217280) / 1000;
 805
 806         // setup tuner buffer
 807         tuner_buf[0] = tuner_frequency >> 8;
 808         tuner_buf[1] = tuner_frequency & 0xff;
 809         tuner_buf[2] = 0xca;
 810         tuner_buf[3] = (cp << 5) | (filter << 3) | band;
 811
 812         if (fe->ops.i2c_gate_ctrl)
 813                 fe->ops.i2c_gate_ctrl(fe, 1);
 814         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
 815                 return -EIO;
 816
 817         msleep(1);
 818         return 0;
 819 }
 820
 821 static int philips_tdm1316l_request_firmware(struct dvb_frontend *fe,
 822                                              const struct firmware **fw, char *name)
 823 {
 824         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 825
 826         return request_firmware(fw, name, &budget_ci->budget.dev->pci->dev);
 827 }
 828
 829 static struct tda1004x_config philips_tdm1316l_config = {
 830
 831         .demod_address = 0x8,
 832         .invert = 0,
 833         .invert_oclk = 0,
 834         .xtal_freq = TDA10046_XTAL_4M,
 835         .agc_config = TDA10046_AGC_DEFAULT,
 836         .if_freq = TDA10046_FREQ_3617,
 837         .request_firmware = philips_tdm1316l_request_firmware,
 838 };
 839
 840 static struct tda1004x_config philips_tdm1316l_config_invert = {
 841
 842         .demod_address = 0x8,
 843         .invert = 1,
 844         .invert_oclk = 0,
 845         .xtal_freq = TDA10046_XTAL_4M,
 846         .agc_config = TDA10046_AGC_DEFAULT,
 847         .if_freq = TDA10046_FREQ_3617,
 848         .request_firmware = philips_tdm1316l_request_firmware,
 849 };
 850
 851 static int dvbc_philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
 852 {
 853         struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
 854         u8 tuner_buf[5];
 855         struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,
 856                                     .flags = 0,
 857                                     .buf = tuner_buf,
 858                                     .len = sizeof(tuner_buf) };
 859         int tuner_frequency = 0;
 860         u8 band, cp, filter;
 861
 862         // determine charge pump
 863         tuner_frequency = params->frequency + 36125000;
 864         if (tuner_frequency < 87000000)
 865                 return -EINVAL;
 866         else if (tuner_frequency < 130000000) {
 867                 cp = 3;
 868                 band = 1;
 869         } else if (tuner_frequency < 160000000) {
 870                 cp = 5;
 871                 band = 1;
 872         } else if (tuner_frequency < 200000000) {
 873                 cp = 6;
 874                 band = 1;
 875         } else if (tuner_frequency < 290000000) {
 876                 cp = 3;
 877                 band = 2;
 878         } else if (tuner_frequency < 420000000) {
 879                 cp = 5;
 880                 band = 2;
 881         } else if (tuner_frequency < 480000000) {
 882                 cp = 6;
 883                 band = 2;
 884         } else if (tuner_frequency < 620000000) {
 885                 cp = 3;
 886                 band = 4;
 887         } else if (tuner_frequency < 830000000) {
 888                 cp = 5;
 889                 band = 4;
 890         } else if (tuner_frequency < 895000000) {
 891                 cp = 7;
 892                 band = 4;
 893         } else
 894                 return -EINVAL;
 895
 896         // assume PLL filter should always be 8MHz for the moment.
 897         filter = 1;
 898
 899         // calculate divisor
 900         tuner_frequency = (params->frequency + 36125000 + (62500/2)) / 62500;
 901
 902         // setup tuner buffer
 903         tuner_buf[0] = tuner_frequency >> 8;
 904         tuner_buf[1] = tuner_frequency & 0xff;
 905         tuner_buf[2] = 0xc8;
 906         tuner_buf[3] = (cp << 5) | (filter << 3) | band;
 907         tuner_buf[4] = 0x80;
 908
 909         if (fe->ops.i2c_gate_ctrl)
 910                 fe->ops.i2c_gate_ctrl(fe, 1);
 911         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
 912                 return -EIO;
 913
 914         msleep(50);
 915
 916         if (fe->ops.i2c_gate_ctrl)
 917                 fe->ops.i2c_gate_ctrl(fe, 1);
 918         if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
 919                 return -EIO;
 920
 921         msleep(1);
 922
 923         return 0;
 924 }
 925
 926 static u8 dvbc_philips_tdm1316l_inittab[] = {
 927         0x80, 0x01,
 928         0x80, 0x00,
 929         0x81, 0x01,
 930         0x81, 0x00,
 931         0x00, 0x09,
 932         0x01, 0x69,
 933         0x03, 0x00,
 934         0x04, 0x00,
 935         0x07, 0x00,
 936         0x08, 0x00,
 937         0x20, 0x00,
 938         0x21, 0x40,
 939         0x22, 0x00,
 940         0x23, 0x00,
 941         0x24, 0x40,
 942         0x25, 0x88,
 943         0x30, 0xff,
 944         0x31, 0x00,
 945         0x32, 0xff,
 946         0x33, 0x00,
 947         0x34, 0x50,
 948         0x35, 0x7f,
 949         0x36, 0x00,
 950         0x37, 0x20,
 951         0x38, 0x00,
 952         0x40, 0x1c,
 953         0x41, 0xff,
 954         0x42, 0x29,
 955         0x43, 0x20,
 956         0x44, 0xff,
 957         0x45, 0x00,
 958         0x46, 0x00,
 959         0x49, 0x04,
 960         0x4a, 0x00,
 961         0x4b, 0x7b,
 962         0x52, 0x30,
 963         0x55, 0xae,
 964         0x56, 0x47,
 965         0x57, 0xe1,
 966         0x58, 0x3a,
 967         0x5a, 0x1e,
 968         0x5b, 0x34,
 969         0x60, 0x00,
 970         0x63, 0x00,
 971         0x64, 0x00,
 972         0x65, 0x00,
 973         0x66, 0x00,
 974         0x67, 0x00,
 975         0x68, 0x00,
 976         0x69, 0x00,
 977         0x6a, 0x02,
 978         0x6b, 0x00,
 979         0x70, 0xff,
 980         0x71, 0x00,
 981         0x72, 0x00,
 982         0x73, 0x00,
 983         0x74, 0x0c,
 984         0x80, 0x00,
 985         0x81, 0x00,
 986         0x82, 0x00,
 987         0x83, 0x00,
 988         0x84, 0x04,
 989         0x85, 0x80,
 990         0x86, 0x24,
 991         0x87, 0x78,
 992         0x88, 0x10,
 993         0x89, 0x00,
 994         0x90, 0x01,
 995         0x91, 0x01,
 996         0xa0, 0x04,
 997         0xa1, 0x00,
 998         0xa2, 0x00,
 999         0xb0, 0x91,
1000         0xb1, 0x0b,
1001         0xc0, 0x53,
1002         0xc1, 0x70,
1003         0xc2, 0x12,
1004         0xd0, 0x00,
1005         0xd1, 0x00,
1006         0xd2, 0x00,
1007         0xd3, 0x00,
1008         0xd4, 0x00,
1009         0xd5, 0x00,
1010         0xde, 0x00,
1011         0xdf, 0x00,
1012         0x61, 0x38,
1013         0x62, 0x0a,
1014         0x53, 0x13,
1015         0x59, 0x08,
1016         0xff, 0xff,
1017 };
1018
1019 static struct stv0297_config dvbc_philips_tdm1316l_config = {
1020         .demod_address = 0x1c,
1021         .inittab = dvbc_philips_tdm1316l_inittab,
1022         .invert = 0,
1023         .stop_during_read = 1,
1024 };
1025
1026 static struct tda10023_config tda10023_config = {
1027         .demod_address = 0xc,
1028         .invert = 0,
1029         .xtal = 16000000,
1030         .pll_m = 11,
1031         .pll_p = 3,
1032         .pll_n = 1,
1033         .deltaf = 0xa511,
1034 };
1035
1036 static struct tda827x_config tda827x_config = {
1037         .config = 0,
1038 };
1039
1040 /* TT S2-3200 DVB-S (STB0899) Inittab */
1041 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = {
1042
1043         { STB0899_DEV_ID                , 0x81 },
1044         { STB0899_DISCNTRL1             , 0x32 },
1045         { STB0899_DISCNTRL2             , 0x80 },
1046         { STB0899_DISRX_ST0             , 0x04 },
1047         { STB0899_DISRX_ST1             , 0x00 },
1048         { STB0899_DISPARITY             , 0x00 },
1049         { STB0899_DISFIFO               , 0x00 },
1050         { STB0899_DISSTATUS             , 0x20 },
1051         { STB0899_DISF22                , 0x8c },
1052         { STB0899_DISF22RX              , 0x9a },
1053         { STB0899_SYSREG                , 0x0b },
1054         { STB0899_ACRPRESC              , 0x11 },
1055         { STB0899_ACRDIV1               , 0x0a },
1056         { STB0899_ACRDIV2               , 0x05 },
1057         { STB0899_DACR1                 , 0x00 },
1058         { STB0899_DACR2                 , 0x00 },
1059         { STB0899_OUTCFG                , 0x00 },
1060         { STB0899_MODECFG               , 0x00 },
1061         { STB0899_IRQSTATUS_3           , 0x30 },
1062         { STB0899_IRQSTATUS_2           , 0x00 },
1063         { STB0899_IRQSTATUS_1           , 0x00 },
1064         { STB0899_IRQSTATUS_0           , 0x00 },
1065         { STB0899_IRQMSK_3              , 0xf3 },
1066         { STB0899_IRQMSK_2              , 0xfc },
1067         { STB0899_IRQMSK_1              , 0xff },
1068         { STB0899_IRQMSK_0              , 0xff },
1069         { STB0899_IRQCFG                , 0x00 },
1070         { STB0899_I2CCFG                , 0x88 },
1071         { STB0899_I2CRPT                , 0x48 }, /* 12k Pullup, Repeater=16, Stop=disabled */
1072         { STB0899_IOPVALUE5             , 0x00 },
1073         { STB0899_IOPVALUE4             , 0x20 },
1074         { STB0899_IOPVALUE3             , 0xc9 },
1075         { STB0899_IOPVALUE2             , 0x90 },
1076         { STB0899_IOPVALUE1             , 0x40 },
1077         { STB0899_IOPVALUE0             , 0x00 },
1078         { STB0899_GPIO00CFG             , 0x82 },
1079         { STB0899_GPIO01CFG             , 0x82 },
1080         { STB0899_GPIO02CFG             , 0x82 },
1081         { STB0899_GPIO03CFG             , 0x82 },
1082         { STB0899_GPIO04CFG             , 0x82 },
1083         { STB0899_GPIO05CFG             , 0x82 },
1084         { STB0899_GPIO06CFG             , 0x82 },
1085         { STB0899_GPIO07CFG             , 0x82 },
1086         { STB0899_GPIO08CFG             , 0x82 },
1087         { STB0899_GPIO09CFG             , 0x82 },
1088         { STB0899_GPIO10CFG             , 0x82 },
1089         { STB0899_GPIO11CFG             , 0x82 },
1090         { STB0899_GPIO12CFG             , 0x82 },
1091         { STB0899_GPIO13CFG             , 0x82 },
1092         { STB0899_GPIO14CFG             , 0x82 },
1093         { STB0899_GPIO15CFG             , 0x82 },
1094         { STB0899_GPIO16CFG             , 0x82 },
1095         { STB0899_GPIO17CFG             , 0x82 },
1096         { STB0899_GPIO18CFG             , 0x82 },
1097         { STB0899_GPIO19CFG             , 0x82 },
1098         { STB0899_GPIO20CFG             , 0x82 },
1099         { STB0899_SDATCFG               , 0xb8 },
1100         { STB0899_SCLTCFG               , 0xba },
1101         { STB0899_AGCRFCFG              , 0x1c }, /* 0x11 */
1102         { STB0899_GPIO22                , 0x82 }, /* AGCBB2CFG */
1103         { STB0899_GPIO21                , 0x91 }, /* AGCBB1CFG */
1104         { STB0899_DIRCLKCFG             , 0x82 },
1105         { STB0899_CLKOUT27CFG           , 0x7e },
1106         { STB0899_STDBYCFG              , 0x82 },
1107         { STB0899_CS0CFG                , 0x82 },
1108         { STB0899_CS1CFG                , 0x82 },
1109         { STB0899_DISEQCOCFG            , 0x20 },
1110         { STB0899_GPIO32CFG             , 0x82 },
1111         { STB0899_GPIO33CFG             , 0x82 },
1112         { STB0899_GPIO34CFG             , 0x82 },
1113         { STB0899_GPIO35CFG             , 0x82 },
1114         { STB0899_GPIO36CFG             , 0x82 },
1115         { STB0899_GPIO37CFG             , 0x82 },
1116         { STB0899_GPIO38CFG             , 0x82 },
1117         { STB0899_GPIO39CFG             , 0x82 },
1118         { STB0899_NCOARSE               , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
1119         { STB0899_SYNTCTRL              , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
1120         { STB0899_FILTCTRL              , 0x00 },
1121         { STB0899_SYSCTRL               , 0x00 },
1122         { STB0899_STOPCLK1              , 0x20 },
1123         { STB0899_STOPCLK2              , 0x00 },
1124         { STB0899_INTBUFSTATUS          , 0x00 },
1125         { STB0899_INTBUFCTRL            , 0x0a },
1126         { 0xffff                        , 0xff },
1127 };
1128
1129 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = {
1130         { STB0899_DEMOD                 , 0x00 },
1131         { STB0899_RCOMPC                , 0xc9 },
1132         { STB0899_AGC1CN                , 0x41 },
1133         { STB0899_AGC1REF               , 0x10 },
1134         { STB0899_RTC                   , 0x7a },
1135         { STB0899_TMGCFG                , 0x4e },
1136         { STB0899_AGC2REF               , 0x34 },
1137         { STB0899_TLSR                  , 0x84 },
1138         { STB0899_CFD                   , 0xc7 },
1139         { STB0899_ACLC                  , 0x87 },
1140         { STB0899_BCLC                  , 0x94 },
1141         { STB0899_EQON                  , 0x41 },
1142         { STB0899_LDT                   , 0xdd },
1143         { STB0899_LDT2                  , 0xc9 },
1144         { STB0899_EQUALREF              , 0xb4 },
1145         { STB0899_TMGRAMP               , 0x10 },
1146         { STB0899_TMGTHD                , 0x30 },
1147         { STB0899_IDCCOMP               , 0xfb },
1148         { STB0899_QDCCOMP               , 0x03 },
1149         { STB0899_POWERI                , 0x3b },
1150         { STB0899_POWERQ                , 0x3d },
1151         { STB0899_RCOMP                 , 0x81 },
1152         { STB0899_AGCIQIN               , 0x80 },
1153         { STB0899_AGC2I1                , 0x04 },
1154         { STB0899_AGC2I2                , 0xf5 },
1155         { STB0899_TLIR                  , 0x25 },
1156         { STB0899_RTF                   , 0x80 },
1157         { STB0899_DSTATUS               , 0x00 },
1158         { STB0899_LDI                   , 0xca },
1159         { STB0899_CFRM                  , 0xf1 },
1160         { STB0899_CFRL                  , 0xf3 },
1161         { STB0899_NIRM                  , 0x2a },
1162         { STB0899_NIRL                  , 0x05 },
1163         { STB0899_ISYMB                 , 0x17 },
1164         { STB0899_QSYMB                 , 0xfa },
1165         { STB0899_SFRH                  , 0x2f },
1166         { STB0899_SFRM                  , 0x68 },
1167         { STB0899_SFRL                  , 0x40 },
1168         { STB0899_SFRUPH                , 0x2f },
1169         { STB0899_SFRUPM                , 0x68 },
1170         { STB0899_SFRUPL                , 0x40 },
1171         { STB0899_EQUAI1                , 0xfd },
1172         { STB0899_EQUAQ1                , 0x04 },
1173         { STB0899_EQUAI2                , 0x0f },
1174         { STB0899_EQUAQ2                , 0xff },
1175         { STB0899_EQUAI3                , 0xdf },
1176         { STB0899_EQUAQ3                , 0xfa },
1177         { STB0899_EQUAI4                , 0x37 },
1178         { STB0899_EQUAQ4                , 0x0d },
1179         { STB0899_EQUAI5                , 0xbd },
1180         { STB0899_EQUAQ5                , 0xf7 },
1181         { STB0899_DSTATUS2              , 0x00 },
1182         { STB0899_VSTATUS               , 0x00 },
1183         { STB0899_VERROR                , 0xff },
1184         { STB0899_IQSWAP                , 0x2a },
1185         { STB0899_ECNT1M                , 0x00 },
1186         { STB0899_ECNT1L                , 0x00 },
1187         { STB0899_ECNT2M                , 0x00 },
1188         { STB0899_ECNT2L                , 0x00 },
1189         { STB0899_ECNT3M                , 0x00 },
1190         { STB0899_ECNT3L                , 0x00 },
1191         { STB0899_FECAUTO1              , 0x06 },
1192         { STB0899_FECM                  , 0x01 },
1193         { STB0899_VTH12                 , 0xf0 },
1194         { STB0899_VTH23                 , 0xa0 },
1195         { STB0899_VTH34                 , 0x78 },
1196         { STB0899_VTH56                 , 0x4e },
1197         { STB0899_VTH67                 , 0x48 },
1198         { STB0899_VTH78                 , 0x38 },
1199         { STB0899_PRVIT                 , 0xff },
1200         { STB0899_VITSYNC               , 0x19 },
1201         { STB0899_RSULC                 , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
1202         { STB0899_TSULC                 , 0x42 },
1203         { STB0899_RSLLC                 , 0x40 },
1204         { STB0899_TSLPL                 , 0x12 },
1205         { STB0899_TSCFGH                , 0x0c },
1206         { STB0899_TSCFGM                , 0x00 },
1207         { STB0899_TSCFGL                , 0x0c },
1208         { STB0899_TSOUT                 , 0x4d }, /* 0x0d for CAM */
1209         { STB0899_RSSYNCDEL             , 0x00 },
1210         { STB0899_TSINHDELH             , 0x02 },
1211         { STB0899_TSINHDELM             , 0x00 },
1212         { STB0899_TSINHDELL             , 0x00 },
1213         { STB0899_TSLLSTKM              , 0x00 },
1214         { STB0899_TSLLSTKL              , 0x00 },
1215         { STB0899_TSULSTKM              , 0x00 },
1216         { STB0899_TSULSTKL              , 0xab },
1217         { STB0899_PCKLENUL              , 0x00 },
1218         { STB0899_PCKLENLL              , 0xcc },
1219         { STB0899_RSPCKLEN              , 0xcc },
1220         { STB0899_TSSTATUS              , 0x80 },
1221         { STB0899_ERRCTRL1              , 0xb6 },
1222         { STB0899_ERRCTRL2              , 0x96 },
1223         { STB0899_ERRCTRL3              , 0x89 },
1224         { STB0899_DMONMSK1              , 0x27 },
1225         { STB0899_DMONMSK0              , 0x03 },
1226         { STB0899_DEMAPVIT              , 0x5c },
1227         { STB0899_PLPARM                , 0x1f },
1228         { STB0899_PDELCTRL              , 0x48 },
1229         { STB0899_PDELCTRL2             , 0x00 },
1230         { STB0899_BBHCTRL1              , 0x00 },
1231         { STB0899_BBHCTRL2              , 0x00 },
1232         { STB0899_HYSTTHRESH            , 0x77 },
1233         { STB0899_MATCSTM               , 0x00 },
1234         { STB0899_MATCSTL               , 0x00 },
1235         { STB0899_UPLCSTM               , 0x00 },
1236         { STB0899_UPLCSTL               , 0x00 },
1237         { STB0899_DFLCSTM               , 0x00 },
1238         { STB0899_DFLCSTL               , 0x00 },
1239         { STB0899_SYNCCST               , 0x00 },
1240         { STB0899_SYNCDCSTM             , 0x00 },
1241         { STB0899_SYNCDCSTL             , 0x00 },
1242         { STB0899_ISI_ENTRY             , 0x00 },
1243         { STB0899_ISI_BIT_EN            , 0x00 },
1244         { STB0899_MATSTRM               , 0x00 },
1245         { STB0899_MATSTRL               , 0x00 },
1246         { STB0899_UPLSTRM               , 0x00 },
1247         { STB0899_UPLSTRL               , 0x00 },
1248         { STB0899_DFLSTRM               , 0x00 },
1249         { STB0899_DFLSTRL               , 0x00 },
1250         { STB0899_SYNCSTR               , 0x00 },
1251         { STB0899_SYNCDSTRM             , 0x00 },
1252         { STB0899_SYNCDSTRL             , 0x00 },
1253         { STB0899_CFGPDELSTATUS1        , 0x10 },
1254         { STB0899_CFGPDELSTATUS2        , 0x00 },
1255         { STB0899_BBFERRORM             , 0x00 },
1256         { STB0899_BBFERRORL             , 0x00 },
1257         { STB0899_UPKTERRORM            , 0x00 },
1258         { STB0899_UPKTERRORL            , 0x00 },
1259         { 0xffff                        , 0xff },
1260 };
1261
1262 static struct stb0899_config tt3200_config = {
1263         .init_dev               = tt3200_stb0899_s1_init_1,
1264         .init_s2_demod          = stb0899_s2_init_2,
1265         .init_s1_demod          = tt3200_stb0899_s1_init_3,
1266         .init_s2_fec            = stb0899_s2_init_4,
1267         .init_tst               = stb0899_s1_init_5,
1268
1269         .postproc               = NULL,
1270
1271         .demod_address          = 0x68,
1272
1273         .xtal_freq              = 27000000,
1274         .inversion              = IQ_SWAP_ON, /* 1 */
1275
1276         .lo_clk                 = 76500000,
1277         .hi_clk                 = 99000000,
1278
1279         .esno_ave               = STB0899_DVBS2_ESNO_AVE,
1280         .esno_quant             = STB0899_DVBS2_ESNO_QUANT,
1281         .avframes_coarse        = STB0899_DVBS2_AVFRAMES_COARSE,
1282         .avframes_fine          = STB0899_DVBS2_AVFRAMES_FINE,
1283         .miss_threshold         = STB0899_DVBS2_MISS_THRESHOLD,
1284         .uwp_threshold_acq      = STB0899_DVBS2_UWP_THRESHOLD_ACQ,
1285         .uwp_threshold_track    = STB0899_DVBS2_UWP_THRESHOLD_TRACK,
1286         .uwp_threshold_sof      = STB0899_DVBS2_UWP_THRESHOLD_SOF,
1287         .sof_search_timeout     = STB0899_DVBS2_SOF_SEARCH_TIMEOUT,
1288
1289         .btr_nco_bits           = STB0899_DVBS2_BTR_NCO_BITS,
1290         .btr_gain_shift_offset  = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET,
1291         .crl_nco_bits           = STB0899_DVBS2_CRL_NCO_BITS,
1292         .ldpc_max_iter          = STB0899_DVBS2_LDPC_MAX_ITER,
1293
1294         .tuner_get_frequency    = stb6100_get_frequency,
1295         .tuner_set_frequency    = stb6100_set_frequency,
1296         .tuner_set_bandwidth    = stb6100_set_bandwidth,
1297         .tuner_get_bandwidth    = stb6100_get_bandwidth,
1298         .tuner_set_rfsiggain    = NULL
1299 };
1300
1301 static struct stb6100_config tt3200_stb6100_config = {
1302         .tuner_address  = 0x60,
1303         .refclock       = 27000000,
1304 };
1305
1306 static void frontend_init(struct budget_ci *budget_ci)
1307 {
1308         switch (budget_ci->budget.dev->pci->subsystem_device) {
1309         case 0x100c:            // Hauppauge/TT Nova-CI budget (stv0299/ALPS BSRU6(tsa5059))
1310                 budget_ci->budget.dvb_frontend =
1311                         dvb_attach(stv0299_attach, &alps_bsru6_config, &budget_ci->budget.i2c_adap);
1312                 if (budget_ci->budget.dvb_frontend) {
1313                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params;
1314                         budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap;
1315                         break;
1316                 }
1317                 break;
1318
1319         case 0x100f:            // Hauppauge/TT Nova-CI budget (stv0299b/Philips su1278(tsa5059))
1320                 budget_ci->budget.dvb_frontend =
1321                         dvb_attach(stv0299_attach, &philips_su1278_tt_config, &budget_ci->budget.i2c_adap);
1322                 if (budget_ci->budget.dvb_frontend) {
1323                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_su1278_tt_tuner_set_params;
1324                         break;
1325                 }
1326                 break;
1327
1328         case 0x1010:            // TT DVB-C CI budget (stv0297/Philips tdm1316l(tda6651tt))
1329                 budget_ci->tuner_pll_address = 0x61;
1330                 budget_ci->budget.dvb_frontend =
1331                         dvb_attach(stv0297_attach, &dvbc_philips_tdm1316l_config, &budget_ci->budget.i2c_adap);
1332                 if (budget_ci->budget.dvb_frontend) {
1333                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = dvbc_philips_tdm1316l_tuner_set_params;
1334                         break;
1335                 }
1336                 break;
1337
1338         case 0x1011:            // Hauppauge/TT Nova-T budget (tda10045/Philips tdm1316l(tda6651tt) + TDA9889)
1339                 budget_ci->tuner_pll_address = 0x63;
1340                 budget_ci->budget.dvb_frontend =
1341                         dvb_attach(tda10045_attach, &philips_tdm1316l_config, &budget_ci->budget.i2c_adap);
1342                 if (budget_ci->budget.dvb_frontend) {
1343                         budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init;
1344                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params;
1345                         break;
1346                 }
1347                 break;
1348
1349         case 0x1012:            // TT DVB-T CI budget (tda10046/Philips tdm1316l(tda6651tt))
1350                 budget_ci->tuner_pll_address = 0x60;
1351                 budget_ci->budget.dvb_frontend =
1352                         dvb_attach(tda10046_attach, &philips_tdm1316l_config_invert, &budget_ci->budget.i2c_adap);
1353                 if (budget_ci->budget.dvb_frontend) {
1354                         budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init;
1355                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params;
1356                         break;
1357                 }
1358                 break;
1359
1360         case 0x1017:            // TT S-1500 PCI
1361                 budget_ci->budget.dvb_frontend = dvb_attach(stv0299_attach, &alps_bsbe1_config, &budget_ci->budget.i2c_adap);
1362                 if (budget_ci->budget.dvb_frontend) {
1363                         budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsbe1_tuner_set_params;
1364                         budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap;
1365
1366                         budget_ci->budget.dvb_frontend->ops.dishnetwork_send_legacy_command = NULL;
1367                         if (dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, LNBP21_LLC, 0) == NULL) {
1368                                 printk("%s: No LNBP21 found!\n", __func__);
1369                                 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1370                                 budget_ci->budget.dvb_frontend = NULL;
1371                         }
1372                 }
1373                 break;
1374
1375         case 0x101a: /* TT Budget-C-1501 (philips tda10023/philips tda8274A) */
1376                 budget_ci->budget.dvb_frontend = dvb_attach(tda10023_attach, &tda10023_config, &budget_ci->budget.i2c_adap, 0x48);
1377                 if (budget_ci->budget.dvb_frontend) {
1378                         if (dvb_attach(tda827x_attach, budget_ci->budget.dvb_frontend, 0x61, &budget_ci->budget.i2c_adap, &tda827x_config) == NULL) {
1379                                 printk(KERN_ERR "%s: No tda827x found!\n", __func__);
1380                                 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1381                                 budget_ci->budget.dvb_frontend = NULL;
1382                         }
1383                 }
1384                 break;
1385
1386         case 0x1019:            // TT S2-3200 PCI
1387                 /*
1388                  * NOTE! on some STB0899 versions, the internal PLL takes a longer time
1389                  * to settle, aka LOCK. On the older revisions of the chip, we don't see
1390                  * this, as a result on the newer chips the entire clock tree, will not
1391                  * be stable after a freshly POWER 'ed up situation.
1392                  * In this case, we should RESET the STB0899 (Active LOW) and wait for
1393                  * PLL stabilization.
1394                  *
1395                  * On the TT S2 3200 and clones, the STB0899 demodulator's RESETB is
1396                  * connected to the SAA7146 GPIO, GPIO2, Pin 142
1397                  */
1398                 /* Reset Demodulator */
1399                 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTLO);
1400                 /* Wait for everything to die */
1401                 msleep(50);
1402                 /* Pull it up out of Reset state */
1403                 saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTHI);
1404                 /* Wait for PLL to stabilize */
1405                 msleep(250);
1406                 /*
1407                  * PLL state should be stable now. Ideally, we should check
1408                  * for PLL LOCK status. But well, never mind!
1409                  */
1410                 budget_ci->budget.dvb_frontend = dvb_attach(stb0899_attach, &tt3200_config, &budget_ci->budget.i2c_adap);
1411                 if (budget_ci->budget.dvb_frontend) {
1412                         if (dvb_attach(stb6100_attach, budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) {
1413                                 if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) {
1414                                         printk("%s: No LNBP21 found!\n", __func__);
1415                                         dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1416                                         budget_ci->budget.dvb_frontend = NULL;
1417                                 }
1418                         } else {
1419                                         dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1420                                         budget_ci->budget.dvb_frontend = NULL;
1421                         }
1422                 }
1423                 break;
1424
1425         }
1426
1427         if (budget_ci->budget.dvb_frontend == NULL) {
1428                 printk("budget-ci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n",
1429                        budget_ci->budget.dev->pci->vendor,
1430                        budget_ci->budget.dev->pci->device,
1431                        budget_ci->budget.dev->pci->subsystem_vendor,
1432                        budget_ci->budget.dev->pci->subsystem_device);
1433         } else {
1434                 if (dvb_register_frontend
1435                     (&budget_ci->budget.dvb_adapter, budget_ci->budget.dvb_frontend)) {
1436                         printk("budget-ci: Frontend registration failed!\n");
1437                         dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1438                         budget_ci->budget.dvb_frontend = NULL;
1439                 }
1440         }
1441 }
1442
1443 static int budget_ci_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info)
1444 {
1445         struct budget_ci *budget_ci;
1446         int err;
1447
1448         budget_ci = kzalloc(sizeof(struct budget_ci), GFP_KERNEL);
1449         if (!budget_ci) {
1450                 err = -ENOMEM;
1451                 goto out1;
1452         }
1453
1454         dprintk(2, "budget_ci: %p\n", budget_ci);
1455
1456         dev->ext_priv = budget_ci;
1457
1458         err = ttpci_budget_init(&budget_ci->budget, dev, info, THIS_MODULE,
1459                                 adapter_nr);
1460         if (err)
1461                 goto out2;
1462
1463         err = msp430_ir_init(budget_ci);
1464         if (err)
1465                 goto out3;
1466
1467         ciintf_init(budget_ci);
1468
1469         budget_ci->budget.dvb_adapter.priv = budget_ci;
1470         frontend_init(budget_ci);
1471
1472         ttpci_budget_init_hooks(&budget_ci->budget);
1473
1474         return 0;
1475
1476 out3:
1477         ttpci_budget_deinit(&budget_ci->budget);
1478 out2:
1479         kfree(budget_ci);
1480 out1:
1481         return err;
1482 }
1483
1484 static int budget_ci_detach(struct saa7146_dev *dev)
1485 {
1486         struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv;
1487         struct saa7146_dev *saa = budget_ci->budget.dev;
1488         int err;
1489
1490         if (budget_ci->budget.ci_present)
1491                 ciintf_deinit(budget_ci);
1492         msp430_ir_deinit(budget_ci);
1493         if (budget_ci->budget.dvb_frontend) {
1494                 dvb_unregister_frontend(budget_ci->budget.dvb_frontend);
1495                 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1496         }
1497         err = ttpci_budget_deinit(&budget_ci->budget);
1498
1499         // disable frontend and CI interface
1500         saa7146_setgpio(saa, 2, SAA7146_GPIO_INPUT);
1501
1502         kfree(budget_ci);
1503
1504         return err;
1505 }
1506
1507 static struct saa7146_extension budget_extension;
1508
1509 MAKE_BUDGET_INFO(ttbs2, "TT-Budget/S-1500 PCI", BUDGET_TT);
1510 MAKE_BUDGET_INFO(ttbci, "TT-Budget/WinTV-NOVA-CI PCI", BUDGET_TT_HW_DISEQC);
1511 MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T  PCI", BUDGET_TT);
1512 MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT);
1513 MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT);
1514 MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT);
1515 MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT);
1516
1517 static struct pci_device_id pci_tbl[] = {
1518         MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c),
1519         MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100f),
1520         MAKE_EXTENSION_PCI(ttbcci, 0x13c2, 0x1010),
1521         MAKE_EXTENSION_PCI(ttbt2, 0x13c2, 0x1011),
1522         MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012),
1523         MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017),
1524         MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a),
1525         MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019),
1526         {
1527          .vendor = 0,
1528          }
1529 };
1530
1531 MODULE_DEVICE_TABLE(pci, pci_tbl);
1532
1533 static struct saa7146_extension budget_extension = {
1534         .name = "budget_ci dvb",
1535         .flags = SAA7146_USE_I2C_IRQ,
1536
1537         .module = THIS_MODULE,
1538         .pci_tbl = &pci_tbl[0],
1539         .attach = budget_ci_attach,
1540         .detach = budget_ci_detach,
1541
1542         .irq_mask = MASK_03 | MASK_06 | MASK_10,
1543         .irq_func = budget_ci_irq,
1544 };
1545
1546 static int __init budget_ci_init(void)
1547 {
1548         return saa7146_register_extension(&budget_extension);
1549 }
1550
1551 static void __exit budget_ci_exit(void)
1552 {
1553         saa7146_unregister_extension(&budget_extension);
1554 }
1555
1556 module_init(budget_ci_init);
1557 module_exit(budget_ci_exit);
1558
1559 MODULE_LICENSE("GPL");
1560 MODULE_AUTHOR("Michael Hunold, Jack Thomasson, Andrew de Quincey, others");
1561 MODULE_DESCRIPTION("driver for the SAA7146 based so-called "
1562                    "budget PCI DVB cards w/ CI-module produced by "
1563                    "Siemens, Technotrend, Hauppauge");