drivers/media/dvb/frontends/s5h1411.c

   1 /*
   2     Samsung S5H1411 VSB/QAM demodulator driver
   3
   4     Copyright (C) 2008 Steven Toth <stoth@hauppauge.com>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19
  20 */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/string.h>
  26 #include <linux/slab.h>
  27 #include <linux/delay.h>
  28 #include "dvb_frontend.h"
  29 #include "dvb-pll.h"
  30 #include "s5h1411.h"
  31
  32 struct s5h1411_state {
  33
  34         struct i2c_adapter *i2c;
  35
  36         /* configuration settings */
  37         const struct s5h1411_config *config;
  38
  39         struct dvb_frontend frontend;
  40
  41         fe_modulation_t current_modulation;
  42
  43         u32 current_frequency;
  44         int if_freq;
  45
  46         u8 inversion;
  47 };
  48
  49 static int debug;
  50
  51 #define dprintk(arg...) do {    \
  52         if (debug)              \
  53                 printk(arg);    \
  54         } while (0)
  55
  56 /* Register values to initialise the demod, defaults to VSB */
  57 static struct init_tab {
  58         u8      addr;
  59         u8      reg;
  60         u16     data;
  61 } init_tab[] = {
  62         { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
  63         { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
  64         { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
  65         { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
  66         { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342a, },
  67         { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
  68         { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
  69         { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
  70         { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
  71         { S5H1411_I2C_TOP_ADDR, 0x28, 0x070f, },
  72         { S5H1411_I2C_TOP_ADDR, 0x29, 0x2820, },
  73         { S5H1411_I2C_TOP_ADDR, 0x2a, 0x102e, },
  74         { S5H1411_I2C_TOP_ADDR, 0x2b, 0x0220, },
  75         { S5H1411_I2C_TOP_ADDR, 0x2e, 0x0d0e, },
  76         { S5H1411_I2C_TOP_ADDR, 0x2f, 0x1013, },
  77         { S5H1411_I2C_TOP_ADDR, 0x31, 0x171b, },
  78         { S5H1411_I2C_TOP_ADDR, 0x32, 0x0e0f, },
  79         { S5H1411_I2C_TOP_ADDR, 0x33, 0x0f10, },
  80         { S5H1411_I2C_TOP_ADDR, 0x34, 0x170e, },
  81         { S5H1411_I2C_TOP_ADDR, 0x35, 0x4b10, },
  82         { S5H1411_I2C_TOP_ADDR, 0x36, 0x0f17, },
  83         { S5H1411_I2C_TOP_ADDR, 0x3c, 0x1577, },
  84         { S5H1411_I2C_TOP_ADDR, 0x3d, 0x081a, },
  85         { S5H1411_I2C_TOP_ADDR, 0x3e, 0x77ee, },
  86         { S5H1411_I2C_TOP_ADDR, 0x40, 0x1e09, },
  87         { S5H1411_I2C_TOP_ADDR, 0x41, 0x0f0c, },
  88         { S5H1411_I2C_TOP_ADDR, 0x42, 0x1f10, },
  89         { S5H1411_I2C_TOP_ADDR, 0x4d, 0x0509, },
  90         { S5H1411_I2C_TOP_ADDR, 0x4e, 0x0a00, },
  91         { S5H1411_I2C_TOP_ADDR, 0x50, 0x0000, },
  92         { S5H1411_I2C_TOP_ADDR, 0x5b, 0x0000, },
  93         { S5H1411_I2C_TOP_ADDR, 0x5c, 0x0008, },
  94         { S5H1411_I2C_TOP_ADDR, 0x57, 0x1101, },
  95         { S5H1411_I2C_TOP_ADDR, 0x65, 0x007c, },
  96         { S5H1411_I2C_TOP_ADDR, 0x68, 0x0512, },
  97         { S5H1411_I2C_TOP_ADDR, 0x69, 0x0258, },
  98         { S5H1411_I2C_TOP_ADDR, 0x70, 0x0004, },
  99         { S5H1411_I2C_TOP_ADDR, 0x71, 0x0007, },
 100         { S5H1411_I2C_TOP_ADDR, 0x76, 0x00a9, },
 101         { S5H1411_I2C_TOP_ADDR, 0x78, 0x3141, },
 102         { S5H1411_I2C_TOP_ADDR, 0x7a, 0x3141, },
 103         { S5H1411_I2C_TOP_ADDR, 0xb3, 0x8003, },
 104         { S5H1411_I2C_TOP_ADDR, 0xb5, 0xafbb, },
 105         { S5H1411_I2C_TOP_ADDR, 0xb5, 0xa6bb, },
 106         { S5H1411_I2C_TOP_ADDR, 0xb6, 0x0609, },
 107         { S5H1411_I2C_TOP_ADDR, 0xb7, 0x2f06, },
 108         { S5H1411_I2C_TOP_ADDR, 0xb8, 0x003f, },
 109         { S5H1411_I2C_TOP_ADDR, 0xb9, 0x2700, },
 110         { S5H1411_I2C_TOP_ADDR, 0xba, 0xfac8, },
 111         { S5H1411_I2C_TOP_ADDR, 0xbe, 0x1003, },
 112         { S5H1411_I2C_TOP_ADDR, 0xbf, 0x103f, },
 113         { S5H1411_I2C_TOP_ADDR, 0xce, 0x2000, },
 114         { S5H1411_I2C_TOP_ADDR, 0xcf, 0x0800, },
 115         { S5H1411_I2C_TOP_ADDR, 0xd0, 0x0800, },
 116         { S5H1411_I2C_TOP_ADDR, 0xd1, 0x0400, },
 117         { S5H1411_I2C_TOP_ADDR, 0xd2, 0x0800, },
 118         { S5H1411_I2C_TOP_ADDR, 0xd3, 0x2000, },
 119         { S5H1411_I2C_TOP_ADDR, 0xd4, 0x3000, },
 120         { S5H1411_I2C_TOP_ADDR, 0xdb, 0x4a9b, },
 121         { S5H1411_I2C_TOP_ADDR, 0xdc, 0x1000, },
 122         { S5H1411_I2C_TOP_ADDR, 0xde, 0x0001, },
 123         { S5H1411_I2C_TOP_ADDR, 0xdf, 0x0000, },
 124         { S5H1411_I2C_TOP_ADDR, 0xe3, 0x0301, },
 125         { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, },
 126         { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, },
 127         { S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, },
 128         { S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, },
 129         { S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, },
 130         { S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, },
 131         { S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, },
 132         { S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, },
 133         { S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, },
 134         { S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, },
 135         { S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, },
 136         { S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, },
 137         { S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, },
 138         { S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, },
 139         { S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, },
 140         { S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, },
 141         { S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, },
 142         { S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, },
 143 };
 144
 145 /* VSB SNR lookup table */
 146 static struct vsb_snr_tab {
 147         u16     val;
 148         u16     data;
 149 } vsb_snr_tab[] = {
 150         {  0x39f, 300, },
 151         {  0x39b, 295, },
 152         {  0x397, 290, },
 153         {  0x394, 285, },
 154         {  0x38f, 280, },
 155         {  0x38b, 275, },
 156         {  0x387, 270, },
 157         {  0x382, 265, },
 158         {  0x37d, 260, },
 159         {  0x377, 255, },
 160         {  0x370, 250, },
 161         {  0x36a, 245, },
 162         {  0x364, 240, },
 163         {  0x35b, 235, },
 164         {  0x353, 230, },
 165         {  0x349, 225, },
 166         {  0x340, 320, },
 167         {  0x337, 215, },
 168         {  0x327, 210, },
 169         {  0x31b, 205, },
 170         {  0x310, 200, },
 171         {  0x302, 195, },
 172         {  0x2f3, 190, },
 173         {  0x2e4, 185, },
 174         {  0x2d7, 180, },
 175         {  0x2cd, 175, },
 176         {  0x2bb, 170, },
 177         {  0x2a9, 165, },
 178         {  0x29e, 160, },
 179         {  0x284, 155, },
 180         {  0x27a, 150, },
 181         {  0x260, 145, },
 182         {  0x23a, 140, },
 183         {  0x224, 135, },
 184         {  0x213, 130, },
 185         {  0x204, 125, },
 186         {  0x1fe, 120, },
 187         {      0,   0, },
 188 };
 189
 190 /* QAM64 SNR lookup table */
 191 static struct qam64_snr_tab {
 192         u16     val;
 193         u16     data;
 194 } qam64_snr_tab[] = {
 195         {  0x0001,   0, },
 196         {  0x0af0, 300, },
 197         {  0x0d80, 290, },
 198         {  0x10a0, 280, },
 199         {  0x14b5, 270, },
 200         {  0x1590, 268, },
 201         {  0x1680, 266, },
 202         {  0x17b0, 264, },
 203         {  0x18c0, 262, },
 204         {  0x19b0, 260, },
 205         {  0x1ad0, 258, },
 206         {  0x1d00, 256, },
 207         {  0x1da0, 254, },
 208         {  0x1ef0, 252, },
 209         {  0x2050, 250, },
 210         {  0x20f0, 249, },
 211         {  0x21d0, 248, },
 212         {  0x22b0, 247, },
 213         {  0x23a0, 246, },
 214         {  0x2470, 245, },
 215         {  0x24f0, 244, },
 216         {  0x25a0, 243, },
 217         {  0x26c0, 242, },
 218         {  0x27b0, 241, },
 219         {  0x28d0, 240, },
 220         {  0x29b0, 239, },
 221         {  0x2ad0, 238, },
 222         {  0x2ba0, 237, },
 223         {  0x2c80, 236, },
 224         {  0x2d20, 235, },
 225         {  0x2e00, 234, },
 226         {  0x2f10, 233, },
 227         {  0x3050, 232, },
 228         {  0x3190, 231, },
 229         {  0x3300, 230, },
 230         {  0x3340, 229, },
 231         {  0x3200, 228, },
 232         {  0x3550, 227, },
 233         {  0x3610, 226, },
 234         {  0x3600, 225, },
 235         {  0x3700, 224, },
 236         {  0x3800, 223, },
 237         {  0x3920, 222, },
 238         {  0x3a20, 221, },
 239         {  0x3b30, 220, },
 240         {  0x3d00, 219, },
 241         {  0x3e00, 218, },
 242         {  0x4000, 217, },
 243         {  0x4100, 216, },
 244         {  0x4300, 215, },
 245         {  0x4400, 214, },
 246         {  0x4600, 213, },
 247         {  0x4700, 212, },
 248         {  0x4800, 211, },
 249         {  0x4a00, 210, },
 250         {  0x4b00, 209, },
 251         {  0x4d00, 208, },
 252         {  0x4f00, 207, },
 253         {  0x5050, 206, },
 254         {  0x5200, 205, },
 255         {  0x53c0, 204, },
 256         {  0x5450, 203, },
 257         {  0x5650, 202, },
 258         {  0x5820, 201, },
 259         {  0x6000, 200, },
 260         {  0xffff,   0, },
 261 };
 262
 263 /* QAM256 SNR lookup table */
 264 static struct qam256_snr_tab {
 265         u16     val;
 266         u16     data;
 267 } qam256_snr_tab[] = {
 268         {  0x0001,   0, },
 269         {  0x0970, 400, },
 270         {  0x0a90, 390, },
 271         {  0x0b90, 380, },
 272         {  0x0d90, 370, },
 273         {  0x0ff0, 360, },
 274         {  0x1240, 350, },
 275         {  0x1345, 348, },
 276         {  0x13c0, 346, },
 277         {  0x14c0, 344, },
 278         {  0x1500, 342, },
 279         {  0x1610, 340, },
 280         {  0x1700, 338, },
 281         {  0x1800, 336, },
 282         {  0x18b0, 334, },
 283         {  0x1900, 332, },
 284         {  0x1ab0, 330, },
 285         {  0x1bc0, 328, },
 286         {  0x1cb0, 326, },
 287         {  0x1db0, 324, },
 288         {  0x1eb0, 322, },
 289         {  0x2030, 320, },
 290         {  0x2200, 318, },
 291         {  0x2280, 316, },
 292         {  0x2410, 314, },
 293         {  0x25b0, 312, },
 294         {  0x27a0, 310, },
 295         {  0x2840, 308, },
 296         {  0x29d0, 306, },
 297         {  0x2b10, 304, },
 298         {  0x2d30, 302, },
 299         {  0x2f20, 300, },
 300         {  0x30c0, 298, },
 301         {  0x3260, 297, },
 302         {  0x32c0, 296, },
 303         {  0x3300, 295, },
 304         {  0x33b0, 294, },
 305         {  0x34b0, 293, },
 306         {  0x35a0, 292, },
 307         {  0x3650, 291, },
 308         {  0x3800, 290, },
 309         {  0x3900, 289, },
 310         {  0x3a50, 288, },
 311         {  0x3b30, 287, },
 312         {  0x3cb0, 286, },
 313         {  0x3e20, 285, },
 314         {  0x3fa0, 284, },
 315         {  0x40a0, 283, },
 316         {  0x41c0, 282, },
 317         {  0x42f0, 281, },
 318         {  0x44a0, 280, },
 319         {  0x4600, 279, },
 320         {  0x47b0, 278, },
 321         {  0x4900, 277, },
 322         {  0x4a00, 276, },
 323         {  0x4ba0, 275, },
 324         {  0x4d00, 274, },
 325         {  0x4f00, 273, },
 326         {  0x5000, 272, },
 327         {  0x51f0, 272, },
 328         {  0x53a0, 270, },
 329         {  0x5520, 269, },
 330         {  0x5700, 268, },
 331         {  0x5800, 267, },
 332         {  0x5a00, 266, },
 333         {  0x5c00, 265, },
 334         {  0x5d00, 264, },
 335         {  0x5f00, 263, },
 336         {  0x6000, 262, },
 337         {  0x6200, 261, },
 338         {  0x6400, 260, },
 339         {  0xffff,   0, },
 340 };
 341
 342 /* 8 bit registers, 16 bit values */
 343 static int s5h1411_writereg(struct s5h1411_state *state,
 344         u8 addr, u8 reg, u16 data)
 345 {
 346         int ret;
 347         u8 buf [] = { reg, data >> 8,  data & 0xff };
 348
 349         struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 };
 350
 351         ret = i2c_transfer(state->i2c, &msg, 1);
 352
 353         if (ret != 1)
 354                 printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, "
 355                        "ret == %i)\n", __func__, addr, reg, data, ret);
 356
 357         return (ret != 1) ? -1 : 0;
 358 }
 359
 360 static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg)
 361 {
 362         int ret;
 363         u8 b0 [] = { reg };
 364         u8 b1 [] = { 0, 0 };
 365
 366         struct i2c_msg msg [] = {
 367                 { .addr = addr, .flags = 0, .buf = b0, .len = 1 },
 368                 { .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 2 } };
 369
 370         ret = i2c_transfer(state->i2c, msg, 2);
 371
 372         if (ret != 2)
 373                 printk(KERN_ERR "%s: readreg error (ret == %i)\n",
 374                         __func__, ret);
 375         return (b1[0] << 8) | b1[1];
 376 }
 377
 378 static int s5h1411_softreset(struct dvb_frontend *fe)
 379 {
 380         struct s5h1411_state *state = fe->demodulator_priv;
 381
 382         dprintk("%s()\n", __func__);
 383
 384         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0);
 385         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1);
 386         return 0;
 387 }
 388
 389 static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz)
 390 {
 391         struct s5h1411_state *state = fe->demodulator_priv;
 392
 393         dprintk("%s(%d KHz)\n", __func__, KHz);
 394
 395         switch (KHz) {
 396         case 3250:
 397                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d9);
 398                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342);
 399                 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9);
 400                 break;
 401         case 3500:
 402                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225);
 403                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96);
 404                 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225);
 405                 break;
 406         case 4000:
 407                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc);
 408                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e);
 409                 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd);
 410                 break;
 411         default:
 412                 dprintk("%s(%d KHz) Invalid, defaulting to 5380\n",
 413                         __func__, KHz);
 414                 /* no break, need to continue */
 415         case 5380:
 416         case 44000:
 417                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4);
 418                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655);
 419                 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4);
 420                 break;
 421         }
 422
 423         state->if_freq = KHz;
 424
 425         return 0;
 426 }
 427
 428 static int s5h1411_set_mpeg_timing(struct dvb_frontend *fe, int mode)
 429 {
 430         struct s5h1411_state *state = fe->demodulator_priv;
 431         u16 val;
 432
 433         dprintk("%s(%d)\n", __func__, mode);
 434
 435         val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff;
 436         switch (mode) {
 437         case S5H1411_MPEGTIMING_CONTINOUS_INVERTING_CLOCK:
 438                 val |= 0x0000;
 439                 break;
 440         case S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK:
 441                 dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode);
 442                 val |= 0x1000;
 443                 break;
 444         case S5H1411_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK:
 445                 val |= 0x2000;
 446                 break;
 447         case S5H1411_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK:
 448                 val |= 0x3000;
 449                 break;
 450         default:
 451                 return -EINVAL;
 452         }
 453
 454         /* Configure MPEG Signal Timing charactistics */
 455         return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val);
 456 }
 457
 458 static int s5h1411_set_spectralinversion(struct dvb_frontend *fe, int inversion)
 459 {
 460         struct s5h1411_state *state = fe->demodulator_priv;
 461         u16 val;
 462
 463         dprintk("%s(%d)\n", __func__, inversion);
 464         val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000;
 465
 466         if (inversion == 1)
 467                 val |= 0x1000; /* Inverted */
 468         else
 469                 val |= 0x0000;
 470
 471         state->inversion = inversion;
 472         return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val);
 473 }
 474
 475 static int s5h1411_enable_modulation(struct dvb_frontend *fe,
 476                                      fe_modulation_t m)
 477 {
 478         struct s5h1411_state *state = fe->demodulator_priv;
 479
 480         dprintk("%s(0x%08x)\n", __func__, m);
 481
 482         switch (m) {
 483         case VSB_8:
 484                 dprintk("%s() VSB_8\n", __func__);
 485                 s5h1411_set_if_freq(fe, state->config->vsb_if);
 486                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71);
 487                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00);
 488                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1);
 489                 break;
 490         case QAM_64:
 491         case QAM_256:
 492                 dprintk("%s() QAM_AUTO (64/256)\n", __func__);
 493                 s5h1411_set_if_freq(fe, state->config->qam_if);
 494                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171);
 495                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001);
 496                 s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101);
 497                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0);
 498                 break;
 499         default:
 500                 dprintk("%s() Invalid modulation\n", __func__);
 501                 return -EINVAL;
 502         }
 503
 504         state->current_modulation = m;
 505         s5h1411_softreset(fe);
 506
 507         return 0;
 508 }
 509
 510 static int s5h1411_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
 511 {
 512         struct s5h1411_state *state = fe->demodulator_priv;
 513
 514         dprintk("%s(%d)\n", __func__, enable);
 515
 516         if (enable)
 517                 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
 518         else
 519                 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0);
 520 }
 521
 522 static int s5h1411_set_gpio(struct dvb_frontend *fe, int enable)
 523 {
 524         struct s5h1411_state *state = fe->demodulator_priv;
 525         u16 val;
 526
 527         dprintk("%s(%d)\n", __func__, enable);
 528
 529         val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02;
 530
 531         if (enable)
 532                 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0,
 533                                 val | 0x02);
 534         else
 535                 return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val);
 536 }
 537
 538 static int s5h1411_sleep(struct dvb_frontend *fe, int enable)
 539 {
 540         struct s5h1411_state *state = fe->demodulator_priv;
 541
 542         dprintk("%s(%d)\n", __func__, enable);
 543
 544         if (enable)
 545                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1);
 546         else {
 547                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0);
 548                 s5h1411_softreset(fe);
 549         }
 550
 551         return 0;
 552 }
 553
 554 static int s5h1411_register_reset(struct dvb_frontend *fe)
 555 {
 556         struct s5h1411_state *state = fe->demodulator_priv;
 557
 558         dprintk("%s()\n", __func__);
 559
 560         return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0);
 561 }
 562
 563 /* Talk to the demod, set the FEC, GUARD, QAM settings etc */
 564 static int s5h1411_set_frontend(struct dvb_frontend *fe,
 565         struct dvb_frontend_parameters *p)
 566 {
 567         struct s5h1411_state *state = fe->demodulator_priv;
 568
 569         dprintk("%s(frequency=%d)\n", __func__, p->frequency);
 570
 571         s5h1411_softreset(fe);
 572
 573         state->current_frequency = p->frequency;
 574
 575         s5h1411_enable_modulation(fe, p->u.vsb.modulation);
 576
 577         /* Allow the demod to settle */
 578         msleep(100);
 579
 580         if (fe->ops.tuner_ops.set_params) {
 581                 if (fe->ops.i2c_gate_ctrl)
 582                         fe->ops.i2c_gate_ctrl(fe, 1);
 583
 584                 fe->ops.tuner_ops.set_params(fe, p);
 585
 586                 if (fe->ops.i2c_gate_ctrl)
 587                         fe->ops.i2c_gate_ctrl(fe, 0);
 588         }
 589
 590         return 0;
 591 }
 592
 593 /* Reset the demod hardware and reset all of the configuration registers
 594    to a default state. */
 595 static int s5h1411_init(struct dvb_frontend *fe)
 596 {
 597         struct s5h1411_state *state = fe->demodulator_priv;
 598         int i;
 599
 600         dprintk("%s()\n", __func__);
 601
 602         s5h1411_sleep(fe, 0);
 603         s5h1411_register_reset(fe);
 604
 605         for (i = 0; i < ARRAY_SIZE(init_tab); i++)
 606                 s5h1411_writereg(state, init_tab[i].addr,
 607                         init_tab[i].reg,
 608                         init_tab[i].data);
 609
 610         /* The datasheet says that after initialisation, VSB is default */
 611         state->current_modulation = VSB_8;
 612
 613         if (state->config->output_mode == S5H1411_SERIAL_OUTPUT)
 614                 /* Serial */
 615                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, 0x1101);
 616         else
 617                 /* Parallel */
 618                 s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, 0x1001);
 619
 620         s5h1411_set_spectralinversion(fe, state->config->inversion);
 621         s5h1411_set_if_freq(fe, state->config->vsb_if);
 622         s5h1411_set_gpio(fe, state->config->gpio);
 623         s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing);
 624         s5h1411_softreset(fe);
 625
 626         /* Note: Leaving the I2C gate closed. */
 627         s5h1411_i2c_gate_ctrl(fe, 0);
 628
 629         return 0;
 630 }
 631
 632 static int s5h1411_read_status(struct dvb_frontend *fe, fe_status_t *status)
 633 {
 634         struct s5h1411_state *state = fe->demodulator_priv;
 635         u16 reg;
 636         u32 tuner_status = 0;
 637
 638         *status = 0;
 639
 640         /* Get the demodulator status */
 641         reg = (s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2) >> 15)
 642                 & 0x0001;
 643         if (reg)
 644                 *status |= FE_HAS_LOCK | FE_HAS_CARRIER | FE_HAS_SIGNAL;
 645
 646         switch (state->current_modulation) {
 647         case QAM_64:
 648         case QAM_256:
 649                 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0);
 650                 if (reg & 0x100)
 651                         *status |= FE_HAS_VITERBI;
 652                 if (reg & 0x10)
 653                         *status |= FE_HAS_SYNC;
 654                 break;
 655         case VSB_8:
 656                 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x5e);
 657                 if (reg & 0x0001)
 658                         *status |= FE_HAS_SYNC;
 659                 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2);
 660                 if (reg & 0x1000)
 661                         *status |= FE_HAS_VITERBI;
 662                 break;
 663         default:
 664                 return -EINVAL;
 665         }
 666
 667         switch (state->config->status_mode) {
 668         case S5H1411_DEMODLOCKING:
 669                 if (*status & FE_HAS_VITERBI)
 670                         *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
 671                 break;
 672         case S5H1411_TUNERLOCKING:
 673                 /* Get the tuner status */
 674                 if (fe->ops.tuner_ops.get_status) {
 675                         if (fe->ops.i2c_gate_ctrl)
 676                                 fe->ops.i2c_gate_ctrl(fe, 1);
 677
 678                         fe->ops.tuner_ops.get_status(fe, &tuner_status);
 679
 680                         if (fe->ops.i2c_gate_ctrl)
 681                                 fe->ops.i2c_gate_ctrl(fe, 0);
 682                 }
 683                 if (tuner_status)
 684                         *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
 685                 break;
 686         }
 687
 688         dprintk("%s() status 0x%08x\n", __func__, *status);
 689
 690         return 0;
 691 }
 692
 693 static int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
 694 {
 695         int i, ret = -EINVAL;
 696         dprintk("%s()\n", __func__);
 697
 698         for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) {
 699                 if (v < qam256_snr_tab[i].val) {
 700                         *snr = qam256_snr_tab[i].data;
 701                         ret = 0;
 702                         break;
 703                 }
 704         }
 705         return ret;
 706 }
 707
 708 static int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
 709 {
 710         int i, ret = -EINVAL;
 711         dprintk("%s()\n", __func__);
 712
 713         for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) {
 714                 if (v < qam64_snr_tab[i].val) {
 715                         *snr = qam64_snr_tab[i].data;
 716                         ret = 0;
 717                         break;
 718                 }
 719         }
 720         return ret;
 721 }
 722
 723 static int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v)
 724 {
 725         int i, ret = -EINVAL;
 726         dprintk("%s()\n", __func__);
 727
 728         for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) {
 729                 if (v > vsb_snr_tab[i].val) {
 730                         *snr = vsb_snr_tab[i].data;
 731                         ret = 0;
 732                         break;
 733                 }
 734         }
 735         dprintk("%s() snr=%d\n", __func__, *snr);
 736         return ret;
 737 }
 738
 739 static int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr)
 740 {
 741         struct s5h1411_state *state = fe->demodulator_priv;
 742         u16 reg;
 743         dprintk("%s()\n", __func__);
 744
 745         switch (state->current_modulation) {
 746         case QAM_64:
 747                 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
 748                 return s5h1411_qam64_lookup_snr(fe, snr, reg);
 749         case QAM_256:
 750                 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1);
 751                 return s5h1411_qam256_lookup_snr(fe, snr, reg);
 752         case VSB_8:
 753                 reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR,
 754                         0xf2) & 0x3ff;
 755                 return s5h1411_vsb_lookup_snr(fe, snr, reg);
 756         default:
 757                 break;
 758         }
 759
 760         return -EINVAL;
 761 }
 762
 763 static int s5h1411_read_signal_strength(struct dvb_frontend *fe,
 764         u16 *signal_strength)
 765 {
 766         return s5h1411_read_snr(fe, signal_strength);
 767 }
 768
 769 static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
 770 {
 771         struct s5h1411_state *state = fe->demodulator_priv;
 772
 773         *ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9);
 774
 775         return 0;
 776 }
 777
 778 static int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber)
 779 {
 780         return s5h1411_read_ucblocks(fe, ber);
 781 }
 782
 783 static int s5h1411_get_frontend(struct dvb_frontend *fe,
 784                                 struct dvb_frontend_parameters *p)
 785 {
 786         struct s5h1411_state *state = fe->demodulator_priv;
 787
 788         p->frequency = state->current_frequency;
 789         p->u.vsb.modulation = state->current_modulation;
 790
 791         return 0;
 792 }
 793
 794 static int s5h1411_get_tune_settings(struct dvb_frontend *fe,
 795                                      struct dvb_frontend_tune_settings *tune)
 796 {
 797         tune->min_delay_ms = 1000;
 798         return 0;
 799 }
 800
 801 static void s5h1411_release(struct dvb_frontend *fe)
 802 {
 803         struct s5h1411_state *state = fe->demodulator_priv;
 804         kfree(state);
 805 }
 806
 807 static struct dvb_frontend_ops s5h1411_ops;
 808
 809 struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config,
 810                                     struct i2c_adapter *i2c)
 811 {
 812         struct s5h1411_state *state = NULL;
 813         u16 reg;
 814
 815         /* allocate memory for the internal state */
 816         state = kmalloc(sizeof(struct s5h1411_state), GFP_KERNEL);
 817         if (state == NULL)
 818                 goto error;
 819
 820         /* setup the state */
 821         state->config = config;
 822         state->i2c = i2c;
 823         state->current_modulation = VSB_8;
 824         state->inversion = state->config->inversion;
 825
 826         /* check if the demod exists */
 827         reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05);
 828         if (reg != 0x0066)
 829                 goto error;
 830
 831         /* create dvb_frontend */
 832         memcpy(&state->frontend.ops, &s5h1411_ops,
 833                sizeof(struct dvb_frontend_ops));
 834
 835         state->frontend.demodulator_priv = state;
 836
 837         if (s5h1411_init(&state->frontend) != 0) {
 838                 printk(KERN_ERR "%s: Failed to initialize correctly\n",
 839                         __func__);
 840                 goto error;
 841         }
 842
 843         /* Note: Leaving the I2C gate open here. */
 844         s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1);
 845
 846         return &state->frontend;
 847
 848 error:
 849         kfree(state);
 850         return NULL;
 851 }
 852 EXPORT_SYMBOL(s5h1411_attach);
 853
 854 static struct dvb_frontend_ops s5h1411_ops = {
 855
 856         .info = {
 857                 .name                   = "Samsung S5H1411 QAM/8VSB Frontend",
 858                 .type                   = FE_ATSC,
 859                 .frequency_min          = 54000000,
 860                 .frequency_max          = 858000000,
 861                 .frequency_stepsize     = 62500,
 862                 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
 863         },
 864
 865         .init                 = s5h1411_init,
 866         .i2c_gate_ctrl        = s5h1411_i2c_gate_ctrl,
 867         .set_frontend         = s5h1411_set_frontend,
 868         .get_frontend         = s5h1411_get_frontend,
 869         .get_tune_settings    = s5h1411_get_tune_settings,
 870         .read_status          = s5h1411_read_status,
 871         .read_ber             = s5h1411_read_ber,
 872         .read_signal_strength = s5h1411_read_signal_strength,
 873         .read_snr             = s5h1411_read_snr,
 874         .read_ucblocks        = s5h1411_read_ucblocks,
 875         .release              = s5h1411_release,
 876 };
 877
 878 module_param(debug, int, 0644);
 879 MODULE_PARM_DESC(debug, "Enable verbose debug messages");
 880
 881 MODULE_DESCRIPTION("Samsung S5H1411 QAM-B/ATSC Demodulator driver");
 882 MODULE_AUTHOR("Steven Toth");
 883 MODULE_LICENSE("GPL");
 884
 885 /*
 886  * Local variables:
 887  * c-basic-offset: 8
 888  */