2 * drxk_hard: DRX-K DVB-C/T demodulator driver
4 * Copyright (C) 2010-2011 Digital Devices GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <linux/version.h>
32 #include <asm/div64.h>
34 #include "dvb_frontend.h"
36 #include "drxk_hard.h"
38 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
39 static int PowerDownQAM(struct drxk_state *state);
40 static int SetDVBTStandard(struct drxk_state *state,
41 enum OperationMode oMode);
42 static int SetQAMStandard(struct drxk_state *state,
43 enum OperationMode oMode);
44 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
46 static int SetDVBTStandard(struct drxk_state *state,
47 enum OperationMode oMode);
48 static int DVBTStart(struct drxk_state *state);
49 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
51 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
53 static int SwitchAntennaToQAM(struct drxk_state *state);
54 static int SwitchAntennaToDVBT(struct drxk_state *state);
56 static bool IsDVBT(struct drxk_state *state)
58 return state->m_OperationMode == OM_DVBT;
61 static bool IsQAM(struct drxk_state *state)
63 return state->m_OperationMode == OM_QAM_ITU_A ||
64 state->m_OperationMode == OM_QAM_ITU_B ||
65 state->m_OperationMode == OM_QAM_ITU_C;
68 bool IsA1WithPatchCode(struct drxk_state *state)
70 return state->m_DRXK_A1_PATCH_CODE;
73 bool IsA1WithRomCode(struct drxk_state *state)
75 return state->m_DRXK_A1_ROM_CODE;
80 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
81 #define DRXDAP_FASI_LONG_FORMAT(addr) (((addr) & 0xFC30FF80) != 0)
83 #define DEFAULT_MER_83 165
84 #define DEFAULT_MER_93 250
86 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
87 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
90 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
91 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
94 #ifndef DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH
95 #define DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH (0x06)
98 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
99 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
101 #ifndef DRXK_KI_RAGC_ATV
102 #define DRXK_KI_RAGC_ATV 4
104 #ifndef DRXK_KI_IAGC_ATV
105 #define DRXK_KI_IAGC_ATV 6
107 #ifndef DRXK_KI_DAGC_ATV
108 #define DRXK_KI_DAGC_ATV 7
111 #ifndef DRXK_KI_RAGC_QAM
112 #define DRXK_KI_RAGC_QAM 3
114 #ifndef DRXK_KI_IAGC_QAM
115 #define DRXK_KI_IAGC_QAM 4
117 #ifndef DRXK_KI_DAGC_QAM
118 #define DRXK_KI_DAGC_QAM 7
120 #ifndef DRXK_KI_RAGC_DVBT
121 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
123 #ifndef DRXK_KI_IAGC_DVBT
124 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
126 #ifndef DRXK_KI_DAGC_DVBT
127 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
130 #ifndef DRXK_AGC_DAC_OFFSET
131 #define DRXK_AGC_DAC_OFFSET (0x800)
134 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
135 #define DRXK_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
138 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
139 #define DRXK_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
142 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
143 #define DRXK_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
146 #ifndef DRXK_QAM_SYMBOLRATE_MAX
147 #define DRXK_QAM_SYMBOLRATE_MAX (7233000)
150 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT 56
151 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A 64
152 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C 0x5FE0
153 #define DRXK_BL_ROM_OFFSET_TAPS_BG 24
154 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP 32
155 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC 40
156 #define DRXK_BL_ROM_OFFSET_TAPS_FM 48
157 #define DRXK_BL_ROM_OFFSET_UCODE 0
159 #define DRXK_BLC_TIMEOUT 100
161 #define DRXK_BLCC_NR_ELEMENTS_TAPS 2
162 #define DRXK_BLCC_NR_ELEMENTS_UCODE 6
164 #define DRXK_BLDC_NR_ELEMENTS_TAPS 28
166 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
167 #define DRXK_OFDM_NE_NOTCH_WIDTH (4)
170 #define DRXK_QAM_SL_SIG_POWER_QAM16 (40960)
171 #define DRXK_QAM_SL_SIG_POWER_QAM32 (20480)
172 #define DRXK_QAM_SL_SIG_POWER_QAM64 (43008)
173 #define DRXK_QAM_SL_SIG_POWER_QAM128 (20992)
174 #define DRXK_QAM_SL_SIG_POWER_QAM256 (43520)
176 static unsigned int debug;
177 module_param(debug, int, 0644);
178 MODULE_PARM_DESC(debug, "enable debug messages");
180 #define dprintk(level, fmt, arg...) do { \
181 if (debug >= level) \
182 printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg); \
186 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
190 tmp64 = (u64) a * (u64) b;
196 inline u32 Frac28a(u32 a, u32 c)
202 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
203 Q1 = a / c; /* integer part, only the 4 least significant bits
204 will be visible in the result */
206 /* division using radix 16, 7 nibbles in the result */
207 for (i = 0; i < 7; i++) {
208 Q1 = (Q1 << 4) | (R0 / c);
218 static u32 Log10Times100(u32 x)
220 static const u8 scale = 15;
221 static const u8 indexWidth = 5;
228 log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
229 0 <= n < ((1<<INDEXWIDTH)+1)
232 static const u32 log2lut[] = {
234 290941, /* 290941.300628 */
235 573196, /* 573196.476418 */
236 847269, /* 847269.179851 */
237 1113620, /* 1113620.489452 */
238 1372674, /* 1372673.576986 */
239 1624818, /* 1624817.752104 */
240 1870412, /* 1870411.981536 */
241 2109788, /* 2109787.962654 */
242 2343253, /* 2343252.817465 */
243 2571091, /* 2571091.461923 */
244 2793569, /* 2793568.696416 */
245 3010931, /* 3010931.055901 */
246 3223408, /* 3223408.452106 */
247 3431216, /* 3431215.635215 */
248 3634553, /* 3634553.498355 */
249 3833610, /* 3833610.244726 */
250 4028562, /* 4028562.434393 */
251 4219576, /* 4219575.925308 */
252 4406807, /* 4406806.721144 */
253 4590402, /* 4590401.736809 */
254 4770499, /* 4770499.491025 */
255 4947231, /* 4947230.734179 */
256 5120719, /* 5120719.018555 */
257 5291081, /* 5291081.217197 */
258 5458428, /* 5458427.996830 */
259 5622864, /* 5622864.249668 */
260 5784489, /* 5784489.488298 */
261 5943398, /* 5943398.207380 */
262 6099680, /* 6099680.215452 */
263 6253421, /* 6253420.939751 */
264 6404702, /* 6404701.706649 */
265 6553600, /* 6553600.000000 */
272 /* Scale x (normalize) */
273 /* computing y in log(x/y) = log(x) - log(y) */
274 if ((x & ((0xffffffff) << (scale + 1))) == 0) {
275 for (k = scale; k > 0; k--) {
276 if (x & (((u32) 1) << scale))
281 for (k = scale; k < 31; k++) {
282 if ((x & (((u32) (-1)) << (scale + 1))) == 0)
288 Now x has binary point between bit[scale] and bit[scale-1]
289 and 1.0 <= x < 2.0 */
291 /* correction for divison: log(x) = log(x/y)+log(y) */
292 y = k * ((((u32) 1) << scale) * 200);
294 /* remove integer part */
295 x &= ((((u32) 1) << scale) - 1);
297 i = (u8) (x >> (scale - indexWidth));
298 /* compute delta (x - a) */
299 d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
300 /* compute log, multiplication (d* (..)) must be within range ! */
302 ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
303 /* Conver to log10() */
304 y /= 108853; /* (log2(10) << scale) */
312 /****************************************************************************/
313 /* I2C **********************************************************************/
314 /****************************************************************************/
316 static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
318 struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
319 .buf = val, .len = 1}
322 return i2c_transfer(adapter, msgs, 1);
325 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
328 struct i2c_msg msg = {
329 .addr = adr, .flags = 0, .buf = data, .len = len };
334 for (i = 0; i < len; i++)
335 printk(KERN_CONT " %02x", data[i]);
336 printk(KERN_CONT "\n");
338 status = i2c_transfer(adap, &msg, 1);
339 if (status >= 0 && status != 1)
343 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
348 static int i2c_read(struct i2c_adapter *adap,
349 u8 adr, u8 *msg, int len, u8 *answ, int alen)
352 struct i2c_msg msgs[2] = {
353 {.addr = adr, .flags = 0,
354 .buf = msg, .len = len},
355 {.addr = adr, .flags = I2C_M_RD,
356 .buf = answ, .len = alen}
359 status = i2c_transfer(adap, msgs, 2);
362 printk(KERN_CONT ": ERROR!\n");
366 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
371 dprintk(2, ": read from");
372 for (i = 0; i < len; i++)
373 printk(KERN_CONT " %02x", msg[i]);
374 printk(KERN_CONT ", value = ");
375 for (i = 0; i < alen; i++)
376 printk(KERN_CONT " %02x", answ[i]);
377 printk(KERN_CONT "\n");
382 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
385 u8 adr = state->demod_address, mm1[4], mm2[2], len;
387 if (state->single_master)
390 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
391 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
392 mm1[1] = ((reg >> 16) & 0xFF);
393 mm1[2] = ((reg >> 24) & 0xFF) | flags;
394 mm1[3] = ((reg >> 7) & 0xFF);
397 mm1[0] = ((reg << 1) & 0xFF);
398 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
401 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
402 status = i2c_read(state->i2c, adr, mm1, len, mm2, 2);
406 *data = mm2[0] | (mm2[1] << 8);
411 static int read16(struct drxk_state *state, u32 reg, u16 *data)
413 return read16_flags(state, reg, data, 0);
416 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
419 u8 adr = state->demod_address, mm1[4], mm2[4], len;
421 if (state->single_master)
424 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
425 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
426 mm1[1] = ((reg >> 16) & 0xFF);
427 mm1[2] = ((reg >> 24) & 0xFF) | flags;
428 mm1[3] = ((reg >> 7) & 0xFF);
431 mm1[0] = ((reg << 1) & 0xFF);
432 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
435 dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
436 status = i2c_read(state->i2c, adr, mm1, len, mm2, 4);
440 *data = mm2[0] | (mm2[1] << 8) |
441 (mm2[2] << 16) | (mm2[3] << 24);
446 static int read32(struct drxk_state *state, u32 reg, u32 *data)
448 return read32_flags(state, reg, data, 0);
451 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
453 u8 adr = state->demod_address, mm[6], len;
455 if (state->single_master)
457 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
458 mm[0] = (((reg << 1) & 0xFF) | 0x01);
459 mm[1] = ((reg >> 16) & 0xFF);
460 mm[2] = ((reg >> 24) & 0xFF) | flags;
461 mm[3] = ((reg >> 7) & 0xFF);
464 mm[0] = ((reg << 1) & 0xFF);
465 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
468 mm[len] = data & 0xff;
469 mm[len + 1] = (data >> 8) & 0xff;
471 dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
472 return i2c_write(state->i2c, adr, mm, len + 2);
475 static int write16(struct drxk_state *state, u32 reg, u16 data)
477 return write16_flags(state, reg, data, 0);
480 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
482 u8 adr = state->demod_address, mm[8], len;
484 if (state->single_master)
486 if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
487 mm[0] = (((reg << 1) & 0xFF) | 0x01);
488 mm[1] = ((reg >> 16) & 0xFF);
489 mm[2] = ((reg >> 24) & 0xFF) | flags;
490 mm[3] = ((reg >> 7) & 0xFF);
493 mm[0] = ((reg << 1) & 0xFF);
494 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
497 mm[len] = data & 0xff;
498 mm[len + 1] = (data >> 8) & 0xff;
499 mm[len + 2] = (data >> 16) & 0xff;
500 mm[len + 3] = (data >> 24) & 0xff;
501 dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
503 return i2c_write(state->i2c, adr, mm, len + 4);
506 static int write32(struct drxk_state *state, u32 reg, u32 data)
508 return write32_flags(state, reg, data, 0);
511 static int write_block(struct drxk_state *state, u32 Address,
512 const int BlockSize, const u8 pBlock[])
514 int status = 0, BlkSize = BlockSize;
517 if (state->single_master)
520 while (BlkSize > 0) {
521 int Chunk = BlkSize > state->m_ChunkSize ?
522 state->m_ChunkSize : BlkSize;
523 u8 *AdrBuf = &state->Chunk[0];
526 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
527 AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
528 AdrBuf[1] = ((Address >> 16) & 0xFF);
529 AdrBuf[2] = ((Address >> 24) & 0xFF);
530 AdrBuf[3] = ((Address >> 7) & 0xFF);
533 if (Chunk == state->m_ChunkSize)
536 AdrBuf[0] = ((Address << 1) & 0xFF);
537 AdrBuf[1] = (((Address >> 16) & 0x0F) |
538 ((Address >> 18) & 0xF0));
541 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
542 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
546 for (i = 0; i < Chunk; i++)
547 printk(KERN_CONT " %02x", pBlock[i]);
548 printk(KERN_CONT "\n");
550 status = i2c_write(state->i2c, state->demod_address,
551 &state->Chunk[0], Chunk + AdrLength);
553 printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
558 Address += (Chunk >> 1);
564 #ifndef DRXK_MAX_RETRIES_POWERUP
565 #define DRXK_MAX_RETRIES_POWERUP 20
568 int PowerUpDevice(struct drxk_state *state)
576 status = i2c_read1(state->i2c, state->demod_address, &data);
580 status = i2c_write(state->i2c, state->demod_address,
586 status = i2c_read1(state->i2c, state->demod_address,
588 } while (status < 0 &&
589 (retryCount < DRXK_MAX_RETRIES_POWERUP));
590 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
594 /* Make sure all clk domains are active */
595 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
598 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
601 /* Enable pll lock tests */
602 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
606 state->m_currentPowerMode = DRX_POWER_UP;
610 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
616 static int init_state(struct drxk_state *state)
619 * FIXME: most (all?) of the values bellow should be moved into
620 * struct drxk_config, as they are probably board-specific
622 u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
623 u32 ulVSBIfAgcOutputLevel = 0;
624 u32 ulVSBIfAgcMinLevel = 0;
625 u32 ulVSBIfAgcMaxLevel = 0x7FFF;
626 u32 ulVSBIfAgcSpeed = 3;
628 u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
629 u32 ulVSBRfAgcOutputLevel = 0;
630 u32 ulVSBRfAgcMinLevel = 0;
631 u32 ulVSBRfAgcMaxLevel = 0x7FFF;
632 u32 ulVSBRfAgcSpeed = 3;
633 u32 ulVSBRfAgcTop = 9500;
634 u32 ulVSBRfAgcCutOffCurrent = 4000;
636 u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
637 u32 ulATVIfAgcOutputLevel = 0;
638 u32 ulATVIfAgcMinLevel = 0;
639 u32 ulATVIfAgcMaxLevel = 0;
640 u32 ulATVIfAgcSpeed = 3;
642 u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
643 u32 ulATVRfAgcOutputLevel = 0;
644 u32 ulATVRfAgcMinLevel = 0;
645 u32 ulATVRfAgcMaxLevel = 0;
646 u32 ulATVRfAgcTop = 9500;
647 u32 ulATVRfAgcCutOffCurrent = 4000;
648 u32 ulATVRfAgcSpeed = 3;
650 u32 ulQual83 = DEFAULT_MER_83;
651 u32 ulQual93 = DEFAULT_MER_93;
653 u32 ulDVBTStaticTSClock = 1;
654 u32 ulDVBCStaticTSClock = 1;
656 u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
657 u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
659 /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
660 /* io_pad_cfg_mode output mode is drive always */
661 /* io_pad_cfg_drive is set to power 2 (23 mA) */
662 u32 ulGPIOCfg = 0x0113;
663 u32 ulInvertTSClock = 0;
664 u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
665 u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH;
666 u32 ulDVBTBitrate = 50000000;
667 u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
669 u32 ulInsertRSByte = 0;
676 state->m_hasLNA = false;
677 state->m_hasDVBT = false;
678 state->m_hasDVBC = false;
679 state->m_hasATV = false;
680 state->m_hasOOB = false;
681 state->m_hasAudio = false;
683 if (!state->m_ChunkSize)
684 state->m_ChunkSize = 124;
686 state->m_oscClockFreq = 0;
687 state->m_smartAntInverted = false;
688 state->m_bPDownOpenBridge = false;
690 /* real system clock frequency in kHz */
691 state->m_sysClockFreq = 151875;
692 /* Timing div, 250ns/Psys */
693 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
694 state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
695 HI_I2C_DELAY) / 1000;
697 if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
698 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
699 state->m_HICfgWakeUpKey = (state->demod_address << 1);
700 /* port/bridge/power down ctrl */
701 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
703 state->m_bPowerDown = (ulPowerDown != 0);
705 state->m_DRXK_A1_PATCH_CODE = false;
706 state->m_DRXK_A1_ROM_CODE = false;
707 state->m_DRXK_A2_ROM_CODE = false;
708 state->m_DRXK_A3_ROM_CODE = false;
709 state->m_DRXK_A2_PATCH_CODE = false;
710 state->m_DRXK_A3_PATCH_CODE = false;
712 /* Init AGC and PGA parameters */
714 state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
715 state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
716 state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
717 state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
718 state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
719 state->m_vsbPgaCfg = 140;
722 state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
723 state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
724 state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
725 state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
726 state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
727 state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
728 state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
729 state->m_vsbPreSawCfg.reference = 0x07;
730 state->m_vsbPreSawCfg.usePreSaw = true;
732 state->m_Quality83percent = DEFAULT_MER_83;
733 state->m_Quality93percent = DEFAULT_MER_93;
734 if (ulQual93 <= 500 && ulQual83 < ulQual93) {
735 state->m_Quality83percent = ulQual83;
736 state->m_Quality93percent = ulQual93;
740 state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
741 state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
742 state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
743 state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
744 state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
747 state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
748 state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
749 state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
750 state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
751 state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
752 state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
753 state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
754 state->m_atvPreSawCfg.reference = 0x04;
755 state->m_atvPreSawCfg.usePreSaw = true;
759 state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
760 state->m_dvbtRfAgcCfg.outputLevel = 0;
761 state->m_dvbtRfAgcCfg.minOutputLevel = 0;
762 state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
763 state->m_dvbtRfAgcCfg.top = 0x2100;
764 state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
765 state->m_dvbtRfAgcCfg.speed = 1;
769 state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
770 state->m_dvbtIfAgcCfg.outputLevel = 0;
771 state->m_dvbtIfAgcCfg.minOutputLevel = 0;
772 state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
773 state->m_dvbtIfAgcCfg.top = 13424;
774 state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
775 state->m_dvbtIfAgcCfg.speed = 3;
776 state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
777 state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
778 /* state->m_dvbtPgaCfg = 140; */
780 state->m_dvbtPreSawCfg.reference = 4;
781 state->m_dvbtPreSawCfg.usePreSaw = false;
784 state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
785 state->m_qamRfAgcCfg.outputLevel = 0;
786 state->m_qamRfAgcCfg.minOutputLevel = 6023;
787 state->m_qamRfAgcCfg.maxOutputLevel = 27000;
788 state->m_qamRfAgcCfg.top = 0x2380;
789 state->m_qamRfAgcCfg.cutOffCurrent = 4000;
790 state->m_qamRfAgcCfg.speed = 3;
793 state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
794 state->m_qamIfAgcCfg.outputLevel = 0;
795 state->m_qamIfAgcCfg.minOutputLevel = 0;
796 state->m_qamIfAgcCfg.maxOutputLevel = 9000;
797 state->m_qamIfAgcCfg.top = 0x0511;
798 state->m_qamIfAgcCfg.cutOffCurrent = 0;
799 state->m_qamIfAgcCfg.speed = 3;
800 state->m_qamIfAgcCfg.IngainTgtMax = 5119;
801 state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
803 state->m_qamPgaCfg = 140;
804 state->m_qamPreSawCfg.reference = 4;
805 state->m_qamPreSawCfg.usePreSaw = false;
807 state->m_OperationMode = OM_NONE;
808 state->m_DrxkState = DRXK_UNINITIALIZED;
810 /* MPEG output configuration */
811 state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */
812 state->m_insertRSByte = false; /* If TRUE; insert RS byte */
813 state->m_invertDATA = false; /* If TRUE; invert DATA signals */
814 state->m_invertERR = false; /* If TRUE; invert ERR signal */
815 state->m_invertSTR = false; /* If TRUE; invert STR signals */
816 state->m_invertVAL = false; /* If TRUE; invert VAL signals */
817 state->m_invertCLK = (ulInvertTSClock != 0); /* If TRUE; invert CLK signals */
818 state->m_DVBTStaticCLK = (ulDVBTStaticTSClock != 0);
819 state->m_DVBCStaticCLK = (ulDVBCStaticTSClock != 0);
820 /* If TRUE; static MPEG clockrate will be used;
821 otherwise clockrate will adapt to the bitrate of the TS */
823 state->m_DVBTBitrate = ulDVBTBitrate;
824 state->m_DVBCBitrate = ulDVBCBitrate;
826 state->m_TSDataStrength = (ulTSDataStrength & 0x07);
827 state->m_TSClockkStrength = (ulTSClockkStrength & 0x07);
829 /* Maximum bitrate in b/s in case static clockrate is selected */
830 state->m_mpegTsStaticBitrate = 19392658;
831 state->m_disableTEIhandling = false;
834 state->m_insertRSByte = true;
836 state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
837 if (ulMpegLockTimeOut < 10000)
838 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
839 state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
840 if (ulDemodLockTimeOut < 10000)
841 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
844 state->m_Constellation = DRX_CONSTELLATION_AUTO;
845 state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
846 state->m_fecRsPlen = 204 * 8; /* fecRsPlen annex A */
847 state->m_fecRsPrescale = 1;
849 state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
850 state->m_agcFastClipCtrlDelay = 0;
852 state->m_GPIOCfg = (ulGPIOCfg);
854 state->m_bPowerDown = false;
855 state->m_currentPowerMode = DRX_POWER_DOWN;
857 state->m_rfmirror = (ulRfMirror == 0);
858 state->m_IfAgcPol = false;
862 static int DRXX_Open(struct drxk_state *state)
870 /* stop lock indicator process */
871 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
874 /* Check device id */
875 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
878 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
881 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
884 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
887 status = write16(state, SIO_TOP_COMM_KEY__A, key);
890 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
894 static int GetDeviceCapabilities(struct drxk_state *state)
896 u16 sioPdrOhwCfg = 0;
897 u32 sioTopJtagidLo = 0;
899 const char *spin = "";
904 /* stop lock indicator process */
905 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
908 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
911 status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
914 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
918 switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
920 /* ignore (bypass ?) */
924 state->m_oscClockFreq = 27000;
928 state->m_oscClockFreq = 20250;
932 state->m_oscClockFreq = 20250;
935 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
939 Determine device capabilities
942 status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
946 printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo);
949 switch ((sioTopJtagidLo >> 29) & 0xF) {
951 state->m_deviceSpin = DRXK_SPIN_A1;
955 state->m_deviceSpin = DRXK_SPIN_A2;
959 state->m_deviceSpin = DRXK_SPIN_A3;
963 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
965 printk(KERN_ERR "drxk: Spin %d unknown\n",
966 (sioTopJtagidLo >> 29) & 0xF);
969 switch ((sioTopJtagidLo >> 12) & 0xFF) {
971 /* typeId = DRX3913K_TYPE_ID */
972 state->m_hasLNA = false;
973 state->m_hasOOB = false;
974 state->m_hasATV = false;
975 state->m_hasAudio = false;
976 state->m_hasDVBT = true;
977 state->m_hasDVBC = true;
978 state->m_hasSAWSW = true;
979 state->m_hasGPIO2 = false;
980 state->m_hasGPIO1 = false;
981 state->m_hasIRQN = false;
984 /* typeId = DRX3915K_TYPE_ID */
985 state->m_hasLNA = false;
986 state->m_hasOOB = false;
987 state->m_hasATV = true;
988 state->m_hasAudio = false;
989 state->m_hasDVBT = true;
990 state->m_hasDVBC = false;
991 state->m_hasSAWSW = true;
992 state->m_hasGPIO2 = true;
993 state->m_hasGPIO1 = true;
994 state->m_hasIRQN = false;
997 /* typeId = DRX3916K_TYPE_ID */
998 state->m_hasLNA = false;
999 state->m_hasOOB = false;
1000 state->m_hasATV = true;
1001 state->m_hasAudio = false;
1002 state->m_hasDVBT = true;
1003 state->m_hasDVBC = false;
1004 state->m_hasSAWSW = true;
1005 state->m_hasGPIO2 = true;
1006 state->m_hasGPIO1 = true;
1007 state->m_hasIRQN = false;
1010 /* typeId = DRX3918K_TYPE_ID */
1011 state->m_hasLNA = false;
1012 state->m_hasOOB = false;
1013 state->m_hasATV = true;
1014 state->m_hasAudio = true;
1015 state->m_hasDVBT = true;
1016 state->m_hasDVBC = false;
1017 state->m_hasSAWSW = true;
1018 state->m_hasGPIO2 = true;
1019 state->m_hasGPIO1 = true;
1020 state->m_hasIRQN = false;
1023 /* typeId = DRX3921K_TYPE_ID */
1024 state->m_hasLNA = false;
1025 state->m_hasOOB = false;
1026 state->m_hasATV = true;
1027 state->m_hasAudio = true;
1028 state->m_hasDVBT = true;
1029 state->m_hasDVBC = true;
1030 state->m_hasSAWSW = true;
1031 state->m_hasGPIO2 = true;
1032 state->m_hasGPIO1 = true;
1033 state->m_hasIRQN = false;
1036 /* typeId = DRX3923K_TYPE_ID */
1037 state->m_hasLNA = false;
1038 state->m_hasOOB = false;
1039 state->m_hasATV = true;
1040 state->m_hasAudio = true;
1041 state->m_hasDVBT = true;
1042 state->m_hasDVBC = true;
1043 state->m_hasSAWSW = true;
1044 state->m_hasGPIO2 = true;
1045 state->m_hasGPIO1 = true;
1046 state->m_hasIRQN = false;
1049 /* typeId = DRX3925K_TYPE_ID */
1050 state->m_hasLNA = false;
1051 state->m_hasOOB = false;
1052 state->m_hasATV = true;
1053 state->m_hasAudio = true;
1054 state->m_hasDVBT = true;
1055 state->m_hasDVBC = true;
1056 state->m_hasSAWSW = true;
1057 state->m_hasGPIO2 = true;
1058 state->m_hasGPIO1 = true;
1059 state->m_hasIRQN = false;
1062 /* typeId = DRX3926K_TYPE_ID */
1063 state->m_hasLNA = false;
1064 state->m_hasOOB = false;
1065 state->m_hasATV = true;
1066 state->m_hasAudio = false;
1067 state->m_hasDVBT = true;
1068 state->m_hasDVBC = true;
1069 state->m_hasSAWSW = true;
1070 state->m_hasGPIO2 = true;
1071 state->m_hasGPIO1 = true;
1072 state->m_hasIRQN = false;
1075 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1076 ((sioTopJtagidLo >> 12) & 0xFF));
1082 "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1083 ((sioTopJtagidLo >> 12) & 0xFF), spin,
1084 state->m_oscClockFreq / 1000,
1085 state->m_oscClockFreq % 1000);
1089 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1095 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1103 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1106 if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1110 (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1111 ((state->m_HICfgCtrl) &
1112 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1113 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1114 if (powerdown_cmd == false) {
1115 /* Wait until command rdy */
1122 status = read16(state, SIO_HI_RA_RAM_CMD__A,
1124 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1128 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1132 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1137 static int HI_CfgCommand(struct drxk_state *state)
1143 mutex_lock(&state->mutex);
1145 status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1148 status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1151 status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1154 status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1157 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1160 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1163 status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1167 state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1169 mutex_unlock(&state->mutex);
1171 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1175 static int InitHI(struct drxk_state *state)
1179 state->m_HICfgWakeUpKey = (state->demod_address << 1);
1180 state->m_HICfgTimeout = 0x96FF;
1181 /* port/bridge/power down ctrl */
1182 state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1184 return HI_CfgCommand(state);
1187 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1190 u16 sioPdrMclkCfg = 0;
1191 u16 sioPdrMdxCfg = 0;
1193 dprintk(1, ": mpeg %s, %s mode\n",
1194 mpegEnable ? "enable" : "disable",
1195 state->m_enableParallel ? "parallel" : "serial");
1197 /* stop lock indicator process */
1198 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1202 /* MPEG TS pad configuration */
1203 status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1207 if (mpegEnable == false) {
1208 /* Set MPEG TS pads to inputmode */
1209 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1212 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1215 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1218 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1221 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1224 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1227 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1230 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1233 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1236 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1239 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1242 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1246 /* Enable MPEG output */
1248 ((state->m_TSDataStrength <<
1249 SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1250 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1251 SIO_PDR_MCLK_CFG_DRIVE__B) |
1254 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1257 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000); /* Disable */
1260 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000); /* Disable */
1263 if (state->m_enableParallel == true) {
1264 /* paralel -> enable MD1 to MD7 */
1265 status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1268 status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1271 status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1274 status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1277 status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1280 status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1283 status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1287 sioPdrMdxCfg = ((state->m_TSDataStrength <<
1288 SIO_PDR_MD0_CFG_DRIVE__B)
1290 /* serial -> disable MD1 to MD7 */
1291 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1294 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1297 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1300 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1303 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1306 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1309 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1313 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1316 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1320 /* Enable MB output over MPEG pads and ctl input */
1321 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1324 /* Write nomagic word to enable pdr reg write */
1325 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1328 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1332 static int MPEGTSDisable(struct drxk_state *state)
1336 return MPEGTSConfigurePins(state, false);
1339 static int BLChainCmd(struct drxk_state *state,
1340 u16 romOffset, u16 nrOfElements, u32 timeOut)
1347 mutex_lock(&state->mutex);
1348 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1351 status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1354 status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1357 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1361 end = jiffies + msecs_to_jiffies(timeOut);
1364 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1367 } while ((blStatus == 0x1) &&
1368 ((time_is_after_jiffies(end))));
1370 if (blStatus == 0x1) {
1371 printk(KERN_ERR "drxk: SIO not ready\n");
1377 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1379 mutex_unlock(&state->mutex);
1384 static int DownloadMicrocode(struct drxk_state *state,
1385 const u8 pMCImage[], u32 Length)
1387 const u8 *pSrc = pMCImage;
1400 /* down the drain (we don care about MAGIC_WORD) */
1401 Drain = (pSrc[0] << 8) | pSrc[1];
1402 pSrc += sizeof(u16);
1403 offset += sizeof(u16);
1404 nBlocks = (pSrc[0] << 8) | pSrc[1];
1405 pSrc += sizeof(u16);
1406 offset += sizeof(u16);
1408 for (i = 0; i < nBlocks; i += 1) {
1409 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1410 (pSrc[2] << 8) | pSrc[3];
1411 pSrc += sizeof(u32);
1412 offset += sizeof(u32);
1414 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1415 pSrc += sizeof(u16);
1416 offset += sizeof(u16);
1418 Flags = (pSrc[0] << 8) | pSrc[1];
1419 pSrc += sizeof(u16);
1420 offset += sizeof(u16);
1422 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1423 pSrc += sizeof(u16);
1424 offset += sizeof(u16);
1426 if (offset + BlockSize > Length) {
1427 printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1431 status = write_block(state, Address, BlockSize, pSrc);
1433 printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1437 offset += BlockSize;
1442 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1446 u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1447 u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1452 if (enable == false) {
1453 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1454 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1457 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1458 if (status >= 0 && data == desiredStatus) {
1459 /* tokenring already has correct status */
1462 /* Disable/enable dvbt tokenring bridge */
1463 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1465 end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1467 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1468 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1472 if (data != desiredStatus) {
1473 printk(KERN_ERR "drxk: SIO not ready\n");
1479 static int MPEGTSStop(struct drxk_state *state)
1482 u16 fecOcSncMode = 0;
1483 u16 fecOcIprMode = 0;
1487 /* Gracefull shutdown (byte boundaries) */
1488 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1491 fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1492 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1496 /* Suppress MCLK during absence of data */
1497 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1500 fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1501 status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1505 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1510 static int scu_command(struct drxk_state *state,
1511 u16 cmd, u8 parameterLen,
1512 u16 *parameter, u8 resultLen, u16 *result)
1514 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1515 #error DRXK register mapping no longer compatible with this routine!
1518 int status = -EINVAL;
1527 if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1528 ((resultLen > 0) && (result == NULL)))
1531 mutex_lock(&state->mutex);
1533 /* assume that the command register is ready
1534 since it is checked afterwards */
1535 for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1536 buffer[cnt++] = (parameter[ii] & 0xFF);
1537 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1539 buffer[cnt++] = (cmd & 0xFF);
1540 buffer[cnt++] = ((cmd >> 8) & 0xFF);
1542 write_block(state, SCU_RAM_PARAM_0__A -
1543 (parameterLen - 1), cnt, buffer);
1544 /* Wait until SCU has processed command */
1545 end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1548 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1551 } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1552 if (curCmd != DRX_SCU_READY) {
1553 printk(KERN_ERR "drxk: SCU not ready\n");
1558 if ((resultLen > 0) && (result != NULL)) {
1562 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1563 status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1568 /* Check if an error was reported by SCU */
1569 err = (s16)result[0];
1573 /* check for the known error codes */
1575 case SCU_RESULT_UNKCMD:
1576 p = "SCU_RESULT_UNKCMD";
1578 case SCU_RESULT_UNKSTD:
1579 p = "SCU_RESULT_UNKSTD";
1581 case SCU_RESULT_SIZE:
1582 p = "SCU_RESULT_SIZE";
1584 case SCU_RESULT_INVPAR:
1585 p = "SCU_RESULT_INVPAR";
1587 default: /* Other negative values are errors */
1588 sprintf(errname, "ERROR: %d\n", err);
1591 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1592 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1599 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1601 mutex_unlock(&state->mutex);
1605 static int SetIqmAf(struct drxk_state *state, bool active)
1613 status = read16(state, IQM_AF_STDBY__A, &data);
1618 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1619 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1620 | IQM_AF_STDBY_STDBY_PD_STANDBY
1621 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1622 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1624 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1625 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1626 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1627 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1628 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1631 status = write16(state, IQM_AF_STDBY__A, data);
1635 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1639 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1642 u16 sioCcPwdMode = 0;
1646 /* Check arguments */
1652 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1654 case DRXK_POWER_DOWN_OFDM:
1655 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1657 case DRXK_POWER_DOWN_CORE:
1658 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1660 case DRXK_POWER_DOWN_PLL:
1661 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1663 case DRX_POWER_DOWN:
1664 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1667 /* Unknow sleep mode */
1671 /* If already in requested power mode, do nothing */
1672 if (state->m_currentPowerMode == *mode)
1675 /* For next steps make sure to start from DRX_POWER_UP mode */
1676 if (state->m_currentPowerMode != DRX_POWER_UP) {
1677 status = PowerUpDevice(state);
1680 status = DVBTEnableOFDMTokenRing(state, true);
1685 if (*mode == DRX_POWER_UP) {
1686 /* Restore analog & pin configuartion */
1688 /* Power down to requested mode */
1689 /* Backup some register settings */
1690 /* Set pins with possible pull-ups connected
1691 to them in input mode */
1692 /* Analog power down */
1693 /* ADC power down */
1694 /* Power down device */
1695 /* stop all comm_exec */
1696 /* Stop and power down previous standard */
1697 switch (state->m_OperationMode) {
1699 status = MPEGTSStop(state);
1702 status = PowerDownDVBT(state, false);
1708 status = MPEGTSStop(state);
1711 status = PowerDownQAM(state);
1718 status = DVBTEnableOFDMTokenRing(state, false);
1721 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1724 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1728 if (*mode != DRXK_POWER_DOWN_OFDM) {
1729 state->m_HICfgCtrl |=
1730 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1731 status = HI_CfgCommand(state);
1736 state->m_currentPowerMode = *mode;
1740 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1745 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1747 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1754 status = read16(state, SCU_COMM_EXEC__A, &data);
1757 if (data == SCU_COMM_EXEC_ACTIVE) {
1758 /* Send OFDM stop command */
1759 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1762 /* Send OFDM reset command */
1763 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1768 /* Reset datapath for OFDM, processors first */
1769 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1772 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1775 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1780 status = SetIqmAf(state, false);
1784 /* powerdown to OFDM mode */
1786 status = CtrlPowerMode(state, &powerMode);
1792 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1796 static int SetOperationMode(struct drxk_state *state,
1797 enum OperationMode oMode)
1803 Stop and power down previous standard
1804 TODO investigate total power down instead of partial
1805 power down depending on "previous" standard.
1808 /* disable HW lock indicator */
1809 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1813 /* Device is already at the required mode */
1814 if (state->m_OperationMode == oMode)
1817 switch (state->m_OperationMode) {
1818 /* OM_NONE was added for start up */
1822 status = MPEGTSStop(state);
1825 status = PowerDownDVBT(state, true);
1828 state->m_OperationMode = OM_NONE;
1830 case OM_QAM_ITU_A: /* fallthrough */
1832 status = MPEGTSStop(state);
1835 status = PowerDownQAM(state);
1838 state->m_OperationMode = OM_NONE;
1847 Power up new standard
1851 dprintk(1, ": DVB-T\n");
1852 state->m_OperationMode = oMode;
1853 status = SetDVBTStandard(state, oMode);
1857 case OM_QAM_ITU_A: /* fallthrough */
1859 dprintk(1, ": DVB-C Annex %c\n",
1860 (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1861 state->m_OperationMode = oMode;
1862 status = SetQAMStandard(state, oMode);
1872 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1876 static int Start(struct drxk_state *state, s32 offsetFreq,
1877 s32 IntermediateFrequency)
1879 int status = -EINVAL;
1882 s32 OffsetkHz = offsetFreq / 1000;
1885 if (state->m_DrxkState != DRXK_STOPPED &&
1886 state->m_DrxkState != DRXK_DTV_STARTED)
1889 state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1891 if (IntermediateFrequency < 0) {
1892 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1893 IntermediateFrequency = -IntermediateFrequency;
1896 switch (state->m_OperationMode) {
1899 IFreqkHz = (IntermediateFrequency / 1000);
1900 status = SetQAM(state, IFreqkHz, OffsetkHz);
1903 state->m_DrxkState = DRXK_DTV_STARTED;
1906 IFreqkHz = (IntermediateFrequency / 1000);
1907 status = MPEGTSStop(state);
1910 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1913 status = DVBTStart(state);
1916 state->m_DrxkState = DRXK_DTV_STARTED;
1923 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1927 static int ShutDown(struct drxk_state *state)
1935 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1938 int status = -EINVAL;
1942 if (pLockStatus == NULL)
1945 *pLockStatus = NOT_LOCKED;
1947 /* define the SCU command code */
1948 switch (state->m_OperationMode) {
1952 status = GetQAMLockStatus(state, pLockStatus);
1955 status = GetDVBTLockStatus(state, pLockStatus);
1962 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1966 static int MPEGTSStart(struct drxk_state *state)
1970 u16 fecOcSncMode = 0;
1972 /* Allow OC to sync again */
1973 status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1976 fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1977 status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1980 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1983 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1987 static int MPEGTSDtoInit(struct drxk_state *state)
1993 /* Rate integration settings */
1994 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1997 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
2000 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
2003 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2006 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2009 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2012 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2015 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2019 /* Additional configuration */
2020 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2023 status = write16(state, FEC_OC_SNC_LWM__A, 2);
2026 status = write16(state, FEC_OC_SNC_HWM__A, 12);
2029 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2034 static int MPEGTSDtoSetup(struct drxk_state *state,
2035 enum OperationMode oMode)
2039 u16 fecOcRegMode = 0; /* FEC_OC_MODE register value */
2040 u16 fecOcRegIprMode = 0; /* FEC_OC_IPR_MODE register value */
2041 u16 fecOcDtoMode = 0; /* FEC_OC_IPR_INVERT register value */
2042 u16 fecOcFctMode = 0; /* FEC_OC_IPR_INVERT register value */
2043 u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2044 u16 fecOcDtoBurstLen = 188; /* FEC_OC_IPR_INVERT register value */
2045 u32 fecOcRcnCtlRate = 0; /* FEC_OC_IPR_INVERT register value */
2046 u16 fecOcTmdMode = 0;
2047 u16 fecOcTmdIntUpdRate = 0;
2049 bool staticCLK = false;
2053 /* Check insertion of the Reed-Solomon parity bytes */
2054 status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2057 status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2060 fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2061 fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2062 if (state->m_insertRSByte == true) {
2063 /* enable parity symbol forward */
2064 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2065 /* MVAL disable during parity bytes */
2066 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2067 /* TS burst length to 204 */
2068 fecOcDtoBurstLen = 204;
2071 /* Check serial or parrallel output */
2072 fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2073 if (state->m_enableParallel == false) {
2074 /* MPEG data output is serial -> set ipr_mode[0] */
2075 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2080 maxBitRate = state->m_DVBTBitrate;
2082 fecOcRcnCtlRate = 0xC00000;
2083 staticCLK = state->m_DVBTStaticCLK;
2085 case OM_QAM_ITU_A: /* fallthrough */
2087 fecOcTmdMode = 0x0004;
2088 fecOcRcnCtlRate = 0xD2B4EE; /* good for >63 Mb/s */
2089 maxBitRate = state->m_DVBCBitrate;
2090 staticCLK = state->m_DVBCStaticCLK;
2094 } /* switch (standard) */
2098 /* Configure DTO's */
2102 /* Rational DTO for MCLK source (static MCLK rate),
2103 Dynamic DTO for optimal grouping
2104 (avoid intra-packet gaps),
2105 DTO offset enable to sync TS burst with MSTRT */
2106 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2107 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2108 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2109 FEC_OC_FCT_MODE_VIRT_ENA__M);
2111 /* Check user defined bitrate */
2112 bitRate = maxBitRate;
2113 if (bitRate > 75900000UL) { /* max is 75.9 Mb/s */
2114 bitRate = 75900000UL;
2116 /* Rational DTO period:
2117 dto_period = (Fsys / bitrate) - 2
2119 Result should be floored,
2120 to make sure >= requested bitrate
2122 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2124 if (fecOcDtoPeriod <= 2)
2127 fecOcDtoPeriod -= 2;
2128 fecOcTmdIntUpdRate = 8;
2130 /* (commonAttr->staticCLK == false) => dynamic mode */
2131 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2132 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2133 fecOcTmdIntUpdRate = 5;
2136 /* Write appropriate registers with requested configuration */
2137 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2140 status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2143 status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2146 status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2149 status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2152 status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2156 /* Rate integration settings */
2157 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2160 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2163 status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2166 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2170 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2172 u16 fecOcRegIprInvert = 0;
2174 /* Data mask for the output data byte */
2175 u16 InvertDataMask =
2176 FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2177 FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2178 FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2179 FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2183 /* Control selective inversion of output bits */
2184 fecOcRegIprInvert &= (~(InvertDataMask));
2185 if (state->m_invertDATA == true)
2186 fecOcRegIprInvert |= InvertDataMask;
2187 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2188 if (state->m_invertERR == true)
2189 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2190 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2191 if (state->m_invertSTR == true)
2192 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2193 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2194 if (state->m_invertVAL == true)
2195 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2196 fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2197 if (state->m_invertCLK == true)
2198 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2200 return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2203 #define SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2205 static int SetAgcRf(struct drxk_state *state,
2206 struct SCfgAgc *pAgcCfg, bool isDTV)
2208 int status = -EINVAL;
2210 struct SCfgAgc *pIfAgcSettings;
2214 if (pAgcCfg == NULL)
2217 switch (pAgcCfg->ctrlMode) {
2218 case DRXK_AGC_CTRL_AUTO:
2219 /* Enable RF AGC DAC */
2220 status = read16(state, IQM_AF_STDBY__A, &data);
2223 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2224 status = write16(state, IQM_AF_STDBY__A, data);
2227 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2231 /* Enable SCU RF AGC loop */
2232 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2235 if (state->m_RfAgcPol)
2236 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2238 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2239 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2243 /* Set speed (using complementary reduction value) */
2244 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2248 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2249 data |= (~(pAgcCfg->speed <<
2250 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2251 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2253 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2258 pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2259 else if (IsQAM(state))
2260 pIfAgcSettings = &state->m_qamIfAgcCfg;
2262 pIfAgcSettings = &state->m_atvIfAgcCfg;
2263 if (pIfAgcSettings == NULL) {
2268 /* Set TOP, only if IF-AGC is in AUTO mode */
2269 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2270 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2274 /* Cut-Off current */
2275 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2279 /* Max. output level */
2280 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2286 case DRXK_AGC_CTRL_USER:
2287 /* Enable RF AGC DAC */
2288 status = read16(state, IQM_AF_STDBY__A, &data);
2291 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2292 status = write16(state, IQM_AF_STDBY__A, data);
2296 /* Disable SCU RF AGC loop */
2297 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2300 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2301 if (state->m_RfAgcPol)
2302 data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2304 data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2305 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2309 /* SCU c.o.c. to 0, enabling full control range */
2310 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2314 /* Write value to output pin */
2315 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2320 case DRXK_AGC_CTRL_OFF:
2321 /* Disable RF AGC DAC */
2322 status = read16(state, IQM_AF_STDBY__A, &data);
2325 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2326 status = write16(state, IQM_AF_STDBY__A, data);
2330 /* Disable SCU RF AGC loop */
2331 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2334 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2335 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2346 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2350 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2352 static int SetAgcIf(struct drxk_state *state,
2353 struct SCfgAgc *pAgcCfg, bool isDTV)
2357 struct SCfgAgc *pRfAgcSettings;
2361 switch (pAgcCfg->ctrlMode) {
2362 case DRXK_AGC_CTRL_AUTO:
2364 /* Enable IF AGC DAC */
2365 status = read16(state, IQM_AF_STDBY__A, &data);
2368 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2369 status = write16(state, IQM_AF_STDBY__A, data);
2373 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2377 /* Enable SCU IF AGC loop */
2378 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2381 if (state->m_IfAgcPol)
2382 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2384 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2385 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2389 /* Set speed (using complementary reduction value) */
2390 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2393 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2394 data |= (~(pAgcCfg->speed <<
2395 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2396 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2398 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2403 pRfAgcSettings = &state->m_qamRfAgcCfg;
2405 pRfAgcSettings = &state->m_atvRfAgcCfg;
2406 if (pRfAgcSettings == NULL)
2409 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2414 case DRXK_AGC_CTRL_USER:
2416 /* Enable IF AGC DAC */
2417 status = read16(state, IQM_AF_STDBY__A, &data);
2420 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2421 status = write16(state, IQM_AF_STDBY__A, data);
2425 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2429 /* Disable SCU IF AGC loop */
2430 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2433 if (state->m_IfAgcPol)
2434 data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2436 data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2437 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2441 /* Write value to output pin */
2442 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2447 case DRXK_AGC_CTRL_OFF:
2449 /* Disable If AGC DAC */
2450 status = read16(state, IQM_AF_STDBY__A, &data);
2453 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2454 status = write16(state, IQM_AF_STDBY__A, data);
2458 /* Disable SCU IF AGC loop */
2459 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2462 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2463 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2467 } /* switch (agcSettingsIf->ctrlMode) */
2469 /* always set the top to support
2470 configurations without if-loop */
2471 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2474 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2478 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2486 status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2488 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2494 if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2495 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2497 *pValue = (14000 - Level) / 4;
2504 static int GetQAMSignalToNoise(struct drxk_state *state,
2505 s32 *pSignalToNoise)
2508 u16 qamSlErrPower = 0; /* accum. error between
2509 raw and sliced symbols */
2510 u32 qamSlSigPower = 0; /* used for MER, depends of
2512 u32 qamSlMer = 0; /* QAM MER */
2516 /* MER calculation */
2518 /* get the register value needed for MER */
2519 status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2521 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2525 switch (state->props.modulation) {
2527 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2530 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2533 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2536 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2540 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2544 if (qamSlErrPower > 0) {
2545 qamSlMer = Log10Times100(qamSlSigPower) -
2546 Log10Times100((u32) qamSlErrPower);
2548 *pSignalToNoise = qamSlMer;
2553 static int GetDVBTSignalToNoise(struct drxk_state *state,
2554 s32 *pSignalToNoise)
2558 u32 EqRegTdSqrErrI = 0;
2559 u32 EqRegTdSqrErrQ = 0;
2560 u16 EqRegTdSqrErrExp = 0;
2561 u16 EqRegTdTpsPwrOfs = 0;
2562 u16 EqRegTdReqSmbCnt = 0;
2569 u16 transmissionParams = 0;
2573 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2576 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2579 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2582 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®Data);
2585 /* Extend SQR_ERR_I operational range */
2586 EqRegTdSqrErrI = (u32) regData;
2587 if ((EqRegTdSqrErrExp > 11) &&
2588 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2589 EqRegTdSqrErrI += 0x00010000UL;
2591 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®Data);
2594 /* Extend SQR_ERR_Q operational range */
2595 EqRegTdSqrErrQ = (u32) regData;
2596 if ((EqRegTdSqrErrExp > 11) &&
2597 (EqRegTdSqrErrQ < 0x00000FFFUL))
2598 EqRegTdSqrErrQ += 0x00010000UL;
2600 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2604 /* Check input data for MER */
2606 /* MER calculation (in 0.1 dB) without math.h */
2607 if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2609 else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2610 /* No error at all, this must be the HW reset value
2611 * Apparently no first measurement yet
2615 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2617 if ((transmissionParams &
2618 OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2619 == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2624 /* IMER = 100 * log10 (x)
2625 where x = (EqRegTdTpsPwrOfs^2 *
2626 EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2629 where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2630 b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2631 c = 100 * log10 (SqrErrIQ)
2634 /* log(x) x = 9bits * 9bits->18 bits */
2635 a = Log10Times100(EqRegTdTpsPwrOfs *
2637 /* log(x) x = 16bits * 7bits->23 bits */
2638 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2639 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */
2640 c = Log10Times100(SqrErrIQ);
2643 /* No negative MER, clip to zero */
2649 *pSignalToNoise = iMER;
2653 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2657 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2661 *pSignalToNoise = 0;
2662 switch (state->m_OperationMode) {
2664 return GetDVBTSignalToNoise(state, pSignalToNoise);
2667 return GetQAMSignalToNoise(state, pSignalToNoise);
2675 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2677 /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2682 static s32 QE_SN[] = {
2688 108, /* 16-QAM 1/2 */
2689 131, /* 16-QAM 2/3 */
2690 146, /* 16-QAM 3/4 */
2691 156, /* 16-QAM 5/6 */
2692 160, /* 16-QAM 7/8 */
2693 165, /* 64-QAM 1/2 */
2694 187, /* 64-QAM 2/3 */
2695 202, /* 64-QAM 3/4 */
2696 216, /* 64-QAM 5/6 */
2697 225, /* 64-QAM 7/8 */
2703 s32 SignalToNoise = 0;
2704 u16 Constellation = 0;
2706 u32 SignalToNoiseRel;
2709 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2712 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2715 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2717 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2720 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2722 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2723 CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2725 SignalToNoiseRel = SignalToNoise -
2726 QE_SN[Constellation * 5 + CodeRate];
2729 if (SignalToNoiseRel < -70)
2731 else if (SignalToNoiseRel < 30)
2732 *pQuality = ((SignalToNoiseRel + 70) *
2735 *pQuality = BERQuality;
2740 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2748 u32 SignalToNoise = 0;
2749 u32 BERQuality = 100;
2750 u32 SignalToNoiseRel = 0;
2752 status = GetQAMSignalToNoise(state, &SignalToNoise);
2756 switch (state->props.modulation) {
2758 SignalToNoiseRel = SignalToNoise - 200;
2761 SignalToNoiseRel = SignalToNoise - 230;
2762 break; /* Not in NorDig */
2764 SignalToNoiseRel = SignalToNoise - 260;
2767 SignalToNoiseRel = SignalToNoise - 290;
2771 SignalToNoiseRel = SignalToNoise - 320;
2775 if (SignalToNoiseRel < -70)
2777 else if (SignalToNoiseRel < 30)
2778 *pQuality = ((SignalToNoiseRel + 70) *
2781 *pQuality = BERQuality;
2787 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2791 switch (state->m_OperationMode) {
2793 return GetDVBTQuality(state, pQuality);
2795 return GetDVBCQuality(state, pQuality);
2804 /* Free data ram in SIO HI */
2805 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2806 #define SIO_HI_RA_RAM_USR_END__A 0x420060
2808 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2809 #define DRXK_HI_ATOMIC_BUF_END (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2810 #define DRXK_HI_ATOMIC_READ SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2811 #define DRXK_HI_ATOMIC_WRITE SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2813 #define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr) >> 22) & 0x3F)
2814 #define DRXDAP_FASI_ADDR2BANK(addr) (((addr) >> 16) & 0x3F)
2815 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2817 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2819 int status = -EINVAL;
2823 if (state->m_DrxkState == DRXK_UNINITIALIZED)
2825 if (state->m_DrxkState == DRXK_POWERED_DOWN)
2828 if (state->no_i2c_bridge)
2831 status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2834 if (bEnableBridge) {
2835 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2839 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2844 status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2848 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2852 static int SetPreSaw(struct drxk_state *state,
2853 struct SCfgPreSaw *pPreSawCfg)
2855 int status = -EINVAL;
2859 if ((pPreSawCfg == NULL)
2860 || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2863 status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2866 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2870 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2871 u16 romOffset, u16 nrOfElements, u32 timeOut)
2874 u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2875 u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2881 mutex_lock(&state->mutex);
2882 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2885 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2888 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2891 status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2894 status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2897 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2901 end = jiffies + msecs_to_jiffies(timeOut);
2903 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2906 } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2907 if (blStatus == 0x1) {
2908 printk(KERN_ERR "drxk: SIO not ready\n");
2914 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2916 mutex_unlock(&state->mutex);
2921 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2928 /* Start measurement */
2929 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2932 status = write16(state, IQM_AF_START_LOCK__A, 1);
2937 status = read16(state, IQM_AF_PHASE0__A, &data);
2941 *count = *count + 1;
2942 status = read16(state, IQM_AF_PHASE1__A, &data);
2946 *count = *count + 1;
2947 status = read16(state, IQM_AF_PHASE2__A, &data);
2951 *count = *count + 1;
2955 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2959 static int ADCSynchronization(struct drxk_state *state)
2966 status = ADCSyncMeasurement(state, &count);
2971 /* Try sampling on a diffrent edge */
2974 status = read16(state, IQM_AF_CLKNEG__A, &clkNeg);
2977 if ((clkNeg | IQM_AF_CLKNEG_CLKNEGDATA__M) ==
2978 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS) {
2979 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2981 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG;
2983 clkNeg &= (~(IQM_AF_CLKNEG_CLKNEGDATA__M));
2985 IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS;
2987 status = write16(state, IQM_AF_CLKNEG__A, clkNeg);
2990 status = ADCSyncMeasurement(state, &count);
2999 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3003 static int SetFrequencyShifter(struct drxk_state *state,
3004 u16 intermediateFreqkHz,
3005 s32 tunerFreqOffset, bool isDTV)
3007 bool selectPosImage = false;
3008 u32 rfFreqResidual = tunerFreqOffset;
3009 u32 fmFrequencyShift = 0;
3010 bool tunerMirror = !state->m_bMirrorFreqSpect;
3015 u32 samplingFrequency = (u32) (state->m_sysClockFreq / 3);
3022 Program frequency shifter
3023 No need to account for mirroring on RF
3026 if ((state->m_OperationMode == OM_QAM_ITU_A) ||
3027 (state->m_OperationMode == OM_QAM_ITU_C) ||
3028 (state->m_OperationMode == OM_DVBT))
3029 selectPosImage = true;
3031 selectPosImage = false;
3034 /* tuner doesn't mirror */
3035 ifFreqActual = intermediateFreqkHz +
3036 rfFreqResidual + fmFrequencyShift;
3039 ifFreqActual = intermediateFreqkHz -
3040 rfFreqResidual - fmFrequencyShift;
3041 if (ifFreqActual > samplingFrequency / 2) {
3043 adcFreq = samplingFrequency - ifFreqActual;
3046 /* adc doesn't mirror */
3047 adcFreq = ifFreqActual;
3051 frequencyShift = adcFreq;
3052 imageToSelect = state->m_rfmirror ^ tunerMirror ^
3053 adcFlip ^ selectPosImage;
3054 state->m_IqmFsRateOfs =
3055 Frac28a((frequencyShift), samplingFrequency);
3058 state->m_IqmFsRateOfs = ~state->m_IqmFsRateOfs + 1;
3060 /* Program frequency shifter with tuner offset compensation */
3061 /* frequencyShift += tunerFreqOffset; TODO */
3062 status = write32(state, IQM_FS_RATE_OFS_LO__A,
3063 state->m_IqmFsRateOfs);
3065 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3069 static int InitAGC(struct drxk_state *state, bool isDTV)
3072 u16 ingainTgtMin = 0;
3073 u16 ingainTgtMax = 0;
3081 u16 kiInnergainMin = 0;
3082 u16 ifIaccuHiTgt = 0;
3083 u16 ifIaccuHiTgtMin = 0;
3084 u16 ifIaccuHiTgtMax = 0;
3086 u16 fastClpCtrlDelay = 0;
3087 u16 clpCtrlMode = 0;
3092 /* Common settings */
3094 ifIaccuHiTgtMin = 2047;
3098 /* AGCInit() not available for DVBT; init done in microcode */
3099 if (!IsQAM(state)) {
3100 printk(KERN_ERR "drxk: %s: mode %d is not DVB-C\n", __func__, state->m_OperationMode);
3104 /* FIXME: Analog TV AGC require different settings */
3106 /* Standard specific settings */
3108 clpDirTo = (u16) -9;
3111 snsDirTo = (u16) -9;
3112 kiInnergainMin = (u16) -1030;
3113 ifIaccuHiTgtMax = 0x2380;
3114 ifIaccuHiTgt = 0x2380;
3115 ingainTgtMin = 0x0511;
3117 ingainTgtMax = 5119;
3118 fastClpCtrlDelay = state->m_qamIfAgcCfg.FastClipCtrlDelay;
3120 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fastClpCtrlDelay);
3124 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clpCtrlMode);
3127 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingainTgt);
3130 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingainTgtMin);
3133 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingainTgtMax);
3136 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, ifIaccuHiTgtMin);
3139 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, ifIaccuHiTgtMax);
3142 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3145 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3148 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3151 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3154 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clpSumMax);
3157 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, snsSumMax);
3161 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, kiInnergainMin);
3164 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, ifIaccuHiTgt);
3167 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clpCyclen);
3171 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3174 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3177 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3181 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3184 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clpSumMin);
3187 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, snsSumMin);
3190 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clpDirTo);
3193 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, snsDirTo);
3196 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3199 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3202 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3205 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3208 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3211 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3214 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3217 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3220 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3223 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3226 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3229 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3232 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3235 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3239 /* Initialize inner-loop KI gain factors */
3240 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3245 data &= ~SCU_RAM_AGC_KI_RF__M;
3246 data |= (DRXK_KI_RAGC_QAM << SCU_RAM_AGC_KI_RF__B);
3247 data &= ~SCU_RAM_AGC_KI_IF__M;
3248 data |= (DRXK_KI_IAGC_QAM << SCU_RAM_AGC_KI_IF__B);
3250 status = write16(state, SCU_RAM_AGC_KI__A, data);
3253 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3257 static int DVBTQAMGetAccPktErr(struct drxk_state *state, u16 *packetErr)
3262 if (packetErr == NULL)
3263 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3265 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packetErr);
3267 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3271 static int DVBTScCommand(struct drxk_state *state,
3272 u16 cmd, u16 subcmd,
3273 u16 param0, u16 param1, u16 param2,
3274 u16 param3, u16 param4)
3283 status = read16(state, OFDM_SC_COMM_EXEC__A, &scExec);
3285 /* SC is not running */
3291 /* Wait until sc is ready to receive command */
3295 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3297 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3298 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3301 /* Write sub-command */
3303 /* All commands using sub-cmd */
3304 case OFDM_SC_RA_RAM_CMD_PROC_START:
3305 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3306 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3307 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3316 /* Write needed parameters and the command */
3318 /* All commands using 5 parameters */
3319 /* All commands using 4 parameters */
3320 /* All commands using 3 parameters */
3321 /* All commands using 2 parameters */
3322 case OFDM_SC_RA_RAM_CMD_PROC_START:
3323 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3324 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3325 status = write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3326 /* All commands using 1 parameters */
3327 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3328 case OFDM_SC_RA_RAM_CMD_USER_IO:
3329 status = write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3330 /* All commands using 0 parameters */
3331 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3332 case OFDM_SC_RA_RAM_CMD_NULL:
3334 status = write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3337 /* Unknown command */
3343 /* Wait until sc is ready processing command */
3347 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &curCmd);
3349 } while ((curCmd != 0) && (retryCnt < DRXK_MAX_RETRIES));
3350 if (retryCnt >= DRXK_MAX_RETRIES && (status < 0))
3353 /* Check for illegal cmd */
3354 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &errCode);
3355 if (errCode == 0xFFFF) {
3356 /* illegal command */
3362 /* Retreive results parameters from SC */
3364 /* All commands yielding 5 results */
3365 /* All commands yielding 4 results */
3366 /* All commands yielding 3 results */
3367 /* All commands yielding 2 results */
3368 /* All commands yielding 1 result */
3369 case OFDM_SC_RA_RAM_CMD_USER_IO:
3370 case OFDM_SC_RA_RAM_CMD_GET_OP_PARAM:
3371 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3372 /* All commands yielding 0 results */
3373 case OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING:
3374 case OFDM_SC_RA_RAM_CMD_SET_TIMER:
3375 case OFDM_SC_RA_RAM_CMD_PROC_START:
3376 case OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM:
3377 case OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM:
3378 case OFDM_SC_RA_RAM_CMD_NULL:
3381 /* Unknown command */
3384 } /* switch (cmd->cmd) */
3387 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3391 static int PowerUpDVBT(struct drxk_state *state)
3393 enum DRXPowerMode powerMode = DRX_POWER_UP;
3397 status = CtrlPowerMode(state, &powerMode);
3399 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3403 static int DVBTCtrlSetIncEnable(struct drxk_state *state, bool *enabled)
3408 if (*enabled == true)
3409 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3411 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3413 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3417 #define DEFAULT_FR_THRES_8K 4000
3418 static int DVBTCtrlSetFrEnable(struct drxk_state *state, bool *enabled)
3424 if (*enabled == true) {
3425 /* write mask to 1 */
3426 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3427 DEFAULT_FR_THRES_8K);
3429 /* write mask to 0 */
3430 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3433 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3438 static int DVBTCtrlSetEchoThreshold(struct drxk_state *state,
3439 struct DRXKCfgDvbtEchoThres_t *echoThres)
3445 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3449 switch (echoThres->fftMode) {
3450 case DRX_FFTMODE_2K:
3451 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_2K__M;
3452 data |= ((echoThres->threshold <<
3453 OFDM_SC_RA_RAM_ECHO_THRES_2K__B)
3454 & (OFDM_SC_RA_RAM_ECHO_THRES_2K__M));
3456 case DRX_FFTMODE_8K:
3457 data &= ~OFDM_SC_RA_RAM_ECHO_THRES_8K__M;
3458 data |= ((echoThres->threshold <<
3459 OFDM_SC_RA_RAM_ECHO_THRES_8K__B)
3460 & (OFDM_SC_RA_RAM_ECHO_THRES_8K__M));
3466 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3469 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3473 static int DVBTCtrlSetSqiSpeed(struct drxk_state *state,
3474 enum DRXKCfgDvbtSqiSpeed *speed)
3476 int status = -EINVAL;
3481 case DRXK_DVBT_SQI_SPEED_FAST:
3482 case DRXK_DVBT_SQI_SPEED_MEDIUM:
3483 case DRXK_DVBT_SQI_SPEED_SLOW:
3488 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3492 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3496 /*============================================================================*/
3499 * \brief Activate DVBT specific presets
3500 * \param demod instance of demodulator.
3501 * \return DRXStatus_t.
3503 * Called in DVBTSetStandard
3506 static int DVBTActivatePresets(struct drxk_state *state)
3509 bool setincenable = false;
3510 bool setfrenable = true;
3512 struct DRXKCfgDvbtEchoThres_t echoThres2k = { 0, DRX_FFTMODE_2K };
3513 struct DRXKCfgDvbtEchoThres_t echoThres8k = { 0, DRX_FFTMODE_8K };
3516 status = DVBTCtrlSetIncEnable(state, &setincenable);
3519 status = DVBTCtrlSetFrEnable(state, &setfrenable);
3522 status = DVBTCtrlSetEchoThreshold(state, &echoThres2k);
3525 status = DVBTCtrlSetEchoThreshold(state, &echoThres8k);
3528 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbtIfAgcCfg.IngainTgtMax);
3531 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3535 /*============================================================================*/
3538 * \brief Initialize channelswitch-independent settings for DVBT.
3539 * \param demod instance of demodulator.
3540 * \return DRXStatus_t.
3542 * For ROM code channel filter taps are loaded from the bootloader. For microcode
3543 * the DVB-T taps from the drxk_filters.h are used.
3545 static int SetDVBTStandard(struct drxk_state *state,
3546 enum OperationMode oMode)
3555 /* added antenna switch */
3556 SwitchAntennaToDVBT(state);
3557 /* send OFDM reset command */
3558 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
3562 /* send OFDM setenv command */
3563 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmdResult);
3567 /* reset datapath for OFDM, processors first */
3568 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3571 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3574 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3579 /* synchronize on ofdstate->m_festart */
3580 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3583 /* window size for clipping ADC detection */
3584 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3587 /* window size for for sense pre-SAW detection */
3588 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3591 /* sense threshold for sense pre-SAW detection */
3592 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3595 status = SetIqmAf(state, true);
3599 status = write16(state, IQM_AF_AGC_RF__A, 0);
3603 /* Impulse noise cruncher setup */
3604 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3607 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3610 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3614 status = write16(state, IQM_RC_STRETCH__A, 16);
3617 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3620 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3623 status = write16(state, IQM_CF_SCALE__A, 1600);
3626 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3630 /* virtual clipping threshold for clipping ADC detection */
3631 status = write16(state, IQM_AF_CLP_TH__A, 448);
3634 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3638 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
3642 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3645 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3648 /* enable power measurement interrupt */
3649 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3652 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3656 /* IQM will not be reset from here, sync ADC and update/init AGC */
3657 status = ADCSynchronization(state);
3660 status = SetPreSaw(state, &state->m_dvbtPreSawCfg);
3664 /* Halt SCU to enable safe non-atomic accesses */
3665 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3669 status = SetAgcRf(state, &state->m_dvbtRfAgcCfg, true);
3672 status = SetAgcIf(state, &state->m_dvbtIfAgcCfg, true);
3676 /* Set Noise Estimation notch width and enable DC fix */
3677 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3680 data |= OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M;
3681 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3685 /* Activate SCU to enable SCU commands */
3686 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3690 if (!state->m_DRXK_A3_ROM_CODE) {
3691 /* AGCInit() is not done for DVBT, so set agcFastClipCtrlDelay */
3692 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbtIfAgcCfg.FastClipCtrlDelay);
3698 #ifdef COMPILE_FOR_NONRT
3699 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3702 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3708 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3713 #ifdef COMPILE_FOR_NONRT
3714 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3718 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3722 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3726 /* Setup MPEG bus */
3727 status = MPEGTSDtoSetup(state, OM_DVBT);
3730 /* Set DVBT Presets */
3731 status = DVBTActivatePresets(state);
3737 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3741 /*============================================================================*/
3743 * \brief Start dvbt demodulating for channel.
3744 * \param demod instance of demodulator.
3745 * \return DRXStatus_t.
3747 static int DVBTStart(struct drxk_state *state)
3751 /* DRXKOfdmScCmd_t scCmd; */
3754 /* Start correct processes to get in lock */
3755 /* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
3756 param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
3757 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
3761 status = MPEGTSStart(state);
3764 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3769 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
3774 /*============================================================================*/
3777 * \brief Set up dvbt demodulator for channel.
3778 * \param demod instance of demodulator.
3779 * \return DRXStatus_t.
3780 * // original DVBTSetChannel()
3782 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
3783 s32 tunerFreqOffset)
3786 u16 transmissionParams = 0;
3787 u16 operationMode = 0;
3788 u32 iqmRcRateOfs = 0;
3793 dprintk(1, "IF =%d, TFO = %d\n", IntermediateFreqkHz, tunerFreqOffset);
3795 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
3799 /* Halt SCU to enable safe non-atomic accesses */
3800 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3804 /* Stop processors */
3805 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3808 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3812 /* Mandatory fix, always stop CP, required to set spl offset back to
3813 hardware default (is set to 0 by ucode during pilot detection */
3814 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3818 /*== Write channel settings to device =====================================*/
3821 switch (state->props.transmission_mode) {
3822 case TRANSMISSION_MODE_AUTO:
3824 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M;
3825 /* fall through , try first guess DRX_FFTMODE_8K */
3826 case TRANSMISSION_MODE_8K:
3827 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_8K;
3829 case TRANSMISSION_MODE_2K:
3830 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_MODE_2K;
3835 switch (state->props.guard_interval) {
3837 case GUARD_INTERVAL_AUTO:
3838 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M;
3839 /* fall through , try first guess DRX_GUARD_1DIV4 */
3840 case GUARD_INTERVAL_1_4:
3841 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_4;
3843 case GUARD_INTERVAL_1_32:
3844 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_32;
3846 case GUARD_INTERVAL_1_16:
3847 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_16;
3849 case GUARD_INTERVAL_1_8:
3850 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_GUARD_8;
3855 switch (state->props.hierarchy) {
3856 case HIERARCHY_AUTO:
3857 case HIERARCHY_NONE:
3859 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_HIER__M;
3860 /* fall through , try first guess SC_RA_RAM_OP_PARAM_HIER_NO */
3861 /* transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_NO; */
3864 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A1;
3867 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A2;
3870 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_HIER_A4;
3876 switch (state->props.modulation) {
3879 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M;
3880 /* fall through , try first guess DRX_CONSTELLATION_QAM64 */
3882 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64;
3885 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK;
3888 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16;
3892 /* No hierachical channels support in BDA */
3893 /* Priority (only for hierarchical channels) */
3894 switch (channel->priority) {
3895 case DRX_PRIORITY_LOW:
3896 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO;
3897 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3898 OFDM_EC_SB_PRIOR_LO);
3900 case DRX_PRIORITY_HIGH:
3901 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3902 WR16(devAddr, OFDM_EC_SB_PRIOR__A,
3903 OFDM_EC_SB_PRIOR_HI));
3905 case DRX_PRIORITY_UNKNOWN: /* fall through */
3911 /* Set Priorty high */
3912 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI;
3913 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3919 switch (state->props.code_rate_HP) {
3922 operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M;
3923 /* fall through , try first guess DRX_CODERATE_2DIV3 */
3925 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3;
3928 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2;
3931 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4;
3934 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6;
3937 transmissionParams |= OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8;
3941 /* SAW filter selection: normaly not necesarry, but if wanted
3942 the application can select a SAW filter via the driver by using UIOs */
3943 /* First determine real bandwidth (Hz) */
3944 /* Also set delay for impulse noise cruncher */
3945 /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
3946 by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
3948 switch (state->props.bandwidth_hz) {
3950 state->props.bandwidth_hz = 8000000;
3953 bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
3954 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
3957 /* cochannel protection for PAL 8 MHz */
3958 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
3961 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
3964 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
3967 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3972 bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
3973 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
3976 /* cochannel protection for PAL 7 MHz */
3977 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
3980 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
3983 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
3986 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
3991 bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
3992 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
3995 /* cochannel protection for NTSC 6 MHz */
3996 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
3999 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
4002 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
4005 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
4014 if (iqmRcRateOfs == 0) {
4015 /* Now compute IQM_RC_RATE_OFS
4016 (((SysFreq/BandWidth)/2)/2) -1) * 2^23)
4018 ((SysFreq / BandWidth) * (2^21)) - (2^23)
4020 /* (SysFreq / BandWidth) * (2^28) */
4021 /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
4022 => assert(MAX(sysClk) < 16*MIN(bandwidth))
4023 => assert(109714272 > 48000000) = true so Frac 28 can be used */
4024 iqmRcRateOfs = Frac28a((u32)
4025 ((state->m_sysClockFreq *
4026 1000) / 3), bandwidth);
4027 /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
4028 if ((iqmRcRateOfs & 0x7fL) >= 0x40)
4029 iqmRcRateOfs += 0x80L;
4030 iqmRcRateOfs = iqmRcRateOfs >> 7;
4031 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */
4032 iqmRcRateOfs = iqmRcRateOfs - (1 << 23);
4036 ((((u32) IQM_RC_RATE_OFS_HI__M) <<
4037 IQM_RC_RATE_OFS_LO__W) | IQM_RC_RATE_OFS_LO__M);
4038 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRateOfs);
4042 /* Bandwidth setting done */
4045 status = DVBTSetFrequencyShift(demod, channel, tunerOffset);
4049 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
4053 /*== Start SC, write channel settings to SC ===============================*/
4055 /* Activate SCU to enable SCU commands */
4056 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
4060 /* Enable SC after setting all other parameters */
4061 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
4064 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4069 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
4073 /* Write SC parameter registers, set all AUTO flags in operation mode */
4074 param1 = (OFDM_SC_RA_RAM_OP_AUTO_MODE__M |
4075 OFDM_SC_RA_RAM_OP_AUTO_GUARD__M |
4076 OFDM_SC_RA_RAM_OP_AUTO_CONST__M |
4077 OFDM_SC_RA_RAM_OP_AUTO_HIER__M |
4078 OFDM_SC_RA_RAM_OP_AUTO_RATE__M);
4079 status = DVBTScCommand(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4080 0, transmissionParams, param1, 0, 0, 0);
4084 if (!state->m_DRXK_A3_ROM_CODE)
4085 status = DVBTCtrlSetSqiSpeed(state, &state->m_sqiSpeed);
4088 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4094 /*============================================================================*/
4097 * \brief Retreive lock status .
4098 * \param demod Pointer to demodulator instance.
4099 * \param lockStat Pointer to lock status structure.
4100 * \return DRXStatus_t.
4103 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus)
4106 const u16 mpeg_lock_mask = (OFDM_SC_RA_RAM_LOCK_MPEG__M |
4107 OFDM_SC_RA_RAM_LOCK_FEC__M);
4108 const u16 fec_lock_mask = (OFDM_SC_RA_RAM_LOCK_FEC__M);
4109 const u16 demod_lock_mask = OFDM_SC_RA_RAM_LOCK_DEMOD__M;
4111 u16 ScRaRamLock = 0;
4116 *pLockStatus = NOT_LOCKED;
4118 /* Check if SC is running */
4119 status = read16(state, OFDM_SC_COMM_EXEC__A, &ScCommExec);
4122 if (ScCommExec == OFDM_SC_COMM_EXEC_STOP)
4125 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &ScRaRamLock);
4129 if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask)
4130 *pLockStatus = MPEG_LOCK;
4131 else if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
4132 *pLockStatus = FEC_LOCK;
4133 else if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
4134 *pLockStatus = DEMOD_LOCK;
4135 else if (ScRaRamLock & OFDM_SC_RA_RAM_LOCK_NODVBT__M)
4136 *pLockStatus = NEVER_LOCK;
4139 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4144 static int PowerUpQAM(struct drxk_state *state)
4146 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
4150 status = CtrlPowerMode(state, &powerMode);
4152 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4158 /** Power Down QAM */
4159 static int PowerDownQAM(struct drxk_state *state)
4166 status = read16(state, SCU_COMM_EXEC__A, &data);
4169 if (data == SCU_COMM_EXEC_ACTIVE) {
4174 /* stop all comstate->m_exec */
4175 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4178 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
4183 status = SetIqmAf(state, false);
4187 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4192 /*============================================================================*/
4195 * \brief Setup of the QAM Measurement intervals for signal quality
4196 * \param demod instance of demod.
4197 * \param modulation current modulation.
4198 * \return DRXStatus_t.
4201 * Take into account that for certain settings the errorcounters can overflow.
4202 * The implementation does not check this.
4205 static int SetQAMMeasurement(struct drxk_state *state,
4206 enum EDrxkConstellation modulation,
4209 u32 fecBitsDesired = 0; /* BER accounting period */
4210 u32 fecRsPeriodTotal = 0; /* Total period */
4211 u16 fecRsPrescale = 0; /* ReedSolomon Measurement Prescale */
4212 u16 fecRsPeriod = 0; /* Value for corresponding I2C register */
4218 /* fecBitsDesired = symbolRate [kHz] *
4224 switch (modulation) {
4225 case DRX_CONSTELLATION_QAM16:
4226 fecBitsDesired = 4 * symbolRate;
4228 case DRX_CONSTELLATION_QAM32:
4229 fecBitsDesired = 5 * symbolRate;
4231 case DRX_CONSTELLATION_QAM64:
4232 fecBitsDesired = 6 * symbolRate;
4234 case DRX_CONSTELLATION_QAM128:
4235 fecBitsDesired = 7 * symbolRate;
4237 case DRX_CONSTELLATION_QAM256:
4238 fecBitsDesired = 8 * symbolRate;
4246 fecBitsDesired /= 1000; /* symbolRate [Hz] -> symbolRate [kHz] */
4247 fecBitsDesired *= 500; /* meas. period [ms] */
4249 /* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
4250 /* fecRsPeriodTotal = fecBitsDesired / 1632 */
4251 fecRsPeriodTotal = (fecBitsDesired / 1632UL) + 1; /* roughly ceil */
4253 /* fecRsPeriodTotal = fecRsPrescale * fecRsPeriod */
4254 fecRsPrescale = 1 + (u16) (fecRsPeriodTotal >> 16);
4255 if (fecRsPrescale == 0) {
4256 /* Divide by zero (though impossible) */
4262 ((u16) fecRsPeriodTotal +
4263 (fecRsPrescale >> 1)) / fecRsPrescale;
4265 /* write corresponding registers */
4266 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fecRsPeriod);
4269 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fecRsPrescale);
4272 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fecRsPeriod);
4275 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4279 static int SetQAM16(struct drxk_state *state)
4284 /* QAM Equalizer Setup */
4286 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4289 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4292 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4295 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4298 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4301 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4304 /* Decision Feedback Equalizer */
4305 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4308 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4311 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4314 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4317 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4320 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4324 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4327 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4330 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4334 /* QAM Slicer Settings */
4335 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
4339 /* QAM Loop Controller Coeficients */
4340 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4343 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4346 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4349 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4352 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4355 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4358 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4361 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4365 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4368 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4371 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4374 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4377 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4380 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4383 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4386 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4389 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4392 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4395 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4398 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4403 /* QAM State Machine (FSM) Thresholds */
4405 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4408 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4411 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4414 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4417 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4420 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4424 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4427 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4430 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4435 /* QAM FSM Tracking Parameters */
4437 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4440 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4443 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4446 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4449 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4452 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4455 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4461 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4465 /*============================================================================*/
4468 * \brief QAM32 specific setup
4469 * \param demod instance of demod.
4470 * \return DRXStatus_t.
4472 static int SetQAM32(struct drxk_state *state)
4478 /* QAM Equalizer Setup */
4480 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4483 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4486 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4489 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4492 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4495 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4499 /* Decision Feedback Equalizer */
4500 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4503 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4506 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4509 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4512 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4515 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4519 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4522 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4525 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4529 /* QAM Slicer Settings */
4531 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
4536 /* QAM Loop Controller Coeficients */
4538 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4541 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4544 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4547 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4550 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4553 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4556 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4559 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4563 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4566 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4569 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4572 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4575 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4578 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4581 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4584 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4587 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4590 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4593 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4596 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4601 /* QAM State Machine (FSM) Thresholds */
4603 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4606 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4609 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4612 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4615 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4618 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4622 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4625 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4628 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4633 /* QAM FSM Tracking Parameters */
4635 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4638 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4641 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4644 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4647 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4650 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4653 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4656 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4660 /*============================================================================*/
4663 * \brief QAM64 specific setup
4664 * \param demod instance of demod.
4665 * \return DRXStatus_t.
4667 static int SetQAM64(struct drxk_state *state)
4672 /* QAM Equalizer Setup */
4674 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4677 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4680 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4683 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4686 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4689 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4693 /* Decision Feedback Equalizer */
4694 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4697 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4700 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4703 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4706 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4709 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4713 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4716 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4719 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4723 /* QAM Slicer Settings */
4724 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
4729 /* QAM Loop Controller Coeficients */
4731 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4734 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4737 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4740 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4743 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4746 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4749 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4752 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4756 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4759 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4762 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4765 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4768 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4771 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4774 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4777 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4780 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4783 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4786 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4789 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4794 /* QAM State Machine (FSM) Thresholds */
4796 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4799 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4802 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4805 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4808 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4811 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4815 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4818 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4821 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4826 /* QAM FSM Tracking Parameters */
4828 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4831 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4834 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4837 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4840 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4843 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4846 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4849 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
4854 /*============================================================================*/
4857 * \brief QAM128 specific setup
4858 * \param demod: instance of demod.
4859 * \return DRXStatus_t.
4861 static int SetQAM128(struct drxk_state *state)
4866 /* QAM Equalizer Setup */
4868 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4871 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4874 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4877 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4880 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4883 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4887 /* Decision Feedback Equalizer */
4888 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4891 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4894 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4897 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4900 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4903 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4907 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4910 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4913 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4918 /* QAM Slicer Settings */
4920 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
4925 /* QAM Loop Controller Coeficients */
4927 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4930 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4933 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4936 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4939 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4942 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4945 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4948 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4952 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4955 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4958 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4961 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4964 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4967 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4970 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4973 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4976 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4979 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4982 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4985 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4990 /* QAM State Machine (FSM) Thresholds */
4992 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4995 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4998 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5001 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5004 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
5007 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
5011 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5014 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
5018 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5022 /* QAM FSM Tracking Parameters */
5024 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5027 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
5030 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
5033 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
5036 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
5039 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
5042 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
5045 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5050 /*============================================================================*/
5053 * \brief QAM256 specific setup
5054 * \param demod: instance of demod.
5055 * \return DRXStatus_t.
5057 static int SetQAM256(struct drxk_state *state)
5062 /* QAM Equalizer Setup */
5064 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5067 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5070 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5073 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5076 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5079 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5083 /* Decision Feedback Equalizer */
5084 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5087 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5090 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5093 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5096 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5099 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5103 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5106 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5109 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5113 /* QAM Slicer Settings */
5115 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
5120 /* QAM Loop Controller Coeficients */
5122 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5125 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5128 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5131 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5134 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5137 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5140 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5143 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5147 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5150 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5153 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5156 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5159 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5162 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5165 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5168 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5171 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5174 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5177 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5180 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5185 /* QAM State Machine (FSM) Thresholds */
5187 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5190 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5193 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5196 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5199 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5202 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5206 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5209 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5212 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5217 /* QAM FSM Tracking Parameters */
5219 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5222 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5225 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5228 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5231 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5234 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5237 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5240 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5245 /*============================================================================*/
5247 * \brief Reset QAM block.
5248 * \param demod: instance of demod.
5249 * \param channel: pointer to channel data.
5250 * \return DRXStatus_t.
5252 static int QAMResetQAM(struct drxk_state *state)
5258 /* Stop QAM comstate->m_exec */
5259 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5263 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
5266 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5270 /*============================================================================*/
5273 * \brief Set QAM symbolrate.
5274 * \param demod: instance of demod.
5275 * \param channel: pointer to channel data.
5276 * \return DRXStatus_t.
5278 static int QAMSetSymbolrate(struct drxk_state *state)
5280 u32 adcFrequency = 0;
5288 /* Select & calculate correct IQM rate */
5289 adcFrequency = (state->m_sysClockFreq * 1000) / 3;
5291 /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */
5292 if (state->props.symbol_rate <= 1188750)
5294 else if (state->props.symbol_rate <= 2377500)
5296 else if (state->props.symbol_rate <= 4755000)
5298 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5303 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23)
5305 symbFreq = state->props.symbol_rate * (1 << ratesel);
5306 if (symbFreq == 0) {
5307 /* Divide by zero */
5311 iqmRcRate = (adcFrequency / symbFreq) * (1 << 21) +
5312 (Frac28a((adcFrequency % symbFreq), symbFreq) >> 7) -
5314 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqmRcRate);
5317 state->m_iqmRcRate = iqmRcRate;
5319 LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15))
5321 symbFreq = state->props.symbol_rate;
5322 if (adcFrequency == 0) {
5323 /* Divide by zero */
5327 lcSymbRate = (symbFreq / adcFrequency) * (1 << 12) +
5328 (Frac28a((symbFreq % adcFrequency), adcFrequency) >>
5330 if (lcSymbRate > 511)
5332 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lcSymbRate);
5336 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5340 /*============================================================================*/
5343 * \brief Get QAM lock status.
5344 * \param demod: instance of demod.
5345 * \param channel: pointer to channel data.
5346 * \return DRXStatus_t.
5349 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus)
5352 u16 Result[2] = { 0, 0 };
5355 *pLockStatus = NOT_LOCKED;
5356 status = scu_command(state,
5357 SCU_RAM_COMMAND_STANDARD_QAM |
5358 SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK, 0, NULL, 2,
5361 printk(KERN_ERR "drxk: %s status = %08x\n", __func__, status);
5363 if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED) {
5364 /* 0x0000 NOT LOCKED */
5365 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_LOCKED) {
5366 /* 0x4000 DEMOD LOCKED */
5367 *pLockStatus = DEMOD_LOCK;
5368 } else if (Result[1] < SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK) {
5369 /* 0x8000 DEMOD + FEC LOCKED (system lock) */
5370 *pLockStatus = MPEG_LOCK;
5372 /* 0xC000 NEVER LOCKED */
5373 /* (system will never be able to lock to the signal) */
5374 /* TODO: check this, intermediate & standard specific lock states are not
5375 taken into account here */
5376 *pLockStatus = NEVER_LOCK;
5381 #define QAM_MIRROR__M 0x03
5382 #define QAM_MIRROR_NORMAL 0x00
5383 #define QAM_MIRRORED 0x01
5384 #define QAM_MIRROR_AUTO_ON 0x02
5385 #define QAM_LOCKRANGE__M 0x10
5386 #define QAM_LOCKRANGE_NORMAL 0x10
5388 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
5389 s32 tunerFreqOffset)
5392 u16 setParamParameters[4] = { 0, 0, 0, 0 };
5397 * STEP 1: reset demodulator
5398 * resets FEC DI and FEC RS
5400 * resets SCU variables
5402 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5405 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5408 status = QAMResetQAM(state);
5413 * STEP 2: configure demodulator
5414 * -set params; resets IQM,QAM,FEC HW; initializes some
5417 status = QAMSetSymbolrate(state);
5422 switch (state->props.modulation) {
5424 state->m_Constellation = DRX_CONSTELLATION_QAM256;
5428 state->m_Constellation = DRX_CONSTELLATION_QAM64;
5431 state->m_Constellation = DRX_CONSTELLATION_QAM16;
5434 state->m_Constellation = DRX_CONSTELLATION_QAM32;
5437 state->m_Constellation = DRX_CONSTELLATION_QAM128;
5445 setParamParameters[0] = state->m_Constellation; /* modulation */
5446 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5447 if (state->m_OperationMode == OM_QAM_ITU_C)
5448 setParamParameters[2] = QAM_TOP_ANNEX_C;
5450 setParamParameters[2] = QAM_TOP_ANNEX_A;
5451 setParamParameters[3] |= (QAM_MIRROR_AUTO_ON);
5452 /* Env parameters */
5453 /* check for LOCKRANGE Extented */
5454 /* setParamParameters[3] |= QAM_LOCKRANGE_NORMAL; */
5456 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 4, setParamParameters, 1, &cmdResult);
5458 /* Fall-back to the simpler call */
5459 if (state->m_OperationMode == OM_QAM_ITU_C)
5460 setParamParameters[0] = QAM_TOP_ANNEX_C;
5462 setParamParameters[0] = QAM_TOP_ANNEX_A;
5463 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 1, setParamParameters, 1, &cmdResult);
5467 setParamParameters[0] = state->m_Constellation; /* modulation */
5468 setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */
5469 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult);
5475 * STEP 3: enable the system in a mode where the ADC provides valid
5476 * signal setup modulation independent registers
5479 status = SetFrequency(channel, tunerFreqOffset));
5483 status = SetFrequencyShifter(state, IntermediateFreqkHz, tunerFreqOffset, true);
5487 /* Setup BER measurement */
5488 status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate);
5492 /* Reset default values */
5493 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5496 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5500 /* Reset default LC values */
5501 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5504 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5507 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5510 status = write16(state, QAM_LC_MODE__A, 7);
5514 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5517 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5520 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5523 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5526 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5529 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5532 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5535 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5538 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5541 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5544 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5547 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5550 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5553 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5556 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5560 /* Mirroring, QAM-block starting point not inverted */
5561 status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
5565 /* Halt SCU to enable safe non-atomic accesses */
5566 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5570 /* STEP 4: modulation specific setup */
5571 switch (state->props.modulation) {
5573 status = SetQAM16(state);
5576 status = SetQAM32(state);
5580 status = SetQAM64(state);
5583 status = SetQAM128(state);
5586 status = SetQAM256(state);
5595 /* Activate SCU to enable SCU commands */
5596 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5600 /* Re-configure MPEG output, requires knowledge of channel bitrate */
5601 /* extAttr->currentChannel.modulation = channel->modulation; */
5602 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */
5603 status = MPEGTSDtoSetup(state, state->m_OperationMode);
5607 /* Start processes */
5608 status = MPEGTSStart(state);
5611 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5614 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5617 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5621 /* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
5622 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmdResult);
5626 /* update global DRXK data container */
5627 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */
5631 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5635 static int SetQAMStandard(struct drxk_state *state,
5636 enum OperationMode oMode)
5639 #ifdef DRXK_QAM_TAPS
5640 #define DRXK_QAMA_TAPS_SELECT
5641 #include "drxk_filters.h"
5642 #undef DRXK_QAMA_TAPS_SELECT
5647 /* added antenna switch */
5648 SwitchAntennaToQAM(state);
5650 /* Ensure correct power-up mode */
5651 status = PowerUpQAM(state);
5654 /* Reset QAM block */
5655 status = QAMResetQAM(state);
5661 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5664 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5668 /* Upload IQM Channel Filter settings by
5669 boot loader from ROM table */
5672 status = BLChainCmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5675 status = BLDirectCmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5678 status = BLDirectCmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
5686 status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
5689 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5692 status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
5696 status = write16(state, IQM_RC_STRETCH__A, 21);
5699 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5702 status = write16(state, IQM_AF_CLP_TH__A, 448);
5705 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5708 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5712 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5715 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5718 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5721 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5725 /* IQM Impulse Noise Processing Unit */
5726 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5729 status = write16(state, IQM_CF_DATATH__A, 1000);
5732 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5735 status = write16(state, IQM_CF_DET_LCT__A, 0);
5738 status = write16(state, IQM_CF_WND_LEN__A, 1);
5741 status = write16(state, IQM_CF_PKDTH__A, 1);
5744 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5748 /* turn on IQMAF. Must be done before setAgc**() */
5749 status = SetIqmAf(state, true);
5752 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5756 /* IQM will not be reset from here, sync ADC and update/init AGC */
5757 status = ADCSynchronization(state);
5761 /* Set the FSM step period */
5762 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5766 /* Halt SCU to enable safe non-atomic accesses */
5767 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5771 /* No more resets of the IQM, current standard correctly set =>
5772 now AGCs can be configured. */
5774 status = InitAGC(state, true);
5777 status = SetPreSaw(state, &(state->m_qamPreSawCfg));
5781 /* Configure AGC's */
5782 status = SetAgcRf(state, &(state->m_qamRfAgcCfg), true);
5785 status = SetAgcIf(state, &(state->m_qamIfAgcCfg), true);
5789 /* Activate SCU to enable SCU commands */
5790 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5793 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5797 static int WriteGPIO(struct drxk_state *state)
5803 /* stop lock indicator process */
5804 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
5808 /* Write magic word to enable pdr reg write */
5809 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5813 if (state->m_hasSAWSW) {
5814 if (state->UIO_mask & 0x0001) { /* UIO-1 */
5815 /* write to io pad configuration register - output mode */
5816 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5820 /* use corresponding bit in io data output registar */
5821 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5824 if ((state->m_GPIO & 0x0001) == 0)
5825 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */
5827 value |= 0x8000; /* write one to 15th bit - 1st UIO */
5828 /* write back to io data output register */
5829 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5833 if (state->UIO_mask & 0x0002) { /* UIO-2 */
5834 /* write to io pad configuration register - output mode */
5835 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5839 /* use corresponding bit in io data output registar */
5840 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5843 if ((state->m_GPIO & 0x0002) == 0)
5844 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */
5846 value |= 0x4000; /* write one to 14th bit - 2st UIO */
5847 /* write back to io data output register */
5848 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5852 if (state->UIO_mask & 0x0004) { /* UIO-3 */
5853 /* write to io pad configuration register - output mode */
5854 status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_GPIOCfg);
5858 /* use corresponding bit in io data output registar */
5859 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5862 if ((state->m_GPIO & 0x0004) == 0)
5863 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */
5865 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */
5866 /* write back to io data output register */
5867 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5872 /* Write magic word to disable pdr reg write */
5873 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5876 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5880 static int SwitchAntennaToQAM(struct drxk_state *state)
5887 if (!state->antenna_gpio)
5890 gpio_state = state->m_GPIO & state->antenna_gpio;
5892 if (state->antenna_dvbt ^ gpio_state) {
5893 /* Antenna is on DVB-T mode. Switch */
5894 if (state->antenna_dvbt)
5895 state->m_GPIO &= ~state->antenna_gpio;
5897 state->m_GPIO |= state->antenna_gpio;
5898 status = WriteGPIO(state);
5901 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5905 static int SwitchAntennaToDVBT(struct drxk_state *state)
5912 if (!state->antenna_gpio)
5915 gpio_state = state->m_GPIO & state->antenna_gpio;
5917 if (!(state->antenna_dvbt ^ gpio_state)) {
5918 /* Antenna is on DVB-C mode. Switch */
5919 if (state->antenna_dvbt)
5920 state->m_GPIO |= state->antenna_gpio;
5922 state->m_GPIO &= ~state->antenna_gpio;
5923 status = WriteGPIO(state);
5926 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5931 static int PowerDownDevice(struct drxk_state *state)
5933 /* Power down to requested mode */
5934 /* Backup some register settings */
5935 /* Set pins with possible pull-ups connected to them in input mode */
5936 /* Analog power down */
5937 /* ADC power down */
5938 /* Power down device */
5942 if (state->m_bPDownOpenBridge) {
5943 /* Open I2C bridge before power down of DRXK */
5944 status = ConfigureI2CBridge(state, true);
5949 status = DVBTEnableOFDMTokenRing(state, false);
5953 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
5956 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5959 state->m_HICfgCtrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5960 status = HI_CfgCommand(state);
5963 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
5968 static int load_microcode(struct drxk_state *state, const char *mc_name)
5970 const struct firmware *fw = NULL;
5975 err = request_firmware(&fw, mc_name, state->i2c->dev.parent);
5978 "drxk: Could not load firmware file %s.\n", mc_name);
5980 "drxk: Copy %s to your hotplug directory!\n", mc_name);
5983 err = DownloadMicrocode(state, fw->data, fw->size);
5984 release_firmware(fw);
5988 static int init_drxk(struct drxk_state *state)
5991 enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
5995 if ((state->m_DrxkState == DRXK_UNINITIALIZED)) {
5996 status = PowerUpDevice(state);
5999 status = DRXX_Open(state);
6002 /* Soft reset of OFDM-, sys- and osc-clockdomain */
6003 status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
6006 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6009 /* TODO is this needed, if yes how much delay in worst case scenario */
6011 state->m_DRXK_A3_PATCH_CODE = true;
6012 status = GetDeviceCapabilities(state);
6016 /* Bridge delay, uses oscilator clock */
6017 /* Delay = (delay (nano seconds) * oscclk (kHz))/ 1000 */
6018 /* SDA brdige delay */
6019 state->m_HICfgBridgeDelay =
6020 (u16) ((state->m_oscClockFreq / 1000) *
6021 HI_I2C_BRIDGE_DELAY) / 1000;
6023 if (state->m_HICfgBridgeDelay >
6024 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M) {
6025 state->m_HICfgBridgeDelay =
6026 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M;
6028 /* SCL bridge delay, same as SDA for now */
6029 state->m_HICfgBridgeDelay +=
6030 state->m_HICfgBridgeDelay <<
6031 SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B;
6033 status = InitHI(state);
6036 /* disable various processes */
6038 if (!(state->m_DRXK_A1_ROM_CODE)
6039 && !(state->m_DRXK_A2_ROM_CODE))
6042 status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
6047 /* disable MPEG port */
6048 status = MPEGTSDisable(state);
6052 /* Stop AUD and SCU */
6053 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6056 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6060 /* enable token-ring bus through OFDM block for possible ucode upload */
6061 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
6065 /* include boot loader section */
6066 status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
6069 status = BLChainCmd(state, 0, 6, 100);
6073 if (!state->microcode_name)
6074 load_microcode(state, "drxk_a3.mc");
6076 load_microcode(state, state->microcode_name);
6078 /* disable token-ring bus through OFDM block for possible ucode upload */
6079 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
6083 /* Run SCU for a little while to initialize microcode version numbers */
6084 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6087 status = DRXX_Open(state);
6090 /* added for test */
6093 powerMode = DRXK_POWER_DOWN_OFDM;
6094 status = CtrlPowerMode(state, &powerMode);
6098 /* Stamp driver version number in SCU data RAM in BCD code
6099 Done to enable field application engineers to retreive drxdriver version
6100 via I2C from SCU RAM.
6101 Not using SCU command interface for SCU register access since no
6102 microcode may be present.
6105 (((DRXK_VERSION_MAJOR / 100) % 10) << 12) +
6106 (((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
6107 ((DRXK_VERSION_MAJOR % 10) << 4) +
6108 (DRXK_VERSION_MINOR % 10);
6109 status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driverVersion);
6113 (((DRXK_VERSION_PATCH / 1000) % 10) << 12) +
6114 (((DRXK_VERSION_PATCH / 100) % 10) << 8) +
6115 (((DRXK_VERSION_PATCH / 10) % 10) << 4) +
6116 (DRXK_VERSION_PATCH % 10);
6117 status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driverVersion);
6121 printk(KERN_INFO "DRXK driver version %d.%d.%d\n",
6122 DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
6123 DRXK_VERSION_PATCH);
6125 /* Dirty fix of default values for ROM/PATCH microcode
6126 Dirty because this fix makes it impossible to setup suitable values
6127 before calling DRX_Open. This solution requires changes to RF AGC speed
6128 to be done via the CTRL function after calling DRX_Open */
6130 /* m_dvbtRfAgcCfg.speed = 3; */
6132 /* Reset driver debug flags to 0 */
6133 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6138 NOTE: No more full FEC resets allowed afterwards!! */
6139 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6142 /* MPEGTS functions are still the same */
6143 status = MPEGTSDtoInit(state);
6146 status = MPEGTSStop(state);
6149 status = MPEGTSConfigurePolarity(state);
6152 status = MPEGTSConfigurePins(state, state->m_enableMPEGOutput);
6155 /* added: configure GPIO */
6156 status = WriteGPIO(state);
6160 state->m_DrxkState = DRXK_STOPPED;
6162 if (state->m_bPowerDown) {
6163 status = PowerDownDevice(state);
6166 state->m_DrxkState = DRXK_POWERED_DOWN;
6168 state->m_DrxkState = DRXK_STOPPED;
6172 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
6177 static void drxk_release(struct dvb_frontend *fe)
6179 struct drxk_state *state = fe->demodulator_priv;
6185 static int drxk_sleep(struct dvb_frontend *fe)
6187 struct drxk_state *state = fe->demodulator_priv;
6194 static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable)
6196 struct drxk_state *state = fe->demodulator_priv;
6198 dprintk(1, "%s\n", enable ? "enable" : "disable");
6199 return ConfigureI2CBridge(state, enable ? true : false);
6202 static int drxk_set_parameters(struct dvb_frontend *fe)
6204 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6205 u32 delsys = p->delivery_system, old_delsys;
6206 struct drxk_state *state = fe->demodulator_priv;
6211 if (!fe->ops.tuner_ops.get_if_frequency) {
6213 "drxk: Error: get_if_frequency() not defined at tuner. Can't work without it!\n");
6217 if (fe->ops.i2c_gate_ctrl)
6218 fe->ops.i2c_gate_ctrl(fe, 1);
6219 if (fe->ops.tuner_ops.set_params)
6220 fe->ops.tuner_ops.set_params(fe);
6221 if (fe->ops.i2c_gate_ctrl)
6222 fe->ops.i2c_gate_ctrl(fe, 0);
6224 old_delsys = state->props.delivery_system;
6227 if (old_delsys != delsys) {
6230 case SYS_DVBC_ANNEX_A:
6231 case SYS_DVBC_ANNEX_C:
6232 if (!state->m_hasDVBC)
6234 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
6235 if (state->m_itut_annex_c)
6236 SetOperationMode(state, OM_QAM_ITU_C);
6238 SetOperationMode(state, OM_QAM_ITU_A);
6241 if (!state->m_hasDVBT)
6243 SetOperationMode(state, OM_DVBT);
6250 fe->ops.tuner_ops.get_if_frequency(fe, &IF);
6251 Start(state, 0, IF);
6253 /* printk(KERN_DEBUG "drxk: %s IF=%d done\n", __func__, IF); */
6258 static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status)
6260 struct drxk_state *state = fe->demodulator_priv;
6265 GetLockStatus(state, &stat, 0);
6266 if (stat == MPEG_LOCK)
6268 if (stat == FEC_LOCK)
6270 if (stat == DEMOD_LOCK)
6275 static int drxk_read_ber(struct dvb_frontend *fe, u32 *ber)
6283 static int drxk_read_signal_strength(struct dvb_frontend *fe,
6286 struct drxk_state *state = fe->demodulator_priv;
6290 ReadIFAgc(state, &val);
6291 *strength = val & 0xffff;
6295 static int drxk_read_snr(struct dvb_frontend *fe, u16 *snr)
6297 struct drxk_state *state = fe->demodulator_priv;
6301 GetSignalToNoise(state, &snr2);
6302 *snr = snr2 & 0xffff;
6306 static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
6308 struct drxk_state *state = fe->demodulator_priv;
6312 DVBTQAMGetAccPktErr(state, &err);
6313 *ucblocks = (u32) err;
6317 static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
6320 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
6323 switch (p->delivery_system) {
6324 case SYS_DVBC_ANNEX_A:
6325 case SYS_DVBC_ANNEX_C:
6326 sets->min_delay_ms = 3000;
6327 sets->max_drift = 0;
6328 sets->step_size = 0;
6332 * For DVB-T, let it use the default DVB core way, that is:
6333 * fepriv->step_size = fe->ops.info.frequency_stepsize * 2
6339 static struct dvb_frontend_ops drxk_ops = {
6340 /* .delsys will be filled dynamically */
6343 .frequency_min = 47000000,
6344 .frequency_max = 865000000,
6346 .symbol_rate_min = 870000,
6347 .symbol_rate_max = 11700000,
6349 .frequency_stepsize = 166667,
6351 .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
6352 FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO |
6353 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
6354 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS |
6355 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER |
6356 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO
6359 .release = drxk_release,
6360 .sleep = drxk_sleep,
6361 .i2c_gate_ctrl = drxk_gate_ctrl,
6363 .set_frontend = drxk_set_parameters,
6364 .get_tune_settings = drxk_get_tune_settings,
6366 .read_status = drxk_read_status,
6367 .read_ber = drxk_read_ber,
6368 .read_signal_strength = drxk_read_signal_strength,
6369 .read_snr = drxk_read_snr,
6370 .read_ucblocks = drxk_read_ucblocks,
6373 struct dvb_frontend *drxk_attach(const struct drxk_config *config,
6374 struct i2c_adapter *i2c)
6378 struct drxk_state *state = NULL;
6379 u8 adr = config->adr;
6382 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6387 state->demod_address = adr;
6388 state->single_master = config->single_master;
6389 state->microcode_name = config->microcode_name;
6390 state->no_i2c_bridge = config->no_i2c_bridge;
6391 state->antenna_gpio = config->antenna_gpio;
6392 state->antenna_dvbt = config->antenna_dvbt;
6393 state->m_ChunkSize = config->chunk_size;
6395 if (config->parallel_ts)
6396 state->m_enableParallel = true;
6398 state->m_enableParallel = false;
6400 /* NOTE: as more UIO bits will be used, add them to the mask */
6401 state->UIO_mask = config->antenna_gpio;
6403 /* Default gpio to DVB-C */
6404 if (!state->antenna_dvbt && state->antenna_gpio)
6405 state->m_GPIO |= state->antenna_gpio;
6407 state->m_GPIO &= ~state->antenna_gpio;
6409 mutex_init(&state->mutex);
6411 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6412 state->frontend.demodulator_priv = state;
6415 if (init_drxk(state) < 0)
6418 /* Initialize the supported delivery systems */
6420 if (state->m_hasDVBC) {
6421 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6422 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6423 strlcat(state->frontend.ops.info.name, " DVB-C",
6424 sizeof(state->frontend.ops.info.name));
6426 if (state->m_hasDVBT) {
6427 state->frontend.ops.delsys[n++] = SYS_DVBT;
6428 strlcat(state->frontend.ops.info.name, " DVB-T",
6429 sizeof(state->frontend.ops.info.name));
6432 printk(KERN_INFO "drxk: frontend initialized.\n");
6433 return &state->frontend;
6436 printk(KERN_ERR "drxk: not found\n");
6440 EXPORT_SYMBOL(drxk_attach);
6442 MODULE_DESCRIPTION("DRX-K driver");
6443 MODULE_AUTHOR("Ralph Metzler");
6444 MODULE_LICENSE("GPL");