[media] drxk: Does not unlock mutex if sanity check failed in scu_command()
[pandora-kernel.git] / drivers / media / dvb / frontends / drxk_hard.c
1 /*
2  * drxk_hard: DRX-K DVB-C/T demodulator driver
3  *
4  * Copyright (C) 2010-2011 Digital Devices GmbH
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 only, as published by the Free Software Foundation.
9  *
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20  * 02110-1301, USA
21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/firmware.h>
30 #include <linux/i2c.h>
31 #include <asm/div64.h>
32
33 #include "dvb_frontend.h"
34 #include "drxk.h"
35 #include "drxk_hard.h"
36
37 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode);
38 static int PowerDownQAM(struct drxk_state *state);
39 static int SetDVBTStandard(struct drxk_state *state,
40                            enum OperationMode oMode);
41 static int SetQAMStandard(struct drxk_state *state,
42                           enum OperationMode oMode);
43 static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz,
44                   s32 tunerFreqOffset);
45 static int SetDVBTStandard(struct drxk_state *state,
46                            enum OperationMode oMode);
47 static int DVBTStart(struct drxk_state *state);
48 static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz,
49                    s32 tunerFreqOffset);
50 static int GetQAMLockStatus(struct drxk_state *state, u32 *pLockStatus);
51 static int GetDVBTLockStatus(struct drxk_state *state, u32 *pLockStatus);
52 static int SwitchAntennaToQAM(struct drxk_state *state);
53 static int SwitchAntennaToDVBT(struct drxk_state *state);
54
55 static bool IsDVBT(struct drxk_state *state)
56 {
57         return state->m_OperationMode == OM_DVBT;
58 }
59
60 static bool IsQAM(struct drxk_state *state)
61 {
62         return state->m_OperationMode == OM_QAM_ITU_A ||
63             state->m_OperationMode == OM_QAM_ITU_B ||
64             state->m_OperationMode == OM_QAM_ITU_C;
65 }
66
67 bool IsA1WithPatchCode(struct drxk_state *state)
68 {
69         return state->m_DRXK_A1_PATCH_CODE;
70 }
71
72 bool IsA1WithRomCode(struct drxk_state *state)
73 {
74         return state->m_DRXK_A1_ROM_CODE;
75 }
76
77 #define NOA1ROM 0
78
79 #define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr) & 0xFC30FF80) == 0)
80 #define DRXDAP_FASI_LONG_FORMAT(addr)  (((addr) & 0xFC30FF80) != 0)
81
82 #define DEFAULT_MER_83  165
83 #define DEFAULT_MER_93  250
84
85 #ifndef DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH
86 #define DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH (0x02)
87 #endif
88
89 #ifndef DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH
90 #define DRXK_MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH (0x03)
91 #endif
92
93 #define DEFAULT_DRXK_MPEG_LOCK_TIMEOUT 700
94 #define DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT 500
95
96 #ifndef DRXK_KI_RAGC_ATV
97 #define DRXK_KI_RAGC_ATV   4
98 #endif
99 #ifndef DRXK_KI_IAGC_ATV
100 #define DRXK_KI_IAGC_ATV   6
101 #endif
102 #ifndef DRXK_KI_DAGC_ATV
103 #define DRXK_KI_DAGC_ATV   7
104 #endif
105
106 #ifndef DRXK_KI_RAGC_QAM
107 #define DRXK_KI_RAGC_QAM   3
108 #endif
109 #ifndef DRXK_KI_IAGC_QAM
110 #define DRXK_KI_IAGC_QAM   4
111 #endif
112 #ifndef DRXK_KI_DAGC_QAM
113 #define DRXK_KI_DAGC_QAM   7
114 #endif
115 #ifndef DRXK_KI_RAGC_DVBT
116 #define DRXK_KI_RAGC_DVBT  (IsA1WithPatchCode(state) ? 3 : 2)
117 #endif
118 #ifndef DRXK_KI_IAGC_DVBT
119 #define DRXK_KI_IAGC_DVBT  (IsA1WithPatchCode(state) ? 4 : 2)
120 #endif
121 #ifndef DRXK_KI_DAGC_DVBT
122 #define DRXK_KI_DAGC_DVBT  (IsA1WithPatchCode(state) ? 10 : 7)
123 #endif
124
125 #ifndef DRXK_AGC_DAC_OFFSET
126 #define DRXK_AGC_DAC_OFFSET (0x800)
127 #endif
128
129 #ifndef DRXK_BANDWIDTH_8MHZ_IN_HZ
130 #define DRXK_BANDWIDTH_8MHZ_IN_HZ  (0x8B8249L)
131 #endif
132
133 #ifndef DRXK_BANDWIDTH_7MHZ_IN_HZ
134 #define DRXK_BANDWIDTH_7MHZ_IN_HZ  (0x7A1200L)
135 #endif
136
137 #ifndef DRXK_BANDWIDTH_6MHZ_IN_HZ
138 #define DRXK_BANDWIDTH_6MHZ_IN_HZ  (0x68A1B6L)
139 #endif
140
141 #ifndef DRXK_QAM_SYMBOLRATE_MAX
142 #define DRXK_QAM_SYMBOLRATE_MAX         (7233000)
143 #endif
144
145 #define DRXK_BL_ROM_OFFSET_TAPS_DVBT    56
146 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_A   64
147 #define DRXK_BL_ROM_OFFSET_TAPS_ITU_C   0x5FE0
148 #define DRXK_BL_ROM_OFFSET_TAPS_BG      24
149 #define DRXK_BL_ROM_OFFSET_TAPS_DKILLP  32
150 #define DRXK_BL_ROM_OFFSET_TAPS_NTSC    40
151 #define DRXK_BL_ROM_OFFSET_TAPS_FM      48
152 #define DRXK_BL_ROM_OFFSET_UCODE        0
153
154 #define DRXK_BLC_TIMEOUT                100
155
156 #define DRXK_BLCC_NR_ELEMENTS_TAPS      2
157 #define DRXK_BLCC_NR_ELEMENTS_UCODE     6
158
159 #define DRXK_BLDC_NR_ELEMENTS_TAPS      28
160
161 #ifndef DRXK_OFDM_NE_NOTCH_WIDTH
162 #define DRXK_OFDM_NE_NOTCH_WIDTH             (4)
163 #endif
164
165 #define DRXK_QAM_SL_SIG_POWER_QAM16       (40960)
166 #define DRXK_QAM_SL_SIG_POWER_QAM32       (20480)
167 #define DRXK_QAM_SL_SIG_POWER_QAM64       (43008)
168 #define DRXK_QAM_SL_SIG_POWER_QAM128      (20992)
169 #define DRXK_QAM_SL_SIG_POWER_QAM256      (43520)
170
171 static unsigned int debug;
172 module_param(debug, int, 0644);
173 MODULE_PARM_DESC(debug, "enable debug messages");
174
175 #define dprintk(level, fmt, arg...) do {                        \
176 if (debug >= level)                                             \
177         printk(KERN_DEBUG "drxk: %s" fmt, __func__, ## arg);    \
178 } while (0)
179
180
181 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
182 {
183         u64 tmp64;
184
185         tmp64 = (u64) a * (u64) b;
186         do_div(tmp64, c);
187
188         return (u32) tmp64;
189 }
190
191 inline u32 Frac28a(u32 a, u32 c)
192 {
193         int i = 0;
194         u32 Q1 = 0;
195         u32 R0 = 0;
196
197         R0 = (a % c) << 4;      /* 32-28 == 4 shifts possible at max */
198         Q1 = a / c;             /* integer part, only the 4 least significant bits
199                                    will be visible in the result */
200
201         /* division using radix 16, 7 nibbles in the result */
202         for (i = 0; i < 7; i++) {
203                 Q1 = (Q1 << 4) | (R0 / c);
204                 R0 = (R0 % c) << 4;
205         }
206         /* rounding */
207         if ((R0 >> 3) >= c)
208                 Q1++;
209
210         return Q1;
211 }
212
213 static u32 Log10Times100(u32 x)
214 {
215         static const u8 scale = 15;
216         static const u8 indexWidth = 5;
217         u8 i = 0;
218         u32 y = 0;
219         u32 d = 0;
220         u32 k = 0;
221         u32 r = 0;
222         /*
223            log2lut[n] = (1<<scale) * 200 * log2(1.0 + ((1.0/(1<<INDEXWIDTH)) * n))
224            0 <= n < ((1<<INDEXWIDTH)+1)
225          */
226
227         static const u32 log2lut[] = {
228                 0,              /* 0.000000 */
229                 290941,         /* 290941.300628 */
230                 573196,         /* 573196.476418 */
231                 847269,         /* 847269.179851 */
232                 1113620,        /* 1113620.489452 */
233                 1372674,        /* 1372673.576986 */
234                 1624818,        /* 1624817.752104 */
235                 1870412,        /* 1870411.981536 */
236                 2109788,        /* 2109787.962654 */
237                 2343253,        /* 2343252.817465 */
238                 2571091,        /* 2571091.461923 */
239                 2793569,        /* 2793568.696416 */
240                 3010931,        /* 3010931.055901 */
241                 3223408,        /* 3223408.452106 */
242                 3431216,        /* 3431215.635215 */
243                 3634553,        /* 3634553.498355 */
244                 3833610,        /* 3833610.244726 */
245                 4028562,        /* 4028562.434393 */
246                 4219576,        /* 4219575.925308 */
247                 4406807,        /* 4406806.721144 */
248                 4590402,        /* 4590401.736809 */
249                 4770499,        /* 4770499.491025 */
250                 4947231,        /* 4947230.734179 */
251                 5120719,        /* 5120719.018555 */
252                 5291081,        /* 5291081.217197 */
253                 5458428,        /* 5458427.996830 */
254                 5622864,        /* 5622864.249668 */
255                 5784489,        /* 5784489.488298 */
256                 5943398,        /* 5943398.207380 */
257                 6099680,        /* 6099680.215452 */
258                 6253421,        /* 6253420.939751 */
259                 6404702,        /* 6404701.706649 */
260                 6553600,        /* 6553600.000000 */
261         };
262
263
264         if (x == 0)
265                 return 0;
266
267         /* Scale x (normalize) */
268         /* computing y in log(x/y) = log(x) - log(y) */
269         if ((x & ((0xffffffff) << (scale + 1))) == 0) {
270                 for (k = scale; k > 0; k--) {
271                         if (x & (((u32) 1) << scale))
272                                 break;
273                         x <<= 1;
274                 }
275         } else {
276                 for (k = scale; k < 31; k++) {
277                         if ((x & (((u32) (-1)) << (scale + 1))) == 0)
278                                 break;
279                         x >>= 1;
280                 }
281         }
282         /*
283            Now x has binary point between bit[scale] and bit[scale-1]
284            and 1.0 <= x < 2.0 */
285
286         /* correction for divison: log(x) = log(x/y)+log(y) */
287         y = k * ((((u32) 1) << scale) * 200);
288
289         /* remove integer part */
290         x &= ((((u32) 1) << scale) - 1);
291         /* get index */
292         i = (u8) (x >> (scale - indexWidth));
293         /* compute delta (x - a) */
294         d = x & ((((u32) 1) << (scale - indexWidth)) - 1);
295         /* compute log, multiplication (d* (..)) must be within range ! */
296         y += log2lut[i] +
297             ((d * (log2lut[i + 1] - log2lut[i])) >> (scale - indexWidth));
298         /* Conver to log10() */
299         y /= 108853;            /* (log2(10) << scale) */
300         r = (y >> 1);
301         /* rounding */
302         if (y & ((u32) 1))
303                 r++;
304         return r;
305 }
306
307 /****************************************************************************/
308 /* I2C **********************************************************************/
309 /****************************************************************************/
310
311 static int i2c_read1(struct i2c_adapter *adapter, u8 adr, u8 *val)
312 {
313         struct i2c_msg msgs[1] = { {.addr = adr, .flags = I2C_M_RD,
314                                     .buf = val, .len = 1}
315         };
316
317         return i2c_transfer(adapter, msgs, 1);
318 }
319
320 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
321 {
322         int status;
323         struct i2c_msg msg = {
324             .addr = adr, .flags = 0, .buf = data, .len = len };
325
326         dprintk(3, ":");
327         if (debug > 2) {
328                 int i;
329                 for (i = 0; i < len; i++)
330                         printk(KERN_CONT " %02x", data[i]);
331                 printk(KERN_CONT "\n");
332         }
333         status = i2c_transfer(adap, &msg, 1);
334         if (status >= 0 && status != 1)
335                 status = -EIO;
336
337         if (status < 0)
338                 printk(KERN_ERR "drxk: i2c write error at addr 0x%02x\n", adr);
339
340         return status;
341 }
342
343 static int i2c_read(struct i2c_adapter *adap,
344                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
345 {
346         int status;
347         struct i2c_msg msgs[2] = {
348                 {.addr = adr, .flags = 0,
349                                     .buf = msg, .len = len},
350                 {.addr = adr, .flags = I2C_M_RD,
351                  .buf = answ, .len = alen}
352         };
353
354         status = i2c_transfer(adap, msgs, 2);
355         if (status != 2) {
356                 if (debug > 2)
357                         printk(KERN_CONT ": ERROR!\n");
358                 if (status >= 0)
359                         status = -EIO;
360
361                 printk(KERN_ERR "drxk: i2c read error at addr 0x%02x\n", adr);
362                 return status;
363         }
364         if (debug > 2) {
365                 int i;
366                 dprintk(2, ": read from");
367                 for (i = 0; i < len; i++)
368                         printk(KERN_CONT " %02x", msg[i]);
369                 printk(KERN_CONT ", value = ");
370                 for (i = 0; i < alen; i++)
371                         printk(KERN_CONT " %02x", answ[i]);
372                 printk(KERN_CONT "\n");
373         }
374         return 0;
375 }
376
377 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
378 {
379         int status;
380         u8 adr = state->demod_address, mm1[4], mm2[2], len;
381
382         if (state->single_master)
383                 flags |= 0xC0;
384
385         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
386                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
387                 mm1[1] = ((reg >> 16) & 0xFF);
388                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
389                 mm1[3] = ((reg >> 7) & 0xFF);
390                 len = 4;
391         } else {
392                 mm1[0] = ((reg << 1) & 0xFF);
393                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
394                 len = 2;
395         }
396         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
397         status = i2c_read(state->i2c, adr, mm1, len, mm2, 2);
398         if (status < 0)
399                 return status;
400         if (data)
401                 *data = mm2[0] | (mm2[1] << 8);
402
403         return 0;
404 }
405
406 static int read16(struct drxk_state *state, u32 reg, u16 *data)
407 {
408         return read16_flags(state, reg, data, 0);
409 }
410
411 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
412 {
413         int status;
414         u8 adr = state->demod_address, mm1[4], mm2[4], len;
415
416         if (state->single_master)
417                 flags |= 0xC0;
418
419         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
420                 mm1[0] = (((reg << 1) & 0xFF) | 0x01);
421                 mm1[1] = ((reg >> 16) & 0xFF);
422                 mm1[2] = ((reg >> 24) & 0xFF) | flags;
423                 mm1[3] = ((reg >> 7) & 0xFF);
424                 len = 4;
425         } else {
426                 mm1[0] = ((reg << 1) & 0xFF);
427                 mm1[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
428                 len = 2;
429         }
430         dprintk(2, "(0x%08x, 0x%02x)\n", reg, flags);
431         status = i2c_read(state->i2c, adr, mm1, len, mm2, 4);
432         if (status < 0)
433                 return status;
434         if (data)
435                 *data = mm2[0] | (mm2[1] << 8) |
436                     (mm2[2] << 16) | (mm2[3] << 24);
437
438         return 0;
439 }
440
441 static int read32(struct drxk_state *state, u32 reg, u32 *data)
442 {
443         return read32_flags(state, reg, data, 0);
444 }
445
446 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
447 {
448         u8 adr = state->demod_address, mm[6], len;
449
450         if (state->single_master)
451                 flags |= 0xC0;
452         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
453                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
454                 mm[1] = ((reg >> 16) & 0xFF);
455                 mm[2] = ((reg >> 24) & 0xFF) | flags;
456                 mm[3] = ((reg >> 7) & 0xFF);
457                 len = 4;
458         } else {
459                 mm[0] = ((reg << 1) & 0xFF);
460                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
461                 len = 2;
462         }
463         mm[len] = data & 0xff;
464         mm[len + 1] = (data >> 8) & 0xff;
465
466         dprintk(2, "(0x%08x, 0x%04x, 0x%02x)\n", reg, data, flags);
467         return i2c_write(state->i2c, adr, mm, len + 2);
468 }
469
470 static int write16(struct drxk_state *state, u32 reg, u16 data)
471 {
472         return write16_flags(state, reg, data, 0);
473 }
474
475 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
476 {
477         u8 adr = state->demod_address, mm[8], len;
478
479         if (state->single_master)
480                 flags |= 0xC0;
481         if (DRXDAP_FASI_LONG_FORMAT(reg) || (flags != 0)) {
482                 mm[0] = (((reg << 1) & 0xFF) | 0x01);
483                 mm[1] = ((reg >> 16) & 0xFF);
484                 mm[2] = ((reg >> 24) & 0xFF) | flags;
485                 mm[3] = ((reg >> 7) & 0xFF);
486                 len = 4;
487         } else {
488                 mm[0] = ((reg << 1) & 0xFF);
489                 mm[1] = (((reg >> 16) & 0x0F) | ((reg >> 18) & 0xF0));
490                 len = 2;
491         }
492         mm[len] = data & 0xff;
493         mm[len + 1] = (data >> 8) & 0xff;
494         mm[len + 2] = (data >> 16) & 0xff;
495         mm[len + 3] = (data >> 24) & 0xff;
496         dprintk(2, "(0x%08x, 0x%08x, 0x%02x)\n", reg, data, flags);
497
498         return i2c_write(state->i2c, adr, mm, len + 4);
499 }
500
501 static int write32(struct drxk_state *state, u32 reg, u32 data)
502 {
503         return write32_flags(state, reg, data, 0);
504 }
505
506 static int write_block(struct drxk_state *state, u32 Address,
507                       const int BlockSize, const u8 pBlock[])
508 {
509         int status = 0, BlkSize = BlockSize;
510         u8 Flags = 0;
511
512         if (state->single_master)
513                 Flags |= 0xC0;
514
515         while (BlkSize > 0) {
516                 int Chunk = BlkSize > state->m_ChunkSize ?
517                     state->m_ChunkSize : BlkSize;
518                 u8 *AdrBuf = &state->Chunk[0];
519                 u32 AdrLength = 0;
520
521                 if (DRXDAP_FASI_LONG_FORMAT(Address) || (Flags != 0)) {
522                         AdrBuf[0] = (((Address << 1) & 0xFF) | 0x01);
523                         AdrBuf[1] = ((Address >> 16) & 0xFF);
524                         AdrBuf[2] = ((Address >> 24) & 0xFF);
525                         AdrBuf[3] = ((Address >> 7) & 0xFF);
526                         AdrBuf[2] |= Flags;
527                         AdrLength = 4;
528                         if (Chunk == state->m_ChunkSize)
529                                 Chunk -= 2;
530                 } else {
531                         AdrBuf[0] = ((Address << 1) & 0xFF);
532                         AdrBuf[1] = (((Address >> 16) & 0x0F) |
533                                      ((Address >> 18) & 0xF0));
534                         AdrLength = 2;
535                 }
536                 memcpy(&state->Chunk[AdrLength], pBlock, Chunk);
537                 dprintk(2, "(0x%08x, 0x%02x)\n", Address, Flags);
538                 if (debug > 1) {
539                         int i;
540                         if (pBlock)
541                                 for (i = 0; i < Chunk; i++)
542                                         printk(KERN_CONT " %02x", pBlock[i]);
543                         printk(KERN_CONT "\n");
544                 }
545                 status = i2c_write(state->i2c, state->demod_address,
546                                    &state->Chunk[0], Chunk + AdrLength);
547                 if (status < 0) {
548                         printk(KERN_ERR "drxk: %s: i2c write error at addr 0x%02x\n",
549                                __func__, Address);
550                         break;
551                 }
552                 pBlock += Chunk;
553                 Address += (Chunk >> 1);
554                 BlkSize -= Chunk;
555         }
556         return status;
557 }
558
559 #ifndef DRXK_MAX_RETRIES_POWERUP
560 #define DRXK_MAX_RETRIES_POWERUP 20
561 #endif
562
563 int PowerUpDevice(struct drxk_state *state)
564 {
565         int status;
566         u8 data = 0;
567         u16 retryCount = 0;
568
569         dprintk(1, "\n");
570
571         status = i2c_read1(state->i2c, state->demod_address, &data);
572         if (status < 0) {
573                 do {
574                         data = 0;
575                         status = i2c_write(state->i2c, state->demod_address,
576                                            &data, 1);
577                         msleep(10);
578                         retryCount++;
579                         if (status < 0)
580                                 continue;
581                         status = i2c_read1(state->i2c, state->demod_address,
582                                            &data);
583                 } while (status < 0 &&
584                          (retryCount < DRXK_MAX_RETRIES_POWERUP));
585                 if (status < 0 && retryCount >= DRXK_MAX_RETRIES_POWERUP)
586                         goto error;
587         }
588
589         /* Make sure all clk domains are active */
590         status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
591         if (status < 0)
592                 goto error;
593         status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
594         if (status < 0)
595                 goto error;
596         /* Enable pll lock tests */
597         status = write16(state, SIO_CC_PLL_LOCK__A, 1);
598         if (status < 0)
599                 goto error;
600
601         state->m_currentPowerMode = DRX_POWER_UP;
602
603 error:
604         if (status < 0)
605                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
606
607         return status;
608 }
609
610
611 static int init_state(struct drxk_state *state)
612 {
613         /*
614          * FIXME: most (all?) of the values bellow should be moved into
615          * struct drxk_config, as they are probably board-specific
616          */
617         u32 ulVSBIfAgcMode = DRXK_AGC_CTRL_AUTO;
618         u32 ulVSBIfAgcOutputLevel = 0;
619         u32 ulVSBIfAgcMinLevel = 0;
620         u32 ulVSBIfAgcMaxLevel = 0x7FFF;
621         u32 ulVSBIfAgcSpeed = 3;
622
623         u32 ulVSBRfAgcMode = DRXK_AGC_CTRL_AUTO;
624         u32 ulVSBRfAgcOutputLevel = 0;
625         u32 ulVSBRfAgcMinLevel = 0;
626         u32 ulVSBRfAgcMaxLevel = 0x7FFF;
627         u32 ulVSBRfAgcSpeed = 3;
628         u32 ulVSBRfAgcTop = 9500;
629         u32 ulVSBRfAgcCutOffCurrent = 4000;
630
631         u32 ulATVIfAgcMode = DRXK_AGC_CTRL_AUTO;
632         u32 ulATVIfAgcOutputLevel = 0;
633         u32 ulATVIfAgcMinLevel = 0;
634         u32 ulATVIfAgcMaxLevel = 0;
635         u32 ulATVIfAgcSpeed = 3;
636
637         u32 ulATVRfAgcMode = DRXK_AGC_CTRL_OFF;
638         u32 ulATVRfAgcOutputLevel = 0;
639         u32 ulATVRfAgcMinLevel = 0;
640         u32 ulATVRfAgcMaxLevel = 0;
641         u32 ulATVRfAgcTop = 9500;
642         u32 ulATVRfAgcCutOffCurrent = 4000;
643         u32 ulATVRfAgcSpeed = 3;
644
645         u32 ulQual83 = DEFAULT_MER_83;
646         u32 ulQual93 = DEFAULT_MER_93;
647
648         u32 ulMpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
649         u32 ulDemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
650
651         /* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
652         /* io_pad_cfg_mode output mode is drive always */
653         /* io_pad_cfg_drive is set to power 2 (23 mA) */
654         u32 ulGPIOCfg = 0x0113;
655         u32 ulInvertTSClock = 0;
656         u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH;
657         u32 ulDVBTBitrate = 50000000;
658         u32 ulDVBCBitrate = DRXK_QAM_SYMBOLRATE_MAX * 8;
659
660         u32 ulInsertRSByte = 0;
661
662         u32 ulRfMirror = 1;
663         u32 ulPowerDown = 0;
664
665         dprintk(1, "\n");
666
667         state->m_hasLNA = false;
668         state->m_hasDVBT = false;
669         state->m_hasDVBC = false;
670         state->m_hasATV = false;
671         state->m_hasOOB = false;
672         state->m_hasAudio = false;
673
674         if (!state->m_ChunkSize)
675                 state->m_ChunkSize = 124;
676
677         state->m_oscClockFreq = 0;
678         state->m_smartAntInverted = false;
679         state->m_bPDownOpenBridge = false;
680
681         /* real system clock frequency in kHz */
682         state->m_sysClockFreq = 151875;
683         /* Timing div, 250ns/Psys */
684         /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */
685         state->m_HICfgTimingDiv = ((state->m_sysClockFreq / 1000) *
686                                    HI_I2C_DELAY) / 1000;
687         /* Clipping */
688         if (state->m_HICfgTimingDiv > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
689                 state->m_HICfgTimingDiv = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
690         state->m_HICfgWakeUpKey = (state->demod_address << 1);
691         /* port/bridge/power down ctrl */
692         state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
693
694         state->m_bPowerDown = (ulPowerDown != 0);
695
696         state->m_DRXK_A1_PATCH_CODE = false;
697         state->m_DRXK_A1_ROM_CODE = false;
698         state->m_DRXK_A2_ROM_CODE = false;
699         state->m_DRXK_A3_ROM_CODE = false;
700         state->m_DRXK_A2_PATCH_CODE = false;
701         state->m_DRXK_A3_PATCH_CODE = false;
702
703         /* Init AGC and PGA parameters */
704         /* VSB IF */
705         state->m_vsbIfAgcCfg.ctrlMode = (ulVSBIfAgcMode);
706         state->m_vsbIfAgcCfg.outputLevel = (ulVSBIfAgcOutputLevel);
707         state->m_vsbIfAgcCfg.minOutputLevel = (ulVSBIfAgcMinLevel);
708         state->m_vsbIfAgcCfg.maxOutputLevel = (ulVSBIfAgcMaxLevel);
709         state->m_vsbIfAgcCfg.speed = (ulVSBIfAgcSpeed);
710         state->m_vsbPgaCfg = 140;
711
712         /* VSB RF */
713         state->m_vsbRfAgcCfg.ctrlMode = (ulVSBRfAgcMode);
714         state->m_vsbRfAgcCfg.outputLevel = (ulVSBRfAgcOutputLevel);
715         state->m_vsbRfAgcCfg.minOutputLevel = (ulVSBRfAgcMinLevel);
716         state->m_vsbRfAgcCfg.maxOutputLevel = (ulVSBRfAgcMaxLevel);
717         state->m_vsbRfAgcCfg.speed = (ulVSBRfAgcSpeed);
718         state->m_vsbRfAgcCfg.top = (ulVSBRfAgcTop);
719         state->m_vsbRfAgcCfg.cutOffCurrent = (ulVSBRfAgcCutOffCurrent);
720         state->m_vsbPreSawCfg.reference = 0x07;
721         state->m_vsbPreSawCfg.usePreSaw = true;
722
723         state->m_Quality83percent = DEFAULT_MER_83;
724         state->m_Quality93percent = DEFAULT_MER_93;
725         if (ulQual93 <= 500 && ulQual83 < ulQual93) {
726                 state->m_Quality83percent = ulQual83;
727                 state->m_Quality93percent = ulQual93;
728         }
729
730         /* ATV IF */
731         state->m_atvIfAgcCfg.ctrlMode = (ulATVIfAgcMode);
732         state->m_atvIfAgcCfg.outputLevel = (ulATVIfAgcOutputLevel);
733         state->m_atvIfAgcCfg.minOutputLevel = (ulATVIfAgcMinLevel);
734         state->m_atvIfAgcCfg.maxOutputLevel = (ulATVIfAgcMaxLevel);
735         state->m_atvIfAgcCfg.speed = (ulATVIfAgcSpeed);
736
737         /* ATV RF */
738         state->m_atvRfAgcCfg.ctrlMode = (ulATVRfAgcMode);
739         state->m_atvRfAgcCfg.outputLevel = (ulATVRfAgcOutputLevel);
740         state->m_atvRfAgcCfg.minOutputLevel = (ulATVRfAgcMinLevel);
741         state->m_atvRfAgcCfg.maxOutputLevel = (ulATVRfAgcMaxLevel);
742         state->m_atvRfAgcCfg.speed = (ulATVRfAgcSpeed);
743         state->m_atvRfAgcCfg.top = (ulATVRfAgcTop);
744         state->m_atvRfAgcCfg.cutOffCurrent = (ulATVRfAgcCutOffCurrent);
745         state->m_atvPreSawCfg.reference = 0x04;
746         state->m_atvPreSawCfg.usePreSaw = true;
747
748
749         /* DVBT RF */
750         state->m_dvbtRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
751         state->m_dvbtRfAgcCfg.outputLevel = 0;
752         state->m_dvbtRfAgcCfg.minOutputLevel = 0;
753         state->m_dvbtRfAgcCfg.maxOutputLevel = 0xFFFF;
754         state->m_dvbtRfAgcCfg.top = 0x2100;
755         state->m_dvbtRfAgcCfg.cutOffCurrent = 4000;
756         state->m_dvbtRfAgcCfg.speed = 1;
757
758
759         /* DVBT IF */
760         state->m_dvbtIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
761         state->m_dvbtIfAgcCfg.outputLevel = 0;
762         state->m_dvbtIfAgcCfg.minOutputLevel = 0;
763         state->m_dvbtIfAgcCfg.maxOutputLevel = 9000;
764         state->m_dvbtIfAgcCfg.top = 13424;
765         state->m_dvbtIfAgcCfg.cutOffCurrent = 0;
766         state->m_dvbtIfAgcCfg.speed = 3;
767         state->m_dvbtIfAgcCfg.FastClipCtrlDelay = 30;
768         state->m_dvbtIfAgcCfg.IngainTgtMax = 30000;
769         /* state->m_dvbtPgaCfg = 140; */
770
771         state->m_dvbtPreSawCfg.reference = 4;
772         state->m_dvbtPreSawCfg.usePreSaw = false;
773
774         /* QAM RF */
775         state->m_qamRfAgcCfg.ctrlMode = DRXK_AGC_CTRL_OFF;
776         state->m_qamRfAgcCfg.outputLevel = 0;
777         state->m_qamRfAgcCfg.minOutputLevel = 6023;
778         state->m_qamRfAgcCfg.maxOutputLevel = 27000;
779         state->m_qamRfAgcCfg.top = 0x2380;
780         state->m_qamRfAgcCfg.cutOffCurrent = 4000;
781         state->m_qamRfAgcCfg.speed = 3;
782
783         /* QAM IF */
784         state->m_qamIfAgcCfg.ctrlMode = DRXK_AGC_CTRL_AUTO;
785         state->m_qamIfAgcCfg.outputLevel = 0;
786         state->m_qamIfAgcCfg.minOutputLevel = 0;
787         state->m_qamIfAgcCfg.maxOutputLevel = 9000;
788         state->m_qamIfAgcCfg.top = 0x0511;
789         state->m_qamIfAgcCfg.cutOffCurrent = 0;
790         state->m_qamIfAgcCfg.speed = 3;
791         state->m_qamIfAgcCfg.IngainTgtMax = 5119;
792         state->m_qamIfAgcCfg.FastClipCtrlDelay = 50;
793
794         state->m_qamPgaCfg = 140;
795         state->m_qamPreSawCfg.reference = 4;
796         state->m_qamPreSawCfg.usePreSaw = false;
797
798         state->m_OperationMode = OM_NONE;
799         state->m_DrxkState = DRXK_UNINITIALIZED;
800
801         /* MPEG output configuration */
802         state->m_enableMPEGOutput = true;       /* If TRUE; enable MPEG ouput */
803         state->m_insertRSByte = false;  /* If TRUE; insert RS byte */
804         state->m_invertDATA = false;    /* If TRUE; invert DATA signals */
805         state->m_invertERR = false;     /* If TRUE; invert ERR signal */
806         state->m_invertSTR = false;     /* If TRUE; invert STR signals */
807         state->m_invertVAL = false;     /* If TRUE; invert VAL signals */
808         state->m_invertCLK = (ulInvertTSClock != 0);    /* If TRUE; invert CLK signals */
809
810         /* If TRUE; static MPEG clockrate will be used;
811            otherwise clockrate will adapt to the bitrate of the TS */
812
813         state->m_DVBTBitrate = ulDVBTBitrate;
814         state->m_DVBCBitrate = ulDVBCBitrate;
815
816         state->m_TSDataStrength = (ulTSDataStrength & 0x07);
817
818         /* Maximum bitrate in b/s in case static clockrate is selected */
819         state->m_mpegTsStaticBitrate = 19392658;
820         state->m_disableTEIhandling = false;
821
822         if (ulInsertRSByte)
823                 state->m_insertRSByte = true;
824
825         state->m_MpegLockTimeOut = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
826         if (ulMpegLockTimeOut < 10000)
827                 state->m_MpegLockTimeOut = ulMpegLockTimeOut;
828         state->m_DemodLockTimeOut = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
829         if (ulDemodLockTimeOut < 10000)
830                 state->m_DemodLockTimeOut = ulDemodLockTimeOut;
831
832         /* QAM defaults */
833         state->m_Constellation = DRX_CONSTELLATION_AUTO;
834         state->m_qamInterleaveMode = DRXK_QAM_I12_J17;
835         state->m_fecRsPlen = 204 * 8;   /* fecRsPlen  annex A */
836         state->m_fecRsPrescale = 1;
837
838         state->m_sqiSpeed = DRXK_DVBT_SQI_SPEED_MEDIUM;
839         state->m_agcFastClipCtrlDelay = 0;
840
841         state->m_GPIOCfg = (ulGPIOCfg);
842
843         state->m_bPowerDown = false;
844         state->m_currentPowerMode = DRX_POWER_DOWN;
845
846         state->m_rfmirror = (ulRfMirror == 0);
847         state->m_IfAgcPol = false;
848         return 0;
849 }
850
851 static int DRXX_Open(struct drxk_state *state)
852 {
853         int status = 0;
854         u32 jtag = 0;
855         u16 bid = 0;
856         u16 key = 0;
857
858         dprintk(1, "\n");
859         /* stop lock indicator process */
860         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
861         if (status < 0)
862                 goto error;
863         /* Check device id */
864         status = read16(state, SIO_TOP_COMM_KEY__A, &key);
865         if (status < 0)
866                 goto error;
867         status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
868         if (status < 0)
869                 goto error;
870         status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
871         if (status < 0)
872                 goto error;
873         status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
874         if (status < 0)
875                 goto error;
876         status = write16(state, SIO_TOP_COMM_KEY__A, key);
877 error:
878         if (status < 0)
879                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
880         return status;
881 }
882
883 static int GetDeviceCapabilities(struct drxk_state *state)
884 {
885         u16 sioPdrOhwCfg = 0;
886         u32 sioTopJtagidLo = 0;
887         int status;
888         const char *spin = "";
889
890         dprintk(1, "\n");
891
892         /* driver 0.9.0 */
893         /* stop lock indicator process */
894         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
895         if (status < 0)
896                 goto error;
897         status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
898         if (status < 0)
899                 goto error;
900         status = read16(state, SIO_PDR_OHW_CFG__A, &sioPdrOhwCfg);
901         if (status < 0)
902                 goto error;
903         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
904         if (status < 0)
905                 goto error;
906
907         switch ((sioPdrOhwCfg & SIO_PDR_OHW_CFG_FREF_SEL__M)) {
908         case 0:
909                 /* ignore (bypass ?) */
910                 break;
911         case 1:
912                 /* 27 MHz */
913                 state->m_oscClockFreq = 27000;
914                 break;
915         case 2:
916                 /* 20.25 MHz */
917                 state->m_oscClockFreq = 20250;
918                 break;
919         case 3:
920                 /* 4 MHz */
921                 state->m_oscClockFreq = 20250;
922                 break;
923         default:
924                 printk(KERN_ERR "drxk: Clock Frequency is unkonwn\n");
925                 return -EINVAL;
926         }
927         /*
928                 Determine device capabilities
929                 Based on pinning v14
930                 */
931         status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo);
932         if (status < 0)
933                 goto error;
934
935 printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo);
936
937         /* driver 0.9.0 */
938         switch ((sioTopJtagidLo >> 29) & 0xF) {
939         case 0:
940                 state->m_deviceSpin = DRXK_SPIN_A1;
941                 spin = "A1";
942                 break;
943         case 2:
944                 state->m_deviceSpin = DRXK_SPIN_A2;
945                 spin = "A2";
946                 break;
947         case 3:
948                 state->m_deviceSpin = DRXK_SPIN_A3;
949                 spin = "A3";
950                 break;
951         default:
952                 state->m_deviceSpin = DRXK_SPIN_UNKNOWN;
953                 status = -EINVAL;
954                 printk(KERN_ERR "drxk: Spin %d unknown\n",
955                        (sioTopJtagidLo >> 29) & 0xF);
956                 goto error2;
957         }
958         switch ((sioTopJtagidLo >> 12) & 0xFF) {
959         case 0x13:
960                 /* typeId = DRX3913K_TYPE_ID */
961                 state->m_hasLNA = false;
962                 state->m_hasOOB = false;
963                 state->m_hasATV = false;
964                 state->m_hasAudio = false;
965                 state->m_hasDVBT = true;
966                 state->m_hasDVBC = true;
967                 state->m_hasSAWSW = true;
968                 state->m_hasGPIO2 = false;
969                 state->m_hasGPIO1 = false;
970                 state->m_hasIRQN = false;
971                 break;
972         case 0x15:
973                 /* typeId = DRX3915K_TYPE_ID */
974                 state->m_hasLNA = false;
975                 state->m_hasOOB = false;
976                 state->m_hasATV = true;
977                 state->m_hasAudio = false;
978                 state->m_hasDVBT = true;
979                 state->m_hasDVBC = false;
980                 state->m_hasSAWSW = true;
981                 state->m_hasGPIO2 = true;
982                 state->m_hasGPIO1 = true;
983                 state->m_hasIRQN = false;
984                 break;
985         case 0x16:
986                 /* typeId = DRX3916K_TYPE_ID */
987                 state->m_hasLNA = false;
988                 state->m_hasOOB = false;
989                 state->m_hasATV = true;
990                 state->m_hasAudio = false;
991                 state->m_hasDVBT = true;
992                 state->m_hasDVBC = false;
993                 state->m_hasSAWSW = true;
994                 state->m_hasGPIO2 = true;
995                 state->m_hasGPIO1 = true;
996                 state->m_hasIRQN = false;
997                 break;
998         case 0x18:
999                 /* typeId = DRX3918K_TYPE_ID */
1000                 state->m_hasLNA = false;
1001                 state->m_hasOOB = false;
1002                 state->m_hasATV = true;
1003                 state->m_hasAudio = true;
1004                 state->m_hasDVBT = true;
1005                 state->m_hasDVBC = false;
1006                 state->m_hasSAWSW = true;
1007                 state->m_hasGPIO2 = true;
1008                 state->m_hasGPIO1 = true;
1009                 state->m_hasIRQN = false;
1010                 break;
1011         case 0x21:
1012                 /* typeId = DRX3921K_TYPE_ID */
1013                 state->m_hasLNA = false;
1014                 state->m_hasOOB = false;
1015                 state->m_hasATV = true;
1016                 state->m_hasAudio = true;
1017                 state->m_hasDVBT = true;
1018                 state->m_hasDVBC = true;
1019                 state->m_hasSAWSW = true;
1020                 state->m_hasGPIO2 = true;
1021                 state->m_hasGPIO1 = true;
1022                 state->m_hasIRQN = false;
1023                 break;
1024         case 0x23:
1025                 /* typeId = DRX3923K_TYPE_ID */
1026                 state->m_hasLNA = false;
1027                 state->m_hasOOB = false;
1028                 state->m_hasATV = true;
1029                 state->m_hasAudio = true;
1030                 state->m_hasDVBT = true;
1031                 state->m_hasDVBC = true;
1032                 state->m_hasSAWSW = true;
1033                 state->m_hasGPIO2 = true;
1034                 state->m_hasGPIO1 = true;
1035                 state->m_hasIRQN = false;
1036                 break;
1037         case 0x25:
1038                 /* typeId = DRX3925K_TYPE_ID */
1039                 state->m_hasLNA = false;
1040                 state->m_hasOOB = false;
1041                 state->m_hasATV = true;
1042                 state->m_hasAudio = true;
1043                 state->m_hasDVBT = true;
1044                 state->m_hasDVBC = true;
1045                 state->m_hasSAWSW = true;
1046                 state->m_hasGPIO2 = true;
1047                 state->m_hasGPIO1 = true;
1048                 state->m_hasIRQN = false;
1049                 break;
1050         case 0x26:
1051                 /* typeId = DRX3926K_TYPE_ID */
1052                 state->m_hasLNA = false;
1053                 state->m_hasOOB = false;
1054                 state->m_hasATV = true;
1055                 state->m_hasAudio = false;
1056                 state->m_hasDVBT = true;
1057                 state->m_hasDVBC = true;
1058                 state->m_hasSAWSW = true;
1059                 state->m_hasGPIO2 = true;
1060                 state->m_hasGPIO1 = true;
1061                 state->m_hasIRQN = false;
1062                 break;
1063         default:
1064                 printk(KERN_ERR "drxk: DeviceID 0x%02x not supported\n",
1065                         ((sioTopJtagidLo >> 12) & 0xFF));
1066                 status = -EINVAL;
1067                 goto error2;
1068         }
1069
1070         printk(KERN_INFO
1071                "drxk: detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n",
1072                ((sioTopJtagidLo >> 12) & 0xFF), spin,
1073                state->m_oscClockFreq / 1000,
1074                state->m_oscClockFreq % 1000);
1075
1076 error:
1077         if (status < 0)
1078                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1079
1080 error2:
1081         return status;
1082 }
1083
1084 static int HI_Command(struct drxk_state *state, u16 cmd, u16 *pResult)
1085 {
1086         int status;
1087         bool powerdown_cmd;
1088
1089         dprintk(1, "\n");
1090
1091         /* Write command */
1092         status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
1093         if (status < 0)
1094                 goto error;
1095         if (cmd == SIO_HI_RA_RAM_CMD_RESET)
1096                 msleep(1);
1097
1098         powerdown_cmd =
1099             (bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
1100                     ((state->m_HICfgCtrl) &
1101                      SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M) ==
1102                     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ);
1103         if (powerdown_cmd == false) {
1104                 /* Wait until command rdy */
1105                 u32 retryCount = 0;
1106                 u16 waitCmd;
1107
1108                 do {
1109                         msleep(1);
1110                         retryCount += 1;
1111                         status = read16(state, SIO_HI_RA_RAM_CMD__A,
1112                                           &waitCmd);
1113                 } while ((status < 0) && (retryCount < DRXK_MAX_RETRIES)
1114                          && (waitCmd != 0));
1115                 if (status < 0)
1116                         goto error;
1117                 status = read16(state, SIO_HI_RA_RAM_RES__A, pResult);
1118         }
1119 error:
1120         if (status < 0)
1121                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1122
1123         return status;
1124 }
1125
1126 static int HI_CfgCommand(struct drxk_state *state)
1127 {
1128         int status;
1129
1130         dprintk(1, "\n");
1131
1132         mutex_lock(&state->mutex);
1133
1134         status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_HICfgTimeout);
1135         if (status < 0)
1136                 goto error;
1137         status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_HICfgCtrl);
1138         if (status < 0)
1139                 goto error;
1140         status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_HICfgWakeUpKey);
1141         if (status < 0)
1142                 goto error;
1143         status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_HICfgBridgeDelay);
1144         if (status < 0)
1145                 goto error;
1146         status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_HICfgTimingDiv);
1147         if (status < 0)
1148                 goto error;
1149         status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
1150         if (status < 0)
1151                 goto error;
1152         status = HI_Command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
1153         if (status < 0)
1154                 goto error;
1155
1156         state->m_HICfgCtrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1157 error:
1158         mutex_unlock(&state->mutex);
1159         if (status < 0)
1160                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1161         return status;
1162 }
1163
1164 static int InitHI(struct drxk_state *state)
1165 {
1166         dprintk(1, "\n");
1167
1168         state->m_HICfgWakeUpKey = (state->demod_address << 1);
1169         state->m_HICfgTimeout = 0x96FF;
1170         /* port/bridge/power down ctrl */
1171         state->m_HICfgCtrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1172
1173         return HI_CfgCommand(state);
1174 }
1175
1176 static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable)
1177 {
1178         int status = -1;
1179         u16 sioPdrMclkCfg = 0;
1180         u16 sioPdrMdxCfg = 0;
1181         u16 err_cfg = 0;
1182
1183         dprintk(1, ": mpeg %s, %s mode\n",
1184                 mpegEnable ? "enable" : "disable",
1185                 state->m_enableParallel ? "parallel" : "serial");
1186
1187         /* stop lock indicator process */
1188         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1189         if (status < 0)
1190                 goto error;
1191
1192         /*  MPEG TS pad configuration */
1193         status = write16(state, SIO_TOP_COMM_KEY__A, 0xFABA);
1194         if (status < 0)
1195                 goto error;
1196
1197         if (mpegEnable == false) {
1198                 /*  Set MPEG TS pads to inputmode */
1199                 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1200                 if (status < 0)
1201                         goto error;
1202                 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1203                 if (status < 0)
1204                         goto error;
1205                 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1206                 if (status < 0)
1207                         goto error;
1208                 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1209                 if (status < 0)
1210                         goto error;
1211                 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1212                 if (status < 0)
1213                         goto error;
1214                 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1215                 if (status < 0)
1216                         goto error;
1217                 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1218                 if (status < 0)
1219                         goto error;
1220                 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1221                 if (status < 0)
1222                         goto error;
1223                 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1224                 if (status < 0)
1225                         goto error;
1226                 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1227                 if (status < 0)
1228                         goto error;
1229                 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1230                 if (status < 0)
1231                         goto error;
1232                 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1233                 if (status < 0)
1234                         goto error;
1235         } else {
1236                 /* Enable MPEG output */
1237                 sioPdrMdxCfg =
1238                         ((state->m_TSDataStrength <<
1239                         SIO_PDR_MD0_CFG_DRIVE__B) | 0x0003);
1240                 sioPdrMclkCfg = ((state->m_TSClockkStrength <<
1241                                         SIO_PDR_MCLK_CFG_DRIVE__B) |
1242                                         0x0003);
1243
1244                 status = write16(state, SIO_PDR_MSTRT_CFG__A, sioPdrMdxCfg);
1245                 if (status < 0)
1246                         goto error;
1247
1248                 if (state->enable_merr_cfg)
1249                         err_cfg = sioPdrMdxCfg;
1250
1251                 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1252                 if (status < 0)
1253                         goto error;
1254                 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1255                 if (status < 0)
1256                         goto error;
1257
1258                 if (state->m_enableParallel == true) {
1259                         /* paralel -> enable MD1 to MD7 */
1260                         status = write16(state, SIO_PDR_MD1_CFG__A, sioPdrMdxCfg);
1261                         if (status < 0)
1262                                 goto error;
1263                         status = write16(state, SIO_PDR_MD2_CFG__A, sioPdrMdxCfg);
1264                         if (status < 0)
1265                                 goto error;
1266                         status = write16(state, SIO_PDR_MD3_CFG__A, sioPdrMdxCfg);
1267                         if (status < 0)
1268                                 goto error;
1269                         status = write16(state, SIO_PDR_MD4_CFG__A, sioPdrMdxCfg);
1270                         if (status < 0)
1271                                 goto error;
1272                         status = write16(state, SIO_PDR_MD5_CFG__A, sioPdrMdxCfg);
1273                         if (status < 0)
1274                                 goto error;
1275                         status = write16(state, SIO_PDR_MD6_CFG__A, sioPdrMdxCfg);
1276                         if (status < 0)
1277                                 goto error;
1278                         status = write16(state, SIO_PDR_MD7_CFG__A, sioPdrMdxCfg);
1279                         if (status < 0)
1280                                 goto error;
1281                 } else {
1282                         sioPdrMdxCfg = ((state->m_TSDataStrength <<
1283                                                 SIO_PDR_MD0_CFG_DRIVE__B)
1284                                         | 0x0003);
1285                         /* serial -> disable MD1 to MD7 */
1286                         status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1287                         if (status < 0)
1288                                 goto error;
1289                         status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1290                         if (status < 0)
1291                                 goto error;
1292                         status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1293                         if (status < 0)
1294                                 goto error;
1295                         status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1296                         if (status < 0)
1297                                 goto error;
1298                         status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1299                         if (status < 0)
1300                                 goto error;
1301                         status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1302                         if (status < 0)
1303                                 goto error;
1304                         status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1305                         if (status < 0)
1306                                 goto error;
1307                 }
1308                 status = write16(state, SIO_PDR_MCLK_CFG__A, sioPdrMclkCfg);
1309                 if (status < 0)
1310                         goto error;
1311                 status = write16(state, SIO_PDR_MD0_CFG__A, sioPdrMdxCfg);
1312                 if (status < 0)
1313                         goto error;
1314         }
1315         /*  Enable MB output over MPEG pads and ctl input */
1316         status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1317         if (status < 0)
1318                 goto error;
1319         /*  Write nomagic word to enable pdr reg write */
1320         status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1321 error:
1322         if (status < 0)
1323                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1324         return status;
1325 }
1326
1327 static int MPEGTSDisable(struct drxk_state *state)
1328 {
1329         dprintk(1, "\n");
1330
1331         return MPEGTSConfigurePins(state, false);
1332 }
1333
1334 static int BLChainCmd(struct drxk_state *state,
1335                       u16 romOffset, u16 nrOfElements, u32 timeOut)
1336 {
1337         u16 blStatus = 0;
1338         int status;
1339         unsigned long end;
1340
1341         dprintk(1, "\n");
1342         mutex_lock(&state->mutex);
1343         status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1344         if (status < 0)
1345                 goto error;
1346         status = write16(state, SIO_BL_CHAIN_ADDR__A, romOffset);
1347         if (status < 0)
1348                 goto error;
1349         status = write16(state, SIO_BL_CHAIN_LEN__A, nrOfElements);
1350         if (status < 0)
1351                 goto error;
1352         status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1353         if (status < 0)
1354                 goto error;
1355
1356         end = jiffies + msecs_to_jiffies(timeOut);
1357         do {
1358                 msleep(1);
1359                 status = read16(state, SIO_BL_STATUS__A, &blStatus);
1360                 if (status < 0)
1361                         goto error;
1362         } while ((blStatus == 0x1) &&
1363                         ((time_is_after_jiffies(end))));
1364
1365         if (blStatus == 0x1) {
1366                 printk(KERN_ERR "drxk: SIO not ready\n");
1367                 status = -EINVAL;
1368                 goto error2;
1369         }
1370 error:
1371         if (status < 0)
1372                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1373 error2:
1374         mutex_unlock(&state->mutex);
1375         return status;
1376 }
1377
1378
1379 static int DownloadMicrocode(struct drxk_state *state,
1380                              const u8 pMCImage[], u32 Length)
1381 {
1382         const u8 *pSrc = pMCImage;
1383         u16 Flags;
1384         u16 Drain;
1385         u32 Address;
1386         u16 nBlocks;
1387         u16 BlockSize;
1388         u16 BlockCRC;
1389         u32 offset = 0;
1390         u32 i;
1391         int status = 0;
1392
1393         dprintk(1, "\n");
1394
1395         /* down the drain (we don care about MAGIC_WORD) */
1396         Drain = (pSrc[0] << 8) | pSrc[1];
1397         pSrc += sizeof(u16);
1398         offset += sizeof(u16);
1399         nBlocks = (pSrc[0] << 8) | pSrc[1];
1400         pSrc += sizeof(u16);
1401         offset += sizeof(u16);
1402
1403         for (i = 0; i < nBlocks; i += 1) {
1404                 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
1405                     (pSrc[2] << 8) | pSrc[3];
1406                 pSrc += sizeof(u32);
1407                 offset += sizeof(u32);
1408
1409                 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
1410                 pSrc += sizeof(u16);
1411                 offset += sizeof(u16);
1412
1413                 Flags = (pSrc[0] << 8) | pSrc[1];
1414                 pSrc += sizeof(u16);
1415                 offset += sizeof(u16);
1416
1417                 BlockCRC = (pSrc[0] << 8) | pSrc[1];
1418                 pSrc += sizeof(u16);
1419                 offset += sizeof(u16);
1420
1421                 if (offset + BlockSize > Length) {
1422                         printk(KERN_ERR "drxk: Firmware is corrupted.\n");
1423                         return -EINVAL;
1424                 }
1425
1426                 status = write_block(state, Address, BlockSize, pSrc);
1427                 if (status < 0) {
1428                         printk(KERN_ERR "drxk: Error %d while loading firmware\n", status);
1429                         break;
1430                 }
1431                 pSrc += BlockSize;
1432                 offset += BlockSize;
1433         }
1434         return status;
1435 }
1436
1437 static int DVBTEnableOFDMTokenRing(struct drxk_state *state, bool enable)
1438 {
1439         int status;
1440         u16 data = 0;
1441         u16 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_ON;
1442         u16 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED;
1443         unsigned long end;
1444
1445         dprintk(1, "\n");
1446
1447         if (enable == false) {
1448                 desiredCtrl = SIO_OFDM_SH_OFDM_RING_ENABLE_OFF;
1449                 desiredStatus = SIO_OFDM_SH_OFDM_RING_STATUS_DOWN;
1450         }
1451
1452         status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1453         if (status >= 0 && data == desiredStatus) {
1454                 /* tokenring already has correct status */
1455                 return status;
1456         }
1457         /* Disable/enable dvbt tokenring bridge   */
1458         status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desiredCtrl);
1459
1460         end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
1461         do {
1462                 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1463                 if ((status >= 0 && data == desiredStatus) || time_is_after_jiffies(end))
1464                         break;
1465                 msleep(1);
1466         } while (1);
1467         if (data != desiredStatus) {
1468                 printk(KERN_ERR "drxk: SIO not ready\n");
1469                 return -EINVAL;
1470         }
1471         return status;
1472 }
1473
1474 static int MPEGTSStop(struct drxk_state *state)
1475 {
1476         int status = 0;
1477         u16 fecOcSncMode = 0;
1478         u16 fecOcIprMode = 0;
1479
1480         dprintk(1, "\n");
1481
1482         /* Gracefull shutdown (byte boundaries) */
1483         status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1484         if (status < 0)
1485                 goto error;
1486         fecOcSncMode |= FEC_OC_SNC_MODE_SHUTDOWN__M;
1487         status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1488         if (status < 0)
1489                 goto error;
1490
1491         /* Suppress MCLK during absence of data */
1492         status = read16(state, FEC_OC_IPR_MODE__A, &fecOcIprMode);
1493         if (status < 0)
1494                 goto error;
1495         fecOcIprMode |= FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M;
1496         status = write16(state, FEC_OC_IPR_MODE__A, fecOcIprMode);
1497
1498 error:
1499         if (status < 0)
1500                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1501
1502         return status;
1503 }
1504
1505 static int scu_command(struct drxk_state *state,
1506                        u16 cmd, u8 parameterLen,
1507                        u16 *parameter, u8 resultLen, u16 *result)
1508 {
1509 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15
1510 #error DRXK register mapping no longer compatible with this routine!
1511 #endif
1512         u16 curCmd = 0;
1513         int status = -EINVAL;
1514         unsigned long end;
1515         u8 buffer[34];
1516         int cnt = 0, ii;
1517         const char *p;
1518         char errname[30];
1519
1520         dprintk(1, "\n");
1521
1522         if ((cmd == 0) || ((parameterLen > 0) && (parameter == NULL)) ||
1523             ((resultLen > 0) && (result == NULL))) {
1524                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1525                 return status;
1526         }
1527
1528         mutex_lock(&state->mutex);
1529
1530         /* assume that the command register is ready
1531                 since it is checked afterwards */
1532         for (ii = parameterLen - 1; ii >= 0; ii -= 1) {
1533                 buffer[cnt++] = (parameter[ii] & 0xFF);
1534                 buffer[cnt++] = ((parameter[ii] >> 8) & 0xFF);
1535         }
1536         buffer[cnt++] = (cmd & 0xFF);
1537         buffer[cnt++] = ((cmd >> 8) & 0xFF);
1538
1539         write_block(state, SCU_RAM_PARAM_0__A -
1540                         (parameterLen - 1), cnt, buffer);
1541         /* Wait until SCU has processed command */
1542         end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
1543         do {
1544                 msleep(1);
1545                 status = read16(state, SCU_RAM_COMMAND__A, &curCmd);
1546                 if (status < 0)
1547                         goto error;
1548         } while (!(curCmd == DRX_SCU_READY) && (time_is_after_jiffies(end)));
1549         if (curCmd != DRX_SCU_READY) {
1550                 printk(KERN_ERR "drxk: SCU not ready\n");
1551                 status = -EIO;
1552                 goto error2;
1553         }
1554         /* read results */
1555         if ((resultLen > 0) && (result != NULL)) {
1556                 s16 err;
1557                 int ii;
1558
1559                 for (ii = resultLen - 1; ii >= 0; ii -= 1) {
1560                         status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
1561                         if (status < 0)
1562                                 goto error;
1563                 }
1564
1565                 /* Check if an error was reported by SCU */
1566                 err = (s16)result[0];
1567                 if (err >= 0)
1568                         goto error;
1569
1570                 /* check for the known error codes */
1571                 switch (err) {
1572                 case SCU_RESULT_UNKCMD:
1573                         p = "SCU_RESULT_UNKCMD";
1574                         break;
1575                 case SCU_RESULT_UNKSTD:
1576                         p = "SCU_RESULT_UNKSTD";
1577                         break;
1578                 case SCU_RESULT_SIZE:
1579                         p = "SCU_RESULT_SIZE";
1580                         break;
1581                 case SCU_RESULT_INVPAR:
1582                         p = "SCU_RESULT_INVPAR";
1583                         break;
1584                 default: /* Other negative values are errors */
1585                         sprintf(errname, "ERROR: %d\n", err);
1586                         p = errname;
1587                 }
1588                 printk(KERN_ERR "drxk: %s while sending cmd 0x%04x with params:", p, cmd);
1589                 print_hex_dump_bytes("drxk: ", DUMP_PREFIX_NONE, buffer, cnt);
1590                 status = -EINVAL;
1591                 goto error2;
1592         }
1593
1594 error:
1595         if (status < 0)
1596                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1597 error2:
1598         mutex_unlock(&state->mutex);
1599         return status;
1600 }
1601
1602 static int SetIqmAf(struct drxk_state *state, bool active)
1603 {
1604         u16 data = 0;
1605         int status;
1606
1607         dprintk(1, "\n");
1608
1609         /* Configure IQM */
1610         status = read16(state, IQM_AF_STDBY__A, &data);
1611         if (status < 0)
1612                 goto error;
1613
1614         if (!active) {
1615                 data |= (IQM_AF_STDBY_STDBY_ADC_STANDBY
1616                                 | IQM_AF_STDBY_STDBY_AMP_STANDBY
1617                                 | IQM_AF_STDBY_STDBY_PD_STANDBY
1618                                 | IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY
1619                                 | IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY);
1620         } else {
1621                 data &= ((~IQM_AF_STDBY_STDBY_ADC_STANDBY)
1622                                 & (~IQM_AF_STDBY_STDBY_AMP_STANDBY)
1623                                 & (~IQM_AF_STDBY_STDBY_PD_STANDBY)
1624                                 & (~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY)
1625                                 & (~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY)
1626                         );
1627         }
1628         status = write16(state, IQM_AF_STDBY__A, data);
1629
1630 error:
1631         if (status < 0)
1632                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1633         return status;
1634 }
1635
1636 static int CtrlPowerMode(struct drxk_state *state, enum DRXPowerMode *mode)
1637 {
1638         int status = 0;
1639         u16 sioCcPwdMode = 0;
1640
1641         dprintk(1, "\n");
1642
1643         /* Check arguments */
1644         if (mode == NULL)
1645                 return -EINVAL;
1646
1647         switch (*mode) {
1648         case DRX_POWER_UP:
1649                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_NONE;
1650                 break;
1651         case DRXK_POWER_DOWN_OFDM:
1652                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OFDM;
1653                 break;
1654         case DRXK_POWER_DOWN_CORE:
1655                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_CLOCK;
1656                 break;
1657         case DRXK_POWER_DOWN_PLL:
1658                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_PLL;
1659                 break;
1660         case DRX_POWER_DOWN:
1661                 sioCcPwdMode = SIO_CC_PWD_MODE_LEVEL_OSC;
1662                 break;
1663         default:
1664                 /* Unknow sleep mode */
1665                 return -EINVAL;
1666         }
1667
1668         /* If already in requested power mode, do nothing */
1669         if (state->m_currentPowerMode == *mode)
1670                 return 0;
1671
1672         /* For next steps make sure to start from DRX_POWER_UP mode */
1673         if (state->m_currentPowerMode != DRX_POWER_UP) {
1674                 status = PowerUpDevice(state);
1675                 if (status < 0)
1676                         goto error;
1677                 status = DVBTEnableOFDMTokenRing(state, true);
1678                 if (status < 0)
1679                         goto error;
1680         }
1681
1682         if (*mode == DRX_POWER_UP) {
1683                 /* Restore analog & pin configuartion */
1684         } else {
1685                 /* Power down to requested mode */
1686                 /* Backup some register settings */
1687                 /* Set pins with possible pull-ups connected
1688                    to them in input mode */
1689                 /* Analog power down */
1690                 /* ADC power down */
1691                 /* Power down device */
1692                 /* stop all comm_exec */
1693                 /* Stop and power down previous standard */
1694                 switch (state->m_OperationMode) {
1695                 case OM_DVBT:
1696                         status = MPEGTSStop(state);
1697                         if (status < 0)
1698                                 goto error;
1699                         status = PowerDownDVBT(state, false);
1700                         if (status < 0)
1701                                 goto error;
1702                         break;
1703                 case OM_QAM_ITU_A:
1704                 case OM_QAM_ITU_C:
1705                         status = MPEGTSStop(state);
1706                         if (status < 0)
1707                                 goto error;
1708                         status = PowerDownQAM(state);
1709                         if (status < 0)
1710                                 goto error;
1711                         break;
1712                 default:
1713                         break;
1714                 }
1715                 status = DVBTEnableOFDMTokenRing(state, false);
1716                 if (status < 0)
1717                         goto error;
1718                 status = write16(state, SIO_CC_PWD_MODE__A, sioCcPwdMode);
1719                 if (status < 0)
1720                         goto error;
1721                 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1722                 if (status < 0)
1723                         goto error;
1724
1725                 if (*mode != DRXK_POWER_DOWN_OFDM) {
1726                         state->m_HICfgCtrl |=
1727                                 SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1728                         status = HI_CfgCommand(state);
1729                         if (status < 0)
1730                                 goto error;
1731                 }
1732         }
1733         state->m_currentPowerMode = *mode;
1734
1735 error:
1736         if (status < 0)
1737                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1738
1739         return status;
1740 }
1741
1742 static int PowerDownDVBT(struct drxk_state *state, bool setPowerMode)
1743 {
1744         enum DRXPowerMode powerMode = DRXK_POWER_DOWN_OFDM;
1745         u16 cmdResult = 0;
1746         u16 data = 0;
1747         int status;
1748
1749         dprintk(1, "\n");
1750
1751         status = read16(state, SCU_COMM_EXEC__A, &data);
1752         if (status < 0)
1753                 goto error;
1754         if (data == SCU_COMM_EXEC_ACTIVE) {
1755                 /* Send OFDM stop command */
1756                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmdResult);
1757                 if (status < 0)
1758                         goto error;
1759                 /* Send OFDM reset command */
1760                 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmdResult);
1761                 if (status < 0)
1762                         goto error;
1763         }
1764
1765         /* Reset datapath for OFDM, processors first */
1766         status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1767         if (status < 0)
1768                 goto error;
1769         status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1770         if (status < 0)
1771                 goto error;
1772         status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1773         if (status < 0)
1774                 goto error;
1775
1776         /* powerdown AFE                   */
1777         status = SetIqmAf(state, false);
1778         if (status < 0)
1779                 goto error;
1780
1781         /* powerdown to OFDM mode          */
1782         if (setPowerMode) {
1783                 status = CtrlPowerMode(state, &powerMode);
1784                 if (status < 0)
1785                         goto error;
1786         }
1787 error:
1788         if (status < 0)
1789                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1790         return status;
1791 }
1792
1793 static int SetOperationMode(struct drxk_state *state,
1794                             enum OperationMode oMode)
1795 {
1796         int status = 0;
1797
1798         dprintk(1, "\n");
1799         /*
1800            Stop and power down previous standard
1801            TODO investigate total power down instead of partial
1802            power down depending on "previous" standard.
1803          */
1804
1805         /* disable HW lock indicator */
1806         status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
1807         if (status < 0)
1808                 goto error;
1809
1810         /* Device is already at the required mode */
1811         if (state->m_OperationMode == oMode)
1812                 return 0;
1813
1814         switch (state->m_OperationMode) {
1815                 /* OM_NONE was added for start up */
1816         case OM_NONE:
1817                 break;
1818         case OM_DVBT:
1819                 status = MPEGTSStop(state);
1820                 if (status < 0)
1821                         goto error;
1822                 status = PowerDownDVBT(state, true);
1823                 if (status < 0)
1824                         goto error;
1825                 state->m_OperationMode = OM_NONE;
1826                 break;
1827         case OM_QAM_ITU_A:      /* fallthrough */
1828         case OM_QAM_ITU_C:
1829                 status = MPEGTSStop(state);
1830                 if (status < 0)
1831                         goto error;
1832                 status = PowerDownQAM(state);
1833                 if (status < 0)
1834                         goto error;
1835                 state->m_OperationMode = OM_NONE;
1836                 break;
1837         case OM_QAM_ITU_B:
1838         default:
1839                 status = -EINVAL;
1840                 goto error;
1841         }
1842
1843         /*
1844                 Power up new standard
1845                 */
1846         switch (oMode) {
1847         case OM_DVBT:
1848                 dprintk(1, ": DVB-T\n");
1849                 state->m_OperationMode = oMode;
1850                 status = SetDVBTStandard(state, oMode);
1851                 if (status < 0)
1852                         goto error;
1853                 break;
1854         case OM_QAM_ITU_A:      /* fallthrough */
1855         case OM_QAM_ITU_C:
1856                 dprintk(1, ": DVB-C Annex %c\n",
1857                         (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C');
1858                 state->m_OperationMode = oMode;
1859                 status = SetQAMStandard(state, oMode);
1860                 if (status < 0)
1861                         goto error;
1862                 break;
1863         case OM_QAM_ITU_B:
1864         default:
1865                 status = -EINVAL;
1866         }
1867 error:
1868         if (status < 0)
1869                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1870         return status;
1871 }
1872
1873 static int Start(struct drxk_state *state, s32 offsetFreq,
1874                  s32 IntermediateFrequency)
1875 {
1876         int status = -EINVAL;
1877
1878         u16 IFreqkHz;
1879         s32 OffsetkHz = offsetFreq / 1000;
1880
1881         dprintk(1, "\n");
1882         if (state->m_DrxkState != DRXK_STOPPED &&
1883                 state->m_DrxkState != DRXK_DTV_STARTED)
1884                 goto error;
1885
1886         state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON);
1887
1888         if (IntermediateFrequency < 0) {
1889                 state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect;
1890                 IntermediateFrequency = -IntermediateFrequency;
1891         }
1892
1893         switch (state->m_OperationMode) {
1894         case OM_QAM_ITU_A:
1895         case OM_QAM_ITU_C:
1896                 IFreqkHz = (IntermediateFrequency / 1000);
1897                 status = SetQAM(state, IFreqkHz, OffsetkHz);
1898                 if (status < 0)
1899                         goto error;
1900                 state->m_DrxkState = DRXK_DTV_STARTED;
1901                 break;
1902         case OM_DVBT:
1903                 IFreqkHz = (IntermediateFrequency / 1000);
1904                 status = MPEGTSStop(state);
1905                 if (status < 0)
1906                         goto error;
1907                 status = SetDVBT(state, IFreqkHz, OffsetkHz);
1908                 if (status < 0)
1909                         goto error;
1910                 status = DVBTStart(state);
1911                 if (status < 0)
1912                         goto error;
1913                 state->m_DrxkState = DRXK_DTV_STARTED;
1914                 break;
1915         default:
1916                 break;
1917         }
1918 error:
1919         if (status < 0)
1920                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1921         return status;
1922 }
1923
1924 static int ShutDown(struct drxk_state *state)
1925 {
1926         dprintk(1, "\n");
1927
1928         MPEGTSStop(state);
1929         return 0;
1930 }
1931
1932 static int GetLockStatus(struct drxk_state *state, u32 *pLockStatus,
1933                          u32 Time)
1934 {
1935         int status = -EINVAL;
1936
1937         dprintk(1, "\n");
1938
1939         if (pLockStatus == NULL)
1940                 goto error;
1941
1942         *pLockStatus = NOT_LOCKED;
1943
1944         /* define the SCU command code */
1945         switch (state->m_OperationMode) {
1946         case OM_QAM_ITU_A:
1947         case OM_QAM_ITU_B:
1948         case OM_QAM_ITU_C:
1949                 status = GetQAMLockStatus(state, pLockStatus);
1950                 break;
1951         case OM_DVBT:
1952                 status = GetDVBTLockStatus(state, pLockStatus);
1953                 break;
1954         default:
1955                 break;
1956         }
1957 error:
1958         if (status < 0)
1959                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1960         return status;
1961 }
1962
1963 static int MPEGTSStart(struct drxk_state *state)
1964 {
1965         int status;
1966
1967         u16 fecOcSncMode = 0;
1968
1969         /* Allow OC to sync again */
1970         status = read16(state, FEC_OC_SNC_MODE__A, &fecOcSncMode);
1971         if (status < 0)
1972                 goto error;
1973         fecOcSncMode &= ~FEC_OC_SNC_MODE_SHUTDOWN__M;
1974         status = write16(state, FEC_OC_SNC_MODE__A, fecOcSncMode);
1975         if (status < 0)
1976                 goto error;
1977         status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1978 error:
1979         if (status < 0)
1980                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
1981         return status;
1982 }
1983
1984 static int MPEGTSDtoInit(struct drxk_state *state)
1985 {
1986         int status;
1987
1988         dprintk(1, "\n");
1989
1990         /* Rate integration settings */
1991         status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1992         if (status < 0)
1993                 goto error;
1994         status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1995         if (status < 0)
1996                 goto error;
1997         status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1998         if (status < 0)
1999                 goto error;
2000         status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
2001         if (status < 0)
2002                 goto error;
2003         status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
2004         if (status < 0)
2005                 goto error;
2006         status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
2007         if (status < 0)
2008                 goto error;
2009         status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
2010         if (status < 0)
2011                 goto error;
2012         status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
2013         if (status < 0)
2014                 goto error;
2015
2016         /* Additional configuration */
2017         status = write16(state, FEC_OC_OCR_INVERT__A, 0);
2018         if (status < 0)
2019                 goto error;
2020         status = write16(state, FEC_OC_SNC_LWM__A, 2);
2021         if (status < 0)
2022                 goto error;
2023         status = write16(state, FEC_OC_SNC_HWM__A, 12);
2024 error:
2025         if (status < 0)
2026                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2027
2028         return status;
2029 }
2030
2031 static int MPEGTSDtoSetup(struct drxk_state *state,
2032                           enum OperationMode oMode)
2033 {
2034         int status;
2035
2036         u16 fecOcRegMode = 0;   /* FEC_OC_MODE       register value */
2037         u16 fecOcRegIprMode = 0;        /* FEC_OC_IPR_MODE   register value */
2038         u16 fecOcDtoMode = 0;   /* FEC_OC_IPR_INVERT register value */
2039         u16 fecOcFctMode = 0;   /* FEC_OC_IPR_INVERT register value */
2040         u16 fecOcDtoPeriod = 2; /* FEC_OC_IPR_INVERT register value */
2041         u16 fecOcDtoBurstLen = 188;     /* FEC_OC_IPR_INVERT register value */
2042         u32 fecOcRcnCtlRate = 0;        /* FEC_OC_IPR_INVERT register value */
2043         u16 fecOcTmdMode = 0;
2044         u16 fecOcTmdIntUpdRate = 0;
2045         u32 maxBitRate = 0;
2046         bool staticCLK = false;
2047
2048         dprintk(1, "\n");
2049
2050         /* Check insertion of the Reed-Solomon parity bytes */
2051         status = read16(state, FEC_OC_MODE__A, &fecOcRegMode);
2052         if (status < 0)
2053                 goto error;
2054         status = read16(state, FEC_OC_IPR_MODE__A, &fecOcRegIprMode);
2055         if (status < 0)
2056                 goto error;
2057         fecOcRegMode &= (~FEC_OC_MODE_PARITY__M);
2058         fecOcRegIprMode &= (~FEC_OC_IPR_MODE_MVAL_DIS_PAR__M);
2059         if (state->m_insertRSByte == true) {
2060                 /* enable parity symbol forward */
2061                 fecOcRegMode |= FEC_OC_MODE_PARITY__M;
2062                 /* MVAL disable during parity bytes */
2063                 fecOcRegIprMode |= FEC_OC_IPR_MODE_MVAL_DIS_PAR__M;
2064                 /* TS burst length to 204 */
2065                 fecOcDtoBurstLen = 204;
2066         }
2067
2068         /* Check serial or parrallel output */
2069         fecOcRegIprMode &= (~(FEC_OC_IPR_MODE_SERIAL__M));
2070         if (state->m_enableParallel == false) {
2071                 /* MPEG data output is serial -> set ipr_mode[0] */
2072                 fecOcRegIprMode |= FEC_OC_IPR_MODE_SERIAL__M;
2073         }
2074
2075         switch (oMode) {
2076         case OM_DVBT:
2077                 maxBitRate = state->m_DVBTBitrate;
2078                 fecOcTmdMode = 3;
2079                 fecOcRcnCtlRate = 0xC00000;
2080                 staticCLK = state->m_DVBTStaticCLK;
2081                 break;
2082         case OM_QAM_ITU_A:      /* fallthrough */
2083         case OM_QAM_ITU_C:
2084                 fecOcTmdMode = 0x0004;
2085                 fecOcRcnCtlRate = 0xD2B4EE;     /* good for >63 Mb/s */
2086                 maxBitRate = state->m_DVBCBitrate;
2087                 staticCLK = state->m_DVBCStaticCLK;
2088                 break;
2089         default:
2090                 status = -EINVAL;
2091         }               /* switch (standard) */
2092         if (status < 0)
2093                 goto error;
2094
2095         /* Configure DTO's */
2096         if (staticCLK) {
2097                 u32 bitRate = 0;
2098
2099                 /* Rational DTO for MCLK source (static MCLK rate),
2100                         Dynamic DTO for optimal grouping
2101                         (avoid intra-packet gaps),
2102                         DTO offset enable to sync TS burst with MSTRT */
2103                 fecOcDtoMode = (FEC_OC_DTO_MODE_DYNAMIC__M |
2104                                 FEC_OC_DTO_MODE_OFFSET_ENABLE__M);
2105                 fecOcFctMode = (FEC_OC_FCT_MODE_RAT_ENA__M |
2106                                 FEC_OC_FCT_MODE_VIRT_ENA__M);
2107
2108                 /* Check user defined bitrate */
2109                 bitRate = maxBitRate;
2110                 if (bitRate > 75900000UL) {     /* max is 75.9 Mb/s */
2111                         bitRate = 75900000UL;
2112                 }
2113                 /* Rational DTO period:
2114                         dto_period = (Fsys / bitrate) - 2
2115
2116                         Result should be floored,
2117                         to make sure >= requested bitrate
2118                         */
2119                 fecOcDtoPeriod = (u16) (((state->m_sysClockFreq)
2120                                                 * 1000) / bitRate);
2121                 if (fecOcDtoPeriod <= 2)
2122                         fecOcDtoPeriod = 0;
2123                 else
2124                         fecOcDtoPeriod -= 2;
2125                 fecOcTmdIntUpdRate = 8;
2126         } else {
2127                 /* (commonAttr->staticCLK == false) => dynamic mode */
2128                 fecOcDtoMode = FEC_OC_DTO_MODE_DYNAMIC__M;
2129                 fecOcFctMode = FEC_OC_FCT_MODE__PRE;
2130                 fecOcTmdIntUpdRate = 5;
2131         }
2132
2133         /* Write appropriate registers with requested configuration */
2134         status = write16(state, FEC_OC_DTO_BURST_LEN__A, fecOcDtoBurstLen);
2135         if (status < 0)
2136                 goto error;
2137         status = write16(state, FEC_OC_DTO_PERIOD__A, fecOcDtoPeriod);
2138         if (status < 0)
2139                 goto error;
2140         status = write16(state, FEC_OC_DTO_MODE__A, fecOcDtoMode);
2141         if (status < 0)
2142                 goto error;
2143         status = write16(state, FEC_OC_FCT_MODE__A, fecOcFctMode);
2144         if (status < 0)
2145                 goto error;
2146         status = write16(state, FEC_OC_MODE__A, fecOcRegMode);
2147         if (status < 0)
2148                 goto error;
2149         status = write16(state, FEC_OC_IPR_MODE__A, fecOcRegIprMode);
2150         if (status < 0)
2151                 goto error;
2152
2153         /* Rate integration settings */
2154         status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fecOcRcnCtlRate);
2155         if (status < 0)
2156                 goto error;
2157         status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fecOcTmdIntUpdRate);
2158         if (status < 0)
2159                 goto error;
2160         status = write16(state, FEC_OC_TMD_MODE__A, fecOcTmdMode);
2161 error:
2162         if (status < 0)
2163                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2164         return status;
2165 }
2166
2167 static int MPEGTSConfigurePolarity(struct drxk_state *state)
2168 {
2169         u16 fecOcRegIprInvert = 0;
2170
2171         /* Data mask for the output data byte */
2172         u16 InvertDataMask =
2173             FEC_OC_IPR_INVERT_MD7__M | FEC_OC_IPR_INVERT_MD6__M |
2174             FEC_OC_IPR_INVERT_MD5__M | FEC_OC_IPR_INVERT_MD4__M |
2175             FEC_OC_IPR_INVERT_MD3__M | FEC_OC_IPR_INVERT_MD2__M |
2176             FEC_OC_IPR_INVERT_MD1__M | FEC_OC_IPR_INVERT_MD0__M;
2177
2178         dprintk(1, "\n");
2179
2180         /* Control selective inversion of output bits */
2181         fecOcRegIprInvert &= (~(InvertDataMask));
2182         if (state->m_invertDATA == true)
2183                 fecOcRegIprInvert |= InvertDataMask;
2184         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MERR__M));
2185         if (state->m_invertERR == true)
2186                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MERR__M;
2187         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MSTRT__M));
2188         if (state->m_invertSTR == true)
2189                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MSTRT__M;
2190         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MVAL__M));
2191         if (state->m_invertVAL == true)
2192                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MVAL__M;
2193         fecOcRegIprInvert &= (~(FEC_OC_IPR_INVERT_MCLK__M));
2194         if (state->m_invertCLK == true)
2195                 fecOcRegIprInvert |= FEC_OC_IPR_INVERT_MCLK__M;
2196
2197         return write16(state, FEC_OC_IPR_INVERT__A, fecOcRegIprInvert);
2198 }
2199
2200 #define   SCU_RAM_AGC_KI_INV_RF_POL__M 0x4000
2201
2202 static int SetAgcRf(struct drxk_state *state,
2203                     struct SCfgAgc *pAgcCfg, bool isDTV)
2204 {
2205         int status = -EINVAL;
2206         u16 data = 0;
2207         struct SCfgAgc *pIfAgcSettings;
2208
2209         dprintk(1, "\n");
2210
2211         if (pAgcCfg == NULL)
2212                 goto error;
2213
2214         switch (pAgcCfg->ctrlMode) {
2215         case DRXK_AGC_CTRL_AUTO:
2216                 /* Enable RF AGC DAC */
2217                 status = read16(state, IQM_AF_STDBY__A, &data);
2218                 if (status < 0)
2219                         goto error;
2220                 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2221                 status = write16(state, IQM_AF_STDBY__A, data);
2222                 if (status < 0)
2223                         goto error;
2224                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2225                 if (status < 0)
2226                         goto error;
2227
2228                 /* Enable SCU RF AGC loop */
2229                 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2230
2231                 /* Polarity */
2232                 if (state->m_RfAgcPol)
2233                         data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2234                 else
2235                         data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2236                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2237                 if (status < 0)
2238                         goto error;
2239
2240                 /* Set speed (using complementary reduction value) */
2241                 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2242                 if (status < 0)
2243                         goto error;
2244
2245                 data &= ~SCU_RAM_AGC_KI_RED_RAGC_RED__M;
2246                 data |= (~(pAgcCfg->speed <<
2247                                 SCU_RAM_AGC_KI_RED_RAGC_RED__B)
2248                                 & SCU_RAM_AGC_KI_RED_RAGC_RED__M);
2249
2250                 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2251                 if (status < 0)
2252                         goto error;
2253
2254                 if (IsDVBT(state))
2255                         pIfAgcSettings = &state->m_dvbtIfAgcCfg;
2256                 else if (IsQAM(state))
2257                         pIfAgcSettings = &state->m_qamIfAgcCfg;
2258                 else
2259                         pIfAgcSettings = &state->m_atvIfAgcCfg;
2260                 if (pIfAgcSettings == NULL) {
2261                         status = -EINVAL;
2262                         goto error;
2263                 }
2264
2265                 /* Set TOP, only if IF-AGC is in AUTO mode */
2266                 if (pIfAgcSettings->ctrlMode == DRXK_AGC_CTRL_AUTO)
2267                         status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->top);
2268                         if (status < 0)
2269                                 goto error;
2270
2271                 /* Cut-Off current */
2272                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, pAgcCfg->cutOffCurrent);
2273                 if (status < 0)
2274                         goto error;
2275
2276                 /* Max. output level */
2277                 status = write16(state, SCU_RAM_AGC_RF_MAX__A, pAgcCfg->maxOutputLevel);
2278                 if (status < 0)
2279                         goto error;
2280
2281                 break;
2282
2283         case DRXK_AGC_CTRL_USER:
2284                 /* Enable RF AGC DAC */
2285                 status = read16(state, IQM_AF_STDBY__A, &data);
2286                 if (status < 0)
2287                         goto error;
2288                 data &= ~IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2289                 status = write16(state, IQM_AF_STDBY__A, data);
2290                 if (status < 0)
2291                         goto error;
2292
2293                 /* Disable SCU RF AGC loop */
2294                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2295                 if (status < 0)
2296                         goto error;
2297                 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2298                 if (state->m_RfAgcPol)
2299                         data |= SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2300                 else
2301                         data &= ~SCU_RAM_AGC_CONFIG_INV_RF_POL__M;
2302                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2303                 if (status < 0)
2304                         goto error;
2305
2306                 /* SCU c.o.c. to 0, enabling full control range */
2307                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2308                 if (status < 0)
2309                         goto error;
2310
2311                 /* Write value to output pin */
2312                 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, pAgcCfg->outputLevel);
2313                 if (status < 0)
2314                         goto error;
2315                 break;
2316
2317         case DRXK_AGC_CTRL_OFF:
2318                 /* Disable RF AGC DAC */
2319                 status = read16(state, IQM_AF_STDBY__A, &data);
2320                 if (status < 0)
2321                         goto error;
2322                 data |= IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY;
2323                 status = write16(state, IQM_AF_STDBY__A, data);
2324                 if (status < 0)
2325                         goto error;
2326
2327                 /* Disable SCU RF AGC loop */
2328                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2329                 if (status < 0)
2330                         goto error;
2331                 data |= SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M;
2332                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2333                 if (status < 0)
2334                         goto error;
2335                 break;
2336
2337         default:
2338                 status = -EINVAL;
2339
2340         }
2341 error:
2342         if (status < 0)
2343                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2344         return status;
2345 }
2346
2347 #define SCU_RAM_AGC_KI_INV_IF_POL__M 0x2000
2348
2349 static int SetAgcIf(struct drxk_state *state,
2350                     struct SCfgAgc *pAgcCfg, bool isDTV)
2351 {
2352         u16 data = 0;
2353         int status = 0;
2354         struct SCfgAgc *pRfAgcSettings;
2355
2356         dprintk(1, "\n");
2357
2358         switch (pAgcCfg->ctrlMode) {
2359         case DRXK_AGC_CTRL_AUTO:
2360
2361                 /* Enable IF AGC DAC */
2362                 status = read16(state, IQM_AF_STDBY__A, &data);
2363                 if (status < 0)
2364                         goto error;
2365                 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2366                 status = write16(state, IQM_AF_STDBY__A, data);
2367                 if (status < 0)
2368                         goto error;
2369
2370                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2371                 if (status < 0)
2372                         goto error;
2373
2374                 /* Enable SCU IF AGC loop */
2375                 data &= ~SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2376
2377                 /* Polarity */
2378                 if (state->m_IfAgcPol)
2379                         data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2380                 else
2381                         data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2382                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2383                 if (status < 0)
2384                         goto error;
2385
2386                 /* Set speed (using complementary reduction value) */
2387                 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2388                 if (status < 0)
2389                         goto error;
2390                 data &= ~SCU_RAM_AGC_KI_RED_IAGC_RED__M;
2391                 data |= (~(pAgcCfg->speed <<
2392                                 SCU_RAM_AGC_KI_RED_IAGC_RED__B)
2393                                 & SCU_RAM_AGC_KI_RED_IAGC_RED__M);
2394
2395                 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2396                 if (status < 0)
2397                         goto error;
2398
2399                 if (IsQAM(state))
2400                         pRfAgcSettings = &state->m_qamRfAgcCfg;
2401                 else
2402                         pRfAgcSettings = &state->m_atvRfAgcCfg;
2403                 if (pRfAgcSettings == NULL)
2404                         return -1;
2405                 /* Restore TOP */
2406                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pRfAgcSettings->top);
2407                 if (status < 0)
2408                         goto error;
2409                 break;
2410
2411         case DRXK_AGC_CTRL_USER:
2412
2413                 /* Enable IF AGC DAC */
2414                 status = read16(state, IQM_AF_STDBY__A, &data);
2415                 if (status < 0)
2416                         goto error;
2417                 data &= ~IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2418                 status = write16(state, IQM_AF_STDBY__A, data);
2419                 if (status < 0)
2420                         goto error;
2421
2422                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2423                 if (status < 0)
2424                         goto error;
2425
2426                 /* Disable SCU IF AGC loop */
2427                 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2428
2429                 /* Polarity */
2430                 if (state->m_IfAgcPol)
2431                         data |= SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2432                 else
2433                         data &= ~SCU_RAM_AGC_CONFIG_INV_IF_POL__M;
2434                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2435                 if (status < 0)
2436                         goto error;
2437
2438                 /* Write value to output pin */
2439                 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, pAgcCfg->outputLevel);
2440                 if (status < 0)
2441                         goto error;
2442                 break;
2443
2444         case DRXK_AGC_CTRL_OFF:
2445
2446                 /* Disable If AGC DAC */
2447                 status = read16(state, IQM_AF_STDBY__A, &data);
2448                 if (status < 0)
2449                         goto error;
2450                 data |= IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY;
2451                 status = write16(state, IQM_AF_STDBY__A, data);
2452                 if (status < 0)
2453                         goto error;
2454
2455                 /* Disable SCU IF AGC loop */
2456                 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2457                 if (status < 0)
2458                         goto error;
2459                 data |= SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M;
2460                 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2461                 if (status < 0)
2462                         goto error;
2463                 break;
2464         }               /* switch (agcSettingsIf->ctrlMode) */
2465
2466         /* always set the top to support
2467                 configurations without if-loop */
2468         status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, pAgcCfg->top);
2469 error:
2470         if (status < 0)
2471                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2472         return status;
2473 }
2474
2475 static int ReadIFAgc(struct drxk_state *state, u32 *pValue)
2476 {
2477         u16 agcDacLvl;
2478         int status;
2479         u16 Level = 0;
2480
2481         dprintk(1, "\n");
2482
2483         status = read16(state, IQM_AF_AGC_IF__A, &agcDacLvl);
2484         if (status < 0) {
2485                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2486                 return status;
2487         }
2488
2489         *pValue = 0;
2490
2491         if (agcDacLvl > DRXK_AGC_DAC_OFFSET)
2492                 Level = agcDacLvl - DRXK_AGC_DAC_OFFSET;
2493         if (Level < 14000)
2494                 *pValue = (14000 - Level) / 4;
2495         else
2496                 *pValue = 0;
2497
2498         return status;
2499 }
2500
2501 static int GetQAMSignalToNoise(struct drxk_state *state,
2502                                s32 *pSignalToNoise)
2503 {
2504         int status = 0;
2505         u16 qamSlErrPower = 0;  /* accum. error between
2506                                         raw and sliced symbols */
2507         u32 qamSlSigPower = 0;  /* used for MER, depends of
2508                                         QAM modulation */
2509         u32 qamSlMer = 0;       /* QAM MER */
2510
2511         dprintk(1, "\n");
2512
2513         /* MER calculation */
2514
2515         /* get the register value needed for MER */
2516         status = read16(state, QAM_SL_ERR_POWER__A, &qamSlErrPower);
2517         if (status < 0) {
2518                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2519                 return -EINVAL;
2520         }
2521
2522         switch (state->props.modulation) {
2523         case QAM_16:
2524                 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2;
2525                 break;
2526         case QAM_32:
2527                 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM32 << 2;
2528                 break;
2529         case QAM_64:
2530                 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM64 << 2;
2531                 break;
2532         case QAM_128:
2533                 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM128 << 2;
2534                 break;
2535         default:
2536         case QAM_256:
2537                 qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM256 << 2;
2538                 break;
2539         }
2540
2541         if (qamSlErrPower > 0) {
2542                 qamSlMer = Log10Times100(qamSlSigPower) -
2543                         Log10Times100((u32) qamSlErrPower);
2544         }
2545         *pSignalToNoise = qamSlMer;
2546
2547         return status;
2548 }
2549
2550 static int GetDVBTSignalToNoise(struct drxk_state *state,
2551                                 s32 *pSignalToNoise)
2552 {
2553         int status;
2554         u16 regData = 0;
2555         u32 EqRegTdSqrErrI = 0;
2556         u32 EqRegTdSqrErrQ = 0;
2557         u16 EqRegTdSqrErrExp = 0;
2558         u16 EqRegTdTpsPwrOfs = 0;
2559         u16 EqRegTdReqSmbCnt = 0;
2560         u32 tpsCnt = 0;
2561         u32 SqrErrIQ = 0;
2562         u32 a = 0;
2563         u32 b = 0;
2564         u32 c = 0;
2565         u32 iMER = 0;
2566         u16 transmissionParams = 0;
2567
2568         dprintk(1, "\n");
2569
2570         status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &EqRegTdTpsPwrOfs);
2571         if (status < 0)
2572                 goto error;
2573         status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &EqRegTdReqSmbCnt);
2574         if (status < 0)
2575                 goto error;
2576         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &EqRegTdSqrErrExp);
2577         if (status < 0)
2578                 goto error;
2579         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, &regData);
2580         if (status < 0)
2581                 goto error;
2582         /* Extend SQR_ERR_I operational range */
2583         EqRegTdSqrErrI = (u32) regData;
2584         if ((EqRegTdSqrErrExp > 11) &&
2585                 (EqRegTdSqrErrI < 0x00000FFFUL)) {
2586                 EqRegTdSqrErrI += 0x00010000UL;
2587         }
2588         status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &regData);
2589         if (status < 0)
2590                 goto error;
2591         /* Extend SQR_ERR_Q operational range */
2592         EqRegTdSqrErrQ = (u32) regData;
2593         if ((EqRegTdSqrErrExp > 11) &&
2594                 (EqRegTdSqrErrQ < 0x00000FFFUL))
2595                 EqRegTdSqrErrQ += 0x00010000UL;
2596
2597         status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmissionParams);
2598         if (status < 0)
2599                 goto error;
2600
2601         /* Check input data for MER */
2602
2603         /* MER calculation (in 0.1 dB) without math.h */
2604         if ((EqRegTdTpsPwrOfs == 0) || (EqRegTdReqSmbCnt == 0))
2605                 iMER = 0;
2606         else if ((EqRegTdSqrErrI + EqRegTdSqrErrQ) == 0) {
2607                 /* No error at all, this must be the HW reset value
2608                         * Apparently no first measurement yet
2609                         * Set MER to 0.0 */
2610                 iMER = 0;
2611         } else {
2612                 SqrErrIQ = (EqRegTdSqrErrI + EqRegTdSqrErrQ) <<
2613                         EqRegTdSqrErrExp;
2614                 if ((transmissionParams &
2615                         OFDM_SC_RA_RAM_OP_PARAM_MODE__M)
2616                         == OFDM_SC_RA_RAM_OP_PARAM_MODE_2K)
2617                         tpsCnt = 17;
2618                 else
2619                         tpsCnt = 68;
2620
2621                 /* IMER = 100 * log10 (x)
2622                         where x = (EqRegTdTpsPwrOfs^2 *
2623                         EqRegTdReqSmbCnt * tpsCnt)/SqrErrIQ
2624
2625                         => IMER = a + b -c
2626                         where a = 100 * log10 (EqRegTdTpsPwrOfs^2)
2627                         b = 100 * log10 (EqRegTdReqSmbCnt * tpsCnt)
2628                         c = 100 * log10 (SqrErrIQ)
2629                         */
2630
2631                 /* log(x) x = 9bits * 9bits->18 bits  */
2632                 a = Log10Times100(EqRegTdTpsPwrOfs *
2633                                         EqRegTdTpsPwrOfs);
2634                 /* log(x) x = 16bits * 7bits->23 bits  */
2635                 b = Log10Times100(EqRegTdReqSmbCnt * tpsCnt);
2636                 /* log(x) x = (16bits + 16bits) << 15 ->32 bits  */
2637                 c = Log10Times100(SqrErrIQ);
2638
2639                 iMER = a + b;
2640                 /* No negative MER, clip to zero */
2641                 if (iMER > c)
2642                         iMER -= c;
2643                 else
2644                         iMER = 0;
2645         }
2646         *pSignalToNoise = iMER;
2647
2648 error:
2649         if (status < 0)
2650                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2651         return status;
2652 }
2653
2654 static int GetSignalToNoise(struct drxk_state *state, s32 *pSignalToNoise)
2655 {
2656         dprintk(1, "\n");
2657
2658         *pSignalToNoise = 0;
2659         switch (state->m_OperationMode) {
2660         case OM_DVBT:
2661                 return GetDVBTSignalToNoise(state, pSignalToNoise);
2662         case OM_QAM_ITU_A:
2663         case OM_QAM_ITU_C:
2664                 return GetQAMSignalToNoise(state, pSignalToNoise);
2665         default:
2666                 break;
2667         }
2668         return 0;
2669 }
2670
2671 #if 0
2672 static int GetDVBTQuality(struct drxk_state *state, s32 *pQuality)
2673 {
2674         /* SNR Values for quasi errorfree reception rom Nordig 2.2 */
2675         int status = 0;
2676
2677         dprintk(1, "\n");
2678
2679         static s32 QE_SN[] = {
2680                 51,             /* QPSK 1/2 */
2681                 69,             /* QPSK 2/3 */
2682                 79,             /* QPSK 3/4 */
2683                 89,             /* QPSK 5/6 */
2684                 97,             /* QPSK 7/8 */
2685                 108,            /* 16-QAM 1/2 */
2686                 131,            /* 16-QAM 2/3 */
2687                 146,            /* 16-QAM 3/4 */
2688                 156,            /* 16-QAM 5/6 */
2689                 160,            /* 16-QAM 7/8 */
2690                 165,            /* 64-QAM 1/2 */
2691                 187,            /* 64-QAM 2/3 */
2692                 202,            /* 64-QAM 3/4 */
2693                 216,            /* 64-QAM 5/6 */
2694                 225,            /* 64-QAM 7/8 */
2695         };
2696
2697         *pQuality = 0;
2698
2699         do {
2700                 s32 SignalToNoise = 0;
2701                 u16 Constellation = 0;
2702                 u16 CodeRate = 0;
2703                 u32 SignalToNoiseRel;
2704                 u32 BERQuality;
2705
2706                 status = GetDVBTSignalToNoise(state, &SignalToNoise);
2707                 if (status < 0)
2708                         break;
2709                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &Constellation);
2710                 if (status < 0)
2711                         break;
2712                 Constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
2713
2714                 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &CodeRate);
2715                 if (status < 0)
2716                         break;
2717                 CodeRate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
2718
2719                 if (Constellation > OFDM_EQ_TOP_TD_TPS_CONST_64QAM ||
2720                     CodeRate > OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8)
2721                         break;
2722                 SignalToNoiseRel = SignalToNoise -
2723                     QE_SN[Constellation * 5 + CodeRate];
2724                 BERQuality = 100;
2725
2726                 if (SignalToNoiseRel < -70)
2727                         *pQuality = 0;
2728                 else if (SignalToNoiseRel < 30)
2729                         *pQuality = ((SignalToNoiseRel + 70) *
2730                                      BERQuality) / 100;
2731                 else
2732                         *pQuality = BERQuality;
2733         } while (0);
2734         return 0;
2735 };
2736
2737 static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality)
2738 {
2739         int status = 0;
2740         *pQuality = 0;
2741
2742         dprintk(1, "\n");
2743
2744         do {
2745                 u32 SignalToNoise = 0;
2746                 u32 BERQuality = 100;
2747                 u32 SignalToNoiseRel = 0;
2748
2749                 status = GetQAMSignalToNoise(state, &SignalToNoise);
2750                 if (status < 0)
2751                         break;
2752
2753                 switch (state->props.modulation) {
2754                 case QAM_16:
2755                         SignalToNoiseRel = SignalToNoise - 200;
2756                         break;
2757                 case QAM_32:
2758                         SignalToNoiseRel = SignalToNoise - 230;
2759                         break;  /* Not in NorDig */
2760                 case QAM_64:
2761                         SignalToNoiseRel = SignalToNoise - 260;
2762                         break;
2763                 case QAM_128:
2764                         SignalToNoiseRel = SignalToNoise - 290;
2765                         break;
2766                 default:
2767                 case QAM_256:
2768                         SignalToNoiseRel = SignalToNoise - 320;
2769                         break;
2770                 }
2771
2772                 if (SignalToNoiseRel < -70)
2773                         *pQuality = 0;
2774                 else if (SignalToNoiseRel < 30)
2775                         *pQuality = ((SignalToNoiseRel + 70) *
2776                                      BERQuality) / 100;
2777                 else
2778                         *pQuality = BERQuality;
2779         } while (0);
2780
2781         return status;
2782 }
2783
2784 static int GetQuality(struct drxk_state *state, s32 *pQuality)
2785 {
2786         dprintk(1, "\n");
2787
2788         switch (state->m_OperationMode) {
2789         case OM_DVBT:
2790                 return GetDVBTQuality(state, pQuality);
2791         case OM_QAM_ITU_A:
2792                 return GetDVBCQuality(state, pQuality);
2793         default:
2794                 break;
2795         }
2796
2797         return 0;
2798 }
2799 #endif
2800
2801 /* Free data ram in SIO HI */
2802 #define SIO_HI_RA_RAM_USR_BEGIN__A 0x420040
2803 #define SIO_HI_RA_RAM_USR_END__A   0x420060
2804
2805 #define DRXK_HI_ATOMIC_BUF_START (SIO_HI_RA_RAM_USR_BEGIN__A)
2806 #define DRXK_HI_ATOMIC_BUF_END   (SIO_HI_RA_RAM_USR_BEGIN__A + 7)
2807 #define DRXK_HI_ATOMIC_READ      SIO_HI_RA_RAM_PAR_3_ACP_RW_READ
2808 #define DRXK_HI_ATOMIC_WRITE     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE
2809
2810 #define DRXDAP_FASI_ADDR2BLOCK(addr)  (((addr) >> 22) & 0x3F)
2811 #define DRXDAP_FASI_ADDR2BANK(addr)   (((addr) >> 16) & 0x3F)
2812 #define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr) & 0x7FFF)
2813
2814 static int ConfigureI2CBridge(struct drxk_state *state, bool bEnableBridge)
2815 {
2816         int status = -EINVAL;
2817
2818         dprintk(1, "\n");
2819
2820         if (state->m_DrxkState == DRXK_UNINITIALIZED)
2821                 goto error;
2822         if (state->m_DrxkState == DRXK_POWERED_DOWN)
2823                 goto error;
2824
2825         if (state->no_i2c_bridge)
2826                 return 0;
2827
2828         status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
2829         if (status < 0)
2830                 goto error;
2831         if (bEnableBridge) {
2832                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
2833                 if (status < 0)
2834                         goto error;
2835         } else {
2836                 status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
2837                 if (status < 0)
2838                         goto error;
2839         }
2840
2841         status = HI_Command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, 0);
2842
2843 error:
2844         if (status < 0)
2845                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2846         return status;
2847 }
2848
2849 static int SetPreSaw(struct drxk_state *state,
2850                      struct SCfgPreSaw *pPreSawCfg)
2851 {
2852         int status = -EINVAL;
2853
2854         dprintk(1, "\n");
2855
2856         if ((pPreSawCfg == NULL)
2857             || (pPreSawCfg->reference > IQM_AF_PDREF__M))
2858                 goto error;
2859
2860         status = write16(state, IQM_AF_PDREF__A, pPreSawCfg->reference);
2861 error:
2862         if (status < 0)
2863                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2864         return status;
2865 }
2866
2867 static int BLDirectCmd(struct drxk_state *state, u32 targetAddr,
2868                        u16 romOffset, u16 nrOfElements, u32 timeOut)
2869 {
2870         u16 blStatus = 0;
2871         u16 offset = (u16) ((targetAddr >> 0) & 0x00FFFF);
2872         u16 blockbank = (u16) ((targetAddr >> 16) & 0x000FFF);
2873         int status;
2874         unsigned long end;
2875
2876         dprintk(1, "\n");
2877
2878         mutex_lock(&state->mutex);
2879         status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2880         if (status < 0)
2881                 goto error;
2882         status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2883         if (status < 0)
2884                 goto error;
2885         status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2886         if (status < 0)
2887                 goto error;
2888         status = write16(state, SIO_BL_SRC_ADDR__A, romOffset);
2889         if (status < 0)
2890                 goto error;
2891         status = write16(state, SIO_BL_SRC_LEN__A, nrOfElements);
2892         if (status < 0)
2893                 goto error;
2894         status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2895         if (status < 0)
2896                 goto error;
2897
2898         end = jiffies + msecs_to_jiffies(timeOut);
2899         do {
2900                 status = read16(state, SIO_BL_STATUS__A, &blStatus);
2901                 if (status < 0)
2902                         goto error;
2903         } while ((blStatus == 0x1) && time_is_after_jiffies(end));
2904         if (blStatus == 0x1) {
2905                 printk(KERN_ERR "drxk: SIO not ready\n");
2906                 status = -EINVAL;
2907                 goto error2;
2908         }
2909 error:
2910         if (status < 0)
2911                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2912 error2:
2913         mutex_unlock(&state->mutex);
2914         return status;
2915
2916 }
2917
2918 static int ADCSyncMeasurement(struct drxk_state *state, u16 *count)
2919 {
2920         u16 data = 0;
2921         int status;
2922
2923         dprintk(1, "\n");
2924
2925         /* Start measurement */
2926         status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2927         if (status < 0)
2928                 goto error;
2929         status = write16(state, IQM_AF_START_LOCK__A, 1);
2930         if (status < 0)
2931                 goto error;
2932
2933         *count = 0;
2934         status = read16(state, IQM_AF_PHASE0__A, &data);
2935         if (status < 0)
2936                 goto error;
2937         if (data == 127)
2938                 *count = *count + 1;
2939         status = read16(state, IQM_AF_PHASE1__A, &data);
2940         if (status < 0)
2941                 goto error;
2942         if (data == 127)
2943                 *count = *count + 1;
2944         status = read16(state, IQM_AF_PHASE2__A, &data);
2945         if (status < 0)
2946                 goto error;
2947         if (data == 127)
2948                 *count = *count + 1;
2949
2950 error:
2951         if (status < 0)
2952                 printk(KERN_ERR "drxk: Error %d on %s\n", status, __func__);
2953         return status;
2954 }
2955
2956 static int ADCSynchronization(struct drxk_state *state)
2957 {
2958         u16 count = 0;
2959         int status;
2960