drivers/media/dvb/frontends/dib7000p.c

   1 /*
   2  * Linux-DVB Driver for DiBcom's second generation DiB7000P (PC).
   3  *
   4  * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License as
   8  *      published by the Free Software Foundation, version 2.
   9  */
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/i2c.h>
  13
  14 #include "dvb_math.h"
  15 #include "dvb_frontend.h"
  16
  17 #include "dib7000p.h"
  18
  19 static int debug;
  20 module_param(debug, int, 0644);
  21 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
  22
  23 static int buggy_sfn_workaround;
  24 module_param(buggy_sfn_workaround, int, 0644);
  25 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
  26
  27 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB7000P: "); printk(args); printk("\n"); } } while (0)
  28
  29 struct i2c_device {
  30         struct i2c_adapter *i2c_adap;
  31         u8 i2c_addr;
  32 };
  33
  34 struct dib7000p_state {
  35         struct dvb_frontend demod;
  36         struct dib7000p_config cfg;
  37
  38         u8 i2c_addr;
  39         struct i2c_adapter *i2c_adap;
  40
  41         struct dibx000_i2c_master i2c_master;
  42
  43         u16 wbd_ref;
  44
  45         u8 current_band;
  46         u32 current_bandwidth;
  47         struct dibx000_agc_config *current_agc;
  48         u32 timf;
  49
  50         u8 div_force_off:1;
  51         u8 div_state:1;
  52         u16 div_sync_wait;
  53
  54         u8 agc_state;
  55
  56         u16 gpio_dir;
  57         u16 gpio_val;
  58
  59         u8 sfn_workaround_active:1;
  60
  61 #define SOC7090 0x7090
  62         u16 version;
  63
  64         u16 tuner_enable;
  65         struct i2c_adapter dib7090_tuner_adap;
  66 };
  67
  68 enum dib7000p_power_mode {
  69         DIB7000P_POWER_ALL = 0,
  70         DIB7000P_POWER_ANALOG_ADC,
  71         DIB7000P_POWER_INTERFACE_ONLY,
  72 };
  73
  74 static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode);
  75 static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff);
  76
  77 static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
  78 {
  79         u8 wb[2] = { reg >> 8, reg & 0xff };
  80         u8 rb[2];
  81         struct i2c_msg msg[2] = {
  82                 {.addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
  83                 {.addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2},
  84         };
  85
  86         if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
  87                 dprintk("i2c read error on %d", reg);
  88
  89         return (rb[0] << 8) | rb[1];
  90 }
  91
  92 static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
  93 {
  94         u8 b[4] = {
  95                 (reg >> 8) & 0xff, reg & 0xff,
  96                 (val >> 8) & 0xff, val & 0xff,
  97         };
  98         struct i2c_msg msg = {
  99                 .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
 100         };
 101         return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
 102 }
 103
 104 static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
 105 {
 106         u16 l = 0, r, *n;
 107         n = buf;
 108         l = *n++;
 109         while (l) {
 110                 r = *n++;
 111
 112                 do {
 113                         dib7000p_write_word(state, r, *n++);
 114                         r++;
 115                 } while (--l);
 116                 l = *n++;
 117         }
 118 }
 119
 120 static int dib7000p_set_output_mode(struct dib7000p_state *state, int mode)
 121 {
 122         int ret = 0;
 123         u16 outreg, fifo_threshold, smo_mode;
 124
 125         outreg = 0;
 126         fifo_threshold = 1792;
 127         smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
 128
 129         dprintk("setting output mode for demod %p to %d", &state->demod, mode);
 130
 131         switch (mode) {
 132         case OUTMODE_MPEG2_PAR_GATED_CLK:
 133                 outreg = (1 << 10);     /* 0x0400 */
 134                 break;
 135         case OUTMODE_MPEG2_PAR_CONT_CLK:
 136                 outreg = (1 << 10) | (1 << 6);  /* 0x0440 */
 137                 break;
 138         case OUTMODE_MPEG2_SERIAL:
 139                 outreg = (1 << 10) | (2 << 6) | (0 << 1);       /* 0x0480 */
 140                 break;
 141         case OUTMODE_DIVERSITY:
 142                 if (state->cfg.hostbus_diversity)
 143                         outreg = (1 << 10) | (4 << 6);  /* 0x0500 */
 144                 else
 145                         outreg = (1 << 11);
 146                 break;
 147         case OUTMODE_MPEG2_FIFO:
 148                 smo_mode |= (3 << 1);
 149                 fifo_threshold = 512;
 150                 outreg = (1 << 10) | (5 << 6);
 151                 break;
 152         case OUTMODE_ANALOG_ADC:
 153                 outreg = (1 << 10) | (3 << 6);
 154                 break;
 155         case OUTMODE_HIGH_Z:
 156                 outreg = 0;
 157                 break;
 158         default:
 159                 dprintk("Unhandled output_mode passed to be set for demod %p", &state->demod);
 160                 break;
 161         }
 162
 163         if (state->cfg.output_mpeg2_in_188_bytes)
 164                 smo_mode |= (1 << 5);
 165
 166         ret |= dib7000p_write_word(state, 235, smo_mode);
 167         ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
 168         if (state->version != SOC7090)
 169                 ret |= dib7000p_write_word(state, 1286, outreg);        /* P_Div_active */
 170
 171         return ret;
 172 }
 173
 174 static int dib7000p_set_diversity_in(struct dvb_frontend *demod, int onoff)
 175 {
 176         struct dib7000p_state *state = demod->demodulator_priv;
 177
 178         if (state->div_force_off) {
 179                 dprintk("diversity combination deactivated - forced by COFDM parameters");
 180                 onoff = 0;
 181                 dib7000p_write_word(state, 207, 0);
 182         } else
 183                 dib7000p_write_word(state, 207, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0));
 184
 185         state->div_state = (u8) onoff;
 186
 187         if (onoff) {
 188                 dib7000p_write_word(state, 204, 6);
 189                 dib7000p_write_word(state, 205, 16);
 190                 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */
 191         } else {
 192                 dib7000p_write_word(state, 204, 1);
 193                 dib7000p_write_word(state, 205, 0);
 194         }
 195
 196         return 0;
 197 }
 198
 199 static int dib7000p_set_power_mode(struct dib7000p_state *state, enum dib7000p_power_mode mode)
 200 {
 201         /* by default everything is powered off */
 202         u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0x0007, reg_899 = 0x0003, reg_1280 = (0xfe00) | (dib7000p_read_word(state, 1280) & 0x01ff);
 203
 204         /* now, depending on the requested mode, we power on */
 205         switch (mode) {
 206                 /* power up everything in the demod */
 207         case DIB7000P_POWER_ALL:
 208                 reg_774 = 0x0000;
 209                 reg_775 = 0x0000;
 210                 reg_776 = 0x0;
 211                 reg_899 = 0x0;
 212                 if (state->version == SOC7090)
 213                         reg_1280 &= 0x001f;
 214                 else
 215                         reg_1280 &= 0x01ff;
 216                 break;
 217
 218         case DIB7000P_POWER_ANALOG_ADC:
 219                 /* dem, cfg, iqc, sad, agc */
 220                 reg_774 &= ~((1 << 15) | (1 << 14) | (1 << 11) | (1 << 10) | (1 << 9));
 221                 /* nud */
 222                 reg_776 &= ~((1 << 0));
 223                 /* Dout */
 224                 if (state->version != SOC7090)
 225                         reg_1280 &= ~((1 << 11));
 226                 reg_1280 &= ~(1 << 6);
 227                 /* fall through wanted to enable the interfaces */
 228
 229                 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO) */
 230         case DIB7000P_POWER_INTERFACE_ONLY:     /* TODO power up either SDIO or I2C */
 231                 if (state->version == SOC7090)
 232                         reg_1280 &= ~((1 << 7) | (1 << 5));
 233                 else
 234                         reg_1280 &= ~((1 << 14) | (1 << 13) | (1 << 12) | (1 << 10));
 235                 break;
 236
 237 /* TODO following stuff is just converted from the dib7000-driver - check when is used what */
 238         }
 239
 240         dib7000p_write_word(state, 774, reg_774);
 241         dib7000p_write_word(state, 775, reg_775);
 242         dib7000p_write_word(state, 776, reg_776);
 243         dib7000p_write_word(state, 899, reg_899);
 244         dib7000p_write_word(state, 1280, reg_1280);
 245
 246         return 0;
 247 }
 248
 249 static void dib7000p_set_adc_state(struct dib7000p_state *state, enum dibx000_adc_states no)
 250 {
 251         u16 reg_908 = dib7000p_read_word(state, 908), reg_909 = dib7000p_read_word(state, 909);
 252         u16 reg;
 253
 254         switch (no) {
 255         case DIBX000_SLOW_ADC_ON:
 256                 if (state->version == SOC7090) {
 257                         reg = dib7000p_read_word(state, 1925);
 258
 259                         dib7000p_write_word(state, 1925, reg | (1 << 4) | (1 << 2));    /* en_slowAdc = 1 & reset_sladc = 1 */
 260
 261                         reg = dib7000p_read_word(state, 1925);  /* read acces to make it works... strange ... */
 262                         msleep(200);
 263                         dib7000p_write_word(state, 1925, reg & ~(1 << 4));      /* en_slowAdc = 1 & reset_sladc = 0 */
 264
 265                         reg = dib7000p_read_word(state, 72) & ~((0x3 << 14) | (0x3 << 12));
 266                         dib7000p_write_word(state, 72, reg | (1 << 14) | (3 << 12) | 524);      /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ; (Vin2 = Vcm) */
 267                 } else {
 268                         reg_909 |= (1 << 1) | (1 << 0);
 269                         dib7000p_write_word(state, 909, reg_909);
 270                         reg_909 &= ~(1 << 1);
 271                 }
 272                 break;
 273
 274         case DIBX000_SLOW_ADC_OFF:
 275                 if (state->version == SOC7090) {
 276                         reg = dib7000p_read_word(state, 1925);
 277                         dib7000p_write_word(state, 1925, (reg & ~(1 << 2)) | (1 << 4)); /* reset_sladc = 1 en_slowAdc = 0 */
 278                 } else
 279                         reg_909 |= (1 << 1) | (1 << 0);
 280                 break;
 281
 282         case DIBX000_ADC_ON:
 283                 reg_908 &= 0x0fff;
 284                 reg_909 &= 0x0003;
 285                 break;
 286
 287         case DIBX000_ADC_OFF:
 288                 reg_908 |= (1 << 14) | (1 << 13) | (1 << 12);
 289                 reg_909 |= (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2);
 290                 break;
 291
 292         case DIBX000_VBG_ENABLE:
 293                 reg_908 &= ~(1 << 15);
 294                 break;
 295
 296         case DIBX000_VBG_DISABLE:
 297                 reg_908 |= (1 << 15);
 298                 break;
 299
 300         default:
 301                 break;
 302         }
 303
 304 //      dprintk( "908: %x, 909: %x\n", reg_908, reg_909);
 305
 306         reg_909 |= (state->cfg.disable_sample_and_hold & 1) << 4;
 307         reg_908 |= (state->cfg.enable_current_mirror & 1) << 7;
 308
 309         dib7000p_write_word(state, 908, reg_908);
 310         dib7000p_write_word(state, 909, reg_909);
 311 }
 312
 313 static int dib7000p_set_bandwidth(struct dib7000p_state *state, u32 bw)
 314 {
 315         u32 timf;
 316
 317         // store the current bandwidth for later use
 318         state->current_bandwidth = bw;
 319
 320         if (state->timf == 0) {
 321                 dprintk("using default timf");
 322                 timf = state->cfg.bw->timf;
 323         } else {
 324                 dprintk("using updated timf");
 325                 timf = state->timf;
 326         }
 327
 328         timf = timf * (bw / 50) / 160;
 329
 330         dib7000p_write_word(state, 23, (u16) ((timf >> 16) & 0xffff));
 331         dib7000p_write_word(state, 24, (u16) ((timf) & 0xffff));
 332
 333         return 0;
 334 }
 335
 336 static int dib7000p_sad_calib(struct dib7000p_state *state)
 337 {
 338 /* internal */
 339         dib7000p_write_word(state, 73, (0 << 1) | (0 << 0));
 340
 341         if (state->version == SOC7090)
 342                 dib7000p_write_word(state, 74, 2048);
 343         else
 344                 dib7000p_write_word(state, 74, 776);
 345
 346         /* do the calibration */
 347         dib7000p_write_word(state, 73, (1 << 0));
 348         dib7000p_write_word(state, 73, (0 << 0));
 349
 350         msleep(1);
 351
 352         return 0;
 353 }
 354
 355 int dib7000p_set_wbd_ref(struct dvb_frontend *demod, u16 value)
 356 {
 357         struct dib7000p_state *state = demod->demodulator_priv;
 358         if (value > 4095)
 359                 value = 4095;
 360         state->wbd_ref = value;
 361         return dib7000p_write_word(state, 105, (dib7000p_read_word(state, 105) & 0xf000) | value);
 362 }
 363 EXPORT_SYMBOL(dib7000p_set_wbd_ref);
 364
 365 static void dib7000p_reset_pll(struct dib7000p_state *state)
 366 {
 367         struct dibx000_bandwidth_config *bw = &state->cfg.bw[0];
 368         u16 clk_cfg0;
 369
 370         if (state->version == SOC7090) {
 371                 dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv));
 372
 373                 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
 374                         ;
 375
 376                 dib7000p_write_word(state, 1857, dib7000p_read_word(state, 1857) | (!bw->pll_bypass << 15));
 377         } else {
 378                 /* force PLL bypass */
 379                 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) |
 380                         (bw->modulo << 7) | (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | (bw->enable_refdiv << 1) | (0 << 0);
 381
 382                 dib7000p_write_word(state, 900, clk_cfg0);
 383
 384                 /* P_pll_cfg */
 385                 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
 386                 clk_cfg0 = (bw->pll_bypass << 15) | (clk_cfg0 & 0x7fff);
 387                 dib7000p_write_word(state, 900, clk_cfg0);
 388         }
 389
 390         dib7000p_write_word(state, 18, (u16) (((bw->internal * 1000) >> 16) & 0xffff));
 391         dib7000p_write_word(state, 19, (u16) ((bw->internal * 1000) & 0xffff));
 392         dib7000p_write_word(state, 21, (u16) ((bw->ifreq >> 16) & 0xffff));
 393         dib7000p_write_word(state, 22, (u16) ((bw->ifreq) & 0xffff));
 394
 395         dib7000p_write_word(state, 72, bw->sad_cfg);
 396 }
 397
 398 static u32 dib7000p_get_internal_freq(struct dib7000p_state *state)
 399 {
 400         u32 internal = (u32) dib7000p_read_word(state, 18) << 16;
 401         internal |= (u32) dib7000p_read_word(state, 19);
 402         internal /= 1000;
 403
 404         return internal;
 405 }
 406
 407 int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth_config *bw)
 408 {
 409         struct dib7000p_state *state = fe->demodulator_priv;
 410         u16 reg_1857, reg_1856 = dib7000p_read_word(state, 1856);
 411         u8 loopdiv, prediv;
 412         u32 internal, xtal;
 413
 414         /* get back old values */
 415         prediv = reg_1856 & 0x3f;
 416         loopdiv = (reg_1856 >> 6) & 0x3f;
 417
 418         if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) {
 419                 dprintk("Updating pll (prediv: old =  %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio);
 420                 reg_1856 &= 0xf000;
 421                 reg_1857 = dib7000p_read_word(state, 1857);
 422                 dib7000p_write_word(state, 1857, reg_1857 & ~(1 << 15));
 423
 424                 dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f));
 425
 426                 /* write new system clk into P_sec_len */
 427                 internal = dib7000p_get_internal_freq(state);
 428                 xtal = (internal / loopdiv) * prediv;
 429                 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio;      /* new internal */
 430                 dib7000p_write_word(state, 18, (u16) ((internal >> 16) & 0xffff));
 431                 dib7000p_write_word(state, 19, (u16) (internal & 0xffff));
 432
 433                 dib7000p_write_word(state, 1857, reg_1857 | (1 << 15));
 434
 435                 while (((dib7000p_read_word(state, 1856) >> 15) & 0x1) != 1)
 436                         dprintk("Waiting for PLL to lock");
 437
 438                 return 0;
 439         }
 440         return -EIO;
 441 }
 442 EXPORT_SYMBOL(dib7000p_update_pll);
 443
 444 static int dib7000p_reset_gpio(struct dib7000p_state *st)
 445 {
 446         /* reset the GPIOs */
 447         dprintk("gpio dir: %x: val: %x, pwm_pos: %x", st->gpio_dir, st->gpio_val, st->cfg.gpio_pwm_pos);
 448
 449         dib7000p_write_word(st, 1029, st->gpio_dir);
 450         dib7000p_write_word(st, 1030, st->gpio_val);
 451
 452         /* TODO 1031 is P_gpio_od */
 453
 454         dib7000p_write_word(st, 1032, st->cfg.gpio_pwm_pos);
 455
 456         dib7000p_write_word(st, 1037, st->cfg.pwm_freq_div);
 457         return 0;
 458 }
 459
 460 static int dib7000p_cfg_gpio(struct dib7000p_state *st, u8 num, u8 dir, u8 val)
 461 {
 462         st->gpio_dir = dib7000p_read_word(st, 1029);
 463         st->gpio_dir &= ~(1 << num);    /* reset the direction bit */
 464         st->gpio_dir |= (dir & 0x1) << num;     /* set the new direction */
 465         dib7000p_write_word(st, 1029, st->gpio_dir);
 466
 467         st->gpio_val = dib7000p_read_word(st, 1030);
 468         st->gpio_val &= ~(1 << num);    /* reset the direction bit */
 469         st->gpio_val |= (val & 0x01) << num;    /* set the new value */
 470         dib7000p_write_word(st, 1030, st->gpio_val);
 471
 472         return 0;
 473 }
 474
 475 int dib7000p_set_gpio(struct dvb_frontend *demod, u8 num, u8 dir, u8 val)
 476 {
 477         struct dib7000p_state *state = demod->demodulator_priv;
 478         return dib7000p_cfg_gpio(state, num, dir, val);
 479 }
 480 EXPORT_SYMBOL(dib7000p_set_gpio);
 481
 482 static u16 dib7000p_defaults[] = {
 483         // auto search configuration
 484         3, 2,
 485         0x0004,
 486         0x1000,
 487         0x0814,                 /* Equal Lock */
 488
 489         12, 6,
 490         0x001b,
 491         0x7740,
 492         0x005b,
 493         0x8d80,
 494         0x01c9,
 495         0xc380,
 496         0x0000,
 497         0x0080,
 498         0x0000,
 499         0x0090,
 500         0x0001,
 501         0xd4c0,
 502
 503         1, 26,
 504         0x6680,
 505
 506         /* set ADC level to -16 */
 507         11, 79,
 508         (1 << 13) - 825 - 117,
 509         (1 << 13) - 837 - 117,
 510         (1 << 13) - 811 - 117,
 511         (1 << 13) - 766 - 117,
 512         (1 << 13) - 737 - 117,
 513         (1 << 13) - 693 - 117,
 514         (1 << 13) - 648 - 117,
 515         (1 << 13) - 619 - 117,
 516         (1 << 13) - 575 - 117,
 517         (1 << 13) - 531 - 117,
 518         (1 << 13) - 501 - 117,
 519
 520         1, 142,
 521         0x0410,
 522
 523         /* disable power smoothing */
 524         8, 145,
 525         0,
 526         0,
 527         0,
 528         0,
 529         0,
 530         0,
 531         0,
 532         0,
 533
 534         1, 154,
 535         1 << 13,
 536
 537         1, 168,
 538         0x0ccd,
 539
 540         1, 183,
 541         0x200f,
 542
 543         1, 212,
 544                 0x169,
 545
 546         5, 187,
 547         0x023d,
 548         0x00a4,
 549         0x00a4,
 550         0x7ff0,
 551         0x3ccc,
 552
 553         1, 198,
 554         0x800,
 555
 556         1, 222,
 557         0x0010,
 558
 559         1, 235,
 560         0x0062,
 561
 562         2, 901,
 563         0x0006,
 564         (3 << 10) | (1 << 6),
 565
 566         1, 905,
 567         0x2c8e,
 568
 569         0,
 570 };
 571
 572 static int dib7000p_demod_reset(struct dib7000p_state *state)
 573 {
 574         dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
 575
 576         if (state->version == SOC7090)
 577                 dibx000_reset_i2c_master(&state->i2c_master);
 578
 579         dib7000p_set_adc_state(state, DIBX000_VBG_ENABLE);
 580
 581         /* restart all parts */
 582         dib7000p_write_word(state, 770, 0xffff);
 583         dib7000p_write_word(state, 771, 0xffff);
 584         dib7000p_write_word(state, 772, 0x001f);
 585         dib7000p_write_word(state, 898, 0x0003);
 586         dib7000p_write_word(state, 1280, 0x001f - ((1 << 4) | (1 << 3)));
 587
 588         dib7000p_write_word(state, 770, 0);
 589         dib7000p_write_word(state, 771, 0);
 590         dib7000p_write_word(state, 772, 0);
 591         dib7000p_write_word(state, 898, 0);
 592         dib7000p_write_word(state, 1280, 0);
 593
 594         /* default */
 595         dib7000p_reset_pll(state);
 596
 597         if (dib7000p_reset_gpio(state) != 0)
 598                 dprintk("GPIO reset was not successful.");
 599
 600         if (state->version == SOC7090) {
 601                 dib7000p_write_word(state, 899, 0);
 602
 603                 /* impulse noise */
 604                 dib7000p_write_word(state, 42, (1<<5) | 3); /* P_iqc_thsat_ipc = 1 ; P_iqc_win2 = 3 */
 605                 dib7000p_write_word(state, 43, 0x2d4); /*-300 fag P_iqc_dect_min = -280 */
 606                 dib7000p_write_word(state, 44, 300); /* 300 fag P_iqc_dect_min = +280 */
 607                 dib7000p_write_word(state, 273, (1<<6) | 30);
 608         }
 609         if (dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) != 0)
 610                 dprintk("OUTPUT_MODE could not be reset.");
 611
 612         dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
 613         dib7000p_sad_calib(state);
 614         dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
 615
 616         /* unforce divstr regardless whether i2c enumeration was done or not */
 617         dib7000p_write_word(state, 1285, dib7000p_read_word(state, 1285) & ~(1 << 1));
 618
 619         dib7000p_set_bandwidth(state, 8000);
 620
 621         if (state->version == SOC7090) {
 622                 dib7000p_write_word(state, 36, 0x5755);/* P_iqc_impnc_on =1 & P_iqc_corr_inh = 1 for impulsive noise */
 623         } else {
 624                 if (state->cfg.tuner_is_baseband)
 625                         dib7000p_write_word(state, 36, 0x0755);
 626                 else
 627                         dib7000p_write_word(state, 36, 0x1f55);
 628         }
 629
 630         dib7000p_write_tab(state, dib7000p_defaults);
 631
 632         dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
 633
 634         return 0;
 635 }
 636
 637 static void dib7000p_pll_clk_cfg(struct dib7000p_state *state)
 638 {
 639         u16 tmp = 0;
 640         tmp = dib7000p_read_word(state, 903);
 641         dib7000p_write_word(state, 903, (tmp | 0x1));
 642         tmp = dib7000p_read_word(state, 900);
 643         dib7000p_write_word(state, 900, (tmp & 0x7fff) | (1 << 6));
 644 }
 645
 646 static void dib7000p_restart_agc(struct dib7000p_state *state)
 647 {
 648         // P_restart_iqc & P_restart_agc
 649         dib7000p_write_word(state, 770, (1 << 11) | (1 << 9));
 650         dib7000p_write_word(state, 770, 0x0000);
 651 }
 652
 653 static int dib7000p_update_lna(struct dib7000p_state *state)
 654 {
 655         u16 dyn_gain;
 656
 657         if (state->cfg.update_lna) {
 658                 dyn_gain = dib7000p_read_word(state, 394);
 659                 if (state->cfg.update_lna(&state->demod, dyn_gain)) {
 660                         dib7000p_restart_agc(state);
 661                         return 1;
 662                 }
 663         }
 664
 665         return 0;
 666 }
 667
 668 static int dib7000p_set_agc_config(struct dib7000p_state *state, u8 band)
 669 {
 670         struct dibx000_agc_config *agc = NULL;
 671         int i;
 672         if (state->current_band == band && state->current_agc != NULL)
 673                 return 0;
 674         state->current_band = band;
 675
 676         for (i = 0; i < state->cfg.agc_config_count; i++)
 677                 if (state->cfg.agc[i].band_caps & band) {
 678                         agc = &state->cfg.agc[i];
 679                         break;
 680                 }
 681
 682         if (agc == NULL) {
 683                 dprintk("no valid AGC configuration found for band 0x%02x", band);
 684                 return -EINVAL;
 685         }
 686
 687         state->current_agc = agc;
 688
 689         /* AGC */
 690         dib7000p_write_word(state, 75, agc->setup);
 691         dib7000p_write_word(state, 76, agc->inv_gain);
 692         dib7000p_write_word(state, 77, agc->time_stabiliz);
 693         dib7000p_write_word(state, 100, (agc->alpha_level << 12) | agc->thlock);
 694
 695         // Demod AGC loop configuration
 696         dib7000p_write_word(state, 101, (agc->alpha_mant << 5) | agc->alpha_exp);
 697         dib7000p_write_word(state, 102, (agc->beta_mant << 6) | agc->beta_exp);
 698
 699         /* AGC continued */
 700         dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
 701                 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
 702
 703         if (state->wbd_ref != 0)
 704                 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | state->wbd_ref);
 705         else
 706                 dib7000p_write_word(state, 105, (agc->wbd_inv << 12) | agc->wbd_ref);
 707
 708         dib7000p_write_word(state, 106, (agc->wbd_sel << 13) | (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
 709
 710         dib7000p_write_word(state, 107, agc->agc1_max);
 711         dib7000p_write_word(state, 108, agc->agc1_min);
 712         dib7000p_write_word(state, 109, agc->agc2_max);
 713         dib7000p_write_word(state, 110, agc->agc2_min);
 714         dib7000p_write_word(state, 111, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
 715         dib7000p_write_word(state, 112, agc->agc1_pt3);
 716         dib7000p_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
 717         dib7000p_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
 718         dib7000p_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
 719         return 0;
 720 }
 721
 722 static void dib7000p_set_dds(struct dib7000p_state *state, s32 offset_khz)
 723 {
 724         u32 internal = dib7000p_get_internal_freq(state);
 725         s32 unit_khz_dds_val = 67108864 / (internal);   /* 2**26 / Fsampling is the unit 1KHz offset */
 726         u32 abs_offset_khz = ABS(offset_khz);
 727         u32 dds = state->cfg.bw->ifreq & 0x1ffffff;
 728         u8 invert = !!(state->cfg.bw->ifreq & (1 << 25));
 729
 730         dprintk("setting a frequency offset of %dkHz internal freq = %d invert = %d", offset_khz, internal, invert);
 731
 732         if (offset_khz < 0)
 733                 unit_khz_dds_val *= -1;
 734
 735         /* IF tuner */
 736         if (invert)
 737                 dds -= (abs_offset_khz * unit_khz_dds_val);     /* /100 because of /100 on the unit_khz_dds_val line calc for better accuracy */
 738         else
 739                 dds += (abs_offset_khz * unit_khz_dds_val);
 740
 741         if (abs_offset_khz <= (internal / 2)) { /* Max dds offset is the half of the demod freq */
 742                 dib7000p_write_word(state, 21, (u16) (((dds >> 16) & 0x1ff) | (0 << 10) | (invert << 9)));
 743                 dib7000p_write_word(state, 22, (u16) (dds & 0xffff));
 744         }
 745 }
 746
 747 static int dib7000p_agc_startup(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
 748 {
 749         struct dib7000p_state *state = demod->demodulator_priv;
 750         int ret = -1;
 751         u8 *agc_state = &state->agc_state;
 752         u8 agc_split;
 753         u16 reg;
 754         u32 upd_demod_gain_period = 0x1000;
 755
 756         switch (state->agc_state) {
 757         case 0:
 758                 dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
 759                 if (state->version == SOC7090) {
 760                         reg = dib7000p_read_word(state, 0x79b) & 0xff00;
 761                         dib7000p_write_word(state, 0x79a, upd_demod_gain_period & 0xFFFF);      /* lsb */
 762                         dib7000p_write_word(state, 0x79b, reg | (1 << 14) | ((upd_demod_gain_period >> 16) & 0xFF));
 763
 764                         /* enable adc i & q */
 765                         reg = dib7000p_read_word(state, 0x780);
 766                         dib7000p_write_word(state, 0x780, (reg | (0x3)) & (~(1 << 7)));
 767                 } else {
 768                         dib7000p_set_adc_state(state, DIBX000_ADC_ON);
 769                         dib7000p_pll_clk_cfg(state);
 770                 }
 771
 772                 if (dib7000p_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency / 1000)) != 0)
 773                         return -1;
 774
 775                 dib7000p_set_dds(state, 0);
 776                 ret = 7;
 777                 (*agc_state)++;
 778                 break;
 779
 780         case 1:
 781                 if (state->cfg.agc_control)
 782                         state->cfg.agc_control(&state->demod, 1);
 783
 784                 dib7000p_write_word(state, 78, 32768);
 785                 if (!state->current_agc->perform_agc_softsplit) {
 786                         /* we are using the wbd - so slow AGC startup */
 787                         /* force 0 split on WBD and restart AGC */
 788                         dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | (1 << 8));
 789                         (*agc_state)++;
 790                         ret = 5;
 791                 } else {
 792                         /* default AGC startup */
 793                         (*agc_state) = 4;
 794                         /* wait AGC rough lock time */
 795                         ret = 7;
 796                 }
 797
 798                 dib7000p_restart_agc(state);
 799                 break;
 800
 801         case 2:         /* fast split search path after 5sec */
 802                 dib7000p_write_word(state, 75, state->current_agc->setup | (1 << 4));   /* freeze AGC loop */
 803                 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (2 << 9) | (0 << 8));     /* fast split search 0.25kHz */
 804                 (*agc_state)++;
 805                 ret = 14;
 806                 break;
 807
 808         case 3:         /* split search ended */
 809                 agc_split = (u8) dib7000p_read_word(state, 396);        /* store the split value for the next time */
 810                 dib7000p_write_word(state, 78, dib7000p_read_word(state, 394)); /* set AGC gain start value */
 811
 812                 dib7000p_write_word(state, 75, state->current_agc->setup);      /* std AGC loop */
 813                 dib7000p_write_word(state, 106, (state->current_agc->wbd_sel << 13) | (state->current_agc->wbd_alpha << 9) | agc_split);        /* standard split search */
 814
 815                 dib7000p_restart_agc(state);
 816
 817                 dprintk("SPLIT %p: %hd", demod, agc_split);
 818
 819                 (*agc_state)++;
 820                 ret = 5;
 821                 break;
 822
 823         case 4:         /* LNA startup */
 824                 ret = 7;
 825
 826                 if (dib7000p_update_lna(state))
 827                         ret = 5;
 828                 else
 829                         (*agc_state)++;
 830                 break;
 831
 832         case 5:
 833                 if (state->cfg.agc_control)
 834                         state->cfg.agc_control(&state->demod, 0);
 835                 (*agc_state)++;
 836                 break;
 837         default:
 838                 break;
 839         }
 840         return ret;
 841 }
 842
 843 static void dib7000p_update_timf(struct dib7000p_state *state)
 844 {
 845         u32 timf = (dib7000p_read_word(state, 427) << 16) | dib7000p_read_word(state, 428);
 846         state->timf = timf * 160 / (state->current_bandwidth / 50);
 847         dib7000p_write_word(state, 23, (u16) (timf >> 16));
 848         dib7000p_write_word(state, 24, (u16) (timf & 0xffff));
 849         dprintk("updated timf_frequency: %d (default: %d)", state->timf, state->cfg.bw->timf);
 850
 851 }
 852
 853 u32 dib7000p_ctrl_timf(struct dvb_frontend *fe, u8 op, u32 timf)
 854 {
 855         struct dib7000p_state *state = fe->demodulator_priv;
 856         switch (op) {
 857         case DEMOD_TIMF_SET:
 858                 state->timf = timf;
 859                 break;
 860         case DEMOD_TIMF_UPDATE:
 861                 dib7000p_update_timf(state);
 862                 break;
 863         case DEMOD_TIMF_GET:
 864                 break;
 865         }
 866         dib7000p_set_bandwidth(state, state->current_bandwidth);
 867         return state->timf;
 868 }
 869 EXPORT_SYMBOL(dib7000p_ctrl_timf);
 870
 871 static void dib7000p_set_channel(struct dib7000p_state *state, struct dvb_frontend_parameters *ch, u8 seq)
 872 {
 873         u16 value, est[4];
 874
 875         dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
 876
 877         /* nfft, guard, qam, alpha */
 878         value = 0;
 879         switch (ch->u.ofdm.transmission_mode) {
 880         case TRANSMISSION_MODE_2K:
 881                 value |= (0 << 7);
 882                 break;
 883         case TRANSMISSION_MODE_4K:
 884                 value |= (2 << 7);
 885                 break;
 886         default:
 887         case TRANSMISSION_MODE_8K:
 888                 value |= (1 << 7);
 889                 break;
 890         }
 891         switch (ch->u.ofdm.guard_interval) {
 892         case GUARD_INTERVAL_1_32:
 893                 value |= (0 << 5);
 894                 break;
 895         case GUARD_INTERVAL_1_16:
 896                 value |= (1 << 5);
 897                 break;
 898         case GUARD_INTERVAL_1_4:
 899                 value |= (3 << 5);
 900                 break;
 901         default:
 902         case GUARD_INTERVAL_1_8:
 903                 value |= (2 << 5);
 904                 break;
 905         }
 906         switch (ch->u.ofdm.constellation) {
 907         case QPSK:
 908                 value |= (0 << 3);
 909                 break;
 910         case QAM_16:
 911                 value |= (1 << 3);
 912                 break;
 913         default:
 914         case QAM_64:
 915                 value |= (2 << 3);
 916                 break;
 917         }
 918         switch (HIERARCHY_1) {
 919         case HIERARCHY_2:
 920                 value |= 2;
 921                 break;
 922         case HIERARCHY_4:
 923                 value |= 4;
 924                 break;
 925         default:
 926         case HIERARCHY_1:
 927                 value |= 1;
 928                 break;
 929         }
 930         dib7000p_write_word(state, 0, value);
 931         dib7000p_write_word(state, 5, (seq << 4) | 1);  /* do not force tps, search list 0 */
 932
 933         /* P_dintl_native, P_dintlv_inv, P_hrch, P_code_rate, P_select_hp */
 934         value = 0;
 935         if (1 != 0)
 936                 value |= (1 << 6);
 937         if (ch->u.ofdm.hierarchy_information == 1)
 938                 value |= (1 << 4);
 939         if (1 == 1)
 940                 value |= 1;
 941         switch ((ch->u.ofdm.hierarchy_information == 0 || 1 == 1) ? ch->u.ofdm.code_rate_HP : ch->u.ofdm.code_rate_LP) {
 942         case FEC_2_3:
 943                 value |= (2 << 1);
 944                 break;
 945         case FEC_3_4:
 946                 value |= (3 << 1);
 947                 break;
 948         case FEC_5_6:
 949                 value |= (5 << 1);
 950                 break;
 951         case FEC_7_8:
 952                 value |= (7 << 1);
 953                 break;
 954         default:
 955         case FEC_1_2:
 956                 value |= (1 << 1);
 957                 break;
 958         }
 959         dib7000p_write_word(state, 208, value);
 960
 961         /* offset loop parameters */
 962         dib7000p_write_word(state, 26, 0x6680);
 963         dib7000p_write_word(state, 32, 0x0003);
 964         dib7000p_write_word(state, 29, 0x1273);
 965         dib7000p_write_word(state, 33, 0x0005);
 966
 967         /* P_dvsy_sync_wait */
 968         switch (ch->u.ofdm.transmission_mode) {
 969         case TRANSMISSION_MODE_8K:
 970                 value = 256;
 971                 break;
 972         case TRANSMISSION_MODE_4K:
 973                 value = 128;
 974                 break;
 975         case TRANSMISSION_MODE_2K:
 976         default:
 977                 value = 64;
 978                 break;
 979         }
 980         switch (ch->u.ofdm.guard_interval) {
 981         case GUARD_INTERVAL_1_16:
 982                 value *= 2;
 983                 break;
 984         case GUARD_INTERVAL_1_8:
 985                 value *= 4;
 986                 break;
 987         case GUARD_INTERVAL_1_4:
 988                 value *= 8;
 989                 break;
 990         default:
 991         case GUARD_INTERVAL_1_32:
 992                 value *= 1;
 993                 break;
 994         }
 995         if (state->cfg.diversity_delay == 0)
 996                 state->div_sync_wait = (value * 3) / 2 + 48;
 997         else
 998                 state->div_sync_wait = (value * 3) / 2 + state->cfg.diversity_delay;
 999
1000         /* deactive the possibility of diversity reception if extended interleaver */
1001         state->div_force_off = !1 && ch->u.ofdm.transmission_mode != TRANSMISSION_MODE_8K;
1002         dib7000p_set_diversity_in(&state->demod, state->div_state);
1003
1004         /* channel estimation fine configuration */
1005         switch (ch->u.ofdm.constellation) {
1006         case QAM_64:
1007                 est[0] = 0x0148;        /* P_adp_regul_cnt 0.04 */
1008                 est[1] = 0xfff0;        /* P_adp_noise_cnt -0.002 */
1009                 est[2] = 0x00a4;        /* P_adp_regul_ext 0.02 */
1010                 est[3] = 0xfff8;        /* P_adp_noise_ext -0.001 */
1011                 break;
1012         case QAM_16:
1013                 est[0] = 0x023d;        /* P_adp_regul_cnt 0.07 */
1014                 est[1] = 0xffdf;        /* P_adp_noise_cnt -0.004 */
1015                 est[2] = 0x00a4;        /* P_adp_regul_ext 0.02 */
1016                 est[3] = 0xfff0;        /* P_adp_noise_ext -0.002 */
1017                 break;
1018         default:
1019                 est[0] = 0x099a;        /* P_adp_regul_cnt 0.3 */
1020                 est[1] = 0xffae;        /* P_adp_noise_cnt -0.01 */
1021                 est[2] = 0x0333;        /* P_adp_regul_ext 0.1 */
1022                 est[3] = 0xfff8;        /* P_adp_noise_ext -0.002 */
1023                 break;
1024         }
1025         for (value = 0; value < 4; value++)
1026                 dib7000p_write_word(state, 187 + value, est[value]);
1027 }
1028
1029 static int dib7000p_autosearch_start(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
1030 {
1031         struct dib7000p_state *state = demod->demodulator_priv;
1032         struct dvb_frontend_parameters schan;
1033         u32 value, factor;
1034         u32 internal = dib7000p_get_internal_freq(state);
1035
1036         schan = *ch;
1037         schan.u.ofdm.constellation = QAM_64;
1038         schan.u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1039         schan.u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1040         schan.u.ofdm.code_rate_HP = FEC_2_3;
1041         schan.u.ofdm.code_rate_LP = FEC_3_4;
1042         schan.u.ofdm.hierarchy_information = 0;
1043
1044         dib7000p_set_channel(state, &schan, 7);
1045
1046         factor = BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth);
1047         if (factor >= 5000)
1048                 factor = 1;
1049         else
1050                 factor = 6;
1051
1052         value = 30 * internal * factor;
1053         dib7000p_write_word(state, 6, (u16) ((value >> 16) & 0xffff));
1054         dib7000p_write_word(state, 7, (u16) (value & 0xffff));
1055         value = 100 * internal * factor;
1056         dib7000p_write_word(state, 8, (u16) ((value >> 16) & 0xffff));
1057         dib7000p_write_word(state, 9, (u16) (value & 0xffff));
1058         value = 500 * internal * factor;
1059         dib7000p_write_word(state, 10, (u16) ((value >> 16) & 0xffff));
1060         dib7000p_write_word(state, 11, (u16) (value & 0xffff));
1061
1062         value = dib7000p_read_word(state, 0);
1063         dib7000p_write_word(state, 0, (u16) ((1 << 9) | value));
1064         dib7000p_read_word(state, 1284);
1065         dib7000p_write_word(state, 0, (u16) value);
1066
1067         return 0;
1068 }
1069
1070 static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod)
1071 {
1072         struct dib7000p_state *state = demod->demodulator_priv;
1073         u16 irq_pending = dib7000p_read_word(state, 1284);
1074
1075         if (irq_pending & 0x1)
1076                 return 1;
1077
1078         if (irq_pending & 0x2)
1079                 return 2;
1080
1081         return 0;
1082 }
1083
1084 static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw)
1085 {
1086         static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 };
1087         static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22,
1088                 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51,
1089                 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80,
1090                 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105,
1091                 107, 108, 109, 111, 112, 114, 115, 117, 118, 119, 121, 122, 123, 125, 126,
1092                 128, 129, 130, 132, 133, 134, 136, 137, 138, 140, 141, 142, 144, 145, 146,
1093                 147, 149, 150, 151, 152, 154, 155, 156, 157, 159, 160, 161, 162, 164, 165,
1094                 166, 167, 168, 170, 171, 172, 173, 174, 175, 177, 178, 179, 180, 181, 182,
1095                 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198,
1096                 199, 200, 201, 202, 203, 204, 205, 206, 207, 207, 208, 209, 210, 211, 212,
1097                 213, 214, 215, 215, 216, 217, 218, 219, 220, 220, 221, 222, 223, 224, 224,
1098                 225, 226, 227, 227, 228, 229, 229, 230, 231, 231, 232, 233, 233, 234, 235,
1099                 235, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243,
1100                 244, 244, 245, 245, 245, 246, 246, 247, 247, 248, 248, 248, 249, 249, 249,
1101                 250, 250, 250, 251, 251, 251, 252, 252, 252, 252, 253, 253, 253, 253, 254,
1102                 254, 254, 254, 254, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
1103                 255, 255, 255, 255, 255, 255
1104         };
1105
1106         u32 xtal = state->cfg.bw->xtal_hz / 1000;
1107         int f_rel = DIV_ROUND_CLOSEST(rf_khz, xtal) * xtal - rf_khz;
1108         int k;
1109         int coef_re[8], coef_im[8];
1110         int bw_khz = bw;
1111         u32 pha;
1112
1113         dprintk("relative position of the Spur: %dk (RF: %dk, XTAL: %dk)", f_rel, rf_khz, xtal);
1114
1115         if (f_rel < -bw_khz / 2 || f_rel > bw_khz / 2)
1116                 return;
1117
1118         bw_khz /= 100;
1119
1120         dib7000p_write_word(state, 142, 0x0610);
1121
1122         for (k = 0; k < 8; k++) {
1123                 pha = ((f_rel * (k + 1) * 112 * 80 / bw_khz) / 1000) & 0x3ff;
1124
1125                 if (pha == 0) {
1126                         coef_re[k] = 256;
1127                         coef_im[k] = 0;
1128                 } else if (pha < 256) {
1129                         coef_re[k] = sine[256 - (pha & 0xff)];
1130                         coef_im[k] = sine[pha & 0xff];
1131                 } else if (pha == 256) {
1132                         coef_re[k] = 0;
1133                         coef_im[k] = 256;
1134                 } else if (pha < 512) {
1135                         coef_re[k] = -sine[pha & 0xff];
1136                         coef_im[k] = sine[256 - (pha & 0xff)];
1137                 } else if (pha == 512) {
1138                         coef_re[k] = -256;
1139                         coef_im[k] = 0;
1140                 } else if (pha < 768) {
1141                         coef_re[k] = -sine[256 - (pha & 0xff)];
1142                         coef_im[k] = -sine[pha & 0xff];
1143                 } else if (pha == 768) {
1144                         coef_re[k] = 0;
1145                         coef_im[k] = -256;
1146                 } else {
1147                         coef_re[k] = sine[pha & 0xff];
1148                         coef_im[k] = -sine[256 - (pha & 0xff)];
1149                 }
1150
1151                 coef_re[k] *= notch[k];
1152                 coef_re[k] += (1 << 14);
1153                 if (coef_re[k] >= (1 << 24))
1154                         coef_re[k] = (1 << 24) - 1;
1155                 coef_re[k] /= (1 << 15);
1156
1157                 coef_im[k] *= notch[k];
1158                 coef_im[k] += (1 << 14);
1159                 if (coef_im[k] >= (1 << 24))
1160                         coef_im[k] = (1 << 24) - 1;
1161                 coef_im[k] /= (1 << 15);
1162
1163                 dprintk("PALF COEF: %d re: %d im: %d", k, coef_re[k], coef_im[k]);
1164
1165                 dib7000p_write_word(state, 143, (0 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
1166                 dib7000p_write_word(state, 144, coef_im[k] & 0x3ff);
1167                 dib7000p_write_word(state, 143, (1 << 14) | (k << 10) | (coef_re[k] & 0x3ff));
1168         }
1169         dib7000p_write_word(state, 143, 0);
1170 }
1171
1172 static int dib7000p_tune(struct dvb_frontend *demod, struct dvb_frontend_parameters *ch)
1173 {
1174         struct dib7000p_state *state = demod->demodulator_priv;
1175         u16 tmp = 0;
1176
1177         if (ch != NULL)
1178                 dib7000p_set_channel(state, ch, 0);
1179         else
1180                 return -EINVAL;
1181
1182         // restart demod
1183         dib7000p_write_word(state, 770, 0x4000);
1184         dib7000p_write_word(state, 770, 0x0000);
1185         msleep(45);
1186
1187         /* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, P_ctrl_alpha_cor4=3 */
1188         tmp = (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x3);
1189         if (state->sfn_workaround_active) {
1190                 dprintk("SFN workaround is active");
1191                 tmp |= (1 << 9);
1192                 dib7000p_write_word(state, 166, 0x4000);
1193         } else {
1194                 dib7000p_write_word(state, 166, 0x0000);
1195         }
1196         dib7000p_write_word(state, 29, tmp);
1197
1198         // never achieved a lock with that bandwidth so far - wait for osc-freq to update
1199         if (state->timf == 0)
1200                 msleep(200);
1201
1202         /* offset loop parameters */
1203
1204         /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */
1205         tmp = (6 << 8) | 0x80;
1206         switch (ch->u.ofdm.transmission_mode) {
1207         case TRANSMISSION_MODE_2K:
1208                 tmp |= (2 << 12);
1209                 break;
1210         case TRANSMISSION_MODE_4K:
1211                 tmp |= (3 << 12);
1212                 break;
1213         default:
1214         case TRANSMISSION_MODE_8K:
1215                 tmp |= (4 << 12);
1216                 break;
1217         }
1218         dib7000p_write_word(state, 26, tmp);    /* timf_a(6xxx) */
1219
1220         /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */
1221         tmp = (0 << 4);
1222         switch (ch->u.ofdm.transmission_mode) {
1223         case TRANSMISSION_MODE_2K:
1224                 tmp |= 0x6;
1225                 break;
1226         case TRANSMISSION_MODE_4K:
1227                 tmp |= 0x7;
1228                 break;
1229         default:
1230         case TRANSMISSION_MODE_8K:
1231                 tmp |= 0x8;
1232                 break;
1233         }
1234         dib7000p_write_word(state, 32, tmp);
1235
1236         /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */
1237         tmp = (0 << 4);
1238         switch (ch->u.ofdm.transmission_mode) {
1239         case TRANSMISSION_MODE_2K:
1240                 tmp |= 0x6;
1241                 break;
1242         case TRANSMISSION_MODE_4K:
1243                 tmp |= 0x7;
1244                 break;
1245         default:
1246         case TRANSMISSION_MODE_8K:
1247                 tmp |= 0x8;
1248                 break;
1249         }
1250         dib7000p_write_word(state, 33, tmp);
1251
1252         tmp = dib7000p_read_word(state, 509);
1253         if (!((tmp >> 6) & 0x1)) {
1254                 /* restart the fec */
1255                 tmp = dib7000p_read_word(state, 771);
1256                 dib7000p_write_word(state, 771, tmp | (1 << 1));
1257                 dib7000p_write_word(state, 771, tmp);
1258                 msleep(40);
1259                 tmp = dib7000p_read_word(state, 509);
1260         }
1261         // we achieved a lock - it's time to update the osc freq
1262         if ((tmp >> 6) & 0x1) {
1263                 dib7000p_update_timf(state);
1264                 /* P_timf_alpha += 2 */
1265                 tmp = dib7000p_read_word(state, 26);
1266                 dib7000p_write_word(state, 26, (tmp & ~(0xf << 12)) | ((((tmp >> 12) & 0xf) + 5) << 12));
1267         }
1268
1269         if (state->cfg.spur_protect)
1270                 dib7000p_spur_protect(state, ch->frequency / 1000, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
1271
1272         dib7000p_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->u.ofdm.bandwidth));
1273         return 0;
1274 }
1275
1276 static int dib7000p_wakeup(struct dvb_frontend *demod)
1277 {
1278         struct dib7000p_state *state = demod->demodulator_priv;
1279         dib7000p_set_power_mode(state, DIB7000P_POWER_ALL);
1280         dib7000p_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1281         if (state->version == SOC7090)
1282                 dib7000p_sad_calib(state);
1283         return 0;
1284 }
1285
1286 static int dib7000p_sleep(struct dvb_frontend *demod)
1287 {
1288         struct dib7000p_state *state = demod->demodulator_priv;
1289         if (state->version == SOC7090)
1290                 return dib7090_set_output_mode(demod, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1291         return dib7000p_set_output_mode(state, OUTMODE_HIGH_Z) | dib7000p_set_power_mode(state, DIB7000P_POWER_INTERFACE_ONLY);
1292 }
1293
1294 static int dib7000p_identify(struct dib7000p_state *st)
1295 {
1296         u16 value;
1297         dprintk("checking demod on I2C address: %d (%x)", st->i2c_addr, st->i2c_addr);
1298
1299         if ((value = dib7000p_read_word(st, 768)) != 0x01b3) {
1300                 dprintk("wrong Vendor ID (read=0x%x)", value);
1301                 return -EREMOTEIO;
1302         }
1303
1304         if ((value = dib7000p_read_word(st, 769)) != 0x4000) {
1305                 dprintk("wrong Device ID (%x)", value);
1306                 return -EREMOTEIO;
1307         }
1308
1309         return 0;
1310 }
1311
1312 static int dib7000p_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1313 {
1314         struct dib7000p_state *state = fe->demodulator_priv;
1315         u16 tps = dib7000p_read_word(state, 463);
1316
1317         fep->inversion = INVERSION_AUTO;
1318
1319         fep->u.ofdm.bandwidth = BANDWIDTH_TO_INDEX(state->current_bandwidth);
1320
1321         switch ((tps >> 8) & 0x3) {
1322         case 0:
1323                 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1324                 break;
1325         case 1:
1326                 fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1327                 break;
1328         /* case 2: fep->u.ofdm.transmission_mode = TRANSMISSION_MODE_4K; break; */
1329         }
1330
1331         switch (tps & 0x3) {
1332         case 0:
1333                 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1334                 break;
1335         case 1:
1336                 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1337                 break;
1338         case 2:
1339                 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1340                 break;
1341         case 3:
1342                 fep->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1343                 break;
1344         }
1345
1346         switch ((tps >> 14) & 0x3) {
1347         case 0:
1348                 fep->u.ofdm.constellation = QPSK;
1349                 break;
1350         case 1:
1351                 fep->u.ofdm.constellation = QAM_16;
1352                 break;
1353         case 2:
1354         default:
1355                 fep->u.ofdm.constellation = QAM_64;
1356                 break;
1357         }
1358
1359         /* as long as the frontend_param structure is fixed for hierarchical transmission I refuse to use it */
1360         /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */
1361
1362         fep->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1363         switch ((tps >> 5) & 0x7) {
1364         case 1:
1365                 fep->u.ofdm.code_rate_HP = FEC_1_2;
1366                 break;
1367         case 2:
1368                 fep->u.ofdm.code_rate_HP = FEC_2_3;
1369                 break;
1370         case 3:
1371                 fep->u.ofdm.code_rate_HP = FEC_3_4;
1372                 break;
1373         case 5:
1374                 fep->u.ofdm.code_rate_HP = FEC_5_6;
1375                 break;
1376         case 7:
1377         default:
1378                 fep->u.ofdm.code_rate_HP = FEC_7_8;
1379                 break;
1380
1381         }
1382
1383         switch ((tps >> 2) & 0x7) {
1384         case 1:
1385                 fep->u.ofdm.code_rate_LP = FEC_1_2;
1386                 break;
1387         case 2:
1388                 fep->u.ofdm.code_rate_LP = FEC_2_3;
1389                 break;
1390         case 3:
1391                 fep->u.ofdm.code_rate_LP = FEC_3_4;
1392                 break;
1393         case 5:
1394                 fep->u.ofdm.code_rate_LP = FEC_5_6;
1395                 break;
1396         case 7:
1397         default:
1398                 fep->u.ofdm.code_rate_LP = FEC_7_8;
1399                 break;
1400         }
1401
1402         /* native interleaver: (dib7000p_read_word(state, 464) >>  5) & 0x1 */
1403
1404         return 0;
1405 }
1406
1407 static int dib7000p_set_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *fep)
1408 {
1409         struct dib7000p_state *state = fe->demodulator_priv;
1410         int time, ret;
1411
1412         if (state->version == SOC7090) {
1413                 dib7090_set_diversity_in(fe, 0);
1414                 dib7090_set_output_mode(fe, OUTMODE_HIGH_Z);
1415         } else
1416                 dib7000p_set_output_mode(state, OUTMODE_HIGH_Z);
1417
1418         /* maybe the parameter has been changed */
1419         state->sfn_workaround_active = buggy_sfn_workaround;
1420
1421         if (fe->ops.tuner_ops.set_params)
1422                 fe->ops.tuner_ops.set_params(fe, fep);
1423
1424         /* start up the AGC */
1425         state->agc_state = 0;
1426         do {
1427                 time = dib7000p_agc_startup(fe, fep);
1428                 if (time != -1)
1429                         msleep(time);
1430         } while (time != -1);
1431
1432         if (fep->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ||
1433                 fep->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO || fep->u.ofdm.constellation == QAM_AUTO || fep->u.ofdm.code_rate_HP == FEC_AUTO) {
1434                 int i = 800, found;
1435
1436                 dib7000p_autosearch_start(fe, fep);
1437                 do {
1438                         msleep(1);
1439                         found = dib7000p_autosearch_is_irq(fe);
1440                 } while (found == 0 && i--);
1441
1442                 dprintk("autosearch returns: %d", found);
1443                 if (found == 0 || found == 1)
1444                         return 0;
1445
1446                 dib7000p_get_frontend(fe, fep);
1447         }
1448
1449         ret = dib7000p_tune(fe, fep);
1450
1451         /* make this a config parameter */
1452         if (state->version == SOC7090)
1453                 dib7090_set_output_mode(fe, state->cfg.output_mode);
1454         else
1455                 dib7000p_set_output_mode(state, state->cfg.output_mode);
1456
1457         return ret;
1458 }
1459
1460 static int dib7000p_read_status(struct dvb_frontend *fe, fe_status_t * stat)
1461 {
1462         struct dib7000p_state *state = fe->demodulator_priv;
1463         u16 lock = dib7000p_read_word(state, 509);
1464
1465         *stat = 0;
1466
1467         if (lock & 0x8000)
1468                 *stat |= FE_HAS_SIGNAL;
1469         if (lock & 0x3000)
1470                 *stat |= FE_HAS_CARRIER;
1471         if (lock & 0x0100)
1472                 *stat |= FE_HAS_VITERBI;
1473         if (lock & 0x0010)
1474                 *stat |= FE_HAS_SYNC;
1475         if ((lock & 0x0038) == 0x38)
1476                 *stat |= FE_HAS_LOCK;
1477
1478         return 0;
1479 }
1480
1481 static int dib7000p_read_ber(struct dvb_frontend *fe, u32 * ber)
1482 {
1483         struct dib7000p_state *state = fe->demodulator_priv;
1484         *ber = (dib7000p_read_word(state, 500) << 16) | dib7000p_read_word(state, 501);
1485         return 0;
1486 }
1487
1488 static int dib7000p_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
1489 {
1490         struct dib7000p_state *state = fe->demodulator_priv;
1491         *unc = dib7000p_read_word(state, 506);
1492         return 0;
1493 }
1494
1495 static int dib7000p_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
1496 {
1497         struct dib7000p_state *state = fe->demodulator_priv;
1498         u16 val = dib7000p_read_word(state, 394);
1499         *strength = 65535 - val;
1500         return 0;
1501 }
1502
1503 static int dib7000p_read_snr(struct dvb_frontend *fe, u16 * snr)
1504 {
1505         struct dib7000p_state *state = fe->demodulator_priv;
1506         u16 val;
1507         s32 signal_mant, signal_exp, noise_mant, noise_exp;
1508         u32 result = 0;
1509
1510         val = dib7000p_read_word(state, 479);
1511         noise_mant = (val >> 4) & 0xff;
1512         noise_exp = ((val & 0xf) << 2);
1513         val = dib7000p_read_word(state, 480);
1514         noise_exp += ((val >> 14) & 0x3);
1515         if ((noise_exp & 0x20) != 0)
1516                 noise_exp -= 0x40;
1517
1518         signal_mant = (val >> 6) & 0xFF;
1519         signal_exp = (val & 0x3F);
1520         if ((signal_exp & 0x20) != 0)
1521                 signal_exp -= 0x40;
1522
1523         if (signal_mant != 0)
1524                 result = intlog10(2) * 10 * signal_exp + 10 * intlog10(signal_mant);
1525         else
1526                 result = intlog10(2) * 10 * signal_exp - 100;
1527
1528         if (noise_mant != 0)
1529                 result -= intlog10(2) * 10 * noise_exp + 10 * intlog10(noise_mant);
1530         else
1531                 result -= intlog10(2) * 10 * noise_exp - 100;
1532
1533         *snr = result / ((1 << 24) / 10);
1534         return 0;
1535 }
1536
1537 static int dib7000p_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
1538 {
1539         tune->min_delay_ms = 1000;
1540         return 0;
1541 }
1542
1543 static void dib7000p_release(struct dvb_frontend *demod)
1544 {
1545         struct dib7000p_state *st = demod->demodulator_priv;
1546         dibx000_exit_i2c_master(&st->i2c_master);
1547         i2c_del_adapter(&st->dib7090_tuner_adap);
1548         kfree(st);
1549 }
1550
1551 int dib7000pc_detection(struct i2c_adapter *i2c_adap)
1552 {
1553         u8 tx[2], rx[2];
1554         struct i2c_msg msg[2] = {
1555                 {.addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2},
1556                 {.addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2},
1557         };
1558
1559         tx[0] = 0x03;
1560         tx[1] = 0x00;
1561
1562         if (i2c_transfer(i2c_adap, msg, 2) == 2)
1563                 if (rx[0] == 0x01 && rx[1] == 0xb3) {
1564                         dprintk("-D-  DiB7000PC detected");
1565                         return 1;
1566                 }
1567
1568         msg[0].addr = msg[1].addr = 0x40;
1569
1570         if (i2c_transfer(i2c_adap, msg, 2) == 2)
1571                 if (rx[0] == 0x01 && rx[1] == 0xb3) {
1572                         dprintk("-D-  DiB7000PC detected");
1573                         return 1;
1574                 }
1575
1576         dprintk("-D-  DiB7000PC not detected");
1577         return 0;
1578 }
1579 EXPORT_SYMBOL(dib7000pc_detection);
1580
1581 struct i2c_adapter *dib7000p_get_i2c_master(struct dvb_frontend *demod, enum dibx000_i2c_interface intf, int gating)
1582 {
1583         struct dib7000p_state *st = demod->demodulator_priv;
1584         return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
1585 }
1586 EXPORT_SYMBOL(dib7000p_get_i2c_master);
1587
1588 int dib7000p_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
1589 {
1590         struct dib7000p_state *state = fe->demodulator_priv;
1591         u16 val = dib7000p_read_word(state, 235) & 0xffef;
1592         val |= (onoff & 0x1) << 4;
1593         dprintk("PID filter enabled %d", onoff);
1594         return dib7000p_write_word(state, 235, val);
1595 }
1596 EXPORT_SYMBOL(dib7000p_pid_filter_ctrl);
1597
1598 int dib7000p_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
1599 {
1600         struct dib7000p_state *state = fe->demodulator_priv;
1601         dprintk("PID filter: index %x, PID %d, OnOff %d", id, pid, onoff);
1602         return dib7000p_write_word(state, 241 + id, onoff ? (1 << 13) | pid : 0);
1603 }
1604 EXPORT_SYMBOL(dib7000p_pid_filter);
1605
1606 int dib7000p_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, struct dib7000p_config cfg[])
1607 {
1608         struct dib7000p_state *dpst;
1609         int k = 0;
1610         u8 new_addr = 0;
1611
1612         dpst = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
1613         if (!dpst)
1614                 return -ENOMEM;
1615
1616         dpst->i2c_adap = i2c;
1617
1618         for (k = no_of_demods - 1; k >= 0; k--) {
1619                 dpst->cfg = cfg[k];
1620
1621                 /* designated i2c address */
1622                 if (cfg[k].default_i2c_addr != 0)
1623                         new_addr = cfg[k].default_i2c_addr + (k << 1);
1624                 else
1625                         new_addr = (0x40 + k) << 1;
1626                 dpst->i2c_addr = new_addr;
1627                 dib7000p_write_word(dpst, 1287, 0x0003);        /* sram lead in, rdy */
1628                 if (dib7000p_identify(dpst) != 0) {
1629                         dpst->i2c_addr = default_addr;
1630                         dib7000p_write_word(dpst, 1287, 0x0003);        /* sram lead in, rdy */
1631                         if (dib7000p_identify(dpst) != 0) {
1632                                 dprintk("DiB7000P #%d: not identified\n", k);
1633                                 kfree(dpst);
1634                                 return -EIO;
1635                         }
1636                 }
1637
1638                 /* start diversity to pull_down div_str - just for i2c-enumeration */
1639                 dib7000p_set_output_mode(dpst, OUTMODE_DIVERSITY);
1640
1641                 /* set new i2c address and force divstart */
1642                 dib7000p_write_word(dpst, 1285, (new_addr << 2) | 0x2);
1643
1644                 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
1645         }
1646
1647         for (k = 0; k < no_of_demods; k++) {
1648                 dpst->cfg = cfg[k];
1649                 if (cfg[k].default_i2c_addr != 0)
1650                         dpst->i2c_addr = (cfg[k].default_i2c_addr + k) << 1;
1651                 else
1652                         dpst->i2c_addr = (0x40 + k) << 1;
1653
1654                 // unforce divstr
1655                 dib7000p_write_word(dpst, 1285, dpst->i2c_addr << 2);
1656
1657                 /* deactivate div - it was just for i2c-enumeration */
1658                 dib7000p_set_output_mode(dpst, OUTMODE_HIGH_Z);
1659         }
1660
1661         kfree(dpst);
1662         return 0;
1663 }
1664 EXPORT_SYMBOL(dib7000p_i2c_enumeration);
1665
1666 static const s32 lut_1000ln_mant[] = {
1667         6908, 6956, 7003, 7047, 7090, 7131, 7170, 7208, 7244, 7279, 7313, 7346, 7377, 7408, 7438, 7467, 7495, 7523, 7549, 7575, 7600
1668 };
1669
1670 static s32 dib7000p_get_adc_power(struct dvb_frontend *fe)
1671 {
1672         struct dib7000p_state *state = fe->demodulator_priv;
1673         u32 tmp_val = 0, exp = 0, mant = 0;
1674         s32 pow_i;
1675         u16 buf[2];
1676         u8 ix = 0;
1677
1678         buf[0] = dib7000p_read_word(state, 0x184);
1679         buf[1] = dib7000p_read_word(state, 0x185);
1680         pow_i = (buf[0] << 16) | buf[1];
1681         dprintk("raw pow_i = %d", pow_i);
1682
1683         tmp_val = pow_i;
1684         while (tmp_val >>= 1)
1685                 exp++;
1686
1687         mant = (pow_i * 1000 / (1 << exp));
1688         dprintk(" mant = %d exp = %d", mant / 1000, exp);
1689
1690         ix = (u8) ((mant - 1000) / 100);        /* index of the LUT */
1691         dprintk(" ix = %d", ix);
1692
1693         pow_i = (lut_1000ln_mant[ix] + 693 * (exp - 20) - 6908);
1694         pow_i = (pow_i << 8) / 1000;
1695         dprintk(" pow_i = %d", pow_i);
1696
1697         return pow_i;
1698 }
1699
1700 static int map_addr_to_serpar_number(struct i2c_msg *msg)
1701 {
1702         if ((msg->buf[0] <= 15))
1703                 msg->buf[0] -= 1;
1704         else if (msg->buf[0] == 17)
1705                 msg->buf[0] = 15;
1706         else if (msg->buf[0] == 16)
1707                 msg->buf[0] = 17;
1708         else if (msg->buf[0] == 19)
1709                 msg->buf[0] = 16;
1710         else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1711                 msg->buf[0] -= 3;
1712         else if (msg->buf[0] == 28)
1713                 msg->buf[0] = 23;
1714         else
1715                 return -EINVAL;
1716         return 0;
1717 }
1718
1719 static int w7090p_tuner_write_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1720 {
1721         struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1722         u8 n_overflow = 1;
1723         u16 i = 1000;
1724         u16 serpar_num = msg[0].buf[0];
1725
1726         while (n_overflow == 1 && i) {
1727                 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
1728                 i--;
1729                 if (i == 0)
1730                         dprintk("Tuner ITF: write busy (overflow)");
1731         }
1732         dib7000p_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1733         dib7000p_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1734
1735         return num;
1736 }
1737
1738 static int w7090p_tuner_read_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1739 {
1740         struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1741         u8 n_overflow = 1, n_empty = 1;
1742         u16 i = 1000;
1743         u16 serpar_num = msg[0].buf[0];
1744         u16 read_word;
1745
1746         while (n_overflow == 1 && i) {
1747                 n_overflow = (dib7000p_read_word(state, 1984) >> 1) & 0x1;
1748                 i--;
1749                 if (i == 0)
1750                         dprintk("TunerITF: read busy (overflow)");
1751         }
1752         dib7000p_write_word(state, 1985, (0 << 6) | (serpar_num & 0x3f));
1753
1754         i = 1000;
1755         while (n_empty == 1 && i) {
1756                 n_empty = dib7000p_read_word(state, 1984) & 0x1;
1757                 i--;
1758                 if (i == 0)
1759                         dprintk("TunerITF: read busy (empty)");
1760         }
1761         read_word = dib7000p_read_word(state, 1987);
1762         msg[1].buf[0] = (read_word >> 8) & 0xff;
1763         msg[1].buf[1] = (read_word) & 0xff;
1764
1765         return num;
1766 }
1767
1768 static int w7090p_tuner_rw_serpar(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1769 {
1770         if (map_addr_to_serpar_number(&msg[0]) == 0) {  /* else = Tuner regs to ignore : DIG_CFG, CTRL_RF_LT, PLL_CFG, PWM1_REG, ADCCLK, DIG_CFG_3; SLEEP_EN... */
1771                 if (num == 1) { /* write */
1772                         return w7090p_tuner_write_serpar(i2c_adap, msg, 1);
1773                 } else {        /* read */
1774                         return w7090p_tuner_read_serpar(i2c_adap, msg, 2);
1775                 }
1776         }
1777         return num;
1778 }
1779
1780 int dib7090p_rw_on_apb(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num, u16 apb_address)
1781 {
1782         struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1783         u16 word;
1784
1785         if (num == 1) {         /* write */
1786                 dib7000p_write_word(state, apb_address, ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
1787         } else {
1788                 word = dib7000p_read_word(state, apb_address);
1789                 msg[1].buf[0] = (word >> 8) & 0xff;
1790                 msg[1].buf[1] = (word) & 0xff;
1791         }
1792
1793         return num;
1794 }
1795
1796 static int dib7090_tuner_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg msg[], int num)
1797 {
1798         struct dib7000p_state *state = i2c_get_adapdata(i2c_adap);
1799
1800         u16 apb_address = 0, word;
1801         int i = 0;
1802         switch (msg[0].buf[0]) {
1803         case 0x12:
1804                 apb_address = 1920;
1805                 break;
1806         case 0x14:
1807                 apb_address = 1921;
1808                 break;
1809         case 0x24:
1810                 apb_address = 1922;
1811                 break;
1812         case 0x1a:
1813                 apb_address = 1923;
1814                 break;
1815         case 0x22:
1816                 apb_address = 1924;
1817                 break;
1818         case 0x33:
1819                 apb_address = 1926;
1820                 break;
1821         case 0x34:
1822                 apb_address = 1927;
1823                 break;
1824         case 0x35:
1825                 apb_address = 1928;
1826                 break;
1827         case 0x36:
1828                 apb_address = 1929;
1829                 break;
1830         case 0x37:
1831                 apb_address = 1930;
1832                 break;
1833         case 0x38:
1834                 apb_address = 1931;
1835                 break;
1836         case 0x39:
1837                 apb_address = 1932;
1838                 break;
1839         case 0x2a:
1840                 apb_address = 1935;
1841                 break;
1842         case 0x2b:
1843                 apb_address = 1936;
1844                 break;
1845         case 0x2c:
1846                 apb_address = 1937;
1847                 break;
1848         case 0x2d:
1849                 apb_address = 1938;
1850                 break;
1851         case 0x2e:
1852                 apb_address = 1939;
1853                 break;
1854         case 0x2f:
1855                 apb_address = 1940;
1856                 break;
1857         case 0x30:
1858                 apb_address = 1941;
1859                 break;
1860         case 0x31:
1861                 apb_address = 1942;
1862                 break;
1863         case 0x32:
1864                 apb_address = 1943;
1865                 break;
1866         case 0x3e:
1867                 apb_address = 1944;
1868                 break;
1869         case 0x3f:
1870                 apb_address = 1945;
1871                 break;
1872         case 0x40:
1873                 apb_address = 1948;
1874                 break;
1875         case 0x25:
1876                 apb_address = 914;
1877                 break;
1878         case 0x26:
1879                 apb_address = 915;
1880                 break;
1881         case 0x27:
1882                 apb_address = 916;
1883                 break;
1884         case 0x28:
1885                 apb_address = 917;
1886                 break;
1887         case 0x1d:
1888                 i = ((dib7000p_read_word(state, 72) >> 12) & 0x3);
1889                 word = dib7000p_read_word(state, 384 + i);
1890                 msg[1].buf[0] = (word >> 8) & 0xff;
1891                 msg[1].buf[1] = (word) & 0xff;
1892                 return num;
1893         case 0x1f:
1894                 if (num == 1) { /* write */
1895                         word = (u16) ((msg[0].buf[1] << 8) | msg[0].buf[2]);
1896                         word &= 0x3;
1897                         word = (dib7000p_read_word(state, 72) & ~(3 << 12)) | (word << 12);
1898                         dib7000p_write_word(state, 72, word);   /* Set the proper input */
1899                         return num;
1900                 }
1901         }
1902
1903         if (apb_address != 0)   /* R/W acces via APB */
1904                 return dib7090p_rw_on_apb(i2c_adap, msg, num, apb_address);
1905         else                    /* R/W access via SERPAR  */
1906                 return w7090p_tuner_rw_serpar(i2c_adap, msg, num);
1907
1908         return 0;
1909 }
1910
1911 static u32 dib7000p_i2c_func(struct i2c_adapter *adapter)
1912 {
1913         return I2C_FUNC_I2C;
1914 }
1915
1916 static struct i2c_algorithm dib7090_tuner_xfer_algo = {
1917         .master_xfer = dib7090_tuner_xfer,
1918         .functionality = dib7000p_i2c_func,
1919 };
1920
1921 struct i2c_adapter *dib7090_get_i2c_tuner(struct dvb_frontend *fe)
1922 {
1923         struct dib7000p_state *st = fe->demodulator_priv;
1924         return &st->dib7090_tuner_adap;
1925 }
1926 EXPORT_SYMBOL(dib7090_get_i2c_tuner);
1927
1928 static int dib7090_host_bus_drive(struct dib7000p_state *state, u8 drive)
1929 {
1930         u16 reg;
1931
1932         /* drive host bus 2, 3, 4 */
1933         reg = dib7000p_read_word(state, 1798) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
1934         reg |= (drive << 12) | (drive << 6) | drive;
1935         dib7000p_write_word(state, 1798, reg);
1936
1937         /* drive host bus 5,6 */
1938         reg = dib7000p_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
1939         reg |= (drive << 8) | (drive << 2);
1940         dib7000p_write_word(state, 1799, reg);
1941
1942         /* drive host bus 7, 8, 9 */
1943         reg = dib7000p_read_word(state, 1800) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
1944         reg |= (drive << 12) | (drive << 6) | drive;
1945         dib7000p_write_word(state, 1800, reg);
1946
1947         /* drive host bus 10, 11 */
1948         reg = dib7000p_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
1949         reg |= (drive << 8) | (drive << 2);
1950         dib7000p_write_word(state, 1801, reg);
1951
1952         /* drive host bus 12, 13, 14 */
1953         reg = dib7000p_read_word(state, 1802) & ~((0x7) | (0x7 << 6) | (0x7 << 12));
1954         reg |= (drive << 12) | (drive << 6) | drive;
1955         dib7000p_write_word(state, 1802, reg);
1956
1957         return 0;
1958 }
1959
1960 static u32 dib7090_calcSyncFreq(u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 syncSize)
1961 {
1962         u32 quantif = 3;
1963         u32 nom = (insertExtSynchro * P_Kin + syncSize);
1964         u32 denom = P_Kout;
1965         u32 syncFreq = ((nom << quantif) / denom);
1966
1967         if ((syncFreq & ((1 << quantif) - 1)) != 0)
1968                 syncFreq = (syncFreq >> quantif) + 1;
1969         else
1970                 syncFreq = (syncFreq >> quantif);
1971
1972         if (syncFreq != 0)
1973                 syncFreq = syncFreq - 1;
1974
1975         return syncFreq;
1976 }
1977
1978 static int dib7090_cfg_DibTx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 insertExtSynchro, u32 synchroMode, u32 syncWord, u32 syncSize)
1979 {
1980         u8 index_buf;
1981         u16 rx_copy_buf[22];
1982
1983         dprintk("Configure DibStream Tx");
1984         for (index_buf = 0; index_buf < 22; index_buf++)
1985                 rx_copy_buf[index_buf] = dib7000p_read_word(state, 1536+index_buf);
1986
1987         dib7000p_write_word(state, 1615, 1);
1988         dib7000p_write_word(state, 1603, P_Kin);
1989         dib7000p_write_word(state, 1605, P_Kout);
1990         dib7000p_write_word(state, 1606, insertExtSynchro);
1991         dib7000p_write_word(state, 1608, synchroMode);
1992         dib7000p_write_word(state, 1609, (syncWord >> 16) & 0xffff);
1993         dib7000p_write_word(state, 1610, syncWord & 0xffff);
1994         dib7000p_write_word(state, 1612, syncSize);
1995         dib7000p_write_word(state, 1615, 0);
1996
1997         for (index_buf = 0; index_buf < 22; index_buf++)
1998                 dib7000p_write_word(state, 1536+index_buf, rx_copy_buf[index_buf]);
1999
2000         return 0;
2001 }
2002
2003 static int dib7090_cfg_DibRx(struct dib7000p_state *state, u32 P_Kin, u32 P_Kout, u32 synchroMode, u32 insertExtSynchro, u32 syncWord, u32 syncSize,
2004                 u32 dataOutRate)
2005 {
2006         u32 syncFreq;
2007
2008         dprintk("Configure DibStream Rx");
2009         if ((P_Kin != 0) && (P_Kout != 0)) {
2010                 syncFreq = dib7090_calcSyncFreq(P_Kin, P_Kout, insertExtSynchro, syncSize);
2011                 dib7000p_write_word(state, 1542, syncFreq);
2012         }
2013         dib7000p_write_word(state, 1554, 1);
2014         dib7000p_write_word(state, 1536, P_Kin);
2015         dib7000p_write_word(state, 1537, P_Kout);
2016         dib7000p_write_word(state, 1539, synchroMode);
2017         dib7000p_write_word(state, 1540, (syncWord >> 16) & 0xffff);
2018         dib7000p_write_word(state, 1541, syncWord & 0xffff);
2019         dib7000p_write_word(state, 1543, syncSize);
2020         dib7000p_write_word(state, 1544, dataOutRate);
2021         dib7000p_write_word(state, 1554, 0);
2022
2023         return 0;
2024 }
2025
2026 static int dib7090_enDivOnHostBus(struct dib7000p_state *state)
2027 {
2028         u16 reg;
2029
2030         dprintk("Enable Diversity on host bus");
2031         reg = (1 << 8) | (1 << 5);
2032         dib7000p_write_word(state, 1288, reg);
2033
2034         return dib7090_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
2035 }
2036
2037 static int dib7090_enAdcOnHostBus(struct dib7000p_state *state)
2038 {
2039         u16 reg;
2040
2041         dprintk("Enable ADC on host bus");
2042         reg = (1 << 7) | (1 << 5);
2043         dib7000p_write_word(state, 1288, reg);
2044
2045         return dib7090_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
2046 }
2047
2048 static int dib7090_enMpegOnHostBus(struct dib7000p_state *state)
2049 {
2050         u16 reg;
2051
2052         dprintk("Enable Mpeg on host bus");
2053         reg = (1 << 9) | (1 << 5);
2054         dib7000p_write_word(state, 1288, reg);
2055
2056         return dib7090_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
2057 }
2058
2059 static int dib7090_enMpegInput(struct dib7000p_state *state)
2060 {
2061         dprintk("Enable Mpeg input");
2062         return dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);   /*outputRate = 8 */
2063 }
2064
2065 static int dib7090_enMpegMux(struct dib7000p_state *state, u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
2066 {
2067         u16 reg = (1 << 7) | ((pulseWidth & 0x1f) << 2) | ((enSerialMode & 0x1) << 1) | (enSerialClkDiv2 & 0x1);
2068
2069         dprintk("Enable Mpeg mux");
2070         dib7000p_write_word(state, 1287, reg);
2071
2072         reg &= ~(1 << 7);
2073         dib7000p_write_word(state, 1287, reg);
2074
2075         reg = (1 << 4);
2076         dib7000p_write_word(state, 1288, reg);
2077
2078         return 0;
2079 }
2080
2081 static int dib7090_disableMpegMux(struct dib7000p_state *state)
2082 {
2083         u16 reg;
2084
2085         dprintk("Disable Mpeg mux");
2086         dib7000p_write_word(state, 1288, 0);
2087
2088         reg = dib7000p_read_word(state, 1287);
2089         reg &= ~(1 << 7);
2090         dib7000p_write_word(state, 1287, reg);
2091
2092         return 0;
2093 }
2094
2095 static int dib7090_set_input_mode(struct dvb_frontend *fe, int mode)
2096 {
2097         struct dib7000p_state *state = fe->demodulator_priv;
2098
2099         switch (mode) {
2100         case INPUT_MODE_DIVERSITY:
2101                         dprintk("Enable diversity INPUT");
2102                         dib7090_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
2103                         break;
2104         case INPUT_MODE_MPEG:
2105                         dprintk("Enable Mpeg INPUT");
2106                         dib7090_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); /*outputRate = 8 */
2107                         break;
2108         case INPUT_MODE_OFF:
2109         default:
2110                         dprintk("Disable INPUT");
2111                         dib7090_cfg_DibRx(state, 0, 0, 0, 0, 0, 0, 0);
2112                         break;
2113         }
2114         return 0;
2115 }
2116
2117 static int dib7090_set_diversity_in(struct dvb_frontend *fe, int onoff)
2118 {
2119         switch (onoff) {
2120         case 0:         /* only use the internal way - not the diversity input */
2121                 dib7090_set_input_mode(fe, INPUT_MODE_MPEG);
2122                 break;
2123         case 1:         /* both ways */
2124         case 2:         /* only the diversity input */
2125                 dib7090_set_input_mode(fe, INPUT_MODE_DIVERSITY);
2126                 break;
2127         }
2128
2129         return 0;
2130 }
2131
2132 static int dib7090_set_output_mode(struct dvb_frontend *fe, int mode)
2133 {
2134         struct dib7000p_state *state = fe->demodulator_priv;
2135
2136         u16 outreg, smo_mode, fifo_threshold;
2137         u8 prefer_mpeg_mux_use = 1;
2138         int ret = 0;
2139
2140         dib7090_host_bus_drive(state, 1);
2141
2142         fifo_threshold = 1792;
2143         smo_mode = (dib7000p_read_word(state, 235) & 0x0050) | (1 << 1);
2144         outreg = dib7000p_read_word(state, 1286) & ~((1 << 10) | (0x7 << 6) | (1 << 1));
2145
2146         switch (mode) {
2147         case OUTMODE_HIGH_Z:
2148                 outreg = 0;
2149                 break;
2150
2151         case OUTMODE_MPEG2_SERIAL:
2152                 if (prefer_mpeg_mux_use) {
2153                         dprintk("Sip 7090P setting output mode TS_SERIAL using Mpeg Mux");
2154                         dib7090_enMpegOnHostBus(state);
2155                         dib7090_enMpegInput(state);
2156                         if (state->cfg.enMpegOutput == 1)
2157                                 dib7090_enMpegMux(state, 3, 1, 1);
2158
2159                 } else {        /* Use Smooth block */
2160                         dprintk("Sip 7090P setting output mode TS_SERIAL using Smooth bloc");
2161                         dib7090_disableMpegMux(state);
2162                         dib7000p_write_word(state, 1288, (1 << 6));
2163                         outreg |= (2 << 6) | (0 << 1);
2164                 }
2165                 break;
2166
2167         case OUTMODE_MPEG2_PAR_GATED_CLK:
2168                 if (prefer_mpeg_mux_use) {
2169                         dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
2170                         dib7090_enMpegOnHostBus(state);
2171                         dib7090_enMpegInput(state);
2172                         if (state->cfg.enMpegOutput == 1)
2173                                 dib7090_enMpegMux(state, 2, 0, 0);
2174                 } else {        /* Use Smooth block */
2175                         dprintk("Sip 7090P setting output mode TS_PARALLEL_GATED using Smooth block");
2176                         dib7090_disableMpegMux(state);
2177                         dib7000p_write_word(state, 1288, (1 << 6));
2178                         outreg |= (0 << 6);
2179                 }
2180                 break;
2181
2182         case OUTMODE_MPEG2_PAR_CONT_CLK:        /* Using Smooth block only */
2183                 dprintk("Sip 7090P setting output mode TS_PARALLEL_CONT using Smooth block");
2184                 dib7090_disableMpegMux(state);
2185                 dib7000p_write_word(state, 1288, (1 << 6));
2186                 outreg |= (1 << 6);
2187                 break;
2188
2189         case OUTMODE_MPEG2_FIFO:        /* Using Smooth block because not supported by new Mpeg Mux bloc */
2190                 dprintk("Sip 7090P setting output mode TS_FIFO using Smooth block");
2191                 dib7090_disableMpegMux(state);
2192                 dib7000p_write_word(state, 1288, (1 << 6));
2193                 outreg |= (5 << 6);
2194                 smo_mode |= (3 << 1);
2195                 fifo_threshold = 512;
2196                 break;
2197
2198         case OUTMODE_DIVERSITY:
2199                 dprintk("Sip 7090P setting output mode MODE_DIVERSITY");
2200                 dib7090_disableMpegMux(state);
2201                 dib7090_enDivOnHostBus(state);
2202                 break;
2203
2204         case OUTMODE_ANALOG_ADC:
2205                 dprintk("Sip 7090P setting output mode MODE_ANALOG_ADC");
2206                 dib7090_enAdcOnHostBus(state);
2207                 break;
2208         }
2209
2210         if (state->cfg.output_mpeg2_in_188_bytes)
2211                 smo_mode |= (1 << 5);
2212
2213         ret |= dib7000p_write_word(state, 235, smo_mode);
2214         ret |= dib7000p_write_word(state, 236, fifo_threshold); /* synchronous fread */
2215         ret |= dib7000p_write_word(state, 1286, outreg | (1 << 10));    /* allways set Dout active = 1 !!! */
2216
2217         return ret;
2218 }
2219
2220 int dib7090_tuner_sleep(struct dvb_frontend *fe, int onoff)
2221 {
2222         struct dib7000p_state *state = fe->demodulator_priv;
2223         u16 en_cur_state;
2224
2225         dprintk("sleep dib7090: %d", onoff);
2226
2227         en_cur_state = dib7000p_read_word(state, 1922);
2228
2229         if (en_cur_state > 0xff)
2230                 state->tuner_enable = en_cur_state;
2231
2232         if (onoff)
2233                 en_cur_state &= 0x00ff;
2234         else {
2235                 if (state->tuner_enable != 0)
2236                         en_cur_state = state->tuner_enable;
2237         }
2238
2239         dib7000p_write_word(state, 1922, en_cur_state);
2240
2241         return 0;
2242 }
2243 EXPORT_SYMBOL(dib7090_tuner_sleep);
2244
2245 int dib7090_agc_restart(struct dvb_frontend *fe, u8 restart)
2246 {
2247         dprintk("AGC restart callback: %d", restart);
2248         return 0;
2249 }
2250 EXPORT_SYMBOL(dib7090_agc_restart);
2251
2252 int dib7090_get_adc_power(struct dvb_frontend *fe)
2253 {
2254         return dib7000p_get_adc_power(fe);
2255 }
2256 EXPORT_SYMBOL(dib7090_get_adc_power);
2257
2258 int dib7090_slave_reset(struct dvb_frontend *fe)
2259 {
2260         struct dib7000p_state *state = fe->demodulator_priv;
2261         u16 reg;
2262
2263         reg = dib7000p_read_word(state, 1794);
2264         dib7000p_write_word(state, 1794, reg | (4 << 12));
2265
2266         dib7000p_write_word(state, 1032, 0xffff);
2267         return 0;
2268 }
2269 EXPORT_SYMBOL(dib7090_slave_reset);
2270
2271 static struct dvb_frontend_ops dib7000p_ops;
2272 struct dvb_frontend *dib7000p_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib7000p_config *cfg)
2273 {
2274         struct dvb_frontend *demod;
2275         struct dib7000p_state *st;
2276         st = kzalloc(sizeof(struct dib7000p_state), GFP_KERNEL);
2277         if (st == NULL)
2278                 return NULL;
2279
2280         memcpy(&st->cfg, cfg, sizeof(struct dib7000p_config));
2281         st->i2c_adap = i2c_adap;
2282         st->i2c_addr = i2c_addr;
2283         st->gpio_val = cfg->gpio_val;
2284         st->gpio_dir = cfg->gpio_dir;
2285
2286         /* Ensure the output mode remains at the previous default if it's
2287          * not specifically set by the caller.
2288          */
2289         if ((st->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
2290                 st->cfg.output_mode = OUTMODE_MPEG2_FIFO;
2291
2292         demod = &st->demod;
2293         demod->demodulator_priv = st;
2294         memcpy(&st->demod.ops, &dib7000p_ops, sizeof(struct dvb_frontend_ops));
2295
2296         dib7000p_write_word(st, 1287, 0x0003);  /* sram lead in, rdy */
2297
2298         if (dib7000p_identify(st) != 0)
2299                 goto error;
2300
2301         st->version = dib7000p_read_word(st, 897);
2302
2303         /* FIXME: make sure the dev.parent field is initialized, or else
2304                 request_firmware() will hit an OOPS (this should be moved somewhere
2305                 more common) */
2306
2307         dibx000_init_i2c_master(&st->i2c_master, DIB7000P, st->i2c_adap, st->i2c_addr);
2308
2309         /* init 7090 tuner adapter */
2310         strncpy(st->dib7090_tuner_adap.name, "DiB7090 tuner interface", sizeof(st->dib7090_tuner_adap.name));
2311         st->dib7090_tuner_adap.algo = &dib7090_tuner_xfer_algo;
2312         st->dib7090_tuner_adap.algo_data = NULL;
2313         st->dib7090_tuner_adap.dev.parent = st->i2c_adap->dev.parent;
2314         i2c_set_adapdata(&st->dib7090_tuner_adap, st);
2315         i2c_add_adapter(&st->dib7090_tuner_adap);
2316
2317         dib7000p_demod_reset(st);
2318
2319         if (st->version == SOC7090) {
2320                 dib7090_set_output_mode(demod, st->cfg.output_mode);
2321                 dib7090_set_diversity_in(demod, 0);
2322         }
2323
2324         return demod;
2325
2326 error:
2327         kfree(st);
2328         return NULL;
2329 }
2330 EXPORT_SYMBOL(dib7000p_attach);
2331
2332 static struct dvb_frontend_ops dib7000p_ops = {
2333         .info = {
2334                  .name = "DiBcom 7000PC",
2335                  .type = FE_OFDM,
2336                  .frequency_min = 44250000,
2337                  .frequency_max = 867250000,
2338                  .frequency_stepsize = 62500,
2339                  .caps = FE_CAN_INVERSION_AUTO |
2340                  FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
2341                  FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
2342                  FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
2343                  FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
2344                  },
2345
2346         .release = dib7000p_release,
2347
2348         .init = dib7000p_wakeup,
2349         .sleep = dib7000p_sleep,
2350
2351         .set_frontend = dib7000p_set_frontend,
2352         .get_tune_settings = dib7000p_fe_get_tune_settings,
2353         .get_frontend = dib7000p_get_frontend,
2354
2355         .read_status = dib7000p_read_status,
2356         .read_ber = dib7000p_read_ber,
2357         .read_signal_strength = dib7000p_read_signal_strength,
2358         .read_snr = dib7000p_read_snr,
2359         .read_ucblocks = dib7000p_read_unc_blocks,
2360 };
2361
2362 MODULE_AUTHOR("Olivier Grenie <ogrenie@dibcom.fr>");
2363 MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
2364 MODULE_DESCRIPTION("Driver for the DiBcom 7000PC COFDM demodulator");
2365 MODULE_LICENSE("GPL");