drivers/media/common/saa7146_hlp.c

   1 #include <linux/kernel.h>
   2 #include <media/saa7146_vv.h>
   3
   4 static void calculate_output_format_register(struct saa7146_dev* saa, u32 palette, u32* clip_format)
   5 {
   6         /* clear out the necessary bits */
   7         *clip_format &= 0x0000ffff;
   8         /* set these bits new */
   9         *clip_format |=  (( ((palette&0xf00)>>8) << 30) | ((palette&0x00f) << 24) | (((palette&0x0f0)>>4) << 16));
  10 }
  11
  12 static void calculate_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync, u32* hps_ctrl)
  13 {
  14         *hps_ctrl &= ~(MASK_30 | MASK_31 | MASK_28);
  15         *hps_ctrl |= (source << 30) | (sync << 28);
  16 }
  17
  18 static void calculate_hxo_and_hyo(struct saa7146_vv *vv, u32* hps_h_scale, u32* hps_ctrl)
  19 {
  20         int hyo = 0, hxo = 0;
  21
  22         hyo = vv->standard->v_offset;
  23         hxo = vv->standard->h_offset;
  24
  25         *hps_h_scale    &= ~(MASK_B0 | 0xf00);
  26         *hps_h_scale    |= (hxo <<  0);
  27
  28         *hps_ctrl       &= ~(MASK_W0 | MASK_B2);
  29         *hps_ctrl       |= (hyo << 12);
  30 }
  31
  32 /* helper functions for the calculation of the horizontal- and vertical
  33    scaling registers, clip-format-register etc ...
  34    these functions take pointers to the (most-likely read-out
  35    original-values) and manipulate them according to the requested
  36    changes.
  37 */
  38
  39 /* hps_coeff used for CXY and CXUV; scale 1/1 -> scale 1/64 */
  40 static struct {
  41         u16 hps_coeff;
  42         u16 weight_sum;
  43 } hps_h_coeff_tab [] = {
  44         {0x00,   2}, {0x02,   4}, {0x00,   4}, {0x06,   8}, {0x02,   8},
  45         {0x08,   8}, {0x00,   8}, {0x1E,  16}, {0x0E,   8}, {0x26,   8},
  46         {0x06,   8}, {0x42,   8}, {0x02,   8}, {0x80,   8}, {0x00,   8},
  47         {0xFE,  16}, {0xFE,   8}, {0x7E,   8}, {0x7E,   8}, {0x3E,   8},
  48         {0x3E,   8}, {0x1E,   8}, {0x1E,   8}, {0x0E,   8}, {0x0E,   8},
  49         {0x06,   8}, {0x06,   8}, {0x02,   8}, {0x02,   8}, {0x00,   8},
  50         {0x00,   8}, {0xFE,  16}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
  51         {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
  52         {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
  53         {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0x7E,   8},
  54         {0x7E,   8}, {0x3E,   8}, {0x3E,   8}, {0x1E,   8}, {0x1E,   8},
  55         {0x0E,   8}, {0x0E,   8}, {0x06,   8}, {0x06,   8}, {0x02,   8},
  56         {0x02,   8}, {0x00,   8}, {0x00,   8}, {0xFE,  16}
  57 };
  58
  59 /* table of attenuation values for horizontal scaling */
  60 static u8 h_attenuation[] = { 1, 2, 4, 8, 2, 4, 8, 16, 0};
  61
  62 /* calculate horizontal scale registers */
  63 static int calculate_h_scale_registers(struct saa7146_dev *dev,
  64         int in_x, int out_x, int flip_lr,
  65         u32* hps_ctrl, u32* hps_v_gain, u32* hps_h_prescale, u32* hps_h_scale)
  66 {
  67         /* horizontal prescaler */
  68         u32 dcgx = 0, xpsc = 0, xacm = 0, cxy = 0, cxuv = 0;
  69         /* horizontal scaler */
  70         u32 xim = 0, xp = 0, xsci =0;
  71         /* vertical scale & gain */
  72         u32 pfuv = 0;
  73
  74         /* helper variables */
  75         u32 h_atten = 0, i = 0;
  76
  77         if ( 0 == out_x ) {
  78                 return -EINVAL;
  79         }
  80
  81         /* mask out vanity-bit */
  82         *hps_ctrl &= ~MASK_29;
  83
  84         /* calculate prescale-(xspc)-value:     [n   .. 1/2) : 1
  85                                                 [1/2 .. 1/3) : 2
  86                                                 [1/3 .. 1/4) : 3
  87                                                 ...             */
  88         if (in_x > out_x) {
  89                 xpsc = in_x / out_x;
  90         }
  91         else {
  92                 /* zooming */
  93                 xpsc = 1;
  94         }
  95
  96         /* if flip_lr-bit is set, number of pixels after
  97            horizontal prescaling must be < 384 */
  98         if ( 0 != flip_lr ) {
  99
 100                 /* set vanity bit */
 101                 *hps_ctrl |= MASK_29;
 102
 103                 while (in_x / xpsc >= 384 )
 104                         xpsc++;
 105         }
 106         /* if zooming is wanted, number of pixels after
 107            horizontal prescaling must be < 768 */
 108         else {
 109                 while ( in_x / xpsc >= 768 )
 110                         xpsc++;
 111         }
 112
 113         /* maximum prescale is 64 (p.69) */
 114         if ( xpsc > 64 )
 115                 xpsc = 64;
 116
 117         /* keep xacm clear*/
 118         xacm = 0;
 119
 120         /* set horizontal filter parameters (CXY = CXUV) */
 121         cxy = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].hps_coeff;
 122         cxuv = cxy;
 123
 124         /* calculate and set horizontal fine scale (xsci) */
 125
 126         /* bypass the horizontal scaler ? */
 127         if ( (in_x == out_x) && ( 1 == xpsc ) )
 128                 xsci = 0x400;
 129         else
 130                 xsci = ( (1024 * in_x) / (out_x * xpsc) ) + xpsc;
 131
 132         /* set start phase for horizontal fine scale (xp) to 0 */
 133         xp = 0;
 134
 135         /* set xim, if we bypass the horizontal scaler */
 136         if ( 0x400 == xsci )
 137                 xim = 1;
 138         else
 139                 xim = 0;
 140
 141         /* if the prescaler is bypassed, enable horizontal
 142            accumulation mode (xacm) and clear dcgx */
 143         if( 1 == xpsc ) {
 144                 xacm = 1;
 145                 dcgx = 0;
 146         } else {
 147                 xacm = 0;
 148                 /* get best match in the table of attenuations
 149                    for horizontal scaling */
 150                 h_atten = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].weight_sum;
 151
 152                 for (i = 0; h_attenuation[i] != 0; i++) {
 153                         if (h_attenuation[i] >= h_atten)
 154                                 break;
 155                 }
 156
 157                 dcgx = i;
 158         }
 159
 160         /* the horizontal scaling increment controls the UV filter
 161            to reduce the bandwith to improve the display quality,
 162            so set it ... */
 163         if ( xsci == 0x400)
 164                 pfuv = 0x00;
 165         else if ( xsci < 0x600)
 166                 pfuv = 0x01;
 167         else if ( xsci < 0x680)
 168                 pfuv = 0x11;
 169         else if ( xsci < 0x700)
 170                 pfuv = 0x22;
 171         else
 172                 pfuv = 0x33;
 173
 174
 175         *hps_v_gain  &= MASK_W0|MASK_B2;
 176         *hps_v_gain  |= (pfuv << 24);
 177
 178         *hps_h_scale    &= ~(MASK_W1 | 0xf000);
 179         *hps_h_scale    |= (xim << 31) | (xp << 24) | (xsci << 12);
 180
 181         *hps_h_prescale |= (dcgx << 27) | ((xpsc-1) << 18) | (xacm << 17) | (cxy << 8) | (cxuv << 0);
 182
 183         return 0;
 184 }
 185
 186 static struct {
 187         u16 hps_coeff;
 188         u16 weight_sum;
 189 } hps_v_coeff_tab [] = {
 190  {0x0100,   2},  {0x0102,   4},  {0x0300,   4},  {0x0106,   8},  {0x0502,   8},
 191  {0x0708,   8},  {0x0F00,   8},  {0x011E,  16},  {0x110E,  16},  {0x1926,  16},
 192  {0x3906,  16},  {0x3D42,  16},  {0x7D02,  16},  {0x7F80,  16},  {0xFF00,  16},
 193  {0x01FE,  32},  {0x01FE,  32},  {0x817E,  32},  {0x817E,  32},  {0xC13E,  32},
 194  {0xC13E,  32},  {0xE11E,  32},  {0xE11E,  32},  {0xF10E,  32},  {0xF10E,  32},
 195  {0xF906,  32},  {0xF906,  32},  {0xFD02,  32},  {0xFD02,  32},  {0xFF00,  32},
 196  {0xFF00,  32},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
 197  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
 198  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
 199  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x817E,  64},
 200  {0x817E,  64},  {0xC13E,  64},  {0xC13E,  64},  {0xE11E,  64},  {0xE11E,  64},
 201  {0xF10E,  64},  {0xF10E,  64},  {0xF906,  64},  {0xF906,  64},  {0xFD02,  64},
 202  {0xFD02,  64},  {0xFF00,  64},  {0xFF00,  64},  {0x01FE, 128}
 203 };
 204
 205 /* table of attenuation values for vertical scaling */
 206 static u16 v_attenuation[] = { 2, 4, 8, 16, 32, 64, 128, 256, 0};
 207
 208 /* calculate vertical scale registers */
 209 static int calculate_v_scale_registers(struct saa7146_dev *dev, enum v4l2_field field,
 210         int in_y, int out_y, u32* hps_v_scale, u32* hps_v_gain)
 211 {
 212         int lpi = 0;
 213
 214         /* vertical scaling */
 215         u32 yacm = 0, ysci = 0, yacl = 0, ypo = 0, ype = 0;
 216         /* vertical scale & gain */
 217         u32 dcgy = 0, cya_cyb = 0;
 218
 219         /* helper variables */
 220         u32 v_atten = 0, i = 0;
 221
 222         /* error, if vertical zooming */
 223         if ( in_y < out_y ) {
 224                 return -EINVAL;
 225         }
 226
 227         /* linear phase interpolation may be used
 228            if scaling is between 1 and 1/2 (both fields used)
 229            or scaling is between 1/2 and 1/4 (if only one field is used) */
 230
 231         if (V4L2_FIELD_HAS_BOTH(field)) {
 232                 if( 2*out_y >= in_y) {
 233                         lpi = 1;
 234                 }
 235         } else if (field == V4L2_FIELD_TOP
 236                 || field == V4L2_FIELD_ALTERNATE
 237                 || field == V4L2_FIELD_BOTTOM) {
 238                 if( 4*out_y >= in_y ) {
 239                         lpi = 1;
 240                 }
 241                 out_y *= 2;
 242         }
 243         if( 0 != lpi ) {
 244
 245                 yacm = 0;
 246                 yacl = 0;
 247                 cya_cyb = 0x00ff;
 248
 249                 /* calculate scaling increment */
 250                 if ( in_y > out_y )
 251                         ysci = ((1024 * in_y) / (out_y + 1)) - 1024;
 252                 else
 253                         ysci = 0;
 254
 255                 dcgy = 0;
 256
 257                 /* calculate ype and ypo */
 258                 ype = ysci / 16;
 259                 ypo = ype + (ysci / 64);
 260
 261         } else {
 262                 yacm = 1;
 263
 264                 /* calculate scaling increment */
 265                 ysci = (((10 * 1024 * (in_y - out_y - 1)) / in_y) + 9) / 10;
 266
 267                 /* calculate ype and ypo */
 268                 ypo = ype = ((ysci + 15) / 16);
 269
 270                 /* the sequence length interval (yacl) has to be set according
 271                    to the prescale value, e.g.  [n   .. 1/2) : 0
 272                                                 [1/2 .. 1/3) : 1
 273                                                 [1/3 .. 1/4) : 2
 274                                                 ... */
 275                 if ( ysci < 512) {
 276                         yacl = 0;
 277                 } else {
 278                         yacl = ( ysci / (1024 - ysci) );
 279                 }
 280
 281                 /* get filter coefficients for cya, cyb from table hps_v_coeff_tab */
 282                 cya_cyb = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].hps_coeff;
 283
 284                 /* get best match in the table of attenuations for vertical scaling */
 285                 v_atten = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].weight_sum;
 286
 287                 for (i = 0; v_attenuation[i] != 0; i++) {
 288                         if (v_attenuation[i] >= v_atten)
 289                                 break;
 290                 }
 291
 292                 dcgy = i;
 293         }
 294
 295         /* ypo and ype swapped in spec ? */
 296         *hps_v_scale    |= (yacm << 31) | (ysci << 21) | (yacl << 15) | (ypo << 8 ) | (ype << 1);
 297
 298         *hps_v_gain     &= ~(MASK_W0|MASK_B2);
 299         *hps_v_gain     |= (dcgy << 16) | (cya_cyb << 0);
 300
 301         return 0;
 302 }
 303
 304 /* simple bubble-sort algorithm with duplicate elimination */
 305 static int sort_and_eliminate(u32* values, int* count)
 306 {
 307         int low = 0, high = 0, top = 0, temp = 0;
 308         int cur = 0, next = 0;
 309
 310         /* sanity checks */
 311         if( (0 > *count) || (NULL == values) ) {
 312                 return -EINVAL;
 313         }
 314
 315         /* bubble sort the first ´count´ items of the array ´values´ */
 316         for( top = *count; top > 0; top--) {
 317                 for( low = 0, high = 1; high < top; low++, high++) {
 318                         if( values[low] > values[high] ) {
 319                                 temp = values[low];
 320                                 values[low] = values[high];
 321                                 values[high] = temp;
 322                         }
 323                 }
 324         }
 325
 326         /* remove duplicate items */
 327         for( cur = 0, next = 1; next < *count; next++) {
 328                 if( values[cur] != values[next])
 329                         values[++cur] = values[next];
 330         }
 331
 332         *count = cur + 1;
 333
 334         return 0;
 335 }
 336
 337 static void calculate_clipping_registers_rect(struct saa7146_dev *dev, struct saa7146_fh *fh,
 338         struct saa7146_video_dma *vdma2, u32* clip_format, u32* arbtr_ctrl, enum v4l2_field field)
 339 {
 340         struct saa7146_vv *vv = dev->vv_data;
 341         u32 *clipping = vv->d_clipping.cpu_addr;
 342
 343         int width = fh->ov.win.w.width;
 344         int height =  fh->ov.win.w.height;
 345         int clipcount = fh->ov.nclips;
 346
 347         u32 line_list[32];
 348         u32 pixel_list[32];
 349         int numdwords = 0;
 350
 351         int i = 0, j = 0;
 352         int cnt_line = 0, cnt_pixel = 0;
 353
 354         int x[32], y[32], w[32], h[32];
 355
 356         /* clear out memory */
 357         memset(&line_list[0],  0x00, sizeof(u32)*32);
 358         memset(&pixel_list[0], 0x00, sizeof(u32)*32);
 359         memset(clipping,  0x00, SAA7146_CLIPPING_MEM);
 360
 361         /* fill the line and pixel-lists */
 362         for(i = 0; i < clipcount; i++) {
 363                 int l = 0, r = 0, t = 0, b = 0;
 364
 365                 x[i] = fh->ov.clips[i].c.left;
 366                 y[i] = fh->ov.clips[i].c.top;
 367                 w[i] = fh->ov.clips[i].c.width;
 368                 h[i] = fh->ov.clips[i].c.height;
 369
 370                 if( w[i] < 0) {
 371                         x[i] += w[i]; w[i] = -w[i];
 372                 }
 373                 if( h[i] < 0) {
 374                         y[i] += h[i]; h[i] = -h[i];
 375                 }
 376                 if( x[i] < 0) {
 377                         w[i] += x[i]; x[i] = 0;
 378                 }
 379                 if( y[i] < 0) {
 380                         h[i] += y[i]; y[i] = 0;
 381                 }
 382                 if( 0 != vv->vflip ) {
 383                         y[i] = height - y[i] - h[i];
 384                 }
 385
 386                 l = x[i];
 387                 r = x[i]+w[i];
 388                 t = y[i];
 389                 b = y[i]+h[i];
 390
 391                 /* insert left/right coordinates */
 392                 pixel_list[ 2*i   ] = min_t(int, l, width);
 393                 pixel_list[(2*i)+1] = min_t(int, r, width);
 394                 /* insert top/bottom coordinates */
 395                 line_list[ 2*i   ] = min_t(int, t, height);
 396                 line_list[(2*i)+1] = min_t(int, b, height);
 397         }
 398
 399         /* sort and eliminate lists */
 400         cnt_line = cnt_pixel = 2*clipcount;
 401         sort_and_eliminate( &pixel_list[0], &cnt_pixel );
 402         sort_and_eliminate( &line_list[0], &cnt_line );
 403
 404         /* calculate the number of used u32s */
 405         numdwords = max_t(int, (cnt_line+1), (cnt_pixel+1))*2;
 406         numdwords = max_t(int, 4, numdwords);
 407         numdwords = min_t(int, 64, numdwords);
 408
 409         /* fill up cliptable */
 410         for(i = 0; i < cnt_pixel; i++) {
 411                 clipping[2*i] |= cpu_to_le32(pixel_list[i] << 16);
 412         }
 413         for(i = 0; i < cnt_line; i++) {
 414                 clipping[(2*i)+1] |= cpu_to_le32(line_list[i] << 16);
 415         }
 416
 417         /* fill up cliptable with the display infos */
 418         for(j = 0; j < clipcount; j++) {
 419
 420                 for(i = 0; i < cnt_pixel; i++) {
 421
 422                         if( x[j] < 0)
 423                                 x[j] = 0;
 424
 425                         if( pixel_list[i] < (x[j] + w[j])) {
 426
 427                                 if ( pixel_list[i] >= x[j] ) {
 428                                         clipping[2*i] |= cpu_to_le32(1 << j);
 429                                 }
 430                         }
 431                 }
 432                 for(i = 0; i < cnt_line; i++) {
 433
 434                         if( y[j] < 0)
 435                                 y[j] = 0;
 436
 437                         if( line_list[i] < (y[j] + h[j]) ) {
 438
 439                                 if( line_list[i] >= y[j] ) {
 440                                         clipping[(2*i)+1] |= cpu_to_le32(1 << j);
 441                                 }
 442                         }
 443                 }
 444         }
 445
 446         /* adjust arbitration control register */
 447         *arbtr_ctrl &= 0xffff00ff;
 448         *arbtr_ctrl |= 0x00001c00;
 449
 450         vdma2->base_even        = vv->d_clipping.dma_handle;
 451         vdma2->base_odd         = vv->d_clipping.dma_handle;
 452         vdma2->prot_addr        = vv->d_clipping.dma_handle+((sizeof(u32))*(numdwords));
 453         vdma2->base_page        = 0x04;
 454         vdma2->pitch            = 0x00;
 455         vdma2->num_line_byte    = (0 << 16 | (sizeof(u32))*(numdwords-1) );
 456
 457         /* set clipping-mode. this depends on the field(s) used */
 458         *clip_format &= 0xfffffff7;
 459         if (V4L2_FIELD_HAS_BOTH(field)) {
 460                 *clip_format |= 0x00000008;
 461         } else {
 462                 *clip_format |= 0x00000000;
 463         }
 464 }
 465
 466 /* disable clipping */
 467 static void saa7146_disable_clipping(struct saa7146_dev *dev)
 468 {
 469         u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
 470
 471         /* mask out relevant bits (=lower word)*/
 472         clip_format &= MASK_W1;
 473
 474         /* upload clipping-registers*/
 475         saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
 476         saa7146_write(dev, MC2, (MASK_05 | MASK_21));
 477
 478         /* disable video dma2 */
 479         saa7146_write(dev, MC1, MASK_21);
 480 }
 481
 482 static void saa7146_set_clipping_rect(struct saa7146_fh *fh)
 483 {
 484         struct saa7146_dev *dev = fh->dev;
 485         enum v4l2_field field = fh->ov.win.field;
 486         struct  saa7146_video_dma vdma2;
 487         u32 clip_format;
 488         u32 arbtr_ctrl;
 489
 490         /* check clipcount, disable clipping if clipcount == 0*/
 491         if( fh->ov.nclips == 0 ) {
 492                 saa7146_disable_clipping(dev);
 493                 return;
 494         }
 495
 496         clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
 497         arbtr_ctrl = saa7146_read(dev, PCI_BT_V1);
 498
 499         calculate_clipping_registers_rect(dev, fh, &vdma2, &clip_format, &arbtr_ctrl, field);
 500
 501         /* set clipping format */
 502         clip_format &= 0xffff0008;
 503         clip_format |= (SAA7146_CLIPPING_RECT << 4);
 504
 505         /* prepare video dma2 */
 506         saa7146_write(dev, BASE_EVEN2,          vdma2.base_even);
 507         saa7146_write(dev, BASE_ODD2,           vdma2.base_odd);
 508         saa7146_write(dev, PROT_ADDR2,          vdma2.prot_addr);
 509         saa7146_write(dev, BASE_PAGE2,          vdma2.base_page);
 510         saa7146_write(dev, PITCH2,              vdma2.pitch);
 511         saa7146_write(dev, NUM_LINE_BYTE2,      vdma2.num_line_byte);
 512
 513         /* prepare the rest */
 514         saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
 515         saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);
 516
 517         /* upload clip_control-register, clipping-registers, enable video dma2 */
 518         saa7146_write(dev, MC2, (MASK_05 | MASK_21 | MASK_03 | MASK_19));
 519         saa7146_write(dev, MC1, (MASK_05 | MASK_21));
 520 }
 521
 522 static void saa7146_set_window(struct saa7146_dev *dev, int width, int height, enum v4l2_field field)
 523 {
 524         struct saa7146_vv *vv = dev->vv_data;
 525
 526         int source = vv->current_hps_source;
 527         int sync = vv->current_hps_sync;
 528
 529         u32 hps_v_scale = 0, hps_v_gain  = 0, hps_ctrl = 0, hps_h_prescale = 0, hps_h_scale = 0;
 530
 531         /* set vertical scale */
 532         hps_v_scale = 0; /* all bits get set by the function-call */
 533         hps_v_gain  = 0; /* fixme: saa7146_read(dev, HPS_V_GAIN);*/
 534         calculate_v_scale_registers(dev, field, vv->standard->v_field*2, height, &hps_v_scale, &hps_v_gain);
 535
 536         /* set horizontal scale */
 537         hps_ctrl        = 0;
 538         hps_h_prescale  = 0; /* all bits get set in the function */
 539         hps_h_scale     = 0;
 540         calculate_h_scale_registers(dev, vv->standard->h_pixels, width, vv->hflip, &hps_ctrl, &hps_v_gain, &hps_h_prescale, &hps_h_scale);
 541
 542         /* set hyo and hxo */
 543         calculate_hxo_and_hyo(vv, &hps_h_scale, &hps_ctrl);
 544         calculate_hps_source_and_sync(dev, source, sync, &hps_ctrl);
 545
 546         /* write out new register contents */
 547         saa7146_write(dev, HPS_V_SCALE, hps_v_scale);
 548         saa7146_write(dev, HPS_V_GAIN,  hps_v_gain);
 549         saa7146_write(dev, HPS_CTRL,    hps_ctrl);
 550         saa7146_write(dev, HPS_H_PRESCALE,hps_h_prescale);
 551         saa7146_write(dev, HPS_H_SCALE, hps_h_scale);
 552
 553         /* upload shadow-ram registers */
 554         saa7146_write(dev, MC2, (MASK_05 | MASK_06 | MASK_21 | MASK_22) );
 555 }
 556
 557 /* calculate the new memory offsets for a desired position */
 558 static void saa7146_set_position(struct saa7146_dev *dev, int w_x, int w_y, int w_height, enum v4l2_field field, u32 pixelformat)
 559 {
 560         struct saa7146_vv *vv = dev->vv_data;
 561         struct saa7146_format *sfmt = format_by_fourcc(dev, pixelformat);
 562
 563         int b_depth = vv->ov_fmt->depth;
 564         int b_bpl = vv->ov_fb.fmt.bytesperline;
 565         /* The unsigned long cast is to remove a 64-bit compile warning since
 566            it looks like a 64-bit address is cast to a 32-bit value, even
 567            though the base pointer is really a 32-bit physical address that
 568            goes into a 32-bit DMA register.
 569            FIXME: might not work on some 64-bit platforms, but see the FIXME
 570            in struct v4l2_framebuffer (videodev2.h) for that.
 571          */
 572         u32 base = (u32)(unsigned long)vv->ov_fb.base;
 573
 574         struct  saa7146_video_dma vdma1;
 575
 576         /* calculate memory offsets for picture, look if we shall top-down-flip */
 577         vdma1.pitch     = 2*b_bpl;
 578         if ( 0 == vv->vflip ) {
 579                 vdma1.base_even = base + (w_y * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
 580                 vdma1.base_odd  = vdma1.base_even + (vdma1.pitch / 2);
 581                 vdma1.prot_addr = vdma1.base_even + (w_height * (vdma1.pitch / 2));
 582         }
 583         else {
 584                 vdma1.base_even = base + ((w_y+w_height) * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
 585                 vdma1.base_odd  = vdma1.base_even - (vdma1.pitch / 2);
 586                 vdma1.prot_addr = vdma1.base_odd - (w_height * (vdma1.pitch / 2));
 587         }
 588
 589         if (V4L2_FIELD_HAS_BOTH(field)) {
 590         } else if (field == V4L2_FIELD_ALTERNATE) {
 591                 /* fixme */
 592                 vdma1.base_odd = vdma1.prot_addr;
 593                 vdma1.pitch /= 2;
 594         } else if (field == V4L2_FIELD_TOP) {
 595                 vdma1.base_odd = vdma1.prot_addr;
 596                 vdma1.pitch /= 2;
 597         } else if (field == V4L2_FIELD_BOTTOM) {
 598                 vdma1.base_odd = vdma1.base_even;
 599                 vdma1.base_even = vdma1.prot_addr;
 600                 vdma1.pitch /= 2;
 601         }
 602
 603         if ( 0 != vv->vflip ) {
 604                 vdma1.pitch *= -1;
 605         }
 606
 607         vdma1.base_page = sfmt->swap;
 608         vdma1.num_line_byte = (vv->standard->v_field<<16)+vv->standard->h_pixels;
 609
 610         saa7146_write_out_dma(dev, 1, &vdma1);
 611 }
 612
 613 static void saa7146_set_output_format(struct saa7146_dev *dev, unsigned long palette)
 614 {
 615         u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
 616
 617         /* call helper function */
 618         calculate_output_format_register(dev,palette,&clip_format);
 619
 620         /* update the hps registers */
 621         saa7146_write(dev, CLIP_FORMAT_CTRL, clip_format);
 622         saa7146_write(dev, MC2, (MASK_05 | MASK_21));
 623 }
 624
 625 /* select input-source */
 626 void saa7146_set_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync)
 627 {
 628         struct saa7146_vv *vv = dev->vv_data;
 629         u32 hps_ctrl = 0;
 630
 631         /* read old state */
 632         hps_ctrl = saa7146_read(dev, HPS_CTRL);
 633
 634         hps_ctrl &= ~( MASK_31 | MASK_30 | MASK_28 );
 635         hps_ctrl |= (source << 30) | (sync << 28);
 636
 637         /* write back & upload register */
 638         saa7146_write(dev, HPS_CTRL, hps_ctrl);
 639         saa7146_write(dev, MC2, (MASK_05 | MASK_21));
 640
 641         vv->current_hps_source = source;
 642         vv->current_hps_sync = sync;
 643 }
 644 EXPORT_SYMBOL_GPL(saa7146_set_hps_source_and_sync);
 645
 646 int saa7146_enable_overlay(struct saa7146_fh *fh)
 647 {
 648         struct saa7146_dev *dev = fh->dev;
 649         struct saa7146_vv *vv = dev->vv_data;
 650
 651         saa7146_set_window(dev, fh->ov.win.w.width, fh->ov.win.w.height, fh->ov.win.field);
 652         saa7146_set_position(dev, fh->ov.win.w.left, fh->ov.win.w.top, fh->ov.win.w.height, fh->ov.win.field, vv->ov_fmt->pixelformat);
 653         saa7146_set_output_format(dev, vv->ov_fmt->trans);
 654         saa7146_set_clipping_rect(fh);
 655
 656         /* enable video dma1 */
 657         saa7146_write(dev, MC1, (MASK_06 | MASK_22));
 658         return 0;
 659 }
 660
 661 void saa7146_disable_overlay(struct saa7146_fh *fh)
 662 {
 663         struct saa7146_dev *dev = fh->dev;
 664
 665         /* disable clipping + video dma1 */
 666         saa7146_disable_clipping(dev);
 667         saa7146_write(dev, MC1, MASK_22);
 668 }
 669
 670 void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma)
 671 {
 672         int where = 0;
 673
 674         if( which < 1 || which > 3) {
 675                 return;
 676         }
 677
 678         /* calculate starting address */
 679         where  = (which-1)*0x18;
 680
 681         saa7146_write(dev, where,       vdma->base_odd);
 682         saa7146_write(dev, where+0x04,  vdma->base_even);
 683         saa7146_write(dev, where+0x08,  vdma->prot_addr);
 684         saa7146_write(dev, where+0x0c,  vdma->pitch);
 685         saa7146_write(dev, where+0x10,  vdma->base_page);
 686         saa7146_write(dev, where+0x14,  vdma->num_line_byte);
 687
 688         /* upload */
 689         saa7146_write(dev, MC2, (MASK_02<<(which-1))|(MASK_18<<(which-1)));
 690 /*
 691         printk("vdma%d.base_even:     0x%08x\n", which,vdma->base_even);
 692         printk("vdma%d.base_odd:      0x%08x\n", which,vdma->base_odd);
 693         printk("vdma%d.prot_addr:     0x%08x\n", which,vdma->prot_addr);
 694         printk("vdma%d.base_page:     0x%08x\n", which,vdma->base_page);
 695         printk("vdma%d.pitch:         0x%08x\n", which,vdma->pitch);
 696         printk("vdma%d.num_line_byte: 0x%08x\n", which,vdma->num_line_byte);
 697 */
 698 }
 699
 700 static int calculate_video_dma_grab_packed(struct saa7146_dev* dev, struct saa7146_buf *buf)
 701 {
 702         struct saa7146_vv *vv = dev->vv_data;
 703         struct saa7146_video_dma vdma1;
 704
 705         struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
 706
 707         int width = buf->fmt->width;
 708         int height = buf->fmt->height;
 709         int bytesperline = buf->fmt->bytesperline;
 710         enum v4l2_field field = buf->fmt->field;
 711
 712         int depth = sfmt->depth;
 713
 714         DEB_CAP(("[size=%dx%d,fields=%s]\n",
 715                 width,height,v4l2_field_names[field]));
 716
 717         if( bytesperline != 0) {
 718                 vdma1.pitch = bytesperline*2;
 719         } else {
 720                 vdma1.pitch = (width*depth*2)/8;
 721         }
 722         vdma1.num_line_byte     = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
 723         vdma1.base_page         = buf->pt[0].dma | ME1 | sfmt->swap;
 724
 725         if( 0 != vv->vflip ) {
 726                 vdma1.prot_addr = buf->pt[0].offset;
 727                 vdma1.base_even = buf->pt[0].offset+(vdma1.pitch/2)*height;
 728                 vdma1.base_odd  = vdma1.base_even - (vdma1.pitch/2);
 729         } else {
 730                 vdma1.base_even = buf->pt[0].offset;
 731                 vdma1.base_odd  = vdma1.base_even + (vdma1.pitch/2);
 732                 vdma1.prot_addr = buf->pt[0].offset+(vdma1.pitch/2)*height;
 733         }
 734
 735         if (V4L2_FIELD_HAS_BOTH(field)) {
 736         } else if (field == V4L2_FIELD_ALTERNATE) {
 737                 /* fixme */
 738                 if ( vv->last_field == V4L2_FIELD_TOP ) {
 739                         vdma1.base_odd  = vdma1.prot_addr;
 740                         vdma1.pitch /= 2;
 741                 } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
 742                         vdma1.base_odd  = vdma1.base_even;
 743                         vdma1.base_even = vdma1.prot_addr;
 744                         vdma1.pitch /= 2;
 745                 }
 746         } else if (field == V4L2_FIELD_TOP) {
 747                 vdma1.base_odd  = vdma1.prot_addr;
 748                 vdma1.pitch /= 2;
 749         } else if (field == V4L2_FIELD_BOTTOM) {
 750                 vdma1.base_odd  = vdma1.base_even;
 751                 vdma1.base_even = vdma1.prot_addr;
 752                 vdma1.pitch /= 2;
 753         }
 754
 755         if( 0 != vv->vflip ) {
 756                 vdma1.pitch *= -1;
 757         }
 758
 759         saa7146_write_out_dma(dev, 1, &vdma1);
 760         return 0;
 761 }
 762
 763 static int calc_planar_422(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
 764 {
 765         int height = buf->fmt->height;
 766         int width = buf->fmt->width;
 767
 768         vdma2->pitch    = width;
 769         vdma3->pitch    = width;
 770
 771         /* fixme: look at bytesperline! */
 772
 773         if( 0 != vv->vflip ) {
 774                 vdma2->prot_addr        = buf->pt[1].offset;
 775                 vdma2->base_even        = ((vdma2->pitch/2)*height)+buf->pt[1].offset;
 776                 vdma2->base_odd         = vdma2->base_even - (vdma2->pitch/2);
 777
 778                 vdma3->prot_addr        = buf->pt[2].offset;
 779                 vdma3->base_even        = ((vdma3->pitch/2)*height)+buf->pt[2].offset;
 780                 vdma3->base_odd         = vdma3->base_even - (vdma3->pitch/2);
 781         } else {
 782                 vdma3->base_even        = buf->pt[2].offset;
 783                 vdma3->base_odd         = vdma3->base_even + (vdma3->pitch/2);
 784                 vdma3->prot_addr        = (vdma3->pitch/2)*height+buf->pt[2].offset;
 785
 786                 vdma2->base_even        = buf->pt[1].offset;
 787                 vdma2->base_odd         = vdma2->base_even + (vdma2->pitch/2);
 788                 vdma2->prot_addr        = (vdma2->pitch/2)*height+buf->pt[1].offset;
 789         }
 790
 791         return 0;
 792 }
 793
 794 static int calc_planar_420(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
 795 {
 796         int height = buf->fmt->height;
 797         int width = buf->fmt->width;
 798
 799         vdma2->pitch    = width/2;
 800         vdma3->pitch    = width/2;
 801
 802         if( 0 != vv->vflip ) {
 803                 vdma2->prot_addr        = buf->pt[2].offset;
 804                 vdma2->base_even        = ((vdma2->pitch/2)*height)+buf->pt[2].offset;
 805                 vdma2->base_odd         = vdma2->base_even - (vdma2->pitch/2);
 806
 807                 vdma3->prot_addr        = buf->pt[1].offset;
 808                 vdma3->base_even        = ((vdma3->pitch/2)*height)+buf->pt[1].offset;
 809                 vdma3->base_odd         = vdma3->base_even - (vdma3->pitch/2);
 810
 811         } else {
 812                 vdma3->base_even        = buf->pt[2].offset;
 813                 vdma3->base_odd         = vdma3->base_even + (vdma3->pitch);
 814                 vdma3->prot_addr        = (vdma3->pitch/2)*height+buf->pt[2].offset;
 815
 816                 vdma2->base_even        = buf->pt[1].offset;
 817                 vdma2->base_odd         = vdma2->base_even + (vdma2->pitch);
 818                 vdma2->prot_addr        = (vdma2->pitch/2)*height+buf->pt[1].offset;
 819         }
 820         return 0;
 821 }
 822
 823 static int calculate_video_dma_grab_planar(struct saa7146_dev* dev, struct saa7146_buf *buf)
 824 {
 825         struct saa7146_vv *vv = dev->vv_data;
 826         struct saa7146_video_dma vdma1;
 827         struct saa7146_video_dma vdma2;
 828         struct saa7146_video_dma vdma3;
 829
 830         struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
 831
 832         int width = buf->fmt->width;
 833         int height = buf->fmt->height;
 834         enum v4l2_field field = buf->fmt->field;
 835
 836         BUG_ON(0 == buf->pt[0].dma);
 837         BUG_ON(0 == buf->pt[1].dma);
 838         BUG_ON(0 == buf->pt[2].dma);
 839
 840         DEB_CAP(("[size=%dx%d,fields=%s]\n",
 841                 width,height,v4l2_field_names[field]));
 842
 843         /* fixme: look at bytesperline! */
 844
 845         /* fixme: what happens for user space buffers here?. The offsets are
 846            most likely wrong, this version here only works for page-aligned
 847            buffers, modifications to the pagetable-functions are necessary...*/
 848
 849         vdma1.pitch             = width*2;
 850         vdma1.num_line_byte     = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
 851         vdma1.base_page         = buf->pt[0].dma | ME1;
 852
 853         if( 0 != vv->vflip ) {
 854                 vdma1.prot_addr = buf->pt[0].offset;
 855                 vdma1.base_even = ((vdma1.pitch/2)*height)+buf->pt[0].offset;
 856                 vdma1.base_odd  = vdma1.base_even - (vdma1.pitch/2);
 857         } else {
 858                 vdma1.base_even = buf->pt[0].offset;
 859                 vdma1.base_odd  = vdma1.base_even + (vdma1.pitch/2);
 860                 vdma1.prot_addr = (vdma1.pitch/2)*height+buf->pt[0].offset;
 861         }
 862
 863         vdma2.num_line_byte     = 0; /* unused */
 864         vdma2.base_page         = buf->pt[1].dma | ME1;
 865
 866         vdma3.num_line_byte     = 0; /* unused */
 867         vdma3.base_page         = buf->pt[2].dma | ME1;
 868
 869         switch( sfmt->depth ) {
 870                 case 12: {
 871                         calc_planar_420(vv,buf,&vdma2,&vdma3);
 872                         break;
 873                 }
 874                 case 16: {
 875                         calc_planar_422(vv,buf,&vdma2,&vdma3);
 876                         break;
 877                 }
 878                 default: {
 879                         return -1;
 880                 }
 881         }
 882
 883         if (V4L2_FIELD_HAS_BOTH(field)) {
 884         } else if (field == V4L2_FIELD_ALTERNATE) {
 885                 /* fixme */
 886                 vdma1.base_odd  = vdma1.prot_addr;
 887                 vdma1.pitch /= 2;
 888                 vdma2.base_odd  = vdma2.prot_addr;
 889                 vdma2.pitch /= 2;
 890                 vdma3.base_odd  = vdma3.prot_addr;
 891                 vdma3.pitch /= 2;
 892         } else if (field == V4L2_FIELD_TOP) {
 893                 vdma1.base_odd  = vdma1.prot_addr;
 894                 vdma1.pitch /= 2;
 895                 vdma2.base_odd  = vdma2.prot_addr;
 896                 vdma2.pitch /= 2;
 897                 vdma3.base_odd  = vdma3.prot_addr;
 898                 vdma3.pitch /= 2;
 899         } else if (field == V4L2_FIELD_BOTTOM) {
 900                 vdma1.base_odd  = vdma1.base_even;
 901                 vdma1.base_even = vdma1.prot_addr;
 902                 vdma1.pitch /= 2;
 903                 vdma2.base_odd  = vdma2.base_even;
 904                 vdma2.base_even = vdma2.prot_addr;
 905                 vdma2.pitch /= 2;
 906                 vdma3.base_odd  = vdma3.base_even;
 907                 vdma3.base_even = vdma3.prot_addr;
 908                 vdma3.pitch /= 2;
 909         }
 910
 911         if( 0 != vv->vflip ) {
 912                 vdma1.pitch *= -1;
 913                 vdma2.pitch *= -1;
 914                 vdma3.pitch *= -1;
 915         }
 916
 917         saa7146_write_out_dma(dev, 1, &vdma1);
 918         if( (sfmt->flags & FORMAT_BYTE_SWAP) != 0 ) {
 919                 saa7146_write_out_dma(dev, 3, &vdma2);
 920                 saa7146_write_out_dma(dev, 2, &vdma3);
 921         } else {
 922                 saa7146_write_out_dma(dev, 2, &vdma2);
 923                 saa7146_write_out_dma(dev, 3, &vdma3);
 924         }
 925         return 0;
 926 }
 927
 928 static void program_capture_engine(struct saa7146_dev *dev, int planar)
 929 {
 930         struct saa7146_vv *vv = dev->vv_data;
 931         int count = 0;
 932
 933         unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
 934         unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
 935
 936         /* wait for o_fid_a/b / e_fid_a/b toggle only if rps register 0 is not set*/
 937         WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | o_wait);
 938         WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | e_wait);
 939
 940         /* set rps register 0 */
 941         WRITE_RPS0(CMD_WR_REG | (1 << 8) | (MC2/4));
 942         WRITE_RPS0(MASK_27 | MASK_11);
 943
 944         /* turn on video-dma1 */
 945         WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
 946         WRITE_RPS0(MASK_06 | MASK_22);                  /* => mask */
 947         WRITE_RPS0(MASK_06 | MASK_22);                  /* => values */
 948         if( 0 != planar ) {
 949                 /* turn on video-dma2 */
 950                 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
 951                 WRITE_RPS0(MASK_05 | MASK_21);                  /* => mask */
 952                 WRITE_RPS0(MASK_05 | MASK_21);                  /* => values */
 953
 954                 /* turn on video-dma3 */
 955                 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
 956                 WRITE_RPS0(MASK_04 | MASK_20);                  /* => mask */
 957                 WRITE_RPS0(MASK_04 | MASK_20);                  /* => values */
 958         }
 959
 960         /* wait for o_fid_a/b / e_fid_a/b toggle */
 961         if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
 962                 WRITE_RPS0(CMD_PAUSE | o_wait);
 963                 WRITE_RPS0(CMD_PAUSE | e_wait);
 964         } else if ( vv->last_field == V4L2_FIELD_TOP ) {
 965                 WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
 966                 WRITE_RPS0(CMD_PAUSE | o_wait);
 967         } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
 968                 WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
 969                 WRITE_RPS0(CMD_PAUSE | e_wait);
 970         }
 971
 972         /* turn off video-dma1 */
 973         WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
 974         WRITE_RPS0(MASK_22 | MASK_06);                  /* => mask */
 975         WRITE_RPS0(MASK_22);                            /* => values */
 976         if( 0 != planar ) {
 977                 /* turn off video-dma2 */
 978                 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
 979                 WRITE_RPS0(MASK_05 | MASK_21);                  /* => mask */
 980                 WRITE_RPS0(MASK_21);                            /* => values */
 981
 982                 /* turn off video-dma3 */
 983                 WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
 984                 WRITE_RPS0(MASK_04 | MASK_20);                  /* => mask */
 985                 WRITE_RPS0(MASK_20);                            /* => values */
 986         }
 987
 988         /* generate interrupt */
 989         WRITE_RPS0(CMD_INTERRUPT);
 990
 991         /* stop */
 992         WRITE_RPS0(CMD_STOP);
 993 }
 994
 995 void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
 996 {
 997         struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
 998         struct saa7146_vv *vv = dev->vv_data;
 999         u32 vdma1_prot_addr;
1000
1001         DEB_CAP(("buf:%p, next:%p\n",buf,next));
1002
1003         vdma1_prot_addr = saa7146_read(dev, PROT_ADDR1);
1004         if( 0 == vdma1_prot_addr ) {
1005                 /* clear out beginning of streaming bit (rps register 0)*/
1006                 DEB_CAP(("forcing sync to new frame\n"));
1007                 saa7146_write(dev, MC2, MASK_27 );
1008         }
1009
1010         saa7146_set_window(dev, buf->fmt->width, buf->fmt->height, buf->fmt->field);
1011         saa7146_set_output_format(dev, sfmt->trans);
1012         saa7146_disable_clipping(dev);
1013
1014         if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
1015         } else if ( vv->last_field == V4L2_FIELD_TOP ) {
1016                 vv->last_field = V4L2_FIELD_BOTTOM;
1017         } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
1018                 vv->last_field = V4L2_FIELD_TOP;
1019         }
1020
1021         if( 0 != IS_PLANAR(sfmt->trans)) {
1022                 calculate_video_dma_grab_planar(dev, buf);
1023                 program_capture_engine(dev,1);
1024         } else {
1025                 calculate_video_dma_grab_packed(dev, buf);
1026                 program_capture_engine(dev,0);
1027         }
1028
1029 /*
1030         printk("vdma%d.base_even:     0x%08x\n", 1,saa7146_read(dev,BASE_EVEN1));
1031         printk("vdma%d.base_odd:      0x%08x\n", 1,saa7146_read(dev,BASE_ODD1));
1032         printk("vdma%d.prot_addr:     0x%08x\n", 1,saa7146_read(dev,PROT_ADDR1));
1033         printk("vdma%d.base_page:     0x%08x\n", 1,saa7146_read(dev,BASE_PAGE1));
1034         printk("vdma%d.pitch:         0x%08x\n", 1,saa7146_read(dev,PITCH1));
1035         printk("vdma%d.num_line_byte: 0x%08x\n", 1,saa7146_read(dev,NUM_LINE_BYTE1));
1036         printk("vdma%d => vptr      : 0x%08x\n", 1,saa7146_read(dev,PCI_VDP1));
1037 */
1038
1039         /* write the address of the rps-program */
1040         saa7146_write(dev, RPS_ADDR0, dev->d_rps0.dma_handle);
1041
1042         /* turn on rps */
1043         saa7146_write(dev, MC1, (MASK_12 | MASK_28));
1044 }