2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
21 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
22 * so the code in this file is compiled twice, once per pte size.
26 #define pt_element_t u64
27 #define guest_walker guest_walker64
28 #define FNAME(name) paging##64_##name
29 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
30 #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
31 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
32 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
33 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
34 #define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK
36 #define PT_MAX_FULL_LEVELS 4
38 #define PT_MAX_FULL_LEVELS 2
41 #define pt_element_t u32
42 #define guest_walker guest_walker32
43 #define FNAME(name) paging##32_##name
44 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
45 #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
46 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
47 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
48 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
49 #define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK
50 #define PT_MAX_FULL_LEVELS 2
52 #error Invalid PTTYPE value
56 * The guest_walker structure emulates the behavior of the hardware page
61 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
64 pt_element_t inherited_ar;
68 * Fetch a guest pte for a guest virtual address
70 static void FNAME(walk_addr)(struct guest_walker *walker,
71 struct kvm_vcpu *vcpu, gva_t addr)
74 struct kvm_memory_slot *slot;
79 pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
80 walker->level = vcpu->mmu.root_level;
84 if (!is_long_mode(vcpu)) {
85 walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3];
87 if (!(root & PT_PRESENT_MASK))
92 table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
93 walker->table_gfn[walker->level - 1] = table_gfn;
94 pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
95 walker->level - 1, table_gfn);
96 slot = gfn_to_memslot(vcpu->kvm, table_gfn);
97 hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK);
98 walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);
100 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
101 (vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) == 0);
103 walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;
106 int index = PT_INDEX(addr, walker->level);
109 ptep = &walker->table[index];
110 ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
111 ((unsigned long)ptep & PAGE_MASK));
113 if (is_present_pte(*ptep) && !(*ptep & PT_ACCESSED_MASK))
114 *ptep |= PT_ACCESSED_MASK;
116 if (!is_present_pte(*ptep) ||
117 walker->level == PT_PAGE_TABLE_LEVEL ||
118 (walker->level == PT_DIRECTORY_LEVEL &&
119 (*ptep & PT_PAGE_SIZE_MASK) &&
120 (PTTYPE == 64 || is_pse(vcpu))))
123 if (walker->level != 3 || is_long_mode(vcpu))
124 walker->inherited_ar &= walker->table[index];
125 table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
126 paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK);
127 kunmap_atomic(walker->table, KM_USER0);
128 walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
131 walker->table_gfn[walker->level - 1 ] = table_gfn;
132 pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
133 walker->level - 1, table_gfn);
138 static void FNAME(release_walker)(struct guest_walker *walker)
141 kunmap_atomic(walker->table, KM_USER0);
144 static void FNAME(set_pte)(struct kvm_vcpu *vcpu, u64 guest_pte,
145 u64 *shadow_pte, u64 access_bits)
147 ASSERT(*shadow_pte == 0);
148 access_bits &= guest_pte;
149 *shadow_pte = (guest_pte & PT_PTE_COPY_MASK);
150 set_pte_common(vcpu, shadow_pte, guest_pte & PT_BASE_ADDR_MASK,
151 guest_pte & PT_DIRTY_MASK, access_bits);
154 static void FNAME(set_pde)(struct kvm_vcpu *vcpu, u64 guest_pde,
155 u64 *shadow_pte, u64 access_bits,
160 ASSERT(*shadow_pte == 0);
161 access_bits &= guest_pde;
162 gaddr = (guest_pde & PT_DIR_BASE_ADDR_MASK) + PAGE_SIZE * index;
163 if (PTTYPE == 32 && is_cpuid_PSE36())
164 gaddr |= (guest_pde & PT32_DIR_PSE36_MASK) <<
165 (32 - PT32_DIR_PSE36_SHIFT);
166 *shadow_pte = guest_pde & PT_PTE_COPY_MASK;
167 set_pte_common(vcpu, shadow_pte, gaddr,
168 guest_pde & PT_DIRTY_MASK, access_bits);
172 * Fetch a shadow pte for a specific level in the paging hierarchy.
174 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
175 struct guest_walker *walker)
179 u64 *prev_shadow_ent = NULL;
180 pt_element_t *guest_ent = walker->ptep;
182 if (!is_present_pte(*guest_ent))
185 shadow_addr = vcpu->mmu.root_hpa;
186 level = vcpu->mmu.shadow_root_level;
187 if (level == PT32E_ROOT_LEVEL) {
188 shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
189 shadow_addr &= PT64_BASE_ADDR_MASK;
194 u32 index = SHADOW_PT_INDEX(addr, level);
195 u64 *shadow_ent = ((u64 *)__va(shadow_addr)) + index;
196 struct kvm_mmu_page *shadow_page;
201 if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) {
202 if (level == PT_PAGE_TABLE_LEVEL)
204 shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
205 prev_shadow_ent = shadow_ent;
209 if (level == PT_PAGE_TABLE_LEVEL) {
211 if (walker->level == PT_DIRECTORY_LEVEL) {
213 *prev_shadow_ent |= PT_SHADOW_PS_MARK;
214 FNAME(set_pde)(vcpu, *guest_ent, shadow_ent,
215 walker->inherited_ar,
216 PT_INDEX(addr, PT_PAGE_TABLE_LEVEL));
218 ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
219 FNAME(set_pte)(vcpu, *guest_ent, shadow_ent, walker->inherited_ar);
224 if (level - 1 == PT_PAGE_TABLE_LEVEL
225 && walker->level == PT_DIRECTORY_LEVEL) {
227 table_gfn = (*guest_ent & PT_BASE_ADDR_MASK)
231 table_gfn = walker->table_gfn[level - 2];
233 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
234 metaphysical, shadow_ent);
236 return ERR_PTR(-ENOMEM);
237 shadow_addr = shadow_page->page_hpa;
238 shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
239 | PT_WRITABLE_MASK | PT_USER_MASK;
240 *shadow_ent = shadow_pte;
241 prev_shadow_ent = shadow_ent;
246 * The guest faulted for write. We need to
248 * - check write permissions
249 * - update the guest pte dirty bit
250 * - update our own dirty page tracking structures
252 static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu,
254 struct guest_walker *walker,
259 pt_element_t *guest_ent;
263 if (is_writeble_pte(*shadow_ent))
266 writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK;
269 * User mode access. Fail if it's a kernel page or a read-only
272 if (!(*shadow_ent & PT_SHADOW_USER_MASK) || !writable_shadow)
274 ASSERT(*shadow_ent & PT_USER_MASK);
277 * Kernel mode access. Fail if it's a read-only page and
278 * supervisor write protection is enabled.
280 if (!writable_shadow) {
281 if (is_write_protection(vcpu))
283 *shadow_ent &= ~PT_USER_MASK;
286 guest_ent = walker->ptep;
288 if (!is_present_pte(*guest_ent)) {
293 gfn = (*guest_ent & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
294 if (kvm_mmu_lookup_page(vcpu, gfn)) {
295 pgprintk("%s: found shadow page for %lx, marking ro\n",
300 mark_page_dirty(vcpu->kvm, gfn);
301 *shadow_ent |= PT_WRITABLE_MASK;
302 *guest_ent |= PT_DIRTY_MASK;
303 rmap_add(vcpu->kvm, shadow_ent);
309 * Page fault handler. There are several causes for a page fault:
310 * - there is no shadow pte for the guest pte
311 * - write access through a shadow pte marked read only so that we can set
313 * - write access to a shadow pte marked read only so we can update the page
314 * dirty bitmap, when userspace requests it
315 * - mmio access; in this case we will never install a present shadow pte
316 * - normal guest page fault due to the guest pte marked not present, not
317 * writable, or not executable
319 * Returns: 1 if we need to emulate the instruction, 0 otherwise
321 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
324 int write_fault = error_code & PFERR_WRITE_MASK;
325 int pte_present = error_code & PFERR_PRESENT_MASK;
326 int user_fault = error_code & PFERR_USER_MASK;
327 struct guest_walker walker;
332 pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
334 * Look up the shadow pte for the faulting address.
337 FNAME(walk_addr)(&walker, vcpu, addr);
338 shadow_pte = FNAME(fetch)(vcpu, addr, &walker);
339 if (IS_ERR(shadow_pte)) { /* must be -ENOMEM */
340 printk("%s: oom\n", __FUNCTION__);
341 nonpaging_flush(vcpu);
342 FNAME(release_walker)(&walker);
349 * The page is not mapped by the guest. Let the guest handle it.
352 pgprintk("%s: not mapped\n", __FUNCTION__);
353 inject_page_fault(vcpu, addr, error_code);
354 FNAME(release_walker)(&walker);
358 pgprintk("%s: shadow pte %p %llx\n", __FUNCTION__,
359 shadow_pte, *shadow_pte);
362 * Update the shadow pte.
365 fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr,
366 user_fault, &write_pt);
368 fixed = fix_read_pf(shadow_pte);
370 pgprintk("%s: updated shadow pte %p %llx\n", __FUNCTION__,
371 shadow_pte, *shadow_pte);
373 FNAME(release_walker)(&walker);
376 * mmio: emulate if accessible, otherwise its a guest fault.
378 if (is_io_pte(*shadow_pte)) {
379 if (may_access(*shadow_pte, write_fault, user_fault))
381 pgprintk("%s: io work, no access\n", __FUNCTION__);
382 inject_page_fault(vcpu, addr,
383 error_code | PFERR_PRESENT_MASK);
388 * pte not present, guest page fault.
390 if (pte_present && !fixed && !write_pt) {
391 inject_page_fault(vcpu, addr, error_code);
400 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
402 struct guest_walker walker;
403 pt_element_t guest_pte;
406 FNAME(walk_addr)(&walker, vcpu, vaddr);
407 guest_pte = *walker.ptep;
408 FNAME(release_walker)(&walker);
410 if (!is_present_pte(guest_pte))
413 if (walker.level == PT_DIRECTORY_LEVEL) {
414 ASSERT((guest_pte & PT_PAGE_SIZE_MASK));
415 ASSERT(PTTYPE == 64 || is_pse(vcpu));
417 gpa = (guest_pte & PT_DIR_BASE_ADDR_MASK) | (vaddr &
418 (PT_LEVEL_MASK(PT_PAGE_TABLE_LEVEL) | ~PAGE_MASK));
420 if (PTTYPE == 32 && is_cpuid_PSE36())
421 gpa |= (guest_pte & PT32_DIR_PSE36_MASK) <<
422 (32 - PT32_DIR_PSE36_SHIFT);
424 gpa = (guest_pte & PT_BASE_ADDR_MASK);
425 gpa |= (vaddr & ~PAGE_MASK);
434 #undef PT_BASE_ADDR_MASK
436 #undef SHADOW_PT_INDEX
438 #undef PT_PTE_COPY_MASK
439 #undef PT_NON_PTE_COPY_MASK
440 #undef PT_DIR_BASE_ADDR_MASK
441 #undef PT_MAX_FULL_LEVELS