drivers/isdn/hardware/mISDN/hfcpci.c

   1 /*
   2  *
   3  * hfcpci.c     low level driver for CCD's hfc-pci based cards
   4  *
   5  * Author     Werner Cornelius (werner@isdn4linux.de)
   6  *            based on existing driver for CCD hfc ISA cards
   7  *            type approval valid for HFC-S PCI A based card
   8  *
   9  * Copyright 1999  by Werner Cornelius (werner@isdn-development.de)
  10  * Copyright 2008  by Karsten Keil <kkeil@novell.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2, or (at your option)
  15  * any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Module options:
  27  *
  28  * debug:
  29  *      NOTE: only one poll value must be given for all cards
  30  *      See hfc_pci.h for debug flags.
  31  *
  32  * poll:
  33  *      NOTE: only one poll value must be given for all cards
  34  *      Give the number of samples for each fifo process.
  35  *      By default 128 is used. Decrease to reduce delay, increase to
  36  *      reduce cpu load. If unsure, don't mess with it!
  37  *      A value of 128 will use controller's interrupt. Other values will
  38  *      use kernel timer, because the controller will not allow lower values
  39  *      than 128.
  40  *      Also note that the value depends on the kernel timer frequency.
  41  *      If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
  42  *      If the kernel uses 100 Hz, steps of 80 samples are possible.
  43  *      If the kernel uses 300 Hz, steps of about 26 samples are possible.
  44  *
  45  */
  46
  47 #include <linux/module.h>
  48 #include <linux/pci.h>
  49 #include <linux/delay.h>
  50 #include <linux/mISDNhw.h>
  51 #include <linux/slab.h>
  52
  53 #include "hfc_pci.h"
  54
  55 static const char *hfcpci_revision = "2.0";
  56
  57 static int HFC_cnt;
  58 static uint debug;
  59 static uint poll, tics;
  60 static struct timer_list hfc_tl;
  61 static unsigned long hfc_jiffies;
  62
  63 MODULE_AUTHOR("Karsten Keil");
  64 MODULE_LICENSE("GPL");
  65 module_param(debug, uint, S_IRUGO | S_IWUSR);
  66 module_param(poll, uint, S_IRUGO | S_IWUSR);
  67
  68 enum {
  69         HFC_CCD_2BD0,
  70         HFC_CCD_B000,
  71         HFC_CCD_B006,
  72         HFC_CCD_B007,
  73         HFC_CCD_B008,
  74         HFC_CCD_B009,
  75         HFC_CCD_B00A,
  76         HFC_CCD_B00B,
  77         HFC_CCD_B00C,
  78         HFC_CCD_B100,
  79         HFC_CCD_B700,
  80         HFC_CCD_B701,
  81         HFC_ASUS_0675,
  82         HFC_BERKOM_A1T,
  83         HFC_BERKOM_TCONCEPT,
  84         HFC_ANIGMA_MC145575,
  85         HFC_ZOLTRIX_2BD0,
  86         HFC_DIGI_DF_M_IOM2_E,
  87         HFC_DIGI_DF_M_E,
  88         HFC_DIGI_DF_M_IOM2_A,
  89         HFC_DIGI_DF_M_A,
  90         HFC_ABOCOM_2BD1,
  91         HFC_SITECOM_DC105V2,
  92 };
  93
  94 struct hfcPCI_hw {
  95         unsigned char           cirm;
  96         unsigned char           ctmt;
  97         unsigned char           clkdel;
  98         unsigned char           states;
  99         unsigned char           conn;
 100         unsigned char           mst_m;
 101         unsigned char           int_m1;
 102         unsigned char           int_m2;
 103         unsigned char           sctrl;
 104         unsigned char           sctrl_r;
 105         unsigned char           sctrl_e;
 106         unsigned char           trm;
 107         unsigned char           fifo_en;
 108         unsigned char           bswapped;
 109         unsigned char           protocol;
 110         int                     nt_timer;
 111         unsigned char __iomem   *pci_io; /* start of PCI IO memory */
 112         dma_addr_t              dmahandle;
 113         void                    *fifos; /* FIFO memory */
 114         int                     last_bfifo_cnt[2];
 115             /* marker saving last b-fifo frame count */
 116         struct timer_list       timer;
 117 };
 118
 119 #define HFC_CFG_MASTER          1
 120 #define HFC_CFG_SLAVE           2
 121 #define HFC_CFG_PCM             3
 122 #define HFC_CFG_2HFC            4
 123 #define HFC_CFG_SLAVEHFC        5
 124 #define HFC_CFG_NEG_F0          6
 125 #define HFC_CFG_SW_DD_DU        7
 126
 127 #define FLG_HFC_TIMER_T1        16
 128 #define FLG_HFC_TIMER_T3        17
 129
 130 #define NT_T1_COUNT     1120    /* number of 3.125ms interrupts (3.5s) */
 131 #define NT_T3_COUNT     31      /* number of 3.125ms interrupts (97 ms) */
 132 #define CLKDEL_TE       0x0e    /* CLKDEL in TE mode */
 133 #define CLKDEL_NT       0x6c    /* CLKDEL in NT mode */
 134
 135
 136 struct hfc_pci {
 137         u_char                  subtype;
 138         u_char                  chanlimit;
 139         u_char                  initdone;
 140         u_long                  cfg;
 141         u_int                   irq;
 142         u_int                   irqcnt;
 143         struct pci_dev          *pdev;
 144         struct hfcPCI_hw        hw;
 145         spinlock_t              lock;   /* card lock */
 146         struct dchannel         dch;
 147         struct bchannel         bch[2];
 148 };
 149
 150 /* Interface functions */
 151 static void
 152 enable_hwirq(struct hfc_pci *hc)
 153 {
 154         hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
 155         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 156 }
 157
 158 static void
 159 disable_hwirq(struct hfc_pci *hc)
 160 {
 161         hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
 162         Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
 163 }
 164
 165 /*
 166  * free hardware resources used by driver
 167  */
 168 static void
 169 release_io_hfcpci(struct hfc_pci *hc)
 170 {
 171         /* disable memory mapped ports + busmaster */
 172         pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
 173         del_timer(&hc->hw.timer);
 174         pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
 175         iounmap(hc->hw.pci_io);
 176 }
 177
 178 /*
 179  * set mode (NT or TE)
 180  */
 181 static void
 182 hfcpci_setmode(struct hfc_pci *hc)
 183 {
 184         if (hc->hw.protocol == ISDN_P_NT_S0) {
 185                 hc->hw.clkdel = CLKDEL_NT;      /* ST-Bit delay for NT-Mode */
 186                 hc->hw.sctrl |= SCTRL_MODE_NT;  /* NT-MODE */
 187                 hc->hw.states = 1;              /* G1 */
 188         } else {
 189                 hc->hw.clkdel = CLKDEL_TE;      /* ST-Bit delay for TE-Mode */
 190                 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
 191                 hc->hw.states = 2;              /* F2 */
 192         }
 193         Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
 194         Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
 195         udelay(10);
 196         Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
 197         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
 198 }
 199
 200 /*
 201  * function called to reset the HFC PCI chip. A complete software reset of chip
 202  * and fifos is done.
 203  */
 204 static void
 205 reset_hfcpci(struct hfc_pci *hc)
 206 {
 207         u_char  val;
 208         int     cnt = 0;
 209
 210         printk(KERN_DEBUG "reset_hfcpci: entered\n");
 211         val = Read_hfc(hc, HFCPCI_CHIP_ID);
 212         printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
 213         /* enable memory mapped ports, disable busmaster */
 214         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
 215         disable_hwirq(hc);
 216         /* enable memory ports + busmaster */
 217         pci_write_config_word(hc->pdev, PCI_COMMAND,
 218             PCI_ENA_MEMIO + PCI_ENA_MASTER);
 219         val = Read_hfc(hc, HFCPCI_STATUS);
 220         printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
 221         hc->hw.cirm = HFCPCI_RESET;     /* Reset On */
 222         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 223         set_current_state(TASK_UNINTERRUPTIBLE);
 224         mdelay(10);                     /* Timeout 10ms */
 225         hc->hw.cirm = 0;                /* Reset Off */
 226         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
 227         val = Read_hfc(hc, HFCPCI_STATUS);
 228         printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
 229         while (cnt < 50000) { /* max 50000 us */
 230                 udelay(5);
 231                 cnt += 5;
 232                 val = Read_hfc(hc, HFCPCI_STATUS);
 233                 if (!(val & 2))
 234                         break;
 235         }
 236         printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
 237
 238         hc->hw.fifo_en = 0x30;  /* only D fifos enabled */
 239
 240         hc->hw.bswapped = 0;    /* no exchange */
 241         hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
 242         hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
 243         hc->hw.sctrl = 0x40;    /* set tx_lo mode, error in datasheet ! */
 244         hc->hw.sctrl_r = 0;
 245         hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE;     /* S/T Auto awake */
 246         hc->hw.mst_m = 0;
 247         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 248                 hc->hw.mst_m |= HFCPCI_MASTER;  /* HFC Master Mode */
 249         if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
 250                 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
 251         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 252         Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
 253         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
 254         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
 255
 256         hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
 257             HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
 258         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 259
 260         /* Clear already pending ints */
 261         val = Read_hfc(hc, HFCPCI_INT_S1);
 262
 263         /* set NT/TE mode */
 264         hfcpci_setmode(hc);
 265
 266         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 267         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
 268
 269         /*
 270          * Init GCI/IOM2 in master mode
 271          * Slots 0 and 1 are set for B-chan 1 and 2
 272          * D- and monitor/CI channel are not enabled
 273          * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
 274          * STIO2 is used as data input, B1+B2 from IOM->ST
 275          * ST B-channel send disabled -> continuous 1s
 276          * The IOM slots are always enabled
 277          */
 278         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
 279                 /* set data flow directions: connect B1,B2: HFC to/from PCM */
 280                 hc->hw.conn = 0x09;
 281         } else {
 282                 hc->hw.conn = 0x36;     /* set data flow directions */
 283                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
 284                         Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
 285                         Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
 286                         Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
 287                         Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
 288                 } else {
 289                         Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
 290                         Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
 291                         Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
 292                         Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
 293                 }
 294         }
 295         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
 296         val = Read_hfc(hc, HFCPCI_INT_S2);
 297 }
 298
 299 /*
 300  * Timer function called when kernel timer expires
 301  */
 302 static void
 303 hfcpci_Timer(struct hfc_pci *hc)
 304 {
 305         hc->hw.timer.expires = jiffies + 75;
 306         /* WD RESET */
 307 /*
 308  *      WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
 309  *      add_timer(&hc->hw.timer);
 310  */
 311 }
 312
 313
 314 /*
 315  * select a b-channel entry matching and active
 316  */
 317 static struct bchannel *
 318 Sel_BCS(struct hfc_pci *hc, int channel)
 319 {
 320         if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
 321                 (hc->bch[0].nr & channel))
 322                 return &hc->bch[0];
 323         else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
 324                 (hc->bch[1].nr & channel))
 325                 return &hc->bch[1];
 326         else
 327                 return NULL;
 328 }
 329
 330 /*
 331  * clear the desired B-channel rx fifo
 332  */
 333 static void
 334 hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
 335 {
 336         u_char          fifo_state;
 337         struct bzfifo   *bzr;
 338
 339         if (fifo) {
 340                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 341                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
 342         } else {
 343                 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 344                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
 345         }
 346         if (fifo_state)
 347                 hc->hw.fifo_en ^= fifo_state;
 348         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 349         hc->hw.last_bfifo_cnt[fifo] = 0;
 350         bzr->f1 = MAX_B_FRAMES;
 351         bzr->f2 = bzr->f1;      /* init F pointers to remain constant */
 352         bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 353         bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
 354             le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
 355         if (fifo_state)
 356                 hc->hw.fifo_en |= fifo_state;
 357         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 358 }
 359
 360 /*
 361  * clear the desired B-channel tx fifo
 362  */
 363 static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
 364 {
 365         u_char          fifo_state;
 366         struct bzfifo   *bzt;
 367
 368         if (fifo) {
 369                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 370                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
 371         } else {
 372                 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 373                 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
 374         }
 375         if (fifo_state)
 376                 hc->hw.fifo_en ^= fifo_state;
 377         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 378         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 379                 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
 380                     "z1(%x) z2(%x) state(%x)\n",
 381                     fifo, bzt->f1, bzt->f2,
 382                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 383                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
 384                     fifo_state);
 385         bzt->f2 = MAX_B_FRAMES;
 386         bzt->f1 = bzt->f2;      /* init F pointers to remain constant */
 387         bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
 388         bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
 389         if (fifo_state)
 390                 hc->hw.fifo_en |= fifo_state;
 391         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
 392         if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
 393                 printk(KERN_DEBUG
 394                     "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
 395                     fifo, bzt->f1, bzt->f2,
 396                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
 397                     le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
 398 }
 399
 400 /*
 401  * read a complete B-frame out of the buffer
 402  */
 403 static void
 404 hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
 405     u_char *bdata, int count)
 406 {
 407         u_char          *ptr, *ptr1, new_f2;
 408         int             maxlen, new_z2;
 409         struct zt       *zp;
 410
 411         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 412                 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
 413         zp = &bz->za[bz->f2];   /* point to Z-Regs */
 414         new_z2 = le16_to_cpu(zp->z2) + count;   /* new position in fifo */
 415         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 416                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 417         new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
 418         if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
 419             (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
 420                 if (bch->debug & DEBUG_HW)
 421                         printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
 422                             "invalid length %d or crc\n", count);
 423 #ifdef ERROR_STATISTIC
 424                 bch->err_inv++;
 425 #endif
 426                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 427                 bz->f2 = new_f2;        /* next buffer */
 428         } else {
 429                 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
 430                 if (!bch->rx_skb) {
 431                         printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 432                         return;
 433                 }
 434                 count -= 3;
 435                 ptr = skb_put(bch->rx_skb, count);
 436
 437                 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
 438                         maxlen = count;         /* complete transfer */
 439                 else
 440                         maxlen = B_FIFO_SIZE + B_SUB_VAL -
 441                             le16_to_cpu(zp->z2);        /* maximum */
 442
 443                 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
 444                     /* start of data */
 445                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 446                 count -= maxlen;
 447
 448                 if (count) {    /* rest remaining */
 449                         ptr += maxlen;
 450                         ptr1 = bdata;   /* start of buffer */
 451                         memcpy(ptr, ptr1, count);       /* rest */
 452                 }
 453                 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
 454                 bz->f2 = new_f2;        /* next buffer */
 455                 recv_Bchannel(bch, MISDN_ID_ANY);
 456         }
 457 }
 458
 459 /*
 460  * D-channel receive procedure
 461  */
 462 static int
 463 receive_dmsg(struct hfc_pci *hc)
 464 {
 465         struct dchannel *dch = &hc->dch;
 466         int             maxlen;
 467         int             rcnt, total;
 468         int             count = 5;
 469         u_char          *ptr, *ptr1;
 470         struct dfifo    *df;
 471         struct zt       *zp;
 472
 473         df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
 474         while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
 475                 zp = &df->za[df->f2 & D_FREG_MASK];
 476                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 477                 if (rcnt < 0)
 478                         rcnt += D_FIFO_SIZE;
 479                 rcnt++;
 480                 if (dch->debug & DEBUG_HW_DCHANNEL)
 481                         printk(KERN_DEBUG
 482                             "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
 483                                 df->f1, df->f2,
 484                                 le16_to_cpu(zp->z1),
 485                                 le16_to_cpu(zp->z2),
 486                                 rcnt);
 487
 488                 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
 489                     (df->data[le16_to_cpu(zp->z1)])) {
 490                         if (dch->debug & DEBUG_HW)
 491                                 printk(KERN_DEBUG
 492                                     "empty_fifo hfcpci paket inv. len "
 493                                     "%d or crc %d\n",
 494                                     rcnt,
 495                                     df->data[le16_to_cpu(zp->z1)]);
 496 #ifdef ERROR_STATISTIC
 497                         cs->err_rx++;
 498 #endif
 499                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 500                             (MAX_D_FRAMES + 1); /* next buffer */
 501                         df->za[df->f2 & D_FREG_MASK].z2 =
 502                             cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) &
 503                             (D_FIFO_SIZE - 1));
 504                 } else {
 505                         dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
 506                         if (!dch->rx_skb) {
 507                                 printk(KERN_WARNING
 508                                     "HFC-PCI: D receive out of memory\n");
 509                                 break;
 510                         }
 511                         total = rcnt;
 512                         rcnt -= 3;
 513                         ptr = skb_put(dch->rx_skb, rcnt);
 514
 515                         if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
 516                                 maxlen = rcnt;  /* complete transfer */
 517                         else
 518                                 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
 519                                     /* maximum */
 520
 521                         ptr1 = df->data + le16_to_cpu(zp->z2);
 522                             /* start of data */
 523                         memcpy(ptr, ptr1, maxlen);      /* copy data */
 524                         rcnt -= maxlen;
 525
 526                         if (rcnt) {     /* rest remaining */
 527                                 ptr += maxlen;
 528                                 ptr1 = df->data;        /* start of buffer */
 529                                 memcpy(ptr, ptr1, rcnt);        /* rest */
 530                         }
 531                         df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
 532                             (MAX_D_FRAMES + 1); /* next buffer */
 533                         df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
 534                             le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
 535                         recv_Dchannel(dch);
 536                 }
 537         }
 538         return 1;
 539 }
 540
 541 /*
 542  * check for transparent receive data and read max one 'poll' size if avail
 543  */
 544 static void
 545 hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *rxbz,
 546         struct bzfifo *txbz, u_char *bdata)
 547 {
 548          __le16 *z1r, *z2r, *z1t, *z2t;
 549         int     new_z2, fcnt_rx, fcnt_tx, maxlen;
 550         u_char  *ptr, *ptr1;
 551
 552         z1r = &rxbz->za[MAX_B_FRAMES].z1;       /* pointer to z reg */
 553         z2r = z1r + 1;
 554         z1t = &txbz->za[MAX_B_FRAMES].z1;
 555         z2t = z1t + 1;
 556
 557         fcnt_rx = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
 558         if (!fcnt_rx)
 559                 return; /* no data avail */
 560
 561         if (fcnt_rx <= 0)
 562                 fcnt_rx += B_FIFO_SIZE; /* bytes actually buffered */
 563         new_z2 = le16_to_cpu(*z2r) + fcnt_rx;   /* new position in fifo */
 564         if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
 565                 new_z2 -= B_FIFO_SIZE;  /* buffer wrap */
 566
 567         if (fcnt_rx > MAX_DATA_SIZE) {  /* flush, if oversized */
 568                 *z2r = cpu_to_le16(new_z2);             /* new position */
 569                 return;
 570         }
 571
 572         fcnt_tx = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
 573         if (fcnt_tx <= 0)
 574                 fcnt_tx += B_FIFO_SIZE;
 575                     /* fcnt_tx contains available bytes in tx-fifo */
 576         fcnt_tx = B_FIFO_SIZE - fcnt_tx;
 577                     /* remaining bytes to send (bytes in tx-fifo) */
 578
 579         bch->rx_skb = mI_alloc_skb(fcnt_rx, GFP_ATOMIC);
 580         if (bch->rx_skb) {
 581                 ptr = skb_put(bch->rx_skb, fcnt_rx);
 582                 if (le16_to_cpu(*z2r) + fcnt_rx <= B_FIFO_SIZE + B_SUB_VAL)
 583                         maxlen = fcnt_rx;       /* complete transfer */
 584                 else
 585                         maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
 586                             /* maximum */
 587
 588                 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
 589                     /* start of data */
 590                 memcpy(ptr, ptr1, maxlen);      /* copy data */
 591                 fcnt_rx -= maxlen;
 592
 593                 if (fcnt_rx) {  /* rest remaining */
 594                         ptr += maxlen;
 595                         ptr1 = bdata;   /* start of buffer */
 596                         memcpy(ptr, ptr1, fcnt_rx);     /* rest */
 597                 }
 598                 recv_Bchannel(bch, fcnt_tx); /* bch, id */
 599         } else
 600                 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
 601
 602         *z2r = cpu_to_le16(new_z2);             /* new position */
 603 }
 604
 605 /*
 606  * B-channel main receive routine
 607  */
 608 static void
 609 main_rec_hfcpci(struct bchannel *bch)
 610 {
 611         struct hfc_pci  *hc = bch->hw;
 612         int             rcnt, real_fifo;
 613         int             receive = 0, count = 5;
 614         struct bzfifo   *txbz, *rxbz;
 615         u_char          *bdata;
 616         struct zt       *zp;
 617
 618         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 619                 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
 620                 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 621                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
 622                 real_fifo = 1;
 623         } else {
 624                 rxbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
 625                 txbz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 626                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
 627                 real_fifo = 0;
 628         }
 629 Begin:
 630         count--;
 631         if (rxbz->f1 != rxbz->f2) {
 632                 if (bch->debug & DEBUG_HW_BCHANNEL)
 633                         printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
 634                             bch->nr, rxbz->f1, rxbz->f2);
 635                 zp = &rxbz->za[rxbz->f2];
 636
 637                 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
 638                 if (rcnt < 0)
 639                         rcnt += B_FIFO_SIZE;
 640                 rcnt++;
 641                 if (bch->debug & DEBUG_HW_BCHANNEL)
 642                         printk(KERN_DEBUG
 643                             "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
 644                             bch->nr, le16_to_cpu(zp->z1),
 645                             le16_to_cpu(zp->z2), rcnt);
 646                 hfcpci_empty_bfifo(bch, rxbz, bdata, rcnt);
 647                 rcnt = rxbz->f1 - rxbz->f2;
 648                 if (rcnt < 0)
 649                         rcnt += MAX_B_FRAMES + 1;
 650                 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
 651                         rcnt = 0;
 652                         hfcpci_clear_fifo_rx(hc, real_fifo);
 653                 }
 654                 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
 655                 if (rcnt > 1)
 656                         receive = 1;
 657                 else
 658                         receive = 0;
 659         } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
 660                 hfcpci_empty_fifo_trans(bch, rxbz, txbz, bdata);
 661                 return;
 662         } else
 663                 receive = 0;
 664         if (count && receive)
 665                 goto Begin;
 666
 667 }
 668
 669 /*
 670  * D-channel send routine
 671  */
 672 static void
 673 hfcpci_fill_dfifo(struct hfc_pci *hc)
 674 {
 675         struct dchannel *dch = &hc->dch;
 676         int             fcnt;
 677         int             count, new_z1, maxlen;
 678         struct dfifo    *df;
 679         u_char          *src, *dst, new_f1;
 680
 681         if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
 682                 printk(KERN_DEBUG "%s\n", __func__);
 683
 684         if (!dch->tx_skb)
 685                 return;
 686         count = dch->tx_skb->len - dch->tx_idx;
 687         if (count <= 0)
 688                 return;
 689         df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
 690
 691         if (dch->debug & DEBUG_HW_DFIFO)
 692                 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
 693                     df->f1, df->f2,
 694                     le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
 695         fcnt = df->f1 - df->f2; /* frame count actually buffered */
 696         if (fcnt < 0)
 697                 fcnt += (MAX_D_FRAMES + 1);     /* if wrap around */
 698         if (fcnt > (MAX_D_FRAMES - 1)) {
 699                 if (dch->debug & DEBUG_HW_DCHANNEL)
 700                         printk(KERN_DEBUG
 701                             "hfcpci_fill_Dfifo more as 14 frames\n");
 702 #ifdef ERROR_STATISTIC
 703                 cs->err_tx++;
 704 #endif
 705                 return;
 706         }
 707         /* now determine free bytes in FIFO buffer */
 708         maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
 709             le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
 710         if (maxlen <= 0)
 711                 maxlen += D_FIFO_SIZE;  /* count now contains available bytes */
 712
 713         if (dch->debug & DEBUG_HW_DCHANNEL)
 714                 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
 715                         count, maxlen);
 716         if (count > maxlen) {
 717                 if (dch->debug & DEBUG_HW_DCHANNEL)
 718                         printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
 719                 return;
 720         }
 721         new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
 722             (D_FIFO_SIZE - 1);
 723         new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
 724         src = dch->tx_skb->data + dch->tx_idx;  /* source pointer */
 725         dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 726         maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
 727             /* end fifo */
 728         if (maxlen > count)
 729                 maxlen = count; /* limit size */
 730         memcpy(dst, src, maxlen);       /* first copy */
 731
 732         count -= maxlen;        /* remaining bytes */
 733         if (count) {
 734                 dst = df->data; /* start of buffer */
 735                 src += maxlen;  /* new position */
 736                 memcpy(dst, src, count);
 737         }
 738         df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 739             /* for next buffer */
 740         df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
 741             /* new pos actual buffer */
 742         df->f1 = new_f1;        /* next frame */
 743         dch->tx_idx = dch->tx_skb->len;
 744 }
 745
 746 /*
 747  * B-channel send routine
 748  */
 749 static void
 750 hfcpci_fill_fifo(struct bchannel *bch)
 751 {
 752         struct hfc_pci  *hc = bch->hw;
 753         int             maxlen, fcnt;
 754         int             count, new_z1;
 755         struct bzfifo   *bz;
 756         u_char          *bdata;
 757         u_char          new_f1, *src, *dst;
 758         __le16 *z1t, *z2t;
 759
 760         if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
 761                 printk(KERN_DEBUG "%s\n", __func__);
 762         if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
 763                 return;
 764         count = bch->tx_skb->len - bch->tx_idx;
 765         if ((bch->nr & 2) && (!hc->hw.bswapped)) {
 766                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
 767                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
 768         } else {
 769                 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
 770                 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
 771         }
 772
 773         if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
 774                 z1t = &bz->za[MAX_B_FRAMES].z1;
 775                 z2t = z1t + 1;
 776                 if (bch->debug & DEBUG_HW_BCHANNEL)
 777                         printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
 778                             "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
 779                             le16_to_cpu(*z1t), le16_to_cpu(*z2t));
 780                 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
 781                 if (fcnt <= 0)
 782                         fcnt += B_FIFO_SIZE;
 783                             /* fcnt contains available bytes in fifo */
 784                 fcnt = B_FIFO_SIZE - fcnt;
 785                     /* remaining bytes to send (bytes in fifo) */
 786
 787                 /* "fill fifo if empty" feature */
 788                 if (test_bit(FLG_FILLEMPTY, &bch->Flags) && !fcnt) {
 789                         /* printk(KERN_DEBUG "%s: buffer empty, so we have "
 790                                 "underrun\n", __func__); */
 791                         /* fill buffer, to prevent future underrun */
 792                         count = HFCPCI_FILLEMPTY;
 793                         new_z1 = le16_to_cpu(*z1t) + count;
 794                            /* new buffer Position */
 795                         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 796                                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 797                         dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
 798                         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
 799                             /* end of fifo */
 800                         if (bch->debug & DEBUG_HW_BFIFO)
 801                                 printk(KERN_DEBUG "hfcpci_FFt fillempty "
 802                                     "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
 803                                     fcnt, maxlen, new_z1, dst);
 804                         fcnt += count;
 805                         if (maxlen > count)
 806                                 maxlen = count;         /* limit size */
 807                         memset(dst, 0x2a, maxlen);      /* first copy */
 808                         count -= maxlen;                /* remaining bytes */
 809                         if (count) {
 810                                 dst = bdata;            /* start of buffer */
 811                                 memset(dst, 0x2a, count);
 812                         }
 813                         *z1t = cpu_to_le16(new_z1);     /* now send data */
 814                 }
 815
 816 next_t_frame:
 817                 count = bch->tx_skb->len - bch->tx_idx;
 818                 /* maximum fill shall be poll*2 */
 819                 if (count > (poll << 1) - fcnt)
 820                         count = (poll << 1) - fcnt;
 821                 if (count <= 0)
 822                         return;
 823                 /* data is suitable for fifo */
 824                 new_z1 = le16_to_cpu(*z1t) + count;
 825                     /* new buffer Position */
 826                 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 827                         new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 828                 src = bch->tx_skb->data + bch->tx_idx;
 829                     /* source pointer */
 830                 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
 831                 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
 832                     /* end of fifo */
 833                 if (bch->debug & DEBUG_HW_BFIFO)
 834                         printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
 835                             "maxl(%d) nz1(%x) dst(%p)\n",
 836                             fcnt, maxlen, new_z1, dst);
 837                 fcnt += count;
 838                 bch->tx_idx += count;
 839                 if (maxlen > count)
 840                         maxlen = count;         /* limit size */
 841                 memcpy(dst, src, maxlen);       /* first copy */
 842                 count -= maxlen;        /* remaining bytes */
 843                 if (count) {
 844                         dst = bdata;    /* start of buffer */
 845                         src += maxlen;  /* new position */
 846                         memcpy(dst, src, count);
 847                 }
 848                 *z1t = cpu_to_le16(new_z1);     /* now send data */
 849                 if (bch->tx_idx < bch->tx_skb->len)
 850                         return;
 851                 /* send confirm, on trans, free on hdlc. */
 852                 if (test_bit(FLG_TRANSPARENT, &bch->Flags))
 853                         confirm_Bsend(bch);
 854                 dev_kfree_skb(bch->tx_skb);
 855                 if (get_next_bframe(bch))
 856                         goto next_t_frame;
 857                 return;
 858         }
 859         if (bch->debug & DEBUG_HW_BCHANNEL)
 860                 printk(KERN_DEBUG
 861                     "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
 862                     __func__, bch->nr, bz->f1, bz->f2,
 863                     bz->za[bz->f1].z1);
 864         fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
 865         if (fcnt < 0)
 866                 fcnt += (MAX_B_FRAMES + 1);     /* if wrap around */
 867         if (fcnt > (MAX_B_FRAMES - 1)) {
 868                 if (bch->debug & DEBUG_HW_BCHANNEL)
 869                         printk(KERN_DEBUG
 870                             "hfcpci_fill_Bfifo more as 14 frames\n");
 871                 return;
 872         }
 873         /* now determine free bytes in FIFO buffer */
 874         maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
 875             le16_to_cpu(bz->za[bz->f1].z1) - 1;
 876         if (maxlen <= 0)
 877                 maxlen += B_FIFO_SIZE;  /* count now contains available bytes */
 878
 879         if (bch->debug & DEBUG_HW_BCHANNEL)
 880                 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
 881                         bch->nr, count, maxlen);
 882
 883         if (maxlen < count) {
 884                 if (bch->debug & DEBUG_HW_BCHANNEL)
 885                         printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
 886                 return;
 887         }
 888         new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
 889             /* new buffer Position */
 890         if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
 891                 new_z1 -= B_FIFO_SIZE;  /* buffer wrap */
 892
 893         new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
 894         src = bch->tx_skb->data + bch->tx_idx;  /* source pointer */
 895         dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
 896         maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
 897             /* end fifo */
 898         if (maxlen > count)
 899                 maxlen = count; /* limit size */
 900         memcpy(dst, src, maxlen);       /* first copy */
 901
 902         count -= maxlen;        /* remaining bytes */
 903         if (count) {
 904                 dst = bdata;    /* start of buffer */
 905                 src += maxlen;  /* new position */
 906                 memcpy(dst, src, count);
 907         }
 908         bz->za[new_f1].z1 = cpu_to_le16(new_z1);        /* for next buffer */
 909         bz->f1 = new_f1;        /* next frame */
 910         dev_kfree_skb(bch->tx_skb);
 911         get_next_bframe(bch);
 912 }
 913
 914
 915
 916 /*
 917  * handle L1 state changes TE
 918  */
 919
 920 static void
 921 ph_state_te(struct dchannel *dch)
 922 {
 923         if (dch->debug)
 924                 printk(KERN_DEBUG "%s: TE newstate %x\n",
 925                         __func__, dch->state);
 926         switch (dch->state) {
 927         case 0:
 928                 l1_event(dch->l1, HW_RESET_IND);
 929                 break;
 930         case 3:
 931                 l1_event(dch->l1, HW_DEACT_IND);
 932                 break;
 933         case 5:
 934         case 8:
 935                 l1_event(dch->l1, ANYSIGNAL);
 936                 break;
 937         case 6:
 938                 l1_event(dch->l1, INFO2);
 939                 break;
 940         case 7:
 941                 l1_event(dch->l1, INFO4_P8);
 942                 break;
 943         }
 944 }
 945
 946 /*
 947  * handle L1 state changes NT
 948  */
 949
 950 static void
 951 handle_nt_timer3(struct dchannel *dch) {
 952         struct hfc_pci  *hc = dch->hw;
 953
 954         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 955         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 956         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 957         hc->hw.nt_timer = 0;
 958         test_and_set_bit(FLG_ACTIVE, &dch->Flags);
 959         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
 960                 hc->hw.mst_m |= HFCPCI_MASTER;
 961         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
 962         _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
 963             MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
 964 }
 965
 966 static void
 967 ph_state_nt(struct dchannel *dch)
 968 {
 969         struct hfc_pci  *hc = dch->hw;
 970
 971         if (dch->debug)
 972                 printk(KERN_DEBUG "%s: NT newstate %x\n",
 973                         __func__, dch->state);
 974         switch (dch->state) {
 975         case 2:
 976                 if (hc->hw.nt_timer < 0) {
 977                         hc->hw.nt_timer = 0;
 978                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 979                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 980                         hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
 981                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 982                         /* Clear already pending ints */
 983                         (void) Read_hfc(hc, HFCPCI_INT_S1);
 984                         Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
 985                         udelay(10);
 986                         Write_hfc(hc, HFCPCI_STATES, 4);
 987                         dch->state = 4;
 988                 } else if (hc->hw.nt_timer == 0) {
 989                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
 990                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
 991                         hc->hw.nt_timer = NT_T1_COUNT;
 992                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
 993                         hc->hw.ctmt |= HFCPCI_TIM3_125;
 994                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
 995                                 HFCPCI_CLTIMER);
 996                         test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
 997                         test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
 998                         /* allow G2 -> G3 transition */
 999                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1000                 } else {
1001                         Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
1002                 }
1003                 break;
1004         case 1:
1005                 hc->hw.nt_timer = 0;
1006                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1007                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1008                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1009                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1010                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1011                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1012                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1013                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1014                 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1015                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1016                 break;
1017         case 4:
1018                 hc->hw.nt_timer = 0;
1019                 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1020                 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1021                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1022                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1023                 break;
1024         case 3:
1025                 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1026                         if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1027                             &dch->Flags)) {
1028                                 handle_nt_timer3(dch);
1029                                 break;
1030                         }
1031                         test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1032                         hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1033                         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1034                         hc->hw.nt_timer = NT_T3_COUNT;
1035                         hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1036                         hc->hw.ctmt |= HFCPCI_TIM3_125;
1037                         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1038                                 HFCPCI_CLTIMER);
1039                 }
1040                 break;
1041         }
1042 }
1043
1044 static void
1045 ph_state(struct dchannel *dch)
1046 {
1047         struct hfc_pci  *hc = dch->hw;
1048
1049         if (hc->hw.protocol == ISDN_P_NT_S0) {
1050                 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1051                     hc->hw.nt_timer < 0)
1052                         handle_nt_timer3(dch);
1053                 else
1054                         ph_state_nt(dch);
1055         } else
1056                 ph_state_te(dch);
1057 }
1058
1059 /*
1060  * Layer 1 callback function
1061  */
1062 static int
1063 hfc_l1callback(struct dchannel *dch, u_int cmd)
1064 {
1065         struct hfc_pci          *hc = dch->hw;
1066
1067         switch (cmd) {
1068         case INFO3_P8:
1069         case INFO3_P10:
1070                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1071                         hc->hw.mst_m |= HFCPCI_MASTER;
1072                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1073                 break;
1074         case HW_RESET_REQ:
1075                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1076                 /* HFC ST 3 */
1077                 udelay(6);
1078                 Write_hfc(hc, HFCPCI_STATES, 3);        /* HFC ST 2 */
1079                 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1080                         hc->hw.mst_m |= HFCPCI_MASTER;
1081                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1082                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1083                    HFCPCI_DO_ACTION);
1084                 l1_event(dch->l1, HW_POWERUP_IND);
1085                 break;
1086         case HW_DEACT_REQ:
1087                 hc->hw.mst_m &= ~HFCPCI_MASTER;
1088                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1089                 skb_queue_purge(&dch->squeue);
1090                 if (dch->tx_skb) {
1091                         dev_kfree_skb(dch->tx_skb);
1092                         dch->tx_skb = NULL;
1093                 }
1094                 dch->tx_idx = 0;
1095                 if (dch->rx_skb) {
1096                         dev_kfree_skb(dch->rx_skb);
1097                         dch->rx_skb = NULL;
1098                 }
1099                 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1100                 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1101                         del_timer(&dch->timer);
1102                 break;
1103         case HW_POWERUP_REQ:
1104                 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1105                 break;
1106         case PH_ACTIVATE_IND:
1107                 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1108                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1109                         GFP_ATOMIC);
1110                 break;
1111         case PH_DEACTIVATE_IND:
1112                 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1113                 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1114                         GFP_ATOMIC);
1115                 break;
1116         default:
1117                 if (dch->debug & DEBUG_HW)
1118                         printk(KERN_DEBUG "%s: unknown command %x\n",
1119                             __func__, cmd);
1120                 return -1;
1121         }
1122         return 0;
1123 }
1124
1125 /*
1126  * Interrupt handler
1127  */
1128 static inline void
1129 tx_birq(struct bchannel *bch)
1130 {
1131         if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1132                 hfcpci_fill_fifo(bch);
1133         else {
1134                 if (bch->tx_skb)
1135                         dev_kfree_skb(bch->tx_skb);
1136                 if (get_next_bframe(bch))
1137                         hfcpci_fill_fifo(bch);
1138         }
1139 }
1140
1141 static inline void
1142 tx_dirq(struct dchannel *dch)
1143 {
1144         if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1145                 hfcpci_fill_dfifo(dch->hw);
1146         else {
1147                 if (dch->tx_skb)
1148                         dev_kfree_skb(dch->tx_skb);
1149                 if (get_next_dframe(dch))
1150                         hfcpci_fill_dfifo(dch->hw);
1151         }
1152 }
1153
1154 static irqreturn_t
1155 hfcpci_int(int intno, void *dev_id)
1156 {
1157         struct hfc_pci  *hc = dev_id;
1158         u_char          exval;
1159         struct bchannel *bch;
1160         u_char          val, stat;
1161
1162         spin_lock(&hc->lock);
1163         if (!(hc->hw.int_m2 & 0x08)) {
1164                 spin_unlock(&hc->lock);
1165                 return IRQ_NONE; /* not initialised */
1166         }
1167         stat = Read_hfc(hc, HFCPCI_STATUS);
1168         if (HFCPCI_ANYINT & stat) {
1169                 val = Read_hfc(hc, HFCPCI_INT_S1);
1170                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1171                         printk(KERN_DEBUG
1172                             "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1173         } else {
1174                 /* shared */
1175                 spin_unlock(&hc->lock);
1176                 return IRQ_NONE;
1177         }
1178         hc->irqcnt++;
1179
1180         if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1181                 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1182         val &= hc->hw.int_m1;
1183         if (val & 0x40) {       /* state machine irq */
1184                 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1185                 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1186                         printk(KERN_DEBUG "ph_state chg %d->%d\n",
1187                                 hc->dch.state, exval);
1188                 hc->dch.state = exval;
1189                 schedule_event(&hc->dch, FLG_PHCHANGE);
1190                 val &= ~0x40;
1191         }
1192         if (val & 0x80) {       /* timer irq */
1193                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1194                         if ((--hc->hw.nt_timer) < 0)
1195                                 schedule_event(&hc->dch, FLG_PHCHANGE);
1196                 }
1197                 val &= ~0x80;
1198                 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1199         }
1200         if (val & 0x08) {       /* B1 rx */
1201                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1202                 if (bch)
1203                         main_rec_hfcpci(bch);
1204                 else if (hc->dch.debug)
1205                         printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1206         }
1207         if (val & 0x10) {       /* B2 rx */
1208                 bch = Sel_BCS(hc, 2);
1209                 if (bch)
1210                         main_rec_hfcpci(bch);
1211                 else if (hc->dch.debug)
1212                         printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1213         }
1214         if (val & 0x01) {       /* B1 tx */
1215                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1216                 if (bch)
1217                         tx_birq(bch);
1218                 else if (hc->dch.debug)
1219                         printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1220         }
1221         if (val & 0x02) {       /* B2 tx */
1222                 bch = Sel_BCS(hc, 2);
1223                 if (bch)
1224                         tx_birq(bch);
1225                 else if (hc->dch.debug)
1226                         printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1227         }
1228         if (val & 0x20)         /* D rx */
1229                 receive_dmsg(hc);
1230         if (val & 0x04) {       /* D tx */
1231                 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1232                         del_timer(&hc->dch.timer);
1233                 tx_dirq(&hc->dch);
1234         }
1235         spin_unlock(&hc->lock);
1236         return IRQ_HANDLED;
1237 }
1238
1239 /*
1240  * timer callback for D-chan busy resolution. Currently no function
1241  */
1242 static void
1243 hfcpci_dbusy_timer(struct hfc_pci *hc)
1244 {
1245 }
1246
1247 /*
1248  * activate/deactivate hardware for selected channels and mode
1249  */
1250 static int
1251 mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1252 {
1253         struct hfc_pci  *hc = bch->hw;
1254         int             fifo2;
1255         u_char          rx_slot = 0, tx_slot = 0, pcm_mode;
1256
1257         if (bch->debug & DEBUG_HW_BCHANNEL)
1258                 printk(KERN_DEBUG
1259                     "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1260                     bch->state, protocol, bch->nr, bc);
1261
1262         fifo2 = bc;
1263         pcm_mode = (bc>>24) & 0xff;
1264         if (pcm_mode) { /* PCM SLOT USE */
1265                 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1266                         printk(KERN_WARNING
1267                             "%s: pcm channel id without HFC_CFG_PCM\n",
1268                             __func__);
1269                 rx_slot = (bc>>8) & 0xff;
1270                 tx_slot = (bc>>16) & 0xff;
1271                 bc = bc & 0xff;
1272         } else if (test_bit(HFC_CFG_PCM, &hc->cfg) && (protocol > ISDN_P_NONE))
1273                 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1274                     __func__);
1275         if (hc->chanlimit > 1) {
1276                 hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1277                 hc->hw.sctrl_e &= ~0x80;
1278         } else {
1279                 if (bc & 2) {
1280                         if (protocol != ISDN_P_NONE) {
1281                                 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1282                                 hc->hw.sctrl_e |= 0x80;
1283                         } else {
1284                                 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1285                                 hc->hw.sctrl_e &= ~0x80;
1286                         }
1287                         fifo2 = 1;
1288                 } else {
1289                         hc->hw.bswapped = 0;    /* B1 and B2 normal mode */
1290                         hc->hw.sctrl_e &= ~0x80;
1291                 }
1292         }
1293         switch (protocol) {
1294         case (-1): /* used for init */
1295                 bch->state = -1;
1296                 bch->nr = bc;
1297         case (ISDN_P_NONE):
1298                 if (bch->state == ISDN_P_NONE)
1299                         return 0;
1300                 if (bc & 2) {
1301                         hc->hw.sctrl &= ~SCTRL_B2_ENA;
1302                         hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1303                 } else {
1304                         hc->hw.sctrl &= ~SCTRL_B1_ENA;
1305                         hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1306                 }
1307                 if (fifo2 & 2) {
1308                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1309                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1310                                 HFCPCI_INTS_B2REC);
1311                 } else {
1312                         hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1313                         hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1314                                 HFCPCI_INTS_B1REC);
1315                 }
1316 #ifdef REVERSE_BITORDER
1317                 if (bch->nr & 2)
1318                         hc->hw.cirm &= 0x7f;
1319                 else
1320                         hc->hw.cirm &= 0xbf;
1321 #endif
1322                 bch->state = ISDN_P_NONE;
1323                 bch->nr = bc;
1324                 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1325                 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1326                 break;
1327         case (ISDN_P_B_RAW):
1328                 bch->state = protocol;
1329                 bch->nr = bc;
1330                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1331                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1332                 if (bc & 2) {
1333                         hc->hw.sctrl |= SCTRL_B2_ENA;
1334                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1335 #ifdef REVERSE_BITORDER
1336                         hc->hw.cirm |= 0x80;
1337 #endif
1338                 } else {
1339                         hc->hw.sctrl |= SCTRL_B1_ENA;
1340                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1341 #ifdef REVERSE_BITORDER
1342                         hc->hw.cirm |= 0x40;
1343 #endif
1344                 }
1345                 if (fifo2 & 2) {
1346                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1347                         if (!tics)
1348                                 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1349                                     HFCPCI_INTS_B2REC);
1350                         hc->hw.ctmt |= 2;
1351                         hc->hw.conn &= ~0x18;
1352                 } else {
1353                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1354                         if (!tics)
1355                                 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1356                                     HFCPCI_INTS_B1REC);
1357                         hc->hw.ctmt |= 1;
1358                         hc->hw.conn &= ~0x03;
1359                 }
1360                 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1361                 break;
1362         case (ISDN_P_B_HDLC):
1363                 bch->state = protocol;
1364                 bch->nr = bc;
1365                 hfcpci_clear_fifo_rx(hc, (fifo2 & 2) ? 1 : 0);
1366                 hfcpci_clear_fifo_tx(hc, (fifo2 & 2) ? 1 : 0);
1367                 if (bc & 2) {
1368                         hc->hw.sctrl |= SCTRL_B2_ENA;
1369                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1370                 } else {
1371                         hc->hw.sctrl |= SCTRL_B1_ENA;
1372                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1373                 }
1374                 if (fifo2 & 2) {
1375                         hc->hw.last_bfifo_cnt[1] = 0;
1376                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1377                         hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1378                             HFCPCI_INTS_B2REC);
1379                         hc->hw.ctmt &= ~2;
1380                         hc->hw.conn &= ~0x18;
1381                 } else {
1382                         hc->hw.last_bfifo_cnt[0] = 0;
1383                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1384                         hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1385                             HFCPCI_INTS_B1REC);
1386                         hc->hw.ctmt &= ~1;
1387                         hc->hw.conn &= ~0x03;
1388                 }
1389                 test_and_set_bit(FLG_HDLC, &bch->Flags);
1390                 break;
1391         default:
1392                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1393                 return -ENOPROTOOPT;
1394         }
1395         if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1396                 if ((protocol == ISDN_P_NONE) ||
1397                         (protocol == -1)) {     /* init case */
1398                         rx_slot = 0;
1399                         tx_slot = 0;
1400                 } else {
1401                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1402                                 rx_slot |= 0xC0;
1403                                 tx_slot |= 0xC0;
1404                         } else {
1405                                 rx_slot |= 0x80;
1406                                 tx_slot |= 0x80;
1407                         }
1408                 }
1409                 if (bc & 2) {
1410                         hc->hw.conn &= 0xc7;
1411                         hc->hw.conn |= 0x08;
1412                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1413                                 __func__, tx_slot);
1414                         printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1415                                 __func__, rx_slot);
1416                         Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1417                         Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1418                 } else {
1419                         hc->hw.conn &= 0xf8;
1420                         hc->hw.conn |= 0x01;
1421                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1422                                 __func__, tx_slot);
1423                         printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1424                                 __func__, rx_slot);
1425                         Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1426                         Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1427                 }
1428         }
1429         Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1430         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1431         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1432         Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1433         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1434         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1435         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1436 #ifdef REVERSE_BITORDER
1437         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1438 #endif
1439         return 0;
1440 }
1441
1442 static int
1443 set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1444 {
1445         struct hfc_pci  *hc = bch->hw;
1446
1447         if (bch->debug & DEBUG_HW_BCHANNEL)
1448                 printk(KERN_DEBUG
1449                     "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1450                     bch->state, protocol, bch->nr, chan);
1451         if (bch->nr != chan) {
1452                 printk(KERN_DEBUG
1453                     "HFCPCI rxtest wrong channel parameter %x/%x\n",
1454                     bch->nr, chan);
1455                 return -EINVAL;
1456         }
1457         switch (protocol) {
1458         case (ISDN_P_B_RAW):
1459                 bch->state = protocol;
1460                 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1461                 if (chan & 2) {
1462                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1463                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1464                         if (!tics)
1465                                 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1466                         hc->hw.ctmt |= 2;
1467                         hc->hw.conn &= ~0x18;
1468 #ifdef REVERSE_BITORDER
1469                         hc->hw.cirm |= 0x80;
1470 #endif
1471                 } else {
1472                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1473                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1474                         if (!tics)
1475                                 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1476                         hc->hw.ctmt |= 1;
1477                         hc->hw.conn &= ~0x03;
1478 #ifdef REVERSE_BITORDER
1479                         hc->hw.cirm |= 0x40;
1480 #endif
1481                 }
1482                 break;
1483         case (ISDN_P_B_HDLC):
1484                 bch->state = protocol;
1485                 hfcpci_clear_fifo_rx(hc, (chan & 2) ? 1 : 0);
1486                 if (chan & 2) {
1487                         hc->hw.sctrl_r |= SCTRL_B2_ENA;
1488                         hc->hw.last_bfifo_cnt[1] = 0;
1489                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1490                         hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1491                         hc->hw.ctmt &= ~2;
1492                         hc->hw.conn &= ~0x18;
1493                 } else {
1494                         hc->hw.sctrl_r |= SCTRL_B1_ENA;
1495                         hc->hw.last_bfifo_cnt[0] = 0;
1496                         hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1497                         hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1498                         hc->hw.ctmt &= ~1;
1499                         hc->hw.conn &= ~0x03;
1500                 }
1501                 break;
1502         default:
1503                 printk(KERN_DEBUG "prot not known %x\n", protocol);
1504                 return -ENOPROTOOPT;
1505         }
1506         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1507         Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1508         Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1509         Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1510         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1511 #ifdef REVERSE_BITORDER
1512         Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1513 #endif
1514         return 0;
1515 }
1516
1517 static void
1518 deactivate_bchannel(struct bchannel *bch)
1519 {
1520         struct hfc_pci  *hc = bch->hw;
1521         u_long          flags;
1522
1523         spin_lock_irqsave(&hc->lock, flags);
1524         mISDN_clear_bchannel(bch);
1525         mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1526         spin_unlock_irqrestore(&hc->lock, flags);
1527 }
1528
1529 /*
1530  * Layer 1 B-channel hardware access
1531  */
1532 static int
1533 channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1534 {
1535         int     ret = 0;
1536
1537         switch (cq->op) {
1538         case MISDN_CTRL_GETOP:
1539                 cq->op = MISDN_CTRL_FILL_EMPTY;
1540                 break;
1541         case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
1542                 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
1543                 if (debug & DEBUG_HW_OPEN)
1544                         printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
1545                                 "off=%d)\n", __func__, bch->nr, !!cq->p1);
1546                 break;
1547         default:
1548                 printk(KERN_WARNING "%s: unknown Op %x\n", __func__, cq->op);
1549                 ret = -EINVAL;
1550                 break;
1551         }
1552         return ret;
1553 }
1554 static int
1555 hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1556 {
1557         struct bchannel *bch = container_of(ch, struct bchannel, ch);
1558         struct hfc_pci  *hc = bch->hw;
1559         int             ret = -EINVAL;
1560         u_long          flags;
1561
1562         if (bch->debug & DEBUG_HW)
1563                 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1564         switch (cmd) {
1565         case HW_TESTRX_RAW:
1566                 spin_lock_irqsave(&hc->lock, flags);
1567                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1568                 spin_unlock_irqrestore(&hc->lock, flags);
1569                 break;
1570         case HW_TESTRX_HDLC:
1571                 spin_lock_irqsave(&hc->lock, flags);
1572                 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1573                 spin_unlock_irqrestore(&hc->lock, flags);
1574                 break;
1575         case HW_TESTRX_OFF:
1576                 spin_lock_irqsave(&hc->lock, flags);
1577                 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1578                 spin_unlock_irqrestore(&hc->lock, flags);
1579                 ret = 0;
1580                 break;
1581         case CLOSE_CHANNEL:
1582                 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1583                 if (test_bit(FLG_ACTIVE, &bch->Flags))
1584                         deactivate_bchannel(bch);
1585                 ch->protocol = ISDN_P_NONE;
1586                 ch->peer = NULL;
1587                 module_put(THIS_MODULE);
1588                 ret = 0;
1589                 break;
1590         case CONTROL_CHANNEL:
1591                 ret = channel_bctrl(bch, arg);
1592                 break;
1593         default:
1594                 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1595                         __func__, cmd);
1596         }
1597         return ret;
1598 }
1599
1600 /*
1601  * Layer2 -> Layer 1 Dchannel data
1602  */
1603 static int
1604 hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1605 {
1606         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1607         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1608         struct hfc_pci          *hc = dch->hw;
1609         int                     ret = -EINVAL;
1610         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1611         unsigned int            id;
1612         u_long                  flags;
1613
1614         switch (hh->prim) {
1615         case PH_DATA_REQ:
1616                 spin_lock_irqsave(&hc->lock, flags);
1617                 ret = dchannel_senddata(dch, skb);
1618                 if (ret > 0) { /* direct TX */
1619                         id = hh->id; /* skb can be freed */
1620                         hfcpci_fill_dfifo(dch->hw);
1621                         ret = 0;
1622                         spin_unlock_irqrestore(&hc->lock, flags);
1623                         queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1624                 } else
1625                         spin_unlock_irqrestore(&hc->lock, flags);
1626                 return ret;
1627         case PH_ACTIVATE_REQ:
1628                 spin_lock_irqsave(&hc->lock, flags);
1629                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1630                         ret = 0;
1631                         if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1632                                 hc->hw.mst_m |= HFCPCI_MASTER;
1633                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1634                         if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1635                                 spin_unlock_irqrestore(&hc->lock, flags);
1636                                 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1637                                     MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1638                                 break;
1639                         }
1640                         test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1641                         Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1642                             HFCPCI_DO_ACTION | 1);
1643                 } else
1644                         ret = l1_event(dch->l1, hh->prim);
1645                 spin_unlock_irqrestore(&hc->lock, flags);
1646                 break;
1647         case PH_DEACTIVATE_REQ:
1648                 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1649                 spin_lock_irqsave(&hc->lock, flags);
1650                 if (hc->hw.protocol == ISDN_P_NT_S0) {
1651                         /* prepare deactivation */
1652                         Write_hfc(hc, HFCPCI_STATES, 0x40);
1653                         skb_queue_purge(&dch->squeue);
1654                         if (dch->tx_skb) {
1655                                 dev_kfree_skb(dch->tx_skb);
1656                                 dch->tx_skb = NULL;
1657                         }
1658                         dch->tx_idx = 0;
1659                         if (dch->rx_skb) {
1660                                 dev_kfree_skb(dch->rx_skb);
1661                                 dch->rx_skb = NULL;
1662                         }
1663                         test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1664                         if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1665                                 del_timer(&dch->timer);
1666 #ifdef FIXME
1667                         if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1668                                 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1669 #endif
1670                         hc->hw.mst_m &= ~HFCPCI_MASTER;
1671                         Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1672                         ret = 0;
1673                 } else {
1674                         ret = l1_event(dch->l1, hh->prim);
1675                 }
1676                 spin_unlock_irqrestore(&hc->lock, flags);
1677                 break;
1678         }
1679         if (!ret)
1680                 dev_kfree_skb(skb);
1681         return ret;
1682 }
1683
1684 /*
1685  * Layer2 -> Layer 1 Bchannel data
1686  */
1687 static int
1688 hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1689 {
1690         struct bchannel         *bch = container_of(ch, struct bchannel, ch);
1691         struct hfc_pci          *hc = bch->hw;
1692         int                     ret = -EINVAL;
1693         struct mISDNhead        *hh = mISDN_HEAD_P(skb);
1694         unsigned int            id;
1695         u_long                  flags;
1696
1697         switch (hh->prim) {
1698         case PH_DATA_REQ:
1699                 spin_lock_irqsave(&hc->lock, flags);
1700                 ret = bchannel_senddata(bch, skb);
1701                 if (ret > 0) { /* direct TX */
1702                         id = hh->id; /* skb can be freed */
1703                         hfcpci_fill_fifo(bch);
1704                         ret = 0;
1705                         spin_unlock_irqrestore(&hc->lock, flags);
1706                         if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1707                                 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1708                 } else
1709                         spin_unlock_irqrestore(&hc->lock, flags);
1710                 return ret;
1711         case PH_ACTIVATE_REQ:
1712                 spin_lock_irqsave(&hc->lock, flags);
1713                 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1714                         ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1715                 else
1716                         ret = 0;
1717                 spin_unlock_irqrestore(&hc->lock, flags);
1718                 if (!ret)
1719                         _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1720                                 NULL, GFP_KERNEL);
1721                 break;
1722         case PH_DEACTIVATE_REQ:
1723                 deactivate_bchannel(bch);
1724                 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1725                         NULL, GFP_KERNEL);
1726                 ret = 0;
1727                 break;
1728         }
1729         if (!ret)
1730                 dev_kfree_skb(skb);
1731         return ret;
1732 }
1733
1734 /*
1735  * called for card init message
1736  */
1737
1738 static void
1739 inithfcpci(struct hfc_pci *hc)
1740 {
1741         printk(KERN_DEBUG "inithfcpci: entered\n");
1742         hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1743         hc->dch.timer.data = (long) &hc->dch;
1744         init_timer(&hc->dch.timer);
1745         hc->chanlimit = 2;
1746         mode_hfcpci(&hc->bch[0], 1, -1);
1747         mode_hfcpci(&hc->bch[1], 2, -1);
1748 }
1749
1750
1751 static int
1752 init_card(struct hfc_pci *hc)
1753 {
1754         int     cnt = 3;
1755         u_long  flags;
1756
1757         printk(KERN_DEBUG "init_card: entered\n");
1758
1759
1760         spin_lock_irqsave(&hc->lock, flags);
1761         disable_hwirq(hc);
1762         spin_unlock_irqrestore(&hc->lock, flags);
1763         if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1764                 printk(KERN_WARNING
1765                     "mISDN: couldn't get interrupt %d\n", hc->irq);
1766                 return -EIO;
1767         }
1768         spin_lock_irqsave(&hc->lock, flags);
1769         reset_hfcpci(hc);
1770         while (cnt) {
1771                 inithfcpci(hc);
1772                 /*
1773                  * Finally enable IRQ output
1774                  * this is only allowed, if an IRQ routine is already
1775                  * established for this HFC, so don't do that earlier
1776                  */
1777                 enable_hwirq(hc);
1778                 spin_unlock_irqrestore(&hc->lock, flags);
1779                 /* Timeout 80ms */
1780                 current->state = TASK_UNINTERRUPTIBLE;
1781                 schedule_timeout((80*HZ)/1000);
1782                 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1783                         hc->irq, hc->irqcnt);
1784                 /* now switch timer interrupt off */
1785                 spin_lock_irqsave(&hc->lock, flags);
1786                 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1787                 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1788                 /* reinit mode reg */
1789                 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1790                 if (!hc->irqcnt) {
1791                         printk(KERN_WARNING
1792                             "HFC PCI: IRQ(%d) getting no interrupts "
1793                             "during init %d\n", hc->irq, 4 - cnt);
1794                         if (cnt == 1)
1795                                 break;
1796                         else {
1797                                 reset_hfcpci(hc);
1798                                 cnt--;
1799                         }
1800                 } else {
1801                         spin_unlock_irqrestore(&hc->lock, flags);
1802                         hc->initdone = 1;
1803                         return 0;
1804                 }
1805         }
1806         disable_hwirq(hc);
1807         spin_unlock_irqrestore(&hc->lock, flags);
1808         free_irq(hc->irq, hc);
1809         return -EIO;
1810 }
1811
1812 static int
1813 channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1814 {
1815         int     ret = 0;
1816         u_char  slot;
1817
1818         switch (cq->op) {
1819         case MISDN_CTRL_GETOP:
1820                 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1821                     MISDN_CTRL_DISCONNECT;
1822                 break;
1823         case MISDN_CTRL_LOOP:
1824                 /* channel 0 disabled loop */
1825                 if (cq->channel < 0 || cq->channel > 2) {
1826                         ret = -EINVAL;
1827                         break;
1828                 }
1829                 if (cq->channel & 1) {
1830                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1831                                 slot = 0xC0;
1832                         else
1833                                 slot = 0x80;
1834                         printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1835                             __func__, slot);
1836                         Write_hfc(hc, HFCPCI_B1_SSL, slot);
1837                         Write_hfc(hc, HFCPCI_B1_RSL, slot);
1838                         hc->hw.conn = (hc->hw.conn & ~7) | 6;
1839                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1840                 }
1841                 if (cq->channel & 2) {
1842                         if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1843                                 slot = 0xC1;
1844                         else
1845                                 slot = 0x81;
1846                         printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1847                             __func__, slot);
1848                         Write_hfc(hc, HFCPCI_B2_SSL, slot);
1849                         Write_hfc(hc, HFCPCI_B2_RSL, slot);
1850                         hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1851                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1852                 }
1853                 if (cq->channel & 3)
1854                         hc->hw.trm |= 0x80;     /* enable IOM-loop */
1855                 else {
1856                         hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1857                         Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1858                         hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1859                 }
1860                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1861                 break;
1862         case MISDN_CTRL_CONNECT:
1863                 if (cq->channel == cq->p1) {
1864                         ret = -EINVAL;
1865                         break;
1866                 }
1867                 if (cq->channel < 1 || cq->channel > 2 ||
1868                     cq->p1 < 1 || cq->p1 > 2) {
1869                         ret = -EINVAL;
1870                         break;
1871                 }
1872                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1873                         slot = 0xC0;
1874                 else
1875                         slot = 0x80;
1876                 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1877                     __func__, slot);
1878                 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1879                 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1880                 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1881                         slot = 0xC1;
1882                 else
1883                         slot = 0x81;
1884                 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1885                     __func__, slot);
1886                 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1887                 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1888                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1889                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1890                 hc->hw.trm |= 0x80;
1891                 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1892                 break;
1893         case MISDN_CTRL_DISCONNECT:
1894                 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1895                 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1896                 hc->hw.trm &= 0x7f;     /* disable IOM-loop */
1897                 break;
1898         default:
1899                 printk(KERN_WARNING "%s: unknown Op %x\n",
1900                     __func__, cq->op);
1901                 ret = -EINVAL;
1902                 break;
1903         }
1904         return ret;
1905 }
1906
1907 static int
1908 open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1909     struct channel_req *rq)
1910 {
1911         int err = 0;
1912
1913         if (debug & DEBUG_HW_OPEN)
1914                 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1915                     hc->dch.dev.id, __builtin_return_address(0));
1916         if (rq->protocol == ISDN_P_NONE)
1917                 return -EINVAL;
1918         if (rq->adr.channel == 1) {
1919                 /* TODO: E-Channel */
1920                 return -EINVAL;
1921         }
1922         if (!hc->initdone) {
1923                 if (rq->protocol == ISDN_P_TE_S0) {
1924                         err = create_l1(&hc->dch, hfc_l1callback);
1925                         if (err)
1926                                 return err;
1927                 }
1928                 hc->hw.protocol = rq->protocol;
1929                 ch->protocol = rq->protocol;
1930                 err = init_card(hc);
1931                 if (err)
1932                         return err;
1933         } else {
1934                 if (rq->protocol != ch->protocol) {
1935                         if (hc->hw.protocol == ISDN_P_TE_S0)
1936                                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1937                         if (rq->protocol == ISDN_P_TE_S0) {
1938                                 err = create_l1(&hc->dch, hfc_l1callback);
1939                                 if (err)
1940                                         return err;
1941                         }
1942                         hc->hw.protocol = rq->protocol;
1943                         ch->protocol = rq->protocol;
1944                         hfcpci_setmode(hc);
1945                 }
1946         }
1947
1948         if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1949             ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1950                 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1951                     0, NULL, GFP_KERNEL);
1952         }
1953         rq->ch = ch;
1954         if (!try_module_get(THIS_MODULE))
1955                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1956         return 0;
1957 }
1958
1959 static int
1960 open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1961 {
1962         struct bchannel         *bch;
1963
1964         if (rq->adr.channel > 2)
1965                 return -EINVAL;
1966         if (rq->protocol == ISDN_P_NONE)
1967                 return -EINVAL;
1968         bch = &hc->bch[rq->adr.channel - 1];
1969         if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1970                 return -EBUSY; /* b-channel can be only open once */
1971         test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1972         bch->ch.protocol = rq->protocol;
1973         rq->ch = &bch->ch; /* TODO: E-channel */
1974         if (!try_module_get(THIS_MODULE))
1975                 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1976         return 0;
1977 }
1978
1979 /*
1980  * device control function
1981  */
1982 static int
1983 hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1984 {
1985         struct mISDNdevice      *dev = container_of(ch, struct mISDNdevice, D);
1986         struct dchannel         *dch = container_of(dev, struct dchannel, dev);
1987         struct hfc_pci          *hc = dch->hw;
1988         struct channel_req      *rq;
1989         int                     err = 0;
1990
1991         if (dch->debug & DEBUG_HW)
1992                 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1993                     __func__, cmd, arg);
1994         switch (cmd) {
1995         case OPEN_CHANNEL:
1996                 rq = arg;
1997                 if ((rq->protocol == ISDN_P_TE_S0) ||
1998                     (rq->protocol == ISDN_P_NT_S0))
1999                         err = open_dchannel(hc, ch, rq);
2000                 else
2001                         err = open_bchannel(hc, rq);
2002                 break;
2003         case CLOSE_CHANNEL:
2004                 if (debug & DEBUG_HW_OPEN)
2005                         printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
2006                             __func__, hc->dch.dev.id,
2007                             __builtin_return_address(0));
2008                 module_put(THIS_MODULE);
2009                 break;
2010         case CONTROL_CHANNEL:
2011                 err = channel_ctrl(hc, arg);
2012                 break;
2013         default:
2014                 if (dch->debug & DEBUG_HW)
2015                         printk(KERN_DEBUG "%s: unknown command %x\n",
2016                             __func__, cmd);
2017                 return -EINVAL;
2018         }
2019         return err;
2020 }
2021
2022 static int
2023 setup_hw(struct hfc_pci *hc)
2024 {
2025         void    *buffer;
2026
2027         printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
2028         hc->hw.cirm = 0;
2029         hc->dch.state = 0;
2030         pci_set_master(hc->pdev);
2031         if (!hc->irq) {
2032                 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2033                 return 1;
2034         }
2035         hc->hw.pci_io =
2036                 (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
2037
2038         if (!hc->hw.pci_io) {
2039                 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2040                 return 1;
2041         }
2042         /* Allocate memory for FIFOS */
2043         /* the memory needs to be on a 32k boundary within the first 4G */
2044         pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2045         buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2046         /* We silently assume the address is okay if nonzero */
2047         if (!buffer) {
2048                 printk(KERN_WARNING
2049                     "HFC-PCI: Error allocating memory for FIFO!\n");
2050                 return 1;
2051         }
2052         hc->hw.fifos = buffer;
2053         pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2054         hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2055         printk(KERN_INFO
2056                 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2057                 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
2058                 (u_long) hc->hw.dmahandle, hc->irq, HZ);
2059         /* enable memory mapped ports, disable busmaster */
2060         pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2061         hc->hw.int_m2 = 0;
2062         disable_hwirq(hc);
2063         hc->hw.int_m1 = 0;
2064         Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2065         /* At this point the needed PCI config is done */
2066         /* fifos are still not enabled */
2067         hc->hw.timer.function = (void *) hfcpci_Timer;
2068         hc->hw.timer.data = (long) hc;
2069         init_timer(&hc->hw.timer);
2070         /* default PCM master */
2071         test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2072         return 0;
2073 }
2074
2075 static void
2076 release_card(struct hfc_pci *hc) {
2077         u_long  flags;
2078
2079         spin_lock_irqsave(&hc->lock, flags);
2080         hc->hw.int_m2 = 0; /* interrupt output off ! */
2081         disable_hwirq(hc);
2082         mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2083         mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2084         if (hc->dch.timer.function != NULL) {
2085                 del_timer(&hc->dch.timer);
2086                 hc->dch.timer.function = NULL;
2087         }
2088         spin_unlock_irqrestore(&hc->lock, flags);
2089         if (hc->hw.protocol == ISDN_P_TE_S0)
2090                 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2091         if (hc->initdone)
2092                 free_irq(hc->irq, hc);
2093         release_io_hfcpci(hc); /* must release after free_irq! */
2094         mISDN_unregister_device(&hc->dch.dev);
2095         mISDN_freebchannel(&hc->bch[1]);
2096         mISDN_freebchannel(&hc->bch[0]);
2097         mISDN_freedchannel(&hc->dch);
2098         pci_set_drvdata(hc->pdev, NULL);
2099         kfree(hc);
2100 }
2101
2102 static int
2103 setup_card(struct hfc_pci *card)
2104 {
2105         int             err = -EINVAL;
2106         u_int           i;
2107         char            name[MISDN_MAX_IDLEN];
2108
2109         card->dch.debug = debug;
2110         spin_lock_init(&card->lock);
2111         mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2112         card->dch.hw = card;
2113         card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2114         card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2115             (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2116         card->dch.dev.D.send = hfcpci_l2l1D;
2117         card->dch.dev.D.ctrl = hfc_dctrl;
2118         card->dch.dev.nrbchan = 2;
2119         for (i = 0; i < 2; i++) {
2120                 card->bch[i].nr = i + 1;
2121                 set_channelmap(i + 1, card->dch.dev.channelmap);
2122                 card->bch[i].debug = debug;
2123                 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM);
2124                 card->bch[i].hw = card;
2125                 card->bch[i].ch.send = hfcpci_l2l1B;
2126                 card->bch[i].ch.ctrl = hfc_bctrl;
2127                 card->bch[i].ch.nr = i + 1;
2128                 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2129         }
2130         err = setup_hw(card);
2131         if (err)
2132                 goto error;
2133         snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2134         err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
2135         if (err)
2136                 goto error;
2137         HFC_cnt++;
2138         printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2139         return 0;
2140 error:
2141         mISDN_freebchannel(&card->bch[1]);
2142         mISDN_freebchannel(&card->bch[0]);
2143         mISDN_freedchannel(&card->dch);
2144         kfree(card);
2145         return err;
2146 }
2147
2148 /* private data in the PCI devices list */
2149 struct _hfc_map {
2150         u_int   subtype;
2151         u_int   flag;
2152         char    *name;
2153 };
2154
2155 static const struct _hfc_map hfc_map[] =
2156 {
2157         {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2158         {HFC_CCD_B000, 0, "Billion B000"},
2159         {HFC_CCD_B006, 0, "Billion B006"},
2160         {HFC_CCD_B007, 0, "Billion B007"},
2161         {HFC_CCD_B008, 0, "Billion B008"},
2162         {HFC_CCD_B009, 0, "Billion B009"},
2163         {HFC_CCD_B00A, 0, "Billion B00A"},
2164         {HFC_CCD_B00B, 0, "Billion B00B"},
2165         {HFC_CCD_B00C, 0, "Billion B00C"},
2166         {HFC_CCD_B100, 0, "Seyeon B100"},
2167         {HFC_CCD_B700, 0, "Primux II S0 B700"},
2168         {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2169         {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2170         {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2171         {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2172         {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2173         {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2174         {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2175         {HFC_DIGI_DF_M_IOM2_E, 0,
2176             "Digi International DataFire Micro V IOM2 (Europe)"},
2177         {HFC_DIGI_DF_M_E, 0,
2178             "Digi International DataFire Micro V (Europe)"},
2179         {HFC_DIGI_DF_M_IOM2_A, 0,
2180             "Digi International DataFire Micro V IOM2 (North America)"},
2181         {HFC_DIGI_DF_M_A, 0,
2182             "Digi International DataFire Micro V (North America)"},
2183         {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2184         {},
2185 };
2186
2187 static struct pci_device_id hfc_ids[] =
2188 {
2189         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_2BD0),
2190                 (unsigned long) &hfc_map[0] },
2191         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B000),
2192                 (unsigned long) &hfc_map[1] },
2193         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B006),
2194                 (unsigned long) &hfc_map[2] },
2195         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B007),
2196                 (unsigned long) &hfc_map[3] },
2197         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B008),
2198                 (unsigned long) &hfc_map[4] },
2199         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B009),
2200                 (unsigned long) &hfc_map[5] },
2201         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00A),
2202                 (unsigned long) &hfc_map[6] },
2203         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00B),
2204                 (unsigned long) &hfc_map[7] },
2205         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B00C),
2206                 (unsigned long) &hfc_map[8] },
2207         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B100),
2208                 (unsigned long) &hfc_map[9] },
2209         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B700),
2210                 (unsigned long) &hfc_map[10] },
2211         { PCI_VDEVICE(CCD, PCI_DEVICE_ID_CCD_B701),
2212                 (unsigned long) &hfc_map[11] },
2213         { PCI_VDEVICE(ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1),
2214                 (unsigned long) &hfc_map[12] },
2215         { PCI_VDEVICE(ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675),
2216                 (unsigned long) &hfc_map[13] },
2217         { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT),
2218                 (unsigned long) &hfc_map[14] },
2219         { PCI_VDEVICE(BERKOM, PCI_DEVICE_ID_BERKOM_A1T),
2220                 (unsigned long) &hfc_map[15] },
2221         { PCI_VDEVICE(ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575),
2222                 (unsigned long) &hfc_map[16] },
2223         { PCI_VDEVICE(ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0),
2224                 (unsigned long) &hfc_map[17] },
2225         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E),
2226                 (unsigned long) &hfc_map[18] },
2227         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_E),
2228                 (unsigned long) &hfc_map[19] },
2229         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A),
2230                 (unsigned long) &hfc_map[20] },
2231         { PCI_VDEVICE(DIGI, PCI_DEVICE_ID_DIGI_DF_M_A),
2232                 (unsigned long) &hfc_map[21] },
2233         { PCI_VDEVICE(SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2),
2234                 (unsigned long) &hfc_map[22] },
2235         {},
2236 };
2237
2238 static int __devinit
2239 hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2240 {
2241         int             err = -ENOMEM;
2242         struct hfc_pci  *card;
2243         struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2244
2245         card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2246         if (!card) {
2247                 printk(KERN_ERR "No kmem for HFC card\n");
2248                 return err;
2249         }
2250         card->pdev = pdev;
2251         card->subtype = m->subtype;
2252         err = pci_enable_device(pdev);
2253         if (err) {
2254                 kfree(card);
2255                 return err;
2256         }
2257
2258         printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2259                m->name, pci_name(pdev));
2260
2261         card->irq = pdev->irq;
2262         pci_set_drvdata(pdev, card);
2263         err = setup_card(card);
2264         if (err)
2265                 pci_set_drvdata(pdev, NULL);
2266         return err;
2267 }
2268
2269 static void __devexit
2270 hfc_remove_pci(struct pci_dev *pdev)
2271 {
2272         struct hfc_pci  *card = pci_get_drvdata(pdev);
2273
2274         if (card)
2275                 release_card(card);
2276         else
2277                 if (debug)
2278                         printk(KERN_DEBUG "%s: drvdata already removed\n",
2279                             __func__);
2280 }
2281
2282
2283 static struct pci_driver hfc_driver = {
2284         .name = "hfcpci",
2285         .probe = hfc_probe,
2286         .remove = __devexit_p(hfc_remove_pci),
2287         .id_table = hfc_ids,
2288 };
2289
2290 static int
2291 _hfcpci_softirq(struct device *dev, void *arg)
2292 {
2293         struct hfc_pci  *hc = dev_get_drvdata(dev);
2294         struct bchannel *bch;
2295         if (hc == NULL)
2296                 return 0;
2297
2298         if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2299                 spin_lock(&hc->lock);
2300                 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2301                 if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
2302                         main_rec_hfcpci(bch);
2303                         tx_birq(bch);
2304                 }
2305                 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2306                 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
2307                         main_rec_hfcpci(bch);
2308                         tx_birq(bch);
2309                 }
2310                 spin_unlock(&hc->lock);
2311         }
2312         return 0;
2313 }
2314
2315 static void
2316 hfcpci_softirq(void *arg)
2317 {
2318         (void) driver_for_each_device(&hfc_driver.driver, NULL, arg,
2319                                         _hfcpci_softirq);
2320
2321         /* if next event would be in the past ... */
2322         if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
2323                 hfc_jiffies = jiffies + 1;
2324         else
2325                 hfc_jiffies += tics;
2326         hfc_tl.expires = hfc_jiffies;
2327         add_timer(&hfc_tl);
2328 }
2329
2330 static int __init
2331 HFC_init(void)
2332 {
2333         int             err;
2334
2335         if (!poll)
2336                 poll = HFCPCI_BTRANS_THRESHOLD;
2337
2338         if (poll != HFCPCI_BTRANS_THRESHOLD) {
2339                 tics = (poll * HZ) / 8000;
2340                 if (tics < 1)
2341                         tics = 1;
2342                 poll = (tics * 8000) / HZ;
2343                 if (poll > 256 || poll < 8) {
2344                         printk(KERN_ERR "%s: Wrong poll value %d not in range "
2345                                 "of 8..256.\n", __func__, poll);
2346                         err = -EINVAL;
2347                         return err;
2348                 }
2349         }
2350         if (poll != HFCPCI_BTRANS_THRESHOLD) {
2351                 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2352                         __func__, poll);
2353                 hfc_tl.function = (void *)hfcpci_softirq;
2354                 hfc_tl.data = 0;
2355                 init_timer(&hfc_tl);
2356                 hfc_tl.expires = jiffies + tics;
2357                 hfc_jiffies = hfc_tl.expires;
2358                 add_timer(&hfc_tl);
2359         } else
2360                 tics = 0; /* indicate the use of controller's timer */
2361
2362         err = pci_register_driver(&hfc_driver);
2363         if (err) {
2364                 if (timer_pending(&hfc_tl))
2365                         del_timer(&hfc_tl);
2366         }
2367
2368         return err;
2369 }
2370
2371 static void __exit
2372 HFC_cleanup(void)
2373 {
2374         if (timer_pending(&hfc_tl))
2375                 del_timer(&hfc_tl);
2376
2377         pci_unregister_driver(&hfc_driver);
2378 }
2379
2380 module_init(HFC_init);
2381 module_exit(HFC_cleanup);
2382
2383 MODULE_DEVICE_TABLE(pci, hfc_ids);