2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
42 #include <linux/jiffies.h>
43 #include <linux/module.h>
44 #include <rdma/ib_verbs.h>
45 #include <rdma/ib_smi.h>
48 #include "qib_7322_regs.h"
53 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
54 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
55 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
56 static irqreturn_t qib_7322intr(int irq, void *data);
57 static irqreturn_t qib_7322bufavail(int irq, void *data);
58 static irqreturn_t sdma_intr(int irq, void *data);
59 static irqreturn_t sdma_idle_intr(int irq, void *data);
60 static irqreturn_t sdma_progress_intr(int irq, void *data);
61 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
62 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
63 struct qib_ctxtdata *rcd);
64 static u8 qib_7322_phys_portstate(u64);
65 static u32 qib_7322_iblink_state(u64);
66 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
68 static void force_h1(struct qib_pportdata *);
69 static void adj_tx_serdes(struct qib_pportdata *);
70 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
71 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
73 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
74 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
75 static void serdes_7322_los_enable(struct qib_pportdata *, int);
76 static int serdes_7322_init_old(struct qib_pportdata *);
77 static int serdes_7322_init_new(struct qib_pportdata *);
79 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
81 /* LE2 serdes values for different cases */
86 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
87 #define IBSD(hw_pidx) (hw_pidx + 2)
89 /* these are variables for documentation and experimentation purposes */
90 static const unsigned rcv_int_timeout = 375;
91 static const unsigned rcv_int_count = 16;
92 static const unsigned sdma_idle_cnt = 64;
94 /* Time to stop altering Rx Equalization parameters, after link up. */
95 #define RXEQ_DISABLE_MSECS 2500
98 * Number of VLs we are configured to use (to allow for more
99 * credits per vl, etc.)
101 ushort qib_num_cfg_vls = 2;
102 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
103 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
105 static ushort qib_chase = 1;
106 module_param_named(chase, qib_chase, ushort, S_IRUGO);
107 MODULE_PARM_DESC(chase, "Enable state chase handling");
109 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
110 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
111 MODULE_PARM_DESC(long_attenuation, \
112 "attenuation cutoff (dB) for long copper cable setup");
114 static ushort qib_singleport;
115 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
116 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
118 static ushort qib_krcvq01_no_msi;
119 module_param_named(krcvq01_no_msi, qib_krcvq01_no_msi, ushort, S_IRUGO);
120 MODULE_PARM_DESC(krcvq01_no_msi, "No MSI for kctx < 2");
123 * Receive header queue sizes
125 static unsigned qib_rcvhdrcnt;
126 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
127 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
129 static unsigned qib_rcvhdrsize;
130 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
131 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
133 static unsigned qib_rcvhdrentsize;
134 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
135 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
137 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
138 /* for read back, default index is ~5m copper cable */
139 static char txselect_list[MAX_ATTEN_LEN] = "10";
140 static struct kparam_string kp_txselect = {
141 .string = txselect_list,
142 .maxlen = MAX_ATTEN_LEN
144 static int setup_txselect(const char *, struct kernel_param *);
145 module_param_call(txselect, setup_txselect, param_get_string,
146 &kp_txselect, S_IWUSR | S_IRUGO);
147 MODULE_PARM_DESC(txselect, \
148 "Tx serdes indices (for no QSFP or invalid QSFP data)");
150 #define BOARD_QME7342 5
151 #define BOARD_QMH7342 6
152 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
154 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
157 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
159 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
161 #define MASK_ACROSS(lsb, msb) \
162 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
164 #define SYM_RMASK(regname, fldname) ((u64) \
165 QIB_7322_##regname##_##fldname##_RMASK)
167 #define SYM_MASK(regname, fldname) ((u64) \
168 QIB_7322_##regname##_##fldname##_RMASK << \
169 QIB_7322_##regname##_##fldname##_LSB)
171 #define SYM_FIELD(value, regname, fldname) ((u64) \
172 (((value) >> SYM_LSB(regname, fldname)) & \
173 SYM_RMASK(regname, fldname)))
175 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
176 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
177 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
179 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
180 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
181 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
182 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
183 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
184 /* Below because most, but not all, fields of IntMask have that full suffix */
185 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
188 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
191 * the size bits give us 2^N, in KB units. 0 marks as invalid,
192 * and 7 is reserved. We currently use only 2KB and 4KB
194 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
195 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
196 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
197 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
199 #define SendIBSLIDAssignMask \
200 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
201 #define SendIBSLMCMask \
202 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
204 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
205 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
206 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
207 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
208 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
209 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
211 #define _QIB_GPIO_SDA_NUM 1
212 #define _QIB_GPIO_SCL_NUM 0
213 #define QIB_EEPROM_WEN_NUM 14
214 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
216 /* HW counter clock is at 4nsec */
217 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
219 /* full speed IB port 1 only */
220 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
221 #define PORT_SPD_CAP_SHIFT 3
223 /* full speed featuremask, both ports */
224 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
227 * This file contains almost all the chip-specific register information and
228 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
231 /* Use defines to tie machine-generated names to lower-case names */
232 #define kr_contextcnt KREG_IDX(ContextCnt)
233 #define kr_control KREG_IDX(Control)
234 #define kr_counterregbase KREG_IDX(CntrRegBase)
235 #define kr_errclear KREG_IDX(ErrClear)
236 #define kr_errmask KREG_IDX(ErrMask)
237 #define kr_errstatus KREG_IDX(ErrStatus)
238 #define kr_extctrl KREG_IDX(EXTCtrl)
239 #define kr_extstatus KREG_IDX(EXTStatus)
240 #define kr_gpio_clear KREG_IDX(GPIOClear)
241 #define kr_gpio_mask KREG_IDX(GPIOMask)
242 #define kr_gpio_out KREG_IDX(GPIOOut)
243 #define kr_gpio_status KREG_IDX(GPIOStatus)
244 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
245 #define kr_debugportval KREG_IDX(DebugPortValueReg)
246 #define kr_fmask KREG_IDX(feature_mask)
247 #define kr_act_fmask KREG_IDX(active_feature_mask)
248 #define kr_hwerrclear KREG_IDX(HwErrClear)
249 #define kr_hwerrmask KREG_IDX(HwErrMask)
250 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
251 #define kr_intclear KREG_IDX(IntClear)
252 #define kr_intmask KREG_IDX(IntMask)
253 #define kr_intredirect KREG_IDX(IntRedirect0)
254 #define kr_intstatus KREG_IDX(IntStatus)
255 #define kr_pagealign KREG_IDX(PageAlign)
256 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
257 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
258 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
259 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
260 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
261 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
262 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
263 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
264 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
265 #define kr_revision KREG_IDX(Revision)
266 #define kr_scratch KREG_IDX(Scratch)
267 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
268 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
269 #define kr_sendctrl KREG_IDX(SendCtrl)
270 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
271 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
272 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
273 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
274 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
275 #define kr_sendpiosize KREG_IDX(SendBufSize)
276 #define kr_sendregbase KREG_IDX(SendRegBase)
277 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
278 #define kr_userregbase KREG_IDX(UserRegBase)
279 #define kr_intgranted KREG_IDX(Int_Granted)
280 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
281 #define kr_intblocked KREG_IDX(IntBlocked)
282 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
285 * per-port kernel registers. Access only with qib_read_kreg_port()
286 * or qib_write_kreg_port()
288 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
289 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
290 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
291 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
292 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
293 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
294 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
295 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
296 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
297 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
298 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
299 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
300 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
301 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
302 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
303 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
304 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
305 #define krp_psstart KREG_IBPORT_IDX(PSStart)
306 #define krp_psstat KREG_IBPORT_IDX(PSStat)
307 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
308 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
309 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
310 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
311 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
312 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
313 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
314 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
315 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
316 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
317 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
318 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
319 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
320 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
321 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
322 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
323 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
324 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
325 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
326 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
327 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
328 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
329 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
330 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
331 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
332 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
333 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
334 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
335 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
336 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
337 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
340 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
341 * or qib_write_kreg_ctxt()
343 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
344 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
347 * TID Flow table, per context. Reduces
348 * number of hdrq updates to one per flow (or on errors).
349 * context 0 and 1 share same memory, but have distinct
350 * addresses. Since for now, we never use expected sends
351 * on kernel contexts, we don't worry about that (we initialize
352 * those entries for ctxt 0/1 on driver load twice, for example).
354 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
355 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
357 /* these are the error bits in the tid flows, and are W1C */
358 #define TIDFLOW_ERRBITS ( \
359 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
360 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
361 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
362 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
364 /* Most (not all) Counters are per-IBport.
365 * Requires LBIntCnt is at offset 0 in the group
367 #define CREG_IDX(regname) \
368 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
370 #define crp_badformat CREG_IDX(RxVersionErrCnt)
371 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
372 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
373 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
374 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
375 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
376 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
377 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
378 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
379 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
380 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
381 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
382 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
383 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
384 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
385 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
386 #define crp_pktsend CREG_IDX(TxDataPktCnt)
387 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
388 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
389 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
390 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
391 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
392 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
393 #define crp_rcvebp CREG_IDX(RxEBPCnt)
394 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
395 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
396 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
397 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
398 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
399 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
400 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
401 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
402 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
403 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
404 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
405 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
406 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
407 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
408 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
409 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
410 #define crp_wordrcv CREG_IDX(RxDwordCnt)
411 #define crp_wordsend CREG_IDX(TxDwordCnt)
412 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
414 /* these are the (few) counters that are not port-specific */
415 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
416 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
417 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
418 #define cr_lbint CREG_DEVIDX(LBIntCnt)
419 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
420 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
421 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
422 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
423 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
425 /* no chip register for # of IB ports supported, so define */
426 #define NUM_IB_PORTS 2
428 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
429 #define NUM_VL15_BUFS NUM_IB_PORTS
432 * context 0 and 1 are special, and there is no chip register that
433 * defines this value, so we have to define it here.
434 * These are all allocated to either 0 or 1 for single port
435 * hardware configuration, otherwise each gets half
437 #define KCTXT0_EGRCNT 2048
439 /* values for vl and port fields in PBC, 7322-specific */
440 #define PBC_PORT_SEL_LSB 26
441 #define PBC_PORT_SEL_RMASK 1
442 #define PBC_VL_NUM_LSB 27
443 #define PBC_VL_NUM_RMASK 7
444 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
445 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
447 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
448 [IB_RATE_2_5_GBPS] = 16,
449 [IB_RATE_5_GBPS] = 8,
450 [IB_RATE_10_GBPS] = 4,
451 [IB_RATE_20_GBPS] = 2,
452 [IB_RATE_30_GBPS] = 2,
453 [IB_RATE_40_GBPS] = 1
456 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
457 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
459 /* link training states, from IBC */
460 #define IB_7322_LT_STATE_DISABLED 0x00
461 #define IB_7322_LT_STATE_LINKUP 0x01
462 #define IB_7322_LT_STATE_POLLACTIVE 0x02
463 #define IB_7322_LT_STATE_POLLQUIET 0x03
464 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
465 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
466 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
467 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
468 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
469 #define IB_7322_LT_STATE_CFGIDLE 0x0b
470 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
471 #define IB_7322_LT_STATE_TXREVLANES 0x0d
472 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
473 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
474 #define IB_7322_LT_STATE_CFGENH 0x10
475 #define IB_7322_LT_STATE_CFGTEST 0x11
476 #define IB_7322_LT_STATE_CFGWAITRMTTEST 0x12
477 #define IB_7322_LT_STATE_CFGWAITENH 0x13
479 /* link state machine states from IBC */
480 #define IB_7322_L_STATE_DOWN 0x0
481 #define IB_7322_L_STATE_INIT 0x1
482 #define IB_7322_L_STATE_ARM 0x2
483 #define IB_7322_L_STATE_ACTIVE 0x3
484 #define IB_7322_L_STATE_ACT_DEFER 0x4
486 static const u8 qib_7322_physportstate[0x20] = {
487 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
488 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
489 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
490 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
491 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
492 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
493 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
494 [IB_7322_LT_STATE_CFGRCVFCFG] =
495 IB_PHYSPORTSTATE_CFG_TRAIN,
496 [IB_7322_LT_STATE_CFGWAITRMT] =
497 IB_PHYSPORTSTATE_CFG_TRAIN,
498 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
499 [IB_7322_LT_STATE_RECOVERRETRAIN] =
500 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
501 [IB_7322_LT_STATE_RECOVERWAITRMT] =
502 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
503 [IB_7322_LT_STATE_RECOVERIDLE] =
504 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
505 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
506 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
507 [IB_7322_LT_STATE_CFGWAITRMTTEST] =
508 IB_PHYSPORTSTATE_CFG_TRAIN,
509 [IB_7322_LT_STATE_CFGWAITENH] =
510 IB_PHYSPORTSTATE_CFG_WAIT_ENH,
511 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
512 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
513 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
514 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
517 struct qib_chip_specific {
518 u64 __iomem *cregbase;
520 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
521 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
522 u64 main_int_mask; /* clear bits which have dedicated handlers */
523 u64 int_enable_mask; /* for per port interrupts in single port mode */
526 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
527 u64 gpio_mask; /* shadow the gpio mask register */
528 u64 extctrl; /* shadow the gpio output enable, etc... */
535 u32 updthresh; /* current AvailUpdThld */
536 u32 updthresh_dflt; /* default AvailUpdThld */
539 u32 num_msix_entries;
543 u32 recovery_ports_initted;
544 struct msix_entry *msix_entries;
546 unsigned long *sendchkenable;
547 unsigned long *sendgrhchk;
548 unsigned long *sendibchk;
549 u32 rcvavail_timeout[18];
550 char emsgbuf[128]; /* for device error interrupt msg buffer */
553 /* Table of entries in "human readable" form Tx Emphasis. */
561 struct vendor_txdds_ent {
562 u8 oui[QSFP_VOUI_LEN];
564 struct txdds_ent sdr;
565 struct txdds_ent ddr;
566 struct txdds_ent qdr;
569 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
571 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
572 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
573 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
574 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
576 #define H1_FORCE_VAL 8
577 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
578 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
580 /* The static and dynamic registers are paired, and the pairs indexed by spd */
581 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
584 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
585 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
586 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
587 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
588 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
590 struct qib_chippport_specific {
591 u64 __iomem *kpregbase;
592 u64 __iomem *cpregbase;
594 struct qib_pportdata *ppd;
595 wait_queue_head_t autoneg_wait;
596 struct delayed_work autoneg_work;
597 struct delayed_work ipg_work;
598 struct timer_list chase_timer;
600 * these 5 fields are used to establish deltas for IB symbol
601 * errors and linkrecovery errors. They can be reported on
602 * some chips during link negotiation prior to INIT, and with
603 * DDR when faking DDR negotiations with non-IBTA switches.
604 * The chip counters are adjusted at driver unload if there is
616 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
617 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
625 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
626 * entry zero is unused, to simplify indexing
629 u8 no_eep; /* txselect table index to use if no qsfp info */
632 struct qib_qsfp_data qsfp_data;
633 char epmsgbuf[192]; /* for port error interrupt msg buffer */
638 irq_handler_t handler;
640 int port; /* 0 if not port-specific, else port # */
642 { QIB_DRV_NAME, qib_7322intr, -1, 0 },
643 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail,
644 SYM_LSB(IntStatus, SendBufAvail), 0 },
645 { QIB_DRV_NAME " (sdma 0)", sdma_intr,
646 SYM_LSB(IntStatus, SDmaInt_0), 1 },
647 { QIB_DRV_NAME " (sdma 1)", sdma_intr,
648 SYM_LSB(IntStatus, SDmaInt_1), 2 },
649 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr,
650 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
651 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr,
652 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
653 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr,
654 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
655 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr,
656 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
657 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr,
658 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
659 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr,
660 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
664 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
665 /* cycle through TS1/TS2 till OK */
666 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
667 /* wait for TS1, then go on */
668 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
669 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
671 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
672 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
673 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
675 #define BLOB_7322_IBCHG 0x101
677 static inline void qib_write_kreg(const struct qib_devdata *dd,
678 const u32 regno, u64 value);
679 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
680 static void write_7322_initregs(struct qib_devdata *);
681 static void write_7322_init_portregs(struct qib_pportdata *);
682 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
683 static void check_7322_rxe_status(struct qib_pportdata *);
684 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
687 * qib_read_ureg32 - read 32-bit virtualized per-context register
689 * @regno: register number
690 * @ctxt: context number
692 * Return the contents of a register that is virtualized to be per context.
693 * Returns -1 on errors (not distinguishable from valid contents at
694 * runtime; we may add a separate error variable at some point).
696 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
697 enum qib_ureg regno, int ctxt)
699 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
701 return readl(regno + (u64 __iomem *)(
702 (dd->ureg_align * ctxt) + (dd->userbase ?
703 (char __iomem *)dd->userbase :
704 (char __iomem *)dd->kregbase + dd->uregbase)));
708 * qib_read_ureg - read virtualized per-context register
710 * @regno: register number
711 * @ctxt: context number
713 * Return the contents of a register that is virtualized to be per context.
714 * Returns -1 on errors (not distinguishable from valid contents at
715 * runtime; we may add a separate error variable at some point).
717 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
718 enum qib_ureg regno, int ctxt)
721 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
723 return readq(regno + (u64 __iomem *)(
724 (dd->ureg_align * ctxt) + (dd->userbase ?
725 (char __iomem *)dd->userbase :
726 (char __iomem *)dd->kregbase + dd->uregbase)));
730 * qib_write_ureg - write virtualized per-context register
732 * @regno: register number
736 * Write the contents of a register that is virtualized to be per context.
738 static inline void qib_write_ureg(const struct qib_devdata *dd,
739 enum qib_ureg regno, u64 value, int ctxt)
743 ubase = (u64 __iomem *)
744 ((char __iomem *) dd->userbase +
745 dd->ureg_align * ctxt);
747 ubase = (u64 __iomem *)
749 (char __iomem *) dd->kregbase +
750 dd->ureg_align * ctxt);
752 if (dd->kregbase && (dd->flags & QIB_PRESENT))
753 writeq(value, &ubase[regno]);
756 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
759 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
761 return readl((u32 __iomem *) &dd->kregbase[regno]);
764 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
767 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
769 return readq(&dd->kregbase[regno]);
772 static inline void qib_write_kreg(const struct qib_devdata *dd,
773 const u32 regno, u64 value)
775 if (dd->kregbase && (dd->flags & QIB_PRESENT))
776 writeq(value, &dd->kregbase[regno]);
780 * not many sanity checks for the port-specific kernel register routines,
781 * since they are only used when it's known to be safe.
783 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
786 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
788 return readq(&ppd->cpspec->kpregbase[regno]);
791 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
792 const u16 regno, u64 value)
794 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
795 (ppd->dd->flags & QIB_PRESENT))
796 writeq(value, &ppd->cpspec->kpregbase[regno]);
800 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
801 * @dd: the qlogic_ib device
802 * @regno: the register number to write
803 * @ctxt: the context containing the register
804 * @value: the value to write
806 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
807 const u16 regno, unsigned ctxt,
810 qib_write_kreg(dd, regno + ctxt, value);
813 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
815 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
817 return readq(&dd->cspec->cregbase[regno]);
822 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
824 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
826 return readl(&dd->cspec->cregbase[regno]);
831 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
832 u16 regno, u64 value)
834 if (ppd->cpspec && ppd->cpspec->cpregbase &&
835 (ppd->dd->flags & QIB_PRESENT))
836 writeq(value, &ppd->cpspec->cpregbase[regno]);
839 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
842 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
843 !(ppd->dd->flags & QIB_PRESENT))
845 return readq(&ppd->cpspec->cpregbase[regno]);
848 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
851 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
852 !(ppd->dd->flags & QIB_PRESENT))
854 return readl(&ppd->cpspec->cpregbase[regno]);
857 /* bits in Control register */
858 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
859 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
861 /* bits in general interrupt regs */
862 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
863 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
864 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
865 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
866 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
867 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
868 #define QIB_I_C_ERROR INT_MASK(Err)
870 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
871 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
872 #define QIB_I_GPIO INT_MASK(AssertGPIO)
873 #define QIB_I_P_SDMAINT(pidx) \
874 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
875 INT_MASK_P(SDmaProgress, pidx) | \
876 INT_MASK_PM(SDmaCleanupDone, pidx))
878 /* Interrupt bits that are "per port" */
879 #define QIB_I_P_BITSEXTANT(pidx) \
880 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
881 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
882 INT_MASK_P(SDmaProgress, pidx) | \
883 INT_MASK_PM(SDmaCleanupDone, pidx))
885 /* Interrupt bits that are common to a device */
886 /* currently unused: QIB_I_SPIOSENT */
887 #define QIB_I_C_BITSEXTANT \
888 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
890 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
892 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
893 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
896 * Error bits that are "per port".
898 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
899 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
900 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
901 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
902 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
903 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
904 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
905 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
906 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
907 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
908 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
909 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
910 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
911 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
912 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
913 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
914 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
915 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
916 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
917 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
918 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
919 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
920 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
921 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
922 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
923 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
924 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
925 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
927 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
928 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
929 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
930 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
931 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
932 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
933 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
934 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
935 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
936 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
937 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
939 /* Error bits that are common to a device */
940 #define QIB_E_RESET ERR_MASK(ResetNegated)
941 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
942 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
946 * Per chip (rather than per-port) errors. Most either do
947 * nothing but trigger a print (because they self-recover, or
948 * always occur in tandem with other errors that handle the
949 * issue), or because they indicate errors with no recovery,
950 * but we want to know that they happened.
952 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
953 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
954 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
955 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
956 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
957 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
958 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
959 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
961 /* SDMA chip errors (not per port)
962 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
963 * the SDMAHALT error immediately, so we just print the dup error via the
964 * E_AUTO mechanism. This is true of most of the per-port fatal errors
965 * as well, but since this is port-independent, by definition, it's
966 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
967 * packet send errors, and so are handled in the same manner as other
970 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
971 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
972 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
975 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
976 * it is used to print "common" packet errors.
978 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
979 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
980 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
981 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
984 /* Error Bits that Packet-related (Receive, per-port) */
985 #define QIB_E_P_RPKTERRS (\
986 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
987 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
988 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
989 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
990 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
991 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
994 * Error bits that are Send-related (per port)
995 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
996 * All of these potentially need to have a buffer disarmed
998 #define QIB_E_P_SPKTERRS (\
999 QIB_E_P_SUNEXP_PKTNUM |\
1000 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1001 QIB_E_P_SMAXPKTLEN |\
1002 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
1003 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
1004 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
1006 #define QIB_E_SPKTERRS ( \
1007 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1008 ERR_MASK_N(SendUnsupportedVLErr) | \
1009 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1011 #define QIB_E_P_SDMAERRS ( \
1012 QIB_E_P_SDMAHALT | \
1013 QIB_E_P_SDMADESCADDRMISALIGN | \
1014 QIB_E_P_SDMAUNEXPDATA | \
1015 QIB_E_P_SDMAMISSINGDW | \
1016 QIB_E_P_SDMADWEN | \
1017 QIB_E_P_SDMARPYTAG | \
1018 QIB_E_P_SDMA1STDESC | \
1019 QIB_E_P_SDMABASE | \
1020 QIB_E_P_SDMATAILOUTOFBOUND | \
1021 QIB_E_P_SDMAOUTOFBOUND | \
1022 QIB_E_P_SDMAGENMISMATCH)
1025 * This sets some bits more than once, but makes it more obvious which
1026 * bits are not handled under other categories, and the repeat definition
1029 #define QIB_E_P_BITSEXTANT ( \
1030 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1031 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1032 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1033 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1037 * These are errors that can occur when the link
1038 * changes state while a packet is being sent or received. This doesn't
1039 * cover things like EBP or VCRC that can be the result of a sending
1040 * having the link change state, so we receive a "known bad" packet.
1041 * All of these are "per port", so renamed:
1043 #define QIB_E_P_LINK_PKTERRS (\
1044 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1045 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1046 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1050 * This sets some bits more than once, but makes it more obvious which
1051 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1052 * and the repeat definition is not a problem.
1054 #define QIB_E_C_BITSEXTANT (\
1055 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1056 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1057 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1059 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1060 #define E_SPKT_ERRS_IGNORE 0
1062 #define QIB_EXTS_MEMBIST_DISABLED \
1063 SYM_MASK(EXTStatus, MemBISTDisabled)
1064 #define QIB_EXTS_MEMBIST_ENDTEST \
1065 SYM_MASK(EXTStatus, MemBISTEndTest)
1067 #define QIB_E_SPIOARMLAUNCH \
1068 ERR_MASK(SendArmLaunchErr)
1070 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1071 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1074 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1075 * and also if forced QDR (only QDR enabled). It's enabled for the
1076 * forced QDR case so that scrambling will be enabled by the TS3
1077 * exchange, when supported by both sides of the link.
1079 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1080 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1081 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1082 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1083 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1084 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1085 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1086 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1088 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1089 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1091 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1092 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1093 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1095 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1096 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1097 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1098 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1099 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1100 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1101 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1103 #define IBA7322_REDIRECT_VEC_PER_REG 12
1105 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1106 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1107 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1108 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1109 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1111 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1113 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1114 .msg = #fldname , .sz = sizeof(#fldname) }
1115 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1116 fldname##Mask##_##port), .msg = #fldname , .sz = sizeof(#fldname) }
1117 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1118 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1119 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1120 HWE_AUTO(PCIESerdesPClkNotDetect),
1121 HWE_AUTO(PowerOnBISTFailed),
1122 HWE_AUTO(TempsenseTholdReached),
1123 HWE_AUTO(MemoryErr),
1124 HWE_AUTO(PCIeBusParityErr),
1125 HWE_AUTO(PcieCplTimeout),
1126 HWE_AUTO(PciePoisonedTLP),
1127 HWE_AUTO_P(SDmaMemReadErr, 1),
1128 HWE_AUTO_P(SDmaMemReadErr, 0),
1129 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1130 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1131 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1132 HWE_AUTO(statusValidNoEop),
1133 HWE_AUTO(LATriggered),
1134 { .mask = 0, .sz = 0 }
1137 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1138 .msg = #fldname, .sz = sizeof(#fldname) }
1139 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1140 .msg = #fldname, .sz = sizeof(#fldname) }
1141 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1142 E_AUTO(RcvEgrFullErr),
1143 E_AUTO(RcvHdrFullErr),
1144 E_AUTO(ResetNegated),
1145 E_AUTO(HardwareErr),
1146 E_AUTO(InvalidAddrErr),
1147 E_AUTO(SDmaVL15Err),
1148 E_AUTO(SBufVL15MisUseErr),
1149 E_AUTO(InvalidEEPCmd),
1150 E_AUTO(RcvContextShareErr),
1151 E_AUTO(SendVLMismatchErr),
1152 E_AUTO(SendArmLaunchErr),
1153 E_AUTO(SendSpecialTriggerErr),
1154 E_AUTO(SDmaWrongPortErr),
1155 E_AUTO(SDmaBufMaskDuplicateErr),
1156 { .mask = 0, .sz = 0 }
1159 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1160 E_P_AUTO(IBStatusChanged),
1161 E_P_AUTO(SHeadersErr),
1162 E_P_AUTO(VL15BufMisuseErr),
1164 * SDmaHaltErr is not really an error, make it clearer;
1166 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted",
1168 E_P_AUTO(SDmaDescAddrMisalignErr),
1169 E_P_AUTO(SDmaUnexpDataErr),
1170 E_P_AUTO(SDmaMissingDwErr),
1171 E_P_AUTO(SDmaDwEnErr),
1172 E_P_AUTO(SDmaRpyTagErr),
1173 E_P_AUTO(SDma1stDescErr),
1174 E_P_AUTO(SDmaBaseErr),
1175 E_P_AUTO(SDmaTailOutOfBoundErr),
1176 E_P_AUTO(SDmaOutOfBoundErr),
1177 E_P_AUTO(SDmaGenMismatchErr),
1178 E_P_AUTO(SendBufMisuseErr),
1179 E_P_AUTO(SendUnsupportedVLErr),
1180 E_P_AUTO(SendUnexpectedPktNumErr),
1181 E_P_AUTO(SendDroppedDataPktErr),
1182 E_P_AUTO(SendDroppedSmpPktErr),
1183 E_P_AUTO(SendPktLenErr),
1184 E_P_AUTO(SendUnderRunErr),
1185 E_P_AUTO(SendMaxPktLenErr),
1186 E_P_AUTO(SendMinPktLenErr),
1187 E_P_AUTO(RcvIBLostLinkErr),
1188 E_P_AUTO(RcvHdrErr),
1189 E_P_AUTO(RcvHdrLenErr),
1190 E_P_AUTO(RcvBadTidErr),
1191 E_P_AUTO(RcvBadVersionErr),
1192 E_P_AUTO(RcvIBFlowErr),
1193 E_P_AUTO(RcvEBPErr),
1194 E_P_AUTO(RcvUnsupportedVLErr),
1195 E_P_AUTO(RcvUnexpectedCharErr),
1196 E_P_AUTO(RcvShortPktLenErr),
1197 E_P_AUTO(RcvLongPktLenErr),
1198 E_P_AUTO(RcvMaxPktLenErr),
1199 E_P_AUTO(RcvMinPktLenErr),
1200 E_P_AUTO(RcvICRCErr),
1201 E_P_AUTO(RcvVCRCErr),
1202 E_P_AUTO(RcvFormatErr),
1203 { .mask = 0, .sz = 0 }
1207 * Below generates "auto-message" for interrupts not specific to any port or
1210 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1211 .msg = #fldname, .sz = sizeof(#fldname) }
1212 /* Below generates "auto-message" for interrupts specific to a port */
1213 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1214 SYM_LSB(IntMask, fldname##Mask##_0), \
1215 SYM_LSB(IntMask, fldname##Mask##_1)), \
1216 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1217 /* For some reason, the SerDesTrimDone bits are reversed */
1218 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1219 SYM_LSB(IntMask, fldname##Mask##_1), \
1220 SYM_LSB(IntMask, fldname##Mask##_0)), \
1221 .msg = #fldname "_P", .sz = sizeof(#fldname "_P") }
1223 * Below generates "auto-message" for interrupts specific to a context,
1224 * with ctxt-number appended
1226 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1227 SYM_LSB(IntMask, fldname##0IntMask), \
1228 SYM_LSB(IntMask, fldname##17IntMask)), \
1229 .msg = #fldname "_C", .sz = sizeof(#fldname "_C") }
1231 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1232 INTR_AUTO_P(SDmaInt),
1233 INTR_AUTO_P(SDmaProgressInt),
1234 INTR_AUTO_P(SDmaIdleInt),
1235 INTR_AUTO_P(SDmaCleanupDone),
1236 INTR_AUTO_C(RcvUrg),
1237 INTR_AUTO_P(ErrInt),
1238 INTR_AUTO(ErrInt), /* non-port-specific errs */
1239 INTR_AUTO(AssertGPIOInt),
1240 INTR_AUTO_P(SendDoneInt),
1241 INTR_AUTO(SendBufAvailInt),
1242 INTR_AUTO_C(RcvAvail),
1243 { .mask = 0, .sz = 0 }
1246 #define TXSYMPTOM_AUTO_P(fldname) \
1247 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), \
1248 .msg = #fldname, .sz = sizeof(#fldname) }
1249 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1250 TXSYMPTOM_AUTO_P(NonKeyPacket),
1251 TXSYMPTOM_AUTO_P(GRHFail),
1252 TXSYMPTOM_AUTO_P(PkeyFail),
1253 TXSYMPTOM_AUTO_P(QPFail),
1254 TXSYMPTOM_AUTO_P(SLIDFail),
1255 TXSYMPTOM_AUTO_P(RawIPV6),
1256 TXSYMPTOM_AUTO_P(PacketTooSmall),
1257 { .mask = 0, .sz = 0 }
1260 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1263 * Called when we might have an error that is specific to a particular
1264 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1265 * because we don't need to force the update of pioavail
1267 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1269 struct qib_devdata *dd = ppd->dd;
1272 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1273 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1274 unsigned long sbuf[4];
1277 * It's possible that sendbuffererror could have bits set; might
1278 * have already done this as a result of hardware error handling.
1281 for (i = 0; i < regcnt; ++i) {
1282 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1285 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1290 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1293 /* No txe_recover yet, if ever */
1295 /* No decode__errors yet */
1296 static void err_decode(char *msg, size_t len, u64 errs,
1297 const struct qib_hwerror_msgs *msp)
1300 int took, multi, n = 0;
1302 while (errs && msp && msp->mask) {
1303 multi = (msp->mask & (msp->mask - 1));
1304 while (errs & msp->mask) {
1305 these = (errs & msp->mask);
1306 lmask = (these & (these - 1)) ^ these;
1309 /* separate the strings */
1314 /* msp->sz counts the nul */
1315 took = min_t(size_t, msp->sz - (size_t)1, len);
1316 memcpy(msg, msp->msg, took);
1324 /* More than one bit this mask */
1327 while (lmask & msp->mask) {
1331 took = scnprintf(msg, len, "_%d", idx);
1338 /* If some bits are left, show in hex. */
1340 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1341 (unsigned long long) errs);
1344 /* only called if r1 set */
1345 static void flush_fifo(struct qib_pportdata *ppd)
1347 struct qib_devdata *dd = ppd->dd;
1348 u32 __iomem *piobuf;
1352 const unsigned hdrwords = 7;
1353 static struct qib_ib_header ibhdr = {
1354 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1355 .lrh[1] = IB_LID_PERMISSIVE,
1356 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1357 .lrh[3] = IB_LID_PERMISSIVE,
1358 .u.oth.bth[0] = cpu_to_be32(
1359 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1360 .u.oth.bth[1] = cpu_to_be32(0),
1361 .u.oth.bth[2] = cpu_to_be32(0),
1362 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1363 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1367 * Send a dummy VL15 packet to flush the launch FIFO.
1368 * This will not actually be sent since the TxeBypassIbc bit is set.
1370 pbc = PBC_7322_VL15_SEND |
1371 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1372 (hdrwords + SIZE_OF_CRC);
1373 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1376 writeq(pbc, piobuf);
1377 hdr = (u32 *) &ibhdr;
1378 if (dd->flags & QIB_PIO_FLUSH_WC) {
1380 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1382 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1385 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1386 qib_sendbuf_done(dd, bufn);
1390 * This is called with interrupts disabled and sdma_lock held.
1392 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1394 struct qib_devdata *dd = ppd->dd;
1395 u64 set_sendctrl = 0;
1396 u64 clr_sendctrl = 0;
1398 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1399 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1401 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1403 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1404 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1406 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1408 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1409 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1411 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1413 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1414 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1415 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1416 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1418 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1419 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1420 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1422 spin_lock(&dd->sendctrl_lock);
1424 /* If we are draining everything, block sends first */
1425 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1426 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1427 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1428 qib_write_kreg(dd, kr_scratch, 0);
1431 ppd->p_sendctrl |= set_sendctrl;
1432 ppd->p_sendctrl &= ~clr_sendctrl;
1434 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1435 qib_write_kreg_port(ppd, krp_sendctrl,
1437 SYM_MASK(SendCtrl_0, SDmaCleanup));
1439 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1440 qib_write_kreg(dd, kr_scratch, 0);
1442 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1443 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1444 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1445 qib_write_kreg(dd, kr_scratch, 0);
1448 spin_unlock(&dd->sendctrl_lock);
1450 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1454 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1456 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1459 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1462 * Set SendDmaLenGen and clear and set
1463 * the MSB of the generation count to enable generation checking
1464 * and load the internal generation counter.
1466 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1467 qib_write_kreg_port(ppd, krp_senddmalengen,
1468 ppd->sdma_descq_cnt |
1469 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1473 * Must be called with sdma_lock held, or before init finished.
1475 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1477 /* Commit writes to memory and advance the tail on the chip */
1479 ppd->sdma_descq_tail = tail;
1480 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1484 * This is called with interrupts disabled and sdma_lock held.
1486 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1490 * The hardware doesn't require this but we do it so that verbs
1491 * and user applications don't wait for link active to send stale
1494 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1496 qib_sdma_7322_setlengen(ppd);
1497 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1498 ppd->sdma_head_dma[0] = 0;
1499 qib_7322_sdma_sendctrl(ppd,
1500 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1503 #define DISABLES_SDMA ( \
1504 QIB_E_P_SDMAHALT | \
1505 QIB_E_P_SDMADESCADDRMISALIGN | \
1506 QIB_E_P_SDMAMISSINGDW | \
1507 QIB_E_P_SDMADWEN | \
1508 QIB_E_P_SDMARPYTAG | \
1509 QIB_E_P_SDMA1STDESC | \
1510 QIB_E_P_SDMABASE | \
1511 QIB_E_P_SDMATAILOUTOFBOUND | \
1512 QIB_E_P_SDMAOUTOFBOUND | \
1513 QIB_E_P_SDMAGENMISMATCH)
1515 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1517 unsigned long flags;
1518 struct qib_devdata *dd = ppd->dd;
1520 errs &= QIB_E_P_SDMAERRS;
1522 if (errs & QIB_E_P_SDMAUNEXPDATA)
1523 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1526 spin_lock_irqsave(&ppd->sdma_lock, flags);
1528 switch (ppd->sdma_state.current_state) {
1529 case qib_sdma_state_s00_hw_down:
1532 case qib_sdma_state_s10_hw_start_up_wait:
1533 if (errs & QIB_E_P_SDMAHALT)
1534 __qib_sdma_process_event(ppd,
1535 qib_sdma_event_e20_hw_started);
1538 case qib_sdma_state_s20_idle:
1541 case qib_sdma_state_s30_sw_clean_up_wait:
1544 case qib_sdma_state_s40_hw_clean_up_wait:
1545 if (errs & QIB_E_P_SDMAHALT)
1546 __qib_sdma_process_event(ppd,
1547 qib_sdma_event_e50_hw_cleaned);
1550 case qib_sdma_state_s50_hw_halt_wait:
1551 if (errs & QIB_E_P_SDMAHALT)
1552 __qib_sdma_process_event(ppd,
1553 qib_sdma_event_e60_hw_halted);
1556 case qib_sdma_state_s99_running:
1557 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1558 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1562 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1566 * handle per-device errors (not per-port errors)
1568 static noinline void handle_7322_errors(struct qib_devdata *dd)
1576 qib_stats.sps_errints++;
1577 errs = qib_read_kreg64(dd, kr_errstatus);
1579 qib_devinfo(dd->pcidev, "device error interrupt, "
1580 "but no error bits set!\n");
1584 /* don't report errors that are masked */
1585 errs &= dd->cspec->errormask;
1586 msg = dd->cspec->emsgbuf;
1588 /* do these first, they are most important */
1589 if (errs & QIB_E_HARDWARE) {
1591 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1593 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1594 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1595 qib_inc_eeprom_err(dd, log_idx, 1);
1597 if (errs & QIB_E_SPKTERRS) {
1598 qib_disarm_7322_senderrbufs(dd->pport);
1599 qib_stats.sps_txerrs++;
1600 } else if (errs & QIB_E_INVALIDADDR)
1601 qib_stats.sps_txerrs++;
1602 else if (errs & QIB_E_ARMLAUNCH) {
1603 qib_stats.sps_txerrs++;
1604 qib_disarm_7322_senderrbufs(dd->pport);
1606 qib_write_kreg(dd, kr_errclear, errs);
1609 * The ones we mask off are handled specially below
1610 * or above. Also mask SDMADISABLED by default as it
1613 mask = QIB_E_HARDWARE;
1616 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1617 qib_7322error_msgs);
1620 * Getting reset is a tragedy for all ports. Mark the device
1621 * _and_ the ports as "offline" in way meaningful to each.
1623 if (errs & QIB_E_RESET) {
1626 qib_dev_err(dd, "Got reset, requires re-init "
1627 "(unload and reload driver)\n");
1628 dd->flags &= ~QIB_INITTED; /* needs re-init */
1629 /* mark as having had error */
1630 *dd->devstatusp |= QIB_STATUS_HWERROR;
1631 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1632 if (dd->pport[pidx].link_speed_supported)
1633 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1637 qib_dev_err(dd, "%s error\n", msg);
1640 * If there were hdrq or egrfull errors, wake up any processes
1641 * waiting in poll. We used to try to check which contexts had
1642 * the overflow, but given the cost of that and the chip reads
1643 * to support it, it's better to just wake everybody up if we
1644 * get an overflow; waiters can poll again if it's not them.
1646 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1647 qib_handle_urcv(dd, ~0U);
1648 if (errs & ERR_MASK(RcvEgrFullErr))
1649 qib_stats.sps_buffull++;
1651 qib_stats.sps_hdrfull++;
1658 static void qib_error_tasklet(unsigned long data)
1660 struct qib_devdata *dd = (struct qib_devdata *)data;
1662 handle_7322_errors(dd);
1663 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1666 static void reenable_chase(unsigned long opaque)
1668 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1670 ppd->cpspec->chase_timer.expires = 0;
1671 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1672 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1675 static void disable_chase(struct qib_pportdata *ppd, u64 tnow, u8 ibclt)
1677 ppd->cpspec->chase_end = 0;
1682 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1683 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1684 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1685 add_timer(&ppd->cpspec->chase_timer);
1688 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1693 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1696 * Detect and handle the state chase issue, where we can
1697 * get stuck if we are unlucky on timing on both sides of
1698 * the link. If we are, we disable, set a timer, and
1702 case IB_7322_LT_STATE_CFGRCVFCFG:
1703 case IB_7322_LT_STATE_CFGWAITRMT:
1704 case IB_7322_LT_STATE_TXREVLANES:
1705 case IB_7322_LT_STATE_CFGENH:
1706 tnow = get_jiffies_64();
1707 if (ppd->cpspec->chase_end &&
1708 time_after64(tnow, ppd->cpspec->chase_end))
1709 disable_chase(ppd, tnow, ibclt);
1710 else if (!ppd->cpspec->chase_end)
1711 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1714 ppd->cpspec->chase_end = 0;
1718 if (((ibclt >= IB_7322_LT_STATE_CFGTEST &&
1719 ibclt <= IB_7322_LT_STATE_CFGWAITENH) ||
1720 ibclt == IB_7322_LT_STATE_LINKUP) &&
1721 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1723 ppd->cpspec->qdr_reforce = 1;
1724 if (!ppd->dd->cspec->r1)
1725 serdes_7322_los_enable(ppd, 0);
1726 } else if (ppd->cpspec->qdr_reforce &&
1727 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1728 (ibclt == IB_7322_LT_STATE_CFGENH ||
1729 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1730 ibclt == IB_7322_LT_STATE_LINKUP))
1733 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1734 ppd->link_speed_enabled == QIB_IB_QDR &&
1735 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1736 ibclt == IB_7322_LT_STATE_CFGENH ||
1737 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1738 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1741 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1742 u8 ltstate = qib_7322_phys_portstate(ibcst);
1743 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1745 if (!ppd->dd->cspec->r1 &&
1746 pibclt == IB_7322_LT_STATE_LINKUP &&
1747 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1748 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1749 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1750 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1751 /* If the link went down (but no into recovery,
1752 * turn LOS back on */
1753 serdes_7322_los_enable(ppd, 1);
1754 if (!ppd->cpspec->qdr_dfe_on &&
1755 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1756 ppd->cpspec->qdr_dfe_on = 1;
1757 ppd->cpspec->qdr_dfe_time = 0;
1758 /* On link down, reenable QDR adaptation */
1759 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1760 ppd->dd->cspec->r1 ?
1761 QDR_STATIC_ADAPT_DOWN_R1 :
1762 QDR_STATIC_ADAPT_DOWN);
1763 printk(KERN_INFO QIB_DRV_NAME
1764 " IB%u:%u re-enabled QDR adaptation "
1765 "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt);
1770 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1773 * This is per-pport error handling.
1774 * will likely get it's own MSIx interrupt (one for each port,
1775 * although just a single handler).
1777 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1780 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1781 struct qib_devdata *dd = ppd->dd;
1783 /* do this as soon as possible */
1784 fmask = qib_read_kreg64(dd, kr_act_fmask);
1786 check_7322_rxe_status(ppd);
1788 errs = qib_read_kreg_port(ppd, krp_errstatus);
1790 qib_devinfo(dd->pcidev,
1791 "Port%d error interrupt, but no error bits set!\n",
1794 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1798 msg = ppd->cpspec->epmsgbuf;
1801 if (errs & ~QIB_E_P_BITSEXTANT) {
1802 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1803 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1805 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1807 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown"
1808 " errors 0x%016Lx set (and %s)\n",
1809 (errs & ~QIB_E_P_BITSEXTANT), msg);
1813 if (errs & QIB_E_P_SHDR) {
1816 /* determine cause, then write to clear */
1817 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1818 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1819 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1822 /* senderrbuf cleared in SPKTERRS below */
1825 if (errs & QIB_E_P_SPKTERRS) {
1826 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1827 !(ppd->lflags & QIBL_LINKACTIVE)) {
1829 * This can happen when trying to bring the link
1830 * up, but the IB link changes state at the "wrong"
1831 * time. The IB logic then complains that the packet
1832 * isn't valid. We don't want to confuse people, so
1833 * we just don't print them, except at debug
1835 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1836 (errs & QIB_E_P_LINK_PKTERRS),
1837 qib_7322p_error_msgs);
1839 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1841 qib_disarm_7322_senderrbufs(ppd);
1842 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1843 !(ppd->lflags & QIBL_LINKACTIVE)) {
1845 * This can happen when SMA is trying to bring the link
1846 * up, but the IB link changes state at the "wrong" time.
1847 * The IB logic then complains that the packet isn't
1848 * valid. We don't want to confuse people, so we just
1849 * don't print them, except at debug
1851 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1852 qib_7322p_error_msgs);
1853 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1857 qib_write_kreg_port(ppd, krp_errclear, errs);
1859 errs &= ~ignore_this_time;
1863 if (errs & QIB_E_P_RPKTERRS)
1864 qib_stats.sps_rcverrs++;
1865 if (errs & QIB_E_P_SPKTERRS)
1866 qib_stats.sps_txerrs++;
1868 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1870 if (errs & QIB_E_P_SDMAERRS)
1871 sdma_7322_p_errors(ppd, errs);
1873 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1877 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1878 ltstate = qib_7322_phys_portstate(ibcs);
1880 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1881 handle_serdes_issues(ppd, ibcs);
1882 if (!(ppd->cpspec->ibcctrl_a &
1883 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1885 * We got our interrupt, so init code should be
1886 * happy and not try alternatives. Now squelch
1887 * other "chatter" from link-negotiation (pre Init)
1889 ppd->cpspec->ibcctrl_a |=
1890 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1891 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1892 ppd->cpspec->ibcctrl_a);
1895 /* Update our picture of width and speed from chip */
1896 ppd->link_width_active =
1897 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1898 IB_WIDTH_4X : IB_WIDTH_1X;
1899 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1900 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1901 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1902 QIB_IB_DDR : QIB_IB_SDR;
1904 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1905 IB_PHYSPORTSTATE_DISABLED)
1906 qib_set_ib_7322_lstate(ppd, 0,
1907 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1910 * Since going into a recovery state causes the link
1911 * state to go down and since recovery is transitory,
1912 * it is better if we "miss" ever seeing the link
1913 * training state go into recovery (i.e., ignore this
1914 * transition for link state special handling purposes)
1915 * without updating lastibcstat.
1917 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1918 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1919 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1920 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1921 qib_handle_e_ibstatuschanged(ppd, ibcs);
1924 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1926 if (ppd->state_wanted & ppd->lflags)
1927 wake_up_interruptible(&ppd->state_wait);
1932 /* enable/disable chip from delivering interrupts */
1933 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1936 if (dd->flags & QIB_BADINTR)
1938 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1939 /* cause any pending enabled interrupts to be re-delivered */
1940 qib_write_kreg(dd, kr_intclear, 0ULL);
1941 if (dd->cspec->num_msix_entries) {
1942 /* and same for MSIx */
1943 u64 val = qib_read_kreg64(dd, kr_intgranted);
1945 qib_write_kreg(dd, kr_intgranted, val);
1948 qib_write_kreg(dd, kr_intmask, 0ULL);
1952 * Try to cleanup as much as possible for anything that might have gone
1953 * wrong while in freeze mode, such as pio buffers being written by user
1954 * processes (causing armlaunch), send errors due to going into freeze mode,
1955 * etc., and try to avoid causing extra interrupts while doing so.
1956 * Forcibly update the in-memory pioavail register copies after cleanup
1957 * because the chip won't do it while in freeze mode (the register values
1958 * themselves are kept correct).
1959 * Make sure that we don't lose any important interrupts by using the chip
1960 * feature that says that writing 0 to a bit in *clear that is set in
1961 * *status will cause an interrupt to be generated again (if allowed by
1963 * This is in chip-specific code because of all of the register accesses,
1964 * even though the details are similar on most chips.
1966 static void qib_7322_clear_freeze(struct qib_devdata *dd)
1970 /* disable error interrupts, to avoid confusion */
1971 qib_write_kreg(dd, kr_errmask, 0ULL);
1973 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1974 if (dd->pport[pidx].link_speed_supported)
1975 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1978 /* also disable interrupts; errormask is sometimes overwriten */
1979 qib_7322_set_intr_state(dd, 0);
1981 /* clear the freeze, and be sure chip saw it */
1982 qib_write_kreg(dd, kr_control, dd->control);
1983 qib_read_kreg32(dd, kr_scratch);
1986 * Force new interrupt if any hwerr, error or interrupt bits are
1987 * still set, and clear "safe" send packet errors related to freeze
1988 * and cancelling sends. Re-enable error interrupts before possible
1989 * force of re-interrupt on pending interrupts.
1991 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1992 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1993 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1994 /* We need to purge per-port errs and reset mask, too */
1995 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1996 if (!dd->pport[pidx].link_speed_supported)
1998 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
1999 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
2001 qib_7322_set_intr_state(dd, 1);
2004 /* no error handling to speak of */
2006 * qib_7322_handle_hwerrors - display hardware errors.
2007 * @dd: the qlogic_ib device
2008 * @msg: the output buffer
2009 * @msgl: the size of the output buffer
2011 * Use same msg buffer as regular errors to avoid excessive stack
2012 * use. Most hardware errors are catastrophic, but for right now,
2013 * we'll print them and continue. We reuse the same message buffer as
2014 * qib_handle_errors() to avoid excessive stack usage.
2016 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2023 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2026 if (hwerrs == ~0ULL) {
2027 qib_dev_err(dd, "Read of hardware error status failed "
2028 "(all bits set); ignoring\n");
2031 qib_stats.sps_hwerrs++;
2033 /* Always clear the error status register, except BIST fail */
2034 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2035 ~HWE_MASK(PowerOnBISTFailed));
2037 hwerrs &= dd->cspec->hwerrmask;
2039 /* no EEPROM logging, yet */
2042 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
2043 "(cleared)\n", (unsigned long long) hwerrs);
2045 ctrl = qib_read_kreg32(dd, kr_control);
2046 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2048 * No recovery yet...
2050 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2051 dd->cspec->stay_in_freeze) {
2053 * If any set that we aren't ignoring only make the
2054 * complaint once, in case it's stuck or recurring,
2055 * and we get here multiple times
2056 * Force link down, so switch knows, and
2057 * LEDs are turned off.
2059 if (dd->flags & QIB_INITTED)
2062 qib_7322_clear_freeze(dd);
2065 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2067 strlcpy(msg, "[Memory BIST test failed, "
2068 "InfiniPath hardware unusable]", msgl);
2069 /* ignore from now on, so disable until driver reloaded */
2070 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2071 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2074 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2076 /* Ignore esoteric PLL failures et al. */
2078 qib_dev_err(dd, "%s hardware error\n", msg);
2080 if (isfatal && !dd->diag_client) {
2081 qib_dev_err(dd, "Fatal Hardware Error, no longer"
2082 " usable, SN %.16s\n", dd->serial);
2084 * for /sys status file and user programs to print; if no
2085 * trailing brace is copied, we'll know it was truncated.
2088 snprintf(dd->freezemsg, dd->freezelen,
2090 qib_disable_after_error(dd);
2096 * qib_7322_init_hwerrors - enable hardware errors
2097 * @dd: the qlogic_ib device
2099 * now that we have finished initializing everything that might reasonably
2100 * cause a hardware error, and cleared those errors bits as they occur,
2101 * we can enable hardware errors in the mask (potentially enabling
2102 * freeze mode), and enable hardware errors as errors (along with
2103 * everything else) in errormask
2105 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2110 extsval = qib_read_kreg64(dd, kr_extstatus);
2111 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2112 QIB_EXTS_MEMBIST_ENDTEST)))
2113 qib_dev_err(dd, "MemBIST did not complete!\n");
2115 /* never clear BIST failure, so reported on each driver load */
2116 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2117 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2120 qib_write_kreg(dd, kr_errclear, ~0ULL);
2121 /* enable errors that are masked, at least this first time. */
2122 qib_write_kreg(dd, kr_errmask, ~0ULL);
2123 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2124 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2125 if (dd->pport[pidx].link_speed_supported)
2126 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2131 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2132 * on chips that are count-based, rather than trigger-based. There is no
2133 * reference counting, but that's also fine, given the intended use.
2134 * Only chip-specific because it's all register accesses
2136 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2139 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2140 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2142 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2143 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2147 * Formerly took parameter <which> in pre-shifted,
2148 * pre-merged form with LinkCmd and LinkInitCmd
2149 * together, and assuming the zero was NOP.
2151 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2155 struct qib_devdata *dd = ppd->dd;
2156 unsigned long flags;
2158 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2160 * If we are told to disable, note that so link-recovery
2161 * code does not attempt to bring us back up.
2162 * Also reset everything that we can, so we start
2163 * completely clean when re-enabled (before we
2164 * actually issue the disable to the IBC)
2166 qib_7322_mini_pcs_reset(ppd);
2167 spin_lock_irqsave(&ppd->lflags_lock, flags);
2168 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2169 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2170 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2172 * Any other linkinitcmd will lead to LINKDOWN and then
2173 * to INIT (if all is well), so clear flag to let
2174 * link-recovery code attempt to bring us back up.
2176 spin_lock_irqsave(&ppd->lflags_lock, flags);
2177 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2178 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2180 * Clear status change interrupt reduction so the
2181 * new state is seen.
2183 ppd->cpspec->ibcctrl_a &=
2184 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2187 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2188 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2190 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2192 /* write to chip to prevent back-to-back writes of ibc reg */
2193 qib_write_kreg(dd, kr_scratch, 0);
2198 * The total RCV buffer memory is 64KB, used for both ports, and is
2199 * in units of 64 bytes (same as IB flow control credit unit).
2200 * The consumedVL unit in the same registers are in 32 byte units!
2201 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2202 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2203 * in krp_rxcreditvl15, rather than 10.
2205 #define RCV_BUF_UNITSZ 64
2206 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2208 static void set_vls(struct qib_pportdata *ppd)
2210 int i, numvls, totcred, cred_vl, vl0extra;
2211 struct qib_devdata *dd = ppd->dd;
2214 numvls = qib_num_vls(ppd->vls_operational);
2217 * Set up per-VL credits. Below is kluge based on these assumptions:
2218 * 1) port is disabled at the time early_init is called.
2219 * 2) give VL15 17 credits, for two max-plausible packets.
2220 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2222 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2223 totcred = NUM_RCV_BUF_UNITS(dd);
2224 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2226 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2227 cred_vl = totcred / numvls;
2228 vl0extra = totcred - cred_vl * numvls;
2229 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2230 for (i = 1; i < numvls; i++)
2231 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2232 for (; i < 8; i++) /* no buffer space for other VLs */
2233 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2235 /* Notify IBC that credits need to be recalculated */
2236 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2237 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2238 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2239 qib_write_kreg(dd, kr_scratch, 0ULL);
2240 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2241 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2243 for (i = 0; i < numvls; i++)
2244 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2245 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2247 /* Change the number of operational VLs */
2248 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2249 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2250 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2251 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2252 qib_write_kreg(dd, kr_scratch, 0ULL);
2256 * The code that deals with actual SerDes is in serdes_7322_init().
2257 * Compared to the code for iba7220, it is minimal.
2259 static int serdes_7322_init(struct qib_pportdata *ppd);
2262 * qib_7322_bringup_serdes - bring up the serdes
2263 * @ppd: physical port on the qlogic_ib device
2265 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2267 struct qib_devdata *dd = ppd->dd;
2269 unsigned long flags;
2273 * SerDes model not in Pd, but still need to
2274 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2277 /* Put IBC in reset, sends disabled (should be in reset already) */
2278 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2279 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2280 qib_write_kreg(dd, kr_scratch, 0ULL);
2282 /* ensure previous Tx parameters are not still forced */
2283 qib_write_kreg_port(ppd, krp_tx_deemph_override,
2284 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
2285 reset_tx_deemphasis_override));
2287 if (qib_compat_ddr_negotiate) {
2288 ppd->cpspec->ibdeltainprog = 1;
2289 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2291 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2292 crp_iblinkerrrecov);
2295 /* flowcontrolwatermark is in units of KBytes */
2296 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2298 * Flow control is sent this often, even if no changes in
2299 * buffer space occur. Units are 128ns for this chip.
2302 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2303 /* max error tolerance */
2304 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2305 /* IB credit flow control. */
2306 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2308 * set initial max size pkt IBC will send, including ICRC; it's the
2309 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2311 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2312 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2313 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2316 * Reset the PCS interface to the serdes (and also ibc, which is still
2317 * in reset from above). Writes new value of ibcctrl_a as last step.
2319 qib_7322_mini_pcs_reset(ppd);
2321 if (!ppd->cpspec->ibcctrl_b) {
2322 unsigned lse = ppd->link_speed_enabled;
2325 * Not on re-init after reset, establish shadow
2326 * and force initial config.
2328 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2330 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2331 IBA7322_IBC_SPEED_DDR |
2332 IBA7322_IBC_SPEED_SDR |
2333 IBA7322_IBC_WIDTH_AUTONEG |
2334 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2335 if (lse & (lse - 1)) /* Muliple speeds enabled */
2336 ppd->cpspec->ibcctrl_b |=
2337 (lse << IBA7322_IBC_SPEED_LSB) |
2338 IBA7322_IBC_IBTA_1_2_MASK |
2339 IBA7322_IBC_MAX_SPEED_MASK;
2341 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2342 IBA7322_IBC_SPEED_QDR |
2343 IBA7322_IBC_IBTA_1_2_MASK :
2344 (lse == QIB_IB_DDR) ?
2345 IBA7322_IBC_SPEED_DDR :
2346 IBA7322_IBC_SPEED_SDR;
2347 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2348 (IB_WIDTH_1X | IB_WIDTH_4X))
2349 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2351 ppd->cpspec->ibcctrl_b |=
2352 ppd->link_width_enabled == IB_WIDTH_4X ?
2353 IBA7322_IBC_WIDTH_4X_ONLY :
2354 IBA7322_IBC_WIDTH_1X_ONLY;
2356 /* always enable these on driver reload, not sticky */
2357 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2358 IBA7322_IBC_HRTBT_MASK);
2360 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2362 /* setup so we have more time at CFGTEST to change H1 */
2363 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2364 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2365 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2366 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2368 serdes_7322_init(ppd);
2370 guid = be64_to_cpu(ppd->guid);
2373 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2374 ppd->guid = cpu_to_be64(guid);
2377 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2378 /* write to chip to prevent back-to-back writes of ibc reg */
2379 qib_write_kreg(dd, kr_scratch, 0);
2382 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2385 /* initially come up DISABLED, without sending anything. */
2386 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2387 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2388 qib_write_kreg_port(ppd, krp_ibcctrl_a, val);
2389 qib_write_kreg(dd, kr_scratch, 0ULL);
2390 /* clear the linkinit cmds */
2391 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd);
2393 /* be paranoid against later code motion, etc. */
2394 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2395 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2396 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2397 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2399 /* Also enable IBSTATUSCHG interrupt. */
2400 val = qib_read_kreg_port(ppd, krp_errmask);
2401 qib_write_kreg_port(ppd, krp_errmask,
2402 val | ERR_MASK_N(IBStatusChanged));
2404 /* Always zero until we start messing with SerDes for real */
2409 * qib_7322_quiet_serdes - set serdes to txidle
2410 * @dd: the qlogic_ib device
2411 * Called when driver is being unloaded
2413 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2416 unsigned long flags;
2418 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2420 spin_lock_irqsave(&ppd->lflags_lock, flags);
2421 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2422 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2423 wake_up(&ppd->cpspec->autoneg_wait);
2424 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
2425 if (ppd->dd->cspec->r1)
2426 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2428 ppd->cpspec->chase_end = 0;
2429 if (ppd->cpspec->chase_timer.data) /* if initted */
2430 del_timer_sync(&ppd->cpspec->chase_timer);
2433 * Despite the name, actually disables IBC as well. Do it when
2434 * we are as sure as possible that no more packets can be
2435 * received, following the down and the PCS reset.
2436 * The actual disabling happens in qib_7322_mini_pci_reset(),
2437 * along with the PCS being reset.
2439 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2440 qib_7322_mini_pcs_reset(ppd);
2443 * Update the adjusted counters so the adjustment persists
2444 * across driver reload.
2446 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2447 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2448 struct qib_devdata *dd = ppd->dd;
2451 /* enable counter writes */
2452 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2453 qib_write_kreg(dd, kr_hwdiagctrl,
2454 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2456 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2457 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2458 if (ppd->cpspec->ibdeltainprog)
2459 val -= val - ppd->cpspec->ibsymsnap;
2460 val -= ppd->cpspec->ibsymdelta;
2461 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2463 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2464 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2465 if (ppd->cpspec->ibdeltainprog)
2466 val -= val - ppd->cpspec->iblnkerrsnap;
2467 val -= ppd->cpspec->iblnkerrdelta;
2468 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2470 if (ppd->cpspec->iblnkdowndelta) {
2471 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2472 val += ppd->cpspec->iblnkdowndelta;
2473 write_7322_creg_port(ppd, crp_iblinkdown, val);
2476 * No need to save ibmalfdelta since IB perfcounters
2477 * are cleared on driver reload.
2480 /* and disable counter writes */
2481 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2486 * qib_setup_7322_setextled - set the state of the two external LEDs
2487 * @ppd: physical port on the qlogic_ib device
2488 * @on: whether the link is up or not
2490 * The exact combo of LEDs if on is true is determined by looking
2493 * These LEDs indicate the physical and logical state of IB link.
2494 * For this chip (at least with recommended board pinouts), LED1
2495 * is Yellow (logical state) and LED2 is Green (physical state),
2497 * Note: We try to match the Mellanox HCA LED behavior as best
2498 * we can. Green indicates physical link state is OK (something is
2499 * plugged in, and we can train).
2500 * Amber indicates the link is logically up (ACTIVE).
2501 * Mellanox further blinks the amber LED to indicate data packet
2502 * activity, but we have no hardware support for that, so it would
2503 * require waking up every 10-20 msecs and checking the counters
2504 * on the chip, and then turning the LED off if appropriate. That's
2505 * visible overhead, so not something we will do.
2507 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2509 struct qib_devdata *dd = ppd->dd;
2510 u64 extctl, ledblink = 0, val;
2511 unsigned long flags;
2515 * The diags use the LED to indicate diag info, so we leave
2516 * the external LED alone when the diags are running.
2518 if (dd->diag_client)
2521 /* Allow override of LED display for, e.g. Locating system in rack */
2522 if (ppd->led_override) {
2523 grn = (ppd->led_override & QIB_LED_PHYS);
2524 yel = (ppd->led_override & QIB_LED_LOG);
2526 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2527 grn = qib_7322_phys_portstate(val) ==
2528 IB_PHYSPORTSTATE_LINKUP;
2529 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2535 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2536 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2537 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2539 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2541 * Counts are in chip clock (4ns) periods.
2542 * This is 1/16 sec (66.6ms) on,
2543 * 3/16 sec (187.5 ms) off, with packets rcvd.
2545 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2546 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2549 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2550 dd->cspec->extctrl = extctl;
2551 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2552 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2554 if (ledblink) /* blink the LED on packet receive */
2555 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2559 * Disable MSIx interrupt if enabled, call generic MSIx code
2560 * to cleanup, and clear pending MSIx interrupts.
2561 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2563 static void qib_7322_nomsix(struct qib_devdata *dd)
2568 dd->cspec->main_int_mask = ~0ULL;
2569 n = dd->cspec->num_msix_entries;
2573 dd->cspec->num_msix_entries = 0;
2574 for (i = 0; i < n; i++)
2575 free_irq(dd->cspec->msix_entries[i].vector,
2576 dd->cspec->msix_arg[i]);
2579 /* make sure no MSIx interrupts are left pending */
2580 intgranted = qib_read_kreg64(dd, kr_intgranted);
2582 qib_write_kreg(dd, kr_intgranted, intgranted);
2585 static void qib_7322_free_irq(struct qib_devdata *dd)
2587 if (dd->cspec->irq) {
2588 free_irq(dd->cspec->irq, dd);
2591 qib_7322_nomsix(dd);
2594 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2598 qib_7322_free_irq(dd);
2599 kfree(dd->cspec->cntrs);
2600 kfree(dd->cspec->sendchkenable);
2601 kfree(dd->cspec->sendgrhchk);
2602 kfree(dd->cspec->sendibchk);
2603 kfree(dd->cspec->msix_entries);
2604 kfree(dd->cspec->msix_arg);
2605 for (i = 0; i < dd->num_pports; i++) {
2606 unsigned long flags;
2607 u32 mask = QSFP_GPIO_MOD_PRS_N |
2608 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2610 kfree(dd->pport[i].cpspec->portcntrs);
2611 if (dd->flags & QIB_HAS_QSFP) {
2612 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2613 dd->cspec->gpio_mask &= ~mask;
2614 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2615 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2616 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2618 if (dd->pport[i].ibport_data.smi_ah)
2619 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2623 /* handle SDMA interrupts */
2624 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2626 struct qib_pportdata *ppd0 = &dd->pport[0];
2627 struct qib_pportdata *ppd1 = &dd->pport[1];
2628 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2629 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2630 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2631 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2634 qib_sdma_intr(ppd0);
2636 qib_sdma_intr(ppd1);
2638 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2639 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2640 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2641 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2645 * Set or clear the Send buffer available interrupt enable bit.
2647 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2649 unsigned long flags;
2651 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2653 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2655 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2656 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2657 qib_write_kreg(dd, kr_scratch, 0ULL);
2658 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2662 * Somehow got an interrupt with reserved bits set in interrupt status.
2663 * Print a message so we know it happened, then clear them.
2664 * keep mainline interrupt handler cache-friendly
2666 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2671 kills = istat & ~QIB_I_BITSEXTANT;
2672 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:"
2673 " %s\n", (unsigned long long) kills, msg);
2674 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2677 /* keep mainline interrupt handler cache-friendly */
2678 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2685 * Boards for this chip currently don't use GPIO interrupts,
2686 * so clear by writing GPIOstatus to GPIOclear, and complain
2687 * to developer. To avoid endless repeats, clear
2688 * the bits in the mask, since there is some kind of
2689 * programming error or chip problem.
2691 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2693 * In theory, writing GPIOstatus to GPIOclear could
2694 * have a bad side-effect on some diagnostic that wanted
2695 * to poll for a status-change, but the various shadows
2696 * make that problematic at best. Diags will just suppress
2697 * all GPIO interrupts during such tests.
2699 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2701 * Check for QSFP MOD_PRS changes
2702 * only works for single port if IB1 != pidx1
2704 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2706 struct qib_pportdata *ppd;
2707 struct qib_qsfp_data *qd;
2709 if (!dd->pport[pidx].link_speed_supported)
2711 mask = QSFP_GPIO_MOD_PRS_N;
2712 ppd = dd->pport + pidx;
2713 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2714 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2716 qd = &ppd->cpspec->qsfp_data;
2717 gpiostatus &= ~mask;
2718 pins = qib_read_kreg64(dd, kr_extstatus);
2719 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2720 if (!(pins & mask)) {
2722 qd->t_insert = get_jiffies_64();
2723 queue_work(ib_wq, &qd->work);
2728 if (gpiostatus && !handled) {
2729 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2730 u32 gpio_irq = mask & gpiostatus;
2733 * Clear any troublemakers, and update chip from shadow
2735 dd->cspec->gpio_mask &= ~gpio_irq;
2736 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2741 * Handle errors and unusual events first, separate function
2742 * to improve cache hits for fast path interrupt handling.
2744 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2746 if (istat & ~QIB_I_BITSEXTANT)
2747 unknown_7322_ibits(dd, istat);
2748 if (istat & QIB_I_GPIO)
2749 unknown_7322_gpio_intr(dd);
2750 if (istat & QIB_I_C_ERROR) {
2751 qib_write_kreg(dd, kr_errmask, 0ULL);
2752 tasklet_schedule(&dd->error_tasklet);
2754 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2755 handle_7322_p_errors(dd->rcd[0]->ppd);
2756 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2757 handle_7322_p_errors(dd->rcd[1]->ppd);
2761 * Dynamically adjust the rcv int timeout for a context based on incoming
2764 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2766 struct qib_devdata *dd = rcd->dd;
2767 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2770 * Dynamically adjust idle timeout on chip
2771 * based on number of packets processed.
2773 if (npkts < rcv_int_count && timeout > 2)
2775 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2776 timeout = min(timeout << 1, rcv_int_timeout);
2780 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2781 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2785 * This is the main interrupt handler.
2786 * It will normally only be used for low frequency interrupts but may
2787 * have to handle all interrupts if INTx is enabled or fewer than normal
2788 * MSIx interrupts were allocated.
2789 * This routine should ignore the interrupt bits for any of the
2790 * dedicated MSIx handlers.
2792 static irqreturn_t qib_7322intr(int irq, void *data)
2794 struct qib_devdata *dd = data;
2802 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2804 * This return value is not great, but we do not want the
2805 * interrupt core code to remove our interrupt handler
2806 * because we don't appear to be handling an interrupt
2807 * during a chip reset.
2813 istat = qib_read_kreg64(dd, kr_intstatus);
2815 if (unlikely(istat == ~0ULL)) {
2816 qib_bad_intrstatus(dd);
2817 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2818 /* don't know if it was our interrupt or not */
2823 istat &= dd->cspec->main_int_mask;
2824 if (unlikely(!istat)) {
2825 /* already handled, or shared and not us */
2830 qib_stats.sps_ints++;
2831 if (dd->int_counter != (u32) -1)
2834 /* handle "errors" of various kinds first, device ahead of port */
2835 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2836 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2837 INT_MASK_P(Err, 1))))
2838 unlikely_7322_intr(dd, istat);
2841 * Clear the interrupt bits we found set, relatively early, so we
2842 * "know" know the chip will have seen this by the time we process
2843 * the queue, and will re-interrupt if necessary. The processor
2844 * itself won't take the interrupt again until we return.
2846 qib_write_kreg(dd, kr_intclear, istat);
2849 * Handle kernel receive queues before checking for pio buffers
2850 * available since receives can overflow; piobuf waiters can afford
2851 * a few extra cycles, since they were waiting anyway.
2853 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2855 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2856 (1ULL << QIB_I_RCVURG_LSB);
2857 for (i = 0; i < dd->first_user_ctxt; i++) {
2858 if (ctxtrbits & rmask) {
2859 ctxtrbits &= ~rmask;
2861 qib_kreceive(dd->rcd[i], NULL, &npkts);
2866 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2867 (ctxtrbits >> QIB_I_RCVURG_LSB);
2868 qib_handle_urcv(dd, ctxtrbits);
2872 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2873 sdma_7322_intr(dd, istat);
2875 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2876 qib_ib_piobufavail(dd);
2884 * Dedicated receive packet available interrupt handler.
2886 static irqreturn_t qib_7322pintr(int irq, void *data)
2888 struct qib_ctxtdata *rcd = data;
2889 struct qib_devdata *dd = rcd->dd;
2892 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2894 * This return value is not great, but we do not want the
2895 * interrupt core code to remove our interrupt handler
2896 * because we don't appear to be handling an interrupt
2897 * during a chip reset.
2901 qib_stats.sps_ints++;
2902 if (dd->int_counter != (u32) -1)
2905 /* Clear the interrupt bit we expect to be set. */
2906 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2907 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2909 qib_kreceive(rcd, NULL, &npkts);
2915 * Dedicated Send buffer available interrupt handler.
2917 static irqreturn_t qib_7322bufavail(int irq, void *data)
2919 struct qib_devdata *dd = data;
2921 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2923 * This return value is not great, but we do not want the
2924 * interrupt core code to remove our interrupt handler
2925 * because we don't appear to be handling an interrupt
2926 * during a chip reset.
2930 qib_stats.sps_ints++;
2931 if (dd->int_counter != (u32) -1)
2934 /* Clear the interrupt bit we expect to be set. */
2935 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
2937 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
2938 if (dd->flags & QIB_INITTED)
2939 qib_ib_piobufavail(dd);
2941 qib_wantpiobuf_7322_intr(dd, 0);
2947 * Dedicated Send DMA interrupt handler.
2949 static irqreturn_t sdma_intr(int irq, void *data)
2951 struct qib_pportdata *ppd = data;
2952 struct qib_devdata *dd = ppd->dd;
2954 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2956 * This return value is not great, but we do not want the
2957 * interrupt core code to remove our interrupt handler
2958 * because we don't appear to be handling an interrupt
2959 * during a chip reset.
2963 qib_stats.sps_ints++;
2964 if (dd->int_counter != (u32) -1)
2967 /* Clear the interrupt bit we expect to be set. */
2968 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2969 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
2976 * Dedicated Send DMA idle interrupt handler.
2978 static irqreturn_t sdma_idle_intr(int irq, void *data)
2980 struct qib_pportdata *ppd = data;
2981 struct qib_devdata *dd = ppd->dd;
2983 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2985 * This return value is not great, but we do not want the
2986 * interrupt core code to remove our interrupt handler
2987 * because we don't appear to be handling an interrupt
2988 * during a chip reset.
2992 qib_stats.sps_ints++;
2993 if (dd->int_counter != (u32) -1)
2996 /* Clear the interrupt bit we expect to be set. */
2997 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2998 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
3005 * Dedicated Send DMA progress interrupt handler.
3007 static irqreturn_t sdma_progress_intr(int irq, void *data)
3009 struct qib_pportdata *ppd = data;
3010 struct qib_devdata *dd = ppd->dd;
3012 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3014 * This return value is not great, but we do not want the
3015 * interrupt core code to remove our interrupt handler
3016 * because we don't appear to be handling an interrupt
3017 * during a chip reset.
3021 qib_stats.sps_ints++;
3022 if (dd->int_counter != (u32) -1)
3025 /* Clear the interrupt bit we expect to be set. */
3026 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3027 INT_MASK_P(SDmaProgress, 1) :
3028 INT_MASK_P(SDmaProgress, 0));
3035 * Dedicated Send DMA cleanup interrupt handler.
3037 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3039 struct qib_pportdata *ppd = data;
3040 struct qib_devdata *dd = ppd->dd;
3042 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3044 * This return value is not great, but we do not want the
3045 * interrupt core code to remove our interrupt handler
3046 * because we don't appear to be handling an interrupt
3047 * during a chip reset.
3051 qib_stats.sps_ints++;
3052 if (dd->int_counter != (u32) -1)
3055 /* Clear the interrupt bit we expect to be set. */
3056 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3057 INT_MASK_PM(SDmaCleanupDone, 1) :
3058 INT_MASK_PM(SDmaCleanupDone, 0));
3059 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3065 * Set up our chip-specific interrupt handler.
3066 * The interrupt type has already been setup, so
3067 * we just need to do the registration and error checking.
3068 * If we are using MSIx interrupts, we may fall back to
3069 * INTx later, if the interrupt handler doesn't get called
3070 * within 1/2 second (see verify_interrupt()).
3072 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3074 int ret, i, msixnum;
3078 if (!dd->num_pports)
3083 * if not switching interrupt types, be sure interrupts are
3084 * disabled, and then clear anything pending at this point,
3085 * because we are starting clean.
3087 qib_7322_set_intr_state(dd, 0);
3089 /* clear the reset error, init error/hwerror mask */
3090 qib_7322_init_hwerrors(dd);
3092 /* clear any interrupt bits that might be set */
3093 qib_write_kreg(dd, kr_intclear, ~0ULL);
3095 /* make sure no pending MSIx intr, and clear diag reg */
3096 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3097 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3100 if (!dd->cspec->num_msix_entries) {
3101 /* Try to get INTx interrupt */
3103 if (!dd->pcidev->irq) {
3104 qib_dev_err(dd, "irq is 0, BIOS error? "
3105 "Interrupts won't work\n");
3108 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3109 IRQF_SHARED, QIB_DRV_NAME, dd);
3111 qib_dev_err(dd, "Couldn't setup INTx "
3112 "interrupt (irq=%d): %d\n",
3113 dd->pcidev->irq, ret);
3116 dd->cspec->irq = dd->pcidev->irq;
3117 dd->cspec->main_int_mask = ~0ULL;
3121 /* Try to get MSIx interrupts */
3122 memset(redirect, 0, sizeof redirect);
3125 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3126 irq_handler_t handler;
3132 if (i < ARRAY_SIZE(irq_table)) {
3133 if (irq_table[i].port) {
3134 /* skip if for a non-configured port */
3135 if (irq_table[i].port > dd->num_pports)
3137 arg = dd->pport + irq_table[i].port - 1;
3140 lsb = irq_table[i].lsb;
3141 handler = irq_table[i].handler;
3142 name = irq_table[i].name;
3146 ctxt = i - ARRAY_SIZE(irq_table);
3147 /* per krcvq context receive interrupt */
3148 arg = dd->rcd[ctxt];
3151 if (qib_krcvq01_no_msi && ctxt < 2)
3153 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3154 handler = qib_7322pintr;
3155 name = QIB_DRV_NAME " (kctx)";
3157 ret = request_irq(dd->cspec->msix_entries[msixnum].vector,
3158 handler, 0, name, arg);
3161 * Shouldn't happen since the enable said we could
3162 * have as many as we are trying to setup here.
3164 qib_dev_err(dd, "Couldn't setup MSIx "
3165 "interrupt (vec=%d, irq=%d): %d\n", msixnum,
3166 dd->cspec->msix_entries[msixnum].vector,
3168 qib_7322_nomsix(dd);
3171 dd->cspec->msix_arg[msixnum] = arg;
3173 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3174 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3175 SYM_LSB(IntRedirect0, vec1);
3176 mask &= ~(1ULL << lsb);
3177 redirect[reg] |= ((u64) msixnum) << sh;
3179 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3180 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3183 /* Initialize the vector mapping */
3184 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3185 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3186 dd->cspec->main_int_mask = mask;
3187 tasklet_init(&dd->error_tasklet, qib_error_tasklet,
3193 * qib_7322_boardname - fill in the board name and note features
3194 * @dd: the qlogic_ib device
3196 * info will be based on the board revision register
3198 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3200 /* Will need enumeration of board-types here */
3202 u32 boardid, namelen;
3203 unsigned features = DUAL_PORT_CAP;
3205 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3209 n = "InfiniPath_QLE7342_Emulation";
3212 n = "InfiniPath_QLE7340";
3213 dd->flags |= QIB_HAS_QSFP;
3214 features = PORT_SPD_CAP;
3217 n = "InfiniPath_QLE7342";
3218 dd->flags |= QIB_HAS_QSFP;
3221 n = "InfiniPath_QMI7342";
3224 n = "InfiniPath_Unsupported7342";
3225 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3229 n = "InfiniPath_QMH7342";
3233 n = "InfiniPath_QME7342";
3236 n = "InfiniPath_QME7362";
3237 dd->flags |= QIB_HAS_QSFP;
3240 n = "InfiniPath_QLE7342_TEST";
3241 dd->flags |= QIB_HAS_QSFP;
3244 n = "InfiniPath_QLE73xy_UNKNOWN";
3245 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3248 dd->board_atten = 1; /* index into txdds_Xdr */
3250 namelen = strlen(n) + 1;
3251 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3253 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3255 snprintf(dd->boardname, namelen, "%s", n);
3257 snprintf(dd->boardversion, sizeof(dd->boardversion),
3258 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3259 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3260 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3261 dd->majrev, dd->minrev,
3262 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3264 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3265 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode"
3266 " by module parameter\n", dd->unit);
3267 features &= PORT_SPD_CAP;
3274 * This routine sleeps, so it can only be called from user context, not
3275 * from interrupt context.
3277 static int qib_do_7322_reset(struct qib_devdata *dd)
3281 int i, msix_entries, ret = 1;
3283 u8 int_line, clinesz;
3284 unsigned long flags;
3286 /* Use dev_err so it shows up in logs, etc. */
3287 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3289 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3291 msix_entries = dd->cspec->num_msix_entries;
3293 /* no interrupts till re-initted */
3294 qib_7322_set_intr_state(dd, 0);
3297 qib_7322_nomsix(dd);
3298 /* can be up to 512 bytes, too big for stack */
3299 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3300 sizeof(u64), GFP_KERNEL);
3302 qib_dev_err(dd, "No mem to save MSIx data\n");
3304 msix_vecsave = NULL;
3307 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3308 * info that is set up by the BIOS, so we have to save and restore
3309 * it ourselves. There is some risk something could change it,
3310 * after we save it, but since we have disabled the MSIx, it
3311 * shouldn't be touched...
3313 for (i = 0; i < msix_entries; i++) {
3314 u64 vecaddr, vecdata;
3315 vecaddr = qib_read_kreg64(dd, 2 * i +
3316 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3317 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3318 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3320 msix_vecsave[2 * i] = vecaddr;
3321 /* save it without the masked bit set */
3322 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3326 dd->pport->cpspec->ibdeltainprog = 0;
3327 dd->pport->cpspec->ibsymdelta = 0;
3328 dd->pport->cpspec->iblnkerrdelta = 0;
3329 dd->pport->cpspec->ibmalfdelta = 0;
3330 dd->int_counter = 0; /* so we check interrupts work again */
3333 * Keep chip from being accessed until we are ready. Use
3334 * writeq() directly, to allow the write even though QIB_PRESENT
3337 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3338 dd->flags |= QIB_DOING_RESET;
3339 val = dd->control | QLOGIC_IB_C_RESET;
3340 writeq(val, &dd->kregbase[kr_control]);
3342 for (i = 1; i <= 5; i++) {
3344 * Allow MBIST, etc. to complete; longer on each retry.
3345 * We sometimes get machine checks from bus timeout if no
3346 * response, so for now, make it *really* long.
3348 msleep(1000 + (1 + i) * 3000);
3350 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3353 * Use readq directly, so we don't need to mark it as PRESENT
3354 * until we get a successful indication that all is well.
3356 val = readq(&dd->kregbase[kr_revision]);
3357 if (val == dd->revision)
3360 qib_dev_err(dd, "Failed to initialize after reset, "
3367 dd->flags |= QIB_PRESENT; /* it's back */
3370 /* restore the MSIx vector address and data if saved above */
3371 for (i = 0; i < msix_entries; i++) {
3372 dd->cspec->msix_entries[i].entry = i;
3373 if (!msix_vecsave || !msix_vecsave[2 * i])
3375 qib_write_kreg(dd, 2 * i +
3376 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3377 msix_vecsave[2 * i]);
3378 qib_write_kreg(dd, 1 + 2 * i +
3379 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3380 msix_vecsave[1 + 2 * i]);
3384 /* initialize the remaining registers. */
3385 for (i = 0; i < dd->num_pports; ++i)
3386 write_7322_init_portregs(&dd->pport[i]);
3387 write_7322_initregs(dd);
3389 if (qib_pcie_params(dd, dd->lbus_width,
3390 &dd->cspec->num_msix_entries,
3391 dd->cspec->msix_entries))
3392 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; "
3393 "continuing anyway\n");
3395 qib_setup_7322_interrupt(dd, 1);
3397 for (i = 0; i < dd->num_pports; ++i) {
3398 struct qib_pportdata *ppd = &dd->pport[i];
3400 spin_lock_irqsave(&ppd->lflags_lock, flags);
3401 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3402 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3403 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3407 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3408 kfree(msix_vecsave);
3413 * qib_7322_put_tid - write a TID to the chip
3414 * @dd: the qlogic_ib device
3415 * @tidptr: pointer to the expected TID (in chip) to update
3416 * @tidtype: 0 for eager, 1 for expected
3417 * @pa: physical address of in memory buffer; tidinvalid if freeing
3419 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3420 u32 type, unsigned long pa)
3422 if (!(dd->flags & QIB_PRESENT))
3424 if (pa != dd->tidinvalid) {
3425 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3427 /* paranoia checks */
3428 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3429 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3433 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3434 qib_dev_err(dd, "Physical page address 0x%lx "
3435 "larger than supported\n", pa);
3439 if (type == RCVHQ_RCV_TYPE_EAGER)
3440 chippa |= dd->tidtemplate;
3441 else /* for now, always full 4KB page */
3442 chippa |= IBA7322_TID_SZ_4K;
3450 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3451 * @dd: the qlogic_ib device
3454 * clear all TID entries for a ctxt, expected and eager.
3455 * Used from qib_close().
3457 static void qib_7322_clear_tids(struct qib_devdata *dd,
3458 struct qib_ctxtdata *rcd)
3460 u64 __iomem *tidbase;
3461 unsigned long tidinv;
3465 if (!dd->kregbase || !rcd)
3470 tidinv = dd->tidinvalid;
3471 tidbase = (u64 __iomem *)
3472 ((char __iomem *) dd->kregbase +
3474 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3476 for (i = 0; i < dd->rcvtidcnt; i++)
3477 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3480 tidbase = (u64 __iomem *)
3481 ((char __iomem *) dd->kregbase +
3483 rcd->rcvegr_tid_base * sizeof(*tidbase));
3485 for (i = 0; i < rcd->rcvegrcnt; i++)
3486 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3491 * qib_7322_tidtemplate - setup constants for TID updates
3492 * @dd: the qlogic_ib device
3494 * We setup stuff that we use a lot, to avoid calculating each time
3496 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3499 * For now, we always allocate 4KB buffers (at init) so we can
3500 * receive max size packets. We may want a module parameter to
3501 * specify 2KB or 4KB and/or make it per port instead of per device
3502 * for those who want to reduce memory footprint. Note that the
3503 * rcvhdrentsize size must be large enough to hold the largest
3504 * IB header (currently 96 bytes) that we expect to handle (plus of
3505 * course the 2 dwords of RHF).
3507 if (dd->rcvegrbufsize == 2048)
3508 dd->tidtemplate = IBA7322_TID_SZ_2K;
3509 else if (dd->rcvegrbufsize == 4096)
3510 dd->tidtemplate = IBA7322_TID_SZ_4K;
3515 * qib_init_7322_get_base_info - set chip-specific flags for user code
3516 * @rcd: the qlogic_ib ctxt
3517 * @kbase: qib_base_info pointer
3519 * We set the PCIE flag because the lower bandwidth on PCIe vs
3520 * HyperTransport can affect some user packet algorithims.
3523 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3524 struct qib_base_info *kinfo)
3526 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3527 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3528 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3529 if (rcd->dd->cspec->r1)
3530 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3531 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3532 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3537 static struct qib_message_header *
3538 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3540 u32 offset = qib_hdrget_offset(rhf_addr);
3542 return (struct qib_message_header *)
3543 (rhf_addr - dd->rhf_offset + offset);
3547 * Configure number of contexts.
3549 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3551 unsigned long flags;
3554 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3555 dd->cspec->numctxts = nchipctxts;
3556 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3557 dd->first_user_ctxt = NUM_IB_PORTS +
3558 (qib_n_krcv_queues - 1) * dd->num_pports;
3559 if (dd->first_user_ctxt > nchipctxts)
3560 dd->first_user_ctxt = nchipctxts;
3561 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3563 dd->first_user_ctxt = NUM_IB_PORTS;
3564 dd->n_krcv_queues = 1;
3567 if (!qib_cfgctxts) {
3568 int nctxts = dd->first_user_ctxt + num_online_cpus();
3572 else if (nctxts <= 10)
3574 else if (nctxts <= nchipctxts)
3575 dd->ctxtcnt = nchipctxts;
3576 } else if (qib_cfgctxts < dd->num_pports)
3577 dd->ctxtcnt = dd->num_pports;
3578 else if (qib_cfgctxts <= nchipctxts)
3579 dd->ctxtcnt = qib_cfgctxts;
3580 if (!dd->ctxtcnt) /* none of the above, set to max */
3581 dd->ctxtcnt = nchipctxts;
3584 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3585 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3586 * Lock to be paranoid about later motion, etc.
3588 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3589 if (dd->ctxtcnt > 10)
3590 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3591 else if (dd->ctxtcnt > 6)
3592 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3593 /* else configure for default 6 receive ctxts */
3595 /* The XRC opcode is 5. */
3596 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3599 * RcvCtrl *must* be written here so that the
3600 * chip understands how to change rcvegrcnt below.
3602 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3603 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3605 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3606 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3608 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3610 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
3611 dd->num_pports > 1 ? 1024U : 2048U);
3614 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3618 u64 maskr; /* right-justified mask */
3622 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
3623 ret = ppd->link_width_enabled;
3626 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
3627 ret = ppd->link_width_active;
3630 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
3631 ret = ppd->link_speed_enabled;
3634 case QIB_IB_CFG_SPD: /* Get current Link spd */
3635 ret = ppd->link_speed_active;
3638 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
3639 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3640 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3643 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
3644 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3645 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3648 case QIB_IB_CFG_LINKLATENCY:
3649 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3650 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3653 case QIB_IB_CFG_OP_VLS:
3654 ret = ppd->vls_operational;
3657 case QIB_IB_CFG_VL_HIGH_CAP:
3661 case QIB_IB_CFG_VL_LOW_CAP:
3665 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3666 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3670 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3671 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3675 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3676 /* will only take effect when the link state changes */
3677 ret = (ppd->cpspec->ibcctrl_a &
3678 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3679 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3682 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
3683 lsb = IBA7322_IBC_HRTBT_LSB;
3684 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3687 case QIB_IB_CFG_PMA_TICKS:
3689 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3690 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3692 if (ppd->link_speed_active == QIB_IB_QDR)
3694 else if (ppd->link_speed_active == QIB_IB_DDR)
3704 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3710 * Below again cribbed liberally from older version. Do not lean
3713 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3714 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3715 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3717 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3719 struct qib_devdata *dd = ppd->dd;
3720 u64 maskr; /* right-justified mask */
3723 unsigned long flags;
3726 case QIB_IB_CFG_LIDLMC:
3728 * Set LID and LMC. Combined to avoid possible hazard
3729 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3731 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3732 maskr = IBA7322_IBC_DLIDLMC_MASK;
3734 * For header-checking, the SLID in the packet will
3735 * be masked with SendIBSLMCMask, and compared
3736 * with SendIBSLIDAssignMask. Make sure we do not
3737 * set any bits not covered by the mask, or we get
3740 qib_write_kreg_port(ppd, krp_sendslid,
3741 val & (val >> 16) & SendIBSLIDAssignMask);
3742 qib_write_kreg_port(ppd, krp_sendslidmask,
3743 (val >> 16) & SendIBSLMCMask);
3746 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
3747 ppd->link_width_enabled = val;
3748 /* convert IB value to chip register value */
3749 if (val == IB_WIDTH_1X)
3751 else if (val == IB_WIDTH_4X)
3755 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3756 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3759 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
3761 * As with width, only write the actual register if the
3762 * link is currently down, otherwise takes effect on next
3763 * link change. Since setting is being explicitly requested
3764 * (via MAD or sysfs), clear autoneg failure status if speed
3765 * autoneg is enabled.
3767 ppd->link_speed_enabled = val;
3768 val <<= IBA7322_IBC_SPEED_LSB;
3769 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3770 IBA7322_IBC_MAX_SPEED_MASK;
3771 if (val & (val - 1)) {
3772 /* Muliple speeds enabled */
3773 val |= IBA7322_IBC_IBTA_1_2_MASK |
3774 IBA7322_IBC_MAX_SPEED_MASK;
3775 spin_lock_irqsave(&ppd->lflags_lock, flags);
3776 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3777 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3778 } else if (val & IBA7322_IBC_SPEED_QDR)
3779 val |= IBA7322_IBC_IBTA_1_2_MASK;
3780 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3781 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3784 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
3785 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3786 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3789 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
3790 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3791 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3794 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3795 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3798 ppd->cpspec->ibcctrl_a &=
3799 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3800 ppd->cpspec->ibcctrl_a |= (u64) val <<
3801 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3802 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3803 ppd->cpspec->ibcctrl_a);
3804 qib_write_kreg(dd, kr_scratch, 0ULL);
3808 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3809 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3812 ppd->cpspec->ibcctrl_a &=
3813 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3814 ppd->cpspec->ibcctrl_a |= (u64) val <<
3815 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3816 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3817 ppd->cpspec->ibcctrl_a);
3818 qib_write_kreg(dd, kr_scratch, 0ULL);
3822 case QIB_IB_CFG_PKEYS: /* update pkeys */
3823 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3824 ((u64) ppd->pkeys[2] << 32) |
3825 ((u64) ppd->pkeys[3] << 48);
3826 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3829 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3830 /* will only take effect when the link state changes */
3831 if (val == IB_LINKINITCMD_POLL)
3832 ppd->cpspec->ibcctrl_a &=
3833 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3835 ppd->cpspec->ibcctrl_a |=
3836 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3837 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3838 qib_write_kreg(dd, kr_scratch, 0ULL);
3841 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
3843 * Update our housekeeping variables, and set IBC max
3844 * size, same as init code; max IBC is max we allow in
3845 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3846 * Set even if it's unchanged, print debug message only
3849 val = (ppd->ibmaxlen >> 2) + 1;
3850 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3851 ppd->cpspec->ibcctrl_a |= (u64)val <<
3852 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3853 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3854 ppd->cpspec->ibcctrl_a);
3855 qib_write_kreg(dd, kr_scratch, 0ULL);
3858 case QIB_IB_CFG_LSTATE: /* set the IB link state */
3859 switch (val & 0xffff0000) {
3860 case IB_LINKCMD_DOWN:
3861 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3862 ppd->cpspec->ibmalfusesnap = 1;
3863 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3865 if (!ppd->cpspec->ibdeltainprog &&
3866 qib_compat_ddr_negotiate) {
3867 ppd->cpspec->ibdeltainprog = 1;
3868 ppd->cpspec->ibsymsnap =
3869 read_7322_creg32_port(ppd,
3871 ppd->cpspec->iblnkerrsnap =
3872 read_7322_creg32_port(ppd,
3873 crp_iblinkerrrecov);
3877 case IB_LINKCMD_ARMED:
3878 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3879 if (ppd->cpspec->ibmalfusesnap) {
3880 ppd->cpspec->ibmalfusesnap = 0;
3881 ppd->cpspec->ibmalfdelta +=
3882 read_7322_creg32_port(ppd,
3884 ppd->cpspec->ibmalfsnap;
3888 case IB_LINKCMD_ACTIVE:
3889 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3894 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3897 switch (val & 0xffff) {
3898 case IB_LINKINITCMD_NOP:
3902 case IB_LINKINITCMD_POLL:
3903 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
3906 case IB_LINKINITCMD_SLEEP:
3907 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
3910 case IB_LINKINITCMD_DISABLE:
3911 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
3912 ppd->cpspec->chase_end = 0;
3914 * stop state chase counter and timer, if running.
3915 * wait forpending timer, but don't clear .data (ppd)!
3917 if (ppd->cpspec->chase_timer.expires) {
3918 del_timer_sync(&ppd->cpspec->chase_timer);
3919 ppd->cpspec->chase_timer.expires = 0;
3925 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
3929 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
3932 case QIB_IB_CFG_OP_VLS:
3933 if (ppd->vls_operational != val) {
3934 ppd->vls_operational = val;
3939 case QIB_IB_CFG_VL_HIGH_LIMIT:
3940 qib_write_kreg_port(ppd, krp_highprio_limit, val);
3943 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
3948 lsb = IBA7322_IBC_HRTBT_LSB;
3949 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3952 case QIB_IB_CFG_PORT:
3953 /* val is the port number of the switch we are connected to. */
3954 if (ppd->dd->cspec->r1) {
3955 cancel_delayed_work(&ppd->cpspec->ipg_work);
3956 ppd->cpspec->ipg_tries = 0;
3964 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
3965 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
3966 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
3967 qib_write_kreg(dd, kr_scratch, 0);
3972 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
3977 /* only IBC loopback, may add serdes and xgxs loopbacks later */
3978 if (!strncmp(what, "ibc", 3)) {
3979 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
3981 val = 0; /* disable heart beat, so link will come up */
3982 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
3983 ppd->dd->unit, ppd->port);
3984 } else if (!strncmp(what, "off", 3)) {
3985 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
3987 /* enable heart beat again */
3988 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
3989 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
3990 "(normal)\n", ppd->dd->unit, ppd->port);
3994 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3995 ppd->cpspec->ibcctrl_a);
3996 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
3997 << IBA7322_IBC_HRTBT_LSB);
3998 ppd->cpspec->ibcctrl_b = ctrlb | val;
3999 qib_write_kreg_port(ppd, krp_ibcctrl_b,
4000 ppd->cpspec->ibcctrl_b);
4001 qib_write_kreg(ppd->dd, kr_scratch, 0);
4006 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4007 struct ib_vl_weight_elem *vl)
4011 for (i = 0; i < 16; i++, regno++, vl++) {
4012 u32 val = qib_read_kreg_port(ppd, regno);
4014 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
4015 SYM_RMASK(LowPriority0_0, VirtualLane);
4016 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
4017 SYM_RMASK(LowPriority0_0, Weight);
4021 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4022 struct ib_vl_weight_elem *vl)
4026 for (i = 0; i < 16; i++, regno++, vl++) {
4029 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4030 SYM_LSB(LowPriority0_0, VirtualLane)) |
4031 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4032 SYM_LSB(LowPriority0_0, Weight));
4033 qib_write_kreg_port(ppd, regno, val);
4035 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4036 struct qib_devdata *dd = ppd->dd;
4037 unsigned long flags;
4039 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4040 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4041 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4042 qib_write_kreg(dd, kr_scratch, 0);
4043 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4047 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4050 case QIB_IB_TBL_VL_HIGH_ARB:
4051 get_vl_weights(ppd, krp_highprio_0, t);
4054 case QIB_IB_TBL_VL_LOW_ARB:
4055 get_vl_weights(ppd, krp_lowprio_0, t);
4064 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4067 case QIB_IB_TBL_VL_HIGH_ARB:
4068 set_vl_weights(ppd, krp_highprio_0, t);
4071 case QIB_IB_TBL_VL_LOW_ARB:
4072 set_vl_weights(ppd, krp_lowprio_0, t);
4081 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4082 u32 updegr, u32 egrhd, u32 npkts)
4085 * Need to write timeout register before updating rcvhdrhead to ensure
4086 * that the timer is enabled on reception of a packet.
4088 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4089 adjust_rcv_timeout(rcd, npkts);
4091 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4093 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4094 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4098 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4102 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4103 if (rcd->rcvhdrtail_kvaddr)
4104 tail = qib_get_rcvhdrtail(rcd);
4106 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4107 return head == tail;
4110 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4111 QIB_RCVCTRL_CTXT_DIS | \
4112 QIB_RCVCTRL_TIDFLOW_ENB | \
4113 QIB_RCVCTRL_TIDFLOW_DIS | \
4114 QIB_RCVCTRL_TAILUPD_ENB | \
4115 QIB_RCVCTRL_TAILUPD_DIS | \
4116 QIB_RCVCTRL_INTRAVAIL_ENB | \
4117 QIB_RCVCTRL_INTRAVAIL_DIS | \
4118 QIB_RCVCTRL_BP_ENB | \
4121 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4122 QIB_RCVCTRL_CTXT_DIS | \
4123 QIB_RCVCTRL_PKEY_DIS | \
4124 QIB_RCVCTRL_PKEY_ENB)
4127 * Modify the RCVCTRL register in chip-specific way. This
4128 * is a function because bit positions and (future) register
4129 * location is chip-specifc, but the needed operations are
4130 * generic. <op> is a bit-mask because we often want to
4131 * do multiple modifications.
4133 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4136 struct qib_devdata *dd = ppd->dd;
4137 struct qib_ctxtdata *rcd;
4139 unsigned long flags;
4141 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4143 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4144 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4145 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4146 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4147 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4148 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4149 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4150 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4151 if (op & QIB_RCVCTRL_PKEY_ENB)
4152 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4153 if (op & QIB_RCVCTRL_PKEY_DIS)
4154 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4156 mask = (1ULL << dd->ctxtcnt) - 1;
4159 mask = (1ULL << ctxt);
4160 rcd = dd->rcd[ctxt];
4162 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4164 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4165 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4166 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4167 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4169 /* Write these registers before the context is enabled. */
4170 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4171 rcd->rcvhdrqtailaddr_phys);
4172 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4176 if (op & QIB_RCVCTRL_CTXT_DIS)
4178 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4179 if (op & QIB_RCVCTRL_BP_ENB)
4180 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4181 if (op & QIB_RCVCTRL_BP_DIS)
4182 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4183 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4184 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4185 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4186 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4188 * Decide which registers to write depending on the ops enabled.
4189 * Special case is "flush" (no bits set at all)
4190 * which needs to write both.
4192 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4193 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4194 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4195 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4196 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4198 * Init the context registers also; if we were
4199 * disabled, tail and head should both be zero
4200 * already from the enable, but since we don't
4201 * know, we have to do it explicitly.
4203 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4204 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4206 /* be sure enabling write seen; hd/tl should be 0 */
4207 (void) qib_read_kreg32(dd, kr_scratch);
4208 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4209 dd->rcd[ctxt]->head = val;
4210 /* If kctxt, interrupt on next receive. */
4211 if (ctxt < dd->first_user_ctxt)
4212 val |= dd->rhdrhead_intr_off;
4213 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4214 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4215 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4216 /* arm rcv interrupt */
4217 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4218 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4220 if (op & QIB_RCVCTRL_CTXT_DIS) {
4223 /* Now that the context is disabled, clear these registers. */
4225 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4226 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4227 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4228 qib_write_ureg(dd, ur_rcvflowtable + f,
4229 TIDFLOW_ERRBITS, ctxt);
4233 for (i = 0; i < dd->cfgctxts; i++) {
4234 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4236 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4237 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4238 qib_write_ureg(dd, ur_rcvflowtable + f,
4239 TIDFLOW_ERRBITS, i);
4243 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4247 * Modify the SENDCTRL register in chip-specific way. This
4248 * is a function where there are multiple such registers with
4249 * slightly different layouts.
4250 * The chip doesn't allow back-to-back sendctrl writes, so write
4251 * the scratch register after writing sendctrl.
4253 * Which register is written depends on the operation.
4254 * Most operate on the common register, while
4255 * SEND_ENB and SEND_DIS operate on the per-port ones.
4256 * SEND_ENB is included in common because it can change SPCL_TRIG
4258 #define SENDCTRL_COMMON_MODS (\
4259 QIB_SENDCTRL_CLEAR | \
4260 QIB_SENDCTRL_AVAIL_DIS | \
4261 QIB_SENDCTRL_AVAIL_ENB | \
4262 QIB_SENDCTRL_AVAIL_BLIP | \
4263 QIB_SENDCTRL_DISARM | \
4264 QIB_SENDCTRL_DISARM_ALL | \
4265 QIB_SENDCTRL_SEND_ENB)
4267 #define SENDCTRL_PORT_MODS (\
4268 QIB_SENDCTRL_CLEAR | \
4269 QIB_SENDCTRL_SEND_ENB | \
4270 QIB_SENDCTRL_SEND_DIS | \
4273 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4275 struct qib_devdata *dd = ppd->dd;
4276 u64 tmp_dd_sendctrl;
4277 unsigned long flags;
4279 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4281 /* First the dd ones that are "sticky", saved in shadow */
4282 if (op & QIB_SENDCTRL_CLEAR)
4284 if (op & QIB_SENDCTRL_AVAIL_DIS)
4285 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4286 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4287 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4288 if (dd->flags & QIB_USE_SPCL_TRIG)
4289 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4292 /* Then the ppd ones that are "sticky", saved in shadow */
4293 if (op & QIB_SENDCTRL_SEND_DIS)
4294 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4295 else if (op & QIB_SENDCTRL_SEND_ENB)
4296 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4298 if (op & QIB_SENDCTRL_DISARM_ALL) {
4301 tmp_dd_sendctrl = dd->sendctrl;
4302 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4304 * Disarm any buffers that are not yet launched,
4305 * disabling updates until done.
4307 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4308 for (i = 0; i < last; i++) {
4309 qib_write_kreg(dd, kr_sendctrl,
4311 SYM_MASK(SendCtrl, Disarm) | i);
4312 qib_write_kreg(dd, kr_scratch, 0);
4316 if (op & QIB_SENDCTRL_FLUSH) {
4317 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4320 * Now drain all the fifos. The Abort bit should never be
4321 * needed, so for now, at least, we don't use it.
4324 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4325 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4326 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4327 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4328 qib_write_kreg(dd, kr_scratch, 0);
4331 tmp_dd_sendctrl = dd->sendctrl;
4333 if (op & QIB_SENDCTRL_DISARM)
4334 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4335 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4336 SYM_LSB(SendCtrl, DisarmSendBuf));
4337 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4338 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4339 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4341 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4342 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4343 qib_write_kreg(dd, kr_scratch, 0);
4346 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4347 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4348 qib_write_kreg(dd, kr_scratch, 0);
4351 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4352 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4353 qib_write_kreg(dd, kr_scratch, 0);
4356 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4358 if (op & QIB_SENDCTRL_FLUSH) {
4361 * ensure writes have hit chip, then do a few
4362 * more reads, to allow DMA of pioavail registers
4363 * to occur, so in-memory copy is in sync with
4364 * the chip. Not always safe to sleep.
4366 v = qib_read_kreg32(dd, kr_scratch);
4367 qib_write_kreg(dd, kr_scratch, v);
4368 v = qib_read_kreg32(dd, kr_scratch);
4369 qib_write_kreg(dd, kr_scratch, v);
4370 qib_read_kreg32(dd, kr_scratch);
4374 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4375 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4376 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4379 * qib_portcntr_7322 - read a per-port chip counter
4380 * @ppd: the qlogic_ib pport
4381 * @creg: the counter to read (not a chip offset)
4383 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4385 struct qib_devdata *dd = ppd->dd;
4388 /* 0xffff for unimplemented or synthesized counters */
4389 static const u32 xlator[] = {
4390 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4391 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4392 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4393 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4394 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4395 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4396 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4397 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4398 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4399 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4400 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4401 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4402 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4403 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4404 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4405 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4406 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4407 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4408 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4409 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4410 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4411 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4412 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4413 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4414 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4415 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4416 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4417 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4418 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4419 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4421 * the next 3 aren't really counters, but were implemented
4422 * as counters in older chips, so still get accessed as
4423 * though they were counters from this code.
4425 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4426 [QIBPORTCNTR_PSSTART] = krp_psstart,
4427 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4428 /* pseudo-counter, summed for all ports */
4429 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4432 if (reg >= ARRAY_SIZE(xlator)) {
4433 qib_devinfo(ppd->dd->pcidev,
4434 "Unimplemented portcounter %u\n", reg);
4437 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4439 /* handle non-counters and special cases first */
4440 if (reg == QIBPORTCNTR_KHDROVFL) {
4443 /* sum over all kernel contexts (skip if mini_init) */
4444 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4445 struct qib_ctxtdata *rcd = dd->rcd[i];
4447 if (!rcd || rcd->ppd != ppd)
4449 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4452 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4454 * Used as part of the synthesis of port_rcv_errors
4455 * in the verbs code for IBTA counters. Not needed for 7322,
4456 * because all the errors are already counted by other cntrs.
4459 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4460 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4461 /* were counters in older chips, now per-port kernel regs */
4462 ret = qib_read_kreg_port(ppd, creg);
4467 * Only fast increment counters are 64 bits; use 32 bit reads to
4468 * avoid two independent reads when on Opteron.
4470 if (xlator[reg] & _PORT_64BIT_FLAG)
4471 ret = read_7322_creg_port(ppd, creg);
4473 ret = read_7322_creg32_port(ppd, creg);
4474 if (creg == crp_ibsymbolerr) {
4475 if (ppd->cpspec->ibdeltainprog)
4476 ret -= ret - ppd->cpspec->ibsymsnap;
4477 ret -= ppd->cpspec->ibsymdelta;
4478 } else if (creg == crp_iblinkerrrecov) {
4479 if (ppd->cpspec->ibdeltainprog)
4480 ret -= ret - ppd->cpspec->iblnkerrsnap;
4481 ret -= ppd->cpspec->iblnkerrdelta;
4482 } else if (creg == crp_errlink)
4483 ret -= ppd->cpspec->ibmalfdelta;
4484 else if (creg == crp_iblinkdown)
4485 ret += ppd->cpspec->iblnkdowndelta;
4491 * Device counter names (not port-specific), one line per stat,
4492 * single string. Used by utilities like ipathstats to print the stats
4493 * in a way which works for different versions of drivers, without changing
4494 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4495 * display by utility.
4496 * Non-error counters are first.
4497 * Start of "error" conters is indicated by a leading "E " on the first
4498 * "error" counter, and doesn't count in label length.
4499 * The EgrOvfl list needs to be last so we truncate them at the configured
4500 * context count for the device.
4501 * cntr7322indices contains the corresponding register indices.
4503 static const char cntr7322names[] =
4508 "RxTIDFloDrop\n" /* 7322 only */
4529 static const u32 cntr7322indices[] = {
4530 cr_lbint | _PORT_64BIT_FLAG,
4531 cr_lbstall | _PORT_64BIT_FLAG,
4535 cr_base_egrovfl + 0,
4536 cr_base_egrovfl + 1,
4537 cr_base_egrovfl + 2,
4538 cr_base_egrovfl + 3,
4539 cr_base_egrovfl + 4,
4540 cr_base_egrovfl + 5,
4541 cr_base_egrovfl + 6,
4542 cr_base_egrovfl + 7,
4543 cr_base_egrovfl + 8,
4544 cr_base_egrovfl + 9,
4545 cr_base_egrovfl + 10,
4546 cr_base_egrovfl + 11,
4547 cr_base_egrovfl + 12,
4548 cr_base_egrovfl + 13,
4549 cr_base_egrovfl + 14,
4550 cr_base_egrovfl + 15,
4551 cr_base_egrovfl + 16,
4552 cr_base_egrovfl + 17,
4556 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4557 * portcntr7322indices is somewhat complicated by some registers needing
4558 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4560 static const char portcntr7322names[] =
4568 "TxDmaDesc\n" /* 7220 and 7322-only */
4569 "E RxDlidFltr\n" /* 7220 and 7322-only */
4592 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4596 "RxQPBadCtxt\n" /* 7322-only from here down */
4600 static const u32 portcntr7322indices[] = {
4601 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4603 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4604 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4606 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4607 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4608 crp_txsdmadesc | _PORT_64BIT_FLAG,
4611 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4612 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4613 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4614 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4615 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4616 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4617 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4618 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4619 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4620 crp_rcvflowctrlviol,
4621 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4622 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4623 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4624 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4625 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4626 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4632 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4633 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4634 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4635 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4636 crp_rxqpinvalidctxt,
4640 /* do all the setup to make the counter reads efficient later */
4641 static void init_7322_cntrnames(struct qib_devdata *dd)
4646 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4648 /* we always have at least one counter before the egrovfl */
4649 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4651 s = strchr(s + 1, '\n');
4655 dd->cspec->ncntrs = i;
4657 /* full list; size is without terminating null */
4658 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4660 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4661 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4662 * sizeof(u64), GFP_KERNEL);
4663 if (!dd->cspec->cntrs)
4664 qib_dev_err(dd, "Failed allocation for counters\n");
4666 for (i = 0, s = (char *)portcntr7322names; s; i++)
4667 s = strchr(s + 1, '\n');
4668 dd->cspec->nportcntrs = i - 1;
4669 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4670 for (i = 0; i < dd->num_pports; ++i) {
4671 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4672 * sizeof(u64), GFP_KERNEL);
4673 if (!dd->pport[i].cpspec->portcntrs)
4674 qib_dev_err(dd, "Failed allocation for"
4679 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4685 ret = dd->cspec->cntrnamelen;
4687 ret = 0; /* final read after getting everything */
4689 *namep = (char *) cntr7322names;
4691 u64 *cntr = dd->cspec->cntrs;
4694 ret = dd->cspec->ncntrs * sizeof(u64);
4695 if (!cntr || pos >= ret) {
4696 /* everything read, or couldn't get memory */
4701 for (i = 0; i < dd->cspec->ncntrs; i++)
4702 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4703 *cntr++ = read_7322_creg(dd,
4704 cntr7322indices[i] &
4705 _PORT_CNTR_IDXMASK);
4707 *cntr++ = read_7322_creg32(dd,
4708 cntr7322indices[i]);
4714 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4715 char **namep, u64 **cntrp)
4720 ret = dd->cspec->portcntrnamelen;
4722 ret = 0; /* final read after getting everything */
4724 *namep = (char *)portcntr7322names;
4726 struct qib_pportdata *ppd = &dd->pport[port];
4727 u64 *cntr = ppd->cpspec->portcntrs;
4730 ret = dd->cspec->nportcntrs * sizeof(u64);
4731 if (!cntr || pos >= ret) {
4732 /* everything read, or couldn't get memory */
4737 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4738 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4739 *cntr++ = qib_portcntr_7322(ppd,
4740 portcntr7322indices[i] &
4741 _PORT_CNTR_IDXMASK);
4742 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4743 *cntr++ = read_7322_creg_port(ppd,
4744 portcntr7322indices[i] &
4745 _PORT_CNTR_IDXMASK);
4747 *cntr++ = read_7322_creg32_port(ppd,
4748 portcntr7322indices[i]);
4756 * qib_get_7322_faststats - get word counters from chip before they overflow
4757 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4759 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4760 * real purpose of this function is to maintain the notion of
4761 * "active time", which in turn is only logged into the eeprom,
4762 * which we don;t have, yet, for 7322-based boards.
4764 * called from add_timer
4766 static void qib_get_7322_faststats(unsigned long opaque)
4768 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4769 struct qib_pportdata *ppd;
4770 unsigned long flags;
4774 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4775 ppd = dd->pport + pidx;
4778 * If port isn't enabled or not operational ports, or
4779 * diags is running (can cause memory diags to fail)
4780 * skip this port this time.
4782 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4787 * Maintain an activity timer, based on traffic
4788 * exceeding a threshold, so we need to check the word-counts
4789 * even if they are 64-bit.
4791 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4792 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4793 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4794 traffic_wds -= ppd->dd->traffic_wds;
4795 ppd->dd->traffic_wds += traffic_wds;
4796 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4797 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4799 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4800 QIBL_LINKACTIVE)) &&
4801 ppd->cpspec->qdr_dfe_time &&
4802 time_after64(get_jiffies_64(), ppd->cpspec->qdr_dfe_time)) {
4803 ppd->cpspec->qdr_dfe_on = 0;
4805 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4806 ppd->dd->cspec->r1 ?
4807 QDR_STATIC_ADAPT_INIT_R1 :
4808 QDR_STATIC_ADAPT_INIT);
4812 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4816 * If we were using MSIx, try to fallback to INTx.
4818 static int qib_7322_intr_fallback(struct qib_devdata *dd)
4820 if (!dd->cspec->num_msix_entries)
4821 return 0; /* already using INTx */
4823 qib_devinfo(dd->pcidev, "MSIx interrupt not detected,"
4824 " trying INTx interrupts\n");
4825 qib_7322_nomsix(dd);
4826 qib_enable_intx(dd->pcidev);
4827 qib_setup_7322_interrupt(dd, 0);
4832 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4833 * than resetting the IBC or external link state, and useful in some
4834 * cases to cause some retraining. To do this right, we reset IBC
4835 * as well, then return to previous state (which may be still in reset)
4836 * NOTE: some callers of this "know" this writes the current value
4837 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4838 * check all callers.
4840 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4843 struct qib_devdata *dd = ppd->dd;
4844 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4845 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4846 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4848 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4849 qib_write_kreg(dd, kr_hwerrmask,
4850 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4851 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4852 ppd->cpspec->ibcctrl_a &
4853 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4855 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4856 qib_read_kreg32(dd, kr_scratch);
4857 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4858 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4859 qib_write_kreg(dd, kr_scratch, 0ULL);
4860 qib_write_kreg(dd, kr_hwerrclear,
4861 SYM_MASK(HwErrClear, statusValidNoEopClear));
4862 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4866 * This code for non-IBTA-compliant IB speed negotiation is only known to
4867 * work for the SDR to DDR transition, and only between an HCA and a switch
4868 * with recent firmware. It is based on observed heuristics, rather than
4869 * actual knowledge of the non-compliant speed negotiation.
4870 * It has a number of hard-coded fields, since the hope is to rewrite this
4871 * when a spec is available on how the negoation is intended to work.
4873 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4874 u32 dcnt, u32 *data)
4878 u32 __iomem *piobuf;
4879 u32 pnum, control, len;
4880 struct qib_devdata *dd = ppd->dd;
4883 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
4884 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4885 pbc = ((u64) control << 32) | len;
4886 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4891 /* disable header check on this packet, since it can't be valid */
4892 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4893 writeq(pbc, piobuf);
4895 qib_pio_copy(piobuf + 2, hdr, 7);
4896 qib_pio_copy(piobuf + 9, data, dcnt);
4897 if (dd->flags & QIB_USE_SPCL_TRIG) {
4898 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4901 __raw_writel(0xaebecede, piobuf + spcl_off);
4904 qib_sendbuf_done(dd, pnum);
4905 /* and re-enable hdr check */
4906 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
4910 * _start packet gets sent twice at start, _done gets sent twice at end
4912 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
4914 struct qib_devdata *dd = ppd->dd;
4916 u32 dw, i, hcnt, dcnt, *data;
4917 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4918 static u32 madpayload_start[0x40] = {
4919 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4920 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4921 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
4923 static u32 madpayload_done[0x40] = {
4924 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4925 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4926 0x40000001, 0x1388, 0x15e, /* rest 0's */
4929 dcnt = ARRAY_SIZE(madpayload_start);
4930 hcnt = ARRAY_SIZE(hdr);
4932 /* for maintainability, do it at runtime */
4933 for (i = 0; i < hcnt; i++) {
4934 dw = (__force u32) cpu_to_be32(hdr[i]);
4937 for (i = 0; i < dcnt; i++) {
4938 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
4939 madpayload_start[i] = dw;
4940 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
4941 madpayload_done[i] = dw;
4946 data = which ? madpayload_done : madpayload_start;
4948 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4949 qib_read_kreg64(dd, kr_scratch);
4951 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4952 qib_read_kreg64(dd, kr_scratch);
4957 * Do the absolute minimum to cause an IB speed change, and make it
4958 * ready, but don't actually trigger the change. The caller will
4959 * do that when ready (if link is in Polling training state, it will
4960 * happen immediately, otherwise when link next goes down)
4962 * This routine should only be used as part of the DDR autonegotation
4963 * code for devices that are not compliant with IB 1.2 (or code that
4964 * fixes things up for same).
4966 * When link has gone down, and autoneg enabled, or autoneg has
4967 * failed and we give up until next time we set both speeds, and
4968 * then we want IBTA enabled as well as "use max enabled speed.
4970 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
4973 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
4974 IBA7322_IBC_IBTA_1_2_MASK |
4975 IBA7322_IBC_MAX_SPEED_MASK);
4977 if (speed & (speed - 1)) /* multiple speeds */
4978 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
4979 IBA7322_IBC_IBTA_1_2_MASK |
4980 IBA7322_IBC_MAX_SPEED_MASK;
4982 newctrlb |= speed == QIB_IB_QDR ?
4983 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
4984 ((speed == QIB_IB_DDR ?
4985 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
4987 if (newctrlb == ppd->cpspec->ibcctrl_b)
4990 ppd->cpspec->ibcctrl_b = newctrlb;
4991 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4992 qib_write_kreg(ppd->dd, kr_scratch, 0);
4996 * This routine is only used when we are not talking to another
4997 * IB 1.2-compliant device that we think can do DDR.
4998 * (This includes all existing switch chips as of Oct 2007.)
4999 * 1.2-compliant devices go directly to DDR prior to reaching INIT
5001 static void try_7322_autoneg(struct qib_pportdata *ppd)
5003 unsigned long flags;
5005 spin_lock_irqsave(&ppd->lflags_lock, flags);
5006 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
5007 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5008 qib_autoneg_7322_send(ppd, 0);
5009 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5010 qib_7322_mini_pcs_reset(ppd);
5011 /* 2 msec is minimum length of a poll cycle */
5012 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
5013 msecs_to_jiffies(2));
5017 * Handle the empirically determined mechanism for auto-negotiation
5018 * of DDR speed with switches.
5020 static void autoneg_7322_work(struct work_struct *work)
5022 struct qib_pportdata *ppd;
5023 struct qib_devdata *dd;
5026 unsigned long flags;
5028 ppd = container_of(work, struct qib_chippport_specific,
5029 autoneg_work.work)->ppd;
5032 startms = jiffies_to_msecs(jiffies);
5035 * Busy wait for this first part, it should be at most a
5036 * few hundred usec, since we scheduled ourselves for 2msec.
5038 for (i = 0; i < 25; i++) {
5039 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5040 == IB_7322_LT_STATE_POLLQUIET) {
5041 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5047 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5048 goto done; /* we got there early or told to stop */
5050 /* we expect this to timeout */
5051 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5052 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5053 msecs_to_jiffies(90)))
5055 qib_7322_mini_pcs_reset(ppd);
5057 /* we expect this to timeout */
5058 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5059 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5060 msecs_to_jiffies(1700)))
5062 qib_7322_mini_pcs_reset(ppd);
5064 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5067 * Wait up to 250 msec for link to train and get to INIT at DDR;
5068 * this should terminate early.
5070 wait_event_timeout(ppd->cpspec->autoneg_wait,
5071 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5072 msecs_to_jiffies(250));
5074 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5075 spin_lock_irqsave(&ppd->lflags_lock, flags);
5076 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5077 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5078 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5079 ppd->cpspec->autoneg_tries = 0;
5081 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5082 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5087 * This routine is used to request IPG set in the QLogic switch.
5088 * Only called if r1.
5090 static void try_7322_ipg(struct qib_pportdata *ppd)
5092 struct qib_ibport *ibp = &ppd->ibport_data;
5093 struct ib_mad_send_buf *send_buf;
5094 struct ib_mad_agent *agent;
5099 agent = ibp->send_agent;
5103 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5104 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5105 if (IS_ERR(send_buf))
5109 struct ib_ah_attr attr;
5112 memset(&attr, 0, sizeof attr);
5113 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE);
5114 attr.port_num = ppd->port;
5115 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr);
5120 ibp->smi_ah = to_iah(ah);
5124 send_buf->ah = &ibp->smi_ah->ibah;
5128 smp = send_buf->mad;
5129 smp->base_version = IB_MGMT_BASE_VERSION;
5130 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5131 smp->class_version = 1;
5132 smp->method = IB_MGMT_METHOD_SEND;
5134 smp->attr_id = QIB_VENDOR_IPG;
5138 ret = ib_post_send_mad(send_buf, NULL);
5140 ib_free_send_mad(send_buf);
5142 delay = 2 << ppd->cpspec->ipg_tries;
5143 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5144 msecs_to_jiffies(delay));
5148 * Timeout handler for setting IPG.
5149 * Only called if r1.
5151 static void ipg_7322_work(struct work_struct *work)
5153 struct qib_pportdata *ppd;
5155 ppd = container_of(work, struct qib_chippport_specific,
5156 ipg_work.work)->ppd;
5157 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5158 && ++ppd->cpspec->ipg_tries <= 10)
5162 static u32 qib_7322_iblink_state(u64 ibcs)
5164 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5167 case IB_7322_L_STATE_INIT:
5168 state = IB_PORT_INIT;
5170 case IB_7322_L_STATE_ARM:
5171 state = IB_PORT_ARMED;
5173 case IB_7322_L_STATE_ACTIVE:
5175 case IB_7322_L_STATE_ACT_DEFER:
5176 state = IB_PORT_ACTIVE;
5178 default: /* fall through */
5179 case IB_7322_L_STATE_DOWN:
5180 state = IB_PORT_DOWN;
5186 /* returns the IBTA port state, rather than the IBC link training state */
5187 static u8 qib_7322_phys_portstate(u64 ibcs)
5189 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5190 return qib_7322_physportstate[state];
5193 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5195 int ret = 0, symadj = 0;
5196 unsigned long flags;
5199 spin_lock_irqsave(&ppd->lflags_lock, flags);
5200 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5201 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5203 /* Update our picture of width and speed from chip */
5204 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5205 ppd->link_speed_active = QIB_IB_QDR;
5207 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5208 ppd->link_speed_active = QIB_IB_DDR;
5211 ppd->link_speed_active = QIB_IB_SDR;
5214 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5215 ppd->link_width_active = IB_WIDTH_4X;
5218 ppd->link_width_active = IB_WIDTH_1X;
5219 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5224 /* Link went down. */
5225 /* do IPG MAD again after linkdown, even if last time failed */
5226 ppd->cpspec->ipg_tries = 0;
5227 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5228 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5229 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5231 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5232 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5233 QIBL_IB_AUTONEG_INPROG)))
5234 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5235 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5236 struct qib_qsfp_data *qd =
5237 &ppd->cpspec->qsfp_data;
5238 /* unlock the Tx settings, speed may change */
5239 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5240 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5241 reset_tx_deemphasis_override));
5242 qib_cancel_sends(ppd);
5243 /* on link down, ensure sane pcs state */
5244 qib_7322_mini_pcs_reset(ppd);
5245 /* schedule the qsfp refresh which should turn the link
5247 if (ppd->dd->flags & QIB_HAS_QSFP) {
5248 qd->t_insert = get_jiffies_64();
5249 queue_work(ib_wq, &qd->work);
5251 spin_lock_irqsave(&ppd->sdma_lock, flags);
5252 if (__qib_sdma_running(ppd))
5253 __qib_sdma_process_event(ppd,
5254 qib_sdma_event_e70_go_idle);
5255 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5257 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5258 if (clr == ppd->cpspec->iblnkdownsnap)
5259 ppd->cpspec->iblnkdowndelta++;
5261 if (qib_compat_ddr_negotiate &&
5262 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5263 QIBL_IB_AUTONEG_INPROG)) &&
5264 ppd->link_speed_active == QIB_IB_SDR &&
5265 (ppd->link_speed_enabled & QIB_IB_DDR)
5266 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5267 /* we are SDR, and auto-negotiation enabled */
5268 ++ppd->cpspec->autoneg_tries;
5269 if (!ppd->cpspec->ibdeltainprog) {
5270 ppd->cpspec->ibdeltainprog = 1;
5271 ppd->cpspec->ibsymdelta +=
5272 read_7322_creg32_port(ppd,
5274 ppd->cpspec->ibsymsnap;
5275 ppd->cpspec->iblnkerrdelta +=
5276 read_7322_creg32_port(ppd,
5277 crp_iblinkerrrecov) -
5278 ppd->cpspec->iblnkerrsnap;
5280 try_7322_autoneg(ppd);
5281 ret = 1; /* no other IB status change processing */
5282 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5283 ppd->link_speed_active == QIB_IB_SDR) {
5284 qib_autoneg_7322_send(ppd, 1);
5285 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5286 qib_7322_mini_pcs_reset(ppd);
5288 ret = 1; /* no other IB status change processing */
5289 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5290 (ppd->link_speed_active & QIB_IB_DDR)) {
5291 spin_lock_irqsave(&ppd->lflags_lock, flags);
5292 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5293 QIBL_IB_AUTONEG_FAILED);
5294 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5295 ppd->cpspec->autoneg_tries = 0;
5296 /* re-enable SDR, for next link down */
5297 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5298 wake_up(&ppd->cpspec->autoneg_wait);
5300 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5302 * Clear autoneg failure flag, and do setup
5303 * so we'll try next time link goes down and
5304 * back to INIT (possibly connected to a
5305 * different device).
5307 spin_lock_irqsave(&ppd->lflags_lock, flags);
5308 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5309 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5310 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5313 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5315 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5317 if (!ppd->cpspec->recovery_init)
5318 setup_7322_link_recovery(ppd, 0);
5319 ppd->cpspec->qdr_dfe_time = jiffies +
5320 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5322 ppd->cpspec->ibmalfusesnap = 0;
5323 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5327 ppd->cpspec->iblnkdownsnap =
5328 read_7322_creg32_port(ppd, crp_iblinkdown);
5329 if (ppd->cpspec->ibdeltainprog) {
5330 ppd->cpspec->ibdeltainprog = 0;
5331 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5332 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5333 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5334 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5336 } else if (!ibup && qib_compat_ddr_negotiate &&
5337 !ppd->cpspec->ibdeltainprog &&
5338 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5339 ppd->cpspec->ibdeltainprog = 1;
5340 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5342 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5343 crp_iblinkerrrecov);
5347 qib_setup_7322_setextled(ppd, ibup);
5352 * Does read/modify/write to appropriate registers to
5353 * set output and direction bits selected by mask.
5354 * these are in their canonical postions (e.g. lsb of
5355 * dir will end up in D48 of extctrl on existing chips).
5356 * returns contents of GP Inputs.
5358 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5360 u64 read_val, new_out;
5361 unsigned long flags;
5364 /* some bits being written, lock access to GPIO */
5367 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5368 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5369 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5370 new_out = (dd->cspec->gpio_out & ~mask) | out;
5372 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5373 qib_write_kreg(dd, kr_gpio_out, new_out);
5374 dd->cspec->gpio_out = new_out;
5375 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5378 * It is unlikely that a read at this time would get valid
5379 * data on a pin whose direction line was set in the same
5380 * call to this function. We include the read here because
5381 * that allows us to potentially combine a change on one pin with
5382 * a read on another, and because the old code did something like
5385 read_val = qib_read_kreg64(dd, kr_extstatus);
5386 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5389 /* Enable writes to config EEPROM, if possible. Returns previous state */
5390 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5395 mask = 1 << QIB_EEPROM_WEN_NUM;
5396 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5397 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5399 return prev_wen & 1;
5403 * Read fundamental info we need to use the chip. These are
5404 * the registers that describe chip capabilities, and are
5405 * saved in shadow registers.
5407 static void get_7322_chip_params(struct qib_devdata *dd)
5413 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5415 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5417 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5418 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5419 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5420 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5421 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5423 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5424 dd->piobcnt2k = val & ~0U;
5425 dd->piobcnt4k = val >> 32;
5426 val = qib_read_kreg64(dd, kr_sendpiosize);
5427 dd->piosize2k = val & ~0U;
5428 dd->piosize4k = val >> 32;
5430 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5432 mtu = QIB_DEFAULT_MTU;
5433 dd->pport[0].ibmtu = (u32)mtu;
5434 dd->pport[1].ibmtu = (u32)mtu;
5436 /* these may be adjusted in init_chip_wc_pat() */
5437 dd->pio2kbase = (u32 __iomem *)
5438 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5439 dd->pio4kbase = (u32 __iomem *)
5440 ((char __iomem *) dd->kregbase +
5441 (dd->piobufbase >> 32));
5443 * 4K buffers take 2 pages; we use roundup just to be
5444 * paranoid; we calculate it once here, rather than on
5447 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5449 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5451 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5452 (sizeof(u64) * BITS_PER_BYTE / 2);
5456 * The chip base addresses in cspec and cpspec have to be set
5457 * after possible init_chip_wc_pat(), rather than in
5458 * get_7322_chip_params(), so split out as separate function
5460 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5463 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5465 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5466 (char __iomem *)dd->kregbase);
5468 dd->egrtidbase = (u64 __iomem *)
5469 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5471 /* port registers are defined as relative to base of chip */
5472 dd->pport[0].cpspec->kpregbase =
5473 (u64 __iomem *)((char __iomem *)dd->kregbase);
5474 dd->pport[1].cpspec->kpregbase =
5475 (u64 __iomem *)(dd->palign +
5476 (char __iomem *)dd->kregbase);
5477 dd->pport[0].cpspec->cpregbase =
5478 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5479 kr_counterregbase) + (char __iomem *)dd->kregbase);
5480 dd->pport[1].cpspec->cpregbase =
5481 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5482 kr_counterregbase) + (char __iomem *)dd->kregbase);
5486 * This is a fairly special-purpose observer, so we only support
5487 * the port-specific parts of SendCtrl
5490 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5491 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5492 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5493 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5494 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5495 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5496 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5498 static int sendctrl_hook(struct qib_devdata *dd,
5499 const struct diag_observer *op, u32 offs,
5500 u64 *data, u64 mask, int only_32)
5502 unsigned long flags;
5505 struct qib_pportdata *ppd = NULL;
5506 u64 local_data, all_bits;
5509 * The fixed correspondence between Physical ports and pports is
5510 * severed. We need to hunt for the ppd that corresponds
5511 * to the offset we got. And we have to do that without admitting
5512 * we know the stride, apparently.
5514 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5518 ppd = dd->pport + pidx;
5519 if (!ppd->cpspec->kpregbase)
5522 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5523 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5528 /* If pport is not being managed by driver, just avoid shadows. */
5529 if (pidx >= dd->num_pports)
5532 /* In any case, "idx" is flat index in kreg space */
5533 idx = offs / sizeof(u64);
5539 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5540 if (!ppd || (mask & all_bits) != all_bits) {
5542 * At least some mask bits are zero, so we need
5543 * to read. The judgement call is whether from
5544 * reg or shadow. First-cut: read reg, and complain
5545 * if any bits which should be shadowed are different
5546 * from their shadowed value.
5549 local_data = (u64)qib_read_kreg32(dd, idx);
5551 local_data = qib_read_kreg64(dd, idx);
5552 *data = (local_data & ~mask) | (*data & mask);
5556 * At least some mask bits are one, so we need
5557 * to write, but only shadow some bits.
5559 u64 sval, tval; /* Shadowed, transient */
5562 * New shadow val is bits we don't want to touch,
5563 * ORed with bits we do, that are intended for shadow.
5566 sval = ppd->p_sendctrl & ~mask;
5567 sval |= *data & SENDCTRL_SHADOWED & mask;
5568 ppd->p_sendctrl = sval;
5570 sval = *data & SENDCTRL_SHADOWED & mask;
5571 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5572 qib_write_kreg(dd, idx, tval);
5573 qib_write_kreg(dd, kr_scratch, 0Ull);
5575 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5576 return only_32 ? 4 : 8;
5579 static const struct diag_observer sendctrl_0_observer = {
5580 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5581 KREG_IDX(SendCtrl_0) * sizeof(u64)
5584 static const struct diag_observer sendctrl_1_observer = {
5585 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5586 KREG_IDX(SendCtrl_1) * sizeof(u64)
5589 static ushort sdma_fetch_prio = 8;
5590 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5591 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5593 /* Besides logging QSFP events, we set appropriate TxDDS values */
5594 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5596 static void qsfp_7322_event(struct work_struct *work)
5598 struct qib_qsfp_data *qd;
5599 struct qib_pportdata *ppd;
5601 unsigned long flags;
5605 qd = container_of(work, struct qib_qsfp_data, work);
5607 pwrup = qd->t_insert +
5608 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC);
5610 /* Delay for 20 msecs to allow ModPrs resistor to setup */
5611 mdelay(QSFP_MODPRS_LAG_MSEC);
5613 if (!qib_qsfp_mod_present(ppd)) {
5614 ppd->cpspec->qsfp_data.modpresent = 0;
5615 /* Set the physical link to disabled */
5616 qib_set_ib_7322_lstate(ppd, 0,
5617 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
5618 spin_lock_irqsave(&ppd->lflags_lock, flags);
5619 ppd->lflags &= ~QIBL_LINKV;
5620 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5623 * Some QSFP's not only do not respond until the full power-up
5624 * time, but may behave badly if we try. So hold off responding
5628 u64 now = get_jiffies_64();
5629 if (time_after64(now, pwrup))
5634 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5637 * Need to change LE2 back to defaults if we couldn't
5638 * read the cable type (to handle cable swaps), so do this
5639 * even on failure to read cable information. We don't
5640 * get here for QME, so IS_QME check not needed here.
5642 if (!ret && !ppd->dd->cspec->r1) {
5643 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech))
5645 else if (qd->cache.atten[1] >= qib_long_atten &&
5646 QSFP_IS_CU(qd->cache.tech))
5652 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5654 * We always change parameteters, since we can choose
5655 * values for cables without eeproms, and the cable may have
5656 * changed from a cable with full or partial eeprom content
5657 * to one with partial or no content.
5659 init_txdds_table(ppd, 0);
5660 /* The physical link is being re-enabled only when the
5661 * previous state was DISABLED and the VALID bit is not
5662 * set. This should only happen when the cable has been
5663 * physically pulled. */
5664 if (!ppd->cpspec->qsfp_data.modpresent &&
5665 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) {
5666 ppd->cpspec->qsfp_data.modpresent = 1;
5667 qib_set_ib_7322_lstate(ppd, 0,
5668 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
5669 spin_lock_irqsave(&ppd->lflags_lock, flags);
5670 ppd->lflags |= QIBL_LINKV;
5671 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5677 * There is little we can do but complain to the user if QSFP
5678 * initialization fails.
5680 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5682 unsigned long flags;
5683 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5684 struct qib_devdata *dd = ppd->dd;
5685 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5687 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5689 qib_qsfp_init(qd, qsfp_7322_event);
5690 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5691 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5692 dd->cspec->gpio_mask |= mod_prs_bit;
5693 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5694 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5695 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5699 * called at device initialization time, and also if the txselect
5700 * module parameter is changed. This is used for cables that don't
5701 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5702 * We initialize to the default, then if there is a specific
5703 * unit,port match, we use that (and set it immediately, for the
5704 * current speed, if the link is at INIT or better).
5705 * String format is "default# unit#,port#=# ... u,p=#", separators must
5706 * be a SPACE character. A newline terminates. The u,p=# tuples may
5707 * optionally have "u,p=#,#", where the final # is the H1 value
5708 * The last specific match is used (actually, all are used, but last
5709 * one is the one that winds up set); if none at all, fall back on default.
5711 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5714 u32 pidx, unit, port, deflt, h1;
5719 str = txselect_list;
5721 /* default number is validated in setup_txselect() */
5722 deflt = simple_strtoul(str, &nxt, 0);
5723 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5724 dd->pport[pidx].cpspec->no_eep = deflt;
5726 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
5727 if (IS_QME(dd) || IS_QMH(dd))
5728 txdds_size += TXDDS_MFG_SZ;
5730 while (*nxt && nxt[1]) {
5732 unit = simple_strtoul(str, &nxt, 0);
5733 if (nxt == str || !*nxt || *nxt != ',') {
5734 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5739 port = simple_strtoul(str, &nxt, 0);
5740 if (nxt == str || *nxt != '=') {
5741 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5746 val = simple_strtoul(str, &nxt, 0);
5748 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5752 if (val >= txdds_size)
5755 h1 = 0; /* gcc thinks it might be used uninitted */
5756 if (*nxt == ',' && nxt[1]) {
5758 h1 = (u32)simple_strtoul(str, &nxt, 0);
5760 while (*nxt && *nxt++ != ' ') /* skip */
5765 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5767 struct qib_pportdata *ppd = &dd->pport[pidx];
5769 if (ppd->port != port || !ppd->link_speed_supported)
5771 ppd->cpspec->no_eep = val;
5773 ppd->cpspec->h1_val = h1;
5774 /* now change the IBC and serdes, overriding generic */
5775 init_txdds_table(ppd, 1);
5776 /* Re-enable the physical state machine on mezz boards
5777 * now that the correct settings have been set.
5778 * QSFP boards are handles by the QSFP event handler */
5779 if (IS_QMH(dd) || IS_QME(dd))
5780 qib_set_ib_7322_lstate(ppd, 0,
5781 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
5787 if (change && !any) {
5788 /* no specific setting, use the default.
5789 * Change the IBC and serdes, but since it's
5790 * general, don't override specific settings.
5792 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5793 if (dd->pport[pidx].link_speed_supported)
5794 init_txdds_table(&dd->pport[pidx], 0);
5798 /* handle the txselect parameter changing */
5799 static int setup_txselect(const char *str, struct kernel_param *kp)
5801 struct qib_devdata *dd;
5804 if (strlen(str) >= MAX_ATTEN_LEN) {
5805 printk(KERN_INFO QIB_DRV_NAME " txselect_values string "
5809 val = simple_strtoul(str, &n, 0);
5810 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
5812 printk(KERN_INFO QIB_DRV_NAME
5813 "txselect_values must start with a number < %d\n",
5814 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
5817 strcpy(txselect_list, str);
5819 list_for_each_entry(dd, &qib_dev_list, list)
5820 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5821 set_no_qsfp_atten(dd, 1);
5826 * Write the final few registers that depend on some of the
5827 * init setup. Done late in init, just before bringing up
5830 static int qib_late_7322_initreg(struct qib_devdata *dd)
5835 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5836 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5837 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5838 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5839 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5840 if (val != dd->pioavailregs_phys) {
5841 qib_dev_err(dd, "Catastrophic software error, "
5842 "SendPIOAvailAddr written as %lx, "
5843 "read back as %llx\n",
5844 (unsigned long) dd->pioavailregs_phys,
5845 (unsigned long long) val);
5849 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5850 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5851 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5852 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5854 qib_register_observer(dd, &sendctrl_0_observer);
5855 qib_register_observer(dd, &sendctrl_1_observer);
5857 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5858 qib_write_kreg(dd, kr_control, dd->control);
5860 * Set SendDmaFetchPriority and init Tx params, including
5861 * QSFP handler on boards that have QSFP.
5862 * First set our default attenuation entry for cables that
5863 * don't have valid attenuation.
5865 set_no_qsfp_atten(dd, 0);
5866 for (n = 0; n < dd->num_pports; ++n) {
5867 struct qib_pportdata *ppd = dd->pport + n;
5869 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5870 sdma_fetch_prio & 0xf);
5871 /* Initialize qsfp if present on board. */
5872 if (dd->flags & QIB_HAS_QSFP)
5873 qib_init_7322_qsfp(ppd);
5875 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5876 qib_write_kreg(dd, kr_control, dd->control);
5881 /* per IB port errors. */
5882 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5884 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5885 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5886 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5890 * Write the initialization per-port registers that need to be done at
5891 * driver load and after reset completes (i.e., that aren't done as part
5892 * of other init procedures called from qib_init.c).
5893 * Some of these should be redundant on reset, but play safe.
5895 static void write_7322_init_portregs(struct qib_pportdata *ppd)
5900 if (!ppd->link_speed_supported) {
5901 /* no buffer credits for this port */
5902 for (i = 1; i < 8; i++)
5903 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5904 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5905 qib_write_kreg(ppd->dd, kr_scratch, 0);
5910 * Set the number of supported virtual lanes in IBC,
5911 * for flow control packet handling on unsupported VLs
5913 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5914 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5915 val |= (u64)(ppd->vls_supported - 1) <<
5916 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5917 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5919 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5921 /* enable tx header checking */
5922 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5923 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5924 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5926 qib_write_kreg_port(ppd, krp_ncmodectrl,
5927 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5930 * Unconditionally clear the bufmask bits. If SDMA is
5931 * enabled, we'll set them appropriately later.
5933 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5934 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5935 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5936 if (ppd->dd->cspec->r1)
5937 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5941 * Write the initialization per-device registers that need to be done at
5942 * driver load and after reset completes (i.e., that aren't done as part
5943 * of other init procedures called from qib_init.c). Also write per-port
5944 * registers that are affected by overall device config, such as QP mapping
5945 * Some of these should be redundant on reset, but play safe.
5947 static void write_7322_initregs(struct qib_devdata *dd)
5949 struct qib_pportdata *ppd;
5953 /* Set Multicast QPs received by port 2 to map to context one. */
5954 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
5956 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5958 unsigned long flags;
5960 if (dd->n_krcv_queues < 2 ||
5961 !dd->pport[pidx].link_speed_supported)
5964 ppd = &dd->pport[pidx];
5966 /* be paranoid against later code motion, etc. */
5967 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
5968 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
5969 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5971 /* Initialize QP to context mapping */
5972 regno = krp_rcvqpmaptable;
5974 if (dd->num_pports > 1)
5975 n = dd->first_user_ctxt / dd->num_pports;
5977 n = dd->first_user_ctxt - 1;
5978 for (i = 0; i < 32; ) {
5981 if (dd->num_pports > 1)
5982 ctxt = (i % n) * dd->num_pports + pidx;
5986 ctxt = ppd->hw_pidx;
5987 val |= ctxt << (5 * (i % 6));
5990 qib_write_kreg_port(ppd, regno, val);
5995 qib_write_kreg_port(ppd, regno, val);
5999 * Setup up interrupt mitigation for kernel contexts, but
6000 * not user contexts (user contexts use interrupts when
6001 * stalled waiting for any packet, so want those interrupts
6004 for (i = 0; i < dd->first_user_ctxt; i++) {
6005 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
6006 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
6010 * Initialize as (disabled) rcvflow tables. Application code
6011 * will setup each flow as it uses the flow.
6012 * Doesn't clear any of the error bits that might be set.
6014 val = TIDFLOW_ERRBITS; /* these are W1C */
6015 for (i = 0; i < dd->cfgctxts; i++) {
6017 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
6018 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
6022 * dual cards init to dual port recovery, single port cards to
6023 * the one port. Dual port cards may later adjust to 1 port,
6024 * and then back to dual port if both ports are connected
6027 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
6030 static int qib_init_7322_variables(struct qib_devdata *dd)
6032 struct qib_pportdata *ppd;
6033 unsigned features, pidx, sbufcnt;
6035 u32 sbufs, updthresh;
6037 /* pport structs are contiguous, allocated after devdata */
6038 ppd = (struct qib_pportdata *)(dd + 1);
6043 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
6045 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
6046 ppd[1].cpspec = &ppd[0].cpspec[1];
6047 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
6048 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
6050 spin_lock_init(&dd->cspec->rcvmod_lock);
6051 spin_lock_init(&dd->cspec->gpio_lock);
6053 /* we haven't yet set QIB_PRESENT, so use read directly */
6054 dd->revision = readq(&dd->kregbase[kr_revision]);
6056 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
6057 qib_dev_err(dd, "Revision register read failure, "
6058 "giving up initialization\n");
6062 dd->flags |= QIB_PRESENT; /* now register routines work */
6064 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
6065 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
6066 dd->cspec->r1 = dd->minrev == 1;
6068 get_7322_chip_params(dd);
6069 features = qib_7322_boardname(dd);
6071 /* now that piobcnt2k and 4k set, we can allocate these */
6072 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
6073 NUM_VL15_BUFS + BITS_PER_LONG - 1;
6074 sbufcnt /= BITS_PER_LONG;
6075 dd->cspec->sendchkenable = kmalloc(sbufcnt *
6076 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6077 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6078 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6079 dd->cspec->sendibchk = kmalloc(sbufcnt *
6080 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6081 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6082 !dd->cspec->sendibchk) {
6083 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6091 * GPIO bits for TWSI data and clock,
6092 * used for serial EEPROM.
6094 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6095 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6096 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6098 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6099 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6100 QIB_HAS_THRESH_UPDATE |
6101 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6102 dd->flags |= qib_special_trigger ?
6103 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6106 * Setup initial values. These may change when PAT is enabled, but
6107 * we need these to do initial chip register accesses.
6109 qib_7322_set_baseaddrs(dd);
6111 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6113 mtu = QIB_DEFAULT_MTU;
6115 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6116 /* all hwerrors become interrupts, unless special purposed */
6117 dd->cspec->hwerrmask = ~0ULL;
6118 /* link_recovery setup causes these errors, so ignore them,
6119 * other than clearing them when they occur */
6120 dd->cspec->hwerrmask &=
6121 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6122 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6123 HWE_MASK(LATriggered));
6125 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6126 struct qib_chippport_specific *cp = ppd->cpspec;
6127 ppd->link_speed_supported = features & PORT_SPD_CAP;
6128 features >>= PORT_SPD_CAP_SHIFT;
6129 if (!ppd->link_speed_supported) {
6130 /* single port mode (7340, or configured) */
6131 dd->skip_kctxt_mask |= 1 << pidx;
6133 /* Make sure port is disabled. */
6134 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6135 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6137 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6138 IBSerdesPClkNotDetectMask_0)
6139 | SYM_MASK(HwErrMask,
6140 SDmaMemReadErrMask_0));
6141 dd->cspec->int_enable_mask &= ~(
6142 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6143 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6144 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6145 SYM_MASK(IntMask, SDmaIntMask_0) |
6146 SYM_MASK(IntMask, ErrIntMask_0) |
6147 SYM_MASK(IntMask, SendDoneIntMask_0));
6149 /* Make sure port is disabled. */
6150 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6151 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6152 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6153 IBSerdesPClkNotDetectMask_1)
6154 | SYM_MASK(HwErrMask,
6155 SDmaMemReadErrMask_1));
6156 dd->cspec->int_enable_mask &= ~(
6157 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6158 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6159 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6160 SYM_MASK(IntMask, SDmaIntMask_1) |
6161 SYM_MASK(IntMask, ErrIntMask_1) |
6162 SYM_MASK(IntMask, SendDoneIntMask_1));
6168 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6170 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6171 ppd->link_width_enabled = IB_WIDTH_4X;
6172 ppd->link_speed_enabled = ppd->link_speed_supported;
6174 * Set the initial values to reasonable default, will be set
6175 * for real when link is up.
6177 ppd->link_width_active = IB_WIDTH_4X;
6178 ppd->link_speed_active = QIB_IB_SDR;
6179 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6180 switch (qib_num_cfg_vls) {
6182 ppd->vls_supported = IB_VL_VL0;
6185 ppd->vls_supported = IB_VL_VL0_1;
6188 qib_devinfo(dd->pcidev,
6189 "Invalid num_vls %u, using 4 VLs\n",
6191 qib_num_cfg_vls = 4;
6194 ppd->vls_supported = IB_VL_VL0_3;
6198 ppd->vls_supported = IB_VL_VL0_7;
6200 qib_devinfo(dd->pcidev,
6201 "Invalid num_vls %u for MTU %d "
6203 qib_num_cfg_vls, mtu);
6204 ppd->vls_supported = IB_VL_VL0_3;
6205 qib_num_cfg_vls = 4;
6209 ppd->vls_operational = ppd->vls_supported;
6211 init_waitqueue_head(&cp->autoneg_wait);
6212 INIT_DELAYED_WORK(&cp->autoneg_work,
6214 if (ppd->dd->cspec->r1)
6215 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6218 * For Mez and similar cards, no qsfp info, so do
6219 * the "cable info" setup here. Can be overridden
6220 * in adapter-specific routines.
6222 if (!(dd->flags & QIB_HAS_QSFP)) {
6223 if (!IS_QMH(dd) && !IS_QME(dd))
6224 qib_devinfo(dd->pcidev, "IB%u:%u: "
6225 "Unknown mezzanine card type\n",
6226 dd->unit, ppd->port);
6227 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6229 * Choose center value as default tx serdes setting
6230 * until changed through module parameter.
6232 ppd->cpspec->no_eep = IS_QMH(dd) ?
6233 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6235 cp->h1_val = H1_FORCE_VAL;
6237 /* Avoid writes to chip for mini_init */
6239 write_7322_init_portregs(ppd);
6241 init_timer(&cp->chase_timer);
6242 cp->chase_timer.function = reenable_chase;
6243 cp->chase_timer.data = (unsigned long)ppd;
6248 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6249 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6250 dd->rcvhdrsize = qib_rcvhdrsize ?
6251 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6252 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6254 /* we always allocate at least 2048 bytes for eager buffers */
6255 dd->rcvegrbufsize = max(mtu, 2048);
6256 BUG_ON(!is_power_of_2(dd->rcvegrbufsize));
6257 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize);
6259 qib_7322_tidtemplate(dd);
6262 * We can request a receive interrupt for 1 or
6263 * more packets from current offset.
6265 dd->rhdrhead_intr_off =
6266 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6268 /* setup the stats timer; the add_timer is done at end of init */
6269 init_timer(&dd->stats_timer);
6270 dd->stats_timer.function = qib_get_7322_faststats;
6271 dd->stats_timer.data = (unsigned long) dd;
6273 dd->ureg_align = 0x10000; /* 64KB alignment */
6275 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6277 qib_7322_config_ctxts(dd);
6278 qib_set_ctxtcnt(dd);
6281 resource_size_t vl15off;
6283 * We do not set WC on the VL15 buffers to avoid
6284 * a rare problem with unaligned writes from
6285 * interrupt-flushed store buffers, so we need
6286 * to map those separately here. We can't solve
6287 * this for the rarely used mtrr case.
6289 ret = init_chip_wc_pat(dd, 0);
6293 /* vl15 buffers start just after the 4k buffers */
6294 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6295 dd->piobcnt4k * dd->align4k;
6296 dd->piovl15base = ioremap_nocache(vl15off,
6297 NUM_VL15_BUFS * dd->align4k);
6298 if (!dd->piovl15base)
6301 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6306 if (!dd->num_pports) {
6307 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6308 goto bail; /* no error, so can still figure out why err */
6311 write_7322_initregs(dd);
6312 ret = qib_create_ctxts(dd);
6313 init_7322_cntrnames(dd);
6315 updthresh = 8U; /* update threshold */
6317 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6318 * reserve the update threshold amount for other kernel use, such
6319 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6320 * unless we aren't enabling SDMA, in which case we want to use
6321 * all the 4k bufs for the kernel.
6322 * if this was less than the update threshold, we could wait
6323 * a long time for an update. Coded this way because we
6324 * sometimes change the update threshold for various reasons,
6325 * and we want this to remain robust.
6327 if (dd->flags & QIB_HAS_SEND_DMA) {
6328 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6329 sbufs = updthresh > 3 ? updthresh : 3;
6331 dd->cspec->sdmabufcnt = 0;
6332 sbufs = dd->piobcnt4k;
6334 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6335 dd->cspec->sdmabufcnt;
6336 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6337 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6338 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6339 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6342 * If we have 16 user contexts, we will have 7 sbufs
6343 * per context, so reduce the update threshold to match. We
6344 * want to update before we actually run out, at low pbufs/ctxt
6345 * so give ourselves some margin.
6347 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6348 updthresh = dd->pbufsctxt - 2;
6349 dd->cspec->updthresh_dflt = updthresh;
6350 dd->cspec->updthresh = updthresh;
6352 /* before full enable, no interrupts, no locking needed */
6353 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6354 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6355 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6357 dd->psxmitwait_supported = 1;
6358 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6361 dd->ctxtcnt = 1; /* for other initialization code */
6366 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6369 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6370 struct qib_devdata *dd = ppd->dd;
6372 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6373 if (pbc & PBC_7322_VL15_SEND) {
6374 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6377 if ((plen + 1) > dd->piosize2kmax_dwords)
6378 first = dd->piobcnt2k;
6381 last = dd->cspec->lastbuf_for_pio;
6383 return qib_getsendbuf_range(dd, pbufnum, first, last);
6386 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6389 qib_write_kreg_port(ppd, krp_psinterval, intv);
6390 qib_write_kreg_port(ppd, krp_psstart, start);
6394 * Must be called with sdma_lock held, or before init finished.
6396 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6398 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6401 static struct sdma_set_state_action sdma_7322_action_table[] = {
6402 [qib_sdma_state_s00_hw_down] = {
6403 .go_s99_running_tofalse = 1,
6409 [qib_sdma_state_s10_hw_start_up_wait] = {
6415 [qib_sdma_state_s20_idle] = {
6421 [qib_sdma_state_s30_sw_clean_up_wait] = {
6427 [qib_sdma_state_s40_hw_clean_up_wait] = {
6433 [qib_sdma_state_s50_hw_halt_wait] = {
6439 [qib_sdma_state_s99_running] = {
6444 .go_s99_running_totrue = 1,
6448 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6450 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6453 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6455 struct qib_devdata *dd = ppd->dd;
6456 unsigned lastbuf, erstbuf;
6457 u64 senddmabufmask[3] = { 0 };
6460 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6461 qib_sdma_7322_setlengen(ppd);
6462 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6463 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6464 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6465 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6468 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6470 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6471 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6472 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6473 dd->cspec->sdmabufcnt);
6474 lastbuf = erstbuf + n;
6476 ppd->sdma_state.first_sendbuf = erstbuf;
6477 ppd->sdma_state.last_sendbuf = lastbuf;
6478 for (; erstbuf < lastbuf; ++erstbuf) {
6479 unsigned word = erstbuf / BITS_PER_LONG;
6480 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6483 senddmabufmask[word] |= 1ULL << bit;
6485 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6486 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6487 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6491 /* sdma_lock must be held */
6492 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6494 struct qib_devdata *dd = ppd->dd;
6502 use_dmahead = __qib_sdma_running(ppd) &&
6503 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6505 hwhead = use_dmahead ?
6506 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6507 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6509 swhead = ppd->sdma_descq_head;
6510 swtail = ppd->sdma_descq_tail;
6511 cnt = ppd->sdma_descq_cnt;
6513 if (swhead < swtail)
6515 sane = (hwhead >= swhead) & (hwhead <= swtail);
6516 else if (swhead > swtail)
6517 /* wrapped around */
6518 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6522 sane = (hwhead == swhead);
6524 if (unlikely(!sane)) {
6526 /* try one more time, directly from the register */
6530 /* proceed as if no progress */
6537 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6539 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6541 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6542 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6543 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6544 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6548 * Compute the amount of delay before sending the next packet if the
6549 * port's send rate differs from the static rate set for the QP.
6550 * The delay affects the next packet and the amount of the delay is
6551 * based on the length of the this packet.
6553 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6556 u8 snd_mult = ppd->delay_mult;
6557 u8 rcv_mult = ib_rate_to_delay[srate];
6560 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6562 /* Indicate VL15, else set the VL in the control word */
6564 ret |= PBC_7322_VL15_SEND_CTRL;
6566 ret |= vl << PBC_VL_NUM_LSB;
6567 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6573 * Enable the per-port VL15 send buffers for use.
6574 * They follow the rest of the buffers, without a config parameter.
6575 * This was in initregs, but that is done before the shadow
6576 * is set up, and this has to be done after the shadow is
6579 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6583 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6584 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6585 TXCHK_CHG_TYPE_KERN, NULL);
6588 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6590 if (rcd->ctxt < NUM_IB_PORTS) {
6591 if (rcd->dd->num_pports > 1) {
6592 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6593 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6595 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6596 rcd->rcvegr_tid_base = 0;
6599 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6600 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6601 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6605 #define QTXSLEEPS 5000
6606 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6607 u32 len, u32 which, struct qib_ctxtdata *rcd)
6610 const int last = start + len - 1;
6611 const int lastr = last / BITS_PER_LONG;
6613 int wait = rcd != NULL;
6614 unsigned long flags;
6617 unsigned long shadow;
6618 int cstart, previ = -1;
6621 * when flipping from kernel to user, we can't change
6622 * the checking type if the buffer is allocated to the
6623 * driver. It's OK the other direction, because it's
6624 * from close, and we have just disarm'ed all the
6625 * buffers. All the kernel to kernel changes are also
6628 for (cstart = start; cstart <= last; cstart++) {
6629 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6632 shadow = (unsigned long)
6633 le64_to_cpu(dd->pioavailregs_dma[i]);
6636 if (test_bit(((2 * cstart) +
6637 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6638 % BITS_PER_LONG, &shadow))
6645 if (sleeps == QTXSLEEPS)
6647 /* make sure we see an updated copy next time around */
6648 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6654 case TXCHK_CHG_TYPE_DIS1:
6656 * disable checking on a range; used by diags; just
6657 * one buffer, but still written generically
6659 for (i = start; i <= last; i++)
6660 clear_bit(i, dd->cspec->sendchkenable);
6663 case TXCHK_CHG_TYPE_ENAB1:
6665 * (re)enable checking on a range; used by diags; just
6666 * one buffer, but still written generically; read
6667 * scratch to be sure buffer actually triggered, not
6668 * just flushed from processor.
6670 qib_read_kreg32(dd, kr_scratch);
6671 for (i = start; i <= last; i++)
6672 set_bit(i, dd->cspec->sendchkenable);
6675 case TXCHK_CHG_TYPE_KERN:
6676 /* usable by kernel */
6677 for (i = start; i <= last; i++) {
6678 set_bit(i, dd->cspec->sendibchk);
6679 clear_bit(i, dd->cspec->sendgrhchk);
6681 spin_lock_irqsave(&dd->uctxt_lock, flags);
6682 /* see if we need to raise avail update threshold */
6683 for (i = dd->first_user_ctxt;
6684 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6685 && i < dd->cfgctxts; i++)
6686 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6687 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6688 < dd->cspec->updthresh_dflt)
6690 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6691 if (i == dd->cfgctxts) {
6692 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6693 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6694 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6695 dd->sendctrl |= (dd->cspec->updthresh &
6696 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6697 SYM_LSB(SendCtrl, AvailUpdThld);
6698 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6699 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6703 case TXCHK_CHG_TYPE_USER:
6704 /* for user process */
6705 for (i = start; i <= last; i++) {
6706 clear_bit(i, dd->cspec->sendibchk);
6707 set_bit(i, dd->cspec->sendgrhchk);
6709 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6710 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6711 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6712 dd->cspec->updthresh = (rcd->piocnt /
6713 rcd->subctxt_cnt) - 1;
6714 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6715 dd->sendctrl |= (dd->cspec->updthresh &
6716 SYM_RMASK(SendCtrl, AvailUpdThld))
6717 << SYM_LSB(SendCtrl, AvailUpdThld);
6718 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6719 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6721 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6728 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6729 qib_write_kreg(dd, kr_sendcheckmask + i,
6730 dd->cspec->sendchkenable[i]);
6732 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6733 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6734 dd->cspec->sendgrhchk[i]);
6735 qib_write_kreg(dd, kr_sendibpktmask + i,
6736 dd->cspec->sendibchk[i]);
6740 * Be sure whatever we did was seen by the chip and acted upon,
6741 * before we return. Mostly important for which >= 2.
6743 qib_read_kreg32(dd, kr_scratch);
6747 /* useful for trigger analyzers, etc. */
6748 static void writescratch(struct qib_devdata *dd, u32 val)
6750 qib_write_kreg(dd, kr_scratch, val);
6753 /* Dummy for now, use chip regs soon */
6754 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6760 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6761 * @dev: the pci_dev for qlogic_ib device
6762 * @ent: pci_device_id struct for this dev
6764 * Also allocates, inits, and returns the devdata struct for this
6767 * This is global, and is called directly at init to set up the
6768 * chip-specific function pointers for later use.
6770 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6771 const struct pci_device_id *ent)
6773 struct qib_devdata *dd;
6775 u32 tabsize, actual_cnt = 0;
6777 dd = qib_alloc_devdata(pdev,
6778 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6779 sizeof(struct qib_chip_specific) +
6780 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6784 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6785 dd->f_cleanup = qib_setup_7322_cleanup;
6786 dd->f_clear_tids = qib_7322_clear_tids;
6787 dd->f_free_irq = qib_7322_free_irq;
6788 dd->f_get_base_info = qib_7322_get_base_info;
6789 dd->f_get_msgheader = qib_7322_get_msgheader;
6790 dd->f_getsendbuf = qib_7322_getsendbuf;
6791 dd->f_gpio_mod = gpio_7322_mod;
6792 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6793 dd->f_hdrqempty = qib_7322_hdrqempty;
6794 dd->f_ib_updown = qib_7322_ib_updown;
6795 dd->f_init_ctxt = qib_7322_init_ctxt;
6796 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6797 dd->f_intr_fallback = qib_7322_intr_fallback;
6798 dd->f_late_initreg = qib_late_7322_initreg;
6799 dd->f_setpbc_control = qib_7322_setpbc_control;
6800 dd->f_portcntr = qib_portcntr_7322;
6801 dd->f_put_tid = qib_7322_put_tid;
6802 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6803 dd->f_rcvctrl = rcvctrl_7322_mod;
6804 dd->f_read_cntrs = qib_read_7322cntrs;
6805 dd->f_read_portcntrs = qib_read_7322portcntrs;
6806 dd->f_reset = qib_do_7322_reset;
6807 dd->f_init_sdma_regs = init_sdma_7322_regs;
6808 dd->f_sdma_busy = qib_sdma_7322_busy;
6809 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6810 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6811 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6812 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6813 dd->f_sendctrl = sendctrl_7322_mod;
6814 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6815 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6816 dd->f_iblink_state = qib_7322_iblink_state;
6817 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6818 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6819 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6820 dd->f_set_ib_loopback = qib_7322_set_loopback;
6821 dd->f_get_ib_table = qib_7322_get_ib_table;
6822 dd->f_set_ib_table = qib_7322_set_ib_table;
6823 dd->f_set_intr_state = qib_7322_set_intr_state;
6824 dd->f_setextled = qib_setup_7322_setextled;
6825 dd->f_txchk_change = qib_7322_txchk_change;
6826 dd->f_update_usrhead = qib_update_7322_usrhead;
6827 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6828 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6829 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6830 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6831 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6832 dd->f_writescratch = writescratch;
6833 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6835 * Do remaining PCIe setup and save PCIe values in dd.
6836 * Any error printing is already done by the init code.
6837 * On return, we have the chip mapped, but chip registers
6838 * are not set up until start of qib_init_7322_variables.
6840 ret = qib_pcie_ddinit(dd, pdev, ent);
6844 /* initialize chip-specific variables */
6845 ret = qib_init_7322_variables(dd);
6849 if (qib_mini_init || !dd->num_pports)
6853 * Determine number of vectors we want; depends on port count
6854 * and number of configured kernel receive queues actually used.
6855 * Should also depend on whether sdma is enabled or not, but
6856 * that's such a rare testing case it's not worth worrying about.
6858 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6859 for (i = 0; i < tabsize; i++)
6860 if ((i < ARRAY_SIZE(irq_table) &&
6861 irq_table[i].port <= dd->num_pports) ||
6862 (i >= ARRAY_SIZE(irq_table) &&
6863 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6865 /* reduce by ctxt's < 2 */
6866 if (qib_krcvq01_no_msi)
6867 actual_cnt -= dd->num_pports;
6869 tabsize = actual_cnt;
6870 dd->cspec->msix_entries = kmalloc(tabsize *
6871 sizeof(struct msix_entry), GFP_KERNEL);
6872 dd->cspec->msix_arg = kmalloc(tabsize *
6873 sizeof(void *), GFP_KERNEL);
6874 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) {
6875 qib_dev_err(dd, "No memory for MSIx table\n");
6878 for (i = 0; i < tabsize; i++)
6879 dd->cspec->msix_entries[i].entry = i;
6881 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6882 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
6883 "continuing anyway\n");
6884 /* may be less than we wanted, if not enough available */
6885 dd->cspec->num_msix_entries = tabsize;
6887 /* setup interrupt handler */
6888 qib_setup_7322_interrupt(dd, 1);
6890 /* clear diagctrl register, in case diags were running and crashed */
6891 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6896 qib_pcie_ddcleanup(dd);
6898 qib_free_devdata(dd);
6905 * Set the table entry at the specified index from the table specifed.
6906 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6907 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6908 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6909 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6911 #define DDS_ENT_AMP_LSB 14
6912 #define DDS_ENT_MAIN_LSB 9
6913 #define DDS_ENT_POST_LSB 5
6914 #define DDS_ENT_PRE_XTRA_LSB 3
6915 #define DDS_ENT_PRE_LSB 0
6918 * Set one entry in the TxDDS table for spec'd port
6919 * ridx picks one of the entries, while tp points
6920 * to the appropriate table entry.
6922 static void set_txdds(struct qib_pportdata *ppd, int ridx,
6923 const struct txdds_ent *tp)
6925 struct qib_devdata *dd = ppd->dd;
6929 /* Get correct offset in chip-space, and in source table */
6930 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6932 * We do not use qib_write_kreg_port() because it was intended
6933 * only for registers in the lower "port specific" pages.
6934 * So do index calculation by hand.
6937 regidx += (dd->palign / sizeof(u64));
6939 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6940 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6941 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6942 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6943 qib_write_kreg(dd, regidx, pack_ent);
6944 /* Prevent back-to-back writes by hitting scratch */
6945 qib_write_kreg(ppd->dd, kr_scratch, 0);
6948 static const struct vendor_txdds_ent vendor_txdds[] = {
6949 { /* Amphenol 1m 30awg NoEq */
6950 { 0x41, 0x50, 0x48 }, "584470002 ",
6951 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6953 { /* Amphenol 3m 28awg NoEq */
6954 { 0x41, 0x50, 0x48 }, "584470004 ",
6955 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
6957 { /* Finisar 3m OM2 Optical */
6958 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
6959 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
6961 { /* Finisar 30m OM2 Optical */
6962 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
6963 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
6965 { /* Finisar Default OM2 Optical */
6966 { 0x00, 0x90, 0x65 }, NULL,
6967 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
6969 { /* Gore 1m 30awg NoEq */
6970 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
6971 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
6973 { /* Gore 2m 30awg NoEq */
6974 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
6975 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
6977 { /* Gore 1m 28awg NoEq */
6978 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
6979 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
6981 { /* Gore 3m 28awg NoEq */
6982 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
6983 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
6985 { /* Gore 5m 24awg Eq */
6986 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
6987 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
6989 { /* Gore 7m 24awg Eq */
6990 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
6991 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
6993 { /* Gore 5m 26awg Eq */
6994 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
6995 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
6997 { /* Gore 7m 26awg Eq */
6998 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
6999 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
7001 { /* Intersil 12m 24awg Active */
7002 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
7003 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
7005 { /* Intersil 10m 28awg Active */
7006 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
7007 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
7009 { /* Intersil 7m 30awg Active */
7010 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
7011 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
7013 { /* Intersil 5m 32awg Active */
7014 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
7015 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
7017 { /* Intersil Default Active */
7018 { 0x00, 0x30, 0xB4 }, NULL,
7019 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
7021 { /* Luxtera 20m Active Optical */
7022 { 0x00, 0x25, 0x63 }, NULL,
7023 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
7025 { /* Molex 1M Cu loopback */
7026 { 0x00, 0x09, 0x3A }, "74763-0025 ",
7027 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
7029 { /* Molex 2m 28awg NoEq */
7030 { 0x00, 0x09, 0x3A }, "74757-2201 ",
7031 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
7035 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
7036 /* amp, pre, main, post */
7037 { 2, 2, 15, 6 }, /* Loopback */
7038 { 0, 0, 0, 1 }, /* 2 dB */
7039 { 0, 0, 0, 2 }, /* 3 dB */
7040 { 0, 0, 0, 3 }, /* 4 dB */
7041 { 0, 0, 0, 4 }, /* 5 dB */
7042 { 0, 0, 0, 5 }, /* 6 dB */
7043 { 0, 0, 0, 6 }, /* 7 dB */
7044 { 0, 0, 0, 7 }, /* 8 dB */
7045 { 0, 0, 0, 8 }, /* 9 dB */
7046 { 0, 0, 0, 9 }, /* 10 dB */
7047 { 0, 0, 0, 10 }, /* 11 dB */
7048 { 0, 0, 0, 11 }, /* 12 dB */
7049 { 0, 0, 0, 12 }, /* 13 dB */
7050 { 0, 0, 0, 13 }, /* 14 dB */
7051 { 0, 0, 0, 14 }, /* 15 dB */
7052 { 0, 0, 0, 15 }, /* 16 dB */
7055 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
7056 /* amp, pre, main, post */
7057 { 2, 2, 15, 6 }, /* Loopback */
7058 { 0, 0, 0, 8 }, /* 2 dB */
7059 { 0, 0, 0, 8 }, /* 3 dB */
7060 { 0, 0, 0, 9 }, /* 4 dB */
7061 { 0, 0, 0, 9 }, /* 5 dB */
7062 { 0, 0, 0, 10 }, /* 6 dB */
7063 { 0, 0, 0, 10 }, /* 7 dB */
7064 { 0, 0, 0, 11 }, /* 8 dB */
7065 { 0, 0, 0, 11 }, /* 9 dB */
7066 { 0, 0, 0, 12 }, /* 10 dB */
7067 { 0, 0, 0, 12 }, /* 11 dB */
7068 { 0, 0, 0, 13 }, /* 12 dB */
7069 { 0, 0, 0, 13 }, /* 13 dB */
7070 { 0, 0, 0, 14 }, /* 14 dB */
7071 { 0, 0, 0, 14 }, /* 15 dB */
7072 { 0, 0, 0, 15 }, /* 16 dB */
7075 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
7076 /* amp, pre, main, post */
7077 { 2, 2, 15, 6 }, /* Loopback */
7078 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
7079 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
7080 { 0, 1, 0, 11 }, /* 4 dB */
7081 { 0, 1, 0, 13 }, /* 5 dB */
7082 { 0, 1, 0, 15 }, /* 6 dB */
7083 { 0, 1, 3, 15 }, /* 7 dB */
7084 { 0, 1, 7, 15 }, /* 8 dB */
7085 { 0, 1, 7, 15 }, /* 9 dB */
7086 { 0, 1, 8, 15 }, /* 10 dB */
7087 { 0, 1, 9, 15 }, /* 11 dB */
7088 { 0, 1, 10, 15 }, /* 12 dB */
7089 { 0, 2, 6, 15 }, /* 13 dB */
7090 { 0, 2, 7, 15 }, /* 14 dB */
7091 { 0, 2, 8, 15 }, /* 15 dB */
7092 { 0, 2, 9, 15 }, /* 16 dB */
7096 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7097 * These are mostly used for mez cards going through connectors
7098 * and backplane traces, but can be used to add other "unusual"
7099 * table values as well.
7101 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7102 /* amp, pre, main, post */
7103 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7104 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7105 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7106 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7107 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7108 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7109 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7110 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7111 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7112 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7113 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7114 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7115 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7118 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7119 /* amp, pre, main, post */
7120 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7121 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7122 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7123 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7124 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7125 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7126 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7127 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7128 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7129 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7130 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7131 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7132 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7135 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7136 /* amp, pre, main, post */
7137 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7138 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7139 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7140 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7141 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7142 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7143 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7144 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7145 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7146 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7147 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7148 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7149 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7152 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7153 /* amp, pre, main, post */
7154 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7155 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7158 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7162 * The attenuation table starts at 2dB for entry 1,
7163 * with entry 0 being the loopback entry.
7167 else if (atten > TXDDS_TABLE_SZ)
7168 atten = TXDDS_TABLE_SZ - 1;
7171 return txdds + atten;
7175 * if override is set, the module parameter txselect has a value
7176 * for this specific port, so use it, rather than our normal mechanism.
7178 static void find_best_ent(struct qib_pportdata *ppd,
7179 const struct txdds_ent **sdr_dds,
7180 const struct txdds_ent **ddr_dds,
7181 const struct txdds_ent **qdr_dds, int override)
7183 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7186 /* Search table of known cables */
7187 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7188 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7190 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7192 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7200 /* Active cables don't have attenuation so we only set SERDES
7201 * settings to account for the attenuation of the board traces. */
7202 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7203 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7204 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7205 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7209 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7211 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7212 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7213 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7215 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7217 * If we have no (or incomplete) data from the cable
7218 * EEPROM, or no QSFP, or override is set, use the
7219 * module parameter value to index into the attentuation
7222 idx = ppd->cpspec->no_eep;
7223 *sdr_dds = &txdds_sdr[idx];
7224 *ddr_dds = &txdds_ddr[idx];
7225 *qdr_dds = &txdds_qdr[idx];
7226 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7227 /* similar to above, but index into the "extra" table. */
7228 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7229 *sdr_dds = &txdds_extra_sdr[idx];
7230 *ddr_dds = &txdds_extra_ddr[idx];
7231 *qdr_dds = &txdds_extra_qdr[idx];
7232 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7233 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7235 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7236 printk(KERN_INFO QIB_DRV_NAME
7237 " IB%u:%u use idx %u into txdds_mfg\n",
7238 ppd->dd->unit, ppd->port, idx);
7239 *sdr_dds = &txdds_extra_mfg[idx];
7240 *ddr_dds = &txdds_extra_mfg[idx];
7241 *qdr_dds = &txdds_extra_mfg[idx];
7243 /* this shouldn't happen, it's range checked */
7244 *sdr_dds = txdds_sdr + qib_long_atten;
7245 *ddr_dds = txdds_ddr + qib_long_atten;
7246 *qdr_dds = txdds_qdr + qib_long_atten;
7250 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7252 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7253 struct txdds_ent *dds;
7257 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7259 /* for mez cards or override, use the selected value for all entries */
7260 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7263 /* Fill in the first entry with the best entry found. */
7264 set_txdds(ppd, 0, sdr_dds);
7265 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7266 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7267 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7269 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7270 QIB_IB_QDR ? qdr_dds :
7271 (ppd->link_speed_active ==
7272 QIB_IB_DDR ? ddr_dds : sdr_dds));
7273 write_tx_serdes_param(ppd, dds);
7276 /* Fill in the remaining entries with the default table values. */
7277 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7278 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7279 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7280 single_ent ? ddr_dds : txdds_ddr + idx);
7281 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7282 single_ent ? qdr_dds : txdds_qdr + idx);
7286 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7287 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7288 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7289 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7290 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7291 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7292 #define AHB_TRANS_TRIES 10
7295 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7296 * 5=subsystem which is why most calls have "chan + chan >> 1"
7297 * for the channel argument.
7299 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7302 u32 rd_data, wr_data, sz_mask;
7303 u64 trans, acc, prev_acc;
7304 u32 ret = 0xBAD0BAD;
7307 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7308 /* From this point on, make sure we return access */
7309 acc = (quad << 1) | 1;
7310 qib_write_kreg(dd, KR_AHB_ACC, acc);
7312 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7313 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7314 if (trans & AHB_TRANS_RDY)
7317 if (tries >= AHB_TRANS_TRIES) {
7318 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7322 /* If mask is not all 1s, we need to read, but different SerDes
7323 * entities have different sizes
7325 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7326 wr_data = data & mask & sz_mask;
7327 if ((~mask & sz_mask) != 0) {
7328 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7329 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7331 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7332 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7333 if (trans & AHB_TRANS_RDY)
7336 if (tries >= AHB_TRANS_TRIES) {
7337 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7341 /* Re-read in case host split reads and read data first */
7342 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7343 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7344 wr_data |= (rd_data & ~mask & sz_mask);
7347 /* If mask is not zero, we need to write. */
7348 if (mask & sz_mask) {
7349 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7350 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7352 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7354 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7355 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7356 if (trans & AHB_TRANS_RDY)
7359 if (tries >= AHB_TRANS_TRIES) {
7360 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7367 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7371 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7374 struct qib_devdata *dd = ppd->dd;
7378 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7379 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7381 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7386 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7388 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7389 u8 state = SYM_FIELD(data, IBSerdesCtrl_0, RXLOSEN);
7391 if (enable && !state) {
7392 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS on\n",
7393 ppd->dd->unit, ppd->port);
7394 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7395 } else if (!enable && state) {
7396 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS off\n",
7397 ppd->dd->unit, ppd->port);
7398 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7400 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7403 static int serdes_7322_init(struct qib_pportdata *ppd)
7406 if (ppd->dd->cspec->r1)
7407 ret = serdes_7322_init_old(ppd);
7409 ret = serdes_7322_init_new(ppd);
7413 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7418 * Initialize the Tx DDS tables. Also done every QSFP event,
7419 * for adapters with QSFP
7421 init_txdds_table(ppd, 0);
7423 /* ensure no tx overrides from earlier driver loads */
7424 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7425 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7426 reset_tx_deemphasis_override));
7428 /* Patch some SerDes defaults to "Better for IB" */
7429 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7430 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7432 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7433 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7434 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7435 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7437 /* May be overridden in qsfp_7322_event */
7438 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7439 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7441 /* enable LE1 adaptation for all but QME, which is disabled */
7442 le_val = IS_QME(ppd->dd) ? 0 : 1;
7443 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7445 /* Clear cmode-override, may be set from older driver */
7446 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7448 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7449 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7451 /* setup LoS params; these are subsystem, so chan == 5 */
7452 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7453 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7454 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7455 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7456 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7458 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7459 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7460 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7461 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7462 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7464 /* LoS filter select enabled */
7465 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7467 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7468 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7469 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7470 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7472 serdes_7322_los_enable(ppd, 1);
7474 /* rxbistena; set 0 to avoid effects of it switch later */
7475 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7477 /* Configure 4 DFE taps, and only they adapt */
7478 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7480 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7481 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7482 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7485 * Set receive adaptation mode. SDR and DDR adaptation are
7486 * always on, and QDR is initially enabled; later disabled.
7488 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7489 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7490 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7491 ppd->dd->cspec->r1 ?
7492 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7493 ppd->cpspec->qdr_dfe_on = 1;
7495 /* FLoop LOS gate: PPM filter enabled */
7496 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7498 /* rx offset center enabled */
7499 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7501 if (!ppd->dd->cspec->r1) {
7502 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7503 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7506 /* Set the frequency loop bandwidth to 15 */
7507 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7512 static int serdes_7322_init_new(struct qib_pportdata *ppd)
7515 u32 le_val, rxcaldone;
7516 int chan, chan_done = (1 << SERDES_CHANS) - 1;
7518 /* Clear cmode-override, may be set from older driver */
7519 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7521 /* ensure no tx overrides from earlier driver loads */
7522 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7523 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7524 reset_tx_deemphasis_override));
7526 /* START OF LSI SUGGESTED SERDES BRINGUP */
7527 /* Reset - Calibration Setup */
7528 /* Stop DFE adaptaion */
7529 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
7531 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
7532 /* Disable autoadapt for LE1 */
7533 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
7535 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
7537 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7538 /* Disable AFE Offset Cancel */
7539 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
7540 /* Disable Timing Loop */
7541 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
7542 /* Disable Frequency Loop */
7543 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
7544 /* Disable Baseline Wander Correction */
7545 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
7546 /* Disable RX Calibration */
7547 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7548 /* Disable RX Offset Calibration */
7549 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
7551 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
7553 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
7554 /* Enable phase Calibration */
7555 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
7556 /* DFE Bandwidth [2:14-12] */
7557 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
7558 /* DFE Config (4 taps only) */
7559 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
7560 /* Gain Loop Bandwidth */
7561 if (!ppd->dd->cspec->r1) {
7562 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
7563 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
7565 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
7567 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
7568 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
7569 /* Data Rate Select [5:7-6] (leave as default) */
7570 /* RX Parallel Word Width [3:10-8] (leave as default) */
7573 /* Single- or Multi-channel reset */
7574 /* RX Analog reset */
7575 /* RX Digital reset */
7576 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
7578 /* RX Analog reset */
7579 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
7581 /* RX Digital reset */
7582 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
7585 /* setup LoS params; these are subsystem, so chan == 5 */
7586 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7587 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7588 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7589 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7590 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7592 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7593 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7594 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7595 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7596 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7598 /* LoS filter select enabled */
7599 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7601 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7602 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7603 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7604 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7606 /* Turn on LOS on initial SERDES init */
7607 serdes_7322_los_enable(ppd, 1);
7608 /* FLoop LOS gate: PPM filter enabled */
7609 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7611 /* RX LATCH CALIBRATION */
7612 /* Enable Eyefinder Phase Calibration latch */
7613 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
7614 /* Enable RX Offset Calibration latch */
7615 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
7617 /* Start Calibration */
7618 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
7619 tstart = get_jiffies_64();
7621 !time_after64(get_jiffies_64(),
7622 tstart + msecs_to_jiffies(500))) {
7624 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7625 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7626 (chan + (chan >> 1)),
7628 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
7629 (~chan_done & (1 << chan)) == 0)
7630 chan_done &= ~(1 << chan);
7634 printk(KERN_INFO QIB_DRV_NAME
7635 " Serdes %d calibration not done after .5 sec: 0x%x\n",
7636 IBSD(ppd->hw_pidx), chan_done);
7638 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7639 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7640 (chan + (chan >> 1)),
7642 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
7643 printk(KERN_INFO QIB_DRV_NAME
7644 " Serdes %d chan %d calibration "
7645 "failed\n", IBSD(ppd->hw_pidx), chan);
7649 /* Turn off Calibration */
7650 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7654 /* Set LE2 value (May be overridden in qsfp_7322_event) */
7655 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7656 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7657 /* Set LE2 Loop bandwidth */
7658 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
7660 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
7662 /* Enable H0 only */
7663 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
7664 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7665 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7666 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7668 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7670 /* Set Frequency Loop Bandwidth */
7671 ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5));
7672 /* Enable Frequency Loop */
7673 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
7674 /* Set Timing Loop Bandwidth */
7675 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7676 /* Enable Timing Loop */
7677 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
7680 * Set receive adaptation mode. SDR and DDR adaptation are
7681 * always on, and QDR is initially enabled; later disabled.
7683 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7684 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7685 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7686 ppd->dd->cspec->r1 ?
7687 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7688 ppd->cpspec->qdr_dfe_on = 1;
7690 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
7691 /* Disable auto adapt for LE1 */
7692 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
7694 /* Enable AFE Offset Cancel */
7695 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
7696 /* Enable Baseline Wander Correction */
7697 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
7698 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7699 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7700 /* VGA output common mode */
7701 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
7704 * Initialize the Tx DDS tables. Also done every QSFP event,
7705 * for adapters with QSFP
7707 init_txdds_table(ppd, 0);
7712 /* start adjust QMH serdes parameters */
7714 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7716 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7717 9, code << 9, 0x3f << 9);
7720 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7721 int enable, u32 tapenable)
7724 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7725 1, 3 << 10, 0x1f << 10);
7727 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7731 /* Set clock to 1, 0, 1, 0 */
7732 static void clock_man(struct qib_pportdata *ppd, int chan)
7734 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7736 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7738 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7740 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7745 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7746 * The caller must pass the settings appropriate for the current speed,
7747 * or not care if they are correct for the current speed.
7749 static void write_tx_serdes_param(struct qib_pportdata *ppd,
7750 struct txdds_ent *txdds)
7754 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7755 /* field names for amp, main, post, pre, respectively */
7756 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7757 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7758 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7759 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7761 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7762 tx_override_deemphasis_select);
7763 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7764 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7766 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7767 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7769 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7770 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7772 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7773 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7775 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7779 * Set the parameters for mez cards on link bounce, so they are
7780 * always exactly what was requested. Similar logic to init_txdds
7781 * but does just the serdes.
7783 static void adj_tx_serdes(struct qib_pportdata *ppd)
7785 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7786 struct txdds_ent *dds;
7788 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7789 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7790 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7791 ddr_dds : sdr_dds));
7792 write_tx_serdes_param(ppd, dds);
7795 /* set QDR forced value for H1, if needed */
7796 static void force_h1(struct qib_pportdata *ppd)
7800 ppd->cpspec->qdr_reforce = 0;
7801 if (!ppd->dd->cspec->r1)
7804 for (chan = 0; chan < SERDES_CHANS; chan++) {
7805 set_man_mode_h1(ppd, chan, 1, 0);
7806 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7807 clock_man(ppd, chan);
7808 set_man_mode_h1(ppd, chan, 0, 0);
7812 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7813 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7815 #define R_OPCODE_LSB 3
7817 #define R_OP_SHIFT 2
7818 #define R_OP_UPDATE 3
7823 static int qib_r_grab(struct qib_devdata *dd)
7827 qib_write_kreg(dd, kr_r_access, val);
7828 qib_read_kreg32(dd, kr_scratch);
7832 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
7833 * returns the current state of R_TDO
7835 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7839 for (timeout = 0; timeout < 100 ; ++timeout) {
7840 val = qib_read_kreg32(dd, kr_r_access);
7842 return (val >> R_TDO_LSB) & 1;
7847 static int qib_r_shift(struct qib_devdata *dd, int bisten,
7848 int len, u8 *inp, u8 *outp)
7853 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7854 (R_OP_SHIFT << R_OPCODE_LSB);
7855 ret = qib_r_wait_for_rdy(dd);
7858 for (pos = 0; pos < len; ++pos) {
7861 outp[pos >> 3] &= ~(1 << (pos & 7));
7862 outp[pos >> 3] |= (ret << (pos & 7));
7865 int tdi = inp[pos >> 3] >> (pos & 7);
7866 val |= ((tdi & 1) << R_TDI_LSB);
7868 qib_write_kreg(dd, kr_r_access, val);
7869 qib_read_kreg32(dd, kr_scratch);
7870 ret = qib_r_wait_for_rdy(dd);
7874 /* Restore to NOP between operations. */
7875 val = SJA_EN | (bisten << BISTEN_LSB);
7876 qib_write_kreg(dd, kr_r_access, val);
7877 qib_read_kreg32(dd, kr_scratch);
7878 ret = qib_r_wait_for_rdy(dd);
7886 static int qib_r_update(struct qib_devdata *dd, int bisten)
7891 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7892 ret = qib_r_wait_for_rdy(dd);
7894 qib_write_kreg(dd, kr_r_access, val);
7895 qib_read_kreg32(dd, kr_scratch);
7900 #define BISTEN_PORT_SEL 15
7901 #define LEN_PORT_SEL 625
7902 #define BISTEN_AT 17
7904 #define BISTEN_ETM 16
7907 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7909 /* these are common for all IB port use cases. */
7910 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7911 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7912 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7914 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7915 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7916 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7917 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7918 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7919 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7920 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7921 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7922 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7924 static u8 at[BIT2BYTE(LEN_AT)] = {
7925 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7926 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7929 /* used for IB1 or IB2, only one in use */
7930 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7931 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7932 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7933 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7934 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7935 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7936 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7937 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7938 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7941 /* used when both IB1 and IB2 are in use */
7942 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7943 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7944 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7945 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7946 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7947 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7948 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7949 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7950 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7953 /* used when only IB1 is in use */
7954 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
7955 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7956 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7957 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7958 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7959 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7960 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7961 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7962 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7965 /* used when only IB2 is in use */
7966 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
7967 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
7968 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
7969 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7970 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7971 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
7972 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7973 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7974 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
7977 /* used when both IB1 and IB2 are in use */
7978 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
7979 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7980 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7981 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7982 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7983 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7984 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
7985 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7986 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7990 * Do setup to properly handle IB link recovery; if port is zero, we
7991 * are initializing to cover both ports; otherwise we are initializing
7992 * to cover a single port card, or the port has reached INIT and we may
7993 * need to switch coverage types.
7995 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
7998 struct qib_devdata *dd = ppd->dd;
8000 if (!ppd->dd->cspec->r1)
8003 dd->cspec->recovery_ports_initted++;
8004 ppd->cpspec->recovery_init = 1;
8006 if (!both && dd->cspec->recovery_ports_initted == 1) {
8007 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
8010 portsel = portsel_2port;
8014 if (qib_r_grab(dd) < 0 ||
8015 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
8016 qib_r_update(dd, BISTEN_ETM) < 0 ||
8017 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
8018 qib_r_update(dd, BISTEN_AT) < 0 ||
8019 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
8020 portsel, NULL) < 0 ||
8021 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
8022 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
8023 qib_r_update(dd, BISTEN_AT) < 0 ||
8024 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
8025 qib_r_update(dd, BISTEN_ETM) < 0)
8026 qib_dev_err(dd, "Failed IB link recovery setup\n");
8029 static void check_7322_rxe_status(struct qib_pportdata *ppd)
8031 struct qib_devdata *dd = ppd->dd;
8034 if (dd->cspec->recovery_ports_initted != 1)
8035 return; /* rest doesn't apply to dualport */
8036 qib_write_kreg(dd, kr_control, dd->control |
8037 SYM_MASK(Control, FreezeMode));
8038 (void)qib_read_kreg64(dd, kr_scratch);
8039 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
8040 fmask = qib_read_kreg64(dd, kr_act_fmask);
8043 * require a powercycle before we'll work again, and make
8044 * sure we get no more interrupts, and don't turn off
8047 ppd->dd->cspec->stay_in_freeze = 1;
8048 qib_7322_set_intr_state(ppd->dd, 0);
8049 qib_write_kreg(dd, kr_fmask, 0ULL);
8050 qib_dev_err(dd, "HCA unusable until powercycled\n");
8051 return; /* eventually reset */
8054 qib_write_kreg(ppd->dd, kr_hwerrclear,
8055 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
8057 /* don't do the full clear_freeze(), not needed for this */
8058 qib_write_kreg(dd, kr_control, dd->control);
8059 qib_read_kreg32(dd, kr_scratch);
8060 /* take IBC out of reset */
8061 if (ppd->link_speed_supported) {
8062 ppd->cpspec->ibcctrl_a &=
8063 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
8064 qib_write_kreg_port(ppd, krp_ibcctrl_a,
8065 ppd->cpspec->ibcctrl_a);
8066 qib_read_kreg32(dd, kr_scratch);
8067 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
8068 qib_set_ib_7322_lstate(ppd, 0,
8069 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);